rtl-llm/vhdl_github · Datasets at Hugging Face

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-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc835.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c01s03b00x00p06n01i00835ent IS END c01s03b00x00p06n01i00835ent; ARCHITECTURE c01s03b00x00p06n01i00835arch OF c01s03b00x00p06n01i00835ent IS BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s03b00x00p06n01i00835 - Simple name at beginning and end of configuration should be the same." severity ERROR; wait; END PROCESS TESTING; END c01s03b00x00p06n01i00835arch; configuration C of c01s03b00x00p06n01i00835ent is for c01s03b00x00p06n01i00835arch use WORK.all ; end for ; end C2; -- Failure_here -- ERROR: name given at the end must be the same as that given beginning.
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc835.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c01s03b00x00p06n01i00835ent IS END c01s03b00x00p06n01i00835ent; ARCHITECTURE c01s03b00x00p06n01i00835arch OF c01s03b00x00p06n01i00835ent IS BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s03b00x00p06n01i00835 - Simple name at beginning and end of configuration should be the same." severity ERROR; wait; END PROCESS TESTING; END c01s03b00x00p06n01i00835arch; configuration C of c01s03b00x00p06n01i00835ent is for c01s03b00x00p06n01i00835arch use WORK.all ; end for ; end C2; -- Failure_here -- ERROR: name given at the end must be the same as that given beginning.
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc835.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c01s03b00x00p06n01i00835ent IS END c01s03b00x00p06n01i00835ent; ARCHITECTURE c01s03b00x00p06n01i00835arch OF c01s03b00x00p06n01i00835ent IS BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s03b00x00p06n01i00835 - Simple name at beginning and end of configuration should be the same." severity ERROR; wait; END PROCESS TESTING; END c01s03b00x00p06n01i00835arch; configuration C of c01s03b00x00p06n01i00835ent is for c01s03b00x00p06n01i00835arch use WORK.all ; end for ; end C2; -- Failure_here -- ERROR: name given at the end must be the same as that given beginning.
------------------------------------------------------------------------------ -- Title : Wishbone Orbit Interlock Core ------------------------------------------------------------------------------ -- Author : Lucas Maziero Russo -- Company : CNPEM LNLS-DIG -- Created : 2022-06-12 -- Platform : FPGA-generic ------------------------------------------------------------------------------- -- Description: Wishbone wrapper for orbit interlock ------------------------------------------------------------------------------- -- Copyright (c) 2020 CNPEM -- Licensed under GNU Lesser General Public License (LGPL) v3.0 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2020-06-02 1.0 lucas.russo Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -- Main Wishbone Definitions use work.wishbone_pkg.all; -- Orbit interlock cores use work.orbit_intlk_pkg.all; -- BPM cores use work.bpm_cores_pkg.all; entity xwb_orbit_intlk is generic ( -- Wishbone g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC; g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD; g_WITH_EXTRA_WB_REG : boolean := false; -- Position g_ADC_WIDTH : natural := 16; g_DECIM_WIDTH : natural := 32 ); port ( ----------------------------- -- Clocks and resets ----------------------------- rst_n_i : in std_logic; clk_i : in std_logic; -- Wishbone clock ref_rst_n_i : in std_logic; ref_clk_i : in std_logic; ----------------------------- -- Wishbone signals ----------------------------- wb_slv_i : in t_wishbone_slave_in; wb_slv_o : out t_wishbone_slave_out; ----------------------------- -- Downstream ADC and position signals ----------------------------- fs_clk_ds_i : in std_logic; adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0'); adc_ds_swap_valid_i : in std_logic := '0'; decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_ds_pos_valid_i : in std_logic; ----------------------------- -- Upstream ADC and position signals ----------------------------- fs_clk_us_i : in std_logic; adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0'); adc_us_swap_valid_i : in std_logic := '0'; decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_us_pos_valid_i : in std_logic; ----------------------------- -- Interlock outputs ----------------------------- intlk_trans_bigger_x_o : out std_logic; intlk_trans_bigger_y_o : out std_logic; -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; intlk_trans_bigger_any_o : out std_logic; -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_o : out std_logic; -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; intlk_trans_smaller_x_o : out std_logic; intlk_trans_smaller_y_o : out std_logic; -- only cleared when intlk_trans_clr_i is asserted intlk_trans_smaller_ltc_x_o : out std_logic; intlk_trans_smaller_ltc_y_o : out std_logic; intlk_trans_smaller_any_o : out std_logic; -- only cleared when intlk_trans_clr_i is asserted intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i intlk_trans_smaller_o : out std_logic; intlk_ang_bigger_x_o : out std_logic; intlk_ang_bigger_y_o : out std_logic; intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; intlk_ang_bigger_any_o : out std_logic; -- only cleared when intlk_ang_clr_i is asserted intlk_ang_bigger_ltc_o : out std_logic; -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; intlk_ang_smaller_x_o : out std_logic; intlk_ang_smaller_y_o : out std_logic; intlk_ang_smaller_ltc_x_o : out std_logic; intlk_ang_smaller_ltc_y_o : out std_logic; intlk_ang_smaller_any_o : out std_logic; -- only cleared when intlk_ang_clr_i is asserted intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i intlk_ang_smaller_o : out std_logic; -- only cleared when intlk_clr_i is asserted intlk_ltc_o : out std_logic; -- conditional to intlk_en_i intlk_o : out std_logic ); end xwb_orbit_intlk; architecture rtl of xwb_orbit_intlk is begin cmp_wb_orbit_intlk : wb_orbit_intlk generic map ( -- Wishbone g_INTERFACE_MODE => g_INTERFACE_MODE, g_ADDRESS_GRANULARITY => g_ADDRESS_GRANULARITY, g_WITH_EXTRA_WB_REG => g_WITH_EXTRA_WB_REG, -- Position g_ADC_WIDTH => g_ADC_WIDTH, g_DECIM_WIDTH => g_DECIM_WIDTH ) port map ( ----------------------------- -- Clocks and resets ----------------------------- rst_n_i => rst_n_i, clk_i => clk_i, ref_rst_n_i => ref_rst_n_i, ref_clk_i => ref_clk_i, ----------------------------- -- Wishbone signals ----------------------------- wb_adr_i => wb_slv_i.adr, wb_dat_i => wb_slv_i.dat, wb_dat_o => wb_slv_o.dat, wb_sel_i => wb_slv_i.sel, wb_we_i => wb_slv_i.we, wb_cyc_i => wb_slv_i.cyc, wb_stb_i => wb_slv_i.stb, wb_ack_o => wb_slv_o.ack, wb_stall_o => wb_slv_o.stall, ----------------------------- -- Downstream ADC and position signals ----------------------------- fs_clk_ds_i => fs_clk_ds_i, adc_ds_ch0_swap_i => adc_ds_ch0_swap_i, adc_ds_ch1_swap_i => adc_ds_ch1_swap_i, adc_ds_ch2_swap_i => adc_ds_ch2_swap_i, adc_ds_ch3_swap_i => adc_ds_ch3_swap_i, adc_ds_tag_i => adc_ds_tag_i, adc_ds_swap_valid_i => adc_ds_swap_valid_i, decim_ds_pos_x_i => decim_ds_pos_x_i, decim_ds_pos_y_i => decim_ds_pos_y_i, decim_ds_pos_q_i => decim_ds_pos_q_i, decim_ds_pos_sum_i => decim_ds_pos_sum_i, decim_ds_pos_valid_i => decim_ds_pos_valid_i, ----------------------------- -- Upstream ADC and position signals ----------------------------- fs_clk_us_i => fs_clk_us_i, adc_us_ch0_swap_i => adc_us_ch0_swap_i, adc_us_ch1_swap_i => adc_us_ch1_swap_i, adc_us_ch2_swap_i => adc_us_ch2_swap_i, adc_us_ch3_swap_i => adc_us_ch3_swap_i, adc_us_tag_i => adc_us_tag_i, adc_us_swap_valid_i => adc_us_swap_valid_i, decim_us_pos_x_i => decim_us_pos_x_i, decim_us_pos_y_i => decim_us_pos_y_i, decim_us_pos_q_i => decim_us_pos_q_i, decim_us_pos_sum_i => decim_us_pos_sum_i, decim_us_pos_valid_i => decim_us_pos_valid_i, ----------------------------- -- Interlock outputs ----------------------------- intlk_trans_bigger_x_o => intlk_trans_bigger_x_o, intlk_trans_bigger_y_o => intlk_trans_bigger_y_o, intlk_trans_bigger_ltc_x_o => intlk_trans_bigger_ltc_x_o, intlk_trans_bigger_ltc_y_o => intlk_trans_bigger_ltc_y_o, intlk_trans_bigger_any_o => intlk_trans_bigger_any_o, intlk_trans_bigger_ltc_o => intlk_trans_bigger_ltc_o, intlk_trans_bigger_o => intlk_trans_bigger_o, intlk_trans_smaller_x_o => intlk_trans_smaller_x_o, intlk_trans_smaller_y_o => intlk_trans_smaller_y_o, intlk_trans_smaller_ltc_x_o => intlk_trans_smaller_ltc_x_o, intlk_trans_smaller_ltc_y_o => intlk_trans_smaller_ltc_y_o, intlk_trans_smaller_any_o => intlk_trans_smaller_any_o, intlk_trans_smaller_ltc_o => intlk_trans_smaller_ltc_o, intlk_trans_smaller_o => intlk_trans_smaller_o, intlk_ang_bigger_x_o => intlk_ang_bigger_x_o, intlk_ang_bigger_y_o => intlk_ang_bigger_y_o, intlk_ang_bigger_ltc_x_o => intlk_ang_bigger_ltc_x_o, intlk_ang_bigger_ltc_y_o => intlk_ang_bigger_ltc_y_o, intlk_ang_bigger_any_o => intlk_ang_bigger_any_o, intlk_ang_bigger_ltc_o => intlk_ang_bigger_ltc_o, intlk_ang_bigger_o => intlk_ang_bigger_o, intlk_ang_smaller_x_o => intlk_ang_smaller_x_o, intlk_ang_smaller_y_o => intlk_ang_smaller_y_o, intlk_ang_smaller_ltc_x_o => intlk_ang_smaller_ltc_x_o, intlk_ang_smaller_ltc_y_o => intlk_ang_smaller_ltc_y_o, intlk_ang_smaller_any_o => intlk_ang_smaller_any_o, intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc_o, intlk_ang_smaller_o => intlk_ang_smaller_o, intlk_ltc_o => intlk_ltc_o, intlk_o => intlk_o ); end rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity vga_axi_mem_buffer_v1_0 is generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Slave Bus Interface S_AXI C_S_AXI_ID_WIDTH : integer := 1; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 6; C_S_AXI_AWUSER_WIDTH : integer := 0; C_S_AXI_ARUSER_WIDTH : integer := 0; C_S_AXI_WUSER_WIDTH : integer := 0; C_S_AXI_RUSER_WIDTH : integer := 0; C_S_AXI_BUSER_WIDTH : integer := 0 ); port ( -- Users to add ports here -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Slave Bus Interface S_AXI s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic; s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awqos : in std_logic_vector(3 downto 0); s_axi_awregion : in std_logic_vector(3 downto 0); s_axi_awuser : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wlast : in std_logic; s_axi_wuser : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_buser : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic; s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arqos : in std_logic_vector(3 downto 0); s_axi_arregion : in std_logic_vector(3 downto 0); s_axi_aruser : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_ruser : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic ); end vga_axi_mem_buffer_v1_0; architecture arch_imp of vga_axi_mem_buffer_v1_0 is -- component declaration component vga_axi_mem_buffer_v1_0_S_AXI is generic ( C_S_AXI_ID_WIDTH : integer := 1; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 6; C_S_AXI_AWUSER_WIDTH : integer := 0; C_S_AXI_ARUSER_WIDTH : integer := 0; C_S_AXI_WUSER_WIDTH : integer := 0; C_S_AXI_RUSER_WIDTH : integer := 0; C_S_AXI_BUSER_WIDTH : integer := 0 ); port ( S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWLEN : in std_logic_vector(7 downto 0); S_AXI_AWSIZE : in std_logic_vector(2 downto 0); S_AXI_AWBURST : in std_logic_vector(1 downto 0); S_AXI_AWLOCK : in std_logic; S_AXI_AWCACHE : in std_logic_vector(3 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWQOS : in std_logic_vector(3 downto 0); S_AXI_AWREGION : in std_logic_vector(3 downto 0); S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WLAST : in std_logic; S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARLEN : in std_logic_vector(7 downto 0); S_AXI_ARSIZE : in std_logic_vector(2 downto 0); S_AXI_ARBURST : in std_logic_vector(1 downto 0); S_AXI_ARLOCK : in std_logic; S_AXI_ARCACHE : in std_logic_vector(3 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARQOS : in std_logic_vector(3 downto 0); S_AXI_ARREGION : in std_logic_vector(3 downto 0); S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RLAST : out std_logic; S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic ); end component vga_axi_mem_buffer_v1_0_S_AXI; begin -- Instantiation of Axi Bus Interface S_AXI vga_axi_mem_buffer_v1_0_S_AXI_inst : vga_axi_mem_buffer_v1_0_S_AXI generic map ( C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_AWUSER_WIDTH => C_S_AXI_AWUSER_WIDTH, C_S_AXI_ARUSER_WIDTH => C_S_AXI_ARUSER_WIDTH, C_S_AXI_WUSER_WIDTH => C_S_AXI_WUSER_WIDTH, C_S_AXI_RUSER_WIDTH => C_S_AXI_RUSER_WIDTH, C_S_AXI_BUSER_WIDTH => C_S_AXI_BUSER_WIDTH ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWID => s_axi_awid, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWLEN => s_axi_awlen, S_AXI_AWSIZE => s_axi_awsize, S_AXI_AWBURST => s_axi_awburst, S_AXI_AWLOCK => s_axi_awlock, S_AXI_AWCACHE => s_axi_awcache, S_AXI_AWPROT => s_axi_awprot, S_AXI_AWQOS => s_axi_awqos, S_AXI_AWREGION => s_axi_awregion, S_AXI_AWUSER => s_axi_awuser, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WLAST => s_axi_wlast, S_AXI_WUSER => s_axi_wuser, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BID => s_axi_bid, S_AXI_BRESP => s_axi_bresp, S_AXI_BUSER => s_axi_buser, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARID => s_axi_arid, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARLEN => s_axi_arlen, S_AXI_ARSIZE => s_axi_arsize, S_AXI_ARBURST => s_axi_arburst, S_AXI_ARLOCK => s_axi_arlock, S_AXI_ARCACHE => s_axi_arcache, S_AXI_ARPROT => s_axi_arprot, S_AXI_ARQOS => s_axi_arqos, S_AXI_ARREGION => s_axi_arregion, S_AXI_ARUSER => s_axi_aruser, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RID => s_axi_rid, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RLAST => s_axi_rlast, S_AXI_RUSER => s_axi_ruser, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready ); -- Add user logic here -- User logic ends end arch_imp;
-- -- Authors: Francisco Paiva Knebel -- Gabriel Alexandre Zillmer -- -- Universidade Federal do Rio Grande do Sul -- Instituto de Informática -- Sistemas Digitais -- Prof. Fernanda Lima Kastensmidt -- -- Create Date: 10:44:10 05/03/2016 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; use IEEE.std_logic_arith.all; USE ieee.numeric_std.all; entity ula is Port ( X : in STD_LOGIC_VECTOR (7 downto 0); Y : in STD_LOGIC_VECTOR (7 downto 0); selector : in STD_LOGIC_VECTOR (2 downto 0); N : out STD_LOGIC; Z : out STD_LOGIC; output : out STD_LOGIC_VECTOR (7 downto 0); carryMUL: out STD_LOGIC_VECTOR (7 downto 0) -- need to make this save to address 100, add control unit state ); end ula; architecture Behavioral of ula is signal result : STD_LOGIC_VECTOR(7 downto 0); signal e1, e2 : STD_LOGIC_VECTOR(7 downto 0); signal MULTIPLICATION: STD_LOGIC_VECTOR(15 downto 0); begin e1 <= X; e2 <= Y; process(selector, e1, e2) begin -- 000 ADD -- 001 AND -- 010 OR -- 011 NOT -- 100 LDA -- 101 SHR -- 110 SHL -- 111 MUL case selector is when "000" => result <= e1 + e2; -- ADD when "001" => result <= e1 AND e2; -- AND when "010" => result <= e1 OR e2; -- OR when "011" => result <= not(e1); -- NOT when "100" => result <= e2; -- LDA when "101" => result <= "0" & e1(7 downto 1); -- SHR when "110" => result <= e1(6 downto 0) & "0"; -- SHL when "111" => MULTIPLICATION <= e1 * e2; -- MUL result <= MULTIPLICATION(7 downto 0); -- lsb when others => result <= e2; end case; -- Zero if(result = "00000000") then Z <= '1'; else Z <= '0'; end if; -- Negative N <= result(7); end process; carryMUL <= MULTIPLICATION(15 downto 8); output <= result; end Behavioral;
------------------------------------------------------------------------------- -- axi_master_lite_cntlr.vhd ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_master_lite_cntlr.vhd -- -- Description: -- -- This VHDL file is the design implementation for the Read/Write Controller -- that is part of the AXI Master Lite core. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_master_lite.vhd (v3_00_a) -- \| -- \|- axi_master_lite_cntlr.vhd -- \| -- \|- axi_master_lite_reset.vhd -- ------------------------------------------------------------------------------- -- Author: DET -- Revision: $Revision: 1.1.2.3 $ -- Date: $12/01/2010$ -- -- History: -- DET 12/01/2010 Initial Version -- -- DET 12/14/2010 Initial -- ~~~~~~ -- -- Per CR587090 -- - Removed the input port m_axi_rlast. It is not part of the AXI4-Lite -- signal set. -- ^^^^^^ -- -- DET 12/15/2010 Initial -- ~~~~~~ -- -- Per CR587194 -- - Fixed the Bus2IP_Error assertion logic. -- ^^^^^^ -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library proc_common_v3_00_a; Use proc_common_v3_00_a.proc_common_pkg.all; Use proc_common_v3_00_a.family_support.all; ------------------------------------------------------------------------------- entity axi_master_lite_cntlr is generic ( -- AXI4 Parameters C_M_AXI_LITE_ADDR_WIDTH : INTEGER range 32 to 32 := 32; -- width of AXI4 Address Bus (in bits) C_M_AXI_LITE_DATA_WIDTH : INTEGER range 32 to 32 := 32; -- Width of the AXI4 Data Bus (in bits) -- FPGA Family Parameter C_FAMILY : String := "virtex6" -- Select the target architecture type -- see the family.vhd package in the proc_common -- library ); port ( ----------------------------------------------------------------------- -- Clock Input ----------------------------------------------------------------------- axi_aclk : in std_logic ;-- AXI4 ----------------------------------------------------------------------- -- Reset Input (active high) ----------------------------------------------------------------------- axi_reset : in std_logic ;-- AXI4 ----------------------------------------------------------------------- -- Master Detected Error output ----------------------------------------------------------------------- md_error : out std_logic ;-- Discrete Out ---------------------------------------------------------------------------- -- AXI4 Read Channels ---------------------------------------------------------------------------- -- AXI4 Read Address Channel -- AXI4 m_axi_arready : in std_logic ; -- AXI4 m_axi_arvalid : out std_logic ; -- AXI4 m_axi_araddr : out std_logic_vector -- AXI4 (C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4 m_axi_arprot : out std_logic_vector(2 downto 0) ; -- AXI4 -- AXI4 -- AXI4 Read Data Channel -- AXI4 m_axi_rready : out std_logic ; -- AXI4 m_axi_rvalid : in std_logic ; -- AXI4 m_axi_rdata : in std_logic_vector -- AXI4 (C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- AXI4 m_axi_rresp : in std_logic_vector(1 downto 0) ; -- AXI4 ----------------------------------------------------------------------------- -- AXI4 Write Channels ----------------------------------------------------------------------------- -- AXI4 Write Address Channel m_axi_awready : in std_logic ; -- AXI4 m_axi_awvalid : out std_logic ; -- AXI4 m_axi_awaddr : out std_logic_vector -- AXI4 (C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4 m_axi_awprot : out std_logic_vector(2 downto 0) ; -- AXI4 -- AXI4 -- AXI4 Write Data Channel -- AXI4 m_axi_wready : in std_logic ; -- AXI4 m_axi_wvalid : out std_logic ; -- AXI4 m_axi_wdata : out std_logic_vector -- AXI4 (C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- AXI4 m_axi_wstrb : out std_logic_vector -- AXI4 ((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);-- AXI4 -- AXI4 -- AXI4 Write Response Channel -- AXI4 m_axi_bready : out std_logic ; -- AXI4 m_axi_bvalid : in std_logic ; -- AXI4 m_axi_bresp : in std_logic_vector(1 downto 0) ; -- AXI4 ----------------------------------------------------------------------------- -- IP Master Request/Qualifers ----------------------------------------------------------------------------- ip2bus_mstrd_req : In std_logic; -- IPIC ip2bus_mstwr_req : In std_logic; -- IPIC ip2bus_mst_addr : in std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- IPIC ip2bus_mst_be : in std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);-- IPIC ip2bus_mst_lock : In std_logic; -- IPIC -- IPIC ----------------------------------------------------------------------------- -- IP Request Status Reply ----------------------------------------------------------------------------- bus2ip_mst_cmdack : Out std_logic; -- IPIC bus2ip_mst_cmplt : Out std_logic; -- IPIC bus2ip_mst_error : Out std_logic; -- IPIC bus2ip_mst_rearbitrate : Out std_logic; -- IPIC bus2ip_mst_cmd_timeout : out std_logic; -- IPIC -- IPIC -- IPIC ----------------------------------------------------------------------------- -- IPIC Read data ----------------------------------------------------------------------------- bus2ip_mstrd_d : out std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- IPIC bus2ip_mstrd_src_rdy_n : Out std_logic; -- IPIC -- IPIC ----------------------------------------------------------------------------- -- IPIC Write data ----------------------------------------------------------------------------- ip2bus_mstwr_d : In std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- IPIC bus2ip_mstwr_dst_rdy_n : Out std_logic -- IPIC ); end entity axi_master_lite_cntlr; architecture implementation of axi_master_lite_cntlr is -- Signal declarations --------------------------------------- -- AXI4 Read Address Channel signal sig_m_axi_arready : std_logic := '0'; signal sig_m_axi_arvalid : std_logic := '0'; signal sig_m_axi_araddr : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_m_axi_arprot : std_logic_vector(2 downto 0) := (others => '0') ; -- AXI4 Read Data Channel signal sig_m_axi_rready : std_logic := '0'; signal sig_m_axi_rvalid : std_logic := '0'; signal sig_m_axi_rdata : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_m_axi_rresp : std_logic_vector(1 downto 0) := (others => '0'); -- Write Address Channel signal sig_m_axi_awready : std_logic := '0'; signal sig_m_axi_awvalid : std_logic := '0'; signal sig_m_axi_awaddr : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_m_axi_awprot : std_logic_vector(2 downto 0) := (others => '0'); -- Write Data Channel signal sig_m_axi_wready : std_logic := '0'; signal sig_m_axi_wvalid : std_logic := '0'; signal sig_m_axi_wdata : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_m_axi_wstrb : std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0) := (others => '0'); -- Write Response Channel signal sig_m_axi_bready : std_logic := '0'; signal sig_m_axi_bvalid : std_logic := '0'; signal sig_m_axi_bresp : std_logic_vector(1 downto 0) := (others => '0'); -- IP Master Request Qualifers signal sig_ip2bus_rd_req : std_logic := '0'; signal sig_ip2bus_wr_req : std_logic := '0'; signal sig_ip2bus_addr : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_ip2bus_addr_reg : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_ip2bus_be : std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ip2bus_lock : std_logic := '0'; -- IPIC Status Reply signal sig_bus2ip_cmdack : std_logic := '0'; signal sig_bus2ip_rearbitrate : std_logic := '0'; signal sig_bus2ip_cmd_timeout : std_logic := '0'; signal sig_bus2ip_cmplt : std_logic := '0'; signal sig_bus2ip_error : std_logic := '0'; -- IPIC Data Interface signal sig_bus2ip_mstrd_d : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_bus2ip_rd_src_rdy : std_logic := '0'; signal sig_ip2bus_mstwr_d : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_bus2ip_wr_dst_rdy : std_logic := '0'; -- AXI Error Response signal sig_read_resp_error : std_logic := '0'; signal sig_read_error : std_logic := '0'; signal sig_write_resp_error : std_logic := '0'; signal sig_write_error : std_logic := '0'; -- Transfer completion signal sig_rd_addrqual_taken : std_logic := '0'; signal sig_wr_addrqual_taken : std_logic := '0'; signal sig_rd_data_taken : std_logic := '0'; signal sig_wr_data_taken : std_logic := '0'; signal sig_wr_resp_taken : std_logic := '0'; -- Transfer Startup signal sig_rd_start : std_logic := '0'; signal sig_wr_start : std_logic := '0'; signal sig_ld_addr : std_logic := '0'; -- Read Transfer sequence signal sig_rd_req_reg : std_logic := '0'; signal sig_rd_in_prog : std_logic := '0'; signal sig_rd_addr_cmplt : std_logic := '0'; signal sig_rd_data_cmplt : std_logic := '0'; signal sig_rd_cmplt : std_logic := '0'; -- Write Transfer sequence signal sig_wr_req_reg : std_logic := '0'; signal sig_wr_in_prog : std_logic := '0'; signal sig_wr_addr_cmplt : std_logic := '0'; signal sig_wr_data_cmplt : std_logic := '0'; signal sig_wr_resp_cmplt : std_logic := '0'; signal sig_wr_cmplt : std_logic := '0'; -- Command Completion signal sig_bus2ip_cmplt_local : std_logic := '0'; -- Detected error signal sig_md_error : std_logic := '0'; ---------------------------------------------------------------- -- Register duplication attribute assignments to control fanout -- on register clear signals ---------------------------------------------------------------- Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_bus2ip_cmplt_local : signal is "TRUE"; Attribute KEEP of sig_bus2ip_cmplt : signal is "TRUE"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_bus2ip_cmplt_local : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_bus2ip_cmplt : signal is "no"; begin --(architecture implementation) ----------------------------------------------------------------------------- -- Port Assignments ----------------------------------------------------------------------------- -- Read Address Channel port assignments sig_m_axi_arready <= m_axi_arready ; m_axi_arvalid <= sig_m_axi_arvalid ; m_axi_araddr <= sig_m_axi_araddr ; m_axi_arprot <= sig_m_axi_arprot ; -- Read Data Channel port assignments m_axi_rready <= sig_m_axi_rready ; sig_m_axi_rvalid <= m_axi_rvalid ; sig_m_axi_rdata <= m_axi_rdata ; sig_m_axi_rresp <= m_axi_rresp ; -- Write Address Channel port assignments sig_m_axi_awready <= m_axi_awready ; m_axi_awvalid <= sig_m_axi_awvalid ; m_axi_awaddr <= sig_m_axi_awaddr ; m_axi_awprot <= sig_m_axi_awprot ; -- AXI4 Write Data Channel port assignments sig_m_axi_wready <= m_axi_wready ; m_axi_wvalid <= sig_m_axi_wvalid ; m_axi_wdata <= sig_m_axi_wdata ; m_axi_wstrb <= sig_m_axi_wstrb ; -- AXI4 Write Response Channel port assignments m_axi_bready <= sig_m_axi_bready ; sig_m_axi_bvalid <= m_axi_bvalid ; sig_m_axi_bresp <= m_axi_bresp ; -- IPIC Command Qualifiers sig_ip2bus_rd_req <= ip2bus_mstrd_req ; -- Input sig_ip2bus_wr_req <= ip2bus_mstwr_req ; -- Input sig_ip2bus_addr <= ip2bus_mst_addr ; -- Input sig_ip2bus_be <= ip2bus_mst_be ; -- Input sig_ip2bus_lock <= ip2bus_mst_lock ; -- Input -- IPIC Status reply bus2ip_mst_cmdack <= sig_bus2ip_cmdack ; -- output bus2ip_mst_rearbitrate <= sig_bus2ip_rearbitrate ; -- output bus2ip_mst_cmd_timeout <= sig_bus2ip_cmd_timeout ; -- output bus2ip_mst_cmplt <= sig_bus2ip_cmplt ; -- output bus2ip_mst_error <= sig_bus2ip_error ; -- output -- IPIC Read Data IF bus2ip_mstrd_d <= sig_bus2ip_mstrd_d ; -- output bus2ip_mstrd_src_rdy_n <= not(sig_bus2ip_rd_src_rdy); -- output -- IPIC write Data IF sig_ip2bus_mstwr_d <= ip2bus_mstwr_d ; -- input bus2ip_mstwr_dst_rdy_n <= not(sig_bus2ip_wr_dst_rdy); -- output -- MD Error output md_error <= sig_md_error ; -- output -- IPIC Error status output sig_bus2ip_error <= sig_read_error or -- Assert on either a read sig_write_error ; -- or write error detection ----------------------------------------------------------------------------- -- Combinitorial logic ----------------------------------------------------------------------------- -- Drive the IPIC Rearbitrate and Timeout to zeros sig_bus2ip_rearbitrate <= '0' ; -- not available in AXI4 sig_bus2ip_cmd_timeout <= '0' ; -- not available in AXI4 -- Drive the axi protection qualifiers to zeros sig_m_axi_awprot <= (others => '0') ; -- always driven to zeros sig_m_axi_arprot <= (others => '0') ; -- always driven to zeros -- Share the address register for both read and write xfers sig_m_axi_araddr <= sig_ip2bus_addr_reg ; sig_m_axi_awaddr <= sig_ip2bus_addr_reg ; -- Detect when the read address has been accepted on the axi bus sig_rd_addrqual_taken <= sig_m_axi_arvalid and sig_m_axi_arready ; -- Detect when the write address has been accepted axi bus sig_wr_addrqual_taken <= sig_m_axi_awvalid and sig_m_axi_awready ; -- Detect when the read data has been accepted axi bus sig_rd_data_taken <= sig_m_axi_rvalid and sig_m_axi_rready ; -- Detect when the write data has been accepted axi bus sig_wr_data_taken <= sig_m_axi_wvalid and sig_m_axi_wready ; -- Detect when the write response has been accepted axi bus sig_wr_resp_taken <= sig_m_axi_bvalid and sig_m_axi_bready ; -- Detirmine if a read response error is being flagged sig_read_resp_error <= '1' when (sig_m_axi_rresp(0) = '1' or sig_m_axi_rresp(1) = '1') else '0'; -- Detirmine if a write response error is being flagged sig_write_resp_error <= '1' when (sig_m_axi_bresp(0) = '1' or sig_m_axi_bresp(1) = '1') else '0'; -- Detirmine if a read transfer sequence has completed -- or is about to complete sig_rd_cmplt <= sig_rd_in_prog and (sig_rd_addr_cmplt or sig_rd_addrqual_taken) and (sig_rd_data_cmplt or sig_rd_data_taken); -- Detirmine if a write transfer sequence has completed -- or is about to complete sig_wr_cmplt <= sig_wr_in_prog and (sig_wr_addr_cmplt or sig_wr_addrqual_taken) and (sig_wr_data_cmplt or sig_wr_data_taken) and (sig_wr_resp_cmplt or sig_wr_resp_taken); -- Generate the Command Address sample and hold signal sig_ld_addr <= sig_rd_start or sig_wr_start; -- Detect rising edge of new read command sig_rd_start <= sig_ip2bus_rd_req and not(sig_rd_req_reg); -- Detect rising edge of new write command sig_wr_start <= sig_ip2bus_wr_req and not(sig_wr_req_reg); ----------------------------------------------------------------------------- -- Command Start detection ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RDREQ_REG -- -- Process Description: -- Registers the IPIC read request input. -- ------------------------------------------------------------- IMP_RDREQ_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_rd_req_reg <= '0' ; else sig_rd_req_reg <= sig_ip2bus_rd_req ; end if; end if; end process IMP_RDREQ_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WRREQ_REG -- -- Process Description: -- Registers the IPIC write request input. -- ------------------------------------------------------------- IMP_WRREQ_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_wr_req_reg <= '0' ; else sig_wr_req_reg <= sig_ip2bus_wr_req ; end if; end if; end process IMP_WRREQ_REG; ----------------------------------------------------------------------------- -- shared Address Register ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_REG -- -- Process Description: -- Registers the IPIC addres input whenever a new command -- has been detected. -- ------------------------------------------------------------- IMP_ADDR_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_ip2bus_addr_reg <= (others => '0') ; elsif (sig_ld_addr = '1') then sig_ip2bus_addr_reg <= sig_ip2bus_addr ; else null; -- Hold Current State end if; end if; end process IMP_ADDR_REG; ----------------------------------------------------------------------------- -- Generate Write Transfer Registers and Control ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WRITE_IN_PROG_FLOP -- -- Process Description: -- Implements the read in progress flop. -- ------------------------------------------------------------- IMP_WRITE_IN_PROG_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_wr_in_prog <= '0' ; elsif (sig_wr_start = '1') then sig_wr_in_prog <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WRITE_IN_PROG_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_AWVALID_FLOP -- -- Process Description: -- Implements the write awvalid flop. -- ------------------------------------------------------------- IMP_AWVALID_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_wr_addrqual_taken = '1') then sig_m_axi_awvalid <= '0' ; elsif (sig_wr_start = '1') then sig_m_axi_awvalid <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_AWVALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WVALID_FLOP -- -- Process Description: -- Implements the write wvalid flop. -- ------------------------------------------------------------- IMP_WVALID_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_wr_data_taken = '1') then sig_m_axi_wvalid <= '0' ; elsif (sig_wr_start = '1') then sig_m_axi_wvalid <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WVALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WDATA_REG -- -- Process Description: -- Implements the write data register. -- ------------------------------------------------------------- IMP_WDATA_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_m_axi_wdata <= (others => '0') ; sig_m_axi_wstrb <= (others => '0') ; elsif (sig_wr_start = '1') then sig_m_axi_wdata <= sig_ip2bus_mstwr_d ; sig_m_axi_wstrb <= sig_ip2bus_be ; else null; -- Hold Current State end if; end if; end process IMP_WDATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_ERR_REG -- -- Process Description: -- Implements the read response error flag. -- ------------------------------------------------------------- IMP_WR_ERR_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_write_error <= '0' ; elsif (sig_wr_resp_taken = '1') then sig_write_error <= sig_write_resp_error ; else null; -- Hold Current State end if; end if; end process IMP_WR_ERR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_DST_RDY_FLAG -- -- Process Description: -- Implements the IPIC write destination ready flag. -- ------------------------------------------------------------- IMP_WR_DST_RDY_FLAG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_wr_dst_rdy = '1') then sig_bus2ip_wr_dst_rdy <= '0' ; --elsif (sig_wr_data_taken = '1') then elsif (sig_wr_cmplt = '1') then sig_bus2ip_wr_dst_rdy <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_DST_RDY_FLAG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_BREADY_FLOP -- -- Process Description: -- Implements the write response channel bready flop. -- ------------------------------------------------------------- IMP_WR_BREADY_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_wr_resp_taken = '1') then sig_m_axi_bready <= '0' ; elsif (sig_wr_start = '1') then sig_m_axi_bready <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_BREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_ADDR_CMPLT_FLOP -- -- Process Description: -- Implements the write address complete flag. -- ------------------------------------------------------------- IMP_WR_ADDR_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_wr_addr_cmplt <= '0' ; elsif (sig_wr_addrqual_taken = '1') then sig_wr_addr_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_ADDR_CMPLT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_DATA_CMPLT_FLOP -- -- Process Description: -- Implements the write data complete flag. -- ------------------------------------------------------------- IMP_WR_DATA_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_wr_data_cmplt <= '0' ; elsif (sig_wr_data_taken = '1') then sig_wr_data_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_DATA_CMPLT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_RESP_CMPLT_FLOP -- -- Process Description: -- Implements the write data complete flag. -- ------------------------------------------------------------- IMP_WR_RESP_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_wr_resp_cmplt <= '0' ; elsif (sig_wr_resp_taken = '1') then sig_wr_resp_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_RESP_CMPLT_FLOP; ----------------------------------------------------------------------------- -- Generate Read Transfer Registers and Control ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_READ_IN_PROG_FLOP -- -- Process Description: -- Implements the read in progress flop. -- ------------------------------------------------------------- IMP_READ_IN_PROG_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_rd_in_prog <= '0' ; elsif (sig_rd_start = '1') then sig_rd_in_prog <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_READ_IN_PROG_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RVALID_FLOP -- -- Process Description: -- Implements the write awvalid flop. -- ------------------------------------------------------------- IMP_RVALID_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_rd_addrqual_taken = '1') then sig_m_axi_arvalid <= '0' ; elsif (sig_rd_start = '1') then sig_m_axi_arvalid <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RVALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RREADY_FLOP -- -- Process Description: -- Implements the read rready flop. -- ------------------------------------------------------------- IMP_RREADY_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_rd_data_taken = '1') then sig_m_axi_rready <= '0' ; elsif (sig_rd_start = '1') then sig_m_axi_rready <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RDATA_REG -- -- Process Description: -- Implements the read data register. -- ------------------------------------------------------------- IMP_RDATA_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_bus2ip_mstrd_d <= (others => '0') ; elsif (sig_rd_data_taken = '1') then sig_bus2ip_mstrd_d <= sig_m_axi_rdata ; else null; -- Hold Current State end if; end if; end process IMP_RDATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RD_SRC_RDY_FLAG -- -- Process Description: -- Implements the IPIC read source ready flag. -- ------------------------------------------------------------- IMP_RD_SRC_RDY_FLAG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_rd_src_rdy = '1') then sig_bus2ip_rd_src_rdy <= '0' ; elsif (sig_rd_data_taken = '1') then sig_bus2ip_rd_src_rdy <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RD_SRC_RDY_FLAG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_READ_ERR_REG -- -- Process Description: -- Implements the read response error flag. -- ------------------------------------------------------------- IMP_READ_ERR_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_read_error <= '0' ; elsif (sig_rd_data_taken = '1') then sig_read_error <= sig_read_resp_error ; else null; -- Hold Current State end if; end if; end process IMP_READ_ERR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RD_ADDR_CMPLT_FLOP -- -- Process Description: -- Implements the read address complete flag. -- ------------------------------------------------------------- IMP_RD_ADDR_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_rd_addr_cmplt <= '0' ; elsif (sig_rd_addrqual_taken = '1') then sig_rd_addr_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RD_ADDR_CMPLT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RD_DATA_CMPLT_FLOP -- -- Process Description: -- Implements the read data complete flag. -- ------------------------------------------------------------- IMP_RD_DATA_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_rd_data_cmplt <= '0' ; elsif (sig_rd_data_taken = '1') then sig_rd_data_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RD_DATA_CMPLT_FLOP; ----------------------------------------------------------------------------- -- IPIC Command Status Generation logic ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMDACK_FLOP -- -- Process Description: -- Implements the IPIC Command Acknowledge status flag. -- ------------------------------------------------------------- IMP_CMDACK_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmdack = '1') then sig_bus2ip_cmdack <= '0' ; elsif (sig_rd_addrqual_taken = '1' or sig_wr_addrqual_taken = '1') then sig_bus2ip_cmdack <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_CMDACK_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_CMPLT_LOCAL_FLOP -- -- Process Description: -- Implements the IPIC Command Acknowledge status flag. -- ------------------------------------------------------------- IMP_CMD_CMPLT_LOCAL_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_bus2ip_cmplt_local <= '0' ; elsif (sig_rd_cmplt = '1' or sig_wr_cmplt = '1') then sig_bus2ip_cmplt_local <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_CMD_CMPLT_LOCAL_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_CMPLT_FLOP -- -- Process Description: -- Implements the IPIC Command Acknowledge status flag. -- ------------------------------------------------------------- IMP_CMD_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_bus2ip_cmplt <= '0' ; elsif (sig_rd_cmplt = '1' or sig_wr_cmplt = '1') then sig_bus2ip_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_CMD_CMPLT_FLOP; ----------------------------------------------------------------------------- -- Master Detected error logic ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_H_ERRORS -- -- Process Description: -- This process implements the sample and hold logic for -- any detected errors. If an error is detected, then the -- md_error output signal is driven high until the Master -- is reset. -- ------------------------------------------------------------- S_H_ERRORS : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_md_error <= '0'; elsif (sig_read_error = '1' or sig_write_error = '1') then sig_md_error <= '1'; else null; -- hold last state end if; else null; end if; end process S_H_ERRORS; end implementation;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc613.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- ************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:43 1996 -- -- ************************ -- -- ************************ -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:03 1996 -- -- ************************ -- -- ************************ -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:22 1996 -- -- ************************ -- ENTITY c03s04b01x00p01n01i00613ent IS END c03s04b01x00p01n01i00613ent; ARCHITECTURE c03s04b01x00p01n01i00613arch OF c03s04b01x00p01n01i00613ent IS constant C1 : boolean := true; constant C4 : severity_level := note; constant C5 : integer := 3; constant C6 : real := 3.0; constant C7 : time := 3 ns; constant C8 : natural := 3; constant C9 : positive := 3; type boolean_cons_vector is array (15 downto 0) of boolean; type severity_level_cons_vector is array (15 downto 0) of severity_level; type integer_cons_vector is array (15 downto 0) of integer; type real_cons_vector is array (15 downto 0) of real; type time_cons_vector is array (15 downto 0) of time; type natural_cons_vector is array (15 downto 0) of natural; type positive_cons_vector is array (15 downto 0) of positive; constant C19 : boolean_cons_vector := (others => C1); constant C20 : severity_level_cons_vector := (others => C4); constant C21 : integer_cons_vector := (others => C5); constant C22 : real_cons_vector := (others => C6); constant C23 : time_cons_vector := (others => C7); constant C24 : natural_cons_vector := (others => C8); constant C25 : positive_cons_vector := (others => C9); type record_cons_array is record a:boolean_cons_vector; b:severity_level_cons_vector; c:integer_cons_vector; d:real_cons_vector; e:time_cons_vector; f:natural_cons_vector; g:positive_cons_vector; end record; type record_cons_array_file is file of record_cons_array; constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25); signal k : integer := 0; BEGIN TESTING: PROCESS file filein : record_cons_array_file open read_mode is "iofile.34"; variable v : record_cons_array; BEGIN for i in 1 to 100 loop assert(endfile(filein) = false) report"end of file reached before expected"; read(filein,v); if (v /= C27) then k <= 1; end if; end loop; wait for 1 ns; assert NOT(k = 0) report "PASSED TEST: c03s04b01x00p01n01i00613" severity NOTE; assert (k = 0) report "**FAILED TEST: c03s04b01x00p01n01i00613 - File reading operation (record_cons_array file type) failed." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p01n01i00613arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc613.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- ************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:43 1996 -- -- ************************ -- -- ************************ -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:03 1996 -- -- ************************ -- -- ************************ -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:22 1996 -- -- ************************ -- ENTITY c03s04b01x00p01n01i00613ent IS END c03s04b01x00p01n01i00613ent; ARCHITECTURE c03s04b01x00p01n01i00613arch OF c03s04b01x00p01n01i00613ent IS constant C1 : boolean := true; constant C4 : severity_level := note; constant C5 : integer := 3; constant C6 : real := 3.0; constant C7 : time := 3 ns; constant C8 : natural := 3; constant C9 : positive := 3; type boolean_cons_vector is array (15 downto 0) of boolean; type severity_level_cons_vector is array (15 downto 0) of severity_level; type integer_cons_vector is array (15 downto 0) of integer; type real_cons_vector is array (15 downto 0) of real; type time_cons_vector is array (15 downto 0) of time; type natural_cons_vector is array (15 downto 0) of natural; type positive_cons_vector is array (15 downto 0) of positive; constant C19 : boolean_cons_vector := (others => C1); constant C20 : severity_level_cons_vector := (others => C4); constant C21 : integer_cons_vector := (others => C5); constant C22 : real_cons_vector := (others => C6); constant C23 : time_cons_vector := (others => C7); constant C24 : natural_cons_vector := (others => C8); constant C25 : positive_cons_vector := (others => C9); type record_cons_array is record a:boolean_cons_vector; b:severity_level_cons_vector; c:integer_cons_vector; d:real_cons_vector; e:time_cons_vector; f:natural_cons_vector; g:positive_cons_vector; end record; type record_cons_array_file is file of record_cons_array; constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25); signal k : integer := 0; BEGIN TESTING: PROCESS file filein : record_cons_array_file open read_mode is "iofile.34"; variable v : record_cons_array; BEGIN for i in 1 to 100 loop assert(endfile(filein) = false) report"end of file reached before expected"; read(filein,v); if (v /= C27) then k <= 1; end if; end loop; wait for 1 ns; assert NOT(k = 0) report "PASSED TEST: c03s04b01x00p01n01i00613" severity NOTE; assert (k = 0) report "**FAILED TEST: c03s04b01x00p01n01i00613 - File reading operation (record_cons_array file type) failed." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p01n01i00613arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc613.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- ************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:43 1996 -- -- ************************ -- -- ************************ -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:03 1996 -- -- ************************ -- -- ************************ -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:22 1996 -- -- ************************ -- ENTITY c03s04b01x00p01n01i00613ent IS END c03s04b01x00p01n01i00613ent; ARCHITECTURE c03s04b01x00p01n01i00613arch OF c03s04b01x00p01n01i00613ent IS constant C1 : boolean := true; constant C4 : severity_level := note; constant C5 : integer := 3; constant C6 : real := 3.0; constant C7 : time := 3 ns; constant C8 : natural := 3; constant C9 : positive := 3; type boolean_cons_vector is array (15 downto 0) of boolean; type severity_level_cons_vector is array (15 downto 0) of severity_level; type integer_cons_vector is array (15 downto 0) of integer; type real_cons_vector is array (15 downto 0) of real; type time_cons_vector is array (15 downto 0) of time; type natural_cons_vector is array (15 downto 0) of natural; type positive_cons_vector is array (15 downto 0) of positive; constant C19 : boolean_cons_vector := (others => C1); constant C20 : severity_level_cons_vector := (others => C4); constant C21 : integer_cons_vector := (others => C5); constant C22 : real_cons_vector := (others => C6); constant C23 : time_cons_vector := (others => C7); constant C24 : natural_cons_vector := (others => C8); constant C25 : positive_cons_vector := (others => C9); type record_cons_array is record a:boolean_cons_vector; b:severity_level_cons_vector; c:integer_cons_vector; d:real_cons_vector; e:time_cons_vector; f:natural_cons_vector; g:positive_cons_vector; end record; type record_cons_array_file is file of record_cons_array; constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25); signal k : integer := 0; BEGIN TESTING: PROCESS file filein : record_cons_array_file open read_mode is "iofile.34"; variable v : record_cons_array; BEGIN for i in 1 to 100 loop assert(endfile(filein) = false) report"end of file reached before expected"; read(filein,v); if (v /= C27) then k <= 1; end if; end loop; wait for 1 ns; assert NOT(k = 0) report "PASSED TEST: c03s04b01x00p01n01i00613" severity NOTE; assert (k = 0) report "**FAILED TEST: c03s04b01x00p01n01i00613 - File reading operation (record_cons_array file type) failed." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p01n01i00613arch;
library IEEE; use ieee.std_logic_1164.all; entity pw_process is port ( --length : in natural; clk : in std_logic; pwd : out string ); end pw_process; architecture arch_pw_process of pw_process is component pwd_string port ( push_pop : in std_logic; char : in character; clk : in std_logic; enable: in std_logic; pwd : out string ); end component; component recursive_stack port ( length_in : in natural; length_out : out natural; index_in : in natural; index_out : out natural; enable : in std_logic; push_pop: in std_logic; clk : in std_logic ); end component; component vowels port ( length_in : in natural; length_out : out natural; enable : in STD_LOGIC; reset : in std_logic; load_index : in natural; current_index: out natural; clk : in std_logic; data : out character; valid : out std_logic := '0' ); end component; type DenyFlags is (F_CONSONANT, F_VOWEL, F_DIPTHONG, F_NOT_FIRST, F_DIGIT, F_FIRST, F_UPPERS); -- signal valid : std_logic; signal char : character; signal length, length_addr : natural := 0; signal load_index, current_index : natural := 0; signal next_char : std_logic; signal stack_register : std_logic := '0'; begin final_pwd : pwd_string port map ( push_pop => valid, char => char, clk => clk, enable => '1', pwd => pwd ); stack : recursive_stack port map ( enable => stack_register, push_pop => next_char, length_in => length_addr, length_out => length, index_in => current_index, index_out => load_index, clk => clk ); vowel : vowels port map ( length_in => length, length_out => length_addr, enable => '1', reset => next_char, load_index => load_index, current_index => current_index, clk => clk, data => char, valid => valid ); process(clk) begin if rising_edge(clk) then if valid = '1' and length_addr < 4 then next_char <= '1'; else next_char <= '0'; end if; if length_addr >= 4 and valid = '1' then stack_register <= '0'; else stack_register <= '1'; end if; end if; end process; end arch_pw_process;
---------------------------------------------------------------------------------- -- Felix Winterstein, Imperial College London -- -- Module Name: centre_buffer_mgmt - Behavioral -- -- Revision 1.01 -- Additional Comments: distributed under a BSD license, see LICENSE.txt -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.math_real.all; use work.lloyds_algorithm_pkg.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity centre_buffer_mgmt is port ( clk : in std_logic; sclr : in std_logic; init : in std_logic; addr_in_init : in centre_index_type; nd : in std_logic; request_rdo : in std_logic; addr_in : in centre_index_type; wgtCent_in : in data_type_ext; sum_sq_in : in coord_type_ext; count_in : in coord_type; valid : out std_logic; wgtCent_out : out data_type_ext; sum_sq_out : out coord_type_ext; count_out : out coord_type ); end centre_buffer_mgmt; architecture Behavioral of centre_buffer_mgmt is constant DIM : integer := D; constant LAT : integer := 2; type state_type is (read, write); component centre_buffer_dist port ( a : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(K_MAX))))-1 DOWNTO 0); dpra : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(K_MAX))))-1 DOWNTO 0); d : IN STD_LOGIC_VECTOR(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIMCOORD_BITWIDTH_EXT-1 DOWNTO 0); clk : IN STD_LOGIC; we : IN STD_LOGIC; qdpo_srst : IN STD_LOGIC; qdpo : OUT STD_LOGIC_VECTOR(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIMCOORD_BITWIDTH_EXT-1 DOWNTO 0) ); end component; signal state : state_type; signal tmp_we : std_logic; signal we_reg : std_logic; signal rdo_delay : std_logic_vector(0 to LAT-1); signal wr_addr_in_reg : centre_index_type; signal rd_addr_in_reg : centre_index_type; signal wgtCent_reg : data_type_ext; signal sum_sq_reg : coord_type_ext; signal count_reg : coord_type; signal tmp_dina : std_logic_vector(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIMCOORD_BITWIDTH_EXT-1 downto 0); signal tmp_doutb : std_logic_vector(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIMCOORD_BITWIDTH_EXT-1 downto 0); signal tmp_wgtCent_int : data_type_ext; signal tmp_sum_sq_int : coord_type_ext; signal tmp_count_int : coord_type; signal tmp_wgtCent_int_sum : data_type_ext; signal tmp_sum_sq_int_sum : coord_type_ext; signal tmp_count_int_sum : coord_type; begin fsm_proc : process(clk) begin if rising_edge(clk) then if sclr = '1' then state <= read; elsif state = read AND nd = '1' then state <= write; elsif state = write then state <= read; end if; end if; end process fsm_proc; tmp_we <= '1' WHEN state = write ELSE '0'; reg_proc : process(clk) begin if rising_edge(clk) then if init = '1' then wr_addr_in_reg <= addr_in_init; rd_addr_in_reg <= addr_in; for I in 0 to D-1 loop wgtCent_reg(I) <= (others => '0'); end loop; sum_sq_reg <= (others => '0'); count_reg <= (others => '0'); elsif nd = '1' OR request_rdo='1' then wr_addr_in_reg <= addr_in; rd_addr_in_reg <= addr_in; --addr_in_reg <= addr_in; wgtCent_reg <= wgtCent_in; sum_sq_reg <= sum_sq_in; count_reg <= count_in; end if; end if; end process reg_proc; reg_proc2 : process(clk) begin if rising_edge(clk) then if sclr = '1' then we_reg <= '0'; rdo_delay <= (others => '0'); else we_reg <= tmp_we OR init; rdo_delay(0) <= request_rdo; rdo_delay(1 to LAT-1) <= rdo_delay(0 to LAT-2); end if; end if; end process reg_proc2; centre_buffer_dist_inst : centre_buffer_dist port map ( a => std_logic_vector(wr_addr_in_reg(integer(ceil(log2(real(K_MAX))))-1 downto 0)), dpra => std_logic_vector(rd_addr_in_reg(integer(ceil(log2(real(K_MAX))))-1 downto 0)), d => tmp_dina, clk => clk, we => we_reg, qdpo_srst => init, qdpo => tmp_doutb ); G1: for I in 0 to D-1 generate tmp_wgtCent_int(I) <= tmp_doutb((I+1)COORD_BITWIDTH_EXT-1 downto ICOORD_BITWIDTH_EXT); end generate G1; tmp_sum_sq_int <= tmp_doutb(1COORD_BITWIDTH_EXT+DCOORD_BITWIDTH_EXT-1 downto 0COORD_BITWIDTH_EXT+DCOORD_BITWIDTH_EXT); tmp_count_int <= tmp_doutb(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DCOORD_BITWIDTH_EXT-1 downto 0+COORD_BITWIDTH_EXT+DCOORD_BITWIDTH_EXT); G2: for I in 0 to D-1 generate tmp_wgtCent_int_sum(I) <= std_logic_vector(signed(tmp_wgtCent_int(I)) + signed(wgtCent_reg(I))); tmp_dina((I+1)COORD_BITWIDTH_EXT-1 downto ICOORD_BITWIDTH_EXT) <= (tmp_wgtCent_int_sum(I)); end generate G2; tmp_sum_sq_int_sum <= std_logic_vector(signed(tmp_sum_sq_int) + signed(sum_sq_reg)); tmp_dina(1COORD_BITWIDTH_EXT+DCOORD_BITWIDTH_EXT-1 downto 0COORD_BITWIDTH_EXT+DCOORD_BITWIDTH_EXT) <= tmp_sum_sq_int_sum; tmp_count_int_sum <= std_logic_vector(signed(tmp_count_int) + signed(count_reg)); tmp_dina(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DCOORD_BITWIDTH_EXT-1 downto 0+COORD_BITWIDTH_EXT+DCOORD_BITWIDTH_EXT) <= tmp_count_int_sum; valid <= rdo_delay(LAT-1); wgtCent_out <= tmp_wgtCent_int; sum_sq_out <= tmp_sum_sq_int; count_out <= tmp_count_int; end Behavioral;
library ieee; use ieee.std_logic_1164.all; entity var6_tb is end var6_tb; architecture TB_ARCHITECTURE of var6_tb is component var6 port( W : in STD_LOGIC; X : in STD_LOGIC; Y : in STD_LOGIC; Z : in STD_LOGIC; F : out STD_LOGIC); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal W : STD_LOGIC; signal X : STD_LOGIC; signal Y : STD_LOGIC; signal Z : STD_LOGIC; -- Observed signals - signals mapped to the output ports of tested entity signal F, F1 : STD_LOGIC; signal error : std_logic; begin -- Unit Under Test port map UUT : var6 port map ( W => W, X => X, Y => Y, Z => Z, F => F ); UUT2 : var6 port map ( W => W, X => X, Y => Y, Z => Z, F => F1 ); --Below VHDL code is an inserted .\compile\task.vhs --User can modify it .... STIMULUS: process begin -- of stimulus process --wait for <time to next event>; -- <current time> W <= '0'; Y <= '0'; Z <= '0'; X <= '0'; wait for 50 ns; --0 fs X <= '1'; wait for 50 ns; --50 ns Y <= '1'; X <= '0'; wait for 50 ns; --100 ns X <= '1'; wait for 50 ns; --150 ns Y <= '0'; Z <= '1'; X <= '0'; wait for 50 ns; --200 ns X <= '1'; wait for 50 ns; --250 ns Y <= '1'; X <= '0'; wait for 50 ns; --300 ns X <= '1'; wait for 50 ns; --350 ns W <= '1'; Y <= '0'; Z <= '0'; X <= '0'; wait for 50 ns; --400 ns X <= '1'; wait for 50 ns; --450 ns Y <= '1'; X <= '0'; wait for 50 ns; --500 ns X <= '1'; wait for 50 ns; --550 ns Y <= '0'; Z <= '1'; X <= '0'; wait for 50 ns; --600 ns X <= '1'; wait for 50 ns; --650 ns Y <= '1'; X <= '0'; wait for 50 ns; --700 ns X <= '1'; wait for 50 ns; --750 ns W <= '0'; Y <= '0'; Z <= '0'; X <= '0'; -- end of stimulus events 800 ns wait; end process; -- end of stimulus process error <= F1 xor F; -- Add your stimulus here ... end TB_ARCHITECTURE;
-- SIMON 64/128 -- key schedule test bench -- -- @Author: Jos Wetzels -- @Author: Wouter Bokslag -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.NUMERIC_STD.ALL; ENTITY tb_keyschedule IS END tb_keyschedule; ARCHITECTURE behavior OF tb_keyschedule IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT key_schedule port ( r : in std_logic_vector(7 downto 0); k_0 : in std_logic_vector(31 downto 0); k_1 : in std_logic_vector(31 downto 0); k_3 : in std_logic_vector(31 downto 0); subkey_out : out std_logic_vector(31 downto 0)); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal r : std_logic_vector(7 downto 0); -- round index type key_t is array (0 to 3) of std_logic_vector(31 downto 0); signal key_s : key_t; -- k0..3 --Outputs signal subkey_out : std_logic_vector(31 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; signal clk_generator_finish : STD_LOGIC := '0'; signal test_bench_finish : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: key_schedule PORT MAP ( r => r, k_0 => key_s(0), k_1 => key_s(1), k_3 => key_s(3), subkey_out => subkey_out ); -- Clock process definitions clock : process begin while ( clk_generator_finish /= '1') loop clk <= not clk; wait for clk_period/2; end loop; wait; end process; -- Stimulus process stim_proc: process begin wait for clk_period/2 + 10*clk_period; -- SIMON 64/128 test vectors key_s(0) <= X"03020100"; key_s(1) <= X"0b0a0908"; key_s(2) <= X"13121110"; key_s(3) <= X"1b1a1918"; r <= X"00"; wait for clk_period; assert subkey_out = X"70a011c3" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"b770ec49" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"57e3e835" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d397bc42" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"94dcf81f" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"bf4b5f18" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"8e5dabb9" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"dbf4a863" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"cd0c28fc" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"5cb69911" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"79f112a5" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"77205863" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"99880c12" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"1ce97c58" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"c8ed2145" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"b800dbb8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"e86a2756" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"7c06d4dd" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"ab52df0a" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"247f66a8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"53587ca6" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d25c13f1" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"4583b64b" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"7d9c960d" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"efbfc2f3" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"89ed8513" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"308dfc4e" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"bf1a2a36" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"e1499d70" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"4ce4d2ff" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"32b7ebef" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"c47505c1" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d0e929e8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"8fe484b9" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"42054bee" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"af77bae2" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"18199c02" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"719e3f1c" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"0c1cf793" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"15df4696" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; test_bench_finish <= '1'; clk_generator_finish <= '1'; wait for clk_period; wait; end process; END;
-- SIMON 64/128 -- key schedule test bench -- -- @Author: Jos Wetzels -- @Author: Wouter Bokslag -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.NUMERIC_STD.ALL; ENTITY tb_keyschedule IS END tb_keyschedule; ARCHITECTURE behavior OF tb_keyschedule IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT key_schedule port ( r : in std_logic_vector(7 downto 0); k_0 : in std_logic_vector(31 downto 0); k_1 : in std_logic_vector(31 downto 0); k_3 : in std_logic_vector(31 downto 0); subkey_out : out std_logic_vector(31 downto 0)); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal r : std_logic_vector(7 downto 0); -- round index type key_t is array (0 to 3) of std_logic_vector(31 downto 0); signal key_s : key_t; -- k0..3 --Outputs signal subkey_out : std_logic_vector(31 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; signal clk_generator_finish : STD_LOGIC := '0'; signal test_bench_finish : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: key_schedule PORT MAP ( r => r, k_0 => key_s(0), k_1 => key_s(1), k_3 => key_s(3), subkey_out => subkey_out ); -- Clock process definitions clock : process begin while ( clk_generator_finish /= '1') loop clk <= not clk; wait for clk_period/2; end loop; wait; end process; -- Stimulus process stim_proc: process begin wait for clk_period/2 + 10*clk_period; -- SIMON 64/128 test vectors key_s(0) <= X"03020100"; key_s(1) <= X"0b0a0908"; key_s(2) <= X"13121110"; key_s(3) <= X"1b1a1918"; r <= X"00"; wait for clk_period; assert subkey_out = X"70a011c3" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"b770ec49" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"57e3e835" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d397bc42" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"94dcf81f" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"bf4b5f18" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"8e5dabb9" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"dbf4a863" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"cd0c28fc" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"5cb69911" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"79f112a5" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"77205863" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"99880c12" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"1ce97c58" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"c8ed2145" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"b800dbb8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"e86a2756" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"7c06d4dd" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"ab52df0a" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"247f66a8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"53587ca6" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d25c13f1" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"4583b64b" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"7d9c960d" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"efbfc2f3" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"89ed8513" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"308dfc4e" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"bf1a2a36" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"e1499d70" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"4ce4d2ff" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"32b7ebef" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"c47505c1" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d0e929e8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"8fe484b9" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"42054bee" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"af77bae2" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"18199c02" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"719e3f1c" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"0c1cf793" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"15df4696" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; test_bench_finish <= '1'; clk_generator_finish <= '1'; wait for clk_period; wait; end process; END;
-- SIMON 64/128 -- key schedule test bench -- -- @Author: Jos Wetzels -- @Author: Wouter Bokslag -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.NUMERIC_STD.ALL; ENTITY tb_keyschedule IS END tb_keyschedule; ARCHITECTURE behavior OF tb_keyschedule IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT key_schedule port ( r : in std_logic_vector(7 downto 0); k_0 : in std_logic_vector(31 downto 0); k_1 : in std_logic_vector(31 downto 0); k_3 : in std_logic_vector(31 downto 0); subkey_out : out std_logic_vector(31 downto 0)); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal r : std_logic_vector(7 downto 0); -- round index type key_t is array (0 to 3) of std_logic_vector(31 downto 0); signal key_s : key_t; -- k0..3 --Outputs signal subkey_out : std_logic_vector(31 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; signal clk_generator_finish : STD_LOGIC := '0'; signal test_bench_finish : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: key_schedule PORT MAP ( r => r, k_0 => key_s(0), k_1 => key_s(1), k_3 => key_s(3), subkey_out => subkey_out ); -- Clock process definitions clock : process begin while ( clk_generator_finish /= '1') loop clk <= not clk; wait for clk_period/2; end loop; wait; end process; -- Stimulus process stim_proc: process begin wait for clk_period/2 + 10*clk_period; -- SIMON 64/128 test vectors key_s(0) <= X"03020100"; key_s(1) <= X"0b0a0908"; key_s(2) <= X"13121110"; key_s(3) <= X"1b1a1918"; r <= X"00"; wait for clk_period; assert subkey_out = X"70a011c3" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"b770ec49" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"57e3e835" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d397bc42" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"94dcf81f" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"bf4b5f18" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"8e5dabb9" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"dbf4a863" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"cd0c28fc" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"5cb69911" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"79f112a5" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"77205863" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"99880c12" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"1ce97c58" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"c8ed2145" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"b800dbb8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"e86a2756" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"7c06d4dd" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"ab52df0a" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"247f66a8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"53587ca6" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d25c13f1" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"4583b64b" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"7d9c960d" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"efbfc2f3" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"89ed8513" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"308dfc4e" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"bf1a2a36" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"e1499d70" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"4ce4d2ff" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"32b7ebef" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"c47505c1" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d0e929e8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"8fe484b9" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"42054bee" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"af77bae2" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"18199c02" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"719e3f1c" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"0c1cf793" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"15df4696" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; test_bench_finish <= '1'; clk_generator_finish <= '1'; wait for clk_period; wait; end process; END;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:15:50 10/19/2016 -- Design Name: -- Module Name: Register - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Internal_Register is port( clk : IN STD_LOGIC; -- clock input register_input : IN STD_LOGIC_VECTOR (7 downto 0); -- input data register_data : INOUT STD_LOGIC_VECTOR (7 downto 0); -- internal data register_output : OUT STD_LOGIC_VECTOR (7 downto 0); -- output data register_command : IN STD_LOGIC ); end Internal_Register; architecture Behavioral of Internal_Register is begin REGISTER_PROCESS : process(clk) begin if clk= '1' and clk'event then if register_command = '1' then register_data <= register_input; -- reading from bus elsif register_command = '0' then register_output <= register_data; -- writing to bus end if; end if; end process; end Behavioral;
--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg --Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: -- --1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -- --2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the --documentation and/or other materials provided with the distribution. -- --3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this --software without specific prior written permission. -- --THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS --BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT --LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Library IEEE; Use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_MISC.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; Use IEEE.NUMERIC_STD.all; Use work.all; Entity Keyboard is Port ( Row_Input : in STD_LOGIC_VECTOR (3 downto 0); Col_Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '1'); Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); RDY : out STD_LOGIC := '0'; CLK : in STD_LOGIC; ARESETN : in STD_LOGIC ); end Keyboard; --This is a translator for the Keypad v3.0 to hex --To be connected to the outside world. First it debounces the signal. --It's to be connected to a 16-button keyboard with pins 4 rows and 4 columns --To parse the button presses this module first drives all col-pins with high value. --When a high value is detected on any of the input row-pins it scans over the columns --one by one (with 500 cycles delay) and detects high values on the row pins. If only one --button was pressed it's parsed as a vector defined in the case-statement below, and --the RDY-bit is set high to signal valid input. --Any parsing besides the accepted ones gives output 0 and the RDY-bit to 0 architecture Behaviour of Keyboard is signal input_debounced : STD_LOGIC_VECTOR (3 downto 0); signal counter : unsigned (31 downto 0) := (others => '0'); signal translated : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; Begin Process (CLK) Begin if rising_edge(CLK) then input_debounced <= Row_Input; IF ARESETN = '1' THEN if input_debounced = "0000" and counter = "0000" then --counter <= "0000"; RDY <= '0'; translated <= (others => '0'); else if counter = to_unsigned(0, 32) then Col_Output <= "0001"; elsif counter = to_unsigned(500, 32) then --Wait for 500 cycles fom previous step if input_debounced /= "0000" then translated <= STD_LOGIC_VECTOR(input_debounced) & "0001"; end if; Col_Output <= "0010"; elsif counter = to_unsigned(1000, 32) then--Wait for 500 cycles fom previous step if input_debounced /= "0000" then translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "0010"; end if; Col_Output <= "0100"; elsif counter = to_unsigned(1500, 32) then --Wait for 500 cycles fom previous step if input_debounced /= "0000" then translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "0100"; end if; Col_Output <= "1000"; elsif counter = to_unsigned(2000, 32) then --Wait for 500 cycles fom previous step if input_debounced /= "0000" then translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "1000"; end if; Col_Output <= "1111"; else --do nothing end if; if counter /= to_unsigned(4000, 32) then --Wait for 2000 cycles fom previous step counter <= counter + 1; elsif input_debounced = "0000" then --Wait for release of button counter <= (others => '0'); -- --Case for translations. In order of magnitude. -- Input is in the format 7 downto 4 row, 3 downto 0 col. -- I.e. the vector 0100 0001 is row 3, col 1 Translate: case translated is when "10000010" => RDY <= '1'; --0 Output <= "0000"; when "00010001" => RDY <= '1'; --1 Output <= "0001"; when "00010010" => RDY <= '1'; --2 Output <= "0010"; when "00010100" => RDY <= '1'; --3 Output <= "0011"; when "00100001" => RDY <= '1'; --4 Output <= "0100"; when "00100010" => RDY <= '1'; --5 Output <= "0101"; when "00100100" => RDY <= '1'; --6 Output <= "0110"; when "01000001" => RDY <= '1'; --7 Output <= "0111"; when "01000010" => RDY <= '1'; --8 Output <= "1000"; when "01000100" => RDY <= '1'; --9 Output <= "1001"; when "00011000" => RDY <= '1'; --A Output <= "1010"; when "00101000" => RDY <= '1'; --B Output <= "1011"; when "01001000" => RDY <= '1'; --C Output <= "1100"; when "10001000" => RDY <= '1'; --D Output <= "1101"; when "10000100" => RDY <= '1'; --E Output <= "1110"; when "10000001" => RDY <= '1'; --F Output <= "1111"; when others => RDY <= '0'; --Others Output <= "0000"; end case Translate; end if; end if; elsif ARESETN = '0' then RDY <= '0'; Output <= (others => '0'); --Reset translated <= (others => '0'); counter <= (others => '0'); END IF; end if; end process; end Behaviour;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block jxM21pSCZdk9+AekqzDuMmVlqxFHUwhCmWakT9sHniEynOxa2xIO43zxjPKn3LIShvNjKq+SUugR VjFCBLrkOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ipViEhKlvcdwsr3ezE3VseQjO/kCM0pdOs1nNzdH+1pIkicLlbLbHdLkMwJgNcY41nRZKDvJvNb5 2o640b/uamdoao7lHckZyA/b9hKmu4NQlDpUOr585ne6W8EeXRKbVRFlcIGi/UyklNaey+daKr3t azLvUsMLc9t0W5Lo6bw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block jxM21pSCZdk9+AekqzDuMmVlqxFHUwhCmWakT9sHniEynOxa2xIO43zxjPKn3LIShvNjKq+SUugR VjFCBLrkOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ipViEhKlvcdwsr3ezE3VseQjO/kCM0pdOs1nNzdH+1pIkicLlbLbHdLkMwJgNcY41nRZKDvJvNb5 2o640b/uamdoao7lHckZyA/b9hKmu4NQlDpUOr585ne6W8EeXRKbVRFlcIGi/UyklNaey+daKr3t azLvUsMLc9t0W5Lo6bw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block FLYJUpfsAKpD8kEjApkfbbLN4CE4391iJQyoKaQrJDgskBS8wrXvpHjsK11VGOO2O6z7PTuHfjm4 +rlUyKh0GwMvTZVzCIFrKtkrOmFrK80My0jltDwA7T0o+eRi8zJ891THrerexurnqtwcCscxuY8/ caZcUYJiY0uEZGflvdv4eVJwTO1DznGjwYUQ8N5tVm8w32ZqP8nh73Rn2Jpj5YzHMo6+BzyMIOHn paou15p2P8Tlw5S00HEQRsdb1zN/qQMb4EhsSdSuQUszUf73ESkHtbf6XdhawWIsbhDPYF19BcF7 wltclhF3kzDY/uVrU9zSHD/VWniLlFNhyY0sAg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block EAEQSpuW51cENyn40qmndY1WzBowAVjd0E3ALGYwBsECzF49IVI76D4wHbc2e4sUjHrPmzmkHPF2 B0iblxwK1Xc9rkyv5L5bvcRVm9mU5Zpzr4uTjpocaQ1n6YkZO9ZERJtMNw2Wt/UFLID4ohFEV05x QOjsJIO31Zaaye6Lz4o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block toScMir1dWiP2ET8ayX27hRWZNuLrGtLa22BZsKe2FVcpkYPz5618smUZyaC2gnCHkHBH3RNrF9U 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block jxM21pSCZdk9+AekqzDuMmVlqxFHUwhCmWakT9sHniEynOxa2xIO43zxjPKn3LIShvNjKq+SUugR VjFCBLrkOw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block ipViEhKlvcdwsr3ezE3VseQjO/kCM0pdOs1nNzdH+1pIkicLlbLbHdLkMwJgNcY41nRZKDvJvNb5 2o640b/uamdoao7lHckZyA/b9hKmu4NQlDpUOr585ne6W8EeXRKbVRFlcIGi/UyklNaey+daKr3t azLvUsMLc9t0W5Lo6bw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block FLYJUpfsAKpD8kEjApkfbbLN4CE4391iJQyoKaQrJDgskBS8wrXvpHjsK11VGOO2O6z7PTuHfjm4 +rlUyKh0GwMvTZVzCIFrKtkrOmFrK80My0jltDwA7T0o+eRi8zJ891THrerexurnqtwcCscxuY8/ caZcUYJiY0uEZGflvdv4eVJwTO1DznGjwYUQ8N5tVm8w32ZqP8nh73Rn2Jpj5YzHMo6+BzyMIOHn paou15p2P8Tlw5S00HEQRsdb1zN/qQMb4EhsSdSuQUszUf73ESkHtbf6XdhawWIsbhDPYF19BcF7 wltclhF3kzDY/uVrU9zSHD/VWniLlFNhyY0sAg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block EAEQSpuW51cENyn40qmndY1WzBowAVjd0E3ALGYwBsECzF49IVI76D4wHbc2e4sUjHrPmzmkHPF2 B0iblxwK1Xc9rkyv5L5bvcRVm9mU5Zpzr4uTjpocaQ1n6YkZO9ZERJtMNw2Wt/UFLID4ohFEV05x QOjsJIO31Zaaye6Lz4o= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block toScMir1dWiP2ET8ayX27hRWZNuLrGtLa22BZsKe2FVcpkYPz5618smUZyaC2gnCHkHBH3RNrF9U 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-------------------------------------------------------------------------- -- -- Copyright (C) 1993, Peter J. Ashenden -- Mail: Dept. Computer Science -- University of Adelaide, SA 5005, Australia -- e-mail: [email protected] -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 1, or (at your option) -- any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -- -------------------------------------------------------------------------- -- -- $RCSfile: dlx_test_cache.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 22:16:15 $ -- -------------------------------------------------------------------------- -- -- Configuration of test bench for DLX and cache, -- using behavioural architectures. -- configuration dlx_test_cache of dlx_test is for bench_cache use work.cache_types.all; for cg : clock_gen use entity work.clock_gen(behaviour) generic map (Tpw => 8 ns, Tps => 2 ns); end for; for mem : memory use entity work.memory(behaviour) generic map (mem_size => 65536, Tac1 => 95 ns, Tacb => 35 ns, Tpd_clk_out => 2 ns); end for; for the_cache : cache use entity work.cache(behaviour) generic map (cache_size => 4096, line_size => 16, associativity => 2, write_strategy => write_through, Tpd_clk_out => 2 ns); end for; for cpu_cache_monitor : dlx_bus_monitor use entity work.dlx_bus_monitor(behaviour) generic map (enable => true, verbose => false, tag => "cpu cache monitor"); end for; for cache_mem_monitor : dlx_bus_monitor use entity work.dlx_bus_monitor(behaviour) generic map (enable => true, verbose => false, tag => "cache mem monitor"); end for; for proc : dlx use entity work.dlx(behaviour) generic map (Tpd_clk_out => 2 ns, debug => false, tag => "proc"); end for; end for; end dlx_test_cache;
-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: M9K_RAM.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ********************************************************** -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 13.1.0 Build 162 10/23/2013 SJ Web Edition -- ********************************************************** --Copyright (C) 1991-2013 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY M9K_RAM IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; init_phase : IN STD_LOGIC_VECTOR(3 DOWNTO 0); input : IN STD_LOGIC_VECTOR(15 DOWNTO 0); data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); rden : IN STD_LOGIC := '1'; wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END M9K_RAM; ARCHITECTURE SYN OF m9k_ram IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); signal a : std_logic_vector(7 downto 0); signal d : std_logic_vector(15 downto 0); signal w : std_logic; BEGIN a <= X"00" when (init_phase = X"1") else address; d <= input when (init_phase = X"1") else data; w <= '1' when (init_phase = X"1") else wren; q <= sub_wire0(15 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", init_file => "../content.mif", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", maximum_depth => 256, numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE", ram_block_type => "M9K", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 16, width_byteena_a => 1 ) PORT MAP ( address_a => a, clock0 => clock, data_a => d, wren_a => w, rden_a => rden, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256" -- Retrieval info: PRIVATE: MIFfilename STRING "../content.mif" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "16" -- Retrieval info: PRIVATE: rden NUMERIC "1" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INIT_FILE STRING "../content.mif" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "256" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" -- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" -- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 -- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM_inst.vhd TRUE -- Retrieval info: LIB_FILE: altera_mf
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.ALL; use IEEE.numeric_std.all; use work.SearchModule_pkg.ALL; entity SearchModuleTB is end SearchModuleTB; architecture Behavioral of SearchModuleTB is constant DATA_WIDTH_A_USAR: integer := 32; constant ADDR_WIDTH_A_USAR: integer := 10; --type arrayOfADDR_WIDTH is array ((ADDR_WIDTH_A_USAR-1) downto 0) of std_logic_vector((ADDR_WIDTH_A_USAR-1) downto 0); signal clk : std_logic; signal search : std_logic; signal dataToCompare : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0); signal operationID : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0); signal porta_wr : std_logic; signal porta_waddr : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0); signal porta_din : std_logic_vector( (DATA_WIDTH_A_USAR-1) downto 0); signal searchFinished : std_logic; signal searchresult : std_logic; signal resultIndex : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0); signal result_operationID : std_logic_vector( (DATA_WIDTH_A_USAR-1) downto 0); signal internalResultFinished_dbg : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0); signal resultIndexs_dbg : arrayOfADDR_WIDTH((ADDR_WIDTH_A_USAR-1) downto 0); signal dataFound_dbg : arrayUOfDATA_WIDTH((ADDR_WIDTH_A_USAR-1) downto 0); signal errorDetected : std_logic := '0'; constant clk_period : time := 10 ns; begin uut: entity work.SearchModule generic map ( DATA_WIDTH => DATA_WIDTH_A_USAR, ADDR_WIDTH => ADDR_WIDTH_A_USAR ) port map ( clk => clk, search => search, dataToCompare => dataToCompare, operationID => operationID, porta_wr => porta_wr, porta_waddr => porta_waddr, porta_din => porta_din, searchFinished => searchFinished, searchresult => searchresult, resultIndex => resultIndex, result_operationID => result_operationID, internalResultFinished_dbg => internalResultFinished_dbg, resultIndexs_dbg => resultIndexs_dbg, dataFound_dbg => dataFound_dbg ); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; test : process variable readWriteCounter : integer := 0; variable dataToWrite : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := ( others => '0'); variable addrToWrite : std_logic_vector((ADDR_WIDTH_A_USAR-1) downto 0) := ( others => '0'); begin -- Primero grabar los datos en la memoria search <= '0'; dataToCompare <= (others => '0'); operationID <= (others => '0'); dataToWrite := x"10000000"; porta_wr <= '0'; porta_waddr <= (others => '0'); porta_din <= (others => '0'); wait for 10clk_period; porta_wr <= '0'; porta_waddr <= addrToWrite; porta_din <= dataToWrite; wait for clk_period; while readWriteCounter < (2ADDR_WIDTH_A_USAR) loop porta_wr <= '1'; porta_waddr <= addrToWrite; porta_din <= dataToWrite; wait for clk_period; porta_wr <= '0'; wait for clk_period; dataToWrite := dataToWrite+1; addrToWrite := addrToWrite+1; readWriteCounter := readWriteCounter+1; end loop; porta_wr <= '0'; wait for clk_period; search <= '0'; dataToWrite := x"10000005"; wait for clk_period; wait for clk_period; dataToCompare <= dataToWrite; search <= '0'; wait for clk_period; dataToWrite := x"10000006"; dataToCompare <= dataToWrite; wait for clk_period; search <= '0'; wait for clk_period; readWriteCounter := 0; dataToWrite := x"10000000"; addrToWrite := ( others => '0' ); while readWriteCounter < (2ADDR_WIDTH_A_USAR) loop dataToCompare <= dataToWrite; search <= '1'; wait for clk_period; search <= '0'; wait for clk_period; dataToWrite := dataToWrite+1; addrToWrite := addrToWrite+1; readWriteCounter := readWriteCounter+1; end loop; search <= '0'; wait for clk_period; wait; end process; verification: process variable verifCounter : integer := 0; variable dataToWrite : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := x"10000000"; variable verifDataCounter : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := (others => '0'); begin errorDetected <= '0'; if( rising_edge(clk) ) then if( verifCounter >= (2*ADDR_WIDTH_A_USAR) ) then errorDetected <= '0'; else if (searchFinished = '1') then if( (verifDataCounter/=resultIndex) ) then errorDetected <= '1'; else errorDetected <= '0'; end if; verifCounter := verifCounter+1; dataToWrite := dataToWrite+1; verifDataCounter := verifDataCounter+1; else errorDetected <= '0'; end if; end if; end if; wait; end process verification; end Behavioral;
-- $Id: serport_uart_rxtx.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]> -- ------------------------------------------------------------------------------ -- Module Name: serport_uart_rxtx - syn -- Description: serial port UART - transmitter + receiver -- -- Dependencies: serport_uart_rx -- serport_uart_tx -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic -- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2007-06-24 60 1.0 Initial version ------------------------------------------------------------------------------ -- NOTE: for test bench usage a copy of all serport_* entities, with _tb -- !!!! appended to the name, has been created in the /tb sub folder. -- !!!! Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.serportlib.all; entity serport_uart_rxtx is -- serial port uart: rx+tx combo generic ( CDWIDTH : positive := 13); -- clk divider width port ( CLK : in slbit; -- clock RESET : in slbit; -- reset CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting RXSD : in slbit; -- receive serial data (uart view) RXDATA : out slv8; -- receiver data out RXVAL : out slbit; -- receiver data valid RXERR : out slbit; -- receiver data error (frame error) RXACT : out slbit; -- receiver active TXSD : out slbit; -- transmit serial data (uart view) TXDATA : in slv8; -- transmit data in TXENA : in slbit; -- transmit data enable TXBUSY : out slbit -- transmit busy ); end serport_uart_rxtx; architecture syn of serport_uart_rxtx is begin RX : serport_uart_rx generic map ( CDWIDTH => CDWIDTH) port map ( CLK => CLK, RESET => RESET, CLKDIV => CLKDIV, RXSD => RXSD, RXDATA => RXDATA, RXVAL => RXVAL, RXERR => RXERR, RXACT => RXACT ); TX : serport_uart_tx generic map ( CDWIDTH => CDWIDTH) port map ( CLK => CLK, RESET => RESET, CLKDIV => CLKDIV, TXSD => TXSD, TXDATA => TXDATA, TXENA => TXENA, TXBUSY => TXBUSY ); end syn;
entity tb_asgn09 is end tb_asgn09; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_asgn09 is signal a, b, c, d : std_logic_vector (1 downto 0); signal sel : std_logic_vector(1 downto 0); signal o : std_logic_vector (3 downto 0); begin dut: entity work.asgn09 port map (a, b, c, d, sel, o); process begin a <= "10"; b <= "01"; c <= "00"; d <= "11"; sel <= "00"; wait for 1 ns; assert o = "1110" severity failure; sel <= "01"; wait for 1 ns; assert o = "1101" severity failure; sel <= "10"; wait for 1 ns; assert o = "1100" severity failure; sel <= "11"; wait for 1 ns; assert o = "1111" severity failure; wait; end process; end behav;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Memoria is port( clk, lectura_escritura, habilitador: in STD_LOGIC; direccion: in STD_LOGIC_VECTOR(3 downto 0); dato_entrada: in STD_LOGIC_VECTOR(2 downto 0); dato_salida: out STD_LOGIC_VECTOR(2 downto 0)); end Memoria; architecture Behavioral of Memoria is constant bits_direccion : integer := 4; constant bits_dato : integer := 3; type Block_ram is array(2**bits_direccion-1 downto 0) of STD_LOGIC_VECTOR(bits_dato-1 downto 0); signal RAM: Block_ram; begin process(clk) begin if clk'event and clk = '1' then if habilitador = '1' then if lectura_escritura = '1' then RAM(conv_integer(direccion)) <= dato_entrada; else dato_salida <= RAM(conv_integer(direccion)); end if; end if; end if; end process; end Behavioral;
-- NEED RESULT: ARCH00382.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P2: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P3: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P4: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P5: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P6: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P7: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P8: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P9: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P10: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P11: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P12: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P13: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P14: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P15: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P16: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P17: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P17: Inertial transactions completed entirely passed -- NEED RESULT: P16: Inertial transactions completed entirely passed -- NEED RESULT: P15: Inertial transactions completed entirely passed -- NEED RESULT: P14: Inertial transactions completed entirely passed -- NEED RESULT: P13: Inertial transactions completed entirely passed -- NEED RESULT: P12: Inertial transactions completed entirely passed -- NEED RESULT: P11: Inertial transactions completed entirely passed -- NEED RESULT: P10: Inertial transactions completed entirely passed -- NEED RESULT: P9: Inertial transactions completed entirely passed -- NEED RESULT: P8: Inertial transactions completed entirely passed -- NEED RESULT: P7: Inertial transactions completed entirely passed -- NEED RESULT: P6: Inertial transactions completed entirely passed -- NEED RESULT: P5: Inertial transactions completed entirely passed -- NEED RESULT: P4: Inertial transactions completed entirely passed -- NEED RESULT: P3: Inertial transactions completed entirely passed -- NEED RESULT: P2: Inertial transactions completed entirely passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00382 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00382(ARCH00382) -- ENT00382_Test_Bench(ARCH00382_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00382 is end ENT00382 ; -- -- architecture ARCH00382 of ENT00382 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_boolean_savt : chk_time_type := 0 ns ; signal s_bit_savt : chk_time_type := 0 ns ; signal s_severity_level_savt : chk_time_type := 0 ns ; signal s_character_savt : chk_time_type := 0 ns ; signal s_st_enum1_savt : chk_time_type := 0 ns ; signal s_integer_savt : chk_time_type := 0 ns ; signal s_st_int1_savt : chk_time_type := 0 ns ; signal s_time_savt : chk_time_type := 0 ns ; signal s_st_phys1_savt : chk_time_type := 0 ns ; signal s_real_savt : chk_time_type := 0 ns ; signal s_st_real1_savt : chk_time_type := 0 ns ; signal s_st_rec1_savt : chk_time_type := 0 ns ; signal s_st_rec2_savt : chk_time_type := 0 ns ; signal s_st_rec3_savt : chk_time_type := 0 ns ; signal s_st_arr1_savt : chk_time_type := 0 ns ; signal s_st_arr2_savt : chk_time_type := 0 ns ; signal s_st_arr3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_boolean_cnt : chk_cnt_type := 0 ; signal s_bit_cnt : chk_cnt_type := 0 ; signal s_severity_level_cnt : chk_cnt_type := 0 ; signal s_character_cnt : chk_cnt_type := 0 ; signal s_st_enum1_cnt : chk_cnt_type := 0 ; signal s_integer_cnt : chk_cnt_type := 0 ; signal s_st_int1_cnt : chk_cnt_type := 0 ; signal s_time_cnt : chk_cnt_type := 0 ; signal s_st_phys1_cnt : chk_cnt_type := 0 ; signal s_real_cnt : chk_cnt_type := 0 ; signal s_st_real1_cnt : chk_cnt_type := 0 ; signal s_st_rec1_cnt : chk_cnt_type := 0 ; signal s_st_rec2_cnt : chk_cnt_type := 0 ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; signal s_st_arr1_cnt : chk_cnt_type := 0 ; signal s_st_arr2_cnt : chk_cnt_type := 0 ; signal s_st_arr3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal boolean_select : select_type := 1 ; signal bit_select : select_type := 1 ; signal severity_level_select : select_type := 1 ; signal character_select : select_type := 1 ; signal st_enum1_select : select_type := 1 ; signal integer_select : select_type := 1 ; signal st_int1_select : select_type := 1 ; signal time_select : select_type := 1 ; signal st_phys1_select : select_type := 1 ; signal real_select : select_type := 1 ; signal st_real1_select : select_type := 1 ; signal st_rec1_select : select_type := 1 ; signal st_rec2_select : select_type := 1 ; signal st_rec3_select : select_type := 1 ; signal st_arr1_select : select_type := 1 ; signal st_arr2_select : select_type := 1 ; signal st_arr3_select : select_type := 1 ; -- signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_boolean_cnt is when 0 => null ; -- s_boolean <= -- c_boolean_2 after 10 ns, -- c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- boolean_select <= transport 2 ; -- s_boolean <= -- c_boolean_2 after 10 ns , -- c_boolean_1 after 20 ns , -- c_boolean_2 after 30 ns , -- c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; boolean_select <= transport 3 ; -- s_boolean <= -- c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; boolean_select <= transport 4 ; -- s_boolean <= -- c_boolean_1 after 100 ns ; -- when 5 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; boolean_select <= transport 5 ; -- s_boolean <= -- c_boolean_2 after 10 ns , -- c_boolean_1 after 20 ns , -- c_boolean_2 after 30 ns , -- c_boolean_1 after 40 ns ; -- when 6 => correct := correct and s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; boolean_select <= transport 6 ; -- Last transaction above is marked -- s_boolean <= -- c_boolean_1 after 40 ns ; -- when 7 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_boolean_savt <= transport Std.Standard.Now ; chk_boolean <= transport s_boolean_cnt after (1 us - Std.Standard.Now) ; s_boolean_cnt <= transport s_boolean_cnt + 1 ; wait until (not s_boolean'Quiet) and (s_boolean_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_boolean = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_boolean <= c_boolean_2 after 10 ns, c_boolean_1 after 20 ns when boolean_select = 1 else -- c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns when boolean_select = 2 else -- c_boolean_1 after 5 ns when boolean_select = 3 else -- c_boolean_1 after 100 ns when boolean_select = 4 else -- c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns when boolean_select = 5 else -- -- Last transaction above is marked c_boolean_1 after 40 ns ; -- CHG2 : process variable correct : boolean ; begin case s_bit_cnt is when 0 => null ; -- s_bit <= -- c_bit_2 after 10 ns, -- c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P2" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- bit_select <= transport 2 ; -- s_bit <= -- c_bit_2 after 10 ns , -- c_bit_1 after 20 ns , -- c_bit_2 after 30 ns , -- c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; bit_select <= transport 3 ; -- s_bit <= -- c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; bit_select <= transport 4 ; -- s_bit <= -- c_bit_1 after 100 ns ; -- when 5 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; bit_select <= transport 5 ; -- s_bit <= -- c_bit_2 after 10 ns , -- c_bit_1 after 20 ns , -- c_bit_2 after 30 ns , -- c_bit_1 after 40 ns ; -- when 6 => correct := correct and s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; bit_select <= transport 6 ; -- Last transaction above is marked -- s_bit <= -- c_bit_1 after 40 ns ; -- when 7 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_bit_savt <= transport Std.Standard.Now ; chk_bit <= transport s_bit_cnt after (1 us - Std.Standard.Now) ; s_bit_cnt <= transport s_bit_cnt + 1 ; wait until (not s_bit'Quiet) and (s_bit_savt /= Std.Standard.Now) ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions completed entirely", chk_bit = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_bit <= c_bit_2 after 10 ns, c_bit_1 after 20 ns when bit_select = 1 else -- c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns when bit_select = 2 else -- c_bit_1 after 5 ns when bit_select = 3 else -- c_bit_1 after 100 ns when bit_select = 4 else -- c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns when bit_select = 5 else -- -- Last transaction above is marked c_bit_1 after 40 ns ; -- CHG3 : process variable correct : boolean ; begin case s_severity_level_cnt is when 0 => null ; -- s_severity_level <= -- c_severity_level_2 after 10 ns, -- c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P3" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- severity_level_select <= transport 2 ; -- s_severity_level <= -- c_severity_level_2 after 10 ns , -- c_severity_level_1 after 20 ns , -- c_severity_level_2 after 30 ns , -- c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; severity_level_select <= transport 3 ; -- s_severity_level <= -- c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; severity_level_select <= transport 4 ; -- s_severity_level <= -- c_severity_level_1 after 100 ns ; -- when 5 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; severity_level_select <= transport 5 ; -- s_severity_level <= -- c_severity_level_2 after 10 ns , -- c_severity_level_1 after 20 ns , -- c_severity_level_2 after 30 ns , -- c_severity_level_1 after 40 ns ; -- when 6 => correct := correct and s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; severity_level_select <= transport 6 ; -- Last transaction above is marked -- s_severity_level <= -- c_severity_level_1 after 40 ns ; -- when 7 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_severity_level_savt <= transport Std.Standard.Now ; chk_severity_level <= transport s_severity_level_cnt after (1 us - Std.Standard.Now) ; s_severity_level_cnt <= transport s_severity_level_cnt + 1 ; wait until (not s_severity_level'Quiet) and (s_severity_level_savt /= Std.Standard.Now) ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions completed entirely", chk_severity_level = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_severity_level <= c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns when severity_level_select = 1 else -- c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns when severity_level_select = 2 else -- c_severity_level_1 after 5 ns when severity_level_select = 3 else -- c_severity_level_1 after 100 ns when severity_level_select = 4 else -- c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns when severity_level_select = 5 else -- -- Last transaction above is marked c_severity_level_1 after 40 ns ; -- CHG4 : process variable correct : boolean ; begin case s_character_cnt is when 0 => null ; -- s_character <= -- c_character_2 after 10 ns, -- c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P4" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- character_select <= transport 2 ; -- s_character <= -- c_character_2 after 10 ns , -- c_character_1 after 20 ns , -- c_character_2 after 30 ns , -- c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; character_select <= transport 3 ; -- s_character <= -- c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (s_character_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; character_select <= transport 4 ; -- s_character <= -- c_character_1 after 100 ns ; -- when 5 => correct := correct and s_character = c_character_1 and (s_character_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; character_select <= transport 5 ; -- s_character <= -- c_character_2 after 10 ns , -- c_character_1 after 20 ns , -- c_character_2 after 30 ns , -- c_character_1 after 40 ns ; -- when 6 => correct := correct and s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; character_select <= transport 6 ; -- Last transaction above is marked -- s_character <= -- c_character_1 after 40 ns ; -- when 7 => correct := correct and s_character = c_character_1 and (s_character_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_character = c_character_1 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_character_savt <= transport Std.Standard.Now ; chk_character <= transport s_character_cnt after (1 us - Std.Standard.Now) ; s_character_cnt <= transport s_character_cnt + 1 ; wait until (not s_character'Quiet) and (s_character_savt /= Std.Standard.Now) ; -- end process CHG4 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Inertial transactions completed entirely", chk_character = 8 ) ; end if ; end process PGEN_CHKP_4 ; -- -- s_character <= c_character_2 after 10 ns, c_character_1 after 20 ns when character_select = 1 else -- c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns when character_select = 2 else -- c_character_1 after 5 ns when character_select = 3 else -- c_character_1 after 100 ns when character_select = 4 else -- c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns when character_select = 5 else -- -- Last transaction above is marked c_character_1 after 40 ns ; -- CHG5 : process variable correct : boolean ; begin case s_st_enum1_cnt is when 0 => null ; -- s_st_enum1 <= -- c_st_enum1_2 after 10 ns, -- c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P5" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_enum1_select <= transport 2 ; -- s_st_enum1 <= -- c_st_enum1_2 after 10 ns , -- c_st_enum1_1 after 20 ns , -- c_st_enum1_2 after 30 ns , -- c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; st_enum1_select <= transport 3 ; -- s_st_enum1 <= -- c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_select <= transport 4 ; -- s_st_enum1 <= -- c_st_enum1_1 after 100 ns ; -- when 5 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_enum1_select <= transport 5 ; -- s_st_enum1 <= -- c_st_enum1_2 after 10 ns , -- c_st_enum1_1 after 20 ns , -- c_st_enum1_2 after 30 ns , -- c_st_enum1_1 after 40 ns ; -- when 6 => correct := correct and s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_select <= transport 6 ; -- Last transaction above is marked -- s_st_enum1 <= -- c_st_enum1_1 after 40 ns ; -- when 7 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_enum1_savt <= transport Std.Standard.Now ; chk_st_enum1 <= transport s_st_enum1_cnt after (1 us - Std.Standard.Now) ; s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ; wait until (not s_st_enum1'Quiet) and (s_st_enum1_savt /= Std.Standard.Now) ; -- end process CHG5 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Inertial transactions completed entirely", chk_st_enum1 = 8 ) ; end if ; end process PGEN_CHKP_5 ; -- -- s_st_enum1 <= c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns when st_enum1_select = 1 else -- c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns when st_enum1_select = 2 else -- c_st_enum1_1 after 5 ns when st_enum1_select = 3 else -- c_st_enum1_1 after 100 ns when st_enum1_select = 4 else -- c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns when st_enum1_select = 5 else -- -- Last transaction above is marked c_st_enum1_1 after 40 ns ; -- CHG6 : process variable correct : boolean ; begin case s_integer_cnt is when 0 => null ; -- s_integer <= -- c_integer_2 after 10 ns, -- c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P6" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- integer_select <= transport 2 ; -- s_integer <= -- c_integer_2 after 10 ns , -- c_integer_1 after 20 ns , -- c_integer_2 after 30 ns , -- c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; integer_select <= transport 3 ; -- s_integer <= -- c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; integer_select <= transport 4 ; -- s_integer <= -- c_integer_1 after 100 ns ; -- when 5 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; integer_select <= transport 5 ; -- s_integer <= -- c_integer_2 after 10 ns , -- c_integer_1 after 20 ns , -- c_integer_2 after 30 ns , -- c_integer_1 after 40 ns ; -- when 6 => correct := correct and s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; integer_select <= transport 6 ; -- Last transaction above is marked -- s_integer <= -- c_integer_1 after 40 ns ; -- when 7 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_integer_savt <= transport Std.Standard.Now ; chk_integer <= transport s_integer_cnt after (1 us - Std.Standard.Now) ; s_integer_cnt <= transport s_integer_cnt + 1 ; wait until (not s_integer'Quiet) and (s_integer_savt /= Std.Standard.Now) ; -- end process CHG6 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Inertial transactions completed entirely", chk_integer = 8 ) ; end if ; end process PGEN_CHKP_6 ; -- -- s_integer <= c_integer_2 after 10 ns, c_integer_1 after 20 ns when integer_select = 1 else -- c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns when integer_select = 2 else -- c_integer_1 after 5 ns when integer_select = 3 else -- c_integer_1 after 100 ns when integer_select = 4 else -- c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns when integer_select = 5 else -- -- Last transaction above is marked c_integer_1 after 40 ns ; -- CHG7 : process variable correct : boolean ; begin case s_st_int1_cnt is when 0 => null ; -- s_st_int1 <= -- c_st_int1_2 after 10 ns, -- c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P7" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_int1_select <= transport 2 ; -- s_st_int1 <= -- c_st_int1_2 after 10 ns , -- c_st_int1_1 after 20 ns , -- c_st_int1_2 after 30 ns , -- c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; st_int1_select <= transport 3 ; -- s_st_int1 <= -- c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_int1_select <= transport 4 ; -- s_st_int1 <= -- c_st_int1_1 after 100 ns ; -- when 5 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_int1_select <= transport 5 ; -- s_st_int1 <= -- c_st_int1_2 after 10 ns , -- c_st_int1_1 after 20 ns , -- c_st_int1_2 after 30 ns , -- c_st_int1_1 after 40 ns ; -- when 6 => correct := correct and s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_int1_select <= transport 6 ; -- Last transaction above is marked -- s_st_int1 <= -- c_st_int1_1 after 40 ns ; -- when 7 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_int1_savt <= transport Std.Standard.Now ; chk_st_int1 <= transport s_st_int1_cnt after (1 us - Std.Standard.Now) ; s_st_int1_cnt <= transport s_st_int1_cnt + 1 ; wait until (not s_st_int1'Quiet) and (s_st_int1_savt /= Std.Standard.Now) ; -- end process CHG7 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Inertial transactions completed entirely", chk_st_int1 = 8 ) ; end if ; end process PGEN_CHKP_7 ; -- -- s_st_int1 <= c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns when st_int1_select = 1 else -- c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns when st_int1_select = 2 else -- c_st_int1_1 after 5 ns when st_int1_select = 3 else -- c_st_int1_1 after 100 ns when st_int1_select = 4 else -- c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns when st_int1_select = 5 else -- -- Last transaction above is marked c_st_int1_1 after 40 ns ; -- CHG8 : process variable correct : boolean ; begin case s_time_cnt is when 0 => null ; -- s_time <= -- c_time_2 after 10 ns, -- c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P8" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- time_select <= transport 2 ; -- s_time <= -- c_time_2 after 10 ns , -- c_time_1 after 20 ns , -- c_time_2 after 30 ns , -- c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; time_select <= transport 3 ; -- s_time <= -- c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (s_time_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; time_select <= transport 4 ; -- s_time <= -- c_time_1 after 100 ns ; -- when 5 => correct := correct and s_time = c_time_1 and (s_time_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; time_select <= transport 5 ; -- s_time <= -- c_time_2 after 10 ns , -- c_time_1 after 20 ns , -- c_time_2 after 30 ns , -- c_time_1 after 40 ns ; -- when 6 => correct := correct and s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; time_select <= transport 6 ; -- Last transaction above is marked -- s_time <= -- c_time_1 after 40 ns ; -- when 7 => correct := correct and s_time = c_time_1 and (s_time_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_time = c_time_1 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_time_savt <= transport Std.Standard.Now ; chk_time <= transport s_time_cnt after (1 us - Std.Standard.Now) ; s_time_cnt <= transport s_time_cnt + 1 ; wait until (not s_time'Quiet) and (s_time_savt /= Std.Standard.Now) ; -- end process CHG8 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Inertial transactions completed entirely", chk_time = 8 ) ; end if ; end process PGEN_CHKP_8 ; -- -- s_time <= c_time_2 after 10 ns, c_time_1 after 20 ns when time_select = 1 else -- c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns when time_select = 2 else -- c_time_1 after 5 ns when time_select = 3 else -- c_time_1 after 100 ns when time_select = 4 else -- c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns when time_select = 5 else -- -- Last transaction above is marked c_time_1 after 40 ns ; -- CHG9 : process variable correct : boolean ; begin case s_st_phys1_cnt is when 0 => null ; -- s_st_phys1 <= -- c_st_phys1_2 after 10 ns, -- c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P9" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_phys1_select <= transport 2 ; -- s_st_phys1 <= -- c_st_phys1_2 after 10 ns , -- c_st_phys1_1 after 20 ns , -- c_st_phys1_2 after 30 ns , -- c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; st_phys1_select <= transport 3 ; -- s_st_phys1 <= -- c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_phys1_select <= transport 4 ; -- s_st_phys1 <= -- c_st_phys1_1 after 100 ns ; -- when 5 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_phys1_select <= transport 5 ; -- s_st_phys1 <= -- c_st_phys1_2 after 10 ns , -- c_st_phys1_1 after 20 ns , -- c_st_phys1_2 after 30 ns , -- c_st_phys1_1 after 40 ns ; -- when 6 => correct := correct and s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_phys1_select <= transport 6 ; -- Last transaction above is marked -- s_st_phys1 <= -- c_st_phys1_1 after 40 ns ; -- when 7 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_phys1_savt <= transport Std.Standard.Now ; chk_st_phys1 <= transport s_st_phys1_cnt after (1 us - Std.Standard.Now) ; s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ; wait until (not s_st_phys1'Quiet) and (s_st_phys1_savt /= Std.Standard.Now) ; -- end process CHG9 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Inertial transactions completed entirely", chk_st_phys1 = 8 ) ; end if ; end process PGEN_CHKP_9 ; -- -- s_st_phys1 <= c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns when st_phys1_select = 1 else -- c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns when st_phys1_select = 2 else -- c_st_phys1_1 after 5 ns when st_phys1_select = 3 else -- c_st_phys1_1 after 100 ns when st_phys1_select = 4 else -- c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns when st_phys1_select = 5 else -- -- Last transaction above is marked c_st_phys1_1 after 40 ns ; -- CHG10 : process variable correct : boolean ; begin case s_real_cnt is when 0 => null ; -- s_real <= -- c_real_2 after 10 ns, -- c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P10" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- real_select <= transport 2 ; -- s_real <= -- c_real_2 after 10 ns , -- c_real_1 after 20 ns , -- c_real_2 after 30 ns , -- c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; real_select <= transport 3 ; -- s_real <= -- c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (s_real_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; real_select <= transport 4 ; -- s_real <= -- c_real_1 after 100 ns ; -- when 5 => correct := correct and s_real = c_real_1 and (s_real_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; real_select <= transport 5 ; -- s_real <= -- c_real_2 after 10 ns , -- c_real_1 after 20 ns , -- c_real_2 after 30 ns , -- c_real_1 after 40 ns ; -- when 6 => correct := correct and s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; real_select <= transport 6 ; -- Last transaction above is marked -- s_real <= -- c_real_1 after 40 ns ; -- when 7 => correct := correct and s_real = c_real_1 and (s_real_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_real = c_real_1 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_real_savt <= transport Std.Standard.Now ; chk_real <= transport s_real_cnt after (1 us - Std.Standard.Now) ; s_real_cnt <= transport s_real_cnt + 1 ; wait until (not s_real'Quiet) and (s_real_savt /= Std.Standard.Now) ; -- end process CHG10 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Inertial transactions completed entirely", chk_real = 8 ) ; end if ; end process PGEN_CHKP_10 ; -- -- s_real <= c_real_2 after 10 ns, c_real_1 after 20 ns when real_select = 1 else -- c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns when real_select = 2 else -- c_real_1 after 5 ns when real_select = 3 else -- c_real_1 after 100 ns when real_select = 4 else -- c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns when real_select = 5 else -- -- Last transaction above is marked c_real_1 after 40 ns ; -- CHG11 : process variable correct : boolean ; begin case s_st_real1_cnt is when 0 => null ; -- s_st_real1 <= -- c_st_real1_2 after 10 ns, -- c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P11" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_real1_select <= transport 2 ; -- s_st_real1 <= -- c_st_real1_2 after 10 ns , -- c_st_real1_1 after 20 ns , -- c_st_real1_2 after 30 ns , -- c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; st_real1_select <= transport 3 ; -- s_st_real1 <= -- c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real1_select <= transport 4 ; -- s_st_real1 <= -- c_st_real1_1 after 100 ns ; -- when 5 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_real1_select <= transport 5 ; -- s_st_real1 <= -- c_st_real1_2 after 10 ns , -- c_st_real1_1 after 20 ns , -- c_st_real1_2 after 30 ns , -- c_st_real1_1 after 40 ns ; -- when 6 => correct := correct and s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real1_select <= transport 6 ; -- Last transaction above is marked -- s_st_real1 <= -- c_st_real1_1 after 40 ns ; -- when 7 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_real1_savt <= transport Std.Standard.Now ; chk_st_real1 <= transport s_st_real1_cnt after (1 us - Std.Standard.Now) ; s_st_real1_cnt <= transport s_st_real1_cnt + 1 ; wait until (not s_st_real1'Quiet) and (s_st_real1_savt /= Std.Standard.Now) ; -- end process CHG11 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Inertial transactions completed entirely", chk_st_real1 = 8 ) ; end if ; end process PGEN_CHKP_11 ; -- -- s_st_real1 <= c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns when st_real1_select = 1 else -- c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns when st_real1_select = 2 else -- c_st_real1_1 after 5 ns when st_real1_select = 3 else -- c_st_real1_1 after 100 ns when st_real1_select = 4 else -- c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns when st_real1_select = 5 else -- -- Last transaction above is marked c_st_real1_1 after 40 ns ; -- CHG12 : process variable correct : boolean ; begin case s_st_rec1_cnt is when 0 => null ; -- s_st_rec1 <= -- c_st_rec1_2 after 10 ns, -- c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P12" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_select <= transport 2 ; -- s_st_rec1 <= -- c_st_rec1_2 after 10 ns , -- c_st_rec1_1 after 20 ns , -- c_st_rec1_2 after 30 ns , -- c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; st_rec1_select <= transport 3 ; -- s_st_rec1 <= -- c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_select <= transport 4 ; -- s_st_rec1 <= -- c_st_rec1_1 after 100 ns ; -- when 5 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec1_select <= transport 5 ; -- s_st_rec1 <= -- c_st_rec1_2 after 10 ns , -- c_st_rec1_1 after 20 ns , -- c_st_rec1_2 after 30 ns , -- c_st_rec1_1 after 40 ns ; -- when 6 => correct := correct and s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec1 <= -- c_st_rec1_1 after 40 ns ; -- when 7 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec1_savt <= transport Std.Standard.Now ; chk_st_rec1 <= transport s_st_rec1_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ; wait until (not s_st_rec1'Quiet) and (s_st_rec1_savt /= Std.Standard.Now) ; -- end process CHG12 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Inertial transactions completed entirely", chk_st_rec1 = 8 ) ; end if ; end process PGEN_CHKP_12 ; -- -- s_st_rec1 <= c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns when st_rec1_select = 1 else -- c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns when st_rec1_select = 2 else -- c_st_rec1_1 after 5 ns when st_rec1_select = 3 else -- c_st_rec1_1 after 100 ns when st_rec1_select = 4 else -- c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns when st_rec1_select = 5 else -- -- Last transaction above is marked c_st_rec1_1 after 40 ns ; -- CHG13 : process variable correct : boolean ; begin case s_st_rec2_cnt is when 0 => null ; -- s_st_rec2 <= -- c_st_rec2_2 after 10 ns, -- c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P13" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_select <= transport 2 ; -- s_st_rec2 <= -- c_st_rec2_2 after 10 ns , -- c_st_rec2_1 after 20 ns , -- c_st_rec2_2 after 30 ns , -- c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; st_rec2_select <= transport 3 ; -- s_st_rec2 <= -- c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_select <= transport 4 ; -- s_st_rec2 <= -- c_st_rec2_1 after 100 ns ; -- when 5 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec2_select <= transport 5 ; -- s_st_rec2 <= -- c_st_rec2_2 after 10 ns , -- c_st_rec2_1 after 20 ns , -- c_st_rec2_2 after 30 ns , -- c_st_rec2_1 after 40 ns ; -- when 6 => correct := correct and s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec2 <= -- c_st_rec2_1 after 40 ns ; -- when 7 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec2_savt <= transport Std.Standard.Now ; chk_st_rec2 <= transport s_st_rec2_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ; wait until (not s_st_rec2'Quiet) and (s_st_rec2_savt /= Std.Standard.Now) ; -- end process CHG13 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Inertial transactions completed entirely", chk_st_rec2 = 8 ) ; end if ; end process PGEN_CHKP_13 ; -- -- s_st_rec2 <= c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns when st_rec2_select = 1 else -- c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns when st_rec2_select = 2 else -- c_st_rec2_1 after 5 ns when st_rec2_select = 3 else -- c_st_rec2_1 after 100 ns when st_rec2_select = 4 else -- c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns when st_rec2_select = 5 else -- -- Last transaction above is marked c_st_rec2_1 after 40 ns ; -- CHG14 : process variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3 <= -- c_st_rec3_2 after 10 ns, -- c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P14" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_select <= transport 2 ; -- s_st_rec3 <= -- c_st_rec3_2 after 10 ns , -- c_st_rec3_1 after 20 ns , -- c_st_rec3_2 after 30 ns , -- c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; st_rec3_select <= transport 3 ; -- s_st_rec3 <= -- c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 4 ; -- s_st_rec3 <= -- c_st_rec3_1 after 100 ns ; -- when 5 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 5 ; -- s_st_rec3 <= -- c_st_rec3_2 after 10 ns , -- c_st_rec3_1 after 20 ns , -- c_st_rec3_2 after 30 ns , -- c_st_rec3_1 after 40 ns ; -- when 6 => correct := correct and s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec3 <= -- c_st_rec3_1 after 40 ns ; -- when 7 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec3_savt <= transport Std.Standard.Now ; chk_st_rec3 <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ; wait until (not s_st_rec3'Quiet) and (s_st_rec3_savt /= Std.Standard.Now) ; -- end process CHG14 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Inertial transactions completed entirely", chk_st_rec3 = 8 ) ; end if ; end process PGEN_CHKP_14 ; -- -- s_st_rec3 <= c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns when st_rec3_select = 1 else -- c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns when st_rec3_select = 2 else -- c_st_rec3_1 after 5 ns when st_rec3_select = 3 else -- c_st_rec3_1 after 100 ns when st_rec3_select = 4 else -- c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns when st_rec3_select = 5 else -- -- Last transaction above is marked c_st_rec3_1 after 40 ns ; -- CHG15 : process variable correct : boolean ; begin case s_st_arr1_cnt is when 0 => null ; -- s_st_arr1 <= -- c_st_arr1_2 after 10 ns, -- c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P15" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr1_select <= transport 2 ; -- s_st_arr1 <= -- c_st_arr1_2 after 10 ns , -- c_st_arr1_1 after 20 ns , -- c_st_arr1_2 after 30 ns , -- c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; st_arr1_select <= transport 3 ; -- s_st_arr1 <= -- c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr1_select <= transport 4 ; -- s_st_arr1 <= -- c_st_arr1_1 after 100 ns ; -- when 5 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr1_select <= transport 5 ; -- s_st_arr1 <= -- c_st_arr1_2 after 10 ns , -- c_st_arr1_1 after 20 ns , -- c_st_arr1_2 after 30 ns , -- c_st_arr1_1 after 40 ns ; -- when 6 => correct := correct and s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr1_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr1 <= -- c_st_arr1_1 after 40 ns ; -- when 7 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr1_savt <= transport Std.Standard.Now ; chk_st_arr1 <= transport s_st_arr1_cnt after (1 us - Std.Standard.Now) ; s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ; wait until (not s_st_arr1'Quiet) and (s_st_arr1_savt /= Std.Standard.Now) ; -- end process CHG15 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Inertial transactions completed entirely", chk_st_arr1 = 8 ) ; end if ; end process PGEN_CHKP_15 ; -- -- s_st_arr1 <= c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns when st_arr1_select = 1 else -- c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns when st_arr1_select = 2 else -- c_st_arr1_1 after 5 ns when st_arr1_select = 3 else -- c_st_arr1_1 after 100 ns when st_arr1_select = 4 else -- c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns when st_arr1_select = 5 else -- -- Last transaction above is marked c_st_arr1_1 after 40 ns ; -- CHG16 : process variable correct : boolean ; begin case s_st_arr2_cnt is when 0 => null ; -- s_st_arr2 <= -- c_st_arr2_2 after 10 ns, -- c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P16" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_select <= transport 2 ; -- s_st_arr2 <= -- c_st_arr2_2 after 10 ns , -- c_st_arr2_1 after 20 ns , -- c_st_arr2_2 after 30 ns , -- c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; st_arr2_select <= transport 3 ; -- s_st_arr2 <= -- c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_select <= transport 4 ; -- s_st_arr2 <= -- c_st_arr2_1 after 100 ns ; -- when 5 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr2_select <= transport 5 ; -- s_st_arr2 <= -- c_st_arr2_2 after 10 ns , -- c_st_arr2_1 after 20 ns , -- c_st_arr2_2 after 30 ns , -- c_st_arr2_1 after 40 ns ; -- when 6 => correct := correct and s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr2 <= -- c_st_arr2_1 after 40 ns ; -- when 7 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr2_savt <= transport Std.Standard.Now ; chk_st_arr2 <= transport s_st_arr2_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ; wait until (not s_st_arr2'Quiet) and (s_st_arr2_savt /= Std.Standard.Now) ; -- end process CHG16 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Inertial transactions completed entirely", chk_st_arr2 = 8 ) ; end if ; end process PGEN_CHKP_16 ; -- -- s_st_arr2 <= c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns when st_arr2_select = 1 else -- c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns when st_arr2_select = 2 else -- c_st_arr2_1 after 5 ns when st_arr2_select = 3 else -- c_st_arr2_1 after 100 ns when st_arr2_select = 4 else -- c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns when st_arr2_select = 5 else -- -- Last transaction above is marked c_st_arr2_1 after 40 ns ; -- CHG17 : process variable correct : boolean ; begin case s_st_arr3_cnt is when 0 => null ; -- s_st_arr3 <= -- c_st_arr3_2 after 10 ns, -- c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P17" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr3_select <= transport 2 ; -- s_st_arr3 <= -- c_st_arr3_2 after 10 ns , -- c_st_arr3_1 after 20 ns , -- c_st_arr3_2 after 30 ns , -- c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; st_arr3_select <= transport 3 ; -- s_st_arr3 <= -- c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr3_select <= transport 4 ; -- s_st_arr3 <= -- c_st_arr3_1 after 100 ns ; -- when 5 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr3_select <= transport 5 ; -- s_st_arr3 <= -- c_st_arr3_2 after 10 ns , -- c_st_arr3_1 after 20 ns , -- c_st_arr3_2 after 30 ns , -- c_st_arr3_1 after 40 ns ; -- when 6 => correct := correct and s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr3_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr3 <= -- c_st_arr3_1 after 40 ns ; -- when 7 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr3_savt <= transport Std.Standard.Now ; chk_st_arr3 <= transport s_st_arr3_cnt after (1 us - Std.Standard.Now) ; s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ; wait until (not s_st_arr3'Quiet) and (s_st_arr3_savt /= Std.Standard.Now) ; -- end process CHG17 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Inertial transactions completed entirely", chk_st_arr3 = 8 ) ; end if ; end process PGEN_CHKP_17 ; -- -- s_st_arr3 <= c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns when st_arr3_select = 1 else -- c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns when st_arr3_select = 2 else -- c_st_arr3_1 after 5 ns when st_arr3_select = 3 else -- c_st_arr3_1 after 100 ns when st_arr3_select = 4 else -- c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns when st_arr3_select = 5 else -- -- Last transaction above is marked c_st_arr3_1 after 40 ns ; -- end ARCH00382 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00382_Test_Bench is end ENT00382_Test_Bench ; -- -- architecture ARCH00382_Test_Bench of ENT00382_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00382 ( ARCH00382 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00382_Test_Bench ;
entity t1 is end entity; architecture a of t1 is constant SimulationTime_c : time := 0 fs; begin end;
------------------------------------------------------------------------------- -- Title : Testbench for design "SinGen" ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library ieee_proposed; use ieee_proposed.fixed_float_types.all; use ieee_proposed.fixed_pkg.all; use work.Global.all; ------------------------------------------------------------------------------- entity SinGen_tb is end entity SinGen_tb; ------------------------------------------------------------------------------- architecture Bhv of SinGen_tb is -- component generics constant periode_g : time := 100 us; constant sample_time_g : time := 200 ns; -- component ports signal data_o : audio_data_t; signal data_valid_o : std_ulogic; -- clock signal Clk : std_logic := '1'; begin -- architecture Bhv -- component instantiation DUT : entity work.SinGen generic map ( periode_g => periode_g, sample_time_g => sample_time_g) port map ( clk_i => Clk, data_o => data_o, data_valid_o => data_valid_o); -- clock generation Clk <= not Clk after 10 ns; -- waveform generation WaveGen_Proc : process begin -- insert signal assignments here wait; end process WaveGen_Proc; end architecture Bhv; -------------------------------------------------------------------------------
------------------------------------------------------------------------------- -- -- Project: <Floating Point Unit Core> -- -- Description: division entity for the division unit ------------------------------------------------------------------------------- -- -- 100101011010011100100 -- 110000111011100100000 -- 100000111011000101101 -- 100010111100101111001 -- 110000111011101101001 -- 010000001011101001010 -- 110100111001001100001 -- 110111010000001100111 -- 110110111110001011101 -- 101110110010111101000 -- 100000010111000000000 -- -- Author: Jidan Al-eryani -- E-mail: [email protected] -- -- Copyright (C) 2006 -- -- This source file may be used and distributed without -- restriction provided that this copyright statement is not -- removed from the file and that any derivative work contains -- the original copyright notice and the associated disclaimer. -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; library work; use work.fpupack.all; entity serial_div is port( clk_i : in std_logic; dvdnd_i : in std_logic_vector(2(FRAC_WIDTH+2)-1 downto 0); -- hidden(1) & fraction(23) dvsor_i : in std_logic_vector(FRAC_WIDTH+3 downto 0); sign_dvd_i : in std_logic; sign_div_i : in std_logic; start_i : in std_logic; ready_o : out std_logic; qutnt_o : out std_logic_vector(FRAC_WIDTH+3 downto 0); rmndr_o : out std_logic_vector(FRAC_WIDTH+3 downto 0); sign_o : out std_logic; div_zero_o : out std_logic ); end serial_div; architecture rtl of serial_div is type t_state is (waiting,busy); signal s_qutnt_o, s_rmndr_o : std_logic_vector(FRAC_WIDTH+3 downto 0); signal s_dvdnd_i : std_logic_vector(2(FRAC_WIDTH+2)-1 downto 0); signal s_dvsor_i : std_logic_vector(FRAC_WIDTH+3 downto 0); signal s_sign_dvd_i, s_sign_div_i, s_sign_o : std_logic; signal s_div_zero_o : std_logic; signal s_start_i, s_ready_o : std_logic; signal s_state : t_state; signal s_count : integer range 0 to FRAC_WIDTH+3; signal s_dvd : std_logic_vector(FRAC_WIDTH+3 downto 0); begin -- Input Register process(clk_i) begin if rising_edge(clk_i) then s_dvdnd_i <= dvdnd_i; s_dvsor_i <= dvsor_i; s_sign_dvd_i<= sign_dvd_i; s_sign_div_i<= sign_div_i; s_start_i <= start_i; end if; end process; -- Output Register --process(clk_i) --begin -- if rising_edge(clk_i) then qutnt_o <= s_qutnt_o; rmndr_o <= s_rmndr_o; sign_o <= s_sign_o; ready_o <= s_ready_o; div_zero_o <= s_div_zero_o; -- end if; --end process; s_sign_o <= sign_dvd_i xor sign_div_i; s_div_zero_o <= '1' when or_reduce(s_dvsor_i)='0' and or_reduce(s_dvdnd_i)='1' else '0'; -- FSM process(clk_i) begin if rising_edge(clk_i) then if s_start_i ='1' then s_state <= busy; s_count <= 26; elsif s_count=0 and s_state=busy then s_state <= waiting; s_ready_o <= '1'; s_count <=26; elsif s_state=busy then s_count <= s_count - 1; else s_state <= waiting; s_ready_o <= '0'; end if; end if; end process; process(clk_i) variable v_div : std_logic_vector(26 downto 0); begin if rising_edge(clk_i) then if s_state=busy then if s_count=26 then v_div := "000" & s_dvdnd_i(49 downto 26); else v_div:= s_dvd; end if; if v_div < s_dvsor_i then s_qutnt_o(s_count) <= '0'; else s_qutnt_o(s_count) <= '1'; v_div:=v_div-s_dvsor_i; end if; s_rmndr_o <= v_div; s_dvd <= v_div(25 downto 0)&'0'; end if; end if; end process; end rtl;
------------------------------------------------------------------------------- -- -- Project: <Floating Point Unit Core> -- -- Description: division entity for the division unit ------------------------------------------------------------------------------- -- -- 100101011010011100100 -- 110000111011100100000 -- 100000111011000101101 -- 100010111100101111001 -- 110000111011101101001 -- 010000001011101001010 -- 110100111001001100001 -- 110111010000001100111 -- 110110111110001011101 -- 101110110010111101000 -- 100000010111000000000 -- -- Author: Jidan Al-eryani -- E-mail: [email protected] -- -- Copyright (C) 2006 -- -- This source file may be used and distributed without -- restriction provided that this copyright statement is not -- removed from the file and that any derivative work contains -- the original copyright notice and the associated disclaimer. -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; library work; use work.fpupack.all; entity serial_div is port( clk_i : in std_logic; dvdnd_i : in std_logic_vector(2(FRAC_WIDTH+2)-1 downto 0); -- hidden(1) & fraction(23) dvsor_i : in std_logic_vector(FRAC_WIDTH+3 downto 0); sign_dvd_i : in std_logic; sign_div_i : in std_logic; start_i : in std_logic; ready_o : out std_logic; qutnt_o : out std_logic_vector(FRAC_WIDTH+3 downto 0); rmndr_o : out std_logic_vector(FRAC_WIDTH+3 downto 0); sign_o : out std_logic; div_zero_o : out std_logic ); end serial_div; architecture rtl of serial_div is type t_state is (waiting,busy); signal s_qutnt_o, s_rmndr_o : std_logic_vector(FRAC_WIDTH+3 downto 0); signal s_dvdnd_i : std_logic_vector(2(FRAC_WIDTH+2)-1 downto 0); signal s_dvsor_i : std_logic_vector(FRAC_WIDTH+3 downto 0); signal s_sign_dvd_i, s_sign_div_i, s_sign_o : std_logic; signal s_div_zero_o : std_logic; signal s_start_i, s_ready_o : std_logic; signal s_state : t_state; signal s_count : integer range 0 to FRAC_WIDTH+3; signal s_dvd : std_logic_vector(FRAC_WIDTH+3 downto 0); begin -- Input Register process(clk_i) begin if rising_edge(clk_i) then s_dvdnd_i <= dvdnd_i; s_dvsor_i <= dvsor_i; s_sign_dvd_i<= sign_dvd_i; s_sign_div_i<= sign_div_i; s_start_i <= start_i; end if; end process; -- Output Register --process(clk_i) --begin -- if rising_edge(clk_i) then qutnt_o <= s_qutnt_o; rmndr_o <= s_rmndr_o; sign_o <= s_sign_o; ready_o <= s_ready_o; div_zero_o <= s_div_zero_o; -- end if; --end process; s_sign_o <= sign_dvd_i xor sign_div_i; s_div_zero_o <= '1' when or_reduce(s_dvsor_i)='0' and or_reduce(s_dvdnd_i)='1' else '0'; -- FSM process(clk_i) begin if rising_edge(clk_i) then if s_start_i ='1' then s_state <= busy; s_count <= 26; elsif s_count=0 and s_state=busy then s_state <= waiting; s_ready_o <= '1'; s_count <=26; elsif s_state=busy then s_count <= s_count - 1; else s_state <= waiting; s_ready_o <= '0'; end if; end if; end process; process(clk_i) variable v_div : std_logic_vector(26 downto 0); begin if rising_edge(clk_i) then if s_state=busy then if s_count=26 then v_div := "000" & s_dvdnd_i(49 downto 26); else v_div:= s_dvd; end if; if v_div < s_dvsor_i then s_qutnt_o(s_count) <= '0'; else s_qutnt_o(s_count) <= '1'; v_div:=v_div-s_dvsor_i; end if; s_rmndr_o <= v_div; s_dvd <= v_div(25 downto 0)&'0'; end if; end if; end process; end rtl;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- not in book entity computer_system is end entity computer_system; -- end not in book architecture abstract of computer_system is subtype word is bit_vector(31 downto 0); signal address : natural; signal read_data, write_data : word; signal mem_read, mem_write : bit := '0'; signal mem_ready : bit := '0'; begin cpu : process is variable instr_reg : word; variable PC : natural; -- . . . -- other declarations begin loop address <= PC; mem_read <= '1'; wait until mem_ready = '1'; instr_reg := read_data; mem_read <= '0'; wait until mem_ready = '0'; PC := PC + 4; -- . . . -- execute the instruction end loop; end process cpu; memory : process is type memory_array is array (0 to 2**14 - 1) of word; variable store : memory_array := ( -- . . . -- not in book 0 => X"0000_0000", 1 => X"0000_0004", 2 => X"0000_0008", 3 => X"0000_000C", 4 => X"0000_0010", 5 => X"0000_0014", others => X"0000_0000" -- end not in book ); begin wait until mem_read = '1' or mem_write = '1'; if mem_read = '1' then read_data <= store( address / 4 ); mem_ready <= '1'; wait until mem_read = '0'; mem_ready <= '0'; else -- . . . -- perform write access end if; end process memory; end architecture abstract;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- not in book entity computer_system is end entity computer_system; -- end not in book architecture abstract of computer_system is subtype word is bit_vector(31 downto 0); signal address : natural; signal read_data, write_data : word; signal mem_read, mem_write : bit := '0'; signal mem_ready : bit := '0'; begin cpu : process is variable instr_reg : word; variable PC : natural; -- . . . -- other declarations begin loop address <= PC; mem_read <= '1'; wait until mem_ready = '1'; instr_reg := read_data; mem_read <= '0'; wait until mem_ready = '0'; PC := PC + 4; -- . . . -- execute the instruction end loop; end process cpu; memory : process is type memory_array is array (0 to 2**14 - 1) of word; variable store : memory_array := ( -- . . . -- not in book 0 => X"0000_0000", 1 => X"0000_0004", 2 => X"0000_0008", 3 => X"0000_000C", 4 => X"0000_0010", 5 => X"0000_0014", others => X"0000_0000" -- end not in book ); begin wait until mem_read = '1' or mem_write = '1'; if mem_read = '1' then read_data <= store( address / 4 ); mem_ready <= '1'; wait until mem_read = '0'; mem_ready <= '0'; else -- . . . -- perform write access end if; end process memory; end architecture abstract;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- not in book entity computer_system is end entity computer_system; -- end not in book architecture abstract of computer_system is subtype word is bit_vector(31 downto 0); signal address : natural; signal read_data, write_data : word; signal mem_read, mem_write : bit := '0'; signal mem_ready : bit := '0'; begin cpu : process is variable instr_reg : word; variable PC : natural; -- . . . -- other declarations begin loop address <= PC; mem_read <= '1'; wait until mem_ready = '1'; instr_reg := read_data; mem_read <= '0'; wait until mem_ready = '0'; PC := PC + 4; -- . . . -- execute the instruction end loop; end process cpu; memory : process is type memory_array is array (0 to 2**14 - 1) of word; variable store : memory_array := ( -- . . . -- not in book 0 => X"0000_0000", 1 => X"0000_0004", 2 => X"0000_0008", 3 => X"0000_000C", 4 => X"0000_0010", 5 => X"0000_0014", others => X"0000_0000" -- end not in book ); begin wait until mem_read = '1' or mem_write = '1'; if mem_read = '1' then read_data <= store( address / 4 ); mem_ready <= '1'; wait until mem_read = '0'; mem_ready <= '0'; else -- . . . -- perform write access end if; end process memory; end architecture abstract;
library verilog; use verilog.vl_types.all; entity pll_dps_lcell_comb is generic( family : string := "Stratix V"; lut_mask : vl_logic_vector(0 to 63) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0); dont_touch : string := "on" ); port( dataa : in vl_logic; datab : in vl_logic; datac : in vl_logic; datad : in vl_logic; datae : in vl_logic; dataf : in vl_logic; combout : out vl_logic ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of family : constant is 1; attribute mti_svvh_generic_type of lut_mask : constant is 1; attribute mti_svvh_generic_type of dont_touch : constant is 1; end pll_dps_lcell_comb;
library verilog; use verilog.vl_types.all; entity pll_dps_lcell_comb is generic( family : string := "Stratix V"; lut_mask : vl_logic_vector(0 to 63) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0); dont_touch : string := "on" ); port( dataa : in vl_logic; datab : in vl_logic; datac : in vl_logic; datad : in vl_logic; datae : in vl_logic; dataf : in vl_logic; combout : out vl_logic ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of family : constant is 1; attribute mti_svvh_generic_type of lut_mask : constant is 1; attribute mti_svvh_generic_type of dont_touch : constant is 1; end pll_dps_lcell_comb;
library verilog; use verilog.vl_types.all; entity pll_dps_lcell_comb is generic( family : string := "Stratix V"; lut_mask : vl_logic_vector(0 to 63) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0); dont_touch : string := "on" ); port( dataa : in vl_logic; datab : in vl_logic; datac : in vl_logic; datad : in vl_logic; datae : in vl_logic; dataf : in vl_logic; combout : out vl_logic ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of family : constant is 1; attribute mti_svvh_generic_type of lut_mask : constant is 1; attribute mti_svvh_generic_type of dont_touch : constant is 1; end pll_dps_lcell_comb;
library verilog; use verilog.vl_types.all; entity pll_dps_lcell_comb is generic( family : string := "Stratix V"; lut_mask : vl_logic_vector(0 to 63) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0); dont_touch : string := "on" ); port( dataa : in vl_logic; datab : in vl_logic; datac : in vl_logic; datad : in vl_logic; datae : in vl_logic; dataf : in vl_logic; combout : out vl_logic ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of family : constant is 1; attribute mti_svvh_generic_type of lut_mask : constant is 1; attribute mti_svvh_generic_type of dont_touch : constant is 1; end pll_dps_lcell_comb;
library verilog; use verilog.vl_types.all; entity pll_dps_lcell_comb is generic( family : string := "Stratix V"; lut_mask : vl_logic_vector(0 to 63) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0); dont_touch : string := "on" ); port( dataa : in vl_logic; datab : in vl_logic; datac : in vl_logic; datad : in vl_logic; datae : in vl_logic; dataf : in vl_logic; combout : out vl_logic ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of family : constant is 1; attribute mti_svvh_generic_type of lut_mask : constant is 1; attribute mti_svvh_generic_type of dont_touch : constant is 1; end pll_dps_lcell_comb;
library verilog; use verilog.vl_types.all; entity EX_MEM is port( Clk : in vl_logic; stall : in vl_logic; flush : in vl_logic; Branch_addr_EX : in vl_logic_vector(31 downto 0); op_EX : in vl_logic_vector(5 downto 0); Condition_EX : in vl_logic_vector(2 downto 0); Branch_EX : in vl_logic; MemWrite_EX : in vl_logic; RegWrite_EX : in vl_logic; MemRead_EX : in vl_logic; MemData_EX : in vl_logic_vector(31 downto 0); WBData_EX : in vl_logic_vector(31 downto 0); Less_EX : in vl_logic; Zero_EX : in vl_logic; Overflow_EX : in vl_logic; Rd_EX : in vl_logic_vector(4 downto 0); Branch_addr_MEM : out vl_logic_vector(31 downto 0); op_MEM : out vl_logic_vector(5 downto 0); Condition_MEM : out vl_logic_vector(2 downto 0); Branch_MEM : out vl_logic; MemWrite_MEM : out vl_logic; RegWrite_MEM : out vl_logic; MemRead_MEM : out vl_logic; MemData_MEM : out vl_logic_vector(31 downto 0); WBData_MEM : out vl_logic_vector(31 downto 0); Less_MEM : out vl_logic; Zero_MEM : out vl_logic; Overflow_MEM : out vl_logic; Rd_MEM : out vl_logic_vector(4 downto 0) ); end EX_MEM;
---- -- Original author: Blake Johnson -- Copyright 2015,2016 Raytheon BBN Technologies -- -- A basic down counter. ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity DownCounter is generic ( nbits : natural := 8 ); port ( clk : in std_logic; rst : in std_logic; en : in std_logic; load_value : in std_logic_vector(nbits-1 downto 0); load : in std_logic; Q : out std_logic_vector(nbits-1 downto 0) ); end DownCounter; architecture arch of DownCounter is signal value : std_logic_vector(nbits-1 downto 0) := (others => '0'); begin Q <= value; main: process ( clk ) begin if rising_edge(clk) then if rst = '1' then value <= (others => '0'); else if load = '1' then value <= load_value; elsif en = '1' then value <= std_logic_vector(unsigned(value) - 1); end if; end if; end if; end process; end arch;
------------------------------------------------------------------------------- -- axi_datamover_mm2s_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_full_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Full Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset; use axi_datamover_v5_1.axi_datamover_cmd_status; use axi_datamover_v5_1.axi_datamover_pcc; use axi_datamover_v5_1.axi_datamover_addr_cntl; use axi_datamover_v5_1.axi_datamover_rddata_cntl; use axi_datamover_v5_1.axi_datamover_rd_status_cntl; use axi_datamover_v5_1.axi_datamover_mm2s_dre; Use axi_datamover_v5_1.axi_datamover_rd_sf; use axi_datamover_v5_1.axi_datamover_skid_buf; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_full_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 1; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Lite MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the incllusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit Store and Forward -- 1 = Include Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input --------------------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- MM2S Halt request input control -------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Error discrete output ------------------------------------ mm2s_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------- -- Optional MM2S Command and Status Clock and Reset --------- -- Used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ---------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- --------------------------------------------------------------- -- Address Posting contols ------------------------------------ mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- --------------------------------------------------------------- -- MM2S AXI Address Channel I/O --------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------ -- Currently unsupported AXI Address Channel output signals ------------ -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------------ -- MM2S AXI MMap Read Data Channel I/O ----------------------------------------- mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- --------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- ---------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------ ); end entity axi_datamover_mm2s_full_wrap; architecture implementation of axi_datamover_mm2s_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_rdmux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Read data mux select control. -- ------------------------------------------------------------------- function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_rdmux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin If (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else -- no DRE align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => -- 128 ratio fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for MM2S -- modules upstream from the downsizing Store and Forward. If -- Store and Forward is present, then the effective native width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Native Data width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled = 1) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; -- Constant Declarations ---------------------------------------- Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH, C_MM2S_SDATA_WIDTH, C_INCLUDE_MM2S_GP_SF); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S; Constant IS_MM2S : integer range 0 to 1 := 1; Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID; Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH; Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH; Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH; Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH; Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32); Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO; Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH; Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC; Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE; Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH); Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED; Constant NO_INDET_BTT : integer range 0 to 1 := 0; Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE, C_MM2S_SDATA_WIDTH); Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE, C_MM2S_SDATA_WIDTH); -- Calculates the minimum needed depth of the Store and Forward FIFO -- based on the MM2S pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) MM2S_BURST_SIZE; -- Assigns the depth of the optional Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH, MM2S_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_cmplt : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2rsc_calc_error : std_logic := '0'; signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2rsc_calc_err : std_logic := '0'; signal sig_data2rsc_okay : std_logic := '0'; signal sig_data2rsc_decerr : std_logic := '0'; signal sig_data2rsc_slverr : std_logic := '0'; signal sig_data2rsc_cmd_cmplt : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_data2rsc_valid : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2rsc_status_ready : std_logic := '0'; signal sig_rsc2stat_status_valid : std_logic := '0'; signal sig_rsc2mstr_halt_pipe : std_logic := '0'; signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2rdc_wready : std_logic := '0'; signal sig_rdc2sf_wvalid : std_logic := '0'; signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_rdc2sf_wlast : std_logic := '0'; signal sig_skid2dre_wready : std_logic := '0'; signal sig_dre2skid_wvalid : std_logic := '0'; signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2skid_wlast : std_logic := '0'; signal sig_dre2sf_wready : std_logic := '0'; signal sig_sf2dre_wvalid : std_logic := '0'; signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_sf2dre_wlast : std_logic := '0'; signal sig_rdc2dre_new_align : std_logic := '0'; signal sig_rdc2dre_use_autodest : std_logic := '0'; signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_flush : std_logic := '0'; signal sig_sf2dre_new_align : std_logic := '0'; signal sig_sf2dre_use_autodest : std_logic := '0'; signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_flush : std_logic := '0'; signal sig_dre_new_align : std_logic := '0'; signal sig_dre_use_autodest : std_logic := '0'; signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_sf_allow_addr_req : std_logic := '0'; signal sig_mm2s_allow_addr_req : std_logic := '0'; signal sig_addr_req_posted : std_logic := '0'; signal sig_rd_xfer_cmplt : std_logic := '0'; signal sig_sf2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2sf_cmd_valid : std_logic := '0'; signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2sf_drr : std_logic := '0'; signal sig_mstr2sf_eof : std_logic := '0'; signal sig_mstr2sf_calc_error : std_logic := '0'; signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_data2sf_cmd_cmplt : std_logic := '0'; signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal mm2s_arcache_int : std_logic_vector (3 downto 0); signal mm2s_aruser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug vector output mm2s_dbg_data <= sig_dbg_data_mux_out; -- Note that only the mm2s_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (mm2s_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2rsc_status_ready; sig_dbg_data_1(7) <= sig_rsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake -- Spare bits in debug1 sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc -- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values sig_cache_data <= mm2s_cmd_wdata(79 downto 72); -- This is the xUser and xCache values end generate GEN_CACHE2; -- Internal error output discrete ------------------------------ mm2s_err <= sig_calc2dm_calc_err; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ) port map ( primary_aclk => mm2s_aclk , primary_aresetn => mm2s_aresetn , secondary_awclk => mm2s_cmdsts_awclk , secondary_aresetn => mm2s_cmdsts_aresetn , halt_req => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => LOGIC_HIGH , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO , C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_STS_WIDTH => MM2S_STS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , secondary_awclk => mm2s_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => mm2s_cmd_wvalid , cmd_wready => mm2s_cmd_wready , cmd_wdata => sig_mm2s_cmd_wdata , cache_data => sig_cache_data , sts_wvalid => mm2s_sts_wvalid , sts_wready => mm2s_sts_wready , sts_wdata => mm2s_sts_wdata , sts_wstrb => mm2s_sts_wstrb , sts_wlast => mm2s_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_rsc2stat_status , stat2mstr_status_ready => sig_stat2rsc_status_ready , mst2stst_status_valid => sig_rsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_RD_STATUS_CNTLR -- -- Description: -- Read Status Controller Block -- ------------------------------------------------------------ I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl generic map ( C_STS_WIDTH => MM2S_STS_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , calc2rsc_calc_error => sig_calc2dm_calc_err , addr2rsc_calc_error => sig_addr2rsc_calc_error , addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty , data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_error => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2stat_status => sig_rsc2stat_status , stat2rsc_status_ready => sig_stat2rsc_status_ready , rsc2stat_status_valid => sig_rsc2stat_status_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_MM2S , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_BTT_USED => MM2S_BTT_USED , C_SUPPORT_INDET_BTT => NO_INDET_BTT , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_btt => sig_mstr2sf_btt , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_cmd_cmplt => open , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset ); ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_ADDR_ID => MM2S_ARID_VALUE , C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => mm2s_arid , addr2axi_aaddr => mm2s_araddr , addr2axi_alen => mm2s_arlen , addr2axi_asize => mm2s_arsize , addr2axi_aburst => mm2s_arburst , addr2axi_aprot => mm2s_arprot , addr2axi_avalid => mm2s_arvalid , addr2axi_acache => mm2s_arcache_int , addr2axi_auser => mm2s_aruser_int , axi2addr_aready => mm2s_arready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_mm2s_allow_addr_req , addr_req_posted => sig_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => LOGIC_LOW , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2rsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_RD_DATA_CNTL -- -- Description: -- Read Data Controller Block -- ------------------------------------------------------------ I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl generic map ( C_INCLUDE_DRE => INCLUDE_DRE , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset ----------------------------------- primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , -- Soft Shutdown Interface ----------------------------- rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , -- External Address Pipelining Contol support mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt , -- AXI Read Data Channel I/O ------------------------------- mm2s_rdata => mm2s_rdata , mm2s_rresp => mm2s_rresp , mm2s_rlast => mm2s_rlast , mm2s_rvalid => mm2s_rvalid , mm2s_rready => mm2s_rready , -- MM2S DRE Control ----------------------------------- mm2s_dre_new_align => sig_rdc2dre_new_align , mm2s_dre_use_autodest => sig_rdc2dre_use_autodest , mm2s_dre_src_align => sig_rdc2dre_src_align , mm2s_dre_dest_align => sig_rdc2dre_dest_align , mm2s_dre_flush => sig_rdc2dre_flush , -- AXI Master Stream ----------------------------------- mm2s_strm_wvalid => sig_rdc2sf_wvalid , mm2s_strm_wready => sig_sf2rdc_wready , mm2s_strm_wdata => sig_rdc2sf_wdata , mm2s_strm_wstrb => sig_rdc2sf_wstrb , mm2s_strm_wlast => sig_rdc2sf_wlast , -- MM2S Store and Forward Supplimental Control ---------- mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , -- Command Calculator Interface -------------------------- mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , -- Address Controller Interface -------------------------- addr2data_addr_posted => sig_addr2data_addr_posted , -- Data Controller Halted Status data2all_dcntlr_halted => sig_data2all_dcntlr_halted , -- Output Stream Skid Buffer Halt control data2skid_halt => sig_data2skid_halt , -- Read Status Controller Interface -------------------------- data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_err => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_SF -- -- If Generate Description: -- Include the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate begin -- Merge external address posting control with the -- Store and Forward address posting control sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and mm2s_allow_addr_req; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; sig_dre_new_align <= sig_sf2dre_new_align ; sig_dre_use_autodest <= sig_sf2dre_use_autodest ; sig_dre_src_align <= sig_sf2dre_src_align ; sig_dre_dest_align <= sig_sf2dre_dest_align ; sig_dre_flush <= sig_sf2dre_flush ; ------------------------------------------------------------ -- Instance: I_RD_SF -- -- Description: -- Instance for the MM2S Store and Forward module with -- downsizer support. -- ------------------------------------------------------------ I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_DRE_IS_USED => INCLUDE_DRE , C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ------------------------------- aclk => mm2s_aclk , reset => sig_mmap_rst , -- DataMover Read Side Address Pipelining Control Interface ok_to_post_rd_addr => sig_sf_allow_addr_req , rd_addr_posted => sig_addr_req_posted , rd_xfer_cmplt => sig_rd_xfer_cmplt , -- Read Side Stream In from DataMover MM2S Read Data Controller ----- sf2sin_tready => sig_sf2rdc_wready , sin2sf_tvalid => sig_rdc2sf_wvalid , sin2sf_tdata => sig_rdc2sf_wdata , sin2sf_tkeep => sig_rdc2sf_wstrb , sin2sf_tlast => sig_rdc2sf_wlast , -- RDC Store and Forward Supplimental Controls ---------- data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , data2sf_dre_flush => sig_rdc2dre_flush , -- DRE Control Interface from the Command Calculator ----------------------------- dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset , -- MM2S DRE Control ------------------------------------------------------------- sf2dre_new_align => sig_sf2dre_new_align , sf2dre_use_autodest => sig_sf2dre_use_autodest , sf2dre_src_align => sig_sf2dre_src_align , sf2dre_dest_align => sig_sf2dre_dest_align , sf2dre_flush => sig_sf2dre_flush , -- Stream Out ---------------------------------- sout2sf_tready => sig_dre2sf_wready , sf2sout_tvalid => sig_sf2dre_wvalid , sf2sout_tdata => sig_sf2dre_wdata , sf2sout_tkeep => sig_sf2dre_wstrb , sf2sout_tlast => sig_sf2dre_wlast ); -- ------------------------------------------------------------ -- -- Instance: I_RD_SF -- -- -- -- Description: -- -- Instance for the MM2S Store and Forward module. -- -- -- ------------------------------------------------------------ -- I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf -- generic map ( -- -- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , -- C_MAX_BURST_LEN => MM2S_BURST_SIZE , -- C_DRE_IS_USED => INCLUDE_DRE , -- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- -- -- Clock and Reset inputs ------------------------------- -- aclk => mm2s_aclk , -- reset => sig_mmap_rst , -- -- -- -- DataMover Read Side Address Pipelining Control Interface -- ok_to_post_rd_addr => sig_sf_allow_addr_req , -- rd_addr_posted => sig_addr_req_posted , -- rd_xfer_cmplt => sig_rd_xfer_cmplt , -- -- -- -- -- Read Side Stream In from DataMover MM2S ----- -- sf2sin_tready => sig_sf2dre_wready , -- sin2sf_tvalid => sig_dre2sf_wvalid , -- sin2sf_tdata => sig_dre2sf_wdata , -- sin2sf_tkeep => sig_dre2sf_wstrb , -- sin2sf_tlast => sig_dre2sf_wlast , -- -- -- -- -- Stream Out ---------------------------------- -- sout2sf_tready => sig_skid2sf_wready , -- sf2sout_tvalid => sig_sf2skid_wvalid , -- sf2sout_tdata => sig_sf2skid_wdata , -- sf2sout_tkeep => sig_sf2skid_wstrb , -- sf2sout_tlast => sig_sf2skid_wlast -- -- ); end generate GEN_INCLUDE_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_SF -- -- If Generate Description: -- Omit the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate begin -- Allow external address posting control -- Ignore Store and Forward Control sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ; sig_sf_allow_addr_req <= '0' ; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; -- DRE Control Bus (Connect to the Read data Controller) sig_dre_new_align <= sig_rdc2dre_new_align ; sig_dre_use_autodest <= sig_rdc2dre_use_autodest ; sig_dre_src_align <= sig_rdc2dre_src_align ; sig_dre_dest_align <= sig_rdc2dre_dest_align ; sig_dre_flush <= sig_rdc2dre_flush ; -- Just pass stream signals through sig_sf2rdc_wready <= sig_dre2sf_wready ; sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ; sig_sf2dre_wdata <= sig_rdc2sf_wdata ; sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ; sig_sf2dre_wlast <= sig_rdc2sf_wlast ; -- Always enable the DRE Cmd bus for loading to keep from -- stalling the PCC module sig_sf2mstr_cmd_ready <= LOGIC_HIGH; end generate GEN_NO_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_DRE -- -- If Generate Description: -- Include the MM2S DRE -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate begin ------------------------------------------------------------ -- Instance: I_DRE64 -- -- Description: -- Instance for the MM2S DRE whach can support widths of -- 16 bits to 64 bits. -- ------------------------------------------------------------ I_DRE_16_to_64 : entity axi_datamover_v5_1.axi_datamover_mm2s_dre generic map ( C_DWIDTH => MM2S_SDATA_WIDTH , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ) port map ( -- Control inputs dre_clk => mm2s_aclk , dre_rst => sig_stream_rst , dre_new_align => sig_dre_new_align , dre_use_autodest => sig_dre_use_autodest , dre_src_align => sig_dre_src_align , dre_dest_align => sig_dre_dest_align , dre_flush => sig_dre_flush , -- Stream Inputs dre_in_tstrb => sig_sf2dre_wstrb , dre_in_tdata => sig_sf2dre_wdata , dre_in_tlast => sig_sf2dre_wlast , dre_in_tvalid => sig_sf2dre_wvalid , dre_in_tready => sig_dre2sf_wready , -- Stream Outputs dre_out_tstrb => sig_dre2skid_wstrb , dre_out_tdata => sig_dre2skid_wdata , dre_out_tlast => sig_dre2skid_wlast , dre_out_tvalid => sig_dre2skid_wvalid , dre_out_tready => sig_skid2dre_wready ); end generate GEN_INCLUDE_MM2S_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_DRE -- -- If Generate Description: -- Omit the MM2S DRE and housekeep the signals that it -- needs to output. -- ------------------------------------------------------------ GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate begin -- Just pass stream signals through from the Store -- and Forward module sig_dre2sf_wready <= sig_skid2dre_wready ; sig_dre2skid_wvalid <= sig_sf2dre_wvalid ; sig_dre2skid_wdata <= sig_sf2dre_wdata ; sig_dre2skid_wstrb <= sig_sf2dre_wstrb ; sig_dre2skid_wlast <= sig_sf2dre_wlast ; end generate GEN_NO_MM2S_DRE; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate begin ------------------------------------------------------------ -- Instance: I_MM2S_SKID_BUF -- -- Description: -- Instance for the MM2S Skid Buffer which provides for -- registerd Master Stream outputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => MM2S_SDATA_WIDTH ) port map ( -- System Ports aclk => mm2s_aclk , arst => sig_stream_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => sig_dre2skid_wvalid , s_ready => sig_skid2dre_wready , s_data => sig_dre2skid_wdata , s_strb => sig_dre2skid_wstrb , s_last => sig_dre2skid_wlast , -- Master Side (Stream Data Output m_valid => mm2s_strm_wvalid , m_ready => mm2s_strm_wready , m_data => mm2s_strm_wdata , m_strb => mm2s_strm_wstrb , m_last => mm2s_strm_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate begin mm2s_strm_wvalid <= sig_dre2skid_wvalid; sig_skid2dre_wready <= mm2s_strm_wready; mm2s_strm_wdata <= sig_dre2skid_wdata; mm2s_strm_wstrb <= sig_dre2skid_wstrb; mm2s_strm_wlast <= sig_dre2skid_wlast; end generate DISABLE_AXIS_SKID; end implementation;
------------------------------------------------------------------------------- -- axi_datamover_mm2s_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_full_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Full Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset; use axi_datamover_v5_1.axi_datamover_cmd_status; use axi_datamover_v5_1.axi_datamover_pcc; use axi_datamover_v5_1.axi_datamover_addr_cntl; use axi_datamover_v5_1.axi_datamover_rddata_cntl; use axi_datamover_v5_1.axi_datamover_rd_status_cntl; use axi_datamover_v5_1.axi_datamover_mm2s_dre; Use axi_datamover_v5_1.axi_datamover_rd_sf; use axi_datamover_v5_1.axi_datamover_skid_buf; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_full_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 1; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Lite MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the incllusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit Store and Forward -- 1 = Include Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input --------------------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- MM2S Halt request input control -------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Error discrete output ------------------------------------ mm2s_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------- -- Optional MM2S Command and Status Clock and Reset --------- -- Used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ---------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- --------------------------------------------------------------- -- Address Posting contols ------------------------------------ mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- --------------------------------------------------------------- -- MM2S AXI Address Channel I/O --------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------ -- Currently unsupported AXI Address Channel output signals ------------ -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------------ -- MM2S AXI MMap Read Data Channel I/O ----------------------------------------- mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- --------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- ---------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------ ); end entity axi_datamover_mm2s_full_wrap; architecture implementation of axi_datamover_mm2s_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_rdmux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Read data mux select control. -- ------------------------------------------------------------------- function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_rdmux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin If (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else -- no DRE align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => -- 128 ratio fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for MM2S -- modules upstream from the downsizing Store and Forward. If -- Store and Forward is present, then the effective native width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Native Data width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled = 1) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; -- Constant Declarations ---------------------------------------- Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH, C_MM2S_SDATA_WIDTH, C_INCLUDE_MM2S_GP_SF); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S; Constant IS_MM2S : integer range 0 to 1 := 1; Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID; Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH; Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH; Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH; Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH; Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32); Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO; Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH; Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC; Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE; Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH); Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED; Constant NO_INDET_BTT : integer range 0 to 1 := 0; Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE, C_MM2S_SDATA_WIDTH); Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE, C_MM2S_SDATA_WIDTH); -- Calculates the minimum needed depth of the Store and Forward FIFO -- based on the MM2S pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) MM2S_BURST_SIZE; -- Assigns the depth of the optional Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH, MM2S_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_cmplt : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2rsc_calc_error : std_logic := '0'; signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2rsc_calc_err : std_logic := '0'; signal sig_data2rsc_okay : std_logic := '0'; signal sig_data2rsc_decerr : std_logic := '0'; signal sig_data2rsc_slverr : std_logic := '0'; signal sig_data2rsc_cmd_cmplt : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_data2rsc_valid : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2rsc_status_ready : std_logic := '0'; signal sig_rsc2stat_status_valid : std_logic := '0'; signal sig_rsc2mstr_halt_pipe : std_logic := '0'; signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2rdc_wready : std_logic := '0'; signal sig_rdc2sf_wvalid : std_logic := '0'; signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_rdc2sf_wlast : std_logic := '0'; signal sig_skid2dre_wready : std_logic := '0'; signal sig_dre2skid_wvalid : std_logic := '0'; signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2skid_wlast : std_logic := '0'; signal sig_dre2sf_wready : std_logic := '0'; signal sig_sf2dre_wvalid : std_logic := '0'; signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_sf2dre_wlast : std_logic := '0'; signal sig_rdc2dre_new_align : std_logic := '0'; signal sig_rdc2dre_use_autodest : std_logic := '0'; signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_flush : std_logic := '0'; signal sig_sf2dre_new_align : std_logic := '0'; signal sig_sf2dre_use_autodest : std_logic := '0'; signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_flush : std_logic := '0'; signal sig_dre_new_align : std_logic := '0'; signal sig_dre_use_autodest : std_logic := '0'; signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_sf_allow_addr_req : std_logic := '0'; signal sig_mm2s_allow_addr_req : std_logic := '0'; signal sig_addr_req_posted : std_logic := '0'; signal sig_rd_xfer_cmplt : std_logic := '0'; signal sig_sf2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2sf_cmd_valid : std_logic := '0'; signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2sf_drr : std_logic := '0'; signal sig_mstr2sf_eof : std_logic := '0'; signal sig_mstr2sf_calc_error : std_logic := '0'; signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_data2sf_cmd_cmplt : std_logic := '0'; signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal mm2s_arcache_int : std_logic_vector (3 downto 0); signal mm2s_aruser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug vector output mm2s_dbg_data <= sig_dbg_data_mux_out; -- Note that only the mm2s_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (mm2s_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2rsc_status_ready; sig_dbg_data_1(7) <= sig_rsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake -- Spare bits in debug1 sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc -- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values sig_cache_data <= mm2s_cmd_wdata(79 downto 72); -- This is the xUser and xCache values end generate GEN_CACHE2; -- Internal error output discrete ------------------------------ mm2s_err <= sig_calc2dm_calc_err; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ) port map ( primary_aclk => mm2s_aclk , primary_aresetn => mm2s_aresetn , secondary_awclk => mm2s_cmdsts_awclk , secondary_aresetn => mm2s_cmdsts_aresetn , halt_req => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => LOGIC_HIGH , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO , C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_STS_WIDTH => MM2S_STS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , secondary_awclk => mm2s_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => mm2s_cmd_wvalid , cmd_wready => mm2s_cmd_wready , cmd_wdata => sig_mm2s_cmd_wdata , cache_data => sig_cache_data , sts_wvalid => mm2s_sts_wvalid , sts_wready => mm2s_sts_wready , sts_wdata => mm2s_sts_wdata , sts_wstrb => mm2s_sts_wstrb , sts_wlast => mm2s_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_rsc2stat_status , stat2mstr_status_ready => sig_stat2rsc_status_ready , mst2stst_status_valid => sig_rsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_RD_STATUS_CNTLR -- -- Description: -- Read Status Controller Block -- ------------------------------------------------------------ I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl generic map ( C_STS_WIDTH => MM2S_STS_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , calc2rsc_calc_error => sig_calc2dm_calc_err , addr2rsc_calc_error => sig_addr2rsc_calc_error , addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty , data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_error => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2stat_status => sig_rsc2stat_status , stat2rsc_status_ready => sig_stat2rsc_status_ready , rsc2stat_status_valid => sig_rsc2stat_status_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_MM2S , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_BTT_USED => MM2S_BTT_USED , C_SUPPORT_INDET_BTT => NO_INDET_BTT , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_btt => sig_mstr2sf_btt , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_cmd_cmplt => open , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset ); ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_ADDR_ID => MM2S_ARID_VALUE , C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => mm2s_arid , addr2axi_aaddr => mm2s_araddr , addr2axi_alen => mm2s_arlen , addr2axi_asize => mm2s_arsize , addr2axi_aburst => mm2s_arburst , addr2axi_aprot => mm2s_arprot , addr2axi_avalid => mm2s_arvalid , addr2axi_acache => mm2s_arcache_int , addr2axi_auser => mm2s_aruser_int , axi2addr_aready => mm2s_arready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_mm2s_allow_addr_req , addr_req_posted => sig_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => LOGIC_LOW , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2rsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_RD_DATA_CNTL -- -- Description: -- Read Data Controller Block -- ------------------------------------------------------------ I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl generic map ( C_INCLUDE_DRE => INCLUDE_DRE , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset ----------------------------------- primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , -- Soft Shutdown Interface ----------------------------- rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , -- External Address Pipelining Contol support mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt , -- AXI Read Data Channel I/O ------------------------------- mm2s_rdata => mm2s_rdata , mm2s_rresp => mm2s_rresp , mm2s_rlast => mm2s_rlast , mm2s_rvalid => mm2s_rvalid , mm2s_rready => mm2s_rready , -- MM2S DRE Control ----------------------------------- mm2s_dre_new_align => sig_rdc2dre_new_align , mm2s_dre_use_autodest => sig_rdc2dre_use_autodest , mm2s_dre_src_align => sig_rdc2dre_src_align , mm2s_dre_dest_align => sig_rdc2dre_dest_align , mm2s_dre_flush => sig_rdc2dre_flush , -- AXI Master Stream ----------------------------------- mm2s_strm_wvalid => sig_rdc2sf_wvalid , mm2s_strm_wready => sig_sf2rdc_wready , mm2s_strm_wdata => sig_rdc2sf_wdata , mm2s_strm_wstrb => sig_rdc2sf_wstrb , mm2s_strm_wlast => sig_rdc2sf_wlast , -- MM2S Store and Forward Supplimental Control ---------- mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , -- Command Calculator Interface -------------------------- mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , -- Address Controller Interface -------------------------- addr2data_addr_posted => sig_addr2data_addr_posted , -- Data Controller Halted Status data2all_dcntlr_halted => sig_data2all_dcntlr_halted , -- Output Stream Skid Buffer Halt control data2skid_halt => sig_data2skid_halt , -- Read Status Controller Interface -------------------------- data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_err => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_SF -- -- If Generate Description: -- Include the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate begin -- Merge external address posting control with the -- Store and Forward address posting control sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and mm2s_allow_addr_req; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; sig_dre_new_align <= sig_sf2dre_new_align ; sig_dre_use_autodest <= sig_sf2dre_use_autodest ; sig_dre_src_align <= sig_sf2dre_src_align ; sig_dre_dest_align <= sig_sf2dre_dest_align ; sig_dre_flush <= sig_sf2dre_flush ; ------------------------------------------------------------ -- Instance: I_RD_SF -- -- Description: -- Instance for the MM2S Store and Forward module with -- downsizer support. -- ------------------------------------------------------------ I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_DRE_IS_USED => INCLUDE_DRE , C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ------------------------------- aclk => mm2s_aclk , reset => sig_mmap_rst , -- DataMover Read Side Address Pipelining Control Interface ok_to_post_rd_addr => sig_sf_allow_addr_req , rd_addr_posted => sig_addr_req_posted , rd_xfer_cmplt => sig_rd_xfer_cmplt , -- Read Side Stream In from DataMover MM2S Read Data Controller ----- sf2sin_tready => sig_sf2rdc_wready , sin2sf_tvalid => sig_rdc2sf_wvalid , sin2sf_tdata => sig_rdc2sf_wdata , sin2sf_tkeep => sig_rdc2sf_wstrb , sin2sf_tlast => sig_rdc2sf_wlast , -- RDC Store and Forward Supplimental Controls ---------- data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , data2sf_dre_flush => sig_rdc2dre_flush , -- DRE Control Interface from the Command Calculator ----------------------------- dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset , -- MM2S DRE Control ------------------------------------------------------------- sf2dre_new_align => sig_sf2dre_new_align , sf2dre_use_autodest => sig_sf2dre_use_autodest , sf2dre_src_align => sig_sf2dre_src_align , sf2dre_dest_align => sig_sf2dre_dest_align , sf2dre_flush => sig_sf2dre_flush , -- Stream Out ---------------------------------- sout2sf_tready => sig_dre2sf_wready , sf2sout_tvalid => sig_sf2dre_wvalid , sf2sout_tdata => sig_sf2dre_wdata , sf2sout_tkeep => sig_sf2dre_wstrb , sf2sout_tlast => sig_sf2dre_wlast ); -- ------------------------------------------------------------ -- -- Instance: I_RD_SF -- -- -- -- Description: -- -- Instance for the MM2S Store and Forward module. -- -- -- ------------------------------------------------------------ -- I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf -- generic map ( -- -- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , -- C_MAX_BURST_LEN => MM2S_BURST_SIZE , -- C_DRE_IS_USED => INCLUDE_DRE , -- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- -- -- Clock and Reset inputs ------------------------------- -- aclk => mm2s_aclk , -- reset => sig_mmap_rst , -- -- -- -- DataMover Read Side Address Pipelining Control Interface -- ok_to_post_rd_addr => sig_sf_allow_addr_req , -- rd_addr_posted => sig_addr_req_posted , -- rd_xfer_cmplt => sig_rd_xfer_cmplt , -- -- -- -- -- Read Side Stream In from DataMover MM2S ----- -- sf2sin_tready => sig_sf2dre_wready , -- sin2sf_tvalid => sig_dre2sf_wvalid , -- sin2sf_tdata => sig_dre2sf_wdata , -- sin2sf_tkeep => sig_dre2sf_wstrb , -- sin2sf_tlast => sig_dre2sf_wlast , -- -- -- -- -- Stream Out ---------------------------------- -- sout2sf_tready => sig_skid2sf_wready , -- sf2sout_tvalid => sig_sf2skid_wvalid , -- sf2sout_tdata => sig_sf2skid_wdata , -- sf2sout_tkeep => sig_sf2skid_wstrb , -- sf2sout_tlast => sig_sf2skid_wlast -- -- ); end generate GEN_INCLUDE_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_SF -- -- If Generate Description: -- Omit the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate begin -- Allow external address posting control -- Ignore Store and Forward Control sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ; sig_sf_allow_addr_req <= '0' ; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; -- DRE Control Bus (Connect to the Read data Controller) sig_dre_new_align <= sig_rdc2dre_new_align ; sig_dre_use_autodest <= sig_rdc2dre_use_autodest ; sig_dre_src_align <= sig_rdc2dre_src_align ; sig_dre_dest_align <= sig_rdc2dre_dest_align ; sig_dre_flush <= sig_rdc2dre_flush ; -- Just pass stream signals through sig_sf2rdc_wready <= sig_dre2sf_wready ; sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ; sig_sf2dre_wdata <= sig_rdc2sf_wdata ; sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ; sig_sf2dre_wlast <= sig_rdc2sf_wlast ; -- Always enable the DRE Cmd bus for loading to keep from -- stalling the PCC module sig_sf2mstr_cmd_ready <= LOGIC_HIGH; end generate GEN_NO_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_DRE -- -- If Generate Description: -- Include the MM2S DRE -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate begin ------------------------------------------------------------ -- Instance: I_DRE64 -- -- Description: -- Instance for the MM2S DRE whach can support widths of -- 16 bits to 64 bits. -- ------------------------------------------------------------ I_DRE_16_to_64 : entity axi_datamover_v5_1.axi_datamover_mm2s_dre generic map ( C_DWIDTH => MM2S_SDATA_WIDTH , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ) port map ( -- Control inputs dre_clk => mm2s_aclk , dre_rst => sig_stream_rst , dre_new_align => sig_dre_new_align , dre_use_autodest => sig_dre_use_autodest , dre_src_align => sig_dre_src_align , dre_dest_align => sig_dre_dest_align , dre_flush => sig_dre_flush , -- Stream Inputs dre_in_tstrb => sig_sf2dre_wstrb , dre_in_tdata => sig_sf2dre_wdata , dre_in_tlast => sig_sf2dre_wlast , dre_in_tvalid => sig_sf2dre_wvalid , dre_in_tready => sig_dre2sf_wready , -- Stream Outputs dre_out_tstrb => sig_dre2skid_wstrb , dre_out_tdata => sig_dre2skid_wdata , dre_out_tlast => sig_dre2skid_wlast , dre_out_tvalid => sig_dre2skid_wvalid , dre_out_tready => sig_skid2dre_wready ); end generate GEN_INCLUDE_MM2S_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_DRE -- -- If Generate Description: -- Omit the MM2S DRE and housekeep the signals that it -- needs to output. -- ------------------------------------------------------------ GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate begin -- Just pass stream signals through from the Store -- and Forward module sig_dre2sf_wready <= sig_skid2dre_wready ; sig_dre2skid_wvalid <= sig_sf2dre_wvalid ; sig_dre2skid_wdata <= sig_sf2dre_wdata ; sig_dre2skid_wstrb <= sig_sf2dre_wstrb ; sig_dre2skid_wlast <= sig_sf2dre_wlast ; end generate GEN_NO_MM2S_DRE; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate begin ------------------------------------------------------------ -- Instance: I_MM2S_SKID_BUF -- -- Description: -- Instance for the MM2S Skid Buffer which provides for -- registerd Master Stream outputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => MM2S_SDATA_WIDTH ) port map ( -- System Ports aclk => mm2s_aclk , arst => sig_stream_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => sig_dre2skid_wvalid , s_ready => sig_skid2dre_wready , s_data => sig_dre2skid_wdata , s_strb => sig_dre2skid_wstrb , s_last => sig_dre2skid_wlast , -- Master Side (Stream Data Output m_valid => mm2s_strm_wvalid , m_ready => mm2s_strm_wready , m_data => mm2s_strm_wdata , m_strb => mm2s_strm_wstrb , m_last => mm2s_strm_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate begin mm2s_strm_wvalid <= sig_dre2skid_wvalid; sig_skid2dre_wready <= mm2s_strm_wready; mm2s_strm_wdata <= sig_dre2skid_wdata; mm2s_strm_wstrb <= sig_dre2skid_wstrb; mm2s_strm_wlast <= sig_dre2skid_wlast; end generate DISABLE_AXIS_SKID; end implementation;
------------------------------------------------------------------------------- -- axi_datamover_mm2s_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_full_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Full Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset; use axi_datamover_v5_1.axi_datamover_cmd_status; use axi_datamover_v5_1.axi_datamover_pcc; use axi_datamover_v5_1.axi_datamover_addr_cntl; use axi_datamover_v5_1.axi_datamover_rddata_cntl; use axi_datamover_v5_1.axi_datamover_rd_status_cntl; use axi_datamover_v5_1.axi_datamover_mm2s_dre; Use axi_datamover_v5_1.axi_datamover_rd_sf; use axi_datamover_v5_1.axi_datamover_skid_buf; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_full_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 1; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Lite MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the incllusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit Store and Forward -- 1 = Include Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input --------------------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- MM2S Halt request input control -------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Error discrete output ------------------------------------ mm2s_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------- -- Optional MM2S Command and Status Clock and Reset --------- -- Used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ---------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- --------------------------------------------------------------- -- Address Posting contols ------------------------------------ mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- --------------------------------------------------------------- -- MM2S AXI Address Channel I/O --------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------ -- Currently unsupported AXI Address Channel output signals ------------ -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------------ -- MM2S AXI MMap Read Data Channel I/O ----------------------------------------- mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- --------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- ---------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------ ); end entity axi_datamover_mm2s_full_wrap; architecture implementation of axi_datamover_mm2s_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_rdmux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Read data mux select control. -- ------------------------------------------------------------------- function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_rdmux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin If (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else -- no DRE align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => -- 128 ratio fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for MM2S -- modules upstream from the downsizing Store and Forward. If -- Store and Forward is present, then the effective native width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Native Data width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled = 1) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; -- Constant Declarations ---------------------------------------- Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH, C_MM2S_SDATA_WIDTH, C_INCLUDE_MM2S_GP_SF); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S; Constant IS_MM2S : integer range 0 to 1 := 1; Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID; Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH; Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH; Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH; Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH; Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32); Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO; Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH; Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC; Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE; Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH); Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED; Constant NO_INDET_BTT : integer range 0 to 1 := 0; Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE, C_MM2S_SDATA_WIDTH); Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE, C_MM2S_SDATA_WIDTH); -- Calculates the minimum needed depth of the Store and Forward FIFO -- based on the MM2S pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) MM2S_BURST_SIZE; -- Assigns the depth of the optional Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH, MM2S_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_cmplt : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2rsc_calc_error : std_logic := '0'; signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2rsc_calc_err : std_logic := '0'; signal sig_data2rsc_okay : std_logic := '0'; signal sig_data2rsc_decerr : std_logic := '0'; signal sig_data2rsc_slverr : std_logic := '0'; signal sig_data2rsc_cmd_cmplt : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_data2rsc_valid : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2rsc_status_ready : std_logic := '0'; signal sig_rsc2stat_status_valid : std_logic := '0'; signal sig_rsc2mstr_halt_pipe : std_logic := '0'; signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2rdc_wready : std_logic := '0'; signal sig_rdc2sf_wvalid : std_logic := '0'; signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_rdc2sf_wlast : std_logic := '0'; signal sig_skid2dre_wready : std_logic := '0'; signal sig_dre2skid_wvalid : std_logic := '0'; signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2skid_wlast : std_logic := '0'; signal sig_dre2sf_wready : std_logic := '0'; signal sig_sf2dre_wvalid : std_logic := '0'; signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_sf2dre_wlast : std_logic := '0'; signal sig_rdc2dre_new_align : std_logic := '0'; signal sig_rdc2dre_use_autodest : std_logic := '0'; signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_flush : std_logic := '0'; signal sig_sf2dre_new_align : std_logic := '0'; signal sig_sf2dre_use_autodest : std_logic := '0'; signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_flush : std_logic := '0'; signal sig_dre_new_align : std_logic := '0'; signal sig_dre_use_autodest : std_logic := '0'; signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_sf_allow_addr_req : std_logic := '0'; signal sig_mm2s_allow_addr_req : std_logic := '0'; signal sig_addr_req_posted : std_logic := '0'; signal sig_rd_xfer_cmplt : std_logic := '0'; signal sig_sf2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2sf_cmd_valid : std_logic := '0'; signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2sf_drr : std_logic := '0'; signal sig_mstr2sf_eof : std_logic := '0'; signal sig_mstr2sf_calc_error : std_logic := '0'; signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_data2sf_cmd_cmplt : std_logic := '0'; signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal mm2s_arcache_int : std_logic_vector (3 downto 0); signal mm2s_aruser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug vector output mm2s_dbg_data <= sig_dbg_data_mux_out; -- Note that only the mm2s_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (mm2s_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2rsc_status_ready; sig_dbg_data_1(7) <= sig_rsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake -- Spare bits in debug1 sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc -- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values sig_cache_data <= mm2s_cmd_wdata(79 downto 72); -- This is the xUser and xCache values end generate GEN_CACHE2; -- Internal error output discrete ------------------------------ mm2s_err <= sig_calc2dm_calc_err; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ) port map ( primary_aclk => mm2s_aclk , primary_aresetn => mm2s_aresetn , secondary_awclk => mm2s_cmdsts_awclk , secondary_aresetn => mm2s_cmdsts_aresetn , halt_req => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => LOGIC_HIGH , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO , C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_STS_WIDTH => MM2S_STS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , secondary_awclk => mm2s_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => mm2s_cmd_wvalid , cmd_wready => mm2s_cmd_wready , cmd_wdata => sig_mm2s_cmd_wdata , cache_data => sig_cache_data , sts_wvalid => mm2s_sts_wvalid , sts_wready => mm2s_sts_wready , sts_wdata => mm2s_sts_wdata , sts_wstrb => mm2s_sts_wstrb , sts_wlast => mm2s_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_rsc2stat_status , stat2mstr_status_ready => sig_stat2rsc_status_ready , mst2stst_status_valid => sig_rsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_RD_STATUS_CNTLR -- -- Description: -- Read Status Controller Block -- ------------------------------------------------------------ I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl generic map ( C_STS_WIDTH => MM2S_STS_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , calc2rsc_calc_error => sig_calc2dm_calc_err , addr2rsc_calc_error => sig_addr2rsc_calc_error , addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty , data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_error => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2stat_status => sig_rsc2stat_status , stat2rsc_status_ready => sig_stat2rsc_status_ready , rsc2stat_status_valid => sig_rsc2stat_status_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_MM2S , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_BTT_USED => MM2S_BTT_USED , C_SUPPORT_INDET_BTT => NO_INDET_BTT , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_btt => sig_mstr2sf_btt , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_cmd_cmplt => open , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset ); ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_ADDR_ID => MM2S_ARID_VALUE , C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => mm2s_arid , addr2axi_aaddr => mm2s_araddr , addr2axi_alen => mm2s_arlen , addr2axi_asize => mm2s_arsize , addr2axi_aburst => mm2s_arburst , addr2axi_aprot => mm2s_arprot , addr2axi_avalid => mm2s_arvalid , addr2axi_acache => mm2s_arcache_int , addr2axi_auser => mm2s_aruser_int , axi2addr_aready => mm2s_arready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_mm2s_allow_addr_req , addr_req_posted => sig_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => LOGIC_LOW , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2rsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_RD_DATA_CNTL -- -- Description: -- Read Data Controller Block -- ------------------------------------------------------------ I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl generic map ( C_INCLUDE_DRE => INCLUDE_DRE , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset ----------------------------------- primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , -- Soft Shutdown Interface ----------------------------- rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , -- External Address Pipelining Contol support mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt , -- AXI Read Data Channel I/O ------------------------------- mm2s_rdata => mm2s_rdata , mm2s_rresp => mm2s_rresp , mm2s_rlast => mm2s_rlast , mm2s_rvalid => mm2s_rvalid , mm2s_rready => mm2s_rready , -- MM2S DRE Control ----------------------------------- mm2s_dre_new_align => sig_rdc2dre_new_align , mm2s_dre_use_autodest => sig_rdc2dre_use_autodest , mm2s_dre_src_align => sig_rdc2dre_src_align , mm2s_dre_dest_align => sig_rdc2dre_dest_align , mm2s_dre_flush => sig_rdc2dre_flush , -- AXI Master Stream ----------------------------------- mm2s_strm_wvalid => sig_rdc2sf_wvalid , mm2s_strm_wready => sig_sf2rdc_wready , mm2s_strm_wdata => sig_rdc2sf_wdata , mm2s_strm_wstrb => sig_rdc2sf_wstrb , mm2s_strm_wlast => sig_rdc2sf_wlast , -- MM2S Store and Forward Supplimental Control ---------- mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , -- Command Calculator Interface -------------------------- mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , -- Address Controller Interface -------------------------- addr2data_addr_posted => sig_addr2data_addr_posted , -- Data Controller Halted Status data2all_dcntlr_halted => sig_data2all_dcntlr_halted , -- Output Stream Skid Buffer Halt control data2skid_halt => sig_data2skid_halt , -- Read Status Controller Interface -------------------------- data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_err => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_SF -- -- If Generate Description: -- Include the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate begin -- Merge external address posting control with the -- Store and Forward address posting control sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and mm2s_allow_addr_req; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; sig_dre_new_align <= sig_sf2dre_new_align ; sig_dre_use_autodest <= sig_sf2dre_use_autodest ; sig_dre_src_align <= sig_sf2dre_src_align ; sig_dre_dest_align <= sig_sf2dre_dest_align ; sig_dre_flush <= sig_sf2dre_flush ; ------------------------------------------------------------ -- Instance: I_RD_SF -- -- Description: -- Instance for the MM2S Store and Forward module with -- downsizer support. -- ------------------------------------------------------------ I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_DRE_IS_USED => INCLUDE_DRE , C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ------------------------------- aclk => mm2s_aclk , reset => sig_mmap_rst , -- DataMover Read Side Address Pipelining Control Interface ok_to_post_rd_addr => sig_sf_allow_addr_req , rd_addr_posted => sig_addr_req_posted , rd_xfer_cmplt => sig_rd_xfer_cmplt , -- Read Side Stream In from DataMover MM2S Read Data Controller ----- sf2sin_tready => sig_sf2rdc_wready , sin2sf_tvalid => sig_rdc2sf_wvalid , sin2sf_tdata => sig_rdc2sf_wdata , sin2sf_tkeep => sig_rdc2sf_wstrb , sin2sf_tlast => sig_rdc2sf_wlast , -- RDC Store and Forward Supplimental Controls ---------- data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , data2sf_dre_flush => sig_rdc2dre_flush , -- DRE Control Interface from the Command Calculator ----------------------------- dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset , -- MM2S DRE Control ------------------------------------------------------------- sf2dre_new_align => sig_sf2dre_new_align , sf2dre_use_autodest => sig_sf2dre_use_autodest , sf2dre_src_align => sig_sf2dre_src_align , sf2dre_dest_align => sig_sf2dre_dest_align , sf2dre_flush => sig_sf2dre_flush , -- Stream Out ---------------------------------- sout2sf_tready => sig_dre2sf_wready , sf2sout_tvalid => sig_sf2dre_wvalid , sf2sout_tdata => sig_sf2dre_wdata , sf2sout_tkeep => sig_sf2dre_wstrb , sf2sout_tlast => sig_sf2dre_wlast ); -- ------------------------------------------------------------ -- -- Instance: I_RD_SF -- -- -- -- Description: -- -- Instance for the MM2S Store and Forward module. -- -- -- ------------------------------------------------------------ -- I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf -- generic map ( -- -- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , -- C_MAX_BURST_LEN => MM2S_BURST_SIZE , -- C_DRE_IS_USED => INCLUDE_DRE , -- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- -- -- Clock and Reset inputs ------------------------------- -- aclk => mm2s_aclk , -- reset => sig_mmap_rst , -- -- -- -- DataMover Read Side Address Pipelining Control Interface -- ok_to_post_rd_addr => sig_sf_allow_addr_req , -- rd_addr_posted => sig_addr_req_posted , -- rd_xfer_cmplt => sig_rd_xfer_cmplt , -- -- -- -- -- Read Side Stream In from DataMover MM2S ----- -- sf2sin_tready => sig_sf2dre_wready , -- sin2sf_tvalid => sig_dre2sf_wvalid , -- sin2sf_tdata => sig_dre2sf_wdata , -- sin2sf_tkeep => sig_dre2sf_wstrb , -- sin2sf_tlast => sig_dre2sf_wlast , -- -- -- -- -- Stream Out ---------------------------------- -- sout2sf_tready => sig_skid2sf_wready , -- sf2sout_tvalid => sig_sf2skid_wvalid , -- sf2sout_tdata => sig_sf2skid_wdata , -- sf2sout_tkeep => sig_sf2skid_wstrb , -- sf2sout_tlast => sig_sf2skid_wlast -- -- ); end generate GEN_INCLUDE_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_SF -- -- If Generate Description: -- Omit the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate begin -- Allow external address posting control -- Ignore Store and Forward Control sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ; sig_sf_allow_addr_req <= '0' ; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; -- DRE Control Bus (Connect to the Read data Controller) sig_dre_new_align <= sig_rdc2dre_new_align ; sig_dre_use_autodest <= sig_rdc2dre_use_autodest ; sig_dre_src_align <= sig_rdc2dre_src_align ; sig_dre_dest_align <= sig_rdc2dre_dest_align ; sig_dre_flush <= sig_rdc2dre_flush ; -- Just pass stream signals through sig_sf2rdc_wready <= sig_dre2sf_wready ; sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ; sig_sf2dre_wdata <= sig_rdc2sf_wdata ; sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ; sig_sf2dre_wlast <= sig_rdc2sf_wlast ; -- Always enable the DRE Cmd bus for loading to keep from -- stalling the PCC module sig_sf2mstr_cmd_ready <= LOGIC_HIGH; end generate GEN_NO_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_DRE -- -- If Generate Description: -- Include the MM2S DRE -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate begin ------------------------------------------------------------ -- Instance: I_DRE64 -- -- Description: -- Instance for the MM2S DRE whach can support widths of -- 16 bits to 64 bits. -- ------------------------------------------------------------ I_DRE_16_to_64 : entity axi_datamover_v5_1.axi_datamover_mm2s_dre generic map ( C_DWIDTH => MM2S_SDATA_WIDTH , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ) port map ( -- Control inputs dre_clk => mm2s_aclk , dre_rst => sig_stream_rst , dre_new_align => sig_dre_new_align , dre_use_autodest => sig_dre_use_autodest , dre_src_align => sig_dre_src_align , dre_dest_align => sig_dre_dest_align , dre_flush => sig_dre_flush , -- Stream Inputs dre_in_tstrb => sig_sf2dre_wstrb , dre_in_tdata => sig_sf2dre_wdata , dre_in_tlast => sig_sf2dre_wlast , dre_in_tvalid => sig_sf2dre_wvalid , dre_in_tready => sig_dre2sf_wready , -- Stream Outputs dre_out_tstrb => sig_dre2skid_wstrb , dre_out_tdata => sig_dre2skid_wdata , dre_out_tlast => sig_dre2skid_wlast , dre_out_tvalid => sig_dre2skid_wvalid , dre_out_tready => sig_skid2dre_wready ); end generate GEN_INCLUDE_MM2S_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_DRE -- -- If Generate Description: -- Omit the MM2S DRE and housekeep the signals that it -- needs to output. -- ------------------------------------------------------------ GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate begin -- Just pass stream signals through from the Store -- and Forward module sig_dre2sf_wready <= sig_skid2dre_wready ; sig_dre2skid_wvalid <= sig_sf2dre_wvalid ; sig_dre2skid_wdata <= sig_sf2dre_wdata ; sig_dre2skid_wstrb <= sig_sf2dre_wstrb ; sig_dre2skid_wlast <= sig_sf2dre_wlast ; end generate GEN_NO_MM2S_DRE; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate begin ------------------------------------------------------------ -- Instance: I_MM2S_SKID_BUF -- -- Description: -- Instance for the MM2S Skid Buffer which provides for -- registerd Master Stream outputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => MM2S_SDATA_WIDTH ) port map ( -- System Ports aclk => mm2s_aclk , arst => sig_stream_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => sig_dre2skid_wvalid , s_ready => sig_skid2dre_wready , s_data => sig_dre2skid_wdata , s_strb => sig_dre2skid_wstrb , s_last => sig_dre2skid_wlast , -- Master Side (Stream Data Output m_valid => mm2s_strm_wvalid , m_ready => mm2s_strm_wready , m_data => mm2s_strm_wdata , m_strb => mm2s_strm_wstrb , m_last => mm2s_strm_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate begin mm2s_strm_wvalid <= sig_dre2skid_wvalid; sig_skid2dre_wready <= mm2s_strm_wready; mm2s_strm_wdata <= sig_dre2skid_wdata; mm2s_strm_wstrb <= sig_dre2skid_wstrb; mm2s_strm_wlast <= sig_dre2skid_wlast; end generate DISABLE_AXIS_SKID; end implementation;
------------------------------------------------------------------------------- -- axi_datamover_mm2s_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_full_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Full Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset; use axi_datamover_v5_1.axi_datamover_cmd_status; use axi_datamover_v5_1.axi_datamover_pcc; use axi_datamover_v5_1.axi_datamover_addr_cntl; use axi_datamover_v5_1.axi_datamover_rddata_cntl; use axi_datamover_v5_1.axi_datamover_rd_status_cntl; use axi_datamover_v5_1.axi_datamover_mm2s_dre; Use axi_datamover_v5_1.axi_datamover_rd_sf; use axi_datamover_v5_1.axi_datamover_skid_buf; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_full_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 1; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Lite MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the incllusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit Store and Forward -- 1 = Include Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input --------------------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- MM2S Halt request input control -------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Error discrete output ------------------------------------ mm2s_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------- -- Optional MM2S Command and Status Clock and Reset --------- -- Used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ---------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- --------------------------------------------------------------- -- Address Posting contols ------------------------------------ mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- --------------------------------------------------------------- -- MM2S AXI Address Channel I/O --------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------ -- Currently unsupported AXI Address Channel output signals ------------ -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------------ -- MM2S AXI MMap Read Data Channel I/O ----------------------------------------- mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- --------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- ---------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------ ); end entity axi_datamover_mm2s_full_wrap; architecture implementation of axi_datamover_mm2s_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_rdmux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Read data mux select control. -- ------------------------------------------------------------------- function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_rdmux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin If (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else -- no DRE align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => -- 128 ratio fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for MM2S -- modules upstream from the downsizing Store and Forward. If -- Store and Forward is present, then the effective native width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Native Data width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled = 1) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; -- Constant Declarations ---------------------------------------- Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH, C_MM2S_SDATA_WIDTH, C_INCLUDE_MM2S_GP_SF); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S; Constant IS_MM2S : integer range 0 to 1 := 1; Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID; Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH; Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH; Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH; Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH; Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32); Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO; Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH; Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC; Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE; Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH); Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED; Constant NO_INDET_BTT : integer range 0 to 1 := 0; Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE, C_MM2S_SDATA_WIDTH); Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE, C_MM2S_SDATA_WIDTH); -- Calculates the minimum needed depth of the Store and Forward FIFO -- based on the MM2S pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) MM2S_BURST_SIZE; -- Assigns the depth of the optional Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH, MM2S_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_cmplt : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2rsc_calc_error : std_logic := '0'; signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2rsc_calc_err : std_logic := '0'; signal sig_data2rsc_okay : std_logic := '0'; signal sig_data2rsc_decerr : std_logic := '0'; signal sig_data2rsc_slverr : std_logic := '0'; signal sig_data2rsc_cmd_cmplt : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_data2rsc_valid : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2rsc_status_ready : std_logic := '0'; signal sig_rsc2stat_status_valid : std_logic := '0'; signal sig_rsc2mstr_halt_pipe : std_logic := '0'; signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2rdc_wready : std_logic := '0'; signal sig_rdc2sf_wvalid : std_logic := '0'; signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_rdc2sf_wlast : std_logic := '0'; signal sig_skid2dre_wready : std_logic := '0'; signal sig_dre2skid_wvalid : std_logic := '0'; signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2skid_wlast : std_logic := '0'; signal sig_dre2sf_wready : std_logic := '0'; signal sig_sf2dre_wvalid : std_logic := '0'; signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_sf2dre_wlast : std_logic := '0'; signal sig_rdc2dre_new_align : std_logic := '0'; signal sig_rdc2dre_use_autodest : std_logic := '0'; signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_flush : std_logic := '0'; signal sig_sf2dre_new_align : std_logic := '0'; signal sig_sf2dre_use_autodest : std_logic := '0'; signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_flush : std_logic := '0'; signal sig_dre_new_align : std_logic := '0'; signal sig_dre_use_autodest : std_logic := '0'; signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_sf_allow_addr_req : std_logic := '0'; signal sig_mm2s_allow_addr_req : std_logic := '0'; signal sig_addr_req_posted : std_logic := '0'; signal sig_rd_xfer_cmplt : std_logic := '0'; signal sig_sf2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2sf_cmd_valid : std_logic := '0'; signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2sf_drr : std_logic := '0'; signal sig_mstr2sf_eof : std_logic := '0'; signal sig_mstr2sf_calc_error : std_logic := '0'; signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_data2sf_cmd_cmplt : std_logic := '0'; signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal mm2s_arcache_int : std_logic_vector (3 downto 0); signal mm2s_aruser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug vector output mm2s_dbg_data <= sig_dbg_data_mux_out; -- Note that only the mm2s_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (mm2s_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2rsc_status_ready; sig_dbg_data_1(7) <= sig_rsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake -- Spare bits in debug1 sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc -- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values sig_cache_data <= mm2s_cmd_wdata(79 downto 72); -- This is the xUser and xCache values end generate GEN_CACHE2; -- Internal error output discrete ------------------------------ mm2s_err <= sig_calc2dm_calc_err; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ) port map ( primary_aclk => mm2s_aclk , primary_aresetn => mm2s_aresetn , secondary_awclk => mm2s_cmdsts_awclk , secondary_aresetn => mm2s_cmdsts_aresetn , halt_req => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => LOGIC_HIGH , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO , C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_STS_WIDTH => MM2S_STS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , secondary_awclk => mm2s_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => mm2s_cmd_wvalid , cmd_wready => mm2s_cmd_wready , cmd_wdata => sig_mm2s_cmd_wdata , cache_data => sig_cache_data , sts_wvalid => mm2s_sts_wvalid , sts_wready => mm2s_sts_wready , sts_wdata => mm2s_sts_wdata , sts_wstrb => mm2s_sts_wstrb , sts_wlast => mm2s_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_rsc2stat_status , stat2mstr_status_ready => sig_stat2rsc_status_ready , mst2stst_status_valid => sig_rsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_RD_STATUS_CNTLR -- -- Description: -- Read Status Controller Block -- ------------------------------------------------------------ I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl generic map ( C_STS_WIDTH => MM2S_STS_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , calc2rsc_calc_error => sig_calc2dm_calc_err , addr2rsc_calc_error => sig_addr2rsc_calc_error , addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty , data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_error => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2stat_status => sig_rsc2stat_status , stat2rsc_status_ready => sig_stat2rsc_status_ready , rsc2stat_status_valid => sig_rsc2stat_status_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_MM2S , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_BTT_USED => MM2S_BTT_USED , C_SUPPORT_INDET_BTT => NO_INDET_BTT , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_btt => sig_mstr2sf_btt , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_cmd_cmplt => open , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset ); ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_ADDR_ID => MM2S_ARID_VALUE , C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => mm2s_arid , addr2axi_aaddr => mm2s_araddr , addr2axi_alen => mm2s_arlen , addr2axi_asize => mm2s_arsize , addr2axi_aburst => mm2s_arburst , addr2axi_aprot => mm2s_arprot , addr2axi_avalid => mm2s_arvalid , addr2axi_acache => mm2s_arcache_int , addr2axi_auser => mm2s_aruser_int , axi2addr_aready => mm2s_arready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_mm2s_allow_addr_req , addr_req_posted => sig_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => LOGIC_LOW , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2rsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_RD_DATA_CNTL -- -- Description: -- Read Data Controller Block -- ------------------------------------------------------------ I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl generic map ( C_INCLUDE_DRE => INCLUDE_DRE , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset ----------------------------------- primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , -- Soft Shutdown Interface ----------------------------- rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , -- External Address Pipelining Contol support mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt , -- AXI Read Data Channel I/O ------------------------------- mm2s_rdata => mm2s_rdata , mm2s_rresp => mm2s_rresp , mm2s_rlast => mm2s_rlast , mm2s_rvalid => mm2s_rvalid , mm2s_rready => mm2s_rready , -- MM2S DRE Control ----------------------------------- mm2s_dre_new_align => sig_rdc2dre_new_align , mm2s_dre_use_autodest => sig_rdc2dre_use_autodest , mm2s_dre_src_align => sig_rdc2dre_src_align , mm2s_dre_dest_align => sig_rdc2dre_dest_align , mm2s_dre_flush => sig_rdc2dre_flush , -- AXI Master Stream ----------------------------------- mm2s_strm_wvalid => sig_rdc2sf_wvalid , mm2s_strm_wready => sig_sf2rdc_wready , mm2s_strm_wdata => sig_rdc2sf_wdata , mm2s_strm_wstrb => sig_rdc2sf_wstrb , mm2s_strm_wlast => sig_rdc2sf_wlast , -- MM2S Store and Forward Supplimental Control ---------- mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , -- Command Calculator Interface -------------------------- mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , -- Address Controller Interface -------------------------- addr2data_addr_posted => sig_addr2data_addr_posted , -- Data Controller Halted Status data2all_dcntlr_halted => sig_data2all_dcntlr_halted , -- Output Stream Skid Buffer Halt control data2skid_halt => sig_data2skid_halt , -- Read Status Controller Interface -------------------------- data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_err => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_SF -- -- If Generate Description: -- Include the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate begin -- Merge external address posting control with the -- Store and Forward address posting control sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and mm2s_allow_addr_req; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; sig_dre_new_align <= sig_sf2dre_new_align ; sig_dre_use_autodest <= sig_sf2dre_use_autodest ; sig_dre_src_align <= sig_sf2dre_src_align ; sig_dre_dest_align <= sig_sf2dre_dest_align ; sig_dre_flush <= sig_sf2dre_flush ; ------------------------------------------------------------ -- Instance: I_RD_SF -- -- Description: -- Instance for the MM2S Store and Forward module with -- downsizer support. -- ------------------------------------------------------------ I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_DRE_IS_USED => INCLUDE_DRE , C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ------------------------------- aclk => mm2s_aclk , reset => sig_mmap_rst , -- DataMover Read Side Address Pipelining Control Interface ok_to_post_rd_addr => sig_sf_allow_addr_req , rd_addr_posted => sig_addr_req_posted , rd_xfer_cmplt => sig_rd_xfer_cmplt , -- Read Side Stream In from DataMover MM2S Read Data Controller ----- sf2sin_tready => sig_sf2rdc_wready , sin2sf_tvalid => sig_rdc2sf_wvalid , sin2sf_tdata => sig_rdc2sf_wdata , sin2sf_tkeep => sig_rdc2sf_wstrb , sin2sf_tlast => sig_rdc2sf_wlast , -- RDC Store and Forward Supplimental Controls ---------- data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , data2sf_dre_flush => sig_rdc2dre_flush , -- DRE Control Interface from the Command Calculator ----------------------------- dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset , -- MM2S DRE Control ------------------------------------------------------------- sf2dre_new_align => sig_sf2dre_new_align , sf2dre_use_autodest => sig_sf2dre_use_autodest , sf2dre_src_align => sig_sf2dre_src_align , sf2dre_dest_align => sig_sf2dre_dest_align , sf2dre_flush => sig_sf2dre_flush , -- Stream Out ---------------------------------- sout2sf_tready => sig_dre2sf_wready , sf2sout_tvalid => sig_sf2dre_wvalid , sf2sout_tdata => sig_sf2dre_wdata , sf2sout_tkeep => sig_sf2dre_wstrb , sf2sout_tlast => sig_sf2dre_wlast ); -- ------------------------------------------------------------ -- -- Instance: I_RD_SF -- -- -- -- Description: -- -- Instance for the MM2S Store and Forward module. -- -- -- ------------------------------------------------------------ -- I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf -- generic map ( -- -- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , -- C_MAX_BURST_LEN => MM2S_BURST_SIZE , -- C_DRE_IS_USED => INCLUDE_DRE , -- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- -- -- Clock and Reset inputs ------------------------------- -- aclk => mm2s_aclk , -- reset => sig_mmap_rst , -- -- -- -- DataMover Read Side Address Pipelining Control Interface -- ok_to_post_rd_addr => sig_sf_allow_addr_req , -- rd_addr_posted => sig_addr_req_posted , -- rd_xfer_cmplt => sig_rd_xfer_cmplt , -- -- -- -- -- Read Side Stream In from DataMover MM2S ----- -- sf2sin_tready => sig_sf2dre_wready , -- sin2sf_tvalid => sig_dre2sf_wvalid , -- sin2sf_tdata => sig_dre2sf_wdata , -- sin2sf_tkeep => sig_dre2sf_wstrb , -- sin2sf_tlast => sig_dre2sf_wlast , -- -- -- -- -- Stream Out ---------------------------------- -- sout2sf_tready => sig_skid2sf_wready , -- sf2sout_tvalid => sig_sf2skid_wvalid , -- sf2sout_tdata => sig_sf2skid_wdata , -- sf2sout_tkeep => sig_sf2skid_wstrb , -- sf2sout_tlast => sig_sf2skid_wlast -- -- ); end generate GEN_INCLUDE_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_SF -- -- If Generate Description: -- Omit the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate begin -- Allow external address posting control -- Ignore Store and Forward Control sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ; sig_sf_allow_addr_req <= '0' ; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; -- DRE Control Bus (Connect to the Read data Controller) sig_dre_new_align <= sig_rdc2dre_new_align ; sig_dre_use_autodest <= sig_rdc2dre_use_autodest ; sig_dre_src_align <= sig_rdc2dre_src_align ; sig_dre_dest_align <= sig_rdc2dre_dest_align ; sig_dre_flush <= sig_rdc2dre_flush ; -- Just pass stream signals through sig_sf2rdc_wready <= sig_dre2sf_wready ; sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ; sig_sf2dre_wdata <= sig_rdc2sf_wdata ; sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ; sig_sf2dre_wlast <= sig_rdc2sf_wlast ; -- Always enable the DRE Cmd bus for loading to keep from -- stalling the PCC module sig_sf2mstr_cmd_ready <= LOGIC_HIGH; end generate GEN_NO_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_DRE -- -- If Generate Description: -- Include the MM2S DRE -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate begin ------------------------------------------------------------ -- Instance: I_DRE64 -- -- Description: -- Instance for the MM2S DRE whach can support widths of -- 16 bits to 64 bits. -- ------------------------------------------------------------ I_DRE_16_to_64 : entity axi_datamover_v5_1.axi_datamover_mm2s_dre generic map ( C_DWIDTH => MM2S_SDATA_WIDTH , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ) port map ( -- Control inputs dre_clk => mm2s_aclk , dre_rst => sig_stream_rst , dre_new_align => sig_dre_new_align , dre_use_autodest => sig_dre_use_autodest , dre_src_align => sig_dre_src_align , dre_dest_align => sig_dre_dest_align , dre_flush => sig_dre_flush , -- Stream Inputs dre_in_tstrb => sig_sf2dre_wstrb , dre_in_tdata => sig_sf2dre_wdata , dre_in_tlast => sig_sf2dre_wlast , dre_in_tvalid => sig_sf2dre_wvalid , dre_in_tready => sig_dre2sf_wready , -- Stream Outputs dre_out_tstrb => sig_dre2skid_wstrb , dre_out_tdata => sig_dre2skid_wdata , dre_out_tlast => sig_dre2skid_wlast , dre_out_tvalid => sig_dre2skid_wvalid , dre_out_tready => sig_skid2dre_wready ); end generate GEN_INCLUDE_MM2S_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_DRE -- -- If Generate Description: -- Omit the MM2S DRE and housekeep the signals that it -- needs to output. -- ------------------------------------------------------------ GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate begin -- Just pass stream signals through from the Store -- and Forward module sig_dre2sf_wready <= sig_skid2dre_wready ; sig_dre2skid_wvalid <= sig_sf2dre_wvalid ; sig_dre2skid_wdata <= sig_sf2dre_wdata ; sig_dre2skid_wstrb <= sig_sf2dre_wstrb ; sig_dre2skid_wlast <= sig_sf2dre_wlast ; end generate GEN_NO_MM2S_DRE; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate begin ------------------------------------------------------------ -- Instance: I_MM2S_SKID_BUF -- -- Description: -- Instance for the MM2S Skid Buffer which provides for -- registerd Master Stream outputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => MM2S_SDATA_WIDTH ) port map ( -- System Ports aclk => mm2s_aclk , arst => sig_stream_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => sig_dre2skid_wvalid , s_ready => sig_skid2dre_wready , s_data => sig_dre2skid_wdata , s_strb => sig_dre2skid_wstrb , s_last => sig_dre2skid_wlast , -- Master Side (Stream Data Output m_valid => mm2s_strm_wvalid , m_ready => mm2s_strm_wready , m_data => mm2s_strm_wdata , m_strb => mm2s_strm_wstrb , m_last => mm2s_strm_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate begin mm2s_strm_wvalid <= sig_dre2skid_wvalid; sig_skid2dre_wready <= mm2s_strm_wready; mm2s_strm_wdata <= sig_dre2skid_wdata; mm2s_strm_wstrb <= sig_dre2skid_wstrb; mm2s_strm_wlast <= sig_dre2skid_wlast; end generate DISABLE_AXIS_SKID; end implementation;
------------------------------------------------------------------------------- -- axi_datamover_mm2s_full_wrap.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_full_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Full Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset; use axi_datamover_v5_1.axi_datamover_cmd_status; use axi_datamover_v5_1.axi_datamover_pcc; use axi_datamover_v5_1.axi_datamover_addr_cntl; use axi_datamover_v5_1.axi_datamover_rddata_cntl; use axi_datamover_v5_1.axi_datamover_rd_status_cntl; use axi_datamover_v5_1.axi_datamover_mm2s_dre; Use axi_datamover_v5_1.axi_datamover_rd_sf; use axi_datamover_v5_1.axi_datamover_skid_buf; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_full_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 1; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Lite MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the incllusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit Store and Forward -- 1 = Include Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input --------------------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- MM2S Halt request input control -------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Error discrete output ------------------------------------ mm2s_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------- -- Optional MM2S Command and Status Clock and Reset --------- -- Used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ---------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- --------------------------------------------------------------- -- Address Posting contols ------------------------------------ mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- --------------------------------------------------------------- -- MM2S AXI Address Channel I/O --------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------ -- Currently unsupported AXI Address Channel output signals ------------ -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------------ -- MM2S AXI MMap Read Data Channel I/O ----------------------------------------- mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- --------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- ---------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------ ); end entity axi_datamover_mm2s_full_wrap; architecture implementation of axi_datamover_mm2s_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_rdmux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Read data mux select control. -- ------------------------------------------------------------------- function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_rdmux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin If (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else -- no DRE align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => -- 128 ratio fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for MM2S -- modules upstream from the downsizing Store and Forward. If -- Store and Forward is present, then the effective native width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Native Data width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled = 1) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; -- Constant Declarations ---------------------------------------- Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH, C_MM2S_SDATA_WIDTH, C_INCLUDE_MM2S_GP_SF); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S; Constant IS_MM2S : integer range 0 to 1 := 1; Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID; Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH; Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH; Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH; Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH; Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32); Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO; Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH; Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC; Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE; Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH); Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED; Constant NO_INDET_BTT : integer range 0 to 1 := 0; Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE, C_MM2S_SDATA_WIDTH); Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE, C_MM2S_SDATA_WIDTH); -- Calculates the minimum needed depth of the Store and Forward FIFO -- based on the MM2S pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) MM2S_BURST_SIZE; -- Assigns the depth of the optional Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH, MM2S_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_cmplt : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2rsc_calc_error : std_logic := '0'; signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2rsc_calc_err : std_logic := '0'; signal sig_data2rsc_okay : std_logic := '0'; signal sig_data2rsc_decerr : std_logic := '0'; signal sig_data2rsc_slverr : std_logic := '0'; signal sig_data2rsc_cmd_cmplt : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_data2rsc_valid : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2rsc_status_ready : std_logic := '0'; signal sig_rsc2stat_status_valid : std_logic := '0'; signal sig_rsc2mstr_halt_pipe : std_logic := '0'; signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2rdc_wready : std_logic := '0'; signal sig_rdc2sf_wvalid : std_logic := '0'; signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_rdc2sf_wlast : std_logic := '0'; signal sig_skid2dre_wready : std_logic := '0'; signal sig_dre2skid_wvalid : std_logic := '0'; signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2skid_wlast : std_logic := '0'; signal sig_dre2sf_wready : std_logic := '0'; signal sig_sf2dre_wvalid : std_logic := '0'; signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_sf2dre_wlast : std_logic := '0'; signal sig_rdc2dre_new_align : std_logic := '0'; signal sig_rdc2dre_use_autodest : std_logic := '0'; signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_flush : std_logic := '0'; signal sig_sf2dre_new_align : std_logic := '0'; signal sig_sf2dre_use_autodest : std_logic := '0'; signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_flush : std_logic := '0'; signal sig_dre_new_align : std_logic := '0'; signal sig_dre_use_autodest : std_logic := '0'; signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_sf_allow_addr_req : std_logic := '0'; signal sig_mm2s_allow_addr_req : std_logic := '0'; signal sig_addr_req_posted : std_logic := '0'; signal sig_rd_xfer_cmplt : std_logic := '0'; signal sig_sf2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2sf_cmd_valid : std_logic := '0'; signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2sf_drr : std_logic := '0'; signal sig_mstr2sf_eof : std_logic := '0'; signal sig_mstr2sf_calc_error : std_logic := '0'; signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_data2sf_cmd_cmplt : std_logic := '0'; signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal mm2s_arcache_int : std_logic_vector (3 downto 0); signal mm2s_aruser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug vector output mm2s_dbg_data <= sig_dbg_data_mux_out; -- Note that only the mm2s_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (mm2s_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2rsc_status_ready; sig_dbg_data_1(7) <= sig_rsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake -- Spare bits in debug1 sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc -- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values sig_cache_data <= mm2s_cmd_wdata(79 downto 72); -- This is the xUser and xCache values end generate GEN_CACHE2; -- Internal error output discrete ------------------------------ mm2s_err <= sig_calc2dm_calc_err; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ) port map ( primary_aclk => mm2s_aclk , primary_aresetn => mm2s_aresetn , secondary_awclk => mm2s_cmdsts_awclk , secondary_aresetn => mm2s_cmdsts_aresetn , halt_req => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => LOGIC_HIGH , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO , C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_STS_WIDTH => MM2S_STS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , secondary_awclk => mm2s_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => mm2s_cmd_wvalid , cmd_wready => mm2s_cmd_wready , cmd_wdata => sig_mm2s_cmd_wdata , cache_data => sig_cache_data , sts_wvalid => mm2s_sts_wvalid , sts_wready => mm2s_sts_wready , sts_wdata => mm2s_sts_wdata , sts_wstrb => mm2s_sts_wstrb , sts_wlast => mm2s_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_rsc2stat_status , stat2mstr_status_ready => sig_stat2rsc_status_ready , mst2stst_status_valid => sig_rsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_RD_STATUS_CNTLR -- -- Description: -- Read Status Controller Block -- ------------------------------------------------------------ I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl generic map ( C_STS_WIDTH => MM2S_STS_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , calc2rsc_calc_error => sig_calc2dm_calc_err , addr2rsc_calc_error => sig_addr2rsc_calc_error , addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty , data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_error => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2stat_status => sig_rsc2stat_status , stat2rsc_status_ready => sig_stat2rsc_status_ready , rsc2stat_status_valid => sig_rsc2stat_status_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_MM2S , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_BTT_USED => MM2S_BTT_USED , C_SUPPORT_INDET_BTT => NO_INDET_BTT , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_btt => sig_mstr2sf_btt , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_cmd_cmplt => open , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset ); ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_ADDR_ID => MM2S_ARID_VALUE , C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => mm2s_arid , addr2axi_aaddr => mm2s_araddr , addr2axi_alen => mm2s_arlen , addr2axi_asize => mm2s_arsize , addr2axi_aburst => mm2s_arburst , addr2axi_aprot => mm2s_arprot , addr2axi_avalid => mm2s_arvalid , addr2axi_acache => mm2s_arcache_int , addr2axi_auser => mm2s_aruser_int , axi2addr_aready => mm2s_arready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_mm2s_allow_addr_req , addr_req_posted => sig_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => LOGIC_LOW , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2rsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_RD_DATA_CNTL -- -- Description: -- Read Data Controller Block -- ------------------------------------------------------------ I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl generic map ( C_INCLUDE_DRE => INCLUDE_DRE , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset ----------------------------------- primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , -- Soft Shutdown Interface ----------------------------- rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , -- External Address Pipelining Contol support mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt , -- AXI Read Data Channel I/O ------------------------------- mm2s_rdata => mm2s_rdata , mm2s_rresp => mm2s_rresp , mm2s_rlast => mm2s_rlast , mm2s_rvalid => mm2s_rvalid , mm2s_rready => mm2s_rready , -- MM2S DRE Control ----------------------------------- mm2s_dre_new_align => sig_rdc2dre_new_align , mm2s_dre_use_autodest => sig_rdc2dre_use_autodest , mm2s_dre_src_align => sig_rdc2dre_src_align , mm2s_dre_dest_align => sig_rdc2dre_dest_align , mm2s_dre_flush => sig_rdc2dre_flush , -- AXI Master Stream ----------------------------------- mm2s_strm_wvalid => sig_rdc2sf_wvalid , mm2s_strm_wready => sig_sf2rdc_wready , mm2s_strm_wdata => sig_rdc2sf_wdata , mm2s_strm_wstrb => sig_rdc2sf_wstrb , mm2s_strm_wlast => sig_rdc2sf_wlast , -- MM2S Store and Forward Supplimental Control ---------- mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , -- Command Calculator Interface -------------------------- mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , -- Address Controller Interface -------------------------- addr2data_addr_posted => sig_addr2data_addr_posted , -- Data Controller Halted Status data2all_dcntlr_halted => sig_data2all_dcntlr_halted , -- Output Stream Skid Buffer Halt control data2skid_halt => sig_data2skid_halt , -- Read Status Controller Interface -------------------------- data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_err => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_SF -- -- If Generate Description: -- Include the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate begin -- Merge external address posting control with the -- Store and Forward address posting control sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and mm2s_allow_addr_req; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; sig_dre_new_align <= sig_sf2dre_new_align ; sig_dre_use_autodest <= sig_sf2dre_use_autodest ; sig_dre_src_align <= sig_sf2dre_src_align ; sig_dre_dest_align <= sig_sf2dre_dest_align ; sig_dre_flush <= sig_sf2dre_flush ; ------------------------------------------------------------ -- Instance: I_RD_SF -- -- Description: -- Instance for the MM2S Store and Forward module with -- downsizer support. -- ------------------------------------------------------------ I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_DRE_IS_USED => INCLUDE_DRE , C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ------------------------------- aclk => mm2s_aclk , reset => sig_mmap_rst , -- DataMover Read Side Address Pipelining Control Interface ok_to_post_rd_addr => sig_sf_allow_addr_req , rd_addr_posted => sig_addr_req_posted , rd_xfer_cmplt => sig_rd_xfer_cmplt , -- Read Side Stream In from DataMover MM2S Read Data Controller ----- sf2sin_tready => sig_sf2rdc_wready , sin2sf_tvalid => sig_rdc2sf_wvalid , sin2sf_tdata => sig_rdc2sf_wdata , sin2sf_tkeep => sig_rdc2sf_wstrb , sin2sf_tlast => sig_rdc2sf_wlast , -- RDC Store and Forward Supplimental Controls ---------- data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , data2sf_dre_flush => sig_rdc2dre_flush , -- DRE Control Interface from the Command Calculator ----------------------------- dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset , -- MM2S DRE Control ------------------------------------------------------------- sf2dre_new_align => sig_sf2dre_new_align , sf2dre_use_autodest => sig_sf2dre_use_autodest , sf2dre_src_align => sig_sf2dre_src_align , sf2dre_dest_align => sig_sf2dre_dest_align , sf2dre_flush => sig_sf2dre_flush , -- Stream Out ---------------------------------- sout2sf_tready => sig_dre2sf_wready , sf2sout_tvalid => sig_sf2dre_wvalid , sf2sout_tdata => sig_sf2dre_wdata , sf2sout_tkeep => sig_sf2dre_wstrb , sf2sout_tlast => sig_sf2dre_wlast ); -- ------------------------------------------------------------ -- -- Instance: I_RD_SF -- -- -- -- Description: -- -- Instance for the MM2S Store and Forward module. -- -- -- ------------------------------------------------------------ -- I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf -- generic map ( -- -- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , -- C_MAX_BURST_LEN => MM2S_BURST_SIZE , -- C_DRE_IS_USED => INCLUDE_DRE , -- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- -- -- Clock and Reset inputs ------------------------------- -- aclk => mm2s_aclk , -- reset => sig_mmap_rst , -- -- -- -- DataMover Read Side Address Pipelining Control Interface -- ok_to_post_rd_addr => sig_sf_allow_addr_req , -- rd_addr_posted => sig_addr_req_posted , -- rd_xfer_cmplt => sig_rd_xfer_cmplt , -- -- -- -- -- Read Side Stream In from DataMover MM2S ----- -- sf2sin_tready => sig_sf2dre_wready , -- sin2sf_tvalid => sig_dre2sf_wvalid , -- sin2sf_tdata => sig_dre2sf_wdata , -- sin2sf_tkeep => sig_dre2sf_wstrb , -- sin2sf_tlast => sig_dre2sf_wlast , -- -- -- -- -- Stream Out ---------------------------------- -- sout2sf_tready => sig_skid2sf_wready , -- sf2sout_tvalid => sig_sf2skid_wvalid , -- sf2sout_tdata => sig_sf2skid_wdata , -- sf2sout_tkeep => sig_sf2skid_wstrb , -- sf2sout_tlast => sig_sf2skid_wlast -- -- ); end generate GEN_INCLUDE_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_SF -- -- If Generate Description: -- Omit the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate begin -- Allow external address posting control -- Ignore Store and Forward Control sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ; sig_sf_allow_addr_req <= '0' ; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; -- DRE Control Bus (Connect to the Read data Controller) sig_dre_new_align <= sig_rdc2dre_new_align ; sig_dre_use_autodest <= sig_rdc2dre_use_autodest ; sig_dre_src_align <= sig_rdc2dre_src_align ; sig_dre_dest_align <= sig_rdc2dre_dest_align ; sig_dre_flush <= sig_rdc2dre_flush ; -- Just pass stream signals through sig_sf2rdc_wready <= sig_dre2sf_wready ; sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ; sig_sf2dre_wdata <= sig_rdc2sf_wdata ; sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ; sig_sf2dre_wlast <= sig_rdc2sf_wlast ; -- Always enable the DRE Cmd bus for loading to keep from -- stalling the PCC module sig_sf2mstr_cmd_ready <= LOGIC_HIGH; end generate GEN_NO_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_DRE -- -- If Generate Description: -- Include the MM2S DRE -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate begin ------------------------------------------------------------ -- Instance: I_DRE64 -- -- Description: -- Instance for the MM2S DRE whach can support widths of -- 16 bits to 64 bits. -- ------------------------------------------------------------ I_DRE_16_to_64 : entity axi_datamover_v5_1.axi_datamover_mm2s_dre generic map ( C_DWIDTH => MM2S_SDATA_WIDTH , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ) port map ( -- Control inputs dre_clk => mm2s_aclk , dre_rst => sig_stream_rst , dre_new_align => sig_dre_new_align , dre_use_autodest => sig_dre_use_autodest , dre_src_align => sig_dre_src_align , dre_dest_align => sig_dre_dest_align , dre_flush => sig_dre_flush , -- Stream Inputs dre_in_tstrb => sig_sf2dre_wstrb , dre_in_tdata => sig_sf2dre_wdata , dre_in_tlast => sig_sf2dre_wlast , dre_in_tvalid => sig_sf2dre_wvalid , dre_in_tready => sig_dre2sf_wready , -- Stream Outputs dre_out_tstrb => sig_dre2skid_wstrb , dre_out_tdata => sig_dre2skid_wdata , dre_out_tlast => sig_dre2skid_wlast , dre_out_tvalid => sig_dre2skid_wvalid , dre_out_tready => sig_skid2dre_wready ); end generate GEN_INCLUDE_MM2S_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_DRE -- -- If Generate Description: -- Omit the MM2S DRE and housekeep the signals that it -- needs to output. -- ------------------------------------------------------------ GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate begin -- Just pass stream signals through from the Store -- and Forward module sig_dre2sf_wready <= sig_skid2dre_wready ; sig_dre2skid_wvalid <= sig_sf2dre_wvalid ; sig_dre2skid_wdata <= sig_sf2dre_wdata ; sig_dre2skid_wstrb <= sig_sf2dre_wstrb ; sig_dre2skid_wlast <= sig_sf2dre_wlast ; end generate GEN_NO_MM2S_DRE; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate begin ------------------------------------------------------------ -- Instance: I_MM2S_SKID_BUF -- -- Description: -- Instance for the MM2S Skid Buffer which provides for -- registerd Master Stream outputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => MM2S_SDATA_WIDTH ) port map ( -- System Ports aclk => mm2s_aclk , arst => sig_stream_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => sig_dre2skid_wvalid , s_ready => sig_skid2dre_wready , s_data => sig_dre2skid_wdata , s_strb => sig_dre2skid_wstrb , s_last => sig_dre2skid_wlast , -- Master Side (Stream Data Output m_valid => mm2s_strm_wvalid , m_ready => mm2s_strm_wready , m_data => mm2s_strm_wdata , m_strb => mm2s_strm_wstrb , m_last => mm2s_strm_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate begin mm2s_strm_wvalid <= sig_dre2skid_wvalid; sig_skid2dre_wready <= mm2s_strm_wready; mm2s_strm_wdata <= sig_dre2skid_wdata; mm2s_strm_wstrb <= sig_dre2skid_wstrb; mm2s_strm_wlast <= sig_dre2skid_wlast; end generate DISABLE_AXIS_SKID; end implementation;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; library work; use work.array_t.all; entity fir_sol is Port ( Reset : in STD_LOGIC; Clk : in STD_LOGIC; Input : in array32_t(0 to 9); Output : out STD_LOGIC_VECTOR (31 downto 0) ); end fir_sol; architecture Structural of fir_sol is -- adding the components to the Design -- component adder Port ( A : in STD_LOGIC_VECTOR (31 downto 0); B : in STD_LOGIC_VECTOR (31 downto 0); O : out STD_LOGIC_VECTOR (31 downto 0)); end component; component reg Port ( Reset : in STD_LOGIC; Clk : in STD_LOGIC; Load : in STD_LOGIC; Din : in STD_LOGIC_VECTOR (31 downto 0); Dout : out STD_LOGIC_VECTOR (31 downto 0)); end component; signal mout : array32_t(0 to 30);-- just a big array i will use as much as i need from it , for the first one i will use from 0to 2 and for the second input i will use fro 3to 5 and like that a multiples of 3 signal aout : array32_t(0 to 25); begin -- the equivlant to multiplication of X(0)*b(0) where b(0) = 3 which is 11 in binary that mean shift X(0) by two and add to X(0) --std_logic_vector(unsigned(inputA) srl to_integer(unsigned(inputB))); mout(1)<=std_logic_vector(unsigned(Input(0)) sll 1); add0: adder port map ( A => mout(1), B => Input(0), O => aout(0) ); -- the same for a(1)but with 23 = 11001 left shift by 3 and 4 and 0 mout(3)<=std_logic_vector(unsigned(Input(1)) sll 3); mout(4)<=std_logic_vector(unsigned(Input(1)) sll 4); add1: adder port map ( A => mout(3), B => mout(4), O => mout(5) ); add2: adder port map ( A => mout(5), B => Input(1), O => aout(1) ); -- the same for a(2)but with 96 = 110 0000 left shift by 5 and 6 mout(6)<=std_logic_vector(unsigned(Input(2)) sll 5); mout(7)<=std_logic_vector(unsigned(Input(2)) sll 6); add3: adder port map ( A => mout(6), B => mout(7), O => aout(2) ); -- the same for a(3)but with 384 = 1 1000 0000 left shift by 7 and 8 mout(9)<=std_logic_vector(unsigned(Input(3)) sll 7); mout(10)<=std_logic_vector(unsigned(Input(3)) sll 8); add4: adder port map ( A => mout(9), B => mout(10), O => aout(3) ); -- the same for a(4)but with 3073 = 1100 0000 0001 left shift by 10 and 11 and add a(4) mout(12)<=std_logic_vector(unsigned(Input(4)) sll 10); mout(13)<=std_logic_vector(unsigned(Input(4)) sll 11); add5: adder port map ( A => mout(12), B => mout(13), O => mout(14) ); add6: adder port map ( A => mout(14), B => Input(4), O => aout(4) ); -- the same for a(5)but with 3073 = 1100 0000 0001 left shift by 10 and 11 and add a(5) mout(15)<=std_logic_vector(unsigned(Input(5)) sll 10); mout(16)<=std_logic_vector(unsigned(Input(5)) sll 11); add7: adder port map ( A => mout(15), B => mout(16), O => mout(17) ); add8: adder port map ( A => mout(17), B => Input(5), O => aout(5) ); -- the same for a(6)but with 384 = 1 1000 0000 left shift by 7 and 8 mout(18)<=std_logic_vector(unsigned(Input(6)) sll 7); mout(19)<=std_logic_vector(unsigned(Input(6)) sll 8); add9: adder port map ( A => mout(18), B => mout(19), O => aout(6) ); -- the same for a(7)but with 96 = 110 0000 left shift by 5 and 6 mout(21)<=std_logic_vector(unsigned(Input(7)) sll 5); mout(22)<=std_logic_vector(unsigned(Input(7)) sll 6); add10: adder port map ( A => mout(21), B => mout(22), O => aout(7) ); -- the same for a(8)but with 25 = 11001 left shift by 3 and 4 and 0 mout(24)<=std_logic_vector(unsigned(Input(8)) sll 3); mout(25)<=std_logic_vector(unsigned(Input(8)) sll 4); add11: adder port map ( A => mout(24), B => mout(25), O => mout(26) ); add112: adder port map ( A => mout(26), B => Input(8), O => aout(8) ); -- the same for a(9)but with 3 = 11 left shift by 1 and 0 mout(27)<=std_logic_vector(unsigned(Input(9)) sll 1); add12: adder port map ( A => mout(27), B => Input(9), O => aout(9) ); ---adding the whole results add13: adder port map ( A => aout(0), B => aout(1), O => aout(10) ); add14: adder port map ( A => aout(2), B => aout(3), O => aout(11) ); add15: adder port map ( A => aout(4), B => aout(5), O => aout(12) ); add115: adder port map ( A => aout(6), B => aout(7), O => aout(13) ); add16:adder port map ( A => aout(8), B => aout(9), O => aout(14) ); add117: adder port map ( A => aout(10), B => aout(11), O => aout(15) ); add118: adder port map ( A => aout(12), B => aout(13), O => aout(16) ); add17: adder port map ( A => aout(15), B => aout(16), O => aout(17) ); add18: adder port map ( A => aout(14), B => aout(17), O => aout(18) ); reg3:reg port map ( Reset => Reset, Clk => Clk , Load =>'1', Din => aout(18), Dout => aout(20) ); Output<=aout(20); end Structural;
-- This is a 16 bit Linear Feedback Shift Register library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity LFSR16 is port( CLK : in std_logic; RESET : in std_logic; LD : in std_logic; EN : in std_logic; DIN : in std_logic_vector (0 to 15); PRN : out std_logic_vector (0 to 15); ZERO_D : out std_logic); end LFSR16; architecture RTL of LFSR16 is signal t_prn : std_logic_vector(0 to 15); begin -- Continuous assignments : PRN <= t_prn; ZERO_D <= '1' when (t_prn = "0000000000000000") else '0'; -- LFSR process : process(CLK,RESET) begin if RESET='1' then t_prn <= "0000000000000001"; -- load 1 at reset elsif rising_edge (CLK) then if (LD = '1') then -- load a new seed when ld is active t_prn <= DIN; elsif (EN = '1') then -- shift when enabled t_prn(0) <= t_prn(15) xor t_prn(4) xor t_prn(2) xor t_prn(1); t_prn(1 to 15) <= t_prn(0 to 14); end if; end if; end process; end RTL;
library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use work.fixed_pkg.all; entity EffectEcho is generic ( wordLength : natural := 16; constantsWordLength : natural := 16 ); port ( input : in std_logic_vector(wordLength-1 downto 0); output : out std_logic_vector(wordLength-1 downto 0); clk : in std_logic; reset : in std_logic ); end entity ; -- EffectEcho architecture arch of EffectEcho is COMPONENT blk_mem_gen_0 PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; constant delayDuration : natural := 2; constant decayGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(-0.5, constantsWordLength); constant directGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(0.8, constantsWordLength); constant echoGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(0.5, constantsWordLength); -- 2 second max delay constant addressWidth : natural := 17; constant addressMax : natural := 44100; signal feedback : std_logic_vector(wordLength-1 downto 0); signal directGained : std_logic_vector(wordLength-1 downto 0); signal delayedGained : std_logic_vector(wordLength-1 downto 0); signal delayed : std_logic_vector(wordLength-1 downto 0); signal feedbackDirectSum : std_logic_vector(wordLength-1 downto 0); signal writeBus : std_logic_vector(wordLength-1 downto 0); signal readBus : std_logic_vector(wordLength-1 downto 0); signal writeEnable : std_logic_vector(0 downto 0); signal memoryAddress : std_logic_vector(addressWidth-1 downto 0); type state_type is (readStart, readWait, read, writeDone); constant waitTime : natural := 4; type reg_type is record state : state_type; waitCounter : natural range 0 to waitTime; address : unsigned(addressWidth-1 downto 0); writeEnable : std_logic; delayedOutput : std_logic_vector(wordLength-1 downto 0); end record; signal r, rin : reg_type; begin -- Summation feedbackSum : entity work.AdderSat generic map ( wordLength => wordLength ) port map ( a => input, b => feedback, s => feedbackDirectSum ); outputSum : entity work.AdderSat generic map ( wordLength => wordLength ) port map ( a => directGained, b => delayedGained, s => output ); -- Gains directMult : entity work.Multiplier generic map ( X_WIDTH => wordLength, X_FRACTION => wordLength-1, Y_WIDTH => constantsWordLength, Y_FRACTION => constantsWordLength-1, S_WIDTH => wordLength, S_FRACTION => wordLength-1 ) port map ( x => input, y => directGain, s => directGained ); feedbackMult : entity work.Multiplier generic map ( X_WIDTH => wordLength, X_FRACTION => wordLength-1, Y_WIDTH => constantsWordLength, Y_FRACTION => constantsWordLength-1, S_WIDTH => wordLength, S_FRACTION => wordLength-1 ) port map ( x => delayed, y => decayGain, s => feedback ); echoMult : entity work.Multiplier generic map ( X_WIDTH => wordLength, X_FRACTION => wordLength-1, Y_WIDTH => constantsWordLength, Y_FRACTION => constantsWordLength-1, S_WIDTH => wordLength, S_FRACTION => wordLength-1 ) port map ( x => delayed, y => echoGain, s => delayedGained ); -- Delay writeBus <= feedbackDirectSum; writeEnable <= (others => r.writeEnable); delayed <= r.delayedOutput; memoryAddress <= std_logic_vector(r.address); memory: blk_mem_gen_0 port map ( dina => writeBus, wea => writeEnable, doutb => readBus, clka => clk, clkb => clk, addra => memoryAddress, addrb => memoryAddress ); clk_proc : process( clk, reset ) begin if(reset = '1') then r.state <= readStart; r.address <= (others => '0'); r.writeEnable <= '0'; r.delayedOutput <= (others => '0'); elsif(rising_edge(clk)) then r <= rin; end if; end process ; -- clk_proc comb_proc : process( r, rin, readBus) variable v : reg_type; begin v := r; v.writeEnable := '0'; case r.state is when readStart => v.state := readWait; v.waitCounter := 0; when readWait => -- Wait some cycles before reading if(r.waitCounter >= waitTime) then v.state := read; else v.waitCounter := r.waitCounter + 1; end if; when read => v.state := writeDone; -- Write the new value v.writeEnable := '1'; -- Result is ready, read it. v.delayedOutput := readBus; when writeDone => v.state := readStart; if(r.address = addressMax-1) then v.address := (others => '0'); else v.address := v.address + 1; end if; when others => -- Don't care end case; rin <= v; end process ; -- comb_proc end architecture ; -- arch
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity fsm is port( clock: in std_logic; input: in std_logic_vector(3 downto 0); output: out std_logic_vector(1 downto 0) ); end fsm; architecture behaviour of fsm is type state is (init0, init1, init2, init4, IOwait, RMACK, WMACK, read0, read1, write0); signal current_state, next_state: state; begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= init0; output <= "--"; case current_state is when init0 => if std_match(input, "--00") then next_state <= init1; output <= "00"; end if; when init1 => if std_match(input, "0100") then next_state <= init1; output <= "00"; elsif std_match(input, "--1-") then next_state <= init2; output <= "10"; end if; when init2 => if std_match(input, "1-10") then next_state <= init4; output <= "10"; end if; when init4 => if std_match(input, "-111") then next_state <= init4; output <= "10"; elsif std_match(input, "--01") then next_state <= IOwait; output <= "01"; end if; when IOwait => if std_match(input, "000-") then next_state <= IOwait; output <= "01"; elsif std_match(input, "100-") then next_state <= init1; output <= "01"; elsif std_match(input, "0110") then next_state <= read0; output <= "00"; elsif std_match(input, "1100") then next_state <= write0; output <= "11"; elsif std_match(input, "0111") then next_state <= RMACK; output <= "11"; elsif std_match(input, "1101") then next_state <= WMACK; output <= "00"; elsif std_match(input, "-01-") then next_state <= init2; output <= "01"; end if; when RMACK => if std_match(input, "0010") then next_state <= RMACK; output <= "11"; elsif std_match(input, "0111") then next_state <= read0; output <= "00"; end if; when WMACK => if std_match(input, "1100") then next_state <= WMACK; output <= "00"; elsif std_match(input, "1001") then next_state <= write0; output <= "01"; end if; when read0 => if std_match(input, "0001") then next_state <= read1; output <= "11"; end if; when read1 => if std_match(input, "0010") then next_state <= IOwait; output <= "01"; end if; when write0 => if std_match(input, "0100") then next_state <= IOwait; output <= "01"; end if; end case; end process; end behaviour;
----------------------------------------------------------------------------------------- -- Project : Invent a Chip -- Module : 7-Segment Display -- Author : Jan Dürre -- Last update : 22.07.2014 -- Description : - ----------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.iac_pkg.all; entity seven_seg is port( -- global signals clock : in std_ulogic; reset_n : in std_ulogic; -- bus interface iobus_cs : in std_ulogic; iobus_wr : in std_ulogic; iobus_addr : in std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0); iobus_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0); iobus_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0); -- 7-Seg hex0_n : out std_ulogic_vector(6 downto 0); hex1_n : out std_ulogic_vector(6 downto 0); hex2_n : out std_ulogic_vector(6 downto 0); hex3_n : out std_ulogic_vector(6 downto 0); hex4_n : out std_ulogic_vector(6 downto 0); hex5_n : out std_ulogic_vector(6 downto 0); hex6_n : out std_ulogic_vector(6 downto 0); hex7_n : out std_ulogic_vector(6 downto 0) ); end seven_seg; architecture rtl of seven_seg is -- array for easier use of hex0_n to hex7_n type seg_t is array (0 to 3) of std_ulogic_vector(6 downto 0); signal hex_seg, dec_seg : seg_t; -- 7-Segment Displays -- [][] [][] \| [][][][] -- hex-display \| decimal-display (-999 to 999) -- A4A3A2A1 \| A0 -- +-----+ -- \| 0 \| -- \| 5 1 \| -- \| 6 \| -- \| 4 2 \| -- \| 3 \| -- +-----+ -- register for each hex-display type hex_display_t is array (0 to 3) of std_ulogic_vector(3 downto 0); signal hex_display, hex_display_nxt : hex_display_t; -- register for decimal-display and sign-symbol signal dec_display, dec_display_nxt : std_ulogic_vector(to_log2(1000)-1 downto 0); -- 0...999 signal dec_sign, dec_sign_nxt : std_ulogic; -- register to active 7-seg-displays signal display_active, display_active_nxt : std_ulogic_vector(4 downto 0); begin -- connect and invert signal seg to output hex0_n <= not dec_seg(0); hex1_n <= not dec_seg(1); hex2_n <= not dec_seg(2); hex3_n <= not dec_seg(3); hex4_n <= not hex_seg(0); hex5_n <= not hex_seg(1); hex6_n <= not hex_seg(2); hex7_n <= not hex_seg(3); -- sequential process process(clock, reset_n) begin -- async reset if reset_n = '0' then hex_display <= (others => (others => '0')); dec_display <= (others => '0'); dec_sign <= '0'; display_active <= (others =>'0'); elsif rising_edge(clock) then hex_display <= hex_display_nxt; dec_display <= dec_display_nxt; dec_sign <= dec_sign_nxt; display_active <= display_active_nxt; end if; end process; -- bus interface process(hex_display, dec_display, dec_sign, iobus_cs, iobus_addr, iobus_din, iobus_wr, display_active) begin -- standard: hold register values hex_display_nxt <= hex_display; dec_display_nxt <= dec_display; dec_sign_nxt <= dec_sign; display_active_nxt <= display_active; -- dout always "0..0", no readable registers available iobus_dout <= (others => '0'); -- chip select if iobus_cs = '1' then -- write (no read allowed) if iobus_wr = '1' then -- decode LSB: choose if hex_display or dec_display is changed if iobus_addr(0) = '1' then -- dec -- check MSB for positive or negative number if iobus_din(iobus_din'length-1) = '0' then dec_display_nxt <= iobus_din(dec_display'length-1 downto 0); dec_sign_nxt <= '0'; else -- save positive value dec_display_nxt <= std_ulogic_vector(-signed(iobus_din(dec_display'length-1 downto 0))); dec_sign_nxt <= '1'; end if; -- activate dec-display display_active_nxt(0) <= '1'; else -- hex -- check bits 1 to 4 of iobus_addr for i in 0 to 3 loop -- check if register should be changed if iobus_addr(i+1) = '1' then -- write date to array hex_display_nxt(i) <= iobus_din(i4 + 3 downto i4); -- activate display display_active_nxt(i+1) <= '1'; end if; end loop; end if; end if; end if; end process; -- decode LUT for hex-displays process(hex_display, display_active) begin -- for each hex-display for i in 0 to 3 loop -- check if display is active / has been written to if display_active(i+1) = '1' then case hex_display(i) is when "0000" => hex_seg(i) <= "0111111"; -- 0 when "0001" => hex_seg(i) <= "0000110"; -- 1 when "0010" => hex_seg(i) <= "1011011"; -- 2 when "0011" => hex_seg(i) <= "1001111"; -- 3 when "0100" => hex_seg(i) <= "1100110"; -- 4 when "0101" => hex_seg(i) <= "1101101"; -- 5 when "0110" => hex_seg(i) <= "1111101"; -- 6 when "0111" => hex_seg(i) <= "0000111"; -- 7 when "1000" => hex_seg(i) <= "1111111"; -- 8 when "1001" => hex_seg(i) <= "1101111"; -- 9 when "1010" => hex_seg(i) <= "1110111"; -- A when "1011" => hex_seg(i) <= "1111100"; -- b when "1100" => hex_seg(i) <= "0111001"; -- C when "1101" => hex_seg(i) <= "1011110"; -- d when "1110" => hex_seg(i) <= "1111001"; -- E when "1111" => hex_seg(i) <= "1110001"; -- F when others => hex_seg(i) <= "1111001"; -- wrong value: display E end case; -- deactivate display else hex_seg(i) <= (others => '0'); end if; end loop; end process; -- decode LUT for dec-display process(dec_display, dec_sign, display_active) variable bcd : std_ulogic_vector(11 downto 0); begin -- check if display is active / has been written to if display_active(0) = '1' then -- if value is too big if unsigned(dec_display) > to_unsigned(999, dec_display'length) then -- display E (for "Error") dec_seg(0) <= "1111001"; dec_seg(1) <= "0000000"; dec_seg(2) <= "0000000"; dec_seg(3) <= "0000000"; else -- convert binary to bcd bcd := to_bcd(dec_display, 3); -- for each bcd digit for i in 0 to 2 loop if bcd((i+1)4 -1 downto i4) = "0000" then dec_seg(i) <= "0111111"; -- 0 elsif bcd((i+1)4 -1 downto i4) = "0001" then dec_seg(i) <= "0000110"; -- 1 elsif bcd((i+1)4 -1 downto i4) = "0010" then dec_seg(i) <= "1011011"; -- 2 elsif bcd((i+1)4 -1 downto i4) = "0011" then dec_seg(i) <= "1001111"; -- 3 elsif bcd((i+1)4 -1 downto i4) = "0100" then dec_seg(i) <= "1100110"; -- 4 elsif bcd((i+1)4 -1 downto i4) = "0101" then dec_seg(i) <= "1101101"; -- 5 elsif bcd((i+1)4 -1 downto i4) = "0110" then dec_seg(i) <= "1111101"; -- 6 elsif bcd((i+1)4 -1 downto i4) = "0111" then dec_seg(i) <= "0000111"; -- 7 elsif bcd((i+1)4 -1 downto i4) = "1000" then dec_seg(i) <= "1111111"; -- 8 elsif bcd((i+1)4 -1 downto i4) = "1001" then dec_seg(i) <= "1101111"; -- 9 else dec_seg(i) <= "1111001"; -- wrong value: display E end if; end loop; -- sign-symbol if dec_sign = '1' then dec_seg(3) <= "1000000"; else -- turn off sign-symbol dec_seg(3) <= (others => '0'); end if; end if; -- deactivate display else dec_seg(0) <= (others => '0'); dec_seg(1) <= (others => '0'); dec_seg(2) <= (others => '0'); dec_seg(3) <= (others => '0'); end if; end process; end rtl;
-- ----------------------------------------------------------------------- -- -- Turbo Chameleon -- -- Multi purpose FPGA expansion for the Commodore 64 computer -- -- ----------------------------------------------------------------------- -- Copyright 2005-2021 by Peter Wendrich ([email protected]) -- http://www.syntiac.com/chameleon.html -- -- This source file is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This source file is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- ----------------------------------------------------------------------- -- -- Part of the Gigatron emulator. -- SRAM emulation mapped to FPGA blockram. -- -- ----------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- ----------------------------------------------------------------------- entity gigatron_ram is generic ( abits : integer := 15; dbits : integer := 8 ); port ( clk : in std_logic; we : in std_logic; a : in unsigned(abits-1 downto 0); d : in unsigned(dbits-1 downto 0); q : out unsigned(dbits-1 downto 0) ); end entity; -- ----------------------------------------------------------------------- architecture rtl of gigatron_ram is constant ramsize : integer := 2**abits; type ram_t is array(0 to ramsize-1) of unsigned(d'range); signal ram_reg : ram_t := (others => (others => '0')); signal q_reg : unsigned(q'range); begin q <= q_reg; process(clk) begin if rising_edge(clk) then if we = '1' then ram_reg(to_integer(a)) <= d; end if; q_reg <= ram_reg(to_integer(a)); end if; end process; end architecture;
-- Template for VGA output by: Rene Kristensen -- This design template uses gated clocks which generally are bad design practice. -- This implies that the template design is not optimized for speed and will only serve for educational purpose. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity vga is port (clk,reset : in std_logic; red, green, blue : out std_logic_vector(9 downto 0); hsync, vsync, clockOut, blank, compSync: out std_logic); end vga; architecture testGenerator of vga is -- horizontal Timing constants for 640 x 480 @ 60Hz constant hFrontPorch : natural := 16; -- units are number of 25 MHz clocks constant hBackPorch : natural := 48; constant hDataLen : natural := 640; constant hSynWidth : natural := 96; -- vertical Timing constants for 640 x 480 @ 60Hz constant vFrontPorch : natural := 10; -- units are number of lines constant vBackPorch : natural := 33; constant vDataLen : natural := 480; constant vSynWidth : natural := 2; -- signal declaration signal hSyncCounter, vSyncCounter : integer range 0 to 1023; -- contrain integer to 10 bit. signal hSyncOut,vSyncOut,clk25,vBlank,hBlank : std_logic; -- attributes ensuring the signals defined below are not reduced away before simulation. attribute keep: boolean; -- don't reduce vSyncCounter and hSyncCounter signals away, so we can watch these signals i simulator attribute keep of vSyncCounter : signal is true; -- \|\| -- attribute keep of hSyncCounter: signal is true; -- \|\| -- -- INSERT YOUR PROCEDURE HERE. -- Your procedure should circular increment syncCounter, produce blanking and sync output. begin clkdiv: process (reset,clk) -- creates a 25 MHz pixel clock (clk25) from a 50 MHz input (clk). begin if (reset = '0') then clk25 <= '0'; elsif rising_edge(clk) then clk25 <= not clk25; end if; end process; -- horizontal process using the generic syncGenerator function to generate a proper hsync pulse. hsyn: process (reset,clk25) -- reacts on reset and 25 MHz clock. begin if reset = '0' then hSyncCounter <= 0; elsif rising_edge(clk25) then syncGenerator(hSyncCounter,hSyncOut,hBlank,hFrontPorch,hBackPorch,hDataLen,hSynWidth); -- generates active low pulse after every line end if; end process; -- vertical process using the generic syncGenerator function to generate a proper vsync pulse. vsyn: process (reset,hSyncOut) -- reacts on reset and hsync (meaning every line). begin if reset = '0' then vSyncCounter <= 0; elsif rising_edge(hSyncOut) then syncGenerator(vSyncCounter,vSyncOut,vBlank,vFrontPorch,vBackPorch,vDataLen,vSynWidth); -- generates active low pulse after every picture end if; end process; color: process (reset, hSyncCounter,vSyncCounter) -- draws italian flag color scheme begin if ((hSyncCounter > hBackPorch) and (hSyncCounter <= hBackPorch+213)) then red <= (others => '0'); -- Green green <= (others => '1'); blue <= (others => '0'); elsif ((hSyncCounter > hBackPorch+213) and (hSyncCounter <= hBackPorch+426)) then red <= (others => '1'); -- White green <= (others => '1'); blue <= (others => '1'); else red <= (others => '1'); -- Red green <= (others => '0'); blue <= (others => '0'); end if; end process; vsync <= vSyncOut; -- connect vsync to entity hsync <= hSyncOut; -- connect hsync to entity clockOut <= clk25; -- 25 MHz clock for DAC blank <= not (vBlank or hBlank); -- active low blanking. compSync <= '1'; -- Never perform any composite sync. end testGenerator;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; entity uart_peripheral_io is generic ( g_tx_fifo : boolean := true; g_divisor : natural := 417 ); port ( clock : in std_logic; reset : in std_logic; io_req : in t_io_req; io_resp : out t_io_resp; irq : out std_logic; txd : out std_logic; rxd : in std_logic := '1'; rts : out std_logic; cts : in std_logic := '1' ); end uart_peripheral_io; architecture gideon of uart_peripheral_io is signal dotx : std_logic; signal done : std_logic; signal rxchar : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal rxfifo_get : std_logic; signal rxfifo_dout : std_logic_vector(7 downto 0); signal rxfifo_full : std_logic; signal rxfifo_dav : std_logic; signal overflow : std_logic; signal flags : std_logic_vector(7 downto 0); signal imask : std_logic_vector(7 downto 6); signal rdata_mux : std_logic_vector(7 downto 0); signal txfifo_get : std_logic; signal txfifo_put : std_logic; signal txfifo_dout : std_logic_vector(7 downto 0); signal txfifo_full : std_logic := '1'; signal txfifo_dav : std_logic; signal dotx_d : std_logic; signal txchar : std_logic_vector(7 downto 0); constant c_uart_data : unsigned(1 downto 0) := "00"; constant c_uart_get : unsigned(1 downto 0) := "01"; constant c_uart_flags : unsigned(1 downto 0) := "10"; constant c_uart_imask : unsigned(1 downto 0) := "11"; begin my_tx: entity work.tx generic map (g_divisor) port map ( clk => clock, reset => reset, dotx => dotx, txchar => txchar, cts => cts, txd => txd, done => done ); my_rx: entity work.rx generic map (g_divisor) port map ( clk => clock, reset => reset, rxd => rxd, rxchar => rxchar, rx_ack => rx_ack ); my_rxfifo: entity work.srl_fifo generic map ( Width => 8, Threshold => 12 ) port map ( clock => clock, reset => reset, GetElement => rxfifo_get, PutElement => rx_ack, FlushFifo => '0', DataIn => rxchar, DataOut => rxfifo_dout, SpaceInFifo => open, AlmostFull => rxfifo_full, DataInFifo => rxfifo_dav ); gentx: if g_tx_fifo generate my_txfifo: entity work.srl_fifo generic map ( Width => 8, Threshold => 12 ) port map ( clock => clock, reset => reset, GetElement => txfifo_get, PutElement => txfifo_put, FlushFifo => '0', DataIn => io_req.data, DataOut => txfifo_dout, SpaceInFifo => open, AlmostFull => txfifo_full, DataInFifo => txfifo_dav ); end generate; process(clock) begin if rising_edge(clock) then rxfifo_get <= '0'; dotx_d <= dotx; txfifo_get <= dotx_d; io_resp <= c_io_resp_init; if rxfifo_full='1' and rx_ack='1' then overflow <= '1'; end if; txfifo_put <= '0'; if g_tx_fifo then dotx <= txfifo_dav and done and not dotx; txchar <= txfifo_dout; else dotx <= '0'; -- default, overridden with write end if; if io_req.write='1' then io_resp.ack <= '1'; case io_req.address(1 downto 0) is when c_uart_data => -- dout if not g_tx_fifo then txchar <= io_req.data; dotx <= '1'; else -- there is a fifo txfifo_put <= '1'; end if; when c_uart_get => -- din rxfifo_get <= '1'; when c_uart_flags => -- clear flags overflow <= overflow and not io_req.data(0); when c_uart_imask => -- interrupt control imask <= io_req.data(7 downto 6); when others => null; end case; elsif io_req.read='1' then io_resp.ack <= '1'; io_resp.data <= rdata_mux; end if; if (flags(7 downto 6) and imask) /= "00" then irq <= '1'; else irq <= '0'; end if; if reset='1' then overflow <= '0'; imask <= (others => '0'); end if; end if; end process; flags(0) <= overflow; flags(1) <= '0'; flags(2) <= '0'; flags(3) <= '0'; flags(4) <= txfifo_full; flags(5) <= rxfifo_full; flags(6) <= done; flags(7) <= rxfifo_dav; rts <= not rxfifo_full; with io_req.address(1 downto 0) select rdata_mux <= rxfifo_dout when c_uart_data, flags when c_uart_flags, imask & "000000" when c_uart_imask, X"00" when others; end gideon;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library ieee; use ieee.std_logic_1164.all; package synchronize is procedure init_synchronize ( signal synch : out std_logic ); procedure begin_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ); procedure end_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ); end package synchronize; package body synchronize is -- code from book procedure init_synchronize ( signal synch : out std_logic ) is begin synch <= '0'; end procedure init_synchronize; procedure begin_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ) is begin synch <= 'Z' after Tdelay; wait until synch = 'H'; end procedure begin_synchronize; procedure end_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ) is begin synch <= '0' after Tdelay; wait until synch = '0'; end procedure end_synchronize; -- end code from book end package body synchronize;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library ieee; use ieee.std_logic_1164.all; package synchronize is procedure init_synchronize ( signal synch : out std_logic ); procedure begin_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ); procedure end_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ); end package synchronize; package body synchronize is -- code from book procedure init_synchronize ( signal synch : out std_logic ) is begin synch <= '0'; end procedure init_synchronize; procedure begin_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ) is begin synch <= 'Z' after Tdelay; wait until synch = 'H'; end procedure begin_synchronize; procedure end_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ) is begin synch <= '0' after Tdelay; wait until synch = '0'; end procedure end_synchronize; -- end code from book end package body synchronize;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library ieee; use ieee.std_logic_1164.all; package synchronize is procedure init_synchronize ( signal synch : out std_logic ); procedure begin_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ); procedure end_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ); end package synchronize; package body synchronize is -- code from book procedure init_synchronize ( signal synch : out std_logic ) is begin synch <= '0'; end procedure init_synchronize; procedure begin_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ) is begin synch <= 'Z' after Tdelay; wait until synch = 'H'; end procedure begin_synchronize; procedure end_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ) is begin synch <= '0' after Tdelay; wait until synch = '0'; end procedure end_synchronize; -- end code from book end package body synchronize;
--------------------------------------------------------------------------- -- -- Title: Hardware Thread User Logic Exit Thread -- To be used as a place holder, and size estimate for HWTI -- --------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_misc.all; library Unisim; use Unisim.all; --------------------------------------------------------------------------- -- Port declarations --------------------------------------------------------------------------- -- Definition of Ports: -- -- Misc. Signals -- clock -- -- HWTI to HWTUL interconnect -- intrfc2thrd_address 32 bits memory -- intrfc2thrd_value 32 bits memory function -- intrfc2thrd_function 16 bits control -- intrfc2thrd_goWait 1 bits control -- -- HWTUL to HWTI interconnect -- thrd2intrfc_address 32 bits memory -- thrd2intrfc_value 32 bits memory function -- thrd2intrfc_function 16 bits function -- thrd2intrfc_opcode 6 bits memory function -- --------------------------------------------------------------------------- -- Thread Manager Entity section --------------------------------------------------------------------------- entity user_logic_hwtul is port ( clock : in std_logic; intrfc2thrd_address : in std_logic_vector(0 to 31); intrfc2thrd_value : in std_logic_vector(0 to 31); intrfc2thrd_function : in std_logic_vector(0 to 15); intrfc2thrd_goWait : in std_logic; thrd2intrfc_address : out std_logic_vector(0 to 31); thrd2intrfc_value : out std_logic_vector(0 to 31); thrd2intrfc_function : out std_logic_vector(0 to 15); thrd2intrfc_opcode : out std_logic_vector(0 to 5) ); end entity user_logic_hwtul; --------------------------------------------------------------------------- -- Architecture section --------------------------------------------------------------------------- architecture IMP of user_logic_hwtul is --------------------------------------------------------------------------- -- Signal declarations --------------------------------------------------------------------------- type state_machine is ( FUNCTION_RESET, FUNCTION_USER_SELECT, FUNCTION_START, FUNCTION_EXIT, STATE_1, STATE_2, STATE_3, STATE_4, STATE_5, STATE_6, STATE_7, STATE_8, STATE_9, STATE_10, STATE_11, STATE_12, STATE_13, STATE_14, STATE_15, STATE_16, STATE_17, STATE_18, STATE_19, STATE_20, WAIT_STATE, ERROR_STATE); -- Function definitions constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000"; constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001"; constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002"; constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003"; constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101"; constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102"; constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103"; constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104"; constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105"; constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106"; constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107"; constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108"; constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109"; constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110"; constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111"; constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112"; constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113"; constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114"; constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115"; constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116"; constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117"; constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118"; constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119"; constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120"; -- Range 0003 to 7999 reserved for user logic's state machine -- Range 8000 to 9999 reserved for system calls constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000"; constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001"; constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010"; constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011"; constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012"; constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013"; constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014"; constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015"; constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016"; constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020"; constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021"; constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022"; constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023"; constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030"; constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031"; constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032"; constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033"; constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034"; constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040"; constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041"; constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042"; constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043"; constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050"; constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051"; constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052"; constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053"; constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054"; -- Ranged A000 to FFFF reserved for supported library calls constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000"; constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001"; constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002"; -- user_opcode Constants constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000"; -- Memory sub-interface specific opcodes constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001"; constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010"; constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011"; constant OPCODE_READ : std_logic_vector(0 to 5) := "000100"; constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101"; constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110"; -- Function sub-interface specific opcodes constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000"; constant OPCODE_POP : std_logic_vector(0 to 5) := "010001"; constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010"; constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011"; constant Z32 : std_logic_vector(0 to 31) := (others => '0'); signal current_state, next_state : state_machine := FUNCTION_RESET; signal return_state, return_state_next: state_machine := FUNCTION_RESET; signal toUser_address : std_logic_vector(0 to 31); signal toUser_value : std_logic_vector(0 to 31); signal toUser_function : std_logic_vector(0 to 15); signal toUser_goWait : std_logic; signal retVal, retVal_next : std_logic_vector(0 to 31); signal arg, arg_next : std_logic_vector(0 to 31); signal reg1, reg1_next : std_logic_vector(0 to 31); signal reg2, reg2_next : std_logic_vector(0 to 31); signal reg3, reg3_next : std_logic_vector(0 to 31); signal reg4, reg4_next : std_logic_vector(0 to 31); signal reg5, reg5_next : std_logic_vector(0 to 31); signal reg6, reg6_next : std_logic_vector(0 to 31); signal reg7, reg7_next : std_logic_vector(0 to 31); signal reg8, reg8_next : std_logic_vector(0 to 31); --------------------------------------------------------------------------- -- Begin architecture --------------------------------------------------------------------------- begin -- architecture IMP HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is begin if (clock'event and (clock = '1')) then toUser_address <= intrfc2thrd_address; toUser_value <= intrfc2thrd_value; toUser_function <= intrfc2thrd_function; toUser_goWait <= intrfc2thrd_goWait; return_state <= return_state_next; retVal <= retVal_next; arg <= arg_next; reg1 <= reg1_next; reg2 <= reg2_next; reg3 <= reg3_next; reg4 <= reg4_next; reg5 <= reg5_next; reg6 <= reg6_next; reg7 <= reg7_next; reg8 <= reg8_next; -- Find out if the HWTI is tell us what to do if (intrfc2thrd_goWait = '1') then case intrfc2thrd_function is -- Typically the HWTI will tell us to control our own destiny when U_FUNCTION_USER_SELECT => current_state <= next_state; -- List all the functions the HWTI could tell us to run when U_FUNCTION_RESET => current_state <= FUNCTION_RESET; when U_FUNCTION_START => current_state <= FUNCTION_START; when U_STATE_1 => current_state <= STATE_1; when U_STATE_2 => current_state <= STATE_2; when U_STATE_3 => current_state <= STATE_3; when U_STATE_4 => current_state <= STATE_4; when U_STATE_5 => current_state <= STATE_5; when U_STATE_6 => current_state <= STATE_6; when U_STATE_7 => current_state <= STATE_7; when U_STATE_8 => current_state <= STATE_8; when U_STATE_9 => current_state <= STATE_9; when U_STATE_10 => current_state <= STATE_10; when U_STATE_11 => current_state <= STATE_11; when U_STATE_12 => current_state <= STATE_12; when U_STATE_13 => current_state <= STATE_13; when U_STATE_14 => current_state <= STATE_14; when U_STATE_15 => current_state <= STATE_15; when U_STATE_16 => current_state <= STATE_16; when U_STATE_17 => current_state <= STATE_17; when U_STATE_18 => current_state <= STATE_18; when U_STATE_19 => current_state <= STATE_19; when U_STATE_20 => current_state <= STATE_20; -- If the HWTI tells us to do something we don't know, error when OTHERS => current_state <= ERROR_STATE; end case; else current_state <= WAIT_STATE; end if; end if; end process HWTUL_STATE_PROCESS; HWTUL_STATE_MACHINE : process (clock) is begin -- Default register assignments thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse thrd2intrfc_address <= Z32; thrd2intrfc_value <= Z32; thrd2intrfc_function <= U_FUNCTION_USER_SELECT; return_state_next <= return_state; next_state <= current_state; retVal_next <= retVal; arg_next <= arg; reg1_next <= reg1; reg2_next <= reg2; reg3_next <= reg3; reg4_next <= reg4; reg5_next <= reg5; reg6_next <= reg6; reg7_next <= reg7; reg8_next <= reg8; -- attr_destroy_3.c -- The state machine case current_state is when FUNCTION_RESET => --Set default values thrd2intrfc_opcode <= OPCODE_NOOP; thrd2intrfc_address <= Z32; thrd2intrfc_value <= Z32; thrd2intrfc_function <= U_FUNCTION_START; -- hthread_attr_t * attr = (hthread_attr_t ) arg when FUNCTION_START => -- Pop the argument thrd2intrfc_value <= Z32; thrd2intrfc_opcode <= OPCODE_POP; next_state <= WAIT_STATE; return_state_next <= STATE_1; -- hthread_attr_init( attr ); when STATE_1 => -- Push the argument to hthread_attr_init arg_next <= intrfc2thrd_value; thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= intrfc2thrd_value; next_state <= WAIT_STATE; return_state_next <= STATE_2; when STATE_2 => -- Call hthread_attr_init thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT; thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3; next_state <= WAIT_STATE; -- retVal = hthread_attr_destroy( attr ); when STATE_3 => -- Push the argument to hthread_attr_init thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= arg; next_state <= WAIT_STATE; return_state_next <= STATE_4; when STATE_4 => -- Call hthread_attr_destroy thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_DESTROY; thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5; next_state <= WAIT_STATE; when STATE_5 => retVal_next <= intrfc2thrd_value; next_state <= FUNCTION_EXIT; when FUNCTION_EXIT => --Same as hthread_exit( (void ) retVal ); thrd2intrfc_value <= retVal; thrd2intrfc_opcode <= OPCODE_RETURN; next_state <= WAIT_STATE; when WAIT_STATE => next_state <= return_state; when ERROR_STATE => next_state <= ERROR_STATE; when others => next_state <= ERROR_STATE; end case; end process HWTUL_STATE_MACHINE; end architecture IMP;
library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.all; use work.pico_cpu.all; --ALU entity entity ALU is generic (BitWidth: integer); port ( A: in std_logic_vector (BitWidth-1 downto 0); B: in std_logic_vector (BitWidth-1 downto 0); Command: in std_logic_vector (3 downto 0); Cflag_in: in std_logic; Cflag_out: out std_logic; Result: out std_logic_vector (BitWidth-1 downto 0) ); end ALU; --Architecture of the DPU architecture RTL of ALU is --------------------------------------------- -- Signals --------------------------------------------- signal AddSub_result: std_logic_vector (BitWidth-1 downto 0) := (others => '0'); signal Cout,Add_Sub: std_logic := '0'; begin --------------------------------------------- -- component instantiation --------------------------------------------- Adder_comp: Adder_Sub generic map (BitWidth => BitWidth) port map (A,B,Add_Sub,AddSub_result,Cout); --------------------------------------------- Cflag_out <= Cout; PROC_ALU: process(Command,A,B,AddSub_result,Cflag_in) begin Add_Sub <= '0'; --adding by default case Command is WHEN "0000" => Result<= AddSub_result; --add WHEN "0001" => Add_Sub <= '1'; Result<= AddSub_result; -- Subtract WHEN "0010" => Result<= A; --Bypass A WHEN "0011" => Result<= B; --Bypass B WHEN "0100" => Result<= A and B; --And WHEN "0101" => Result<= A or B; --or WHEN "0110" => Result<= A xor B; --xor WHEN "0111" => Result<= '0' & A(BitWidth-1 downto 1) ; --shift right WHEN "1000" => Result<= A(BitWidth-2 downto 0)& '0' ; --shift left WHEN "1001" => Result<= not A +1; --negation WHEN "1010" => Result<= A(BitWidth-1) & A(BitWidth-1 downto 1) ; --shift right Arith WHEN "1011" => Result<= A(BitWidth-1) & A(BitWidth-3 downto 0)& A(0) ; --shift left Arith WHEN "1100" => Result<= not(A); --Not of A WHEN "1101" => Result<= (others => '0'); --Clear ACC WHEN "1110" => Result<= Cflag_in & A(BitWidth-1 downto 1); -- RRC WHEN "1111" => Result<= A(BitWidth-2 downto 0)& Cflag_in ; -- RLC WHEN OTHERS => Result<= (others => '0'); END CASE; end process PROC_ALU; end RTL;
-- ------------------------------------------------------------- -- -- Generated Configuration for pads_eastnord -- -- Generated -- by: wig -- on: Thu Jan 19 07:44:48 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio2.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: pads_eastnord-struct-conf-c.vhd,v 1.4 2006/01/19 08:50:41 wig Exp $ -- $Date: 2006/01/19 08:50:41 $ -- $Log: pads_eastnord-struct-conf-c.vhd,v $ -- Revision 1.4 2006/01/19 08:50:41 wig -- Updated testcases, left 6 failing now (constant, bitsplice/X, ...) -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.43 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration pads_eastnord_struct_conf / pads_eastnord -- configuration pads_eastnord_struct_conf of pads_eastnord is for struct -- Generated Configuration for ioc_db2o_10 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_11 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_12 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_13 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_14 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_15 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_10 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_11 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_12 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_13 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_14 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_15 : ioc use configuration work.ioc_rtl_conf; end for; end for; end pads_eastnord_struct_conf; -- -- End of Generated Configuration pads_eastnord_struct_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------
-------------------------------------------------------------------------------- -- Entity: mem_io_synth -- Date:2016-07-17 -- Author: Gideon -- -- Description: Testbench for altera io for ddr -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mem_io_synth is port ( ref_clock : in std_logic := '0'; ref_reset : in std_logic; sys_clock : out std_logic; sys_reset : out std_logic; write_data : out std_logic_vector(15 downto 0); read_data : out std_logic_vector(15 downto 0); do_read : out std_logic; rdata_valid : out std_logic; mode : in std_logic_vector(1 downto 0) := "00"; measurement : out std_logic_vector(11 downto 0); SDRAM_CLK : inout std_logic := 'Z'; SDRAM_CLKn : inout std_logic := 'Z'; SDRAM_A : out std_logic_vector(7 downto 0); SDRAM_DQ : inout std_logic_vector(3 downto 0); SDRAM_DQS : inout std_logic ); end entity; architecture arch of mem_io_synth is signal sys_clock_i : std_logic; signal sys_reset_i : std_logic; signal phasecounterselect : std_logic_vector(2 downto 0) := (others => '0'); signal phasestep : std_logic := '0'; signal phaseupdown : std_logic := '0'; signal phasedone : std_logic := '0'; signal addr_first : std_logic_vector(7 downto 0) := X"00"; signal addr_second : std_logic_vector(7 downto 0) := X"00"; signal wdata : std_logic_vector(15 downto 0) := X"0000"; signal wdata_oe : std_logic; signal counter : unsigned(4 downto 0) := (others => '0'); begin i_mut: entity work.mem_io port map ( ref_clock => ref_clock, ref_reset => ref_reset, sys_clock => sys_clock_i, sys_reset => sys_reset_i, phasecounterselect => phasecounterselect, phasestep => phasestep, phaseupdown => phaseupdown, phasedone => phasedone, mode => mode, measurement => measurement, addr_first => addr_first, addr_second => addr_second, wdata => wdata, wdata_oe => wdata_oe, rdata => read_data, mem_clk_p => SDRAM_CLK, mem_clk_n => SDRAM_CLKn, mem_addr => SDRAM_A, mem_dq => SDRAM_DQ, mem_dqs => SDRAM_DQS ); process(sys_clock_i, phasedone) begin if rising_edge(sys_clock_i) then counter <= counter + 1; wdata_oe <= '0'; addr_first <= (others => '1'); addr_second <= (others => '1'); do_read <= '0'; rdata_valid <= '0'; case counter is when "01101" => addr_first(7) <= '0'; addr_first(5) <= '0'; -- write when "01110" => wdata <= wdata(0) & wdata(15 downto 1); wdata_oe <= '1'; when "01111" => addr_first(7) <= '0'; addr_first(6) <= '0'; -- row when "10000" => addr_first(7) <= '0'; addr_first(4) <= '0'; -- read do_read <= '1'; when "10100" => rdata_valid <= '1'; when "10111" => phasecounterselect <= "101"; -- read clock phasestep <= '1'; when "01100" => phasecounterselect <= "110"; -- measure phasestep <= '1'; when others => null; end case; if sys_reset_i = '1' then phasestep <= '0'; wdata <= X"B769"; end if; end if; if phasedone = '0' then phasestep <= '0'; end if; end process; sys_clock <= sys_clock_i; sys_reset <= sys_reset_i; write_data <= wdata; end arch;
------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2011 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Sep 15, 2011 -- Design Name: FMC-IMAGEON -- Module Name: user_logic.vhd -- Project Name: FMC-IMAGEON -- Target Devices: Virtex-6 -- Kintex-7, Zynq -- Avnet Boards: FMC-IMAGEON -- -- Tool versions: ISE 14.1 -- -- Description: FMC-IMAGEON VITA receiver - User Logic. -- This layer implements the following programming model -- 0x00 - SPI_CONTROL -- [ 0] VITA_RESET -- [ 1] SPI_RESET -- [ 8] SPI_STATUS_BUSY -- [ 9] SPI_STATUS_ERROR -- [16] SPI_TXFIFO_FULL -- [24] SPI_RXFIFO_EMPTY -- 0x04 - SPI_TIMING[15:0] -- 0x08 - SPI_TXFIFO_DATA[31:0] -- 0x0C - SPI_RXFIFO_DATA[31:0] -- 0x10 - ISERDES_CONTROL -- [ 0] ISERDES_RESET -- [ 1] ISERDES_AUTO_ALIGN -- [ 2] ISERDES_ALIGN_START -- [ 3] ISERDES_FIFO_ENABLE -- [ 8] ISERDES_CLK_READY -- [ 9] ISERDES_ALIGN_BUSY -- [10] ISERDES_ALIGNED -- [23:16] ISERDES_TXCLK_STATUS -- [31:24] ISERDES_RXCLK_STATUS -- 0x14 - ISERDES_TRAINING -- 0x18 - ISERDES_MANUAL_TAP -- 0x1C - {unused} -- 0x20 - DECODER_CONTROL -- [0] DECODER_RESET -- [1] DECODER_ENABLE -- 0x24 - DECODER_STARTODDEVEN -- 0x28 - DECODER_CODES_LS_LE -- [15: 0] CODE_LS -- [31:16] CODE_LE -- 0x2C - DECODER_CODES_FS_FE -- [15: 0] CODE_FS -- [31:16] CODE_FE -- 0x30 - DECODER_CODES_BL_IMG -- [15: 0] CODE_BL -- [31:16] CODE_IMG -- 0x34 - DECODER_CODES_TR_CRC -- [15: 0] CODE_TR -- [31:16] CODE_CRC -- 0x38 - DECODER_CNT_BLACK_LINES -- 0x3C - DECODER_CNT_IMAGE_LINES -- 0x40 - DECODER_CNT_BLACK_PIXELS -- 0x44 - DECODER_CNT_IMAGE_PIXELS -- 0x48 - DECODER_CNT_FRAMES -- 0x4C - DECODER_CNT_WINDOWS -- 0x50 - DECODER_CNT_CLOCKS -- 0x54 - DECODER_CNT_START_LINES -- 0x58 - DECODER_CNT_END_LINES -- 0x5C - SYNCGEN_DELAY -- [15: 0] DELAY -- 0x60 - SYNCGEN_HTIMING1 -- [15: 0] HACTIVE -- [31:16] HFPORCH -- 0x64 - SYNCGEN_HTIMING2 -- [15: 0] HSYNC -- [31:16] HBPORCH -- 0x68 - SYNCGEN_VTIMING1 -- [15: 0] VACTIVE -- [31:16] VFPORCH -- 0x6C - SYNCGEN_VTIMING2 -- [15: 0] VSYNC -- [31:16] VBPORCH -- 0x70 - CRC_CONTROL -- [0] CRC_RESET -- [1] CRC_INITVALUE -- 0x74 - CRC_STATUS -- 0x78 - REMAPPER_CONTROL[7:0] -- [2:0] REMAPPER_WRITE_CFG -- [6:4] REMAPPER_MODE -- 0x7C - {unused} -- 0x80 - FPN_PRNU_VALUES[ 31: 0] -- [ 7: 0] PRNU_0 -- [15: 8] FPN_0 -- [23:16] PRNU_1 -- [31:24] FPN_1 -- 0x84 - FPN_PRNU_VALUES[ 63: 32] -- [ 7: 0] PRNU_2 -- [15: 8] FPN_2 -- [23:16] PRNU_3 -- [31:24] FPN_3 -- 0x88 - FPN_PRNU_VALUES[ 95: 64] -- 0x8C - FPN_PRNU_VALUES[127: 96] -- 0x90 - FPN_PRNU_VALUES[159:128] -- 0x94 - FPN_PRNU_VALUES[191:160] -- 0x98 - FPN_PRNU_VALUES[223:192] -- 0x9C - FPN_PRNU_VALUES[255:224] -- [ 7: 0] PRNU_14 -- [15: 8] FPN_14 -- [23:16] PRNU_15 -- [31:24] FPN_15 -- 0xA0 - {unused} -- 0xA4 - {unused} -- 0xA8 - {unused} -- 0xAC - {unused} -- 0xB0 - {unused} -- 0xB4 - {unused} -- 0xB8 - {unused} -- 0xBC - {unused} -- 0xC0 - DECODER_CNT_MONITOR0_HIGH -- 0xC4 - DECODER_CNT_MONITOR0_LOW -- 0xC8 - DECODER_CNT_MONITOR1_HIGH -- 0xCC - DECODER_CNT_MONITOR1_LOW -- 0xD0 - {unused} -- 0xD4 - {unused} -- 0xD8 - {unused} -- 0xDC - TRIGGEN_EXT_DEBOUNCE -- 0xE0 - TRIGGEN_CONTROL -- [ 2: 0] TRIGGEN_ENABLE -- [ 6: 4] TRIGGEN_SYNC2READOUT -- [ 8] TRIGGEN_READOUTTRIGGER -- [ 16] TRIGGEN_EXT_POLARITY -- [ 24] TRIGGEN_CNT_UPDATE -- [30:28] TRIGGEN_GEN_POLARITY -- 0xE4 - TRIGGEN_DEFAULT_FREQ -- 0xE8 - TRIGGEN_TRIG0_HIGH -- 0xEC - TRIGGEN_TRIG0_LOW -- 0xF0 - TRIGGEN_TRIG1_HIGH -- 0xF4 - TRIGGEN_TRIG1_LOW -- 0xF8 - TRIGGEN_TRIG2_HIGH -- 0xFC - TRIGGEN_TRIG2_LOW -- -- -- Dependencies: -- -- Revision: Sep 15, 2011: 1.00 Initial version: -- - VITA SPI controller -- Sep 22, 2011: 1.01 Added: -- - ISERDES interface -- Sep 28, 2011: 1.02 Added: -- - sync channel decoder -- - crc checker -- - data remapper -- Oct 20, 2011: 1.03 Modify: -- - iserdes (use BUFR) -- Oct 21, 2011: 1.04 Added: -- - fpn prnu correction -- Nov 03, 2011: 1.05 Added: -- - trigger generator -- Dec 19, 2011: 1.06 Modified: -- - port to Kintex-7 -- Jan 12, 2012: 1.07 Added: -- - new fsync output port -- Modify: -- - syncgen -- Feb 06, 2012: 1.08 Modify: -- - triggergenerator -- (new version with debounce logic) -- - new C_XSVI_DIRECT_OUTPUT option -- Feb 22, 2012: 1.09 Modified -- - port to Zynq -- - new C_XSVI_USE_SYNCGEN option -- May 13, 2012: 1.10 Optimize -- - remove one layer of registers -- May 28, 2012: 1.11 Added -- - host_triggen_cnt_update -- (for simultaneous update of high/low values) -- - host_triggen_gen_polarity -- Jun 01, 2012: 1.12 Modify: -- - Move syncgen after demux_fifo -- - Increase size of demux_fifo -- (to tolerate jitter in video timing from sensor) -- - Add programmable delay on framestart for syncgen -- Jul 31, 2012: 1.13 Modify: -- - define clk200, clk, clk4x with SIGIS = CLK -- - define reset with SIGIS = RST -- - port to Spartan-6 -- ------------------------------------------------------------------ ------------------------------------------------------------------------------ -- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- -- ************************************************************************* -- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -- -- Xilinx, Inc. -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE. -- -- ************************************************************************* -- ------------------------------------------------------------------------------ -- Filename: user_logic.vhd -- Version: 1.00.a -- Description: User logic. -- Date: Thu Sep 15 13:07:23 2011 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port: "_i" -- device pins: "_pin" -- ports: "- Names begin with Uppercase" -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here library fmc_imageon_vita_receiver_v1_13_a; use fmc_imageon_vita_receiver_v1_13_a.fmc_imageon_vita_core; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Addr -- Bus to IP address bus -- Bus2IP_CS -- Bus to IP chip select -- Bus2IP_RNW -- Bus to IP read/not write -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here C_XSVI_DATA_WIDTH : integer := 10; C_XSVI_DIRECT_OUTPUT : integer := 0; C_XSVI_USE_SYNCGEN : integer := 1; C_FAMILY : string := "virtex6"; -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 64; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here clk200 : in std_logic; clk : in std_logic; clk4x : in std_logic; reset : in std_logic; oe : in std_logic; -- I/O pins io_vita_clk_pll : out std_logic; io_vita_reset_n : out std_logic; io_vita_spi_sclk : out std_logic; io_vita_spi_ssel_n : out std_logic; io_vita_spi_mosi : out std_logic; io_vita_spi_miso : in std_logic; io_vita_trigger : out std_logic_vector(2 downto 0); io_vita_monitor : in std_logic_vector(1 downto 0); io_vita_clk_out_p : in std_logic; io_vita_clk_out_n : in std_logic; io_vita_sync_p : in std_logic; io_vita_sync_n : in std_logic; io_vita_data_p : in std_logic_vector(7 downto 0); io_vita_data_n : in std_logic_vector(7 downto 0); -- Trigger Port trigger1 : in std_logic; -- Frame Sync Port fsync : out std_logic; -- XSVI Port xsvi_vsync_o : out std_logic; xsvi_hsync_o : out std_logic; xsvi_vblank_o : out std_logic; xsvi_hblank_o : out std_logic; xsvi_active_video_o : out std_logic; xsvi_video_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0); -- Debug Ports debug_host_o : out std_logic_vector(231 downto 0); debug_spi_o : out std_logic_vector( 95 downto 0); debug_iserdes_o : out std_logic_vector(229 downto 0); debug_decoder_o : out std_logic_vector(186 downto 0); debug_crc_o : out std_logic_vector( 87 downto 0); debug_triggen_o : out std_logic_vector( 9 downto 0); debug_video_o : out std_logic_vector( 31 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Addr : in std_logic_vector(0 to 31); Bus2IP_CS : in std_logic_vector(0 to 0); Bus2IP_RNW : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg30 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg31 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg32 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg33 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg34 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg35 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg36 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg37 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg38 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg39 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg55 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg56 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg57 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg58 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg59 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg60 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg61 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg62 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg63 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg_write_sel : std_logic_vector(63 downto 0); signal slv_reg_read_sel : std_logic_vector(63 downto 0); signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; signal slv_reg4_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg4_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg5_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg6_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg8_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg9_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg10_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg11_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg12_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg13_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg14_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg15_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg16_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg17_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg18_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg19_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg20_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg21_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg22_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg23_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg24_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg25_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg26_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg27_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg28_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg29_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg30_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg32_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg33_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg34_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg35_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg36_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg37_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg38_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg39_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg48_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg49_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg50_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg51_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg55_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg56_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg57_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg58_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg59_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg60_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg61_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg62_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg63_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- HOST Interface - VITA signal host_vita_reset : std_logic; -- HOST Interface - SPI signal host_spi_clk : std_logic; signal host_spi_reset : std_logic; signal host_spi_timing : std_logic_vector(15 downto 0); signal host_spi_status_busy : std_logic; signal host_spi_status_error : std_logic; signal host_spi_txfifo_clk : std_logic; signal host_spi_txfifo_wen_a1 : std_logic; signal host_spi_txfifo_wen : std_logic; signal host_spi_txfifo_din : std_logic_vector(31 downto 0); signal host_spi_txfifo_full : std_logic; signal host_spi_rxfifo_clk : std_logic; signal host_spi_rxfifo_ren : std_logic; signal host_spi_rxfifo_dout : std_logic_vector(31 downto 0); signal host_spi_rxfifo_empty : std_logic; -- HOST Interface - ISERDES signal host_iserdes_reset : std_logic; signal host_iserdes_auto_align : std_logic; signal host_iserdes_align_start : std_logic; signal host_iserdes_fifo_enable : std_logic; signal host_iserdes_manual_tap : std_logic_vector(9 downto 0); signal host_iserdes_training : std_logic_vector(9 downto 0); -- signal host_iserdes_clk_ready : std_logic; signal host_iserdes_clk_status : std_logic_vector(15 downto 0); signal host_iserdes_align_busy : std_logic; signal host_iserdes_aligned : std_logic; -- HOST Interface - Sync Channel Decoder signal host_decoder_reset : std_logic; signal host_decoder_enable : std_logic; signal host_decoder_startoddeven : std_logic_vector(31 downto 0); signal host_decoder_code_ls : std_logic_vector(9 downto 0); signal host_decoder_code_le : std_logic_vector(9 downto 0); signal host_decoder_code_fs : std_logic_vector(9 downto 0); signal host_decoder_code_fe : std_logic_vector(9 downto 0); signal host_decoder_code_bl : std_logic_vector(9 downto 0); signal host_decoder_code_img : std_logic_vector(9 downto 0); signal host_decoder_code_tr : std_logic_vector(9 downto 0); signal host_decoder_code_crc : std_logic_vector(9 downto 0); signal host_decoder_frame_start : std_logic; signal host_decoder_cnt_black_lines : std_logic_vector(31 downto 0); signal host_decoder_cnt_image_lines : std_logic_vector(31 downto 0); signal host_decoder_cnt_black_pixels : std_logic_vector(31 downto 0); signal host_decoder_cnt_image_pixels : std_logic_vector(31 downto 0); signal host_decoder_cnt_frames : std_logic_vector(31 downto 0); signal host_decoder_cnt_windows : std_logic_vector(31 downto 0); signal host_decoder_cnt_clocks : std_logic_vector(31 downto 0); signal host_decoder_cnt_start_lines : std_logic_vector(31 downto 0); signal host_decoder_cnt_end_lines : std_logic_vector(31 downto 0); signal host_decoder_cnt_monitor0high : std_logic_vector(31 downto 0); signal host_decoder_cnt_monitor0low : std_logic_vector(31 downto 0); signal host_decoder_cnt_monitor1high : std_logic_vector(31 downto 0); signal host_decoder_cnt_monitor1low : std_logic_vector(31 downto 0); -- HOST Interface - CRC Checker signal host_crc_reset : std_logic; signal host_crc_initvalue : std_logic; signal host_crc_status : std_logic_vector(31 downto 0); -- HOST Interface - Data Channel Remapper signal host_remapper_write_cfg : std_logic_vector(2 downto 0); signal host_remapper_mode : std_logic_vector(2 downto 0); -- HOST Interface - Trigger Generator signal host_triggen_enable : std_logic_vector(2 downto 0); signal host_triggen_sync2readout : std_logic_vector(2 downto 0); signal host_triggen_readouttrigger : std_logic; signal host_triggen_default_freq : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger0high : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger0low : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger1high : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger1low : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger2high : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger2low : std_logic_vector(31 downto 0); signal host_triggen_ext_debounce : std_logic_vector(31 downto 0); signal host_triggen_ext_polarity : std_logic; signal host_triggen_cnt_update : std_logic; signal host_triggen_gen_polarity : std_logic_vector(2 downto 0); -- HOST Interface - FPN/PRNU Correction signal host_fpn_prnu_values : std_logic_vector((1616)-1 downto 0); -- HOST Interface - Sync Generator signal host_syncgen_delay : std_logic_vector(15 downto 0); signal host_syncgen_hactive : std_logic_vector(15 downto 0); signal host_syncgen_hfporch : std_logic_vector(15 downto 0); signal host_syncgen_hsync : std_logic_vector(15 downto 0); signal host_syncgen_hbporch : std_logic_vector(15 downto 0); signal host_syncgen_vactive : std_logic_vector(15 downto 0); signal host_syncgen_vfporch : std_logic_vector(15 downto 0); signal host_syncgen_vsync : std_logic_vector(15 downto 0); signal host_syncgen_vbporch : std_logic_vector(15 downto 0); begin --USER logic implementation added here ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, -- you are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register -- "1000" C_BASEADDR + 0x0 -- "0100" C_BASEADDR + 0x4 -- "0010" C_BASEADDR + 0x8 -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ slv_reg_write_sel <= Bus2IP_WrCE(63 downto 0); slv_reg_read_sel <= Bus2IP_RdCE(63 downto 0); slv_write_ack <= Bus2IP_WrCE( 0) or Bus2IP_WrCE( 1) or Bus2IP_WrCE( 2) or Bus2IP_WrCE( 3) or Bus2IP_WrCE( 4) or Bus2IP_WrCE( 5) or Bus2IP_WrCE( 6) or Bus2IP_WrCE( 7) or Bus2IP_WrCE( 8) or Bus2IP_WrCE( 9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31) or Bus2IP_WrCE(32) or Bus2IP_WrCE(33) or Bus2IP_WrCE(34) or Bus2IP_WrCE(35) or Bus2IP_WrCE(36) or Bus2IP_WrCE(37) or Bus2IP_WrCE(38) or Bus2IP_WrCE(39) or Bus2IP_WrCE(40) or Bus2IP_WrCE(41) or Bus2IP_WrCE(42) or Bus2IP_WrCE(43) or Bus2IP_WrCE(44) or Bus2IP_WrCE(45) or Bus2IP_WrCE(46) or Bus2IP_WrCE(47) or Bus2IP_WrCE(48) or Bus2IP_WrCE(49) or Bus2IP_WrCE(50) or Bus2IP_WrCE(51) or Bus2IP_WrCE(52) or Bus2IP_WrCE(53) or Bus2IP_WrCE(54) or Bus2IP_WrCE(55) or Bus2IP_WrCE(56) or Bus2IP_WrCE(57) or Bus2IP_WrCE(58) or Bus2IP_WrCE(59) or Bus2IP_WrCE(60) or Bus2IP_WrCE(61) or Bus2IP_WrCE(62) or Bus2IP_WrCE(63); slv_read_ack <= Bus2IP_RdCE( 0) or Bus2IP_RdCE( 1) or Bus2IP_RdCE( 2) or Bus2IP_RdCE( 3) or Bus2IP_RdCE( 4) or Bus2IP_RdCE( 5) or Bus2IP_RdCE( 6) or Bus2IP_RdCE( 7) or Bus2IP_RdCE( 8) or Bus2IP_RdCE( 9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31) or Bus2IP_RdCE(32) or Bus2IP_RdCE(33) or Bus2IP_RdCE(34) or Bus2IP_RdCE(35) or Bus2IP_RdCE(36) or Bus2IP_RdCE(37) or Bus2IP_RdCE(38) or Bus2IP_RdCE(39) or Bus2IP_RdCE(40) or Bus2IP_RdCE(41) or Bus2IP_RdCE(42) or Bus2IP_RdCE(43) or Bus2IP_RdCE(44) or Bus2IP_RdCE(45) or Bus2IP_RdCE(46) or Bus2IP_RdCE(47) or Bus2IP_RdCE(48) or Bus2IP_RdCE(49) or Bus2IP_RdCE(50) or Bus2IP_RdCE(51) or Bus2IP_RdCE(52) or Bus2IP_RdCE(53) or Bus2IP_RdCE(54) or Bus2IP_RdCE(55) or Bus2IP_RdCE(56) or Bus2IP_RdCE(57) or Bus2IP_RdCE(58) or Bus2IP_RdCE(59) or Bus2IP_RdCE(60) or Bus2IP_RdCE(61) or Bus2IP_RdCE(62) or Bus2IP_RdCE(63); -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); slv_reg3 <= (others => '0'); slv_reg4 <= (others => '0'); slv_reg5 <= (others => '0'); slv_reg6 <= (others => '0'); slv_reg7 <= (others => '0'); slv_reg8 <= (others => '0'); slv_reg9 <= (others => '0'); slv_reg10 <= (others => '0'); slv_reg11 <= (others => '0'); slv_reg12 <= (others => '0'); slv_reg13 <= (others => '0'); slv_reg14 <= (others => '0'); slv_reg15 <= (others => '0'); slv_reg16 <= (others => '0'); slv_reg17 <= (others => '0'); slv_reg18 <= (others => '0'); slv_reg19 <= (others => '0'); slv_reg20 <= (others => '0'); slv_reg21 <= (others => '0'); slv_reg22 <= (others => '0'); slv_reg23 <= (others => '0'); slv_reg24 <= (others => '0'); slv_reg25 <= (others => '0'); slv_reg26 <= (others => '0'); slv_reg27 <= (others => '0'); slv_reg28 <= (others => '0'); slv_reg29 <= (others => '0'); slv_reg30 <= (others => '0'); slv_reg31 <= (others => '0'); slv_reg32 <= (others => '0'); slv_reg33 <= (others => '0'); slv_reg34 <= (others => '0'); slv_reg35 <= (others => '0'); slv_reg36 <= (others => '0'); slv_reg37 <= (others => '0'); slv_reg38 <= (others => '0'); slv_reg39 <= (others => '0'); -- slv_reg55 <= (others => '0'); slv_reg56 <= (others => '0'); slv_reg57 <= (others => '0'); slv_reg58 <= (others => '0'); slv_reg59 <= (others => '0'); slv_reg60 <= (others => '0'); slv_reg61 <= (others => '0'); slv_reg62 <= (others => '0'); slv_reg63 <= (others => '0'); else case slv_reg_write_sel is when "1000000000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0100000000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0010000000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg2(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0001000000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg3(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000100000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg4(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000010000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg5(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000001000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg6(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000100000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg7(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000010000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg8(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000001000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg9(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000100000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg10(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000010000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg11(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000001000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg12(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000100000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg13(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000010000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg14(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000001000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg15(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000100000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg16(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000010000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg17(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000001000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg18(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000100000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg19(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000010000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg20(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000001000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg21(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000100000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg22(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000010000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg23(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000001000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg24(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000100000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg25(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000010000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg26(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000001000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg27(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000100000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg28(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000010000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg29(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000001000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg30(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000100000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg31(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000010000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg32(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000001000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg33(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000100000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg34(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000010000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg35(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000001000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg36(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000100000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg37(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000010000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg38(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000001000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg39(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; -- when "0000000000000000000000000000000000000000000000000000000100000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg55(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000010000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg56(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000001000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg57(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000100000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg58(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000010000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg59(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000001000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg60(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000000100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg61(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000000010" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg62(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000000001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg63(byte_index8+7 downto byte_index8) <= Bus2IP_Data(byte_index8+7 downto byte_index8); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39 ) is begin case slv_reg_read_sel is when "1000000000000000000000000000000000000000000000000000000000000000" => --slv_ip2bus_data <= slv_reg0; -- 0x00 - SPI_CONTROL -- [ 0] VITA_RESET -- [ 1] SPI_RESET -- [ 8] SPI_STATUS_BUSY -- [ 9] SPI_STATUS_ERROR -- [16] SPI_TXFIFO_FULL -- [24] SPI_RXFIFO_EMPTY slv_ip2bus_data <= "0000000" & host_spi_rxfifo_empty & "0000000" & host_spi_txfifo_full & "000000" & host_spi_status_error & host_spi_status_busy & "000000" & host_spi_reset & host_vita_reset; when "0100000000000000000000000000000000000000000000000000000000000000" => -- 0x04 - SPI_TIMING[15:0] slv_ip2bus_data <= slv_reg1; when "0010000000000000000000000000000000000000000000000000000000000000" => -- 0x08 - SPI_TXFIFO_DATA[31:0] slv_ip2bus_data <= slv_reg2; when "0001000000000000000000000000000000000000000000000000000000000000" => --slv_ip2bus_data <= slv_reg3; -- 0x0C - SPI_RXFIFO_DATA[31:0] slv_ip2bus_data <= host_spi_rxfifo_dout; when "0000100000000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg4_r1; when "0000010000000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg5; when "0000001000000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg6; when "0000000100000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg7; when "0000000010000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg8; when "0000000001000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg9; when "0000000000100000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg10; when "0000000000010000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg11; when "0000000000001000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg12; when "0000000000000100000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg13; when "0000000000000010000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg14_r1; when "0000000000000001000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg15_r1; when "0000000000000000100000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg16_r1; when "0000000000000000010000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg17_r1; when "0000000000000000001000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg18_r1; when "0000000000000000000100000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg19_r1; when "0000000000000000000010000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg20_r1; when "0000000000000000000001000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg21_r1; when "0000000000000000000000100000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg22_r1; when "0000000000000000000000010000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg23; when "0000000000000000000000001000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg24; when "0000000000000000000000000100000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg25; when "0000000000000000000000000010000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg26; when "0000000000000000000000000001000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg27; when "0000000000000000000000000000100000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg28; when "0000000000000000000000000000010000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg29_r1; when "0000000000000000000000000000001000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg30; when "0000000000000000000000000000000100000000000000000000000000000000" => slv_ip2bus_data <= slv_reg31; when "0000000000000000000000000000000010000000000000000000000000000000" => slv_ip2bus_data <= slv_reg32; when "0000000000000000000000000000000001000000000000000000000000000000" => slv_ip2bus_data <= slv_reg33; when "0000000000000000000000000000000000100000000000000000000000000000" => slv_ip2bus_data <= slv_reg34; when "0000000000000000000000000000000000010000000000000000000000000000" => slv_ip2bus_data <= slv_reg35; when "0000000000000000000000000000000000001000000000000000000000000000" => slv_ip2bus_data <= slv_reg36; when "0000000000000000000000000000000000000100000000000000000000000000" => slv_ip2bus_data <= slv_reg37; when "0000000000000000000000000000000000000010000000000000000000000000" => slv_ip2bus_data <= slv_reg38; when "0000000000000000000000000000000000000001000000000000000000000000" => slv_ip2bus_data <= slv_reg39; -- when "0000000000000000000000000000000000000000000000001000000000000000" => slv_ip2bus_data <= slv_reg48_r1; when "0000000000000000000000000000000000000000000000000100000000000000" => slv_ip2bus_data <= slv_reg49_r1; when "0000000000000000000000000000000000000000000000000010000000000000" => slv_ip2bus_data <= slv_reg50_r1; when "0000000000000000000000000000000000000000000000000001000000000000" => slv_ip2bus_data <= slv_reg51_r1; -- when "0000000000000000000000000000000000000000000000000000000100000000" => slv_ip2bus_data <= slv_reg55; when "0000000000000000000000000000000000000000000000000000000010000000" => slv_ip2bus_data <= slv_reg56; when "0000000000000000000000000000000000000000000000000000000001000000" => slv_ip2bus_data <= slv_reg57; when "0000000000000000000000000000000000000000000000000000000000100000" => slv_ip2bus_data <= slv_reg58; when "0000000000000000000000000000000000000000000000000000000000010000" => slv_ip2bus_data <= slv_reg59; when "0000000000000000000000000000000000000000000000000000000000001000" => slv_ip2bus_data <= slv_reg60; when "0000000000000000000000000000000000000000000000000000000000000100" => slv_ip2bus_data <= slv_reg61; when "0000000000000000000000000000000000000000000000000000000000000010" => slv_ip2bus_data <= slv_reg62; when "0000000000000000000000000000000000000000000000000000000000000001" => slv_ip2bus_data <= slv_reg63; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; -- -- HOST Interface - SPI -- host_spi_clk <= Bus2IP_Clk; host_spi_txfifo_clk <= Bus2IP_Clk; host_spi_rxfifo_clk <= Bus2IP_Clk; host_spi_process : process ( Bus2IP_Clk ) begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then host_vita_reset <= '0'; host_spi_reset <= '0'; host_spi_timing <= (others => '0'); host_spi_txfifo_wen_a1 <= '0'; host_spi_txfifo_wen <= '0'; host_spi_txfifo_din <= (others => '0'); host_spi_rxfifo_ren <= '0'; else -- 0x00 - SPI_CONTROL -- [ 0] VITA_RESET -- [ 1] SPI_RESET -- [ 8] SPI_STATUS_BUSY -- [ 9] SPI_STATUS_ERROR -- [16] SPI_TXFIFO_FULL -- [24] SPI_RXFIFO_EMPTY host_vita_reset <= slv_reg0(0); host_spi_reset <= slv_reg0(1); host_spi_timing <= slv_reg1(15 downto 0); -- slv_reg2 is valid 1 cycle after slv_reg_write_sel(63-2) host_spi_txfifo_wen_a1 <= slv_reg_write_sel(63-2); host_spi_txfifo_wen <= host_spi_txfifo_wen_a1; host_spi_txfifo_din <= slv_reg2; -- use write to pop value from RXFIFO ... host_spi_rxfifo_ren <= slv_reg_write_sel(63-3); end if; end if; end process host_spi_process; slv_reg4_w1 <= slv_reg4; slv_reg5_w1 <= slv_reg5; slv_reg6_w1 <= slv_reg6; slv_reg8_w1 <= slv_reg8; slv_reg9_w1 <= slv_reg9; slv_reg10_w1 <= slv_reg10; slv_reg11_w1 <= slv_reg11; slv_reg12_w1 <= slv_reg12; slv_reg13_w1 <= slv_reg13; slv_reg23_w1 <= slv_reg23; slv_reg24_w1 <= slv_reg24; slv_reg25_w1 <= slv_reg25; slv_reg26_w1 <= slv_reg26; slv_reg27_w1 <= slv_reg27; slv_reg28_w1 <= slv_reg28; slv_reg30_w1 <= slv_reg30; -- slv_reg32_w1 <= slv_reg32; slv_reg33_w1 <= slv_reg33; slv_reg34_w1 <= slv_reg34; slv_reg35_w1 <= slv_reg35; slv_reg36_w1 <= slv_reg36; slv_reg37_w1 <= slv_reg37; slv_reg38_w1 <= slv_reg38; slv_reg39_w1 <= slv_reg39; -- slv_reg55_w1 <= slv_reg55; slv_reg56_w1 <= slv_reg56; slv_reg57_w1 <= slv_reg57; slv_reg58_w1 <= slv_reg58; slv_reg59_w1 <= slv_reg59; slv_reg60_w1 <= slv_reg60; slv_reg61_w1 <= slv_reg61; slv_reg62_w1 <= slv_reg62; slv_reg63_w1 <= slv_reg63; host_iserdes_process : process ( clk ) begin if clk'event and clk = '1' then if reset = '1' then -- slv_reg4_w1 <= (others => '0'); slv_reg4_r1 <= (others => '0'); -- slv_reg5_w1 <= (others => '0'); -- slv_reg6_w1 <= (others => '0'); -- slv_reg8_w1 <= (others => '0'); -- slv_reg9_w1 <= (others => '0'); -- slv_reg10_w1 <= (others => '0'); -- slv_reg11_w1 <= (others => '0'); -- slv_reg12_w1 <= (others => '0'); -- slv_reg13_w1 <= (others => '0'); slv_reg14_r1 <= (others => '0'); slv_reg15_r1 <= (others => '0'); slv_reg16_r1 <= (others => '0'); slv_reg17_r1 <= (others => '0'); slv_reg18_r1 <= (others => '0'); slv_reg19_r1 <= (others => '0'); slv_reg20_r1 <= (others => '0'); slv_reg21_r1 <= (others => '0'); slv_reg22_r1 <= (others => '0'); -- slv_reg23_w1 <= (others => '0'); -- slv_reg24_w1 <= (others => '0'); -- slv_reg25_w1 <= (others => '0'); -- slv_reg26_w1 <= (others => '0'); -- slv_reg27_w1 <= (others => '0'); -- slv_reg28_w1 <= (others => '0'); slv_reg29_r1 <= (others => '0'); -- slv_reg30_w1 <= (others => '0'); -- -- slv_reg32_w1 <= (others => '0'); -- slv_reg33_w1 <= (others => '0'); -- slv_reg34_w1 <= (others => '0'); -- slv_reg35_w1 <= (others => '0'); -- slv_reg36_w1 <= (others => '0'); -- slv_reg37_w1 <= (others => '0'); -- slv_reg38_w1 <= (others => '0'); -- slv_reg39_w1 <= (others => '0'); -- slv_reg48_r1 <= (others => '0'); slv_reg49_r1 <= (others => '0'); slv_reg50_r1 <= (others => '0'); slv_reg51_r1 <= (others => '0'); -- -- slv_reg55_w1 <= (others => '0'); -- slv_reg56_w1 <= (others => '0'); -- slv_reg57_w1 <= (others => '0'); -- slv_reg58_w1 <= (others => '0'); -- slv_reg59_w1 <= (others => '0'); -- slv_reg60_w1 <= (others => '0'); -- slv_reg61_w1 <= (others => '0'); -- slv_reg62_w1 <= (others => '0'); -- slv_reg63_w1 <= (others => '0'); -- host_iserdes_reset <= '0'; host_iserdes_auto_align <= '0'; host_iserdes_align_start <= '0'; host_iserdes_fifo_enable <= '0'; host_iserdes_training <= (others => '0'); host_iserdes_manual_tap <= (others => '0'); -- host_fpn_prnu_values <= (others => '0'); -- host_triggen_enable <= (others => '0'); host_triggen_sync2readout <= (others => '0'); host_triggen_readouttrigger <= '0'; host_triggen_default_freq <= (others => '0'); host_triggen_cnt_trigger0high <= (others => '0'); host_triggen_cnt_trigger0low <= (others => '0'); host_triggen_cnt_trigger1high <= (others => '0'); host_triggen_cnt_trigger1low <= (others => '0'); host_triggen_cnt_trigger2high <= (others => '0'); host_triggen_cnt_trigger2low <= (others => '0'); host_triggen_ext_debounce <= (others => '0'); host_triggen_ext_polarity <= '0'; host_triggen_cnt_update <= '0'; else -- slv_reg4_w1 <= slv_reg4; -- slv_reg5_w1 <= slv_reg5; -- slv_reg6_w1 <= slv_reg6; -- slv_reg8_w1 <= slv_reg8; -- slv_reg9_w1 <= slv_reg9; -- slv_reg10_w1 <= slv_reg10; -- slv_reg11_w1 <= slv_reg11; -- slv_reg12_w1 <= slv_reg12; -- slv_reg13_w1 <= slv_reg13; -- slv_reg23_w1 <= slv_reg23; -- slv_reg24_w1 <= slv_reg24; -- slv_reg25_w1 <= slv_reg25; -- slv_reg26_w1 <= slv_reg26; -- slv_reg27_w1 <= slv_reg27; -- slv_reg28_w1 <= slv_reg28; -- slv_reg30_w1 <= slv_reg30; -- -- slv_reg32_w1 <= slv_reg32; -- slv_reg33_w1 <= slv_reg33; -- slv_reg34_w1 <= slv_reg34; -- slv_reg35_w1 <= slv_reg35; -- slv_reg36_w1 <= slv_reg36; -- slv_reg37_w1 <= slv_reg37; -- slv_reg38_w1 <= slv_reg38; -- slv_reg39_w1 <= slv_reg39; -- -- slv_reg55_w1 <= slv_reg55; -- slv_reg56_w1 <= slv_reg56; -- slv_reg57_w1 <= slv_reg57; -- slv_reg58_w1 <= slv_reg58; -- slv_reg59_w1 <= slv_reg59; -- slv_reg60_w1 <= slv_reg60; -- slv_reg61_w1 <= slv_reg61; -- slv_reg62_w1 <= slv_reg62; -- slv_reg63_w1 <= slv_reg63; -- -- 0x10 - ISERDES_CONTROL -- [ 0] ISERDES_RESET -- [ 1] ISERDES_AUTO_ALIGN -- [ 2] ISERDES_ALIGN_START -- [ 3] ISERDES_FIFO_ENABLE -- [ 8] ISERDES_CLK_READY -- [ 9] ISERDES_ALIGN_BUSY -- [10] ISERDES_ALIGNED -- [23:16] ISERDES_TXCLK_STATUS -- [31:24] ISERDES_RXCLK_STATUS host_iserdes_reset <= slv_reg4_w1(0); host_iserdes_auto_align <= slv_reg4_w1(1); host_iserdes_align_start <= slv_reg4_w1(2); host_iserdes_fifo_enable <= slv_reg4_w1(3); slv_reg4_r1 <= host_iserdes_clk_status & "00000" & host_iserdes_aligned & host_iserdes_align_busy & host_iserdes_clk_ready & "0000" & host_iserdes_fifo_enable & host_iserdes_align_start & host_iserdes_auto_align & host_iserdes_reset; -- -- 0x14 - ISERDES_TRAINING host_iserdes_training <= slv_reg5_w1(9 downto 0); -- -- 0x18 - ISERDES_MANUAL_TAP host_iserdes_manual_tap <= slv_reg6_w1(9 downto 0); -- -- 0x20 - DECODER_CONTROL[7:0] -- [0] DECODER_RESET -- [1] DECODER_ENABLE host_decoder_reset <= slv_reg8_w1(0); host_decoder_enable <= slv_reg8_w1(1); -- -- 0x24 - DECODER_STARTODDEVEN host_decoder_startoddeven <= slv_reg9_w1; -- -- 0x28 - DECODER_CODES_LS_LE host_decoder_code_ls <= slv_reg10_w1( 9 downto 0); host_decoder_code_le <= slv_reg10_w1(25 downto 16); -- -- 0x2C - DECODER_CODES_FS_FE host_decoder_code_fs <= slv_reg11_w1( 9 downto 0); host_decoder_code_fe <= slv_reg11_w1(25 downto 16); -- -- 0x30 - DECODER_CODES_BL_IMG host_decoder_code_bl <= slv_reg12_w1( 9 downto 0); host_decoder_code_img <= slv_reg12_w1(25 downto 16); -- -- 0x34 - DECODER_CODES_TR_CRC host_decoder_code_tr <= slv_reg13_w1( 9 downto 0); host_decoder_code_crc <= slv_reg13_w1(25 downto 16); if ( host_decoder_frame_start = '1' ) then -- -- 0x38 - DECODER_CNT_BLACK_LINES slv_reg14_r1 <= host_decoder_cnt_black_lines; -- -- 0x3C - DECODER_CNT_IMAGE_LINES slv_reg15_r1 <= host_decoder_cnt_image_lines; -- -- 0x40 - DECODER_CNT_BLACK_PIXELS slv_reg16_r1 <= host_decoder_cnt_black_pixels; -- -- 0x44 - DECODER_CNT_IMAGE_PIXELS slv_reg17_r1 <= host_decoder_cnt_image_pixels; -- -- 0x48 - DECODER_CNT_FRAMES slv_reg18_r1 <= host_decoder_cnt_frames; -- -- 0x4C - DECODER_CNT_WINDOWS slv_reg19_r1 <= host_decoder_cnt_windows; -- -- 0x50 - DECODER_CNT_CLOCKS slv_reg20_r1 <= host_decoder_cnt_clocks; -- -- 0x54 - DECODER_CNT_START_LINES slv_reg21_r1 <= host_decoder_cnt_start_lines; -- -- 0x58 - DECODER_CNT_END_LINES slv_reg22_r1 <= host_decoder_cnt_end_lines; end if; --if ( host_decoder_frame_start = '1' ) then -- 0x5C - SYNCGEN_DELAY -- [15: 0] DELAY host_syncgen_delay <= slv_reg23_w1(15 downto 0); -- 0x60 - SYNCGEN_HTIMING1 -- [15: 0] HACTIVE -- [31:16] HFPORCH -- 0x64 - SYNCGEN_HTIMING2 -- [15: 0] HSYNC -- [31:16] HBPORCH -- 0x68 - SYNCGEN_VTIMING1 -- [15: 0] VACTIVE -- [31:16] VFPORCH -- 0x6C - SYNCGEN_VTIMING2 -- [15: 0] VSYNC -- [31:16] VBPORCH host_syncgen_hactive <= slv_reg24_w1(15 downto 0); host_syncgen_hfporch <= slv_reg24_w1(31 downto 16); host_syncgen_hsync <= slv_reg25_w1(15 downto 0); host_syncgen_hbporch <= slv_reg25_w1(31 downto 16); host_syncgen_vactive <= slv_reg26_w1(15 downto 0); host_syncgen_vfporch <= slv_reg26_w1(31 downto 16); host_syncgen_vsync <= slv_reg27_w1(15 downto 0); host_syncgen_vbporch <= slv_reg27_w1(31 downto 16); -- -- 0x70 - CRC_CONTROL[7:0] -- [0] CRC_RESET -- [1] CRC_INITVALUE host_crc_reset <= slv_reg28_w1(0); host_crc_initvalue <= slv_reg28_w1(1); -- -- 0x74 - CRC_STATUS slv_reg29_r1 <= host_crc_status; -- -- 0x78 - REMAPPER_CONTROL[7:0] -- [2:0] REMAPPER_WRITE_CFG -- [6:4] REMAPPER_MODE host_remapper_write_cfg <= slv_reg30_w1(2 downto 0); host_remapper_mode <= slv_reg30_w1(6 downto 4); -- 0x80 - FPN_PRNU_VALUES[ 31: 0] -- 0x84 - FPN_PRNU_VALUES[ 63: 32] -- 0x88 - FPN_PRNU_VALUES[ 95: 64] -- 0x8C - FPN_PRNU_VALUES[127: 96] -- 0x90 - FPN_PRNU_VALUES[159:128] -- 0x94 - FPN_PRNU_VALUES[191:160] -- 0x98 - FPN_PRNU_VALUES[223:192] -- 0x9C - FPN_PRNU_VALUES[255:224] host_fpn_prnu_values( 31 downto 0) <= slv_reg32_w1; host_fpn_prnu_values( 63 downto 32) <= slv_reg33_w1; host_fpn_prnu_values( 95 downto 64) <= slv_reg34_w1; host_fpn_prnu_values(127 downto 96) <= slv_reg35_w1; host_fpn_prnu_values(159 downto 128) <= slv_reg36_w1; host_fpn_prnu_values(191 downto 160) <= slv_reg37_w1; host_fpn_prnu_values(223 downto 192) <= slv_reg38_w1; host_fpn_prnu_values(255 downto 224) <= slv_reg39_w1; -- -- 0xC0 - DECODER_CNT_MONITOR0_HIGH slv_reg48_r1 <= host_decoder_cnt_monitor0high; -- -- 0xC4 - DECODER_CNT_MONITOR0_LOW slv_reg49_r1 <= host_decoder_cnt_monitor0low; -- -- 0xC8 - DECODER_CNT_MONITOR1_HIGH slv_reg50_r1 <= host_decoder_cnt_monitor1high; -- -- 0xCC - DECODER_CNT_MONITOR1_LOW slv_reg51_r1 <= host_decoder_cnt_monitor1low; -- -- 0xDC - TRIGGEN_EXT_DEBOUNCE host_triggen_ext_debounce <= slv_reg55_w1; -- -- 0xE0 - TRIGGEN_CONTROL -- [ 2: 0] TRIGGEN_ENABLE -- [ 6: 4] TRIGGEN_SYNC2READOUT -- [ 8] TRIGGEN_READOUTTRIGGER -- [ 16] TRIGGEN_EXT_POLARITY -- [ 24] TRIGGEN_CNT_UPDATE -- [30:28] TRIGGEN_GEN_POLARITY host_triggen_enable <= slv_reg56_w1(2 downto 0); host_triggen_sync2readout <= slv_reg56_w1(6 downto 4); host_triggen_readouttrigger <= slv_reg56_w1(8); host_triggen_ext_polarity <= slv_reg56_w1(16); host_triggen_cnt_update <= slv_reg56_w1(24); host_triggen_gen_polarity <= slv_reg56_w1(30 downto 28); -- -- 0xE4 - TRIGGEN_DEFAULT_FREQ host_triggen_default_freq <= slv_reg57_w1; -- if ( host_triggen_cnt_update = '1' ) then -- -- 0xE8 - TRIGGEN_TRIG0_HIGH host_triggen_cnt_trigger0high <= slv_reg58_w1; -- -- 0xEC - TRIGGEN_TRIG0_LOW host_triggen_cnt_trigger0low <= slv_reg59_w1; -- -- 0xF0 - TRIGGEN_TRIG1_HIGH host_triggen_cnt_trigger1high <= slv_reg60_w1; -- -- 0xF4 - TRIGGEN_TRIG1_LOW host_triggen_cnt_trigger1low <= slv_reg61_w1; -- -- 0xF8 - TRIGGEN_TRIG2_HIGH host_triggen_cnt_trigger2high <= slv_reg62_w1; -- -- 0xFC - TRIGGEN_TRIG2_LOW host_triggen_cnt_trigger2low <= slv_reg63_w1; -- end if; -- if ( host_triggen_cnt_update == '1' ) then end if; end if; end process host_iserdes_process; ------------------------------------------ -- VITA Receiver Core Logic ------------------------------------------ VITA_CORE_I : entity fmc_imageon_vita_receiver_v1_13_a.fmc_imageon_vita_core generic map ( C_XSVI_DATA_WIDTH => C_XSVI_DATA_WIDTH, C_XSVI_DIRECT_OUTPUT => C_XSVI_DIRECT_OUTPUT, C_XSVI_USE_SYNCGEN => C_XSVI_USE_SYNCGEN, C_FAMILY => C_FAMILY ) port map ( clk200 => clk200, clk => clk, clk4x => clk4x, reset => reset, oe => oe, -- HOST Interface - VITA host_vita_reset => host_vita_reset, -- HOST Interface - SPI host_spi_clk => host_spi_clk, host_spi_reset => host_spi_reset, host_spi_timing => host_spi_timing, host_spi_status_busy => host_spi_status_busy, host_spi_status_error => host_spi_status_error, host_spi_txfifo_clk => host_spi_txfifo_clk, host_spi_txfifo_wen => host_spi_txfifo_wen, host_spi_txfifo_din => host_spi_txfifo_din, host_spi_txfifo_full => host_spi_txfifo_full, host_spi_rxfifo_clk => host_spi_rxfifo_clk, host_spi_rxfifo_ren => host_spi_rxfifo_ren, host_spi_rxfifo_dout => host_spi_rxfifo_dout, host_spi_rxfifo_empty => host_spi_rxfifo_empty, -- HOST Interface - ISERDES host_iserdes_reset => host_iserdes_reset, host_iserdes_auto_align => host_iserdes_auto_align, host_iserdes_align_start => host_iserdes_align_start, host_iserdes_fifo_enable => host_iserdes_fifo_enable, host_iserdes_manual_tap => host_iserdes_manual_tap, host_iserdes_training => host_iserdes_training, host_iserdes_clk_ready => host_iserdes_clk_ready, host_iserdes_clk_status => host_iserdes_clk_status, host_iserdes_align_busy => host_iserdes_align_busy, host_iserdes_aligned => host_iserdes_aligned, -- HOST Interface - Sync Channel Decoder host_decoder_reset => host_decoder_reset, host_decoder_enable => host_decoder_enable, host_decoder_startoddeven => host_decoder_startoddeven, host_decoder_code_ls => host_decoder_code_ls, host_decoder_code_le => host_decoder_code_le, host_decoder_code_fs => host_decoder_code_fs, host_decoder_code_fe => host_decoder_code_fe, host_decoder_code_bl => host_decoder_code_bl, host_decoder_code_img => host_decoder_code_img, host_decoder_code_tr => host_decoder_code_tr, host_decoder_code_crc => host_decoder_code_crc, host_decoder_frame_start => host_decoder_frame_start, host_decoder_cnt_black_lines => host_decoder_cnt_black_lines, host_decoder_cnt_image_lines => host_decoder_cnt_image_lines, host_decoder_cnt_black_pixels => host_decoder_cnt_black_pixels, host_decoder_cnt_image_pixels => host_decoder_cnt_image_pixels, host_decoder_cnt_frames => host_decoder_cnt_frames, host_decoder_cnt_windows => host_decoder_cnt_windows, host_decoder_cnt_clocks => host_decoder_cnt_clocks, host_decoder_cnt_start_lines => host_decoder_cnt_start_lines, host_decoder_cnt_end_lines => host_decoder_cnt_end_lines, host_decoder_cnt_monitor0high => host_decoder_cnt_monitor0high, host_decoder_cnt_monitor0low => host_decoder_cnt_monitor0low, host_decoder_cnt_monitor1high => host_decoder_cnt_monitor1high, host_decoder_cnt_monitor1low => host_decoder_cnt_monitor1low, -- HOST Interface - CRC Checker host_crc_reset => host_crc_reset, host_crc_initvalue => host_crc_initvalue, host_crc_status => host_crc_status, -- HOST Interface - Data Channel Remapper host_remapper_write_cfg => host_remapper_write_cfg, host_remapper_mode => host_remapper_mode, -- HOST Interface - Trigger Generator host_triggen_enable => host_triggen_enable, host_triggen_sync2readout => host_triggen_sync2readout, host_triggen_readouttrigger => host_triggen_readouttrigger, host_triggen_default_freq => host_triggen_default_freq, host_triggen_cnt_trigger0high => host_triggen_cnt_trigger0high, host_triggen_cnt_trigger0low => host_triggen_cnt_trigger0low, host_triggen_cnt_trigger1high => host_triggen_cnt_trigger1high, host_triggen_cnt_trigger1low => host_triggen_cnt_trigger1low, host_triggen_cnt_trigger2high => host_triggen_cnt_trigger2high, host_triggen_cnt_trigger2low => host_triggen_cnt_trigger2low, host_triggen_ext_debounce => host_triggen_ext_debounce, host_triggen_ext_polarity => host_triggen_ext_polarity, host_triggen_gen_polarity => host_triggen_gen_polarity, -- HOST Interface - FPN/PRNU Correction host_fpn_prnu_values => host_fpn_prnu_values, -- HOST Interface - Sync Generator host_syncgen_delay => host_syncgen_delay, host_syncgen_hactive => host_syncgen_hactive, host_syncgen_hfporch => host_syncgen_hfporch, host_syncgen_hsync => host_syncgen_hsync, host_syncgen_hbporch => host_syncgen_hbporch, host_syncgen_vactive => host_syncgen_vactive, host_syncgen_vfporch => host_syncgen_vfporch, host_syncgen_vsync => host_syncgen_vsync, host_syncgen_vbporch => host_syncgen_vbporch, -- I/O pins io_vita_clk_pll => io_vita_clk_pll, io_vita_reset_n => io_vita_reset_n, io_vita_spi_sclk => io_vita_spi_sclk, io_vita_spi_ssel_n => io_vita_spi_ssel_n, io_vita_spi_mosi => io_vita_spi_mosi, io_vita_spi_miso => io_vita_spi_miso, io_vita_trigger => io_vita_trigger, io_vita_monitor => io_vita_monitor, io_vita_clk_out_p => io_vita_clk_out_p, io_vita_clk_out_n => io_vita_clk_out_n, io_vita_sync_p => io_vita_sync_p, io_vita_sync_n => io_vita_sync_n, io_vita_data_p => io_vita_data_p, io_vita_data_n => io_vita_data_n, -- Trigger Port trigger1 => trigger1, -- Frame Sync Port fsync => fsync, -- XSVI Port xsvi_vsync_o => xsvi_vsync_o, xsvi_hsync_o => xsvi_hsync_o, xsvi_vblank_o => xsvi_vblank_o, xsvi_hblank_o => xsvi_hblank_o, xsvi_active_video_o => xsvi_active_video_o, xsvi_video_data_o => xsvi_video_data_o, -- Debug Port debug_spi_o => debug_spi_o, debug_iserdes_o => debug_iserdes_o, debug_decoder_o => debug_decoder_o, debug_crc_o => debug_crc_o, debug_triggen_o => debug_triggen_o, debug_video_o => debug_video_o ); -- -- Debug Port -- Can be used to connect to ChipScope for debugging. -- Having a port makes these signals accessible for debug via EDK. -- debug_host_l : process (Bus2IP_Clk) begin if Rising_Edge(Bus2IP_Clk) then debug_host_o( 31 downto 0) <= Bus2IP_Addr; debug_host_o( 63 downto 32) <= Bus2IP_Data; debug_host_o( 95 downto 64) <= slv_ip2bus_data; debug_host_o(159 downto 96) <= Bus2IP_WrCE; debug_host_o(223 downto 160) <= Bus2IP_RdCE; debug_host_o( 224) <= Bus2IP_CS(0); debug_host_o( 225) <= Bus2IP_RNW; debug_host_o(229 downto 226) <= Bus2IP_BE; debug_host_o( 230) <= slv_write_ack; debug_host_o( 231) <= slv_read_ack; end if; end process; end IMP;
-- EMACS settings: -- tab-width: 2; indent-tabs-mode: t -- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Martin Zabel -- -- Module: Clock Generator for Memory Test on Spartan-3E Starter Kit -- -- Description: -- ------------------------------------ -- DCM configuration for module 'memtest_s3esk'. -- -- The DCMs dcm_mem* have either unstable input clocks upon configuration and/or -- external feedback, and thus must be reset accordingly. So we do not use -- the STARTUP_WAIT feature at all. -- -- After startup the clocks are unstable. Thus, the logic -- clocked by clk_* must be hold in reset until rst_* is deasserted. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ ------------------------------------------------------------------------------- -- Naming Conventions: -- (Based on: Keating and Bricaud: "Reuse Methodology Manual") -- -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: all UPPERCASE -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- output of a register: "_r" -- asynchronous signal: "_a" -- pipelined or register delay signals: "_p#" -- data before being registered into register with the same name: "_nxt" -- clock enable signals: "_ce" -- internal version of output port: "_i" -- tristate internal signal "_z" ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.ALL; entity memtest_s3esk_clockgen is port ( clk_in : in std_logic; sd_ck_fb : in std_logic; user_rst : in std_logic; clk_sys : out std_logic; clk_mem : out std_logic; clk_mem_n : out std_logic; clk_mem90 : out std_logic; clk_mem90_n : out std_logic; clk_memfb90 : out std_logic; clk_memfb90_n : out std_logic; rst_sys : out std_logic; rst_mem : out std_logic; rst_mem90 : out std_logic; rst_mem180 : out std_logic; rst_mem270 : out std_logic; rst_memfb90 : out std_logic; rst_memfb270 : out std_logic; locked : out std_logic); end memtest_s3esk_clockgen; library unisim; use unisim.VComponents.all; architecture rtl of memtest_s3esk_clockgen is -- input buffer signal clk_in_bufo : std_logic; signal sd_ck_fb_bufo : std_logic; -- clock buffer inputs signal clk_sys_bufi : std_logic; signal clk_dv_bufi : std_logic; signal clk_mem_bufi : std_logic; signal clk_mem90_bufi : std_logic; signal clk_memfb90_bufi : std_logic; signal clk_memfb90_n_bufi : std_logic; -- global clocks (internal signals) signal clk_sys_i : std_logic; signal clk_mem_i : std_logic; signal clk_mem_n_i : std_logic; signal clk_mem90_i : std_logic; signal clk_mem90_n_i : std_logic; signal clk_memfb90_i : std_logic; signal clk_memfb90_n_i : std_logic; -- dcm reset signal dcm_mem_rst : std_logic; signal dcm_memfb_rst : std_logic; -- locked signals signal dcm_sys_locked : std_logic; signal dcm_mem_locked : std_logic; signal dcm_mem90_locked : std_logic; signal dcm_memfb_locked : std_logic; -- reset synchronizers for clk_sys, clk_mem and clk_memfb* signal rst_sys_r : std_logic_vector(1 downto 0); signal rst_mem_r : std_logic_vector(1 downto 0); signal rst_mem90_r : std_logic_vector(1 downto 0); signal rst_mem180_r : std_logic_vector(1 downto 0); signal rst_mem270_r : std_logic_vector(1 downto 0); signal rst_memfb90_r : std_logic_vector(1 downto 0); signal rst_memfb270_r : std_logic_vector(1 downto 0); -- internal version of output signals signal locked_i : std_logic; -- do reset signal do_rst : std_logic; begin ----------------------------------------------------------------------------- -- 0. Input Clock buffer and system clock. ----------------------------------------------------------------------------- clk_in_buf : IBUFG port map ( I => clk_in, O => clk_in_bufo); ----------------------------------------------------------------------------- -- 1. System clock. ----------------------------------------------------------------------------- dcm_sys : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.0, -- period of input clock (50 Mhz) DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, CLK_FEEDBACK => "1X", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "NONE", PHASE_SHIFT => 0, CLKDV_DIVIDE => 2.0, FACTORY_JF => X"C080") -- ? port map ( CLK0 => clk_sys_bufi, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => clk_dv_bufi, CLKFX => open, CLKFX180 => open, LOCKED => dcm_sys_locked, PSDONE => open, STATUS => open, CLKFB => clk_sys_i, CLKIN => clk_in_bufo, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => '0'); clk_sys_buf : BUFG port map ( I => clk_sys_bufi, O => clk_sys_i); clk_sys <= clk_sys_i; -- clk_sys is stable as soon as GWE (Global Write Enable) is asserted. -- See documentation in file header. ----------------------------------------------------------------------------- -- 2. Generate memory clocks. -- -- The reset logic for this DCM has to wait until clk_sys gets stable. -- The reset must be asserted for three valid CLKIN cycles or longer. -- -- IMPORTANT NOTE: -- Yes dcm_mem and dcm_mem90 might be merged, if doubled input clock is -- generated by dcm_sys and then clk0 and clk90 DCM outputs are used. But -- these requires a DCM input clock of 100 MHz, which is out of specification -- for Spartan-3E stepping 0. ----------------------------------------------------------------------------- dcm_mem_rst_gen : SRLC16E generic map ( INIT => x"FFFF") -- hold reset for 16 clock cycles port map ( clk => clk_sys_i, ce => dcm_sys_locked, -- wait until clk_sys is stable d => '0', -- finished a0 => '1', a1 => '1', a2 => '1', a3 => '1', q => open, q15 => dcm_mem_rst); dcm_mem : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.0, -- 50 MHz DLL_FREQUENCY_MODE => "LOW", -- no specification found in manual DUTY_CYCLE_CORRECTION => FALSE, -- already 50 % CLK_FEEDBACK => "2X", DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "NONE", PHASE_SHIFT => 0, FACTORY_JF => X"C080") -- ? port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => clk_mem_bufi, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm_mem_locked, PSDONE => open, STATUS => open, CLKFB => clk_mem_i, CLKIN => clk_sys_i, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => dcm_mem_rst); dcm_mem90 : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.0, -- 50 MHz DLL_FREQUENCY_MODE => "LOW", -- no specification found in manual DUTY_CYCLE_CORRECTION => FALSE, -- already 50 % CLK_FEEDBACK => "2X", DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 32, -- 90° @ CLK2x FACTORY_JF => X"C080") -- ? port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => clk_mem90_bufi, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm_mem90_locked, PSDONE => open, STATUS => open, CLKFB => clk_mem90_i, CLKIN => clk_sys_i, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => dcm_mem_rst); clk_mem_buf : BUFG port map ( I => clk_mem_bufi, O => clk_mem_i); clk_mem_n_i <= not clk_mem_i; clk_mem90_buf : BUFG port map ( I => clk_mem90_bufi, O => clk_mem90_i); clk_mem90_n_i <= not clk_mem90_i; clk_mem <= clk_mem_i; clk_mem_n <= clk_mem_n_i; clk_mem90 <= clk_mem90_i; clk_mem90_n <= clk_mem90_n_i; ----------------------------------------------------------------------------- -- 3. Synchronized read clock for DDR-SDRAM controller. -- -- The reset logic for this DCM has to wait until clk_mem gets stable. -- The reset must be asserted for three valid CLKIN cycles or longer. -- Due to the external feedback, the number of cycles should be greater. ----------------------------------------------------------------------------- dcm_memfb_rst_gen : SRLC16E generic map ( INIT => x"FFFF") -- hold reset for 16 clock cycles port map ( clk => clk_mem_i, ce => dcm_mem_locked, -- wait until clk_mem is stable d => '0', -- finished a0 => '1', a1 => '1', a2 => '1', a3 => '1', q => open, q15 => dcm_memfb_rst); sd_ck_fb_buf : IBUFG port map ( I => sd_ck_fb, O => sd_ck_fb_bufo); dcm_memfb : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => TRUE, CLKIN_PERIOD => 10.0, -- period of input clock (100 Mhz) DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => FALSE, -- already 50 % CLK_FEEDBACK => "2X", DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- no deskew CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 32+5, -- 90° +/- x @ CLK2X FACTORY_JF => X"C080") port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => clk_memfb90_bufi, CLK2X180 => clk_memfb90_n_bufi, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm_memfb_locked, PSDONE => open, STATUS => open, CLKFB => clk_memfb90_i, CLKIN => sd_ck_fb_bufo, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => dcm_memfb_rst); clk_memfb90_buf : BUFG port map ( I => clk_memfb90_bufi, O => clk_memfb90_i); clk_memfb90_n_buf : BUFG port map ( I => clk_memfb90_n_bufi, O => clk_memfb90_n_i); clk_memfb90 <= clk_memfb90_i; clk_memfb90_n <= clk_memfb90_n_i; ----------------------------------------------------------------------------- -- 4. Locked & Resets -- -- Coordinated Reset removal: -- - First, remove reset of clk_mem*, because it always waits for commands -- before it writes anything to the read FIFO. -- - Second, remove reset from clk_sys because it writes to the command FIFO -- as soon as possible. But at this time, the rst_rd from that FIFO must -- not be asserted, so that the write_addr is correctly transfered between -- the clock domains (gray-encoding is kept). ----------------------------------------------------------------------------- locked_i <= dcm_sys_locked and dcm_mem_locked and dcm_mem90_locked and dcm_memfb_locked; locked <= locked_i; do_rst <= (not locked_i) or user_rst; -- synchronize locked_i with clock domain clk_sys process (do_rst, clk_sys_i) begin -- process if do_rst = '1' then rst_sys_r <= (others => '1'); elsif rising_edge(clk_sys_i) then rst_sys_r(0) <= rst_mem_r(rst_mem_r'left); -- release as second rst_sys_r(rst_sys_r'left downto 1) <= rst_sys_r(rst_sys_r'left-1 downto 0); end if; end process; rst_sys <= rst_sys_r(rst_sys_r'left); -- synchronize locked_i with clock domain clk_mem process (do_rst, clk_mem_i) begin -- process if do_rst = '1' then rst_mem_r <= (others => '1'); elsif rising_edge(clk_mem_i) then rst_mem_r(0) <= '0'; rst_mem_r(rst_mem_r'left downto 1) <= rst_mem_r(rst_mem_r'left-1 downto 0); end if; end process; rst_mem <= rst_mem_r(rst_mem_r'left); -- synchronize locked_i with clock domain clk_mem90 process (do_rst, clk_mem90_i) begin -- process if do_rst = '1' then rst_mem90_r <= (others => '1'); elsif rising_edge(clk_mem90_i) then rst_mem90_r(0) <= '0'; rst_mem90_r(rst_mem90_r'left downto 1) <= rst_mem90_r(rst_mem90_r'left-1 downto 0); end if; end process; rst_mem90 <= rst_mem90_r(rst_mem90_r'left); -- synchronize locked_i with clock domain clk_mem_n process (do_rst, clk_mem_n_i) begin -- process if do_rst = '1' then rst_mem180_r <= (others => '1'); elsif falling_edge(clk_mem_n_i) then rst_mem180_r(0) <= '0'; rst_mem180_r(rst_mem180_r'left downto 1) <= rst_mem180_r(rst_mem180_r'left-1 downto 0); end if; end process; rst_mem180 <= rst_mem180_r(rst_mem180_r'left); -- synchronize locked_i with clock domain clk_mem90_n process (do_rst, clk_mem90_n_i) begin -- process if do_rst = '1' then rst_mem270_r <= (others => '1'); elsif falling_edge(clk_mem90_n_i) then rst_mem270_r(0) <= '0'; rst_mem270_r(rst_mem270_r'left downto 1) <= rst_mem270_r(rst_mem270_r'left-1 downto 0); end if; end process; rst_mem270 <= rst_mem270_r(rst_mem270_r'left); -- synchronize locked_i with clock domain clk_memfb90 process (do_rst, clk_memfb90_i) begin -- process if do_rst = '1' then rst_memfb90_r <= (others => '1'); elsif rising_edge(clk_memfb90_i) then rst_memfb90_r(0) <= '0'; rst_memfb90_r(rst_memfb90_r'left downto 1) <= rst_memfb90_r(rst_memfb90_r'left-1 downto 0); end if; end process; rst_memfb90 <= rst_memfb90_r(rst_memfb90_r'left); -- synchronize locked_i with clock domain clk_memfb90_n process (do_rst, clk_memfb90_n_i) begin -- process if do_rst = '1' then rst_memfb270_r <= (others => '1'); elsif rising_edge(clk_memfb90_n_i) then rst_memfb270_r(0) <= '0'; rst_memfb270_r(rst_memfb270_r'left downto 1) <= rst_memfb270_r(rst_memfb270_r'left-1 downto 0); end if; end process; rst_memfb270 <= rst_memfb270_r(rst_memfb270_r'left); end rtl;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity mul_383 is port ( result : out std_logic_vector(30 downto 0); in_a : in std_logic_vector(30 downto 0); in_b : in std_logic_vector(14 downto 0) ); end mul_383; architecture augh of mul_383 is signal tmp_res : signed(45 downto 0); begin -- The actual multiplication tmp_res <= signed(in_a) * signed(in_b); -- Set the output result <= std_logic_vector(tmp_res(30 downto 0)); end architecture;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity mul_383 is port ( result : out std_logic_vector(30 downto 0); in_a : in std_logic_vector(30 downto 0); in_b : in std_logic_vector(14 downto 0) ); end mul_383; architecture augh of mul_383 is signal tmp_res : signed(45 downto 0); begin -- The actual multiplication tmp_res <= signed(in_a) * signed(in_b); -- Set the output result <= std_logic_vector(tmp_res(30 downto 0)); end architecture;
-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.4 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Loop_loop_height_lbW_rom is generic( dwidth : integer := 8; awidth : integer := 8; mem_size : integer := 256 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of Loop_loop_height_lbW_rom is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); signal mem : mem_array := ( 0 => "00000000", 1 => "00000010", 2 => "00000100", 3 => "00000110", 4 => "00001000", 5 => "00001010", 6 => "00001100", 7 => "00001110", 8 => "00010000", 9 => "00010010", 10 => "00010100", 11 => "00010110", 12 => "00010111", 13 => "00011001", 14 => "00011011", 15 => "00011101", 16 => "00011111", 17 => "00100001", 18 => "00100011", 19 => "00100101", 20 => "00100110", 21 => "00101000", 22 => "00101010", 23 => "00101100", 24 => "00101110", 25 => "00110000", 26 => "00110001", 27 => "00110011", 28 => "00110101", 29 => "00110111", 30 => "00111000", 31 => "00111010", 32 => "00111100", 33 => "00111110", 34 => "00111111", 35 => "01000001", 36 => "01000011", 37 => "01000101", 38 => "01000110", 39 => "01001000", 40 => "01001010", 41 => "01001011", 42 => "01001101", 43 => "01001111", 44 => "01010000", 45 => "01010010", 46 => "01010100", 47 => "01010101", 48 => "01010111", 49 => "01011001", 50 => "01011010", 51 => "01011100", 52 => "01011101", 53 => "01011111", 54 => "01100001", 55 => "01100010", 56 => "01100100", 57 => "01100101", 58 => "01100111", 59 => "01101000", 60 => "01101010", 61 => "01101011", 62 => "01101101", 63 => "01101110", 64 => "01110000", 65 => "01110001", 66 => "01110011", 67 => "01110100", 68 => "01110110", 69 => "01110111", 70 => "01111001", 71 => "01111010", 72 => "01111100", 73 => "01111101", 74 => "01111111", 75 => "10000000", 76 => "10000001", 77 => "10000011", 78 => "10000100", 79 => "10000110", 80 => "10000111", 81 => "10001000", 82 => "10001010", 83 => "10001011", 84 => "10001100", 85 => "10001110", 86 => "10001111", 87 => "10010000", 88 => "10010010", 89 => "10010011", 90 => "10010100", 91 => "10010110", 92 => "10010111", 93 => "10011000", 94 => "10011001", 95 => "10011011", 96 => "10011100", 97 => "10011101", 98 => "10011110", 99 => "10100000", 100 => "10100001", 101 => "10100010", 102 => "10100011", 103 => "10100100", 104 => "10100110", 105 => "10100111", 106 => "10101000", 107 => "10101001", 108 => "10101010", 109 => "10101011", 110 => "10101101", 111 => "10101110", 112 => "10101111", 113 => "10110000", 114 => "10110001", 115 => "10110010", 116 => "10110011", 117 => "10110100", 118 => "10110101", 119 => "10110110", 120 => "10111000", 121 => "10111001", 122 => "10111010", 123 => "10111011", 124 => "10111100", 125 => "10111101", 126 => "10111110", 127 => "10111111", 128 => "11000000", 129 => "11000001", 130 => "11000010", 131 => "11000011", 132 => "11000100", 133 => "11000101", 134 => "11000110", 135 to 136=> "11000111", 137 => "11001000", 138 => "11001001", 139 => "11001010", 140 => "11001011", 141 => "11001100", 142 => "11001101", 143 => "11001110", 144 => "11001111", 145 to 146=> "11010000", 147 => "11010001", 148 => "11010010", 149 => "11010011", 150 => "11010100", 151 to 152=> "11010101", 153 => "11010110", 154 => "11010111", 155 => "11011000", 156 to 157=> "11011001", 158 => "11011010", 159 => "11011011", 160 to 161=> "11011100", 162 => "11011101", 163 => "11011110", 164 to 165=> "11011111", 166 => "11100000", 167 to 168=> "11100001", 169 => "11100010", 170 to 171=> "11100011", 172 => "11100100", 173 to 174=> "11100101", 175 => "11100110", 176 to 177=> "11100111", 178 to 179=> "11101000", 180 => "11101001", 181 to 182=> "11101010", 183 to 184=> "11101011", 185 to 186=> "11101100", 187 to 188=> "11101101", 189 to 190=> "11101110", 191 to 192=> "11101111", 193 to 194=> "11110000", 195 to 196=> "11110001", 197 to 198=> "11110010", 199 to 200=> "11110011", 201 to 203=> "11110100", 204 to 205=> "11110101", 206 to 208=> "11110110", 209 to 211=> "11110111", 212 to 214=> "11111000", 215 to 217=> "11111001", 218 to 221=> "11111010", 222 to 225=> "11111011", 226 to 229=> "11111100", 230 to 235=> "11111101", 236 to 243=> "11111110", 244 to 255=> "11111111" ); begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_rom_access: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then q0 <= mem(CONV_INTEGER(addr0_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity Loop_loop_height_lbW is generic ( DataWidth : INTEGER := 8; AddressRange : INTEGER := 256; AddressWidth : INTEGER := 8); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of Loop_loop_height_lbW is component Loop_loop_height_lbW_rom is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR); end component; begin Loop_loop_height_lbW_rom_U : component Loop_loop_height_lbW_rom port map ( clk => clk, addr0 => address0, ce0 => ce0, q0 => q0); end architecture;
package body package0 is function fn0 (param0 : bit_vector) return bit is begin -- function code end fn0;
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Tue Sep 19 00:29:48 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_2_sim_netlist.vhdl -- Design : zynq_design_1_processing_system7_0_2 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is port ( CAN0_PHY_TX : out STD_LOGIC; CAN0_PHY_RX : in STD_LOGIC; CAN1_PHY_TX : out STD_LOGIC; CAN1_PHY_RX : in STD_LOGIC; ENET0_GMII_TX_EN : out STD_LOGIC; ENET0_GMII_TX_ER : out STD_LOGIC; ENET0_MDIO_MDC : out STD_LOGIC; ENET0_MDIO_O : out STD_LOGIC; ENET0_MDIO_T : out STD_LOGIC; ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET0_GMII_COL : in STD_LOGIC; ENET0_GMII_CRS : in STD_LOGIC; ENET0_GMII_RX_CLK : in STD_LOGIC; ENET0_GMII_RX_DV : in STD_LOGIC; ENET0_GMII_RX_ER : in STD_LOGIC; ENET0_GMII_TX_CLK : in STD_LOGIC; ENET0_MDIO_I : in STD_LOGIC; ENET0_EXT_INTIN : in STD_LOGIC; ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_TX_EN : out STD_LOGIC; ENET1_GMII_TX_ER : out STD_LOGIC; ENET1_MDIO_MDC : out STD_LOGIC; ENET1_MDIO_O : out STD_LOGIC; ENET1_MDIO_T : out STD_LOGIC; ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET1_SOF_RX : out STD_LOGIC; ENET1_SOF_TX : out STD_LOGIC; ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_COL : in STD_LOGIC; ENET1_GMII_CRS : in STD_LOGIC; ENET1_GMII_RX_CLK : in STD_LOGIC; ENET1_GMII_RX_DV : in STD_LOGIC; ENET1_GMII_RX_ER : in STD_LOGIC; ENET1_GMII_TX_CLK : in STD_LOGIC; ENET1_MDIO_I : in STD_LOGIC; ENET1_EXT_INTIN : in STD_LOGIC; ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; I2C1_SDA_I : in STD_LOGIC; I2C1_SDA_O : out STD_LOGIC; I2C1_SDA_T : out STD_LOGIC; I2C1_SCL_I : in STD_LOGIC; I2C1_SCL_O : out STD_LOGIC; I2C1_SCL_T : out STD_LOGIC; PJTAG_TCK : in STD_LOGIC; PJTAG_TMS : in STD_LOGIC; PJTAG_TDI : in STD_LOGIC; PJTAG_TDO : out STD_LOGIC; SDIO0_CLK : out STD_LOGIC; SDIO0_CLK_FB : in STD_LOGIC; SDIO0_CMD_O : out STD_LOGIC; SDIO0_CMD_I : in STD_LOGIC; SDIO0_CMD_T : out STD_LOGIC; SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_LED : out STD_LOGIC; SDIO0_CDN : in STD_LOGIC; SDIO0_WP : in STD_LOGIC; SDIO0_BUSPOW : out STD_LOGIC; SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SDIO1_CLK : out STD_LOGIC; SDIO1_CLK_FB : in STD_LOGIC; SDIO1_CMD_O : out STD_LOGIC; SDIO1_CMD_I : in STD_LOGIC; SDIO1_CMD_T : out STD_LOGIC; SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_LED : out STD_LOGIC; SDIO1_CDN : in STD_LOGIC; SDIO1_WP : in STD_LOGIC; SDIO1_BUSPOW : out STD_LOGIC; SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SPI0_SCLK_I : in STD_LOGIC; SPI0_SCLK_O : out STD_LOGIC; SPI0_SCLK_T : out STD_LOGIC; SPI0_MOSI_I : in STD_LOGIC; SPI0_MOSI_O : out STD_LOGIC; SPI0_MOSI_T : out STD_LOGIC; SPI0_MISO_I : in STD_LOGIC; SPI0_MISO_O : out STD_LOGIC; SPI0_MISO_T : out STD_LOGIC; SPI0_SS_I : in STD_LOGIC; SPI0_SS_O : out STD_LOGIC; SPI0_SS1_O : out STD_LOGIC; SPI0_SS2_O : out STD_LOGIC; SPI0_SS_T : out STD_LOGIC; SPI1_SCLK_I : in STD_LOGIC; SPI1_SCLK_O : out STD_LOGIC; SPI1_SCLK_T : out STD_LOGIC; SPI1_MOSI_I : in STD_LOGIC; SPI1_MOSI_O : out STD_LOGIC; SPI1_MOSI_T : out STD_LOGIC; SPI1_MISO_I : in STD_LOGIC; SPI1_MISO_O : out STD_LOGIC; SPI1_MISO_T : out STD_LOGIC; SPI1_SS_I : in STD_LOGIC; SPI1_SS_O : out STD_LOGIC; SPI1_SS1_O : out STD_LOGIC; SPI1_SS2_O : out STD_LOGIC; SPI1_SS_T : out STD_LOGIC; UART0_DTRN : out STD_LOGIC; UART0_RTSN : out STD_LOGIC; UART0_TX : out STD_LOGIC; UART0_CTSN : in STD_LOGIC; UART0_DCDN : in STD_LOGIC; UART0_DSRN : in STD_LOGIC; UART0_RIN : in STD_LOGIC; UART0_RX : in STD_LOGIC; UART1_DTRN : out STD_LOGIC; UART1_RTSN : out STD_LOGIC; UART1_TX : out STD_LOGIC; UART1_CTSN : in STD_LOGIC; UART1_DCDN : in STD_LOGIC; UART1_DSRN : in STD_LOGIC; UART1_RIN : in STD_LOGIC; UART1_RX : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; TTC0_CLK0_IN : in STD_LOGIC; TTC0_CLK1_IN : in STD_LOGIC; TTC0_CLK2_IN : in STD_LOGIC; TTC1_WAVE0_OUT : out STD_LOGIC; TTC1_WAVE1_OUT : out STD_LOGIC; TTC1_WAVE2_OUT : out STD_LOGIC; TTC1_CLK0_IN : in STD_LOGIC; TTC1_CLK1_IN : in STD_LOGIC; TTC1_CLK2_IN : in STD_LOGIC; WDT_CLK_IN : in STD_LOGIC; WDT_RST_OUT : out STD_LOGIC; TRACE_CLK : in STD_LOGIC; TRACE_CTL : out STD_LOGIC; TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); TRACE_CLK_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB1_VBUS_PWRSELECT : out STD_LOGIC; USB1_VBUS_PWRFAULT : in STD_LOGIC; SRAM_INTIN : in STD_LOGIC; M_AXI_GP0_ARESETN : out STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARESETN : out STD_LOGIC; M_AXI_GP1_ARVALID : out STD_LOGIC; M_AXI_GP1_AWVALID : out STD_LOGIC; M_AXI_GP1_BREADY : out STD_LOGIC; M_AXI_GP1_RREADY : out STD_LOGIC; M_AXI_GP1_WLAST : out STD_LOGIC; M_AXI_GP1_WVALID : out STD_LOGIC; M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ACLK : in STD_LOGIC; M_AXI_GP1_ARREADY : in STD_LOGIC; M_AXI_GP1_AWREADY : in STD_LOGIC; M_AXI_GP1_BVALID : in STD_LOGIC; M_AXI_GP1_RLAST : in STD_LOGIC; M_AXI_GP1_RVALID : in STD_LOGIC; M_AXI_GP1_WREADY : in STD_LOGIC; M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARESETN : out STD_LOGIC; S_AXI_GP0_ARREADY : out STD_LOGIC; S_AXI_GP0_AWREADY : out STD_LOGIC; S_AXI_GP0_BVALID : out STD_LOGIC; S_AXI_GP0_RLAST : out STD_LOGIC; S_AXI_GP0_RVALID : out STD_LOGIC; S_AXI_GP0_WREADY : out STD_LOGIC; S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_ACLK : in STD_LOGIC; S_AXI_GP0_ARVALID : in STD_LOGIC; S_AXI_GP0_AWVALID : in STD_LOGIC; S_AXI_GP0_BREADY : in STD_LOGIC; S_AXI_GP0_RREADY : in STD_LOGIC; S_AXI_GP0_WLAST : in STD_LOGIC; S_AXI_GP0_WVALID : in STD_LOGIC; S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ARESETN : out STD_LOGIC; S_AXI_GP1_ARREADY : out STD_LOGIC; S_AXI_GP1_AWREADY : out STD_LOGIC; S_AXI_GP1_BVALID : out STD_LOGIC; S_AXI_GP1_RLAST : out STD_LOGIC; S_AXI_GP1_RVALID : out STD_LOGIC; S_AXI_GP1_WREADY : out STD_LOGIC; S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ACLK : in STD_LOGIC; S_AXI_GP1_ARVALID : in STD_LOGIC; S_AXI_GP1_AWVALID : in STD_LOGIC; S_AXI_GP1_BREADY : in STD_LOGIC; S_AXI_GP1_RREADY : in STD_LOGIC; S_AXI_GP1_WLAST : in STD_LOGIC; S_AXI_GP1_WVALID : in STD_LOGIC; S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_ACP_ARESETN : out STD_LOGIC; S_AXI_ACP_ARREADY : out STD_LOGIC; S_AXI_ACP_AWREADY : out STD_LOGIC; S_AXI_ACP_BVALID : out STD_LOGIC; S_AXI_ACP_RLAST : out STD_LOGIC; S_AXI_ACP_RVALID : out STD_LOGIC; S_AXI_ACP_WREADY : out STD_LOGIC; S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_ACLK : in STD_LOGIC; S_AXI_ACP_ARVALID : in STD_LOGIC; S_AXI_ACP_AWVALID : in STD_LOGIC; S_AXI_ACP_BREADY : in STD_LOGIC; S_AXI_ACP_RREADY : in STD_LOGIC; S_AXI_ACP_WLAST : in STD_LOGIC; S_AXI_ACP_WVALID : in STD_LOGIC; S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_ARESETN : out STD_LOGIC; S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_ARESETN : out STD_LOGIC; S_AXI_HP1_ARREADY : out STD_LOGIC; S_AXI_HP1_AWREADY : out STD_LOGIC; S_AXI_HP1_BVALID : out STD_LOGIC; S_AXI_HP1_RLAST : out STD_LOGIC; S_AXI_HP1_RVALID : out STD_LOGIC; S_AXI_HP1_WREADY : out STD_LOGIC; S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_ACLK : in STD_LOGIC; S_AXI_HP1_ARVALID : in STD_LOGIC; S_AXI_HP1_AWVALID : in STD_LOGIC; S_AXI_HP1_BREADY : in STD_LOGIC; S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_RREADY : in STD_LOGIC; S_AXI_HP1_WLAST : in STD_LOGIC; S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_WVALID : in STD_LOGIC; S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_ARESETN : out STD_LOGIC; S_AXI_HP2_ARREADY : out STD_LOGIC; S_AXI_HP2_AWREADY : out STD_LOGIC; S_AXI_HP2_BVALID : out STD_LOGIC; S_AXI_HP2_RLAST : out STD_LOGIC; S_AXI_HP2_RVALID : out STD_LOGIC; S_AXI_HP2_WREADY : out STD_LOGIC; S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_ACLK : in STD_LOGIC; S_AXI_HP2_ARVALID : in STD_LOGIC; S_AXI_HP2_AWVALID : in STD_LOGIC; S_AXI_HP2_BREADY : in STD_LOGIC; S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_RREADY : in STD_LOGIC; S_AXI_HP2_WLAST : in STD_LOGIC; S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_WVALID : in STD_LOGIC; S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_ARESETN : out STD_LOGIC; S_AXI_HP3_ARREADY : out STD_LOGIC; S_AXI_HP3_AWREADY : out STD_LOGIC; S_AXI_HP3_BVALID : out STD_LOGIC; S_AXI_HP3_RLAST : out STD_LOGIC; S_AXI_HP3_RVALID : out STD_LOGIC; S_AXI_HP3_WREADY : out STD_LOGIC; S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_ACLK : in STD_LOGIC; S_AXI_HP3_ARVALID : in STD_LOGIC; S_AXI_HP3_AWVALID : in STD_LOGIC; S_AXI_HP3_BREADY : in STD_LOGIC; S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_RREADY : in STD_LOGIC; S_AXI_HP3_WLAST : in STD_LOGIC; S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_WVALID : in STD_LOGIC; S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); IRQ_P2F_DMAC_ABORT : out STD_LOGIC; IRQ_P2F_DMAC0 : out STD_LOGIC; IRQ_P2F_DMAC1 : out STD_LOGIC; IRQ_P2F_DMAC2 : out STD_LOGIC; IRQ_P2F_DMAC3 : out STD_LOGIC; IRQ_P2F_DMAC4 : out STD_LOGIC; IRQ_P2F_DMAC5 : out STD_LOGIC; IRQ_P2F_DMAC6 : out STD_LOGIC; IRQ_P2F_DMAC7 : out STD_LOGIC; IRQ_P2F_SMC : out STD_LOGIC; IRQ_P2F_QSPI : out STD_LOGIC; IRQ_P2F_CTI : out STD_LOGIC; IRQ_P2F_GPIO : out STD_LOGIC; IRQ_P2F_USB0 : out STD_LOGIC; IRQ_P2F_ENET0 : out STD_LOGIC; IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; IRQ_P2F_SDIO0 : out STD_LOGIC; IRQ_P2F_I2C0 : out STD_LOGIC; IRQ_P2F_SPI0 : out STD_LOGIC; IRQ_P2F_UART0 : out STD_LOGIC; IRQ_P2F_CAN0 : out STD_LOGIC; IRQ_P2F_USB1 : out STD_LOGIC; IRQ_P2F_ENET1 : out STD_LOGIC; IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; IRQ_P2F_SDIO1 : out STD_LOGIC; IRQ_P2F_I2C1 : out STD_LOGIC; IRQ_P2F_SPI1 : out STD_LOGIC; IRQ_P2F_UART1 : out STD_LOGIC; IRQ_P2F_CAN1 : out STD_LOGIC; IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); Core0_nFIQ : in STD_LOGIC; Core0_nIRQ : in STD_LOGIC; Core1_nFIQ : in STD_LOGIC; Core1_nIRQ : in STD_LOGIC; DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA0_DAVALID : out STD_LOGIC; DMA0_DRREADY : out STD_LOGIC; DMA0_RSTN : out STD_LOGIC; DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DAVALID : out STD_LOGIC; DMA1_DRREADY : out STD_LOGIC; DMA1_RSTN : out STD_LOGIC; DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DAVALID : out STD_LOGIC; DMA2_DRREADY : out STD_LOGIC; DMA2_RSTN : out STD_LOGIC; DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DAVALID : out STD_LOGIC; DMA3_DRREADY : out STD_LOGIC; DMA3_RSTN : out STD_LOGIC; DMA0_ACLK : in STD_LOGIC; DMA0_DAREADY : in STD_LOGIC; DMA0_DRLAST : in STD_LOGIC; DMA0_DRVALID : in STD_LOGIC; DMA1_ACLK : in STD_LOGIC; DMA1_DAREADY : in STD_LOGIC; DMA1_DRLAST : in STD_LOGIC; DMA1_DRVALID : in STD_LOGIC; DMA2_ACLK : in STD_LOGIC; DMA2_DAREADY : in STD_LOGIC; DMA2_DRLAST : in STD_LOGIC; DMA2_DRVALID : in STD_LOGIC; DMA3_ACLK : in STD_LOGIC; DMA3_DAREADY : in STD_LOGIC; DMA3_DRLAST : in STD_LOGIC; DMA3_DRVALID : in STD_LOGIC; DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); FCLK_CLK3 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK0 : out STD_LOGIC; FCLK_CLKTRIG3_N : in STD_LOGIC; FCLK_CLKTRIG2_N : in STD_LOGIC; FCLK_CLKTRIG1_N : in STD_LOGIC; FCLK_CLKTRIG0_N : in STD_LOGIC; FCLK_RESET3_N : out STD_LOGIC; FCLK_RESET2_N : out STD_LOGIC; FCLK_RESET1_N : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMD_TRACEIN_VALID : in STD_LOGIC; FTMD_TRACEIN_CLK : in STD_LOGIC; FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); FTMT_F2P_TRIG_0 : in STD_LOGIC; FTMT_F2P_TRIGACK_0 : out STD_LOGIC; FTMT_F2P_TRIG_1 : in STD_LOGIC; FTMT_F2P_TRIGACK_1 : out STD_LOGIC; FTMT_F2P_TRIG_2 : in STD_LOGIC; FTMT_F2P_TRIGACK_2 : out STD_LOGIC; FTMT_F2P_TRIG_3 : in STD_LOGIC; FTMT_F2P_TRIGACK_3 : out STD_LOGIC; FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMT_P2F_TRIGACK_0 : in STD_LOGIC; FTMT_P2F_TRIG_0 : out STD_LOGIC; FTMT_P2F_TRIGACK_1 : in STD_LOGIC; FTMT_P2F_TRIG_1 : out STD_LOGIC; FTMT_P2F_TRIGACK_2 : in STD_LOGIC; FTMT_P2F_TRIG_2 : out STD_LOGIC; FTMT_P2F_TRIGACK_3 : in STD_LOGIC; FTMT_P2F_TRIG_3 : out STD_LOGIC; FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); FPGA_IDLE_N : in STD_LOGIC; EVENT_EVENTO : out STD_LOGIC; EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_EVENTI : in STD_LOGIC; DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zynq_design_1_processing_system7_0_2.hwdef"; attribute POWER : string; attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC; signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 ); signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC; signal I2C1_SDA_T_n : STD_LOGIC; signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal SDIO0_CMD_T_n : STD_LOGIC; signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SDIO1_CMD_T_n : STD_LOGIC; signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SPI0_MISO_T_n : STD_LOGIC; signal SPI0_MOSI_T_n : STD_LOGIC; signal SPI0_SCLK_T_n : STD_LOGIC; signal SPI0_SS_T_n : STD_LOGIC; signal SPI1_MISO_T_n : STD_LOGIC; signal SPI1_MOSI_T_n : STD_LOGIC; signal SPI1_SCLK_T_n : STD_LOGIC; signal SPI1_SS_T_n : STD_LOGIC; signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true"; signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true"; signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true"; signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true"; signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true"; signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true"; signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true"; signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true"; signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true"; signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true"; signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true"; signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true"; signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true"; signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true"; signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true"; signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true"; signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal buffered_DDR_CAS_n : STD_LOGIC; signal buffered_DDR_CKE : STD_LOGIC; signal buffered_DDR_CS_n : STD_LOGIC; signal buffered_DDR_Clk : STD_LOGIC; signal buffered_DDR_Clk_n : STD_LOGIC; signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DRSTB : STD_LOGIC; signal buffered_DDR_ODT : STD_LOGIC; signal buffered_DDR_RAS_n : STD_LOGIC; signal buffered_DDR_VRN : STD_LOGIC; signal buffered_DDR_VRP : STD_LOGIC; signal buffered_DDR_WEB : STD_LOGIC; signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal buffered_PS_CLK : STD_LOGIC; signal buffered_PS_PORB : STD_LOGIC; signal buffered_PS_SRSTB : STD_LOGIC; signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); attribute BOX_TYPE : string; attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; begin ENET0_GMII_TXD(7) <= \<const0>\; ENET0_GMII_TXD(6) <= \<const0>\; ENET0_GMII_TXD(5) <= \<const0>\; ENET0_GMII_TXD(4) <= \<const0>\; ENET0_GMII_TXD(3) <= \<const0>\; ENET0_GMII_TXD(2) <= \<const0>\; ENET0_GMII_TXD(1) <= \<const0>\; ENET0_GMII_TXD(0) <= \<const0>\; ENET0_GMII_TX_EN <= \<const0>\; ENET0_GMII_TX_ER <= \<const0>\; ENET1_GMII_TXD(7) <= \<const0>\; ENET1_GMII_TXD(6) <= \<const0>\; ENET1_GMII_TXD(5) <= \<const0>\; ENET1_GMII_TXD(4) <= \<const0>\; ENET1_GMII_TXD(3) <= \<const0>\; ENET1_GMII_TXD(2) <= \<const0>\; ENET1_GMII_TXD(1) <= \<const0>\; ENET1_GMII_TXD(0) <= \<const0>\; ENET1_GMII_TX_EN <= \<const0>\; ENET1_GMII_TX_ER <= \<const0>\; M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); M_AXI_GP0_ARCACHE(1) <= \<const1>\; M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); M_AXI_GP0_ARSIZE(2) <= \<const0>\; M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); M_AXI_GP0_AWCACHE(1) <= \<const1>\; M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); M_AXI_GP0_AWSIZE(2) <= \<const0>\; M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2); M_AXI_GP1_ARCACHE(1) <= \<const1>\; M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0); M_AXI_GP1_ARSIZE(2) <= \<const0>\; M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0); M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2); M_AXI_GP1_AWCACHE(1) <= \<const1>\; M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0); M_AXI_GP1_AWSIZE(2) <= \<const0>\; M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0); PJTAG_TDO <= \<const0>\; TRACE_CLK_OUT <= \<const0>\; TRACE_CTL <= \TRACE_CTL_PIPE[0]\; TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0); DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CAS_n, PAD => DDR_CAS_n ); DDR_CKE_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CKE, PAD => DDR_CKE ); DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CS_n, PAD => DDR_CS_n ); DDR_Clk_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk, PAD => DDR_Clk ); DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk_n, PAD => DDR_Clk_n ); DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DRSTB, PAD => DDR_DRSTB ); DDR_ODT_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_ODT, PAD => DDR_ODT ); DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_RAS_n, PAD => DDR_RAS_n ); DDR_VRN_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRN, PAD => DDR_VRN ); DDR_VRP_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRP, PAD => DDR_VRP ); DDR_WEB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_WEB, PAD => DDR_WEB ); ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET0_MDIO_T_n, O => ENET0_MDIO_T ); ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET1_MDIO_T_n, O => ENET1_MDIO_T ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(0), O => GPIO_T(0) ); \GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(10), O => GPIO_T(10) ); \GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(11), O => GPIO_T(11) ); \GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(12), O => GPIO_T(12) ); \GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(13), O => GPIO_T(13) ); \GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(14), O => GPIO_T(14) ); \GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(15), O => GPIO_T(15) ); \GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(16), O => GPIO_T(16) ); \GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(17), O => GPIO_T(17) ); \GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(18), O => GPIO_T(18) ); \GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(19), O => GPIO_T(19) ); \GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(1), O => GPIO_T(1) ); \GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(20), O => GPIO_T(20) ); \GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(21), O => GPIO_T(21) ); \GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(22), O => GPIO_T(22) ); \GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(23), O => GPIO_T(23) ); \GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(24), O => GPIO_T(24) ); \GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(25), O => GPIO_T(25) ); \GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(26), O => GPIO_T(26) ); \GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(27), O => GPIO_T(27) ); \GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(28), O => GPIO_T(28) ); \GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(29), O => GPIO_T(29) ); \GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(2), O => GPIO_T(2) ); \GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(30), O => GPIO_T(30) ); \GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(31), O => GPIO_T(31) ); \GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(32), O => GPIO_T(32) ); \GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(33), O => GPIO_T(33) ); \GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(34), O => GPIO_T(34) ); \GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(35), O => GPIO_T(35) ); \GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(36), O => GPIO_T(36) ); \GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(37), O => GPIO_T(37) ); \GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(38), O => GPIO_T(38) ); \GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(39), O => GPIO_T(39) ); \GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(3), O => GPIO_T(3) ); \GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(40), O => GPIO_T(40) ); \GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(41), O => GPIO_T(41) ); \GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(42), O => GPIO_T(42) ); \GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(43), O => GPIO_T(43) ); \GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(44), O => GPIO_T(44) ); \GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(45), O => GPIO_T(45) ); \GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(46), O => GPIO_T(46) ); \GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(47), O => GPIO_T(47) ); \GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(48), O => GPIO_T(48) ); \GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(49), O => GPIO_T(49) ); \GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(4), O => GPIO_T(4) ); \GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(50), O => GPIO_T(50) ); \GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(51), O => GPIO_T(51) ); \GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(52), O => GPIO_T(52) ); \GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(53), O => GPIO_T(53) ); \GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(54), O => GPIO_T(54) ); \GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(55), O => GPIO_T(55) ); \GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(56), O => GPIO_T(56) ); \GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(57), O => GPIO_T(57) ); \GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(58), O => GPIO_T(58) ); \GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(59), O => GPIO_T(59) ); \GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(5), O => GPIO_T(5) ); \GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(60), O => GPIO_T(60) ); \GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(61), O => GPIO_T(61) ); \GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(62), O => GPIO_T(62) ); \GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(63), O => GPIO_T(63) ); \GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(6), O => GPIO_T(6) ); \GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(7), O => GPIO_T(7) ); \GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(8), O => GPIO_T(8) ); \GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(9), O => GPIO_T(9) ); I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SCL_T_n, O => I2C0_SCL_T ); I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SDA_T_n, O => I2C0_SDA_T ); I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SCL_T_n, O => I2C1_SCL_T ); I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SDA_T_n, O => I2C1_SDA_T ); PS7_i: unisim.vcomponents.PS7 port map ( DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), DDRARB(3 downto 0) => DDR_ARB(3 downto 0), DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), DDRCASB => buffered_DDR_CAS_n, DDRCKE => buffered_DDR_CKE, DDRCKN => buffered_DDR_Clk_n, DDRCKP => buffered_DDR_Clk, DDRCSB => buffered_DDR_CS_n, DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), DDRDRSTB => buffered_DDR_DRSTB, DDRODT => buffered_DDR_ODT, DDRRASB => buffered_DDR_RAS_n, DDRVRN => buffered_DDR_VRN, DDRVRP => buffered_DDR_VRP, DDRWEB => buffered_DDR_WEB, DMA0ACLK => DMA0_ACLK, DMA0DAREADY => DMA0_DAREADY, DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0), DMA0DAVALID => DMA0_DAVALID, DMA0DRLAST => DMA0_DRLAST, DMA0DRREADY => DMA0_DRREADY, DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0), DMA0DRVALID => DMA0_DRVALID, DMA0RSTN => DMA0_RSTN, DMA1ACLK => DMA1_ACLK, DMA1DAREADY => DMA1_DAREADY, DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0), DMA1DAVALID => DMA1_DAVALID, DMA1DRLAST => DMA1_DRLAST, DMA1DRREADY => DMA1_DRREADY, DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0), DMA1DRVALID => DMA1_DRVALID, DMA1RSTN => DMA1_RSTN, DMA2ACLK => DMA2_ACLK, DMA2DAREADY => DMA2_DAREADY, DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0), DMA2DAVALID => DMA2_DAVALID, DMA2DRLAST => DMA2_DRLAST, DMA2DRREADY => DMA2_DRREADY, DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0), DMA2DRVALID => DMA2_DRVALID, DMA2RSTN => DMA2_RSTN, DMA3ACLK => DMA3_ACLK, DMA3DAREADY => DMA3_DAREADY, DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0), DMA3DAVALID => DMA3_DAVALID, DMA3DRLAST => DMA3_DRLAST, DMA3DRREADY => DMA3_DRREADY, DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0), DMA3DRVALID => DMA3_DRVALID, DMA3RSTN => DMA3_RSTN, EMIOCAN0PHYRX => CAN0_PHY_RX, EMIOCAN0PHYTX => CAN0_PHY_TX, EMIOCAN1PHYRX => CAN1_PHY_RX, EMIOCAN1PHYTX => CAN1_PHY_TX, EMIOENET0EXTINTIN => ENET0_EXT_INTIN, EMIOENET0GMIICOL => '0', EMIOENET0GMIICRS => '0', EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK, EMIOENET0GMIIRXD(7 downto 0) => B"00000000", EMIOENET0GMIIRXDV => '0', EMIOENET0GMIIRXER => '0', EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK, EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, EMIOENET0MDIOI => ENET0_MDIO_I, EMIOENET0MDIOMDC => ENET0_MDIO_MDC, EMIOENET0MDIOO => ENET0_MDIO_O, EMIOENET0MDIOTN => ENET0_MDIO_T_n, EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX, EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX, EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX, EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX, EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX, EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX, EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX, EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX, EMIOENET0SOFRX => ENET0_SOF_RX, EMIOENET0SOFTX => ENET0_SOF_TX, EMIOENET1EXTINTIN => ENET1_EXT_INTIN, EMIOENET1GMIICOL => '0', EMIOENET1GMIICRS => '0', EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK, EMIOENET1GMIIRXD(7 downto 0) => B"00000000", EMIOENET1GMIIRXDV => '0', EMIOENET1GMIIRXER => '0', EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK, EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, EMIOENET1MDIOI => ENET1_MDIO_I, EMIOENET1MDIOMDC => ENET1_MDIO_MDC, EMIOENET1MDIOO => ENET1_MDIO_O, EMIOENET1MDIOTN => ENET1_MDIO_T_n, EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX, EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX, EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX, EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX, EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX, EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX, EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX, EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX, EMIOENET1SOFRX => ENET1_SOF_RX, EMIOENET1SOFTX => ENET1_SOF_TX, EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0), EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0), EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0), EMIOI2C0SCLI => I2C0_SCL_I, EMIOI2C0SCLO => I2C0_SCL_O, EMIOI2C0SCLTN => I2C0_SCL_T_n, EMIOI2C0SDAI => I2C0_SDA_I, EMIOI2C0SDAO => I2C0_SDA_O, EMIOI2C0SDATN => I2C0_SDA_T_n, EMIOI2C1SCLI => I2C1_SCL_I, EMIOI2C1SCLO => I2C1_SCL_O, EMIOI2C1SCLTN => I2C1_SCL_T_n, EMIOI2C1SDAI => I2C1_SDA_I, EMIOI2C1SDAO => I2C1_SDA_O, EMIOI2C1SDATN => I2C1_SDA_T_n, EMIOPJTAGTCK => PJTAG_TCK, EMIOPJTAGTDI => PJTAG_TDI, EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, EMIOPJTAGTMS => PJTAG_TMS, EMIOSDIO0BUSPOW => SDIO0_BUSPOW, EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0), EMIOSDIO0CDN => SDIO0_CDN, EMIOSDIO0CLK => SDIO0_CLK, EMIOSDIO0CLKFB => SDIO0_CLK_FB, EMIOSDIO0CMDI => SDIO0_CMD_I, EMIOSDIO0CMDO => SDIO0_CMD_O, EMIOSDIO0CMDTN => SDIO0_CMD_T_n, EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0), EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0), EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0), EMIOSDIO0LED => SDIO0_LED, EMIOSDIO0WP => SDIO0_WP, EMIOSDIO1BUSPOW => SDIO1_BUSPOW, EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0), EMIOSDIO1CDN => SDIO1_CDN, EMIOSDIO1CLK => SDIO1_CLK, EMIOSDIO1CLKFB => SDIO1_CLK_FB, EMIOSDIO1CMDI => SDIO1_CMD_I, EMIOSDIO1CMDO => SDIO1_CMD_O, EMIOSDIO1CMDTN => SDIO1_CMD_T_n, EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0), EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0), EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0), EMIOSDIO1LED => SDIO1_LED, EMIOSDIO1WP => SDIO1_WP, EMIOSPI0MI => SPI0_MISO_I, EMIOSPI0MO => SPI0_MOSI_O, EMIOSPI0MOTN => SPI0_MOSI_T_n, EMIOSPI0SCLKI => SPI0_SCLK_I, EMIOSPI0SCLKO => SPI0_SCLK_O, EMIOSPI0SCLKTN => SPI0_SCLK_T_n, EMIOSPI0SI => SPI0_MOSI_I, EMIOSPI0SO => SPI0_MISO_O, EMIOSPI0SSIN => SPI0_SS_I, EMIOSPI0SSNTN => SPI0_SS_T_n, EMIOSPI0SSON(2) => SPI0_SS2_O, EMIOSPI0SSON(1) => SPI0_SS1_O, EMIOSPI0SSON(0) => SPI0_SS_O, EMIOSPI0STN => SPI0_MISO_T_n, EMIOSPI1MI => SPI1_MISO_I, EMIOSPI1MO => SPI1_MOSI_O, EMIOSPI1MOTN => SPI1_MOSI_T_n, EMIOSPI1SCLKI => SPI1_SCLK_I, EMIOSPI1SCLKO => SPI1_SCLK_O, EMIOSPI1SCLKTN => SPI1_SCLK_T_n, EMIOSPI1SI => SPI1_MOSI_I, EMIOSPI1SO => SPI1_MISO_O, EMIOSPI1SSIN => SPI1_SS_I, EMIOSPI1SSNTN => SPI1_SS_T_n, EMIOSPI1SSON(2) => SPI1_SS2_O, EMIOSPI1SSON(1) => SPI1_SS1_O, EMIOSPI1SSON(0) => SPI1_SS_O, EMIOSPI1STN => SPI1_MISO_T_n, EMIOSRAMINTIN => SRAM_INTIN, EMIOTRACECLK => TRACE_CLK, EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), EMIOTTC0CLKI(2) => TTC0_CLK2_IN, EMIOTTC0CLKI(1) => TTC0_CLK1_IN, EMIOTTC0CLKI(0) => TTC0_CLK0_IN, EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT, EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT, EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT, EMIOTTC1CLKI(2) => TTC1_CLK2_IN, EMIOTTC1CLKI(1) => TTC1_CLK1_IN, EMIOTTC1CLKI(0) => TTC1_CLK0_IN, EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT, EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT, EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT, EMIOUART0CTSN => UART0_CTSN, EMIOUART0DCDN => UART0_DCDN, EMIOUART0DSRN => UART0_DSRN, EMIOUART0DTRN => UART0_DTRN, EMIOUART0RIN => UART0_RIN, EMIOUART0RTSN => UART0_RTSN, EMIOUART0RX => UART0_RX, EMIOUART0TX => UART0_TX, EMIOUART1CTSN => UART1_CTSN, EMIOUART1DCDN => UART1_DCDN, EMIOUART1DSRN => UART1_DSRN, EMIOUART1DTRN => UART1_DTRN, EMIOUART1RIN => UART1_RIN, EMIOUART1RTSN => UART1_RTSN, EMIOUART1RX => UART1_RX, EMIOUART1TX => UART1_TX, EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT, EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT, EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT, EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT, EMIOWDTCLKI => WDT_CLK_IN, EMIOWDTRSTO => WDT_RST_OUT, EVENTEVENTI => EVENT_EVENTI, EVENTEVENTO => EVENT_EVENTO, EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0), EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0), FCLKCLK(3) => FCLK_CLK3, FCLKCLK(2) => FCLK_CLK2, FCLKCLK(1) => FCLK_CLK1, FCLKCLK(0) => FCLK_CLK_unbuffered(0), FCLKCLKTRIGN(3 downto 0) => B"0000", FCLKRESETN(3) => FCLK_RESET3_N, FCLKRESETN(2) => FCLK_RESET2_N, FCLKRESETN(1) => FCLK_RESET1_N, FCLKRESETN(0) => FCLK_RESET0_N, FPGAIDLEN => FPGA_IDLE_N, FTMDTRACEINATID(3 downto 0) => B"0000", FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK, FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000", FTMDTRACEINVALID => '0', FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0), FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3, FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2, FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1, FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0, FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3, FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2, FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1, FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0, FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0), FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3, FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2, FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1, FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0, FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3, FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2, FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1, FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0, IRQF2P(19) => Core1_nFIQ, IRQF2P(18) => Core0_nFIQ, IRQF2P(17) => Core1_nIRQ, IRQF2P(16) => Core0_nIRQ, IRQF2P(15 downto 1) => B"000000000000000", IRQF2P(0) => IRQ_F2P(0), IRQP2F(28) => IRQ_P2F_DMAC_ABORT, IRQP2F(27) => IRQ_P2F_DMAC7, IRQP2F(26) => IRQ_P2F_DMAC6, IRQP2F(25) => IRQ_P2F_DMAC5, IRQP2F(24) => IRQ_P2F_DMAC4, IRQP2F(23) => IRQ_P2F_DMAC3, IRQP2F(22) => IRQ_P2F_DMAC2, IRQP2F(21) => IRQ_P2F_DMAC1, IRQP2F(20) => IRQ_P2F_DMAC0, IRQP2F(19) => IRQ_P2F_SMC, IRQP2F(18) => IRQ_P2F_QSPI, IRQP2F(17) => IRQ_P2F_CTI, IRQP2F(16) => IRQ_P2F_GPIO, IRQP2F(15) => IRQ_P2F_USB0, IRQP2F(14) => IRQ_P2F_ENET0, IRQP2F(13) => IRQ_P2F_ENET_WAKE0, IRQP2F(12) => IRQ_P2F_SDIO0, IRQP2F(11) => IRQ_P2F_I2C0, IRQP2F(10) => IRQ_P2F_SPI0, IRQP2F(9) => IRQ_P2F_UART0, IRQP2F(8) => IRQ_P2F_CAN0, IRQP2F(7) => IRQ_P2F_USB1, IRQP2F(6) => IRQ_P2F_ENET1, IRQP2F(5) => IRQ_P2F_ENET_WAKE1, IRQP2F(4) => IRQ_P2F_SDIO1, IRQP2F(3) => IRQ_P2F_I2C1, IRQP2F(2) => IRQ_P2F_SPI1, IRQP2F(1) => IRQ_P2F_UART1, IRQP2F(0) => IRQ_P2F_CAN1, MAXIGP0ACLK => M_AXI_GP0_ACLK, MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1), MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0), MAXIGP0ARESETN => M_AXI_GP0_ARESETN, MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), MAXIGP0ARREADY => M_AXI_GP0_ARREADY, MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), MAXIGP0ARVALID => M_AXI_GP0_ARVALID, MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1), MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0), MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), MAXIGP0AWREADY => M_AXI_GP0_AWREADY, MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), MAXIGP0AWVALID => M_AXI_GP0_AWVALID, MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), MAXIGP0BREADY => M_AXI_GP0_BREADY, MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), MAXIGP0BVALID => M_AXI_GP0_BVALID, MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), MAXIGP0RLAST => M_AXI_GP0_RLAST, MAXIGP0RREADY => M_AXI_GP0_RREADY, MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), MAXIGP0RVALID => M_AXI_GP0_RVALID, MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), MAXIGP0WLAST => M_AXI_GP0_WLAST, MAXIGP0WREADY => M_AXI_GP0_WREADY, MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), MAXIGP0WVALID => M_AXI_GP0_WVALID, MAXIGP1ACLK => M_AXI_GP1_ACLK, MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2), MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1), MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0), MAXIGP1ARESETN => M_AXI_GP1_ARESETN, MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), MAXIGP1ARREADY => M_AXI_GP1_ARREADY, MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0), MAXIGP1ARVALID => M_AXI_GP1_ARVALID, MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2), MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1), MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0), MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), MAXIGP1AWREADY => M_AXI_GP1_AWREADY, MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0), MAXIGP1AWVALID => M_AXI_GP1_AWVALID, MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), MAXIGP1BREADY => M_AXI_GP1_BREADY, MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), MAXIGP1BVALID => M_AXI_GP1_BVALID, MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), MAXIGP1RLAST => M_AXI_GP1_RLAST, MAXIGP1RREADY => M_AXI_GP1_RREADY, MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), MAXIGP1RVALID => M_AXI_GP1_RVALID, MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), MAXIGP1WLAST => M_AXI_GP1_WLAST, MAXIGP1WREADY => M_AXI_GP1_WREADY, MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), MAXIGP1WVALID => M_AXI_GP1_WVALID, MIO(53 downto 0) => buffered_MIO(53 downto 0), PSCLK => buffered_PS_CLK, PSPORB => buffered_PS_PORB, PSSRSTB => buffered_PS_SRSTB, SAXIACPACLK => S_AXI_ACP_ACLK, SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0), SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0), SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0), SAXIACPARESETN => S_AXI_ACP_ARESETN, SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0), SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0), SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0), SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0), SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0), SAXIACPARREADY => S_AXI_ACP_ARREADY, SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0), SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0), SAXIACPARVALID => S_AXI_ACP_ARVALID, SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0), SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0), SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0), SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0), SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0), SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0), SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0), SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0), SAXIACPAWREADY => S_AXI_ACP_AWREADY, SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0), SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0), SAXIACPAWVALID => S_AXI_ACP_AWVALID, SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0), SAXIACPBREADY => S_AXI_ACP_BREADY, SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0), SAXIACPBVALID => S_AXI_ACP_BVALID, SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0), SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0), SAXIACPRLAST => S_AXI_ACP_RLAST, SAXIACPRREADY => S_AXI_ACP_RREADY, SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0), SAXIACPRVALID => S_AXI_ACP_RVALID, SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0), SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0), SAXIACPWLAST => S_AXI_ACP_WLAST, SAXIACPWREADY => S_AXI_ACP_WREADY, SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0), SAXIACPWVALID => S_AXI_ACP_WVALID, SAXIGP0ACLK => S_AXI_GP0_ACLK, SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0), SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0), SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0), SAXIGP0ARESETN => S_AXI_GP0_ARESETN, SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0), SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0), SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0), SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0), SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0), SAXIGP0ARREADY => S_AXI_GP0_ARREADY, SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0), SAXIGP0ARVALID => S_AXI_GP0_ARVALID, SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0), SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0), SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0), SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0), SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0), SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0), SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0), SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0), SAXIGP0AWREADY => S_AXI_GP0_AWREADY, SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0), SAXIGP0AWVALID => S_AXI_GP0_AWVALID, SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0), SAXIGP0BREADY => S_AXI_GP0_BREADY, SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0), SAXIGP0BVALID => S_AXI_GP0_BVALID, SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0), SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0), SAXIGP0RLAST => S_AXI_GP0_RLAST, SAXIGP0RREADY => S_AXI_GP0_RREADY, SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0), SAXIGP0RVALID => S_AXI_GP0_RVALID, SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0), SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0), SAXIGP0WLAST => S_AXI_GP0_WLAST, SAXIGP0WREADY => S_AXI_GP0_WREADY, SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0), SAXIGP0WVALID => S_AXI_GP0_WVALID, SAXIGP1ACLK => S_AXI_GP1_ACLK, SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0), SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0), SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0), SAXIGP1ARESETN => S_AXI_GP1_ARESETN, SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0), SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0), SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0), SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0), SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0), SAXIGP1ARREADY => S_AXI_GP1_ARREADY, SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0), SAXIGP1ARVALID => S_AXI_GP1_ARVALID, SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0), SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0), SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0), SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0), SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0), SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0), SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0), SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0), SAXIGP1AWREADY => S_AXI_GP1_AWREADY, SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0), SAXIGP1AWVALID => S_AXI_GP1_AWVALID, SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0), SAXIGP1BREADY => S_AXI_GP1_BREADY, SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0), SAXIGP1BVALID => S_AXI_GP1_BVALID, SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0), SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0), SAXIGP1RLAST => S_AXI_GP1_RLAST, SAXIGP1RREADY => S_AXI_GP1_RREADY, SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0), SAXIGP1RVALID => S_AXI_GP1_RVALID, SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0), SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0), SAXIGP1WLAST => S_AXI_GP1_WLAST, SAXIGP1WREADY => S_AXI_GP1_WREADY, SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0), SAXIGP1WVALID => S_AXI_GP1_WVALID, SAXIHP0ACLK => S_AXI_HP0_ACLK, SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), SAXIHP0ARESETN => S_AXI_HP0_ARESETN, SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), SAXIHP0ARREADY => S_AXI_HP0_ARREADY, SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0), SAXIHP0ARVALID => S_AXI_HP0_ARVALID, SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), SAXIHP0AWREADY => S_AXI_HP0_AWREADY, SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0), SAXIHP0AWVALID => S_AXI_HP0_AWVALID, SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), SAXIHP0BREADY => S_AXI_HP0_BREADY, SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), SAXIHP0BVALID => S_AXI_HP0_BVALID, SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0), SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN, SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), SAXIHP0RLAST => S_AXI_HP0_RLAST, SAXIHP0RREADY => S_AXI_HP0_RREADY, SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), SAXIHP0RVALID => S_AXI_HP0_RVALID, SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0), SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), SAXIHP0WLAST => S_AXI_HP0_WLAST, SAXIHP0WREADY => S_AXI_HP0_WREADY, SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN, SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0), SAXIHP0WVALID => S_AXI_HP0_WVALID, SAXIHP1ACLK => S_AXI_HP1_ACLK, SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), SAXIHP1ARESETN => S_AXI_HP1_ARESETN, SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), SAXIHP1ARREADY => S_AXI_HP1_ARREADY, SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0), SAXIHP1ARVALID => S_AXI_HP1_ARVALID, SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), SAXIHP1AWREADY => S_AXI_HP1_AWREADY, SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0), SAXIHP1AWVALID => S_AXI_HP1_AWVALID, SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), SAXIHP1BREADY => S_AXI_HP1_BREADY, SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), SAXIHP1BVALID => S_AXI_HP1_BVALID, SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN, SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), SAXIHP1RLAST => S_AXI_HP1_RLAST, SAXIHP1RREADY => S_AXI_HP1_RREADY, SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), SAXIHP1RVALID => S_AXI_HP1_RVALID, SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), SAXIHP1WLAST => S_AXI_HP1_WLAST, SAXIHP1WREADY => S_AXI_HP1_WREADY, SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN, SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), SAXIHP1WVALID => S_AXI_HP1_WVALID, SAXIHP2ACLK => S_AXI_HP2_ACLK, SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0), SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0), SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0), SAXIHP2ARESETN => S_AXI_HP2_ARESETN, SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0), SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0), SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0), SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0), SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0), SAXIHP2ARREADY => S_AXI_HP2_ARREADY, SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0), SAXIHP2ARVALID => S_AXI_HP2_ARVALID, SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0), SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0), SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0), SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0), SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0), SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0), SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0), SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0), SAXIHP2AWREADY => S_AXI_HP2_AWREADY, SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0), SAXIHP2AWVALID => S_AXI_HP2_AWVALID, SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0), SAXIHP2BREADY => S_AXI_HP2_BREADY, SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0), SAXIHP2BVALID => S_AXI_HP2_BVALID, SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0), SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0), SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0), SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN, SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0), SAXIHP2RLAST => S_AXI_HP2_RLAST, SAXIHP2RREADY => S_AXI_HP2_RREADY, SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0), SAXIHP2RVALID => S_AXI_HP2_RVALID, SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0), SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0), SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0), SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0), SAXIHP2WLAST => S_AXI_HP2_WLAST, SAXIHP2WREADY => S_AXI_HP2_WREADY, SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN, SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0), SAXIHP2WVALID => S_AXI_HP2_WVALID, SAXIHP3ACLK => S_AXI_HP3_ACLK, SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0), SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0), SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0), SAXIHP3ARESETN => S_AXI_HP3_ARESETN, SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0), SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0), SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0), SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0), SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0), SAXIHP3ARREADY => S_AXI_HP3_ARREADY, SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0), SAXIHP3ARVALID => S_AXI_HP3_ARVALID, SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0), SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0), SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0), SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0), SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0), SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0), SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0), SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0), SAXIHP3AWREADY => S_AXI_HP3_AWREADY, SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0), SAXIHP3AWVALID => S_AXI_HP3_AWVALID, SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0), SAXIHP3BREADY => S_AXI_HP3_BREADY, SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0), SAXIHP3BVALID => S_AXI_HP3_BVALID, SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0), SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0), SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0), SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN, SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0), SAXIHP3RLAST => S_AXI_HP3_RLAST, SAXIHP3RREADY => S_AXI_HP3_RREADY, SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0), SAXIHP3RVALID => S_AXI_HP3_RVALID, SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0), SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0), SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0), SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0), SAXIHP3WLAST => S_AXI_HP3_WLAST, SAXIHP3WREADY => S_AXI_HP3_WREADY, SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN, SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0), SAXIHP3WVALID => S_AXI_HP3_WVALID ); PS_CLK_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_CLK, PAD => PS_CLK ); PS_PORB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_PORB, PAD => PS_PORB ); PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_SRSTB, PAD => PS_SRSTB ); SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_CMD_T_n, O => SDIO0_CMD_T ); \SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(0), O => SDIO0_DATA_T(0) ); \SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(1), O => SDIO0_DATA_T(1) ); \SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(2), O => SDIO0_DATA_T(2) ); \SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(3), O => SDIO0_DATA_T(3) ); SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_CMD_T_n, O => SDIO1_CMD_T ); \SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(0), O => SDIO1_DATA_T(0) ); \SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(1), O => SDIO1_DATA_T(1) ); \SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(2), O => SDIO1_DATA_T(2) ); \SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(3), O => SDIO1_DATA_T(3) ); SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MISO_T_n, O => SPI0_MISO_T ); SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MOSI_T_n, O => SPI0_MOSI_T ); SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SCLK_T_n, O => SPI0_SCLK_T ); SPI0_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SS_T_n, O => SPI0_SS_T ); SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MISO_T_n, O => SPI1_MISO_T ); SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MOSI_T_n, O => SPI1_MOSI_T ); SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SCLK_T_n, O => SPI1_SCLK_T ); SPI1_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SS_T_n, O => SPI1_SS_T ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG port map ( I => FCLK_CLK_unbuffered(0), O => FCLK_CLK0 ); \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(0), PAD => MIO(0) ); \genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(10), PAD => MIO(10) ); \genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(11), PAD => MIO(11) ); \genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(12), PAD => MIO(12) ); \genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(13), PAD => MIO(13) ); \genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(14), PAD => MIO(14) ); \genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(15), PAD => MIO(15) ); \genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(16), PAD => MIO(16) ); \genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(17), PAD => MIO(17) ); \genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(18), PAD => MIO(18) ); \genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(19), PAD => MIO(19) ); \genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(1), PAD => MIO(1) ); \genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(20), PAD => MIO(20) ); \genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(21), PAD => MIO(21) ); \genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(22), PAD => MIO(22) ); \genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(23), PAD => MIO(23) ); \genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(24), PAD => MIO(24) ); \genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(25), PAD => MIO(25) ); \genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(26), PAD => MIO(26) ); \genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(27), PAD => MIO(27) ); \genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(28), PAD => MIO(28) ); \genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(29), PAD => MIO(29) ); \genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(2), PAD => MIO(2) ); \genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(30), PAD => MIO(30) ); \genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(31), PAD => MIO(31) ); \genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(32), PAD => MIO(32) ); \genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(33), PAD => MIO(33) ); \genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(34), PAD => MIO(34) ); \genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(35), PAD => MIO(35) ); \genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(36), PAD => MIO(36) ); \genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(37), PAD => MIO(37) ); \genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(38), PAD => MIO(38) ); \genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(39), PAD => MIO(39) ); \genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(3), PAD => MIO(3) ); \genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(40), PAD => MIO(40) ); \genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(41), PAD => MIO(41) ); \genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(42), PAD => MIO(42) ); \genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(43), PAD => MIO(43) ); \genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(44), PAD => MIO(44) ); \genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(45), PAD => MIO(45) ); \genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(46), PAD => MIO(46) ); \genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(47), PAD => MIO(47) ); \genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(48), PAD => MIO(48) ); \genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(49), PAD => MIO(49) ); \genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(4), PAD => MIO(4) ); \genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(50), PAD => MIO(50) ); \genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(51), PAD => MIO(51) ); \genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(52), PAD => MIO(52) ); \genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(53), PAD => MIO(53) ); \genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(5), PAD => MIO(5) ); \genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(6), PAD => MIO(6) ); \genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(7), PAD => MIO(7) ); \genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(8), PAD => MIO(8) ); \genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(9), PAD => MIO(9) ); \genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(0), PAD => DDR_BankAddr(0) ); \genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(1), PAD => DDR_BankAddr(1) ); \genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(2), PAD => DDR_BankAddr(2) ); \genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(0), PAD => DDR_Addr(0) ); \genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(10), PAD => DDR_Addr(10) ); \genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(11), PAD => DDR_Addr(11) ); \genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(12), PAD => DDR_Addr(12) ); \genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(13), PAD => DDR_Addr(13) ); \genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(14), PAD => DDR_Addr(14) ); \genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(1), PAD => DDR_Addr(1) ); \genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(2), PAD => DDR_Addr(2) ); \genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(3), PAD => DDR_Addr(3) ); \genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(4), PAD => DDR_Addr(4) ); \genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(5), PAD => DDR_Addr(5) ); \genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(6), PAD => DDR_Addr(6) ); \genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(7), PAD => DDR_Addr(7) ); \genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(8), PAD => DDR_Addr(8) ); \genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(9), PAD => DDR_Addr(9) ); \genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(0), PAD => DDR_DM(0) ); \genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(1), PAD => DDR_DM(1) ); \genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(2), PAD => DDR_DM(2) ); \genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(3), PAD => DDR_DM(3) ); \genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(0), PAD => DDR_DQ(0) ); \genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(10), PAD => DDR_DQ(10) ); \genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(11), PAD => DDR_DQ(11) ); \genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(12), PAD => DDR_DQ(12) ); \genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(13), PAD => DDR_DQ(13) ); \genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(14), PAD => DDR_DQ(14) ); \genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(15), PAD => DDR_DQ(15) ); \genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(16), PAD => DDR_DQ(16) ); \genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(17), PAD => DDR_DQ(17) ); \genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(18), PAD => DDR_DQ(18) ); \genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(19), PAD => DDR_DQ(19) ); \genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(1), PAD => DDR_DQ(1) ); \genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(20), PAD => DDR_DQ(20) ); \genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(21), PAD => DDR_DQ(21) ); \genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(22), PAD => DDR_DQ(22) ); \genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(23), PAD => DDR_DQ(23) ); \genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(24), PAD => DDR_DQ(24) ); \genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(25), PAD => DDR_DQ(25) ); \genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(26), PAD => DDR_DQ(26) ); \genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(27), PAD => DDR_DQ(27) ); \genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(28), PAD => DDR_DQ(28) ); \genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(29), PAD => DDR_DQ(29) ); \genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(2), PAD => DDR_DQ(2) ); \genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(30), PAD => DDR_DQ(30) ); \genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(31), PAD => DDR_DQ(31) ); \genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(3), PAD => DDR_DQ(3) ); \genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(4), PAD => DDR_DQ(4) ); \genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(5), PAD => DDR_DQ(5) ); \genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(6), PAD => DDR_DQ(6) ); \genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(7), PAD => DDR_DQ(7) ); \genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(8), PAD => DDR_DQ(8) ); \genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(9), PAD => DDR_DQ(9) ); \genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(0), PAD => DDR_DQS_n(0) ); \genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(1), PAD => DDR_DQS_n(1) ); \genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(2), PAD => DDR_DQS_n(2) ); \genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(3), PAD => DDR_DQS_n(3) ); \genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(0), PAD => DDR_DQS(0) ); \genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(1), PAD => DDR_DQS(1) ); \genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(2), PAD => DDR_DQS(2) ); \genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(3), PAD => DDR_DQS(3) ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[0]\ ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(1) ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(1) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(0) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(1) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(0) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(1) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(0) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(1) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(0) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(1) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(0) ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(1) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(0) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(1) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(0) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[7]\ ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[6]\ ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[5]\ ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[4]\ ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[3]\ ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[2]\ ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of inst : label is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of inst : label is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of inst : label is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of inst : label is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of inst : label is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of inst : label is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of inst : label is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of inst : label is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of inst : label is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of inst : label is "clg484"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of inst : label is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of inst : label is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of inst : label is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of inst : label is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of inst : label is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of inst : label is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of inst : label is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of inst : label is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of inst : label is "zynq_design_1_processing_system7_0_2.hwdef"; attribute POWER : string; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 port map ( CAN0_PHY_RX => '0', CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, CAN1_PHY_RX => '0', CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, Core0_nFIQ => '0', Core0_nIRQ => '0', Core1_nFIQ => '0', Core1_nIRQ => '0', DDR_ARB(3 downto 0) => B"0000", DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), DDR_CAS_n => DDR_CAS_n, DDR_CKE => DDR_CKE, DDR_CS_n => DDR_CS_n, DDR_Clk => DDR_Clk, DDR_Clk_n => DDR_Clk_n, DDR_DM(3 downto 0) => DDR_DM(3 downto 0), DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), DDR_DRSTB => DDR_DRSTB, DDR_ODT => DDR_ODT, DDR_RAS_n => DDR_RAS_n, DDR_VRN => DDR_VRN, DDR_VRP => DDR_VRP, DDR_WEB => DDR_WEB, DMA0_ACLK => '0', DMA0_DAREADY => '0', DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, DMA0_DRLAST => '0', DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, DMA0_DRTYPE(1 downto 0) => B"00", DMA0_DRVALID => '0', DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, DMA1_ACLK => '0', DMA1_DAREADY => '0', DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, DMA1_DRLAST => '0', DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, DMA1_DRTYPE(1 downto 0) => B"00", DMA1_DRVALID => '0', DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, DMA2_ACLK => '0', DMA2_DAREADY => '0', DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, DMA2_DRLAST => '0', DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, DMA2_DRTYPE(1 downto 0) => B"00", DMA2_DRVALID => '0', DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, DMA3_ACLK => '0', DMA3_DAREADY => '0', DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, DMA3_DRLAST => '0', DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, DMA3_DRTYPE(1 downto 0) => B"00", DMA3_DRVALID => '0', DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, ENET0_EXT_INTIN => '0', ENET0_GMII_COL => '0', ENET0_GMII_CRS => '0', ENET0_GMII_RXD(7 downto 0) => B"00000000", ENET0_GMII_RX_CLK => '0', ENET0_GMII_RX_DV => '0', ENET0_GMII_RX_ER => '0', ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), ENET0_GMII_TX_CLK => '0', ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, ENET0_MDIO_I => '0', ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED, ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED, ENET1_EXT_INTIN => '0', ENET1_GMII_COL => '0', ENET1_GMII_CRS => '0', ENET1_GMII_RXD(7 downto 0) => B"00000000", ENET1_GMII_RX_CLK => '0', ENET1_GMII_RX_DV => '0', ENET1_GMII_RX_ER => '0', ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), ENET1_GMII_TX_CLK => '0', ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, ENET1_MDIO_I => '0', ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, EVENT_EVENTI => '0', EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), FCLK_CLK0 => FCLK_CLK0, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, FCLK_CLKTRIG0_N => '0', FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG3_N => '0', FCLK_RESET0_N => FCLK_RESET0_N, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, FPGA_IDLE_N => '0', FTMD_TRACEIN_ATID(3 downto 0) => B"0000", FTMD_TRACEIN_CLK => '0', FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000", FTMD_TRACEIN_VALID => '0', FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000", FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, FTMT_F2P_TRIG_0 => '0', FTMT_F2P_TRIG_1 => '0', FTMT_F2P_TRIG_2 => '0', FTMT_F2P_TRIG_3 => '0', FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), FTMT_P2F_TRIGACK_0 => '0', FTMT_P2F_TRIGACK_1 => '0', FTMT_P2F_TRIGACK_2 => '0', FTMT_P2F_TRIGACK_3 => '0', FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0), GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0), I2C0_SCL_I => '0', I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED, I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED, I2C0_SDA_I => '0', I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED, I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED, I2C1_SCL_I => '0', I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, I2C1_SDA_I => '0', I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, IRQ_F2P(0) => '0', IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, MIO(53 downto 0) => MIO(53 downto 0), M_AXI_GP0_ACLK => M_AXI_GP0_ACLK, M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => M_AXI_GP0_WVALID, M_AXI_GP1_ACLK => '0', M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0), M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_ARREADY => '0', M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED, M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0), M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_AWREADY => '0', M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED, M_AXI_GP1_BID(11 downto 0) => B"000000000000", M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED, M_AXI_GP1_BRESP(1 downto 0) => B"00", M_AXI_GP1_BVALID => '0', M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000", M_AXI_GP1_RID(11 downto 0) => B"000000000000", M_AXI_GP1_RLAST => '0', M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED, M_AXI_GP1_RRESP(1 downto 0) => B"00", M_AXI_GP1_RVALID => '0', M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0), M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED, M_AXI_GP1_WREADY => '0', M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED, PJTAG_TCK => '0', PJTAG_TDI => '0', PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, PJTAG_TMS => '0', PS_CLK => PS_CLK, PS_PORB => PS_PORB, PS_SRSTB => PS_SRSTB, SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), SDIO0_CDN => '0', SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, SDIO0_CLK_FB => '0', SDIO0_CMD_I => '0', SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, SDIO0_DATA_I(3 downto 0) => B"0000", SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, SDIO0_WP => '0', SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), SDIO1_CDN => '0', SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, SDIO1_CLK_FB => '0', SDIO1_CMD_I => '0', SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, SDIO1_DATA_I(3 downto 0) => B"0000", SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, SDIO1_WP => '0', SPI0_MISO_I => '0', SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, SPI0_MOSI_I => '0', SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, SPI0_SCLK_I => '0', SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, SPI0_SS_I => '0', SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, SPI1_MISO_I => '0', SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, SPI1_MOSI_I => '0', SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, SPI1_SCLK_I => '0', SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, SPI1_SS_I => '0', SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, SRAM_INTIN => '0', S_AXI_ACP_ACLK => '0', S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_ARBURST(1 downto 0) => B"00", S_AXI_ACP_ARCACHE(3 downto 0) => B"0000", S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, S_AXI_ACP_ARID(2 downto 0) => B"000", S_AXI_ACP_ARLEN(3 downto 0) => B"0000", S_AXI_ACP_ARLOCK(1 downto 0) => B"00", S_AXI_ACP_ARPROT(2 downto 0) => B"000", S_AXI_ACP_ARQOS(3 downto 0) => B"0000", S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, S_AXI_ACP_ARSIZE(2 downto 0) => B"000", S_AXI_ACP_ARUSER(4 downto 0) => B"00000", S_AXI_ACP_ARVALID => '0', S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_AWBURST(1 downto 0) => B"00", S_AXI_ACP_AWCACHE(3 downto 0) => B"0000", S_AXI_ACP_AWID(2 downto 0) => B"000", S_AXI_ACP_AWLEN(3 downto 0) => B"0000", S_AXI_ACP_AWLOCK(1 downto 0) => B"00", S_AXI_ACP_AWPROT(2 downto 0) => B"000", S_AXI_ACP_AWQOS(3 downto 0) => B"0000", S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, S_AXI_ACP_AWSIZE(2 downto 0) => B"000", S_AXI_ACP_AWUSER(4 downto 0) => B"00000", S_AXI_ACP_AWVALID => '0', S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), S_AXI_ACP_BREADY => '0', S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, S_AXI_ACP_RREADY => '0', S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_ACP_WID(2 downto 0) => B"000", S_AXI_ACP_WLAST => '0', S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, S_AXI_ACP_WSTRB(7 downto 0) => B"00000000", S_AXI_ACP_WVALID => '0', S_AXI_GP0_ACLK => '0', S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_ARBURST(1 downto 0) => B"00", S_AXI_GP0_ARCACHE(3 downto 0) => B"0000", S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, S_AXI_GP0_ARID(5 downto 0) => B"000000", S_AXI_GP0_ARLEN(3 downto 0) => B"0000", S_AXI_GP0_ARLOCK(1 downto 0) => B"00", S_AXI_GP0_ARPROT(2 downto 0) => B"000", S_AXI_GP0_ARQOS(3 downto 0) => B"0000", S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, S_AXI_GP0_ARSIZE(2 downto 0) => B"000", S_AXI_GP0_ARVALID => '0', S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_AWBURST(1 downto 0) => B"00", S_AXI_GP0_AWCACHE(3 downto 0) => B"0000", S_AXI_GP0_AWID(5 downto 0) => B"000000", S_AXI_GP0_AWLEN(3 downto 0) => B"0000", S_AXI_GP0_AWLOCK(1 downto 0) => B"00", S_AXI_GP0_AWPROT(2 downto 0) => B"000", S_AXI_GP0_AWQOS(3 downto 0) => B"0000", S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, S_AXI_GP0_AWSIZE(2 downto 0) => B"000", S_AXI_GP0_AWVALID => '0', S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), S_AXI_GP0_BREADY => '0', S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, S_AXI_GP0_RREADY => '0', S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_WID(5 downto 0) => B"000000", S_AXI_GP0_WLAST => '0', S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, S_AXI_GP0_WSTRB(3 downto 0) => B"0000", S_AXI_GP0_WVALID => '0', S_AXI_GP1_ACLK => '0', S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_ARBURST(1 downto 0) => B"00", S_AXI_GP1_ARCACHE(3 downto 0) => B"0000", S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, S_AXI_GP1_ARID(5 downto 0) => B"000000", S_AXI_GP1_ARLEN(3 downto 0) => B"0000", S_AXI_GP1_ARLOCK(1 downto 0) => B"00", S_AXI_GP1_ARPROT(2 downto 0) => B"000", S_AXI_GP1_ARQOS(3 downto 0) => B"0000", S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, S_AXI_GP1_ARSIZE(2 downto 0) => B"000", S_AXI_GP1_ARVALID => '0', S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_AWBURST(1 downto 0) => B"00", S_AXI_GP1_AWCACHE(3 downto 0) => B"0000", S_AXI_GP1_AWID(5 downto 0) => B"000000", S_AXI_GP1_AWLEN(3 downto 0) => B"0000", S_AXI_GP1_AWLOCK(1 downto 0) => B"00", S_AXI_GP1_AWPROT(2 downto 0) => B"000", S_AXI_GP1_AWQOS(3 downto 0) => B"0000", S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, S_AXI_GP1_AWSIZE(2 downto 0) => B"000", S_AXI_GP1_AWVALID => '0', S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), S_AXI_GP1_BREADY => '0', S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, S_AXI_GP1_RREADY => '0', S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_WID(5 downto 0) => B"000000", S_AXI_GP1_WLAST => '0', S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, S_AXI_GP1_WSTRB(3 downto 0) => B"0000", S_AXI_GP1_WVALID => '0', S_AXI_HP0_ACLK => '0', S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_ARBURST(1 downto 0) => B"00", S_AXI_HP0_ARCACHE(3 downto 0) => B"0000", S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, S_AXI_HP0_ARID(5 downto 0) => B"000000", S_AXI_HP0_ARLEN(3 downto 0) => B"0000", S_AXI_HP0_ARLOCK(1 downto 0) => B"00", S_AXI_HP0_ARPROT(2 downto 0) => B"000", S_AXI_HP0_ARQOS(3 downto 0) => B"0000", S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED, S_AXI_HP0_ARSIZE(2 downto 0) => B"000", S_AXI_HP0_ARVALID => '0', S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_AWBURST(1 downto 0) => B"00", S_AXI_HP0_AWCACHE(3 downto 0) => B"0000", S_AXI_HP0_AWID(5 downto 0) => B"000000", S_AXI_HP0_AWLEN(3 downto 0) => B"0000", S_AXI_HP0_AWLOCK(1 downto 0) => B"00", S_AXI_HP0_AWPROT(2 downto 0) => B"000", S_AXI_HP0_AWQOS(3 downto 0) => B"0000", S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED, S_AXI_HP0_AWSIZE(2 downto 0) => B"000", S_AXI_HP0_AWVALID => '0', S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), S_AXI_HP0_BREADY => '0', S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED, S_AXI_HP0_RREADY => '0', S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP0_WID(5 downto 0) => B"000000", S_AXI_HP0_WLAST => '0', S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED, S_AXI_HP0_WRISSUECAP1_EN => '0', S_AXI_HP0_WSTRB(7 downto 0) => B"00000000", S_AXI_HP0_WVALID => '0', S_AXI_HP1_ACLK => '0', S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_ARBURST(1 downto 0) => B"00", S_AXI_HP1_ARCACHE(3 downto 0) => B"0000", S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, S_AXI_HP1_ARID(5 downto 0) => B"000000", S_AXI_HP1_ARLEN(3 downto 0) => B"0000", S_AXI_HP1_ARLOCK(1 downto 0) => B"00", S_AXI_HP1_ARPROT(2 downto 0) => B"000", S_AXI_HP1_ARQOS(3 downto 0) => B"0000", S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED, S_AXI_HP1_ARSIZE(2 downto 0) => B"000", S_AXI_HP1_ARVALID => '0', S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_AWBURST(1 downto 0) => B"00", S_AXI_HP1_AWCACHE(3 downto 0) => B"0000", S_AXI_HP1_AWID(5 downto 0) => B"000000", S_AXI_HP1_AWLEN(3 downto 0) => B"0000", S_AXI_HP1_AWLOCK(1 downto 0) => B"00", S_AXI_HP1_AWPROT(2 downto 0) => B"000", S_AXI_HP1_AWQOS(3 downto 0) => B"0000", S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED, S_AXI_HP1_AWSIZE(2 downto 0) => B"000", S_AXI_HP1_AWVALID => '0', S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0), S_AXI_HP1_BREADY => '0', S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED, S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP1_RDISSUECAP1_EN => '0', S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0), S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED, S_AXI_HP1_RREADY => '0', S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED, S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP1_WID(5 downto 0) => B"000000", S_AXI_HP1_WLAST => '0', S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED, S_AXI_HP1_WRISSUECAP1_EN => '0', S_AXI_HP1_WSTRB(7 downto 0) => B"00000000", S_AXI_HP1_WVALID => '0', S_AXI_HP2_ACLK => '0', S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_ARBURST(1 downto 0) => B"00", S_AXI_HP2_ARCACHE(3 downto 0) => B"0000", S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, S_AXI_HP2_ARID(5 downto 0) => B"000000", S_AXI_HP2_ARLEN(3 downto 0) => B"0000", S_AXI_HP2_ARLOCK(1 downto 0) => B"00", S_AXI_HP2_ARPROT(2 downto 0) => B"000", S_AXI_HP2_ARQOS(3 downto 0) => B"0000", S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, S_AXI_HP2_ARSIZE(2 downto 0) => B"000", S_AXI_HP2_ARVALID => '0', S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_AWBURST(1 downto 0) => B"00", S_AXI_HP2_AWCACHE(3 downto 0) => B"0000", S_AXI_HP2_AWID(5 downto 0) => B"000000", S_AXI_HP2_AWLEN(3 downto 0) => B"0000", S_AXI_HP2_AWLOCK(1 downto 0) => B"00", S_AXI_HP2_AWPROT(2 downto 0) => B"000", S_AXI_HP2_AWQOS(3 downto 0) => B"0000", S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, S_AXI_HP2_AWSIZE(2 downto 0) => B"000", S_AXI_HP2_AWVALID => '0', S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), S_AXI_HP2_BREADY => '0', S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP2_RDISSUECAP1_EN => '0', S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, S_AXI_HP2_RREADY => '0', S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP2_WID(5 downto 0) => B"000000", S_AXI_HP2_WLAST => '0', S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, S_AXI_HP2_WRISSUECAP1_EN => '0', S_AXI_HP2_WSTRB(7 downto 0) => B"00000000", S_AXI_HP2_WVALID => '0', S_AXI_HP3_ACLK => '0', S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_ARBURST(1 downto 0) => B"00", S_AXI_HP3_ARCACHE(3 downto 0) => B"0000", S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, S_AXI_HP3_ARID(5 downto 0) => B"000000", S_AXI_HP3_ARLEN(3 downto 0) => B"0000", S_AXI_HP3_ARLOCK(1 downto 0) => B"00", S_AXI_HP3_ARPROT(2 downto 0) => B"000", S_AXI_HP3_ARQOS(3 downto 0) => B"0000", S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, S_AXI_HP3_ARSIZE(2 downto 0) => B"000", S_AXI_HP3_ARVALID => '0', S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_AWBURST(1 downto 0) => B"00", S_AXI_HP3_AWCACHE(3 downto 0) => B"0000", S_AXI_HP3_AWID(5 downto 0) => B"000000", S_AXI_HP3_AWLEN(3 downto 0) => B"0000", S_AXI_HP3_AWLOCK(1 downto 0) => B"00", S_AXI_HP3_AWPROT(2 downto 0) => B"000", S_AXI_HP3_AWQOS(3 downto 0) => B"0000", S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, S_AXI_HP3_AWSIZE(2 downto 0) => B"000", S_AXI_HP3_AWVALID => '0', S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), S_AXI_HP3_BREADY => '0', S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP3_RDISSUECAP1_EN => '0', S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, S_AXI_HP3_RREADY => '0', S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP3_WID(5 downto 0) => B"000000", S_AXI_HP3_WLAST => '0', S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, S_AXI_HP3_WRISSUECAP1_EN => '0', S_AXI_HP3_WSTRB(7 downto 0) => B"00000000", S_AXI_HP3_WVALID => '0', TRACE_CLK => '0', TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), TTC0_CLK0_IN => '0', TTC0_CLK1_IN => '0', TTC0_CLK2_IN => '0', TTC0_WAVE0_OUT => TTC0_WAVE0_OUT, TTC0_WAVE1_OUT => TTC0_WAVE1_OUT, TTC0_WAVE2_OUT => TTC0_WAVE2_OUT, TTC1_CLK0_IN => '0', TTC1_CLK1_IN => '0', TTC1_CLK2_IN => '0', TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, UART0_CTSN => '0', UART0_DCDN => '0', UART0_DSRN => '0', UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, UART0_RIN => '0', UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, UART0_RX => '1', UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, UART1_CTSN => '0', UART1_DCDN => '0', UART1_DSRN => '0', UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, UART1_RIN => '0', UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, UART1_RX => '1', UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT, USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT, USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0), USB1_VBUS_PWRFAULT => '0', USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED, WDT_CLK_IN => '0', WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED ); end STRUCTURE;
-- An 8-bit register entity to make the code smaller and closer to the drawing library IEEE; use IEEE.STD_LOGIC_1164.all; entity reg8bits is port ( rst : in std_logic; ck : in std_logic; ce : in std_logic; di : in std_logic_vector(7 downto 0); do : out std_logic_vector(7 downto 0) ); end entity; -- This is a behaviorial description of a register. However, all -- the synthesis tools will be able to infer a flip-flop with synchronous reset -- and clock enable architecture rtl of reg8bits is begin reg: process(ck) is begin if rising_edge(ck) then if rst = '1' then do <= x"00"; else if ce = '1' then do <= di; end if; end if; end if; end process; end architecture rtl;
entity FIFO is port ( WR_EN_I : in std_logic; DATA_O : out std_logic_vector(31 downto 0); RD_EN_IO : inout std_logic; DATA_O : out std_logic_vector(31 downto 0) ); end entity FIFO; entity FIFO is port ( WR_EN : in std_logic; DATA : out std_logic_vector(31 downto 0); RD_EN : in std_logic; DATA : out std_logic_vector(31 downto 0) ); end entity FIFO;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 05/23/2015 03:41:27 PM -- Design Name: -- Module Name: InstructionDecoder - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity InstructionDecoder is port ( TimingSignals : in BIT_VECTOR(7 downto 0); -- The 8 different timing states Instruction : in BIT_VECTOR(7 downto 0); -- The instruction to execute Flags : in BIT_VECTOR(7 downto 0); -- Content of the FLAGS register - needed for conditional jumps -- ============================================================== -- The various control lines of the CPU which go low/high -- depending on the timing state and the instruction to execute: -- ============================================================== Load_PC : out BIT; Select_PC : out BIT; Load_SRAM: out BIT; Select_SRAM: out BIT; Return_SRAM: out BIT; Load_INC: out BIT; Select_INC: out BIT; Load_INSTR: out BIT; Select_INSTR_To_DataBus: out BIT; Select_INSTR_To_ALU: out BIT; Load_A_From_DataBus: out BIT; Select_A_To_ALU: out BIT; Load_B_From_DataBus: out BIT; Select_B_To_ALU: out BIT; Load_C_From_DataBus: out BIT; Load_InternalA_From_DataBus: out BIT; Select_InternalA_To_DataBus: out BIT; Load_Flags: out BIT; Select_A_To_DataBus: out BIT; Select_B_To_DataBus: out BIT; Select_C_To_DataBus: out BIT; Load_D_From_DataBus: out BIT; Select_D_To_DataBus: out BIT; Load_E_From_DataBus: out BIT; Select_E_To_DataBus: out BIT; Load_F_From_DataBus: out BIT; Select_F_To_DataBus: out BIT; Load_G_From_DataBus: out BIT; Select_G_To_DataBus: out BIT; Load_H_From_DataBus: out BIT; Select_H_To_DataBus: out BIT; load_M_From_AddressBus: out BIT; select_M_To_AddressBus: out BIT; load_XL_From_DataBus: out BIT; load_XH_From_DataBus: out BIT; load_X_From_AddressBus: out BIT; select_XL_To_DataBus: out BIT; select_XH_To_DataBus: out BIT; select_X_To_AddressBus: out BIT; Load_J_From_AddressBus: out BIT; Select_J_To_AddressBus: out BIT; Load_SP_From_AddressBus: out BIT; Select_SP_To_AddressBus: out BIT; Load_BP_From_AddressBus: out BIT; Select_BP_To_AddressBus: out BIT; Load_Y_From_AddressBus: out BIT; Select_Y_To_AddressBus: out BIT; Load_Z_From_AddressBus: out BIT; Select_Z_To_AddressBus: out BIT; Load_Adder16Bit_InputA: out BIT; Select_Adder16Bit_InputA: out BIT; Load_Adder16Bit_InputB: out BIT; Select_Adder16Bit_InputB: out BIT; Load_Adder16Bit_OutputC: out BIT; Select_Adder16Bit_OutputC: out BIT; load_FlagsSaved_From_FlagsRegister: out BIT; load_FlagsSaved_To_FlagsRegister: out BIT; Load_FlagsFromDataBus: out BIT; Select_FlagsToFlagsBus: out BIT; Load_FlagsFromFlagsBus: out BIT; Select_FlagsToDataBus: out BIT; Select_Flags: out BIT; Select_PortA_To_DataBus: out BIT; Select_PortB_To_DataBus: out BIT; Load_PortC_From_DataBus: out BIT; Load_PortD_From_DataBus: out BIT; StopCPU: out BIT ); end InstructionDecoder; architecture Behavioral of InstructionDecoder is component Decoder3to8 is Port ( F : in BIT_VECTOR(2 downto 0); -- 3-Bit Function Code (Input) X : out BIT_VECTOR(7 downto 0); -- 8-Bit State (Output) Started: in BIT -- Is the CPU already running? ); end component Decoder3to8; signal NegatedInstruction : BIT_VECTOR(7 downto 0); signal NegatedFlags : BIT_VECTOR(7 downto 0); signal instruction_SETAB: BIT; signal instruction_ALU: BIT; signal instruction_MOV: BIT; signal instruction_MOV16: BIT; signal instruction_LOAD: BIT; signal instruction_STORE: BIT; signal instruction_JMP: BIT; signal instruction_HLT: BIT; signal instruction_JZ: BIT; signal instruction_JNZ: BIT; signal instruction_JNS: BIT; signal instruction_JNC: BIT; signal instruction_SAVE_FLAGS: BIT; signal instruction_RESTORE_FLAGS: BIT; signal instruction_NOP: BIT; signal instruction_FLAGS_TO_OUTBUFFER: BIT; signal instruction_INBUFFER_TO_FLAGS: BIT; signal instruction_ADDER_16BIT: BIT; signal instruction_STORE_FLAGS: BIT; signal instruction_LOAD_FLAGS: BIT; signal instruction_IN: BIT; signal instruction_OUT: BIT; -- Internal ALU instructions signal instruction_MOV_ALU_IN: BIT; signal instruction_MOV_ALU_OUT: BIT; signal instruction_MOV_ALU_C_TO_AB: BIT; signal MOV_DestinationRegister: BIT_VECTOR(7 downto 0); signal MOV_SourceRegister: BIT_VECTOR(7 downto 0); signal MOV16_DestinationRegister: BIT_VECTOR(7 downto 0); signal MOV16_SourceRegister: BIT_VECTOR(7 downto 0); -- Used by the Fetch/Increment cycle signal Select_SRAM_FETCH: BIT; signal Load_PC_FETCH: BIT; signal Select_PC_FETCH: BIT; signal Return_SRAM_FETCH: BIT; -- Used by the SETAB opcode signal Load_A_From_DataBus_SETAB: BIT; signal Load_B_From_DataBus_SETAB: BIT; -- Used by the ALU opcode signal Load_C_From_DataBus_ALU: BIT; signal Load_Flags_From_ALU: BIT; -- Used by the MOV opcode signal Select_D_To_DataBus_MOV: BIT; signal Select_E_To_DataBus_MOV: BIT; signal Select_F_To_DataBus_MOV: BIT; signal Select_G_To_DataBus_MOV: BIT; signal Select_H_To_DataBus_MOV: BIT; signal Select_SP_To_DataBus_MOV: BIT; signal Select_XL_To_DataBus_MOV: BIT; signal Select_XH_To_DataBus_MOV: BIT; signal Load_D_From_DataBus_MOV: BIT; signal Load_E_From_DataBus_MOV: BIT; signal Load_F_From_DataBus_MOV: BIT; signal Load_G_From_DataBus_MOV: BIT; signal Load_H_From_DataBus_MOV: BIT; signal Load_SP_From_DataBus_MOV: BIT; signal Load_XL_From_DataBus_MOV: BIT; signal Load_XH_From_DataBus_MOV: BIT; signal Load_J_From_DataBus_MOV: BIT; -- Used by the MOV16 opcode signal Select_M_To_AddressBus_MOV16: BIT; signal Select_X_To_AddressBus_MOV16: BIT; signal Load_M_From_AddressBus_MOV16: BIT; signal Load_X_From_AddressBus_MOV16: BIT; signal Select_J_To_AddressBus_MOV16: BIT; signal Load_J_From_AddressBus_MOV16: BIT; signal Select_SP_To_AddressBus_MOV16: BIT; signal Load_SP_From_AddressBus_MOV16: BIT; signal Select_PC_To_AddressBus_MOV16: BIT; signal Load_PC_From_AddressBus_MOV16: BIT; signal Select_BP_To_AddressBus_MOV16: BIT; signal Load_BP_From_AddressBus_MOV16: BIT; signal Select_Y_To_AddressBus_MOV16: BIT; signal Load_Y_From_AddressBus_MOV16: BIT; signal Select_Z_To_AddressBus_MOV16: BIT; signal Load_Z_From_AddressBus_MOV16: BIT; -- Used by the LOAD opcode signal Select_SRAM_LOAD: BIT; signal Return_SRAM_LOAD: BIT; signal Load_D_From_DataBus_LOAD: BIT; signal Load_E_From_DataBus_LOAD: BIT; signal Load_F_From_DataBus_LOAD: BIT; signal Load_G_From_DataBus_LOAD: BIT; signal Load_H_From_DataBus_LOAD: BIT; signal Load_XL_From_DataBus_LOAD: BIT; signal Load_XH_From_DataBus_LOAD: BIT; signal Select_M_To_AddressBus_LOAD: BIT; -- Used by the STORE opcode signal Load_SRAM_LOAD: BIT; signal Select_D_To_DataBus_STORE: BIT; signal Select_E_To_DataBus_STORE: BIT; signal Select_F_To_DataBus_STORE: BIT; signal Select_G_To_DataBus_STORE: BIT; signal Select_H_To_DataBus_STORE: BIT; signal Select_XL_To_DataBus_STORE: BIT; signal Select_XH_To_DataBus_STORE: BIT; signal Select_M_To_AddressBus_STORE: BIT; signal Load_SRAM_STORE: BIT; -- Used by the LOAD_FLAGS opcode signal Load_SRAM_STORE_FLAGS: BIT; signal Select_M_To_AddressBus_STORE_FLAGS: BIT; -- Used by the STORE_FLAGS opcode signal Select_SRAM_LOAD_FLAGS: BIT; signal Select_M_To_AddressBus_LOAD_FLAGS: BIT; signal Return_SRAM_LOAD_FLAGS: BIT; -- Used by the JMP opcode signal Load_PC_JMP: BIT; signal Select_J_To_AddressBus_JMP: BIT; -- Used by the JZ opcode signal Load_PC_JZ: BIT; signal Select_J_To_AddressBus_JZ: BIT; signal Select_Flags_JZ: BIT; -- Used by the JNS opcode signal Load_PC_JNS: BIT; signal Select_J_To_AddressBus_JNS: BIT; signal Select_Flags_JNS: BIT; -- Used by the JNC opcode signal Load_PC_JNC: BIT; signal Select_J_To_AddressBus_JNC: BIT; signal Select_Flags_JNC: BIT; -- Used by the JNZ opcode signal Load_PC_JNZ: BIT; signal Select_J_To_AddressBus_JNZ: BIT; signal Select_Flags_JNZ: BIT; -- Used by the SAVE_FLAGS opcode signal Select_Flags_SAVE_FLAGS: BIT; -- Used by the RESTORE_FLAGS opcode signal Load_Flags_SAVE_FLAGS: BIT; -- Used by the INBUFFER_TO_FLAGS opcode signal Load_Flags_INBUFFER_TO_FLAGS: BIT; -- Used by the FLAGS_TO_DATABUS opcode signal Select_Flags_FLAGS_TO_OUTBUFFER: BIT; -- Used by the MOV_ALU_IN opcode signal Select_D_To_DataBus_MOV_ALU_IN: BIT; signal Select_E_To_DataBus_MOV_ALU_IN: BIT; signal Select_F_To_DataBus_MOV_ALU_IN: BIT; signal Select_G_To_DataBus_MOV_ALU_IN: BIT; signal Select_H_To_DataBus_MOV_ALU_IN: BIT; signal Select_XL_To_DataBus_MOV_ALU_IN: BIT; signal Select_XH_To_DataBus_MOV_ALU_IN: BIT; signal Select_SP_To_DataBus_MOV_ALU_IN: BIT; signal Load_A_From_DataBus_MOV_ALU_IN: BIT; signal Load_B_From_DataBus_MOV_ALU_IN: BIT; signal MOV_ALU_IN_SourceRegister: BIT_VECTOR(7 downto 0); -- Used by the MOV_ALU_OUT opcode signal Load_D_From_DataBus_MOV_ALU_OUT: BIT; signal Load_E_From_DataBus_MOV_ALU_OUT: BIT; signal Load_F_From_DataBus_MOV_ALU_OUT: BIT; signal Load_G_From_DataBus_MOV_ALU_OUT: BIT; signal Load_H_From_DataBus_MOV_ALU_OUT: BIT; signal Load_XL_From_DataBus_MOV_ALU_OUT: BIT; signal Load_XH_From_DataBus_MOV_ALU_OUT: BIT; signal Load_SP_From_DataBus_MOV_ALU_OUT: BIT; signal Load_J_From_DataBus_MOV_ALU_OUT: BIT; signal Select_C_To_DataBus_MOV_ALU_OUT: BIT; signal MOV_ALU_OUT_DestinationRegister: BIT_VECTOR(7 downto 0); -- Used by the MOV_ALU_C_TO_AB opcode signal Load_A_From_DataBus_MOV_ALU_C_TO_AB: BIT; signal Load_B_From_DataBus_MOV_ALU_C_TO_AB: BIT; signal Select_C_To_DataBus_MOV_ALU_C_TO_AB: BIT; -- Used by the ADDER_16BIT opcode signal Select_D_To_DataBus_ADDER_16BIT: BIT; signal Select_X_To_AddressBus_ADDER_16BIT: BIT; signal Load_X_From_AddressBus_ADDER_16BIT: BIT; signal Select_J_To_AddressBus_ADDER_16BIT: BIT; -- Used by the IN opcode signal Load_XL_From_DataBus_IN: BIT; -- Used by the OUT opcode signal Select_XL_To_DataBus_OUT: BIT; begin -- Negate the instruction, so that we can afterwards probe -- for a specific instruction NegatedInstruction <= not(Instruction); -- Negate the FLAGS NegatedFlags <= not(Flags); -- ================================================================ -- The following section implements the Fetch/Increment operations -- ================================================================ Load_PC_FETCH <= TimingSignals(2); -- State #3 Select_PC_FETCH <= TimingSignals(0) or -- State #1 TimingSignals(1); -- State #2 -- We request the data from the RAM in the states #1 and #2 Select_SRAM_FETCH <= TimingSignals(0) or -- State #1 TimingSignals(1); -- State #2 -- Because the RAM has a latency of 1 clock cycle, we only return the -- requested data from the RAM in state #2 (data in state #1 is still unstable!!!) Return_SRAM_FETCH <= TimingSignals(1); -- State #2 Load_INC <= TimingSignals(0); -- State #1 Select_INC <= TimingSignals(2); -- State #3 Load_INSTR <= TimingSignals(1); -- State #2 -- ============================================================ -- Now we have to decode the instruction to enable the correct -- Control Lines based on the provided timing signal -- ============================================================ -- --------------------------------------- -- Instruction "SETAB" - Format: 111DVVVV -- --------------------------------------- -- 111: OpCode -- D: Destination ('0' = Register A, '1' = Register B) -- VVVV: 4-bit value -- Check if we execute the "SETAB" instruction - OpCode "111" instruction_SETAB <= Instruction(7) and Instruction(6) and Instruction(5); -- The "Select_INSTR" control line goes high, when we execute the -- instruction "SETAB" and the time state is #4 -- This gates the instruction from the instruction register onto the data bus Select_INSTR_To_DataBus <= instruction_SETAB and TimingSignals(3); -- The instruction from the data bus is loaded into the register "Internal A" Load_InternalA_From_DataBus <= instruction_SETAB and TimingSignals(3); -- The first 4 bits from the register "Internal A" are gated back to the data bus Select_InternalA_To_DataBus <= instruction_SETAB and TimingSignals(4); -- The "Load_A" control line goes high, when we execute the -- instruction "SETAB" and the time state is #4 -- This loads the data currently stored on the data bus into the Register "A" Load_A_From_DataBus_SETAB <= instruction_SETAB and TimingSignals(4) and NegatedInstruction(4); -- The "Load_B" control line goes high, when we execute the -- instruction "SETAB" and the time state is #4 -- This loads the data currently stored on the data bus into the Register "B" Load_B_From_DataBus_SETAB <= instruction_SETAB and TimingSignals(4) and Instruction(4); -- --------------------------------------- -- Instruction "ALU" - Format: 1000FFFF -- --------------------------------------- -- 1000: OpCode -- FFFF: 4-bit function code -- Check if we execute the "ALU" instruction - OpoCode "1000" instruction_ALU <= Instruction(7) and NegatedInstruction(6) and NegatedInstruction(5) and NegatedInstruction(4); instruction_NOP <= NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- The "Select_A_To_ALU" and "Select_B_To_ALU" control lines are going high, when we execute -- the instruction "ALU" and the time state is #4 or #5. -- This transfers the content of the Register A and Register B into the ALU -- for execution. Select_A_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4)); Select_B_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4)); -- The "SELECT_INSTR" control line goes high, when we execute the instruction "ALU" -- and the time state is #4 or #5. -- This transfers the 4-bit function code of the Instruction Register into the ALU -- for execution. Select_INSTR_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4)); -- The "Select C" control line goes high, when we execute the instruction -- "ALU" and the time state is #5. -- This transfers the result of the ALU into the Register C. Load_C_From_DataBus_ALU <= instruction_ALU and TimingSignals(4); -- This transfers the result of the ALU Flags into the register FLAGS Load_Flags_From_ALU <= instruction_ALU and TimingSignals(4) and not(instruction_NOP); -- ------------------------------------------------- -- Instruction "MOV_ALU_C_TO_AB" - Format: 1010111D -- ------------------------------------------------- -- 1010111: OpCode -- D: Destination Register -- => "0": Register A -- => "1": Register B -- Check if we execute the "MOV_ALU_OUT" instruction - OpCode "1010111" instruction_MOV_ALU_C_TO_AB <= Instruction(7) and NegatedInstruction(6) and Instruction(5) and NegatedInstruction(4) and Instruction(3) and Instruction(2) and Instruction(1); Load_A_From_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); Load_B_From_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and Instruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the register C of the ALU to the data bus Select_C_To_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and (TimingSignals(4) or TimingSignals(5)); -- -------------------------------------------- -- Instruction "MOV_ALU_OUT" - Format: 11011DDD -- -------------------------------------------- -- 11011: OpCode -- DDD: Destination Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not yet used> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "MOV_ALU_OUT" instruction - OpCode "11011" instruction_MOV_ALU_OUT <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and Instruction(4) and Instruction(3); -- Decode the destination and source register from the provided instruction DestinationRegisterDecoder_MOV_ALU_OUT: Decoder3to8 port map(Instruction(2 downto 0), MOV_ALU_OUT_DestinationRegister, '1'); -- Load the specified register from the data bus Load_D_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(0) and (TimingSignals(4) or TimingSignals(5)); Load_E_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(1) and (TimingSignals(4) or TimingSignals(5)); Load_F_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(2) and (TimingSignals(4) or TimingSignals(5)); Load_G_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(3) and (TimingSignals(4) or TimingSignals(5)); Load_H_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(4) and (TimingSignals(4) or TimingSignals(5)); Load_XL_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(6) and (TimingSignals(4) or TimingSignals(5)); Load_XH_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(7) and (TimingSignals(4) or TimingSignals(5)); -- Select the register C of the ALU to the data bus Select_C_To_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and (TimingSignals(4) or TimingSignals(5)); -- -------------------------------------------- -- Instruction "MOV_ALU_IN" - Format: 1011DSSS -- -------------------------------------------- -- 1011: OpCode -- D: Destination Register -- => "0": Register A -- => "1": Register B -- SSS: Source Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not yet used> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "MOV_ALU_IN" instruction - OpCode "1011" instruction_MOV_ALU_IN <= Instruction(7) and NegatedInstruction(6) and Instruction(5) and Instruction(4); -- Decode the destination and source register from the provided instruction SourceRegisterDecoder_MOV_ALU_IN: Decoder3to8 port map(Instruction(2 downto 0), MOV_ALU_IN_SourceRegister, '1'); -- Latch the specified register onto the data bus Select_D_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5)); Select_E_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5)); Select_F_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5)); Select_G_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5)); Select_H_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5)); Select_XL_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5)); Select_XH_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5)); -- Load the specified register from the data bus Load_A_From_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and NegatedInstruction(3) and TimingSignals(4); Load_B_From_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and Instruction(3) and TimingSignals(4); -- --------------------------------------- -- Instruction "MOV" - Format: 00DDDSSS -- --------------------------------------- -- 00: OpCode -- DDD: Destination Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not yet used> -- => "110": Register XL -- => "111": Register XH -- SSS: Source Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not yet used> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "MOV" instruction - OpCode "00" instruction_MOV <= NegatedInstruction(7) and NegatedInstruction(6); -- Decode the destination and source register from the provided instruction DestinationRegisterDecoder: Decoder3to8 port map(Instruction(5 downto 3), MOV_DestinationRegister, '1'); SourceRegisterDecoder: Decoder3to8 port map(Instruction(2 downto 0), MOV_SourceRegister, '1'); -- Gate the specified register onto the data bus Select_D_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5)); Select_E_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5)); Select_F_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5)); Select_G_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5)); Select_H_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5)); Select_XL_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5)); Select_XH_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5)); -- Load the specified register from the data bus Load_D_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(0) and TimingSignals(4); Load_E_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(1) and TimingSignals(4); Load_F_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(2) and TimingSignals(4); Load_G_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(3) and TimingSignals(4); Load_H_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(4) and TimingSignals(4); Load_XL_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(6) and TimingSignals(4); Load_XH_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(7) and TimingSignals(4); -- --------------------------------------- -- Instruction "MOV16" - Format: 01DDDSSS -- --------------------------------------- -- 01: OpCode -- DDD: Destination Register -- => "000": Register M -- => "001": Register X -- => "010": Register J -- => "011": Register SP -- => "100": Register PC -- => "101": Register BP -- => "110": Register Y -- => "111": Register Z -- SSS: Source Register -- => "000": Register M -- => "001": Register X -- => "010": Register J -- => "011": Register SP -- => "100": Register PC -- => "101": Register BP -- => "110": Register Y -- => "111": Register Z -- Check if we execute the "MOV16" instruction - OpCode "01" instruction_MOV16 <= NegatedInstruction(7) and Instruction(6); -- Decode the destination and source register from the provided instruction DestinationRegisterDecoderMOV16: Decoder3to8 port map(Instruction(5 downto 3), MOV16_DestinationRegister, '1'); SourceRegisterDecoderMOV16: Decoder3to8 port map(Instruction(2 downto 0), MOV16_SourceRegister, '1'); -- Gate the specified register onto the data bus Select_M_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5)); Select_X_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5)); Select_J_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5)); Select_SP_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5)); Select_PC_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5)); Select_BP_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(5) and (TimingSignals(4) or TimingSignals(5)); Select_Y_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5)); Select_Z_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5)); -- Load the specified register from the data bus Load_M_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(0) and TimingSignals(4); Load_X_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(1) and TimingSignals(4); Load_J_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(2) and TimingSignals(4); Load_SP_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(3) and TimingSignals(4); Load_PC_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(4) and TimingSignals(4); Load_BP_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(5) and TimingSignals(4); Load_Y_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(6) and TimingSignals(4); Load_Z_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(7) and TimingSignals(4); -- ------------------------------------- -- Instruction "HLT" - Format: 11000011 -- ------------------------------------- -- Stops the execution of the CPU. -- 11010011: OpCode -- Check if we execute the "HLT" instruction - OpCode "11010011" instruction_HLT <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and Instruction(1) and Instruction(0); -- Stops the CPU execution StopCPU <= instruction_HLT; -- --------------------------------------- -- Instruction "LOAD" - Format: 10010DDD -- --------------------------------------- -- Loads a 8-bit value from SRAM memory into the specified register. -- The SRAM memory address is stored in the register "M". -- The transfer of the data to the register from the SRAM memory is done through the data bus. -- 10010: OpCode -- DDD: Destination Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not used...> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "LOAD" instruction - OpCode "10010" instruction_LOAD <= Instruction(7) and NegatedInstruction(6) and NegatedInstruction(5) and Instruction(4) and NegatedInstruction(3); -- Latch the SRAM memory address from register M onto the address bus Select_M_To_AddressBus_LOAD <= instruction_LOAD and (TimingSignals(4) or TimingSignals(5)); -- Request the 8-bit from the RAM memory in the states #5, #6, and #7 Select_SRAM_LOAD <= instruction_LOAD and (TimingSignals(4) or TimingSignals(5) or TimingSignals(6)); -- Because the RAM has a latency of 1 clock cycle, we only return the -- requested data from the RAM in state #7 (data in state #5, #6 is still unstable!!!) -- This finally places the requested RAM data onto the data bus Return_SRAM_LOAD <= TimingSignals(6); -- State #7 -- Load the Register D from the data bus Load_D_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- Load the Register E from the data bus Load_E_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0); -- Load the Register F from the data bus Load_F_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and NegatedInstruction(2) and Instruction(1) and NegatedInstruction(0); -- Load the Register G from the data bus Load_G_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and NegatedInstruction(2) and Instruction(1) and Instruction(0); -- Load the Register H from the data bus Load_H_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and Instruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- Load the Register XL from the data bus Load_XL_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and Instruction(2) and Instruction(1) and NegatedInstruction(0); -- Load the Register XL from the data bus Load_XH_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and Instruction(2) and Instruction(1) and Instruction(0); -- --------------------------------------- -- Instruction "STORE" - Format: 10011SSS -- --------------------------------------- -- Save a 8-bit value to SRAM memory from the specified register. -- The SRAM memory address is stored in the register "M". -- The transfer of the data from the register into the SRAM memory is done through the data bus. -- 10011: OpCode -- SSS: Source Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not used...> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "STORE" instruction - OpCode "10011" instruction_STORE <= Instruction(7) and NegatedInstruction(6) and NegatedInstruction(5) and Instruction(4) and Instruction(3); -- Selects the content of the register "M" onto the address bus Select_M_To_AddressBus_STORE <= instruction_STORE and (TimingSignals(4) or TimingSignals(5)); -- Select the Register D to the data bus Select_D_To_DataBus_STORE <= instruction_STORE and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register E to the data bus Select_E_To_DataBus_STORE <= instruction_STORE and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register F to the data bus Select_F_To_DataBus_STORE <= instruction_STORE and NegatedInstruction(2) and Instruction(1) and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register G to the data bus Select_G_To_DataBus_STORE <= instruction_STORE and NegatedInstruction(2) and Instruction(1) and Instruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register H to the data bus Select_H_To_DataBus_STORE <= instruction_STORE and Instruction(2) and NegatedInstruction(1) and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register XL to the data bus Select_XL_To_DataBus_STORE <= instruction_STORE and Instruction(2) and Instruction(1) and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register XH to the data bus Select_XH_To_DataBus_STORE <= instruction_STORE and Instruction(2) and Instruction(1) and Instruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Enables the Load Line of the RAM memory and transfers the data from the data bus into -- the memory address provided in register M Load_SRAM_STORE <= instruction_STORE and TimingSignals(5); -- --------------------------------------------- -- Instruction "STORE_FLAGS" - Format: 11001001 -- --------------------------------------------- -- Selects the flags from the "FlagsOutBuffer" register onto the data bus -- and stores it in the RAM. -- 11001001: OpCode -- Check if we execute the "STORE_FLAGS" instruction - OpCode "11001001" instruction_STORE_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0); -- Selects the content of the register "M" onto the address bus Select_M_To_AddressBus_STORE_FLAGS <= instruction_STORE_FLAGS and (TimingSignals(4) or TimingSignals(5)); -- Selects the flags from the "FlagsOutBuffer" onto the data bus Select_FlagsToDataBus <= instruction_STORE_FLAGS and (TimingSignals(4) or TimingSignals(5)); -- Enables the Load Line of the RAM memory and transfers the data from the data bus into -- the memory address provided in register M Load_SRAM_STORE_FLAGS <= instruction_STORE_FLAGS and TimingSignals(5); -- --------------------------------------------- -- Instruction "LOAD_FLAGS" - Format: 11001010 -- --------------------------------------------- -- Loads the flags from the RAM and writes them into the "FlagsInBuffer" register. -- and stores it onto the stack -- 11001010: OpCode -- Check if we execute the "STORE_FLAGS" instruction - OpCode "11001010" instruction_LOAD_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and NegatedInstruction(2) and Instruction(1) and NegatedInstruction(0); -- Latch the SRAM memory address from register M onto the address bus Select_M_To_AddressBus_LOAD_FLAGS <= instruction_LOAD_FLAGS and (TimingSignals(4) or TimingSignals(5)); -- Request the 8-bit from the RAM memory in the states #5, #6, and #7 Select_SRAM_LOAD_FLAGS <= instruction_LOAD_FLAGS and (TimingSignals(4) or TimingSignals(5) or TimingSignals(6)); -- Because the RAM has a latency of 1 clock cycle, we only return the -- requested data from the RAM in state #7 (data in state #5, #6 is still unstable!!!) -- This finally places the requested RAM data onto the data bus Return_SRAM_LOAD_FLAGS <= TimingSignals(6); -- State #7 -- Selects the flags from the "FlagsOutBuffer" onto the data bus Load_FlagsFromDataBus <= instruction_LOAD_FLAGS and TimingSignals(6); -- --------------------------------------- -- Instruction "JMP" - Format: 11000010 -- --------------------------------------- -- Unconditional jump to the address in the program code that is stored in the register "J". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11000010: OpCode -- Check if we execute the "JMP" instruction - OpCode "11000010" instruction_JMP <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and Instruction(1) and NegatedInstruction(0); -- Select the target jump address to the address bus Select_J_To_AddressBus_JMP <= instruction_JMP and (TimingSignals(4) or TimingSignals(5)); -- Load the Program Counter from the address bus Load_PC_JMP <= instruction_JMP and TimingSignals(5); -- -------------------------------------------- -- Instruction "SAVE_FLAGS" - Format: 11000100 -- -------------------------------------------- -- Saves the current content of the flags register into the "SavedFlags" register -- 11000100: OpCode -- Check if we execute the "SAVE_FLAGS" instruction - OpCode "11000100" instruction_SAVE_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and Instruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- Enables the Select Line of the flags register to load the flags into the "SavedFlags" register Select_Flags_SAVE_FLAGS <= instruction_SAVE_FLAGS and TimingSignals(4); -- Enables the Load Line of the "SavedFlags" register to load the flags into the "SavedFlags" register Load_FlagsSaved_From_FlagsRegister <= instruction_SAVE_FLAGS and TimingSignals(4); -- ----------------------------------------------- -- Instruction "RESTORE_FLAGS" - Format: 11000101 -- ----------------------------------------------- -- Saves the current content of the flags register into the "SavedFlags" register -- 11000101: OpCode -- Check if we execute the "RESTORE_FLAGS" instruction - OpCode "11000101" instruction_RESTORE_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and Instruction(2) and NegatedInstruction(1) and Instruction(0); -- Enables the Load Line of the flags register to load the "SavedFlags" register into the flags register Load_Flags_SAVE_FLAGS <= instruction_RESTORE_FLAGS and TimingSignals(4); -- Enables the Select Line of the "SavedFlags" register to load the "SavedFlags" register into the flags register Load_FlagsSaved_To_FlagsRegister <= instruction_RESTORE_FLAGS and TimingSignals(4); -- ---------------------------------------------------- -- Instruction "FLAGS_TO_OUTBUFFER" - Format: 11000110 -- ---------------------------------------------------- -- Writes the current content of the flags register onto the data bus -- 11000110: OpCode -- Check if we execute the "FLAGS_TO_OUTBUFFER" instruction - OpCode "11000110" instruction_FLAGS_TO_OUTBUFFER <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and Instruction(2) and Instruction(1) and NegatedInstruction(0); -- Selects the content from the Flags register onto the Flags Bus Select_Flags_FLAGS_TO_OUTBUFFER <= instruction_FLAGS_TO_OUTBUFFER and TimingSignals(4); -- Loads the content from the Flags Bus into the "FlagsOutBuffer" register Load_FlagsFromFlagsBus <= instruction_FLAGS_TO_OUTBUFFER and TimingSignals(4); -- --------------------------------------------------- -- Instruction "INBUFFER_TO_FLAGS" - Format: 11000111 -- --------------------------------------------------- -- Writes the current content of the flags register onto the data bus -- 11000111: OpCode -- Check if we execute the "FLAGS_TO_INBUFFER" instruction - OpCode "11000111" instruction_INBUFFER_TO_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and Instruction(2) and Instruction(1) and Instruction(0); -- Selects the content from the "FlagsInBuffer" register to the Flags Bus Select_FlagsToFlagsBus <= instruction_INBUFFER_TO_FLAGS and TimingSignals(4); -- Loads the content from the Flags Bus into the Flags register Load_Flags_INBUFFER_TO_FLAGS <= instruction_INBUFFER_TO_FLAGS and TimingSignals(4); -- --------------------------------------- -- Instruction "JZ" - Format: 11000000 -- --------------------------------------- -- Conditional jump to the address in the program code that is stored in the register "J". -- The jump is only executed if the Zero-Flag in the FLAGS register is set to "1". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11000000: OpCode -- Check if we execute the "JZ" instruction - OpCode "11000000" instruction_JZ <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0); Select_Flags_JZ <= instruction_JZ and (TimingSignals(5) or TimingSignals(6) or TimingSignals(7)); -- Select the target jump address to the address bus Select_J_To_AddressBus_JZ <= instruction_JZ and Flags(1) and (TimingSignals(6) or TimingSignals(7)); -- Load the Program Counter from the address bus Load_PC_JZ <= instruction_JZ and Flags(1) and TimingSignals(7); -- --------------------------------------- -- Instruction "JNS" - Format: 11001011 -- --------------------------------------- -- Conditional jump to the address in the program code that is stored in the register "J". -- The jump is only executed if the Sign-Flag in the FLAGS register is set to "0". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11001011: OpCode -- Check if we execute the "JNS" instruction - OpCode "11001011" instruction_JNS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and NegatedInstruction(2) and Instruction(1) and Instruction(0); Select_Flags_JNS <= instruction_JNS and (TimingSignals(5) or TimingSignals(6) or TimingSignals(7)); -- Select the target jump address to the address bus Select_J_To_AddressBus_JNS <= instruction_JNS and (not Flags(0)) and (TimingSignals(6) or TimingSignals(7)); -- Load the Program Counter from the address bus Load_PC_JNS <= instruction_JNS and (not Flags(0)) and TimingSignals(7); -- --------------------------------------- -- Instruction "JNC" - Format: 11010001 -- --------------------------------------- -- Conditional jump to the address in the program code that is stored in the register "J". -- The jump is only executed if the Carry-Flag in the FLAGS register is set to "0". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11001011: OpCode -- Check if we execute the "JNC" instruction - OpCode "11010001" instruction_JNC <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and Instruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0); Select_Flags_JNC <= instruction_JNC and (TimingSignals(5) or TimingSignals(6) or TimingSignals(7)); -- Select the target jump address to the address bus Select_J_To_AddressBus_JNC <= instruction_JNC and (not Flags(2)) and (TimingSignals(6) or TimingSignals(7)); -- Load the Program Counter from the address bus Load_PC_JNC <= instruction_JNC and (not Flags(2)) and TimingSignals(7); -- --------------------------------------- -- Instruction "JNZ" - Format: 11000001 -- --------------------------------------- -- Conditional jump to the address in the program code that is stored in the register "J". -- The jump is only executed if the Zero-Flag in the FLAGS register is set to "0". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11000001: OpCode -- Check if we execute the "JNZ" instruction - OpCode "11000001" instruction_JNZ <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0); Select_Flags_JNZ <= instruction_JNZ and (TimingSignals(5) or TimingSignals(6) or TimingSignals(7)); -- Select the target jump address to the address bus Select_J_To_AddressBus_JNZ <= instruction_JNZ and NegatedFlags(1) and (TimingSignals(6) or TimingSignals(7)); -- Load the Program Counter from the address bus Load_PC_JNZ <= instruction_JNZ and NegatedFlags(1) and TimingSignals(7); -- --------------------------------------------- -- Instruction "16BIT_ADDER" - Format: 11001000 -- --------------------------------------------- -- Performs a 16-bit addition between the 16-bit value in register "X" and the -- 8-bit value in register "D". -- The result of the addition is put back into register "X". -- 11001000: OpCode -- Check if we execute the "16BIT_ADDER" instruction - OpCode "11001000" instruction_ADDER_16BIT <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- Select the content of register "X" to the address bus Select_X_To_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and TimingSignals(3); -- Load the A input of the 16-bit Adder from the address bus Load_Adder16Bit_InputA <= instruction_ADDER_16BIT and TimingSignals(3); -- Select the content of register "J" to the address bus Select_J_To_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and TimingSignals(4); -- Load the B input of the 16-bit Adder from the address bus Load_Adder16Bit_InputB <= instruction_ADDER_16BIT and TimingSignals(4); -- Select the A input into the 16-bit Adder Select_Adder16Bit_InputA <= instruction_ADDER_16BIT and (TimingSignals(5) or TimingSignals(6)); -- Select the B input into the 16-bit Adder Select_Adder16Bit_InputB <= instruction_ADDER_16BIT and (TimingSignals(5) or TimingSignals(6)); -- Load the output from the 16-bit adder into the C output Load_Adder16Bit_OutputC <= instruction_ADDER_16BIT and TimingSignals(6); -- Select the output from the C output onto the address bus Select_Adder16Bit_OutputC <= instruction_ADDER_16BIT and TimingSignals(7); -- Load the content from the address bus into the register "X" Load_X_From_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and TimingSignals(7); -- --------------------------------------------- -- Instruction "IN" - Format: 1100110P -- --------------------------------------------- -- Reads from the specified input port and places the read value into the specified register. -- 1100110P: OpCode -- P: Port - "0" -> Input Port A, "1" -> Input Port B -- Check if we execute the "IN" instruction - OpCode "1101" instruction_IN <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and Instruction(2) and NegatedInstruction(1); -- Select the input value from Input Port A to the data bus Select_PortA_To_DataBus <= instruction_IN and NegatedInstruction(0) and (TimingSignals(3) or TimingSignals(4)); -- Select the input value from Input Port B to the data bus Select_PortB_To_DataBus <= instruction_IN and Instruction(0) and (TimingSignals(3) or TimingSignals(4)); -- Load the Register XL from the data bus Load_XL_From_DataBus_IN <= instruction_IN and TimingSignals(4); -- --------------------------------------------- -- Instruction "OUT" - Format: 1100111P -- --------------------------------------------- -- Reads from the specified input port and places the read value into the specified register. -- 1100111P: OpCode -- P: Port - "0" -> Output Port C, "1" -> Output Port D -- Check if we execute the "IN" instruction - OpCode "1100111" instruction_OUT <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and Instruction(2) and Instruction(1); -- Select the register XL to the data bus Select_XL_To_DataBus_OUT <= instruction_OUT and (TimingSignals(3) or TimingSignals(4)); -- Select the output value from the data bus into the Output Port C Load_PortC_From_DataBus <= instruction_OUT and NegatedInstruction(0) and TimingSignals(4); -- Select the output value from the data bus into the Output Port D Load_PortD_From_DataBus <= instruction_OUT and Instruction(0) and TimingSignals(4); -- ================================================================ -- The following section enables the final CPU control lines -- ================================================================ -- Enable/Disable Load Line of register A Load_A_From_DataBus <= Load_A_From_DataBus_SETAB or Load_A_From_DataBus_MOV_ALU_IN or Load_A_From_DataBus_MOV_ALU_C_TO_AB; -- Enable/Disable Load Line of register B Load_B_From_DataBus <= Load_B_From_DataBus_SETAB or Load_B_From_DataBus_MOV_ALU_IN or Load_B_From_DataBus_MOV_ALU_C_TO_AB; -- Enable/Disable Load Line of register C Load_C_From_DataBus <= Load_C_From_DataBus_ALU; -- Enable/Disable Load Line of register D Load_D_From_DataBus <= Load_D_From_DataBus_MOV_ALU_OUT or Load_D_From_DataBus_MOV or Load_D_From_DataBus_LOAD; -- Enable/Disable Load Line of register E Load_E_From_DataBus <= Load_E_From_DataBus_MOV_ALU_OUT or Load_E_From_DataBus_MOV or Load_E_From_DataBus_LOAD; -- Enable/Disable Load Line of register F Load_F_From_DataBus <= Load_F_From_DataBus_MOV_ALU_OUT or Load_F_From_DataBus_MOV or Load_F_From_DataBus_LOAD; -- Enable/Disable Load Line of register G Load_G_From_DataBus <= Load_G_From_DataBus_MOV_ALU_OUT or Load_G_From_DataBus_MOV or Load_G_From_DataBus_LOAD; -- Enable/Disable Load Line of register H Load_H_From_DataBus <= Load_H_From_DataBus_MOV_ALU_OUT or Load_H_From_DataBus_MOV or Load_H_From_DataBus_LOAD; -- Enable/Disable Load Line of register XL Load_XL_From_DataBus <= Load_XL_From_DataBus_MOV_ALU_OUT or Load_XL_From_DataBus_MOV or Load_XL_From_DataBus_LOAD or Load_XL_From_DataBus_IN; -- Enable/Disable Load Line of register XH Load_XH_From_DataBus <= Load_XH_From_DataBus_MOV_ALU_OUT or Load_XH_From_DataBus_MOV or Load_XH_From_DataBus_LOAD; -- Enable/Disable the Load Line of register M Load_M_From_AddressBus <= Load_M_From_AddressBus_MOV16; -- Enable/Disable the Load Line of register X Load_X_From_AddressBus <= Load_X_From_AddressBus_MOV16 or Load_X_From_AddressBus_ADDER_16BIT; -- Enable/Disable Load Line of register J Load_J_From_AddressBus <= Load_J_From_AddressBus_MOV16; -- Enable/Disable Load Line of register SP Load_SP_From_AddressBus <= Load_SP_From_AddressBus_MOV16; -- Enable/Disable Load Line of register BP Load_BP_From_AddressBus <= Load_BP_From_AddressBus_MOV16; -- Enable/Disable Load Line of register Y Load_Y_From_AddressBus <= Load_Y_From_AddressBus_MOV16; -- Enable/Disable Load Line of register Z Load_Z_From_AddressBus <= Load_Z_From_AddressBus_MOV16; -- Enable/Disable Select Line of register C Select_C_To_DataBus <= Select_C_To_DataBus_MOV_ALU_OUT or Select_C_To_DataBus_MOV_ALU_C_TO_AB; -- Enable/Disable Select Line of register D Select_D_To_DataBus <= Select_D_To_DataBus_MOV_ALU_IN or Select_D_To_DataBus_MOV or Select_D_To_DataBus_STORE or Select_D_To_DataBus_ADDER_16BIT; -- Enable/Disable Select Line of register E Select_E_To_DataBus <= Select_E_To_DataBus_MOV_ALU_IN or Select_E_To_DataBus_MOV or Select_E_To_DataBus_STORE; -- Enable/Disable Select Line of register F Select_F_To_DataBus <= Select_F_To_DataBus_MOV_ALU_IN or Select_F_To_DataBus_MOV or Select_F_To_DataBus_STORE; -- Enable/Disable Select Line of register G Select_G_To_DataBus <= Select_G_To_DataBus_MOV_ALU_IN or Select_G_To_DataBus_MOV or Select_G_To_DataBus_STORE; -- Enable/Disable Select Line of register H Select_H_To_DataBus <= Select_H_To_DataBus_MOV_ALU_IN or Select_H_To_DataBus_MOV or Select_H_To_DataBus_STORE; -- Enable/Disable Select Line of register XL Select_XL_To_DataBus <= Select_XL_To_DataBus_MOV_ALU_IN or Select_XL_To_DataBus_MOV or Select_XL_To_DataBus_STORE or Select_XL_To_DataBus_OUT; -- Enable/Disable Select Line of register XH Select_XH_To_DataBus <= Select_XH_To_DataBus_MOV_ALU_IN or Select_XH_To_DataBus_MOV or Select_XH_To_DataBus_STORE; -- Enable/Disable the Select Line of register M Select_M_To_AddressBus <= Select_M_To_AddressBus_MOV16 or Select_M_To_AddressBus_LOAD or Select_M_To_AddressBus_LOAD_FLAGS or Select_M_To_AddressBus_STORE or Select_M_To_AddressBus_STORE_FLAGS; -- Enable/Disable the Select Line of register X Select_X_To_AddressBus <= Select_X_To_AddressBus_MOV16 or Select_X_To_AddressBus_ADDER_16BIT or Select_X_To_AddressBus_ADDER_16BIT; -- Enable/Disable Select Line of register SP Select_SP_To_AddressBus <= Select_SP_To_AddressBus_MOV16; -- Enable/Disable Select Line of register BP Select_BP_To_AddressBus <= Select_BP_To_AddressBus_MOV16; -- Enable/Disable Select Line of register Y Select_Y_To_AddressBus <= Select_Y_To_AddressBus_MOV16; -- Enable/Disable Select Line of register Z Select_Z_To_AddressBus <= Select_Z_To_AddressBus_MOV16; -- Enable/Disable Select Line of register J Select_J_To_AddressBus <= Select_J_To_AddressBus_MOV16 or Select_J_To_AddressBus_JMP or Select_J_To_AddressBus_JZ or Select_J_To_AddressBus_JNS or Select_J_To_AddressBus_JNZ or Select_J_To_AddressBus_JNC or Select_J_To_AddressBus_ADDER_16BIT; -- Enables the Select Line of the flags register Select_Flags <= Select_Flags_JZ or Select_Flags_SAVE_FLAGS or Select_Flags_JNZ or Select_Flags_JNS or Select_Flags_JNC or Select_Flags_FLAGS_TO_OUTBUFFER; -- Enables the Load Line of the flags register Load_Flags <= Load_Flags_From_ALU or Load_Flags_SAVE_FLAGS or Load_Flags_INBUFFER_TO_FLAGS; -- Requests the data from the RAM to the data bus Select_SRAM <= Select_SRAM_FETCH or Select_SRAM_LOAD or Select_SRAM_LOAD_FLAGS; -- Loads the data from the data bus into the RAM Load_SRAM <= Load_SRAM_STORE or Load_SRAM_STORE_FLAGS; -- Returns the requested data from the RAM onto the data bus Return_SRAM <= Return_SRAM_FETCH or Return_SRAM_LOAD or Return_SRAM_LOAD_FLAGS; -- Enable/Disable the Load Line of the Program Counter Load_PC <= Load_PC_FETCH or Load_PC_JMP or Load_PC_JZ or Load_PC_JNS or Load_PC_JNZ or Load_PC_JNC or Load_PC_From_AddressBus_MOV16; -- Enable/Disable the Load Line of the Program Counter Select_PC <= Select_PC_FETCH or Select_PC_To_AddressBus_MOV16; end Behavioral;
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY char_7seg IS PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Display : OUT STD_LOGIC_VECTOR(0 TO 6)); END char_7seg; ARCHITECTURE Behavior OF char_7seg IS BEGIN -- Behavior Display(0) <= C(0); Display(1) <= NOT(C(1)) OR C(0); Display(2) <= C(0); Display(3) <= C(0); Display(4) <= C(1); Display(5) <= C(1); Display(6) <= NOT(C(1)) OR C(0); END Behavior;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc835.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c01s03b00x00p06n01i00835ent IS END c01s03b00x00p06n01i00835ent; ARCHITECTURE c01s03b00x00p06n01i00835arch OF c01s03b00x00p06n01i00835ent IS BEGIN TESTING: PROCESS BEGIN assert FALSE report "***FAILED TEST: c01s03b00x00p06n01i00835 - Simple name at beginning and end of configuration should be the same." severity ERROR; wait; END PROCESS TESTING; END c01s03b00x00p06n01i00835arch; configuration C of c01s03b00x00p06n01i00835ent is for c01s03b00x00p06n01i00835arch use WORK.all ; end for ; end C2; -- Failure_here -- ERROR: name given at the end must be the same as that given beginning.

------------------------------------------------------------------------------ -- Title : Wishbone Orbit Interlock Core ------------------------------------------------------------------------------ -- Author : Lucas Maziero Russo -- Company : CNPEM LNLS-DIG -- Created : 2022-06-12 -- Platform : FPGA-generic ------------------------------------------------------------------------------- -- Description: Wishbone wrapper for orbit interlock ------------------------------------------------------------------------------- -- Copyright (c) 2020 CNPEM -- Licensed under GNU Lesser General Public License (LGPL) v3.0 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2020-06-02 1.0 lucas.russo Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -- Main Wishbone Definitions use work.wishbone_pkg.all; -- Orbit interlock cores use work.orbit_intlk_pkg.all; -- BPM cores use work.bpm_cores_pkg.all; entity xwb_orbit_intlk is generic ( -- Wishbone g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC; g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD; g_WITH_EXTRA_WB_REG : boolean := false; -- Position g_ADC_WIDTH : natural := 16; g_DECIM_WIDTH : natural := 32 ); port ( ----------------------------- -- Clocks and resets ----------------------------- rst_n_i : in std_logic; clk_i : in std_logic; -- Wishbone clock ref_rst_n_i : in std_logic; ref_clk_i : in std_logic; ----------------------------- -- Wishbone signals ----------------------------- wb_slv_i : in t_wishbone_slave_in; wb_slv_o : out t_wishbone_slave_out; ----------------------------- -- Downstream ADC and position signals ----------------------------- fs_clk_ds_i : in std_logic; adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0'); adc_ds_swap_valid_i : in std_logic := '0'; decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_ds_pos_valid_i : in std_logic; ----------------------------- -- Upstream ADC and position signals ----------------------------- fs_clk_us_i : in std_logic; adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0'); adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0'); adc_us_swap_valid_i : in std_logic := '0'; decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0); decim_us_pos_valid_i : in std_logic; ----------------------------- -- Interlock outputs ----------------------------- intlk_trans_bigger_x_o : out std_logic; intlk_trans_bigger_y_o : out std_logic; -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_x_o : out std_logic; intlk_trans_bigger_ltc_y_o : out std_logic; intlk_trans_bigger_any_o : out std_logic; -- only cleared when intlk_trans_clr_i is asserted intlk_trans_bigger_ltc_o : out std_logic; -- conditional to intlk_trans_en_i intlk_trans_bigger_o : out std_logic; intlk_trans_smaller_x_o : out std_logic; intlk_trans_smaller_y_o : out std_logic; -- only cleared when intlk_trans_clr_i is asserted intlk_trans_smaller_ltc_x_o : out std_logic; intlk_trans_smaller_ltc_y_o : out std_logic; intlk_trans_smaller_any_o : out std_logic; -- only cleared when intlk_trans_clr_i is asserted intlk_trans_smaller_ltc_o : out std_logic; -- conditional to intlk_trans_en_i intlk_trans_smaller_o : out std_logic; intlk_ang_bigger_x_o : out std_logic; intlk_ang_bigger_y_o : out std_logic; intlk_ang_bigger_ltc_x_o : out std_logic; intlk_ang_bigger_ltc_y_o : out std_logic; intlk_ang_bigger_any_o : out std_logic; -- only cleared when intlk_ang_clr_i is asserted intlk_ang_bigger_ltc_o : out std_logic; -- conditional to intlk_ang_en_i intlk_ang_bigger_o : out std_logic; intlk_ang_smaller_x_o : out std_logic; intlk_ang_smaller_y_o : out std_logic; intlk_ang_smaller_ltc_x_o : out std_logic; intlk_ang_smaller_ltc_y_o : out std_logic; intlk_ang_smaller_any_o : out std_logic; -- only cleared when intlk_ang_clr_i is asserted intlk_ang_smaller_ltc_o : out std_logic; -- conditional to intlk_ang_en_i intlk_ang_smaller_o : out std_logic; -- only cleared when intlk_clr_i is asserted intlk_ltc_o : out std_logic; -- conditional to intlk_en_i intlk_o : out std_logic ); end xwb_orbit_intlk; architecture rtl of xwb_orbit_intlk is begin cmp_wb_orbit_intlk : wb_orbit_intlk generic map ( -- Wishbone g_INTERFACE_MODE => g_INTERFACE_MODE, g_ADDRESS_GRANULARITY => g_ADDRESS_GRANULARITY, g_WITH_EXTRA_WB_REG => g_WITH_EXTRA_WB_REG, -- Position g_ADC_WIDTH => g_ADC_WIDTH, g_DECIM_WIDTH => g_DECIM_WIDTH ) port map ( ----------------------------- -- Clocks and resets ----------------------------- rst_n_i => rst_n_i, clk_i => clk_i, ref_rst_n_i => ref_rst_n_i, ref_clk_i => ref_clk_i, ----------------------------- -- Wishbone signals ----------------------------- wb_adr_i => wb_slv_i.adr, wb_dat_i => wb_slv_i.dat, wb_dat_o => wb_slv_o.dat, wb_sel_i => wb_slv_i.sel, wb_we_i => wb_slv_i.we, wb_cyc_i => wb_slv_i.cyc, wb_stb_i => wb_slv_i.stb, wb_ack_o => wb_slv_o.ack, wb_stall_o => wb_slv_o.stall, ----------------------------- -- Downstream ADC and position signals ----------------------------- fs_clk_ds_i => fs_clk_ds_i, adc_ds_ch0_swap_i => adc_ds_ch0_swap_i, adc_ds_ch1_swap_i => adc_ds_ch1_swap_i, adc_ds_ch2_swap_i => adc_ds_ch2_swap_i, adc_ds_ch3_swap_i => adc_ds_ch3_swap_i, adc_ds_tag_i => adc_ds_tag_i, adc_ds_swap_valid_i => adc_ds_swap_valid_i, decim_ds_pos_x_i => decim_ds_pos_x_i, decim_ds_pos_y_i => decim_ds_pos_y_i, decim_ds_pos_q_i => decim_ds_pos_q_i, decim_ds_pos_sum_i => decim_ds_pos_sum_i, decim_ds_pos_valid_i => decim_ds_pos_valid_i, ----------------------------- -- Upstream ADC and position signals ----------------------------- fs_clk_us_i => fs_clk_us_i, adc_us_ch0_swap_i => adc_us_ch0_swap_i, adc_us_ch1_swap_i => adc_us_ch1_swap_i, adc_us_ch2_swap_i => adc_us_ch2_swap_i, adc_us_ch3_swap_i => adc_us_ch3_swap_i, adc_us_tag_i => adc_us_tag_i, adc_us_swap_valid_i => adc_us_swap_valid_i, decim_us_pos_x_i => decim_us_pos_x_i, decim_us_pos_y_i => decim_us_pos_y_i, decim_us_pos_q_i => decim_us_pos_q_i, decim_us_pos_sum_i => decim_us_pos_sum_i, decim_us_pos_valid_i => decim_us_pos_valid_i, ----------------------------- -- Interlock outputs ----------------------------- intlk_trans_bigger_x_o => intlk_trans_bigger_x_o, intlk_trans_bigger_y_o => intlk_trans_bigger_y_o, intlk_trans_bigger_ltc_x_o => intlk_trans_bigger_ltc_x_o, intlk_trans_bigger_ltc_y_o => intlk_trans_bigger_ltc_y_o, intlk_trans_bigger_any_o => intlk_trans_bigger_any_o, intlk_trans_bigger_ltc_o => intlk_trans_bigger_ltc_o, intlk_trans_bigger_o => intlk_trans_bigger_o, intlk_trans_smaller_x_o => intlk_trans_smaller_x_o, intlk_trans_smaller_y_o => intlk_trans_smaller_y_o, intlk_trans_smaller_ltc_x_o => intlk_trans_smaller_ltc_x_o, intlk_trans_smaller_ltc_y_o => intlk_trans_smaller_ltc_y_o, intlk_trans_smaller_any_o => intlk_trans_smaller_any_o, intlk_trans_smaller_ltc_o => intlk_trans_smaller_ltc_o, intlk_trans_smaller_o => intlk_trans_smaller_o, intlk_ang_bigger_x_o => intlk_ang_bigger_x_o, intlk_ang_bigger_y_o => intlk_ang_bigger_y_o, intlk_ang_bigger_ltc_x_o => intlk_ang_bigger_ltc_x_o, intlk_ang_bigger_ltc_y_o => intlk_ang_bigger_ltc_y_o, intlk_ang_bigger_any_o => intlk_ang_bigger_any_o, intlk_ang_bigger_ltc_o => intlk_ang_bigger_ltc_o, intlk_ang_bigger_o => intlk_ang_bigger_o, intlk_ang_smaller_x_o => intlk_ang_smaller_x_o, intlk_ang_smaller_y_o => intlk_ang_smaller_y_o, intlk_ang_smaller_ltc_x_o => intlk_ang_smaller_ltc_x_o, intlk_ang_smaller_ltc_y_o => intlk_ang_smaller_ltc_y_o, intlk_ang_smaller_any_o => intlk_ang_smaller_any_o, intlk_ang_smaller_ltc_o => intlk_ang_smaller_ltc_o, intlk_ang_smaller_o => intlk_ang_smaller_o, intlk_ltc_o => intlk_ltc_o, intlk_o => intlk_o ); end rtl;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity vga_axi_mem_buffer_v1_0 is generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Slave Bus Interface S_AXI C_S_AXI_ID_WIDTH : integer := 1; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 6; C_S_AXI_AWUSER_WIDTH : integer := 0; C_S_AXI_ARUSER_WIDTH : integer := 0; C_S_AXI_WUSER_WIDTH : integer := 0; C_S_AXI_RUSER_WIDTH : integer := 0; C_S_AXI_BUSER_WIDTH : integer := 0 ); port ( -- Users to add ports here -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Slave Bus Interface S_AXI s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awlen : in std_logic_vector(7 downto 0); s_axi_awsize : in std_logic_vector(2 downto 0); s_axi_awburst : in std_logic_vector(1 downto 0); s_axi_awlock : in std_logic; s_axi_awcache : in std_logic_vector(3 downto 0); s_axi_awprot : in std_logic_vector(2 downto 0); s_axi_awqos : in std_logic_vector(3 downto 0); s_axi_awregion : in std_logic_vector(3 downto 0); s_axi_awuser : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wlast : in std_logic; s_axi_wuser : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_buser : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arlen : in std_logic_vector(7 downto 0); s_axi_arsize : in std_logic_vector(2 downto 0); s_axi_arburst : in std_logic_vector(1 downto 0); s_axi_arlock : in std_logic; s_axi_arcache : in std_logic_vector(3 downto 0); s_axi_arprot : in std_logic_vector(2 downto 0); s_axi_arqos : in std_logic_vector(3 downto 0); s_axi_arregion : in std_logic_vector(3 downto 0); s_axi_aruser : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rlast : out std_logic; s_axi_ruser : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic ); end vga_axi_mem_buffer_v1_0; architecture arch_imp of vga_axi_mem_buffer_v1_0 is -- component declaration component vga_axi_mem_buffer_v1_0_S_AXI is generic ( C_S_AXI_ID_WIDTH : integer := 1; C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 6; C_S_AXI_AWUSER_WIDTH : integer := 0; C_S_AXI_ARUSER_WIDTH : integer := 0; C_S_AXI_WUSER_WIDTH : integer := 0; C_S_AXI_RUSER_WIDTH : integer := 0; C_S_AXI_BUSER_WIDTH : integer := 0 ); port ( S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWLEN : in std_logic_vector(7 downto 0); S_AXI_AWSIZE : in std_logic_vector(2 downto 0); S_AXI_AWBURST : in std_logic_vector(1 downto 0); S_AXI_AWLOCK : in std_logic; S_AXI_AWCACHE : in std_logic_vector(3 downto 0); S_AXI_AWPROT : in std_logic_vector(2 downto 0); S_AXI_AWQOS : in std_logic_vector(3 downto 0); S_AXI_AWREGION : in std_logic_vector(3 downto 0); S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WLAST : in std_logic; S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARLEN : in std_logic_vector(7 downto 0); S_AXI_ARSIZE : in std_logic_vector(2 downto 0); S_AXI_ARBURST : in std_logic_vector(1 downto 0); S_AXI_ARLOCK : in std_logic; S_AXI_ARCACHE : in std_logic_vector(3 downto 0); S_AXI_ARPROT : in std_logic_vector(2 downto 0); S_AXI_ARQOS : in std_logic_vector(3 downto 0); S_AXI_ARREGION : in std_logic_vector(3 downto 0); S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0); S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RLAST : out std_logic; S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic ); end component vga_axi_mem_buffer_v1_0_S_AXI; begin -- Instantiation of Axi Bus Interface S_AXI vga_axi_mem_buffer_v1_0_S_AXI_inst : vga_axi_mem_buffer_v1_0_S_AXI generic map ( C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_AWUSER_WIDTH => C_S_AXI_AWUSER_WIDTH, C_S_AXI_ARUSER_WIDTH => C_S_AXI_ARUSER_WIDTH, C_S_AXI_WUSER_WIDTH => C_S_AXI_WUSER_WIDTH, C_S_AXI_RUSER_WIDTH => C_S_AXI_RUSER_WIDTH, C_S_AXI_BUSER_WIDTH => C_S_AXI_BUSER_WIDTH ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWID => s_axi_awid, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWLEN => s_axi_awlen, S_AXI_AWSIZE => s_axi_awsize, S_AXI_AWBURST => s_axi_awburst, S_AXI_AWLOCK => s_axi_awlock, S_AXI_AWCACHE => s_axi_awcache, S_AXI_AWPROT => s_axi_awprot, S_AXI_AWQOS => s_axi_awqos, S_AXI_AWREGION => s_axi_awregion, S_AXI_AWUSER => s_axi_awuser, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WLAST => s_axi_wlast, S_AXI_WUSER => s_axi_wuser, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BID => s_axi_bid, S_AXI_BRESP => s_axi_bresp, S_AXI_BUSER => s_axi_buser, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARID => s_axi_arid, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARLEN => s_axi_arlen, S_AXI_ARSIZE => s_axi_arsize, S_AXI_ARBURST => s_axi_arburst, S_AXI_ARLOCK => s_axi_arlock, S_AXI_ARCACHE => s_axi_arcache, S_AXI_ARPROT => s_axi_arprot, S_AXI_ARQOS => s_axi_arqos, S_AXI_ARREGION => s_axi_arregion, S_AXI_ARUSER => s_axi_aruser, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RID => s_axi_rid, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RLAST => s_axi_rlast, S_AXI_RUSER => s_axi_ruser, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready ); -- Add user logic here -- User logic ends end arch_imp;

-- -- Authors: Francisco Paiva Knebel -- Gabriel Alexandre Zillmer -- -- Universidade Federal do Rio Grande do Sul -- Instituto de Informática -- Sistemas Digitais -- Prof. Fernanda Lima Kastensmidt -- -- Create Date: 10:44:10 05/03/2016 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; use IEEE.std_logic_arith.all; USE ieee.numeric_std.all; entity ula is Port ( X : in STD_LOGIC_VECTOR (7 downto 0); Y : in STD_LOGIC_VECTOR (7 downto 0); selector : in STD_LOGIC_VECTOR (2 downto 0); N : out STD_LOGIC; Z : out STD_LOGIC; output : out STD_LOGIC_VECTOR (7 downto 0); carryMUL: out STD_LOGIC_VECTOR (7 downto 0) -- need to make this save to address 100, add control unit state ); end ula; architecture Behavioral of ula is signal result : STD_LOGIC_VECTOR(7 downto 0); signal e1, e2 : STD_LOGIC_VECTOR(7 downto 0); signal MULTIPLICATION: STD_LOGIC_VECTOR(15 downto 0); begin e1 <= X; e2 <= Y; process(selector, e1, e2) begin -- 000 ADD -- 001 AND -- 010 OR -- 011 NOT -- 100 LDA -- 101 SHR -- 110 SHL -- 111 MUL case selector is when "000" => result <= e1 + e2; -- ADD when "001" => result <= e1 AND e2; -- AND when "010" => result <= e1 OR e2; -- OR when "011" => result <= not(e1); -- NOT when "100" => result <= e2; -- LDA when "101" => result <= "0" & e1(7 downto 1); -- SHR when "110" => result <= e1(6 downto 0) & "0"; -- SHL when "111" => MULTIPLICATION <= e1 * e2; -- MUL result <= MULTIPLICATION(7 downto 0); -- lsb when others => result <= e2; end case; -- Zero if(result = "00000000") then Z <= '1'; else Z <= '0'; end if; -- Negative N <= result(7); end process; carryMUL <= MULTIPLICATION(15 downto 8); output <= result; end Behavioral;

------------------------------------------------------------------------------- -- axi_master_lite_cntlr.vhd ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_master_lite_cntlr.vhd -- -- Description: -- -- This VHDL file is the design implementation for the Read/Write Controller -- that is part of the AXI Master Lite core. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_master_lite.vhd (v3_00_a) -- | -- |- axi_master_lite_cntlr.vhd -- | -- |- axi_master_lite_reset.vhd -- ------------------------------------------------------------------------------- -- Author: DET -- Revision: $Revision: 1.1.2.3 $ -- Date: $12/01/2010$ -- -- History: -- DET 12/01/2010 Initial Version -- -- DET 12/14/2010 Initial -- ~~~~~~ -- -- Per CR587090 -- - Removed the input port m_axi_rlast. It is not part of the AXI4-Lite -- signal set. -- ^^^^^^ -- -- DET 12/15/2010 Initial -- ~~~~~~ -- -- Per CR587194 -- - Fixed the Bus2IP_Error assertion logic. -- ^^^^^^ -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library proc_common_v3_00_a; Use proc_common_v3_00_a.proc_common_pkg.all; Use proc_common_v3_00_a.family_support.all; ------------------------------------------------------------------------------- entity axi_master_lite_cntlr is generic ( -- AXI4 Parameters C_M_AXI_LITE_ADDR_WIDTH : INTEGER range 32 to 32 := 32; -- width of AXI4 Address Bus (in bits) C_M_AXI_LITE_DATA_WIDTH : INTEGER range 32 to 32 := 32; -- Width of the AXI4 Data Bus (in bits) -- FPGA Family Parameter C_FAMILY : String := "virtex6" -- Select the target architecture type -- see the family.vhd package in the proc_common -- library ); port ( ----------------------------------------------------------------------- -- Clock Input ----------------------------------------------------------------------- axi_aclk : in std_logic ;-- AXI4 ----------------------------------------------------------------------- -- Reset Input (active high) ----------------------------------------------------------------------- axi_reset : in std_logic ;-- AXI4 ----------------------------------------------------------------------- -- Master Detected Error output ----------------------------------------------------------------------- md_error : out std_logic ;-- Discrete Out ---------------------------------------------------------------------------- -- AXI4 Read Channels ---------------------------------------------------------------------------- -- AXI4 Read Address Channel -- AXI4 m_axi_arready : in std_logic ; -- AXI4 m_axi_arvalid : out std_logic ; -- AXI4 m_axi_araddr : out std_logic_vector -- AXI4 (C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4 m_axi_arprot : out std_logic_vector(2 downto 0) ; -- AXI4 -- AXI4 -- AXI4 Read Data Channel -- AXI4 m_axi_rready : out std_logic ; -- AXI4 m_axi_rvalid : in std_logic ; -- AXI4 m_axi_rdata : in std_logic_vector -- AXI4 (C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- AXI4 m_axi_rresp : in std_logic_vector(1 downto 0) ; -- AXI4 ----------------------------------------------------------------------------- -- AXI4 Write Channels ----------------------------------------------------------------------------- -- AXI4 Write Address Channel m_axi_awready : in std_logic ; -- AXI4 m_axi_awvalid : out std_logic ; -- AXI4 m_axi_awaddr : out std_logic_vector -- AXI4 (C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4 m_axi_awprot : out std_logic_vector(2 downto 0) ; -- AXI4 -- AXI4 -- AXI4 Write Data Channel -- AXI4 m_axi_wready : in std_logic ; -- AXI4 m_axi_wvalid : out std_logic ; -- AXI4 m_axi_wdata : out std_logic_vector -- AXI4 (C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- AXI4 m_axi_wstrb : out std_logic_vector -- AXI4 ((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);-- AXI4 -- AXI4 -- AXI4 Write Response Channel -- AXI4 m_axi_bready : out std_logic ; -- AXI4 m_axi_bvalid : in std_logic ; -- AXI4 m_axi_bresp : in std_logic_vector(1 downto 0) ; -- AXI4 ----------------------------------------------------------------------------- -- IP Master Request/Qualifers ----------------------------------------------------------------------------- ip2bus_mstrd_req : In std_logic; -- IPIC ip2bus_mstwr_req : In std_logic; -- IPIC ip2bus_mst_addr : in std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- IPIC ip2bus_mst_be : in std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);-- IPIC ip2bus_mst_lock : In std_logic; -- IPIC -- IPIC ----------------------------------------------------------------------------- -- IP Request Status Reply ----------------------------------------------------------------------------- bus2ip_mst_cmdack : Out std_logic; -- IPIC bus2ip_mst_cmplt : Out std_logic; -- IPIC bus2ip_mst_error : Out std_logic; -- IPIC bus2ip_mst_rearbitrate : Out std_logic; -- IPIC bus2ip_mst_cmd_timeout : out std_logic; -- IPIC -- IPIC -- IPIC ----------------------------------------------------------------------------- -- IPIC Read data ----------------------------------------------------------------------------- bus2ip_mstrd_d : out std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- IPIC bus2ip_mstrd_src_rdy_n : Out std_logic; -- IPIC -- IPIC ----------------------------------------------------------------------------- -- IPIC Write data ----------------------------------------------------------------------------- ip2bus_mstwr_d : In std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- IPIC bus2ip_mstwr_dst_rdy_n : Out std_logic -- IPIC ); end entity axi_master_lite_cntlr; architecture implementation of axi_master_lite_cntlr is -- Signal declarations --------------------------------------- -- AXI4 Read Address Channel signal sig_m_axi_arready : std_logic := '0'; signal sig_m_axi_arvalid : std_logic := '0'; signal sig_m_axi_araddr : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_m_axi_arprot : std_logic_vector(2 downto 0) := (others => '0') ; -- AXI4 Read Data Channel signal sig_m_axi_rready : std_logic := '0'; signal sig_m_axi_rvalid : std_logic := '0'; signal sig_m_axi_rdata : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_m_axi_rresp : std_logic_vector(1 downto 0) := (others => '0'); -- Write Address Channel signal sig_m_axi_awready : std_logic := '0'; signal sig_m_axi_awvalid : std_logic := '0'; signal sig_m_axi_awaddr : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_m_axi_awprot : std_logic_vector(2 downto 0) := (others => '0'); -- Write Data Channel signal sig_m_axi_wready : std_logic := '0'; signal sig_m_axi_wvalid : std_logic := '0'; signal sig_m_axi_wdata : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_m_axi_wstrb : std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0) := (others => '0'); -- Write Response Channel signal sig_m_axi_bready : std_logic := '0'; signal sig_m_axi_bvalid : std_logic := '0'; signal sig_m_axi_bresp : std_logic_vector(1 downto 0) := (others => '0'); -- IP Master Request Qualifers signal sig_ip2bus_rd_req : std_logic := '0'; signal sig_ip2bus_wr_req : std_logic := '0'; signal sig_ip2bus_addr : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_ip2bus_addr_reg : std_logic_vector(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_ip2bus_be : std_logic_vector((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_ip2bus_lock : std_logic := '0'; -- IPIC Status Reply signal sig_bus2ip_cmdack : std_logic := '0'; signal sig_bus2ip_rearbitrate : std_logic := '0'; signal sig_bus2ip_cmd_timeout : std_logic := '0'; signal sig_bus2ip_cmplt : std_logic := '0'; signal sig_bus2ip_error : std_logic := '0'; -- IPIC Data Interface signal sig_bus2ip_mstrd_d : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_bus2ip_rd_src_rdy : std_logic := '0'; signal sig_ip2bus_mstwr_d : std_logic_vector(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); signal sig_bus2ip_wr_dst_rdy : std_logic := '0'; -- AXI Error Response signal sig_read_resp_error : std_logic := '0'; signal sig_read_error : std_logic := '0'; signal sig_write_resp_error : std_logic := '0'; signal sig_write_error : std_logic := '0'; -- Transfer completion signal sig_rd_addrqual_taken : std_logic := '0'; signal sig_wr_addrqual_taken : std_logic := '0'; signal sig_rd_data_taken : std_logic := '0'; signal sig_wr_data_taken : std_logic := '0'; signal sig_wr_resp_taken : std_logic := '0'; -- Transfer Startup signal sig_rd_start : std_logic := '0'; signal sig_wr_start : std_logic := '0'; signal sig_ld_addr : std_logic := '0'; -- Read Transfer sequence signal sig_rd_req_reg : std_logic := '0'; signal sig_rd_in_prog : std_logic := '0'; signal sig_rd_addr_cmplt : std_logic := '0'; signal sig_rd_data_cmplt : std_logic := '0'; signal sig_rd_cmplt : std_logic := '0'; -- Write Transfer sequence signal sig_wr_req_reg : std_logic := '0'; signal sig_wr_in_prog : std_logic := '0'; signal sig_wr_addr_cmplt : std_logic := '0'; signal sig_wr_data_cmplt : std_logic := '0'; signal sig_wr_resp_cmplt : std_logic := '0'; signal sig_wr_cmplt : std_logic := '0'; -- Command Completion signal sig_bus2ip_cmplt_local : std_logic := '0'; -- Detected error signal sig_md_error : std_logic := '0'; ---------------------------------------------------------------- -- Register duplication attribute assignments to control fanout -- on register clear signals ---------------------------------------------------------------- Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_bus2ip_cmplt_local : signal is "TRUE"; Attribute KEEP of sig_bus2ip_cmplt : signal is "TRUE"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_bus2ip_cmplt_local : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_bus2ip_cmplt : signal is "no"; begin --(architecture implementation) ----------------------------------------------------------------------------- -- Port Assignments ----------------------------------------------------------------------------- -- Read Address Channel port assignments sig_m_axi_arready <= m_axi_arready ; m_axi_arvalid <= sig_m_axi_arvalid ; m_axi_araddr <= sig_m_axi_araddr ; m_axi_arprot <= sig_m_axi_arprot ; -- Read Data Channel port assignments m_axi_rready <= sig_m_axi_rready ; sig_m_axi_rvalid <= m_axi_rvalid ; sig_m_axi_rdata <= m_axi_rdata ; sig_m_axi_rresp <= m_axi_rresp ; -- Write Address Channel port assignments sig_m_axi_awready <= m_axi_awready ; m_axi_awvalid <= sig_m_axi_awvalid ; m_axi_awaddr <= sig_m_axi_awaddr ; m_axi_awprot <= sig_m_axi_awprot ; -- AXI4 Write Data Channel port assignments sig_m_axi_wready <= m_axi_wready ; m_axi_wvalid <= sig_m_axi_wvalid ; m_axi_wdata <= sig_m_axi_wdata ; m_axi_wstrb <= sig_m_axi_wstrb ; -- AXI4 Write Response Channel port assignments m_axi_bready <= sig_m_axi_bready ; sig_m_axi_bvalid <= m_axi_bvalid ; sig_m_axi_bresp <= m_axi_bresp ; -- IPIC Command Qualifiers sig_ip2bus_rd_req <= ip2bus_mstrd_req ; -- Input sig_ip2bus_wr_req <= ip2bus_mstwr_req ; -- Input sig_ip2bus_addr <= ip2bus_mst_addr ; -- Input sig_ip2bus_be <= ip2bus_mst_be ; -- Input sig_ip2bus_lock <= ip2bus_mst_lock ; -- Input -- IPIC Status reply bus2ip_mst_cmdack <= sig_bus2ip_cmdack ; -- output bus2ip_mst_rearbitrate <= sig_bus2ip_rearbitrate ; -- output bus2ip_mst_cmd_timeout <= sig_bus2ip_cmd_timeout ; -- output bus2ip_mst_cmplt <= sig_bus2ip_cmplt ; -- output bus2ip_mst_error <= sig_bus2ip_error ; -- output -- IPIC Read Data IF bus2ip_mstrd_d <= sig_bus2ip_mstrd_d ; -- output bus2ip_mstrd_src_rdy_n <= not(sig_bus2ip_rd_src_rdy); -- output -- IPIC write Data IF sig_ip2bus_mstwr_d <= ip2bus_mstwr_d ; -- input bus2ip_mstwr_dst_rdy_n <= not(sig_bus2ip_wr_dst_rdy); -- output -- MD Error output md_error <= sig_md_error ; -- output -- IPIC Error status output sig_bus2ip_error <= sig_read_error or -- Assert on either a read sig_write_error ; -- or write error detection ----------------------------------------------------------------------------- -- Combinitorial logic ----------------------------------------------------------------------------- -- Drive the IPIC Rearbitrate and Timeout to zeros sig_bus2ip_rearbitrate <= '0' ; -- not available in AXI4 sig_bus2ip_cmd_timeout <= '0' ; -- not available in AXI4 -- Drive the axi protection qualifiers to zeros sig_m_axi_awprot <= (others => '0') ; -- always driven to zeros sig_m_axi_arprot <= (others => '0') ; -- always driven to zeros -- Share the address register for both read and write xfers sig_m_axi_araddr <= sig_ip2bus_addr_reg ; sig_m_axi_awaddr <= sig_ip2bus_addr_reg ; -- Detect when the read address has been accepted on the axi bus sig_rd_addrqual_taken <= sig_m_axi_arvalid and sig_m_axi_arready ; -- Detect when the write address has been accepted axi bus sig_wr_addrqual_taken <= sig_m_axi_awvalid and sig_m_axi_awready ; -- Detect when the read data has been accepted axi bus sig_rd_data_taken <= sig_m_axi_rvalid and sig_m_axi_rready ; -- Detect when the write data has been accepted axi bus sig_wr_data_taken <= sig_m_axi_wvalid and sig_m_axi_wready ; -- Detect when the write response has been accepted axi bus sig_wr_resp_taken <= sig_m_axi_bvalid and sig_m_axi_bready ; -- Detirmine if a read response error is being flagged sig_read_resp_error <= '1' when (sig_m_axi_rresp(0) = '1' or sig_m_axi_rresp(1) = '1') else '0'; -- Detirmine if a write response error is being flagged sig_write_resp_error <= '1' when (sig_m_axi_bresp(0) = '1' or sig_m_axi_bresp(1) = '1') else '0'; -- Detirmine if a read transfer sequence has completed -- or is about to complete sig_rd_cmplt <= sig_rd_in_prog and (sig_rd_addr_cmplt or sig_rd_addrqual_taken) and (sig_rd_data_cmplt or sig_rd_data_taken); -- Detirmine if a write transfer sequence has completed -- or is about to complete sig_wr_cmplt <= sig_wr_in_prog and (sig_wr_addr_cmplt or sig_wr_addrqual_taken) and (sig_wr_data_cmplt or sig_wr_data_taken) and (sig_wr_resp_cmplt or sig_wr_resp_taken); -- Generate the Command Address sample and hold signal sig_ld_addr <= sig_rd_start or sig_wr_start; -- Detect rising edge of new read command sig_rd_start <= sig_ip2bus_rd_req and not(sig_rd_req_reg); -- Detect rising edge of new write command sig_wr_start <= sig_ip2bus_wr_req and not(sig_wr_req_reg); ----------------------------------------------------------------------------- -- Command Start detection ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RDREQ_REG -- -- Process Description: -- Registers the IPIC read request input. -- ------------------------------------------------------------- IMP_RDREQ_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_rd_req_reg <= '0' ; else sig_rd_req_reg <= sig_ip2bus_rd_req ; end if; end if; end process IMP_RDREQ_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WRREQ_REG -- -- Process Description: -- Registers the IPIC write request input. -- ------------------------------------------------------------- IMP_WRREQ_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_wr_req_reg <= '0' ; else sig_wr_req_reg <= sig_ip2bus_wr_req ; end if; end if; end process IMP_WRREQ_REG; ----------------------------------------------------------------------------- -- shared Address Register ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_REG -- -- Process Description: -- Registers the IPIC addres input whenever a new command -- has been detected. -- ------------------------------------------------------------- IMP_ADDR_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_ip2bus_addr_reg <= (others => '0') ; elsif (sig_ld_addr = '1') then sig_ip2bus_addr_reg <= sig_ip2bus_addr ; else null; -- Hold Current State end if; end if; end process IMP_ADDR_REG; ----------------------------------------------------------------------------- -- Generate Write Transfer Registers and Control ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WRITE_IN_PROG_FLOP -- -- Process Description: -- Implements the read in progress flop. -- ------------------------------------------------------------- IMP_WRITE_IN_PROG_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_wr_in_prog <= '0' ; elsif (sig_wr_start = '1') then sig_wr_in_prog <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WRITE_IN_PROG_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_AWVALID_FLOP -- -- Process Description: -- Implements the write awvalid flop. -- ------------------------------------------------------------- IMP_AWVALID_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_wr_addrqual_taken = '1') then sig_m_axi_awvalid <= '0' ; elsif (sig_wr_start = '1') then sig_m_axi_awvalid <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_AWVALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WVALID_FLOP -- -- Process Description: -- Implements the write wvalid flop. -- ------------------------------------------------------------- IMP_WVALID_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_wr_data_taken = '1') then sig_m_axi_wvalid <= '0' ; elsif (sig_wr_start = '1') then sig_m_axi_wvalid <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WVALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WDATA_REG -- -- Process Description: -- Implements the write data register. -- ------------------------------------------------------------- IMP_WDATA_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_m_axi_wdata <= (others => '0') ; sig_m_axi_wstrb <= (others => '0') ; elsif (sig_wr_start = '1') then sig_m_axi_wdata <= sig_ip2bus_mstwr_d ; sig_m_axi_wstrb <= sig_ip2bus_be ; else null; -- Hold Current State end if; end if; end process IMP_WDATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_ERR_REG -- -- Process Description: -- Implements the read response error flag. -- ------------------------------------------------------------- IMP_WR_ERR_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_write_error <= '0' ; elsif (sig_wr_resp_taken = '1') then sig_write_error <= sig_write_resp_error ; else null; -- Hold Current State end if; end if; end process IMP_WR_ERR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_DST_RDY_FLAG -- -- Process Description: -- Implements the IPIC write destination ready flag. -- ------------------------------------------------------------- IMP_WR_DST_RDY_FLAG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_wr_dst_rdy = '1') then sig_bus2ip_wr_dst_rdy <= '0' ; --elsif (sig_wr_data_taken = '1') then elsif (sig_wr_cmplt = '1') then sig_bus2ip_wr_dst_rdy <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_DST_RDY_FLAG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_BREADY_FLOP -- -- Process Description: -- Implements the write response channel bready flop. -- ------------------------------------------------------------- IMP_WR_BREADY_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_wr_resp_taken = '1') then sig_m_axi_bready <= '0' ; elsif (sig_wr_start = '1') then sig_m_axi_bready <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_BREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_ADDR_CMPLT_FLOP -- -- Process Description: -- Implements the write address complete flag. -- ------------------------------------------------------------- IMP_WR_ADDR_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_wr_addr_cmplt <= '0' ; elsif (sig_wr_addrqual_taken = '1') then sig_wr_addr_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_ADDR_CMPLT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_DATA_CMPLT_FLOP -- -- Process Description: -- Implements the write data complete flag. -- ------------------------------------------------------------- IMP_WR_DATA_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_wr_data_cmplt <= '0' ; elsif (sig_wr_data_taken = '1') then sig_wr_data_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_DATA_CMPLT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WR_RESP_CMPLT_FLOP -- -- Process Description: -- Implements the write data complete flag. -- ------------------------------------------------------------- IMP_WR_RESP_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_wr_resp_cmplt <= '0' ; elsif (sig_wr_resp_taken = '1') then sig_wr_resp_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_WR_RESP_CMPLT_FLOP; ----------------------------------------------------------------------------- -- Generate Read Transfer Registers and Control ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_READ_IN_PROG_FLOP -- -- Process Description: -- Implements the read in progress flop. -- ------------------------------------------------------------- IMP_READ_IN_PROG_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_rd_in_prog <= '0' ; elsif (sig_rd_start = '1') then sig_rd_in_prog <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_READ_IN_PROG_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RVALID_FLOP -- -- Process Description: -- Implements the write awvalid flop. -- ------------------------------------------------------------- IMP_RVALID_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_rd_addrqual_taken = '1') then sig_m_axi_arvalid <= '0' ; elsif (sig_rd_start = '1') then sig_m_axi_arvalid <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RVALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RREADY_FLOP -- -- Process Description: -- Implements the read rready flop. -- ------------------------------------------------------------- IMP_RREADY_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_rd_data_taken = '1') then sig_m_axi_rready <= '0' ; elsif (sig_rd_start = '1') then sig_m_axi_rready <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RDATA_REG -- -- Process Description: -- Implements the read data register. -- ------------------------------------------------------------- IMP_RDATA_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_bus2ip_mstrd_d <= (others => '0') ; elsif (sig_rd_data_taken = '1') then sig_bus2ip_mstrd_d <= sig_m_axi_rdata ; else null; -- Hold Current State end if; end if; end process IMP_RDATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RD_SRC_RDY_FLAG -- -- Process Description: -- Implements the IPIC read source ready flag. -- ------------------------------------------------------------- IMP_RD_SRC_RDY_FLAG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_rd_src_rdy = '1') then sig_bus2ip_rd_src_rdy <= '0' ; elsif (sig_rd_data_taken = '1') then sig_bus2ip_rd_src_rdy <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RD_SRC_RDY_FLAG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_READ_ERR_REG -- -- Process Description: -- Implements the read response error flag. -- ------------------------------------------------------------- IMP_READ_ERR_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_read_error <= '0' ; elsif (sig_rd_data_taken = '1') then sig_read_error <= sig_read_resp_error ; else null; -- Hold Current State end if; end if; end process IMP_READ_ERR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RD_ADDR_CMPLT_FLOP -- -- Process Description: -- Implements the read address complete flag. -- ------------------------------------------------------------- IMP_RD_ADDR_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_rd_addr_cmplt <= '0' ; elsif (sig_rd_addrqual_taken = '1') then sig_rd_addr_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RD_ADDR_CMPLT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_RD_DATA_CMPLT_FLOP -- -- Process Description: -- Implements the read data complete flag. -- ------------------------------------------------------------- IMP_RD_DATA_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_rd_data_cmplt <= '0' ; elsif (sig_rd_data_taken = '1') then sig_rd_data_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_RD_DATA_CMPLT_FLOP; ----------------------------------------------------------------------------- -- IPIC Command Status Generation logic ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMDACK_FLOP -- -- Process Description: -- Implements the IPIC Command Acknowledge status flag. -- ------------------------------------------------------------- IMP_CMDACK_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmdack = '1') then sig_bus2ip_cmdack <= '0' ; elsif (sig_rd_addrqual_taken = '1' or sig_wr_addrqual_taken = '1') then sig_bus2ip_cmdack <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_CMDACK_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_CMPLT_LOCAL_FLOP -- -- Process Description: -- Implements the IPIC Command Acknowledge status flag. -- ------------------------------------------------------------- IMP_CMD_CMPLT_LOCAL_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_bus2ip_cmplt_local <= '0' ; elsif (sig_rd_cmplt = '1' or sig_wr_cmplt = '1') then sig_bus2ip_cmplt_local <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_CMD_CMPLT_LOCAL_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_CMPLT_FLOP -- -- Process Description: -- Implements the IPIC Command Acknowledge status flag. -- ------------------------------------------------------------- IMP_CMD_CMPLT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_bus2ip_cmplt_local = '1') then sig_bus2ip_cmplt <= '0' ; elsif (sig_rd_cmplt = '1' or sig_wr_cmplt = '1') then sig_bus2ip_cmplt <= '1' ; else null; -- Hold Current State end if; end if; end process IMP_CMD_CMPLT_FLOP; ----------------------------------------------------------------------------- -- Master Detected error logic ----------------------------------------------------------------------------- ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_H_ERRORS -- -- Process Description: -- This process implements the sample and hold logic for -- any detected errors. If an error is detected, then the -- md_error output signal is driven high until the Master -- is reset. -- ------------------------------------------------------------- S_H_ERRORS : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_md_error <= '0'; elsif (sig_read_error = '1' or sig_write_error = '1') then sig_md_error <= '1'; else null; -- hold last state end if; else null; end if; end process S_H_ERRORS; end implementation;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc613.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:43 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:03 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:22 1996 -- -- **************************** -- ENTITY c03s04b01x00p01n01i00613ent IS END c03s04b01x00p01n01i00613ent; ARCHITECTURE c03s04b01x00p01n01i00613arch OF c03s04b01x00p01n01i00613ent IS constant C1 : boolean := true; constant C4 : severity_level := note; constant C5 : integer := 3; constant C6 : real := 3.0; constant C7 : time := 3 ns; constant C8 : natural := 3; constant C9 : positive := 3; type boolean_cons_vector is array (15 downto 0) of boolean; type severity_level_cons_vector is array (15 downto 0) of severity_level; type integer_cons_vector is array (15 downto 0) of integer; type real_cons_vector is array (15 downto 0) of real; type time_cons_vector is array (15 downto 0) of time; type natural_cons_vector is array (15 downto 0) of natural; type positive_cons_vector is array (15 downto 0) of positive; constant C19 : boolean_cons_vector := (others => C1); constant C20 : severity_level_cons_vector := (others => C4); constant C21 : integer_cons_vector := (others => C5); constant C22 : real_cons_vector := (others => C6); constant C23 : time_cons_vector := (others => C7); constant C24 : natural_cons_vector := (others => C8); constant C25 : positive_cons_vector := (others => C9); type record_cons_array is record a:boolean_cons_vector; b:severity_level_cons_vector; c:integer_cons_vector; d:real_cons_vector; e:time_cons_vector; f:natural_cons_vector; g:positive_cons_vector; end record; type record_cons_array_file is file of record_cons_array; constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25); signal k : integer := 0; BEGIN TESTING: PROCESS file filein : record_cons_array_file open read_mode is "iofile.34"; variable v : record_cons_array; BEGIN for i in 1 to 100 loop assert(endfile(filein) = false) report"end of file reached before expected"; read(filein,v); if (v /= C27) then k <= 1; end if; end loop; wait for 1 ns; assert NOT(k = 0) report "***PASSED TEST: c03s04b01x00p01n01i00613" severity NOTE; assert (k = 0) report "***FAILED TEST: c03s04b01x00p01n01i00613 - File reading operation (record_cons_array file type) failed." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p01n01i00613arch;

library IEEE; use ieee.std_logic_1164.all; entity pw_process is port ( --length : in natural; clk : in std_logic; pwd : out string ); end pw_process; architecture arch_pw_process of pw_process is component pwd_string port ( push_pop : in std_logic; char : in character; clk : in std_logic; enable: in std_logic; pwd : out string ); end component; component recursive_stack port ( length_in : in natural; length_out : out natural; index_in : in natural; index_out : out natural; enable : in std_logic; push_pop: in std_logic; clk : in std_logic ); end component; component vowels port ( length_in : in natural; length_out : out natural; enable : in STD_LOGIC; reset : in std_logic; load_index : in natural; current_index: out natural; clk : in std_logic; data : out character; valid : out std_logic := '0' ); end component; type DenyFlags is (F_CONSONANT, F_VOWEL, F_DIPTHONG, F_NOT_FIRST, F_DIGIT, F_FIRST, F_UPPERS); -- signal valid : std_logic; signal char : character; signal length, length_addr : natural := 0; signal load_index, current_index : natural := 0; signal next_char : std_logic; signal stack_register : std_logic := '0'; begin final_pwd : pwd_string port map ( push_pop => valid, char => char, clk => clk, enable => '1', pwd => pwd ); stack : recursive_stack port map ( enable => stack_register, push_pop => next_char, length_in => length_addr, length_out => length, index_in => current_index, index_out => load_index, clk => clk ); vowel : vowels port map ( length_in => length, length_out => length_addr, enable => '1', reset => next_char, load_index => load_index, current_index => current_index, clk => clk, data => char, valid => valid ); process(clk) begin if rising_edge(clk) then if valid = '1' and length_addr < 4 then next_char <= '1'; else next_char <= '0'; end if; if length_addr >= 4 and valid = '1' then stack_register <= '0'; else stack_register <= '1'; end if; end if; end process; end arch_pw_process;

---------------------------------------------------------------------------------- -- Felix Winterstein, Imperial College London -- -- Module Name: centre_buffer_mgmt - Behavioral -- -- Revision 1.01 -- Additional Comments: distributed under a BSD license, see LICENSE.txt -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.math_real.all; use work.lloyds_algorithm_pkg.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity centre_buffer_mgmt is port ( clk : in std_logic; sclr : in std_logic; init : in std_logic; addr_in_init : in centre_index_type; nd : in std_logic; request_rdo : in std_logic; addr_in : in centre_index_type; wgtCent_in : in data_type_ext; sum_sq_in : in coord_type_ext; count_in : in coord_type; valid : out std_logic; wgtCent_out : out data_type_ext; sum_sq_out : out coord_type_ext; count_out : out coord_type ); end centre_buffer_mgmt; architecture Behavioral of centre_buffer_mgmt is constant DIM : integer := D; constant LAT : integer := 2; type state_type is (read, write); component centre_buffer_dist port ( a : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(K_MAX))))-1 DOWNTO 0); dpra : IN STD_LOGIC_VECTOR(integer(ceil(log2(real(K_MAX))))-1 DOWNTO 0); d : IN STD_LOGIC_VECTOR(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 DOWNTO 0); clk : IN STD_LOGIC; we : IN STD_LOGIC; qdpo_srst : IN STD_LOGIC; qdpo : OUT STD_LOGIC_VECTOR(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 DOWNTO 0) ); end component; signal state : state_type; signal tmp_we : std_logic; signal we_reg : std_logic; signal rdo_delay : std_logic_vector(0 to LAT-1); signal wr_addr_in_reg : centre_index_type; signal rd_addr_in_reg : centre_index_type; signal wgtCent_reg : data_type_ext; signal sum_sq_reg : coord_type_ext; signal count_reg : coord_type; signal tmp_dina : std_logic_vector(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 downto 0); signal tmp_doutb : std_logic_vector(COORD_BITWIDTH+COORD_BITWIDTH_EXT+DIM*COORD_BITWIDTH_EXT-1 downto 0); signal tmp_wgtCent_int : data_type_ext; signal tmp_sum_sq_int : coord_type_ext; signal tmp_count_int : coord_type; signal tmp_wgtCent_int_sum : data_type_ext; signal tmp_sum_sq_int_sum : coord_type_ext; signal tmp_count_int_sum : coord_type; begin fsm_proc : process(clk) begin if rising_edge(clk) then if sclr = '1' then state <= read; elsif state = read AND nd = '1' then state <= write; elsif state = write then state <= read; end if; end if; end process fsm_proc; tmp_we <= '1' WHEN state = write ELSE '0'; reg_proc : process(clk) begin if rising_edge(clk) then if init = '1' then wr_addr_in_reg <= addr_in_init; rd_addr_in_reg <= addr_in; for I in 0 to D-1 loop wgtCent_reg(I) <= (others => '0'); end loop; sum_sq_reg <= (others => '0'); count_reg <= (others => '0'); elsif nd = '1' OR request_rdo='1' then wr_addr_in_reg <= addr_in; rd_addr_in_reg <= addr_in; --addr_in_reg <= addr_in; wgtCent_reg <= wgtCent_in; sum_sq_reg <= sum_sq_in; count_reg <= count_in; end if; end if; end process reg_proc; reg_proc2 : process(clk) begin if rising_edge(clk) then if sclr = '1' then we_reg <= '0'; rdo_delay <= (others => '0'); else we_reg <= tmp_we OR init; rdo_delay(0) <= request_rdo; rdo_delay(1 to LAT-1) <= rdo_delay(0 to LAT-2); end if; end if; end process reg_proc2; centre_buffer_dist_inst : centre_buffer_dist port map ( a => std_logic_vector(wr_addr_in_reg(integer(ceil(log2(real(K_MAX))))-1 downto 0)), dpra => std_logic_vector(rd_addr_in_reg(integer(ceil(log2(real(K_MAX))))-1 downto 0)), d => tmp_dina, clk => clk, we => we_reg, qdpo_srst => init, qdpo => tmp_doutb ); G1: for I in 0 to D-1 generate tmp_wgtCent_int(I) <= tmp_doutb((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT); end generate G1; tmp_sum_sq_int <= tmp_doutb(1*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT); tmp_count_int <= tmp_doutb(COORD_BITWIDTH+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT); G2: for I in 0 to D-1 generate tmp_wgtCent_int_sum(I) <= std_logic_vector(signed(tmp_wgtCent_int(I)) + signed(wgtCent_reg(I))); tmp_dina((I+1)*COORD_BITWIDTH_EXT-1 downto I*COORD_BITWIDTH_EXT) <= (tmp_wgtCent_int_sum(I)); end generate G2; tmp_sum_sq_int_sum <= std_logic_vector(signed(tmp_sum_sq_int) + signed(sum_sq_reg)); tmp_dina(1*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0*COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT) <= tmp_sum_sq_int_sum; tmp_count_int_sum <= std_logic_vector(signed(tmp_count_int) + signed(count_reg)); tmp_dina(COORD_BITWIDTH+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT-1 downto 0+COORD_BITWIDTH_EXT+D*COORD_BITWIDTH_EXT) <= tmp_count_int_sum; valid <= rdo_delay(LAT-1); wgtCent_out <= tmp_wgtCent_int; sum_sq_out <= tmp_sum_sq_int; count_out <= tmp_count_int; end Behavioral;

library ieee; use ieee.std_logic_1164.all; entity var6_tb is end var6_tb; architecture TB_ARCHITECTURE of var6_tb is component var6 port( W : in STD_LOGIC; X : in STD_LOGIC; Y : in STD_LOGIC; Z : in STD_LOGIC; F : out STD_LOGIC); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal W : STD_LOGIC; signal X : STD_LOGIC; signal Y : STD_LOGIC; signal Z : STD_LOGIC; -- Observed signals - signals mapped to the output ports of tested entity signal F, F1 : STD_LOGIC; signal error : std_logic; begin -- Unit Under Test port map UUT : var6 port map ( W => W, X => X, Y => Y, Z => Z, F => F ); UUT2 : var6 port map ( W => W, X => X, Y => Y, Z => Z, F => F1 ); --Below VHDL code is an inserted .\compile\task.vhs --User can modify it .... STIMULUS: process begin -- of stimulus process --wait for <time to next event>; -- <current time> W <= '0'; Y <= '0'; Z <= '0'; X <= '0'; wait for 50 ns; --0 fs X <= '1'; wait for 50 ns; --50 ns Y <= '1'; X <= '0'; wait for 50 ns; --100 ns X <= '1'; wait for 50 ns; --150 ns Y <= '0'; Z <= '1'; X <= '0'; wait for 50 ns; --200 ns X <= '1'; wait for 50 ns; --250 ns Y <= '1'; X <= '0'; wait for 50 ns; --300 ns X <= '1'; wait for 50 ns; --350 ns W <= '1'; Y <= '0'; Z <= '0'; X <= '0'; wait for 50 ns; --400 ns X <= '1'; wait for 50 ns; --450 ns Y <= '1'; X <= '0'; wait for 50 ns; --500 ns X <= '1'; wait for 50 ns; --550 ns Y <= '0'; Z <= '1'; X <= '0'; wait for 50 ns; --600 ns X <= '1'; wait for 50 ns; --650 ns Y <= '1'; X <= '0'; wait for 50 ns; --700 ns X <= '1'; wait for 50 ns; --750 ns W <= '0'; Y <= '0'; Z <= '0'; X <= '0'; -- end of stimulus events 800 ns wait; end process; -- end of stimulus process error <= F1 xor F; -- Add your stimulus here ... end TB_ARCHITECTURE;

-- SIMON 64/128 -- key schedule test bench -- -- @Author: Jos Wetzels -- @Author: Wouter Bokslag -- LIBRARY ieee; USE ieee.std_logic_1164.ALL; use ieee.NUMERIC_STD.ALL; ENTITY tb_keyschedule IS END tb_keyschedule; ARCHITECTURE behavior OF tb_keyschedule IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT key_schedule port ( r : in std_logic_vector(7 downto 0); k_0 : in std_logic_vector(31 downto 0); k_1 : in std_logic_vector(31 downto 0); k_3 : in std_logic_vector(31 downto 0); subkey_out : out std_logic_vector(31 downto 0)); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal r : std_logic_vector(7 downto 0); -- round index type key_t is array (0 to 3) of std_logic_vector(31 downto 0); signal key_s : key_t; -- k0..3 --Outputs signal subkey_out : std_logic_vector(31 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; signal clk_generator_finish : STD_LOGIC := '0'; signal test_bench_finish : STD_LOGIC := '0'; BEGIN -- Instantiate the Unit Under Test (UUT) uut: key_schedule PORT MAP ( r => r, k_0 => key_s(0), k_1 => key_s(1), k_3 => key_s(3), subkey_out => subkey_out ); -- Clock process definitions clock : process begin while ( clk_generator_finish /= '1') loop clk <= not clk; wait for clk_period/2; end loop; wait; end process; -- Stimulus process stim_proc: process begin wait for clk_period/2 + 10*clk_period; -- SIMON 64/128 test vectors key_s(0) <= X"03020100"; key_s(1) <= X"0b0a0908"; key_s(2) <= X"13121110"; key_s(3) <= X"1b1a1918"; r <= X"00"; wait for clk_period; assert subkey_out = X"70a011c3" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"b770ec49" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"57e3e835" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d397bc42" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"94dcf81f" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"bf4b5f18" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"8e5dabb9" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"dbf4a863" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"cd0c28fc" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"5cb69911" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"79f112a5" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"77205863" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"99880c12" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"1ce97c58" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"c8ed2145" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"b800dbb8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"e86a2756" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"7c06d4dd" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"ab52df0a" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"247f66a8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"53587ca6" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d25c13f1" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"4583b64b" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"7d9c960d" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"efbfc2f3" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"89ed8513" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"308dfc4e" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"bf1a2a36" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"e1499d70" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"4ce4d2ff" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"32b7ebef" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"c47505c1" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"d0e929e8" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"8fe484b9" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"42054bee" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"af77bae2" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"18199c02" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"719e3f1c" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"0c1cf793" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; key_s(0) <= key_s(1); key_s(1) <= key_s(2); key_s(2) <= key_s(3); key_s(3) <= subkey_out; r <= std_logic_vector(unsigned(r) + 1); wait for clk_period; assert subkey_out = X"15df4696" report "KEY_SCHEDULE ERROR (k)" severity FAILURE; test_bench_finish <= '1'; clk_generator_finish <= '1'; wait for clk_period; wait; end process; END;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:15:50 10/19/2016 -- Design Name: -- Module Name: Register - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Internal_Register is port( clk : IN STD_LOGIC; -- clock input register_input : IN STD_LOGIC_VECTOR (7 downto 0); -- input data register_data : INOUT STD_LOGIC_VECTOR (7 downto 0); -- internal data register_output : OUT STD_LOGIC_VECTOR (7 downto 0); -- output data register_command : IN STD_LOGIC ); end Internal_Register; architecture Behavioral of Internal_Register is begin REGISTER_PROCESS : process(clk) begin if clk= '1' and clk'event then if register_command = '1' then register_data <= register_input; -- reading from bus elsif register_command = '0' then register_output <= register_data; -- writing to bus end if; end if; end process; end Behavioral;

--Copyright 2017 Christoffer Mathiesen, Gustav Örtenberg --Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: -- --1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -- --2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the --documentation and/or other materials provided with the distribution. -- --3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this --software without specific prior written permission. -- --THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, --THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS --BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE --GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT --LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Library IEEE; Use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_MISC.ALL; Use IEEE.STD_LOGIC_UNSIGNED.ALL; Use IEEE.NUMERIC_STD.all; Use work.all; Entity Keyboard is Port ( Row_Input : in STD_LOGIC_VECTOR (3 downto 0); Col_Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '1'); Output : out STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); RDY : out STD_LOGIC := '0'; CLK : in STD_LOGIC; ARESETN : in STD_LOGIC ); end Keyboard; --This is a translator for the Keypad v3.0 to hex --To be connected to the outside world. First it debounces the signal. --It's to be connected to a 16-button keyboard with pins 4 rows and 4 columns --To parse the button presses this module first drives all col-pins with high value. --When a high value is detected on any of the input row-pins it scans over the columns --one by one (with 500 cycles delay) and detects high values on the row pins. If only one --button was pressed it's parsed as a vector defined in the case-statement below, and --the RDY-bit is set high to signal valid input. --Any parsing besides the accepted ones gives output 0 and the RDY-bit to 0 architecture Behaviour of Keyboard is signal input_debounced : STD_LOGIC_VECTOR (3 downto 0); signal counter : unsigned (31 downto 0) := (others => '0'); signal translated : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; Begin Process (CLK) Begin if rising_edge(CLK) then input_debounced <= Row_Input; IF ARESETN = '1' THEN if input_debounced = "0000" and counter = "0000" then --counter <= "0000"; RDY <= '0'; translated <= (others => '0'); else if counter = to_unsigned(0, 32) then Col_Output <= "0001"; elsif counter = to_unsigned(500, 32) then --Wait for 500 cycles fom previous step if input_debounced /= "0000" then translated <= STD_LOGIC_VECTOR(input_debounced) & "0001"; end if; Col_Output <= "0010"; elsif counter = to_unsigned(1000, 32) then--Wait for 500 cycles fom previous step if input_debounced /= "0000" then translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "0010"; end if; Col_Output <= "0100"; elsif counter = to_unsigned(1500, 32) then --Wait for 500 cycles fom previous step if input_debounced /= "0000" then translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "0100"; end if; Col_Output <= "1000"; elsif counter = to_unsigned(2000, 32) then --Wait for 500 cycles fom previous step if input_debounced /= "0000" then translated <= translated or STD_LOGIC_VECTOR(input_debounced) & "1000"; end if; Col_Output <= "1111"; else --do nothing end if; if counter /= to_unsigned(4000, 32) then --Wait for 2000 cycles fom previous step counter <= counter + 1; elsif input_debounced = "0000" then --Wait for release of button counter <= (others => '0'); -- --Case for translations. In order of magnitude. -- Input is in the format 7 downto 4 row, 3 downto 0 col. -- I.e. the vector 0100 0001 is row 3, col 1 Translate: case translated is when "10000010" => RDY <= '1'; --0 Output <= "0000"; when "00010001" => RDY <= '1'; --1 Output <= "0001"; when "00010010" => RDY <= '1'; --2 Output <= "0010"; when "00010100" => RDY <= '1'; --3 Output <= "0011"; when "00100001" => RDY <= '1'; --4 Output <= "0100"; when "00100010" => RDY <= '1'; --5 Output <= "0101"; when "00100100" => RDY <= '1'; --6 Output <= "0110"; when "01000001" => RDY <= '1'; --7 Output <= "0111"; when "01000010" => RDY <= '1'; --8 Output <= "1000"; when "01000100" => RDY <= '1'; --9 Output <= "1001"; when "00011000" => RDY <= '1'; --A Output <= "1010"; when "00101000" => RDY <= '1'; --B Output <= "1011"; when "01001000" => RDY <= '1'; --C Output <= "1100"; when "10001000" => RDY <= '1'; --D Output <= "1101"; when "10000100" => RDY <= '1'; --E Output <= "1110"; when "10000001" => RDY <= '1'; --F Output <= "1111"; when others => RDY <= '0'; --Others Output <= "0000"; end case Translate; end if; end if; elsif ARESETN = '0' then RDY <= '0'; Output <= (others => '0'); --Reset translated <= (others => '0'); counter <= (others => '0'); END IF; end if; end process; end Behaviour;

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-------------------------------------------------------------------------- -- -- Copyright (C) 1993, Peter J. Ashenden -- Mail: Dept. Computer Science -- University of Adelaide, SA 5005, Australia -- e-mail: [email protected] -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 1, or (at your option) -- any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -- -------------------------------------------------------------------------- -- -- $RCSfile: dlx_test_cache.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 22:16:15 $ -- -------------------------------------------------------------------------- -- -- Configuration of test bench for DLX and cache, -- using behavioural architectures. -- configuration dlx_test_cache of dlx_test is for bench_cache use work.cache_types.all; for cg : clock_gen use entity work.clock_gen(behaviour) generic map (Tpw => 8 ns, Tps => 2 ns); end for; for mem : memory use entity work.memory(behaviour) generic map (mem_size => 65536, Tac1 => 95 ns, Tacb => 35 ns, Tpd_clk_out => 2 ns); end for; for the_cache : cache use entity work.cache(behaviour) generic map (cache_size => 4096, line_size => 16, associativity => 2, write_strategy => write_through, Tpd_clk_out => 2 ns); end for; for cpu_cache_monitor : dlx_bus_monitor use entity work.dlx_bus_monitor(behaviour) generic map (enable => true, verbose => false, tag => "cpu cache monitor"); end for; for cache_mem_monitor : dlx_bus_monitor use entity work.dlx_bus_monitor(behaviour) generic map (enable => true, verbose => false, tag => "cache mem monitor"); end for; for proc : dlx use entity work.dlx(behaviour) generic map (Tpd_clk_out => 2 ns, debug => false, tag => "proc"); end for; end for; end dlx_test_cache;

-- megafunction wizard: %RAM: 1-PORT% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: M9K_RAM.vhd -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 13.1.0 Build 162 10/23/2013 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2013 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY M9K_RAM IS PORT ( address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); clock : IN STD_LOGIC := '1'; init_phase : IN STD_LOGIC_VECTOR(3 DOWNTO 0); input : IN STD_LOGIC_VECTOR(15 DOWNTO 0); data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); rden : IN STD_LOGIC := '1'; wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END M9K_RAM; ARCHITECTURE SYN OF m9k_ram IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); signal a : std_logic_vector(7 downto 0); signal d : std_logic_vector(15 downto 0); signal w : std_logic; BEGIN a <= X"00" when (init_phase = X"1") else address; d <= input when (init_phase = X"1") else data; w <= '1' when (init_phase = X"1") else wren; q <= sub_wire0(15 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( clock_enable_input_a => "BYPASS", clock_enable_output_a => "BYPASS", init_file => "../content.mif", intended_device_family => "Cyclone III", lpm_hint => "ENABLE_RUNTIME_MOD=NO", lpm_type => "altsyncram", maximum_depth => 256, numwords_a => 256, operation_mode => "SINGLE_PORT", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE", ram_block_type => "M9K", read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", widthad_a => 8, width_a => 16, width_byteena_a => 1 ) PORT MAP ( address_a => a, clock0 => clock, data_a => d, wren_a => w, rden_a => rden, q_a => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" -- Retrieval info: PRIVATE: AclrByte NUMERIC "0" -- Retrieval info: PRIVATE: AclrData NUMERIC "0" -- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: Clken NUMERIC "0" -- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "256" -- Retrieval info: PRIVATE: MIFfilename STRING "../content.mif" -- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" -- Retrieval info: PRIVATE: RegAddr NUMERIC "1" -- Retrieval info: PRIVATE: RegData NUMERIC "1" -- Retrieval info: PRIVATE: RegOutput NUMERIC "0" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SingleClock NUMERIC "1" -- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" -- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "8" -- Retrieval info: PRIVATE: WidthData NUMERIC "16" -- Retrieval info: PRIVATE: rden NUMERIC "1" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: INIT_FILE STRING "../content.mif" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "256" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" -- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" -- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" -- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" -- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden" -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" -- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 -- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 -- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL M9K_RAM_inst.vhd TRUE -- Retrieval info: LIB_FILE: altera_mf

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.ALL; use IEEE.numeric_std.all; use work.SearchModule_pkg.ALL; entity SearchModuleTB is end SearchModuleTB; architecture Behavioral of SearchModuleTB is constant DATA_WIDTH_A_USAR: integer := 32; constant ADDR_WIDTH_A_USAR: integer := 10; --type arrayOfADDR_WIDTH is array ((ADDR_WIDTH_A_USAR-1) downto 0) of std_logic_vector((ADDR_WIDTH_A_USAR-1) downto 0); signal clk : std_logic; signal search : std_logic; signal dataToCompare : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0); signal operationID : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0); signal porta_wr : std_logic; signal porta_waddr : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0); signal porta_din : std_logic_vector( (DATA_WIDTH_A_USAR-1) downto 0); signal searchFinished : std_logic; signal searchresult : std_logic; signal resultIndex : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0); signal result_operationID : std_logic_vector( (DATA_WIDTH_A_USAR-1) downto 0); signal internalResultFinished_dbg : std_logic_vector( (ADDR_WIDTH_A_USAR-1) downto 0); signal resultIndexs_dbg : arrayOfADDR_WIDTH((ADDR_WIDTH_A_USAR-1) downto 0); signal dataFound_dbg : arrayUOfDATA_WIDTH((ADDR_WIDTH_A_USAR-1) downto 0); signal errorDetected : std_logic := '0'; constant clk_period : time := 10 ns; begin uut: entity work.SearchModule generic map ( DATA_WIDTH => DATA_WIDTH_A_USAR, ADDR_WIDTH => ADDR_WIDTH_A_USAR ) port map ( clk => clk, search => search, dataToCompare => dataToCompare, operationID => operationID, porta_wr => porta_wr, porta_waddr => porta_waddr, porta_din => porta_din, searchFinished => searchFinished, searchresult => searchresult, resultIndex => resultIndex, result_operationID => result_operationID, internalResultFinished_dbg => internalResultFinished_dbg, resultIndexs_dbg => resultIndexs_dbg, dataFound_dbg => dataFound_dbg ); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; test : process variable readWriteCounter : integer := 0; variable dataToWrite : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := ( others => '0'); variable addrToWrite : std_logic_vector((ADDR_WIDTH_A_USAR-1) downto 0) := ( others => '0'); begin -- Primero grabar los datos en la memoria search <= '0'; dataToCompare <= (others => '0'); operationID <= (others => '0'); dataToWrite := x"10000000"; porta_wr <= '0'; porta_waddr <= (others => '0'); porta_din <= (others => '0'); wait for 10*clk_period; porta_wr <= '0'; porta_waddr <= addrToWrite; porta_din <= dataToWrite; wait for clk_period; while readWriteCounter < (2**ADDR_WIDTH_A_USAR) loop porta_wr <= '1'; porta_waddr <= addrToWrite; porta_din <= dataToWrite; wait for clk_period; porta_wr <= '0'; wait for clk_period; dataToWrite := dataToWrite+1; addrToWrite := addrToWrite+1; readWriteCounter := readWriteCounter+1; end loop; porta_wr <= '0'; wait for clk_period; search <= '0'; dataToWrite := x"10000005"; wait for clk_period; wait for clk_period; dataToCompare <= dataToWrite; search <= '0'; wait for clk_period; dataToWrite := x"10000006"; dataToCompare <= dataToWrite; wait for clk_period; search <= '0'; wait for clk_period; readWriteCounter := 0; dataToWrite := x"10000000"; addrToWrite := ( others => '0' ); while readWriteCounter < (2**ADDR_WIDTH_A_USAR) loop dataToCompare <= dataToWrite; search <= '1'; wait for clk_period; search <= '0'; wait for clk_period; dataToWrite := dataToWrite+1; addrToWrite := addrToWrite+1; readWriteCounter := readWriteCounter+1; end loop; search <= '0'; wait for clk_period; wait; end process; verification: process variable verifCounter : integer := 0; variable dataToWrite : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := x"10000000"; variable verifDataCounter : std_logic_vector((DATA_WIDTH_A_USAR-1) downto 0) := (others => '0'); begin errorDetected <= '0'; if( rising_edge(clk) ) then if( verifCounter >= (2**ADDR_WIDTH_A_USAR) ) then errorDetected <= '0'; else if (searchFinished = '1') then if( (verifDataCounter/=resultIndex) ) then errorDetected <= '1'; else errorDetected <= '0'; end if; verifCounter := verifCounter+1; dataToWrite := dataToWrite+1; verifDataCounter := verifDataCounter+1; else errorDetected <= '0'; end if; end if; end if; wait; end process verification; end Behavioral;

-- $Id: serport_uart_rxtx.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2007-2016 by Walter F.J. Mueller <[email protected]> -- ------------------------------------------------------------------------------ -- Module Name: serport_uart_rxtx - syn -- Description: serial port UART - transmitter + receiver -- -- Dependencies: serport_uart_rx -- serport_uart_tx -- Test bench: tb/tb_serport_uart_rxtx -- Target Devices: generic -- Tool versions: ise 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33 -- Revision History: -- Date Rev Version Comment -- 2007-06-24 60 1.0 Initial version ------------------------------------------------------------------------------ -- NOTE: for test bench usage a copy of all serport_* entities, with _tb -- !!!! appended to the name, has been created in the /tb sub folder. -- !!!! Ensure to update the copy when this file is changed !! library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.serportlib.all; entity serport_uart_rxtx is -- serial port uart: rx+tx combo generic ( CDWIDTH : positive := 13); -- clk divider width port ( CLK : in slbit; -- clock RESET : in slbit; -- reset CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting RXSD : in slbit; -- receive serial data (uart view) RXDATA : out slv8; -- receiver data out RXVAL : out slbit; -- receiver data valid RXERR : out slbit; -- receiver data error (frame error) RXACT : out slbit; -- receiver active TXSD : out slbit; -- transmit serial data (uart view) TXDATA : in slv8; -- transmit data in TXENA : in slbit; -- transmit data enable TXBUSY : out slbit -- transmit busy ); end serport_uart_rxtx; architecture syn of serport_uart_rxtx is begin RX : serport_uart_rx generic map ( CDWIDTH => CDWIDTH) port map ( CLK => CLK, RESET => RESET, CLKDIV => CLKDIV, RXSD => RXSD, RXDATA => RXDATA, RXVAL => RXVAL, RXERR => RXERR, RXACT => RXACT ); TX : serport_uart_tx generic map ( CDWIDTH => CDWIDTH) port map ( CLK => CLK, RESET => RESET, CLKDIV => CLKDIV, TXSD => TXSD, TXDATA => TXDATA, TXENA => TXENA, TXBUSY => TXBUSY ); end syn;

entity tb_asgn09 is end tb_asgn09; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_asgn09 is signal a, b, c, d : std_logic_vector (1 downto 0); signal sel : std_logic_vector(1 downto 0); signal o : std_logic_vector (3 downto 0); begin dut: entity work.asgn09 port map (a, b, c, d, sel, o); process begin a <= "10"; b <= "01"; c <= "00"; d <= "11"; sel <= "00"; wait for 1 ns; assert o = "1110" severity failure; sel <= "01"; wait for 1 ns; assert o = "1101" severity failure; sel <= "10"; wait for 1 ns; assert o = "1100" severity failure; sel <= "11"; wait for 1 ns; assert o = "1111" severity failure; wait; end process; end behav;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Memoria is port( clk, lectura_escritura, habilitador: in STD_LOGIC; direccion: in STD_LOGIC_VECTOR(3 downto 0); dato_entrada: in STD_LOGIC_VECTOR(2 downto 0); dato_salida: out STD_LOGIC_VECTOR(2 downto 0)); end Memoria; architecture Behavioral of Memoria is constant bits_direccion : integer := 4; constant bits_dato : integer := 3; type Block_ram is array(2**bits_direccion-1 downto 0) of STD_LOGIC_VECTOR(bits_dato-1 downto 0); signal RAM: Block_ram; begin process(clk) begin if clk'event and clk = '1' then if habilitador = '1' then if lectura_escritura = '1' then RAM(conv_integer(direccion)) <= dato_entrada; else dato_salida <= RAM(conv_integer(direccion)); end if; end if; end if; end process; end Behavioral;

-- NEED RESULT: ARCH00382.P1: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P2: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P3: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P4: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P5: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P6: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P7: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P8: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P9: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P10: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P11: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P12: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P13: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P14: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P15: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P16: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382.P17: Multi inertial transactions occurred on concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Old transactions were removed on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: One inertial transaction occurred on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: ARCH00382: Inertial semantics check on a concurrent signal asg passed -- NEED RESULT: P17: Inertial transactions completed entirely passed -- NEED RESULT: P16: Inertial transactions completed entirely passed -- NEED RESULT: P15: Inertial transactions completed entirely passed -- NEED RESULT: P14: Inertial transactions completed entirely passed -- NEED RESULT: P13: Inertial transactions completed entirely passed -- NEED RESULT: P12: Inertial transactions completed entirely passed -- NEED RESULT: P11: Inertial transactions completed entirely passed -- NEED RESULT: P10: Inertial transactions completed entirely passed -- NEED RESULT: P9: Inertial transactions completed entirely passed -- NEED RESULT: P8: Inertial transactions completed entirely passed -- NEED RESULT: P7: Inertial transactions completed entirely passed -- NEED RESULT: P6: Inertial transactions completed entirely passed -- NEED RESULT: P5: Inertial transactions completed entirely passed -- NEED RESULT: P4: Inertial transactions completed entirely passed -- NEED RESULT: P3: Inertial transactions completed entirely passed -- NEED RESULT: P2: Inertial transactions completed entirely passed -- NEED RESULT: P1: Inertial transactions completed entirely passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00382 -- -- AUTHOR: -- -- G. Tominovich -- -- TEST OBJECTIVES: -- -- 9.5 (3) -- 9.5.1 (1) -- 9.5.1 (2) -- -- DESIGN UNIT ORDERING: -- -- ENT00382(ARCH00382) -- ENT00382_Test_Bench(ARCH00382_Test_Bench) -- -- REVISION HISTORY: -- -- 30-JUL-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00382 is end ENT00382 ; -- -- architecture ARCH00382 of ENT00382 is subtype chk_sig_type is integer range -1 to 100 ; signal chk_boolean : chk_sig_type := -1 ; signal chk_bit : chk_sig_type := -1 ; signal chk_severity_level : chk_sig_type := -1 ; signal chk_character : chk_sig_type := -1 ; signal chk_st_enum1 : chk_sig_type := -1 ; signal chk_integer : chk_sig_type := -1 ; signal chk_st_int1 : chk_sig_type := -1 ; signal chk_time : chk_sig_type := -1 ; signal chk_st_phys1 : chk_sig_type := -1 ; signal chk_real : chk_sig_type := -1 ; signal chk_st_real1 : chk_sig_type := -1 ; signal chk_st_rec1 : chk_sig_type := -1 ; signal chk_st_rec2 : chk_sig_type := -1 ; signal chk_st_rec3 : chk_sig_type := -1 ; signal chk_st_arr1 : chk_sig_type := -1 ; signal chk_st_arr2 : chk_sig_type := -1 ; signal chk_st_arr3 : chk_sig_type := -1 ; -- subtype chk_time_type is Time ; signal s_boolean_savt : chk_time_type := 0 ns ; signal s_bit_savt : chk_time_type := 0 ns ; signal s_severity_level_savt : chk_time_type := 0 ns ; signal s_character_savt : chk_time_type := 0 ns ; signal s_st_enum1_savt : chk_time_type := 0 ns ; signal s_integer_savt : chk_time_type := 0 ns ; signal s_st_int1_savt : chk_time_type := 0 ns ; signal s_time_savt : chk_time_type := 0 ns ; signal s_st_phys1_savt : chk_time_type := 0 ns ; signal s_real_savt : chk_time_type := 0 ns ; signal s_st_real1_savt : chk_time_type := 0 ns ; signal s_st_rec1_savt : chk_time_type := 0 ns ; signal s_st_rec2_savt : chk_time_type := 0 ns ; signal s_st_rec3_savt : chk_time_type := 0 ns ; signal s_st_arr1_savt : chk_time_type := 0 ns ; signal s_st_arr2_savt : chk_time_type := 0 ns ; signal s_st_arr3_savt : chk_time_type := 0 ns ; -- subtype chk_cnt_type is Integer ; signal s_boolean_cnt : chk_cnt_type := 0 ; signal s_bit_cnt : chk_cnt_type := 0 ; signal s_severity_level_cnt : chk_cnt_type := 0 ; signal s_character_cnt : chk_cnt_type := 0 ; signal s_st_enum1_cnt : chk_cnt_type := 0 ; signal s_integer_cnt : chk_cnt_type := 0 ; signal s_st_int1_cnt : chk_cnt_type := 0 ; signal s_time_cnt : chk_cnt_type := 0 ; signal s_st_phys1_cnt : chk_cnt_type := 0 ; signal s_real_cnt : chk_cnt_type := 0 ; signal s_st_real1_cnt : chk_cnt_type := 0 ; signal s_st_rec1_cnt : chk_cnt_type := 0 ; signal s_st_rec2_cnt : chk_cnt_type := 0 ; signal s_st_rec3_cnt : chk_cnt_type := 0 ; signal s_st_arr1_cnt : chk_cnt_type := 0 ; signal s_st_arr2_cnt : chk_cnt_type := 0 ; signal s_st_arr3_cnt : chk_cnt_type := 0 ; -- type select_type is range 1 to 6 ; signal boolean_select : select_type := 1 ; signal bit_select : select_type := 1 ; signal severity_level_select : select_type := 1 ; signal character_select : select_type := 1 ; signal st_enum1_select : select_type := 1 ; signal integer_select : select_type := 1 ; signal st_int1_select : select_type := 1 ; signal time_select : select_type := 1 ; signal st_phys1_select : select_type := 1 ; signal real_select : select_type := 1 ; signal st_real1_select : select_type := 1 ; signal st_rec1_select : select_type := 1 ; signal st_rec2_select : select_type := 1 ; signal st_rec3_select : select_type := 1 ; signal st_arr1_select : select_type := 1 ; signal st_arr2_select : select_type := 1 ; signal st_arr3_select : select_type := 1 ; -- signal s_boolean : boolean := c_boolean_1 ; signal s_bit : bit := c_bit_1 ; signal s_severity_level : severity_level := c_severity_level_1 ; signal s_character : character := c_character_1 ; signal s_st_enum1 : st_enum1 := c_st_enum1_1 ; signal s_integer : integer := c_integer_1 ; signal s_st_int1 : st_int1 := c_st_int1_1 ; signal s_time : time := c_time_1 ; signal s_st_phys1 : st_phys1 := c_st_phys1_1 ; signal s_real : real := c_real_1 ; signal s_st_real1 : st_real1 := c_st_real1_1 ; signal s_st_rec1 : st_rec1 := c_st_rec1_1 ; signal s_st_rec2 : st_rec2 := c_st_rec2_1 ; signal s_st_rec3 : st_rec3 := c_st_rec3_1 ; signal s_st_arr1 : st_arr1 := c_st_arr1_1 ; signal s_st_arr2 : st_arr2 := c_st_arr2_1 ; signal s_st_arr3 : st_arr3 := c_st_arr3_1 ; -- begin CHG1 : process variable correct : boolean ; begin case s_boolean_cnt is when 0 => null ; -- s_boolean <= -- c_boolean_2 after 10 ns, -- c_boolean_1 after 20 ns ; -- when 1 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P1" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- boolean_select <= transport 2 ; -- s_boolean <= -- c_boolean_2 after 10 ns , -- c_boolean_1 after 20 ns , -- c_boolean_2 after 30 ns , -- c_boolean_1 after 40 ns ; -- when 3 => correct := s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; boolean_select <= transport 3 ; -- s_boolean <= -- c_boolean_1 after 5 ns ; -- when 4 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; boolean_select <= transport 4 ; -- s_boolean <= -- c_boolean_1 after 100 ns ; -- when 5 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; boolean_select <= transport 5 ; -- s_boolean <= -- c_boolean_2 after 10 ns , -- c_boolean_1 after 20 ns , -- c_boolean_2 after 30 ns , -- c_boolean_1 after 40 ns ; -- when 6 => correct := correct and s_boolean = c_boolean_2 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; boolean_select <= transport 6 ; -- Last transaction above is marked -- s_boolean <= -- c_boolean_1 after 40 ns ; -- when 7 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_boolean = c_boolean_1 and (s_boolean_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_boolean_savt <= transport Std.Standard.Now ; chk_boolean <= transport s_boolean_cnt after (1 us - Std.Standard.Now) ; s_boolean_cnt <= transport s_boolean_cnt + 1 ; wait until (not s_boolean'Quiet) and (s_boolean_savt /= Std.Standard.Now) ; -- end process CHG1 ; -- PGEN_CHKP_1 : process ( chk_boolean ) begin if Std.Standard.Now > 0 ns then test_report ( "P1" , "Inertial transactions completed entirely", chk_boolean = 8 ) ; end if ; end process PGEN_CHKP_1 ; -- -- s_boolean <= c_boolean_2 after 10 ns, c_boolean_1 after 20 ns when boolean_select = 1 else -- c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns when boolean_select = 2 else -- c_boolean_1 after 5 ns when boolean_select = 3 else -- c_boolean_1 after 100 ns when boolean_select = 4 else -- c_boolean_2 after 10 ns , c_boolean_1 after 20 ns , c_boolean_2 after 30 ns , c_boolean_1 after 40 ns when boolean_select = 5 else -- -- Last transaction above is marked c_boolean_1 after 40 ns ; -- CHG2 : process variable correct : boolean ; begin case s_bit_cnt is when 0 => null ; -- s_bit <= -- c_bit_2 after 10 ns, -- c_bit_1 after 20 ns ; -- when 1 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P2" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- bit_select <= transport 2 ; -- s_bit <= -- c_bit_2 after 10 ns , -- c_bit_1 after 20 ns , -- c_bit_2 after 30 ns , -- c_bit_1 after 40 ns ; -- when 3 => correct := s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; bit_select <= transport 3 ; -- s_bit <= -- c_bit_1 after 5 ns ; -- when 4 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; bit_select <= transport 4 ; -- s_bit <= -- c_bit_1 after 100 ns ; -- when 5 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; bit_select <= transport 5 ; -- s_bit <= -- c_bit_2 after 10 ns , -- c_bit_1 after 20 ns , -- c_bit_2 after 30 ns , -- c_bit_1 after 40 ns ; -- when 6 => correct := correct and s_bit = c_bit_2 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; bit_select <= transport 6 ; -- Last transaction above is marked -- s_bit <= -- c_bit_1 after 40 ns ; -- when 7 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_bit = c_bit_1 and (s_bit_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_bit_savt <= transport Std.Standard.Now ; chk_bit <= transport s_bit_cnt after (1 us - Std.Standard.Now) ; s_bit_cnt <= transport s_bit_cnt + 1 ; wait until (not s_bit'Quiet) and (s_bit_savt /= Std.Standard.Now) ; -- end process CHG2 ; -- PGEN_CHKP_2 : process ( chk_bit ) begin if Std.Standard.Now > 0 ns then test_report ( "P2" , "Inertial transactions completed entirely", chk_bit = 8 ) ; end if ; end process PGEN_CHKP_2 ; -- -- s_bit <= c_bit_2 after 10 ns, c_bit_1 after 20 ns when bit_select = 1 else -- c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns when bit_select = 2 else -- c_bit_1 after 5 ns when bit_select = 3 else -- c_bit_1 after 100 ns when bit_select = 4 else -- c_bit_2 after 10 ns , c_bit_1 after 20 ns , c_bit_2 after 30 ns , c_bit_1 after 40 ns when bit_select = 5 else -- -- Last transaction above is marked c_bit_1 after 40 ns ; -- CHG3 : process variable correct : boolean ; begin case s_severity_level_cnt is when 0 => null ; -- s_severity_level <= -- c_severity_level_2 after 10 ns, -- c_severity_level_1 after 20 ns ; -- when 1 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P3" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- severity_level_select <= transport 2 ; -- s_severity_level <= -- c_severity_level_2 after 10 ns , -- c_severity_level_1 after 20 ns , -- c_severity_level_2 after 30 ns , -- c_severity_level_1 after 40 ns ; -- when 3 => correct := s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; severity_level_select <= transport 3 ; -- s_severity_level <= -- c_severity_level_1 after 5 ns ; -- when 4 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; severity_level_select <= transport 4 ; -- s_severity_level <= -- c_severity_level_1 after 100 ns ; -- when 5 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; severity_level_select <= transport 5 ; -- s_severity_level <= -- c_severity_level_2 after 10 ns , -- c_severity_level_1 after 20 ns , -- c_severity_level_2 after 30 ns , -- c_severity_level_1 after 40 ns ; -- when 6 => correct := correct and s_severity_level = c_severity_level_2 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; severity_level_select <= transport 6 ; -- Last transaction above is marked -- s_severity_level <= -- c_severity_level_1 after 40 ns ; -- when 7 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_severity_level = c_severity_level_1 and (s_severity_level_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_severity_level_savt <= transport Std.Standard.Now ; chk_severity_level <= transport s_severity_level_cnt after (1 us - Std.Standard.Now) ; s_severity_level_cnt <= transport s_severity_level_cnt + 1 ; wait until (not s_severity_level'Quiet) and (s_severity_level_savt /= Std.Standard.Now) ; -- end process CHG3 ; -- PGEN_CHKP_3 : process ( chk_severity_level ) begin if Std.Standard.Now > 0 ns then test_report ( "P3" , "Inertial transactions completed entirely", chk_severity_level = 8 ) ; end if ; end process PGEN_CHKP_3 ; -- -- s_severity_level <= c_severity_level_2 after 10 ns, c_severity_level_1 after 20 ns when severity_level_select = 1 else -- c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns when severity_level_select = 2 else -- c_severity_level_1 after 5 ns when severity_level_select = 3 else -- c_severity_level_1 after 100 ns when severity_level_select = 4 else -- c_severity_level_2 after 10 ns , c_severity_level_1 after 20 ns , c_severity_level_2 after 30 ns , c_severity_level_1 after 40 ns when severity_level_select = 5 else -- -- Last transaction above is marked c_severity_level_1 after 40 ns ; -- CHG4 : process variable correct : boolean ; begin case s_character_cnt is when 0 => null ; -- s_character <= -- c_character_2 after 10 ns, -- c_character_1 after 20 ns ; -- when 1 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_character = c_character_1 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P4" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- character_select <= transport 2 ; -- s_character <= -- c_character_2 after 10 ns , -- c_character_1 after 20 ns , -- c_character_2 after 30 ns , -- c_character_1 after 40 ns ; -- when 3 => correct := s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; character_select <= transport 3 ; -- s_character <= -- c_character_1 after 5 ns ; -- when 4 => correct := correct and s_character = c_character_1 and (s_character_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; character_select <= transport 4 ; -- s_character <= -- c_character_1 after 100 ns ; -- when 5 => correct := correct and s_character = c_character_1 and (s_character_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; character_select <= transport 5 ; -- s_character <= -- c_character_2 after 10 ns , -- c_character_1 after 20 ns , -- c_character_2 after 30 ns , -- c_character_1 after 40 ns ; -- when 6 => correct := correct and s_character = c_character_2 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; character_select <= transport 6 ; -- Last transaction above is marked -- s_character <= -- c_character_1 after 40 ns ; -- when 7 => correct := correct and s_character = c_character_1 and (s_character_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_character = c_character_1 and (s_character_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_character_savt <= transport Std.Standard.Now ; chk_character <= transport s_character_cnt after (1 us - Std.Standard.Now) ; s_character_cnt <= transport s_character_cnt + 1 ; wait until (not s_character'Quiet) and (s_character_savt /= Std.Standard.Now) ; -- end process CHG4 ; -- PGEN_CHKP_4 : process ( chk_character ) begin if Std.Standard.Now > 0 ns then test_report ( "P4" , "Inertial transactions completed entirely", chk_character = 8 ) ; end if ; end process PGEN_CHKP_4 ; -- -- s_character <= c_character_2 after 10 ns, c_character_1 after 20 ns when character_select = 1 else -- c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns when character_select = 2 else -- c_character_1 after 5 ns when character_select = 3 else -- c_character_1 after 100 ns when character_select = 4 else -- c_character_2 after 10 ns , c_character_1 after 20 ns , c_character_2 after 30 ns , c_character_1 after 40 ns when character_select = 5 else -- -- Last transaction above is marked c_character_1 after 40 ns ; -- CHG5 : process variable correct : boolean ; begin case s_st_enum1_cnt is when 0 => null ; -- s_st_enum1 <= -- c_st_enum1_2 after 10 ns, -- c_st_enum1_1 after 20 ns ; -- when 1 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P5" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_enum1_select <= transport 2 ; -- s_st_enum1 <= -- c_st_enum1_2 after 10 ns , -- c_st_enum1_1 after 20 ns , -- c_st_enum1_2 after 30 ns , -- c_st_enum1_1 after 40 ns ; -- when 3 => correct := s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; st_enum1_select <= transport 3 ; -- s_st_enum1 <= -- c_st_enum1_1 after 5 ns ; -- when 4 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_select <= transport 4 ; -- s_st_enum1 <= -- c_st_enum1_1 after 100 ns ; -- when 5 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_enum1_select <= transport 5 ; -- s_st_enum1 <= -- c_st_enum1_2 after 10 ns , -- c_st_enum1_1 after 20 ns , -- c_st_enum1_2 after 30 ns , -- c_st_enum1_1 after 40 ns ; -- when 6 => correct := correct and s_st_enum1 = c_st_enum1_2 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_enum1_select <= transport 6 ; -- Last transaction above is marked -- s_st_enum1 <= -- c_st_enum1_1 after 40 ns ; -- when 7 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_enum1 = c_st_enum1_1 and (s_st_enum1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_enum1_savt <= transport Std.Standard.Now ; chk_st_enum1 <= transport s_st_enum1_cnt after (1 us - Std.Standard.Now) ; s_st_enum1_cnt <= transport s_st_enum1_cnt + 1 ; wait until (not s_st_enum1'Quiet) and (s_st_enum1_savt /= Std.Standard.Now) ; -- end process CHG5 ; -- PGEN_CHKP_5 : process ( chk_st_enum1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P5" , "Inertial transactions completed entirely", chk_st_enum1 = 8 ) ; end if ; end process PGEN_CHKP_5 ; -- -- s_st_enum1 <= c_st_enum1_2 after 10 ns, c_st_enum1_1 after 20 ns when st_enum1_select = 1 else -- c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns when st_enum1_select = 2 else -- c_st_enum1_1 after 5 ns when st_enum1_select = 3 else -- c_st_enum1_1 after 100 ns when st_enum1_select = 4 else -- c_st_enum1_2 after 10 ns , c_st_enum1_1 after 20 ns , c_st_enum1_2 after 30 ns , c_st_enum1_1 after 40 ns when st_enum1_select = 5 else -- -- Last transaction above is marked c_st_enum1_1 after 40 ns ; -- CHG6 : process variable correct : boolean ; begin case s_integer_cnt is when 0 => null ; -- s_integer <= -- c_integer_2 after 10 ns, -- c_integer_1 after 20 ns ; -- when 1 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P6" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- integer_select <= transport 2 ; -- s_integer <= -- c_integer_2 after 10 ns , -- c_integer_1 after 20 ns , -- c_integer_2 after 30 ns , -- c_integer_1 after 40 ns ; -- when 3 => correct := s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; integer_select <= transport 3 ; -- s_integer <= -- c_integer_1 after 5 ns ; -- when 4 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; integer_select <= transport 4 ; -- s_integer <= -- c_integer_1 after 100 ns ; -- when 5 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; integer_select <= transport 5 ; -- s_integer <= -- c_integer_2 after 10 ns , -- c_integer_1 after 20 ns , -- c_integer_2 after 30 ns , -- c_integer_1 after 40 ns ; -- when 6 => correct := correct and s_integer = c_integer_2 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; integer_select <= transport 6 ; -- Last transaction above is marked -- s_integer <= -- c_integer_1 after 40 ns ; -- when 7 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_integer = c_integer_1 and (s_integer_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_integer_savt <= transport Std.Standard.Now ; chk_integer <= transport s_integer_cnt after (1 us - Std.Standard.Now) ; s_integer_cnt <= transport s_integer_cnt + 1 ; wait until (not s_integer'Quiet) and (s_integer_savt /= Std.Standard.Now) ; -- end process CHG6 ; -- PGEN_CHKP_6 : process ( chk_integer ) begin if Std.Standard.Now > 0 ns then test_report ( "P6" , "Inertial transactions completed entirely", chk_integer = 8 ) ; end if ; end process PGEN_CHKP_6 ; -- -- s_integer <= c_integer_2 after 10 ns, c_integer_1 after 20 ns when integer_select = 1 else -- c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns when integer_select = 2 else -- c_integer_1 after 5 ns when integer_select = 3 else -- c_integer_1 after 100 ns when integer_select = 4 else -- c_integer_2 after 10 ns , c_integer_1 after 20 ns , c_integer_2 after 30 ns , c_integer_1 after 40 ns when integer_select = 5 else -- -- Last transaction above is marked c_integer_1 after 40 ns ; -- CHG7 : process variable correct : boolean ; begin case s_st_int1_cnt is when 0 => null ; -- s_st_int1 <= -- c_st_int1_2 after 10 ns, -- c_st_int1_1 after 20 ns ; -- when 1 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P7" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_int1_select <= transport 2 ; -- s_st_int1 <= -- c_st_int1_2 after 10 ns , -- c_st_int1_1 after 20 ns , -- c_st_int1_2 after 30 ns , -- c_st_int1_1 after 40 ns ; -- when 3 => correct := s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; st_int1_select <= transport 3 ; -- s_st_int1 <= -- c_st_int1_1 after 5 ns ; -- when 4 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_int1_select <= transport 4 ; -- s_st_int1 <= -- c_st_int1_1 after 100 ns ; -- when 5 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_int1_select <= transport 5 ; -- s_st_int1 <= -- c_st_int1_2 after 10 ns , -- c_st_int1_1 after 20 ns , -- c_st_int1_2 after 30 ns , -- c_st_int1_1 after 40 ns ; -- when 6 => correct := correct and s_st_int1 = c_st_int1_2 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_int1_select <= transport 6 ; -- Last transaction above is marked -- s_st_int1 <= -- c_st_int1_1 after 40 ns ; -- when 7 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_int1 = c_st_int1_1 and (s_st_int1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_int1_savt <= transport Std.Standard.Now ; chk_st_int1 <= transport s_st_int1_cnt after (1 us - Std.Standard.Now) ; s_st_int1_cnt <= transport s_st_int1_cnt + 1 ; wait until (not s_st_int1'Quiet) and (s_st_int1_savt /= Std.Standard.Now) ; -- end process CHG7 ; -- PGEN_CHKP_7 : process ( chk_st_int1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P7" , "Inertial transactions completed entirely", chk_st_int1 = 8 ) ; end if ; end process PGEN_CHKP_7 ; -- -- s_st_int1 <= c_st_int1_2 after 10 ns, c_st_int1_1 after 20 ns when st_int1_select = 1 else -- c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns when st_int1_select = 2 else -- c_st_int1_1 after 5 ns when st_int1_select = 3 else -- c_st_int1_1 after 100 ns when st_int1_select = 4 else -- c_st_int1_2 after 10 ns , c_st_int1_1 after 20 ns , c_st_int1_2 after 30 ns , c_st_int1_1 after 40 ns when st_int1_select = 5 else -- -- Last transaction above is marked c_st_int1_1 after 40 ns ; -- CHG8 : process variable correct : boolean ; begin case s_time_cnt is when 0 => null ; -- s_time <= -- c_time_2 after 10 ns, -- c_time_1 after 20 ns ; -- when 1 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_time = c_time_1 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P8" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- time_select <= transport 2 ; -- s_time <= -- c_time_2 after 10 ns , -- c_time_1 after 20 ns , -- c_time_2 after 30 ns , -- c_time_1 after 40 ns ; -- when 3 => correct := s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; time_select <= transport 3 ; -- s_time <= -- c_time_1 after 5 ns ; -- when 4 => correct := correct and s_time = c_time_1 and (s_time_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; time_select <= transport 4 ; -- s_time <= -- c_time_1 after 100 ns ; -- when 5 => correct := correct and s_time = c_time_1 and (s_time_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; time_select <= transport 5 ; -- s_time <= -- c_time_2 after 10 ns , -- c_time_1 after 20 ns , -- c_time_2 after 30 ns , -- c_time_1 after 40 ns ; -- when 6 => correct := correct and s_time = c_time_2 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; time_select <= transport 6 ; -- Last transaction above is marked -- s_time <= -- c_time_1 after 40 ns ; -- when 7 => correct := correct and s_time = c_time_1 and (s_time_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_time = c_time_1 and (s_time_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_time_savt <= transport Std.Standard.Now ; chk_time <= transport s_time_cnt after (1 us - Std.Standard.Now) ; s_time_cnt <= transport s_time_cnt + 1 ; wait until (not s_time'Quiet) and (s_time_savt /= Std.Standard.Now) ; -- end process CHG8 ; -- PGEN_CHKP_8 : process ( chk_time ) begin if Std.Standard.Now > 0 ns then test_report ( "P8" , "Inertial transactions completed entirely", chk_time = 8 ) ; end if ; end process PGEN_CHKP_8 ; -- -- s_time <= c_time_2 after 10 ns, c_time_1 after 20 ns when time_select = 1 else -- c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns when time_select = 2 else -- c_time_1 after 5 ns when time_select = 3 else -- c_time_1 after 100 ns when time_select = 4 else -- c_time_2 after 10 ns , c_time_1 after 20 ns , c_time_2 after 30 ns , c_time_1 after 40 ns when time_select = 5 else -- -- Last transaction above is marked c_time_1 after 40 ns ; -- CHG9 : process variable correct : boolean ; begin case s_st_phys1_cnt is when 0 => null ; -- s_st_phys1 <= -- c_st_phys1_2 after 10 ns, -- c_st_phys1_1 after 20 ns ; -- when 1 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P9" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_phys1_select <= transport 2 ; -- s_st_phys1 <= -- c_st_phys1_2 after 10 ns , -- c_st_phys1_1 after 20 ns , -- c_st_phys1_2 after 30 ns , -- c_st_phys1_1 after 40 ns ; -- when 3 => correct := s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; st_phys1_select <= transport 3 ; -- s_st_phys1 <= -- c_st_phys1_1 after 5 ns ; -- when 4 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_phys1_select <= transport 4 ; -- s_st_phys1 <= -- c_st_phys1_1 after 100 ns ; -- when 5 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_phys1_select <= transport 5 ; -- s_st_phys1 <= -- c_st_phys1_2 after 10 ns , -- c_st_phys1_1 after 20 ns , -- c_st_phys1_2 after 30 ns , -- c_st_phys1_1 after 40 ns ; -- when 6 => correct := correct and s_st_phys1 = c_st_phys1_2 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_phys1_select <= transport 6 ; -- Last transaction above is marked -- s_st_phys1 <= -- c_st_phys1_1 after 40 ns ; -- when 7 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_phys1 = c_st_phys1_1 and (s_st_phys1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_phys1_savt <= transport Std.Standard.Now ; chk_st_phys1 <= transport s_st_phys1_cnt after (1 us - Std.Standard.Now) ; s_st_phys1_cnt <= transport s_st_phys1_cnt + 1 ; wait until (not s_st_phys1'Quiet) and (s_st_phys1_savt /= Std.Standard.Now) ; -- end process CHG9 ; -- PGEN_CHKP_9 : process ( chk_st_phys1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P9" , "Inertial transactions completed entirely", chk_st_phys1 = 8 ) ; end if ; end process PGEN_CHKP_9 ; -- -- s_st_phys1 <= c_st_phys1_2 after 10 ns, c_st_phys1_1 after 20 ns when st_phys1_select = 1 else -- c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns when st_phys1_select = 2 else -- c_st_phys1_1 after 5 ns when st_phys1_select = 3 else -- c_st_phys1_1 after 100 ns when st_phys1_select = 4 else -- c_st_phys1_2 after 10 ns , c_st_phys1_1 after 20 ns , c_st_phys1_2 after 30 ns , c_st_phys1_1 after 40 ns when st_phys1_select = 5 else -- -- Last transaction above is marked c_st_phys1_1 after 40 ns ; -- CHG10 : process variable correct : boolean ; begin case s_real_cnt is when 0 => null ; -- s_real <= -- c_real_2 after 10 ns, -- c_real_1 after 20 ns ; -- when 1 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_real = c_real_1 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P10" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- real_select <= transport 2 ; -- s_real <= -- c_real_2 after 10 ns , -- c_real_1 after 20 ns , -- c_real_2 after 30 ns , -- c_real_1 after 40 ns ; -- when 3 => correct := s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; real_select <= transport 3 ; -- s_real <= -- c_real_1 after 5 ns ; -- when 4 => correct := correct and s_real = c_real_1 and (s_real_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; real_select <= transport 4 ; -- s_real <= -- c_real_1 after 100 ns ; -- when 5 => correct := correct and s_real = c_real_1 and (s_real_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; real_select <= transport 5 ; -- s_real <= -- c_real_2 after 10 ns , -- c_real_1 after 20 ns , -- c_real_2 after 30 ns , -- c_real_1 after 40 ns ; -- when 6 => correct := correct and s_real = c_real_2 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; real_select <= transport 6 ; -- Last transaction above is marked -- s_real <= -- c_real_1 after 40 ns ; -- when 7 => correct := correct and s_real = c_real_1 and (s_real_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_real = c_real_1 and (s_real_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_real_savt <= transport Std.Standard.Now ; chk_real <= transport s_real_cnt after (1 us - Std.Standard.Now) ; s_real_cnt <= transport s_real_cnt + 1 ; wait until (not s_real'Quiet) and (s_real_savt /= Std.Standard.Now) ; -- end process CHG10 ; -- PGEN_CHKP_10 : process ( chk_real ) begin if Std.Standard.Now > 0 ns then test_report ( "P10" , "Inertial transactions completed entirely", chk_real = 8 ) ; end if ; end process PGEN_CHKP_10 ; -- -- s_real <= c_real_2 after 10 ns, c_real_1 after 20 ns when real_select = 1 else -- c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns when real_select = 2 else -- c_real_1 after 5 ns when real_select = 3 else -- c_real_1 after 100 ns when real_select = 4 else -- c_real_2 after 10 ns , c_real_1 after 20 ns , c_real_2 after 30 ns , c_real_1 after 40 ns when real_select = 5 else -- -- Last transaction above is marked c_real_1 after 40 ns ; -- CHG11 : process variable correct : boolean ; begin case s_st_real1_cnt is when 0 => null ; -- s_st_real1 <= -- c_st_real1_2 after 10 ns, -- c_st_real1_1 after 20 ns ; -- when 1 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P11" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_real1_select <= transport 2 ; -- s_st_real1 <= -- c_st_real1_2 after 10 ns , -- c_st_real1_1 after 20 ns , -- c_st_real1_2 after 30 ns , -- c_st_real1_1 after 40 ns ; -- when 3 => correct := s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; st_real1_select <= transport 3 ; -- s_st_real1 <= -- c_st_real1_1 after 5 ns ; -- when 4 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real1_select <= transport 4 ; -- s_st_real1 <= -- c_st_real1_1 after 100 ns ; -- when 5 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_real1_select <= transport 5 ; -- s_st_real1 <= -- c_st_real1_2 after 10 ns , -- c_st_real1_1 after 20 ns , -- c_st_real1_2 after 30 ns , -- c_st_real1_1 after 40 ns ; -- when 6 => correct := correct and s_st_real1 = c_st_real1_2 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_real1_select <= transport 6 ; -- Last transaction above is marked -- s_st_real1 <= -- c_st_real1_1 after 40 ns ; -- when 7 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_real1 = c_st_real1_1 and (s_st_real1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_real1_savt <= transport Std.Standard.Now ; chk_st_real1 <= transport s_st_real1_cnt after (1 us - Std.Standard.Now) ; s_st_real1_cnt <= transport s_st_real1_cnt + 1 ; wait until (not s_st_real1'Quiet) and (s_st_real1_savt /= Std.Standard.Now) ; -- end process CHG11 ; -- PGEN_CHKP_11 : process ( chk_st_real1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P11" , "Inertial transactions completed entirely", chk_st_real1 = 8 ) ; end if ; end process PGEN_CHKP_11 ; -- -- s_st_real1 <= c_st_real1_2 after 10 ns, c_st_real1_1 after 20 ns when st_real1_select = 1 else -- c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns when st_real1_select = 2 else -- c_st_real1_1 after 5 ns when st_real1_select = 3 else -- c_st_real1_1 after 100 ns when st_real1_select = 4 else -- c_st_real1_2 after 10 ns , c_st_real1_1 after 20 ns , c_st_real1_2 after 30 ns , c_st_real1_1 after 40 ns when st_real1_select = 5 else -- -- Last transaction above is marked c_st_real1_1 after 40 ns ; -- CHG12 : process variable correct : boolean ; begin case s_st_rec1_cnt is when 0 => null ; -- s_st_rec1 <= -- c_st_rec1_2 after 10 ns, -- c_st_rec1_1 after 20 ns ; -- when 1 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P12" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec1_select <= transport 2 ; -- s_st_rec1 <= -- c_st_rec1_2 after 10 ns , -- c_st_rec1_1 after 20 ns , -- c_st_rec1_2 after 30 ns , -- c_st_rec1_1 after 40 ns ; -- when 3 => correct := s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; st_rec1_select <= transport 3 ; -- s_st_rec1 <= -- c_st_rec1_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_select <= transport 4 ; -- s_st_rec1 <= -- c_st_rec1_1 after 100 ns ; -- when 5 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec1_select <= transport 5 ; -- s_st_rec1 <= -- c_st_rec1_2 after 10 ns , -- c_st_rec1_1 after 20 ns , -- c_st_rec1_2 after 30 ns , -- c_st_rec1_1 after 40 ns ; -- when 6 => correct := correct and s_st_rec1 = c_st_rec1_2 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec1_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec1 <= -- c_st_rec1_1 after 40 ns ; -- when 7 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec1 = c_st_rec1_1 and (s_st_rec1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec1_savt <= transport Std.Standard.Now ; chk_st_rec1 <= transport s_st_rec1_cnt after (1 us - Std.Standard.Now) ; s_st_rec1_cnt <= transport s_st_rec1_cnt + 1 ; wait until (not s_st_rec1'Quiet) and (s_st_rec1_savt /= Std.Standard.Now) ; -- end process CHG12 ; -- PGEN_CHKP_12 : process ( chk_st_rec1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P12" , "Inertial transactions completed entirely", chk_st_rec1 = 8 ) ; end if ; end process PGEN_CHKP_12 ; -- -- s_st_rec1 <= c_st_rec1_2 after 10 ns, c_st_rec1_1 after 20 ns when st_rec1_select = 1 else -- c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns when st_rec1_select = 2 else -- c_st_rec1_1 after 5 ns when st_rec1_select = 3 else -- c_st_rec1_1 after 100 ns when st_rec1_select = 4 else -- c_st_rec1_2 after 10 ns , c_st_rec1_1 after 20 ns , c_st_rec1_2 after 30 ns , c_st_rec1_1 after 40 ns when st_rec1_select = 5 else -- -- Last transaction above is marked c_st_rec1_1 after 40 ns ; -- CHG13 : process variable correct : boolean ; begin case s_st_rec2_cnt is when 0 => null ; -- s_st_rec2 <= -- c_st_rec2_2 after 10 ns, -- c_st_rec2_1 after 20 ns ; -- when 1 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P13" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec2_select <= transport 2 ; -- s_st_rec2 <= -- c_st_rec2_2 after 10 ns , -- c_st_rec2_1 after 20 ns , -- c_st_rec2_2 after 30 ns , -- c_st_rec2_1 after 40 ns ; -- when 3 => correct := s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; st_rec2_select <= transport 3 ; -- s_st_rec2 <= -- c_st_rec2_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_select <= transport 4 ; -- s_st_rec2 <= -- c_st_rec2_1 after 100 ns ; -- when 5 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec2_select <= transport 5 ; -- s_st_rec2 <= -- c_st_rec2_2 after 10 ns , -- c_st_rec2_1 after 20 ns , -- c_st_rec2_2 after 30 ns , -- c_st_rec2_1 after 40 ns ; -- when 6 => correct := correct and s_st_rec2 = c_st_rec2_2 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec2_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec2 <= -- c_st_rec2_1 after 40 ns ; -- when 7 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec2 = c_st_rec2_1 and (s_st_rec2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec2_savt <= transport Std.Standard.Now ; chk_st_rec2 <= transport s_st_rec2_cnt after (1 us - Std.Standard.Now) ; s_st_rec2_cnt <= transport s_st_rec2_cnt + 1 ; wait until (not s_st_rec2'Quiet) and (s_st_rec2_savt /= Std.Standard.Now) ; -- end process CHG13 ; -- PGEN_CHKP_13 : process ( chk_st_rec2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P13" , "Inertial transactions completed entirely", chk_st_rec2 = 8 ) ; end if ; end process PGEN_CHKP_13 ; -- -- s_st_rec2 <= c_st_rec2_2 after 10 ns, c_st_rec2_1 after 20 ns when st_rec2_select = 1 else -- c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns when st_rec2_select = 2 else -- c_st_rec2_1 after 5 ns when st_rec2_select = 3 else -- c_st_rec2_1 after 100 ns when st_rec2_select = 4 else -- c_st_rec2_2 after 10 ns , c_st_rec2_1 after 20 ns , c_st_rec2_2 after 30 ns , c_st_rec2_1 after 40 ns when st_rec2_select = 5 else -- -- Last transaction above is marked c_st_rec2_1 after 40 ns ; -- CHG14 : process variable correct : boolean ; begin case s_st_rec3_cnt is when 0 => null ; -- s_st_rec3 <= -- c_st_rec3_2 after 10 ns, -- c_st_rec3_1 after 20 ns ; -- when 1 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P14" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_rec3_select <= transport 2 ; -- s_st_rec3 <= -- c_st_rec3_2 after 10 ns , -- c_st_rec3_1 after 20 ns , -- c_st_rec3_2 after 30 ns , -- c_st_rec3_1 after 40 ns ; -- when 3 => correct := s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; st_rec3_select <= transport 3 ; -- s_st_rec3 <= -- c_st_rec3_1 after 5 ns ; -- when 4 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 4 ; -- s_st_rec3 <= -- c_st_rec3_1 after 100 ns ; -- when 5 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 5 ; -- s_st_rec3 <= -- c_st_rec3_2 after 10 ns , -- c_st_rec3_1 after 20 ns , -- c_st_rec3_2 after 30 ns , -- c_st_rec3_1 after 40 ns ; -- when 6 => correct := correct and s_st_rec3 = c_st_rec3_2 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_rec3_select <= transport 6 ; -- Last transaction above is marked -- s_st_rec3 <= -- c_st_rec3_1 after 40 ns ; -- when 7 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_rec3 = c_st_rec3_1 and (s_st_rec3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_rec3_savt <= transport Std.Standard.Now ; chk_st_rec3 <= transport s_st_rec3_cnt after (1 us - Std.Standard.Now) ; s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ; wait until (not s_st_rec3'Quiet) and (s_st_rec3_savt /= Std.Standard.Now) ; -- end process CHG14 ; -- PGEN_CHKP_14 : process ( chk_st_rec3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P14" , "Inertial transactions completed entirely", chk_st_rec3 = 8 ) ; end if ; end process PGEN_CHKP_14 ; -- -- s_st_rec3 <= c_st_rec3_2 after 10 ns, c_st_rec3_1 after 20 ns when st_rec3_select = 1 else -- c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns when st_rec3_select = 2 else -- c_st_rec3_1 after 5 ns when st_rec3_select = 3 else -- c_st_rec3_1 after 100 ns when st_rec3_select = 4 else -- c_st_rec3_2 after 10 ns , c_st_rec3_1 after 20 ns , c_st_rec3_2 after 30 ns , c_st_rec3_1 after 40 ns when st_rec3_select = 5 else -- -- Last transaction above is marked c_st_rec3_1 after 40 ns ; -- CHG15 : process variable correct : boolean ; begin case s_st_arr1_cnt is when 0 => null ; -- s_st_arr1 <= -- c_st_arr1_2 after 10 ns, -- c_st_arr1_1 after 20 ns ; -- when 1 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P15" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr1_select <= transport 2 ; -- s_st_arr1 <= -- c_st_arr1_2 after 10 ns , -- c_st_arr1_1 after 20 ns , -- c_st_arr1_2 after 30 ns , -- c_st_arr1_1 after 40 ns ; -- when 3 => correct := s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; st_arr1_select <= transport 3 ; -- s_st_arr1 <= -- c_st_arr1_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr1_select <= transport 4 ; -- s_st_arr1 <= -- c_st_arr1_1 after 100 ns ; -- when 5 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr1_select <= transport 5 ; -- s_st_arr1 <= -- c_st_arr1_2 after 10 ns , -- c_st_arr1_1 after 20 ns , -- c_st_arr1_2 after 30 ns , -- c_st_arr1_1 after 40 ns ; -- when 6 => correct := correct and s_st_arr1 = c_st_arr1_2 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr1_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr1 <= -- c_st_arr1_1 after 40 ns ; -- when 7 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr1 = c_st_arr1_1 and (s_st_arr1_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr1_savt <= transport Std.Standard.Now ; chk_st_arr1 <= transport s_st_arr1_cnt after (1 us - Std.Standard.Now) ; s_st_arr1_cnt <= transport s_st_arr1_cnt + 1 ; wait until (not s_st_arr1'Quiet) and (s_st_arr1_savt /= Std.Standard.Now) ; -- end process CHG15 ; -- PGEN_CHKP_15 : process ( chk_st_arr1 ) begin if Std.Standard.Now > 0 ns then test_report ( "P15" , "Inertial transactions completed entirely", chk_st_arr1 = 8 ) ; end if ; end process PGEN_CHKP_15 ; -- -- s_st_arr1 <= c_st_arr1_2 after 10 ns, c_st_arr1_1 after 20 ns when st_arr1_select = 1 else -- c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns when st_arr1_select = 2 else -- c_st_arr1_1 after 5 ns when st_arr1_select = 3 else -- c_st_arr1_1 after 100 ns when st_arr1_select = 4 else -- c_st_arr1_2 after 10 ns , c_st_arr1_1 after 20 ns , c_st_arr1_2 after 30 ns , c_st_arr1_1 after 40 ns when st_arr1_select = 5 else -- -- Last transaction above is marked c_st_arr1_1 after 40 ns ; -- CHG16 : process variable correct : boolean ; begin case s_st_arr2_cnt is when 0 => null ; -- s_st_arr2 <= -- c_st_arr2_2 after 10 ns, -- c_st_arr2_1 after 20 ns ; -- when 1 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P16" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr2_select <= transport 2 ; -- s_st_arr2 <= -- c_st_arr2_2 after 10 ns , -- c_st_arr2_1 after 20 ns , -- c_st_arr2_2 after 30 ns , -- c_st_arr2_1 after 40 ns ; -- when 3 => correct := s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; st_arr2_select <= transport 3 ; -- s_st_arr2 <= -- c_st_arr2_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_select <= transport 4 ; -- s_st_arr2 <= -- c_st_arr2_1 after 100 ns ; -- when 5 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr2_select <= transport 5 ; -- s_st_arr2 <= -- c_st_arr2_2 after 10 ns , -- c_st_arr2_1 after 20 ns , -- c_st_arr2_2 after 30 ns , -- c_st_arr2_1 after 40 ns ; -- when 6 => correct := correct and s_st_arr2 = c_st_arr2_2 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr2_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr2 <= -- c_st_arr2_1 after 40 ns ; -- when 7 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr2 = c_st_arr2_1 and (s_st_arr2_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr2_savt <= transport Std.Standard.Now ; chk_st_arr2 <= transport s_st_arr2_cnt after (1 us - Std.Standard.Now) ; s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ; wait until (not s_st_arr2'Quiet) and (s_st_arr2_savt /= Std.Standard.Now) ; -- end process CHG16 ; -- PGEN_CHKP_16 : process ( chk_st_arr2 ) begin if Std.Standard.Now > 0 ns then test_report ( "P16" , "Inertial transactions completed entirely", chk_st_arr2 = 8 ) ; end if ; end process PGEN_CHKP_16 ; -- -- s_st_arr2 <= c_st_arr2_2 after 10 ns, c_st_arr2_1 after 20 ns when st_arr2_select = 1 else -- c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns when st_arr2_select = 2 else -- c_st_arr2_1 after 5 ns when st_arr2_select = 3 else -- c_st_arr2_1 after 100 ns when st_arr2_select = 4 else -- c_st_arr2_2 after 10 ns , c_st_arr2_1 after 20 ns , c_st_arr2_2 after 30 ns , c_st_arr2_1 after 40 ns when st_arr2_select = 5 else -- -- Last transaction above is marked c_st_arr2_1 after 40 ns ; -- CHG17 : process variable correct : boolean ; begin case s_st_arr3_cnt is when 0 => null ; -- s_st_arr3 <= -- c_st_arr3_2 after 10 ns, -- c_st_arr3_1 after 20 ns ; -- when 1 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; -- when 2 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382.P17" , "Multi inertial transactions occurred on " & "concurrent signal asg", correct ) ; -- st_arr3_select <= transport 2 ; -- s_st_arr3 <= -- c_st_arr3_2 after 10 ns , -- c_st_arr3_1 after 20 ns , -- c_st_arr3_2 after 30 ns , -- c_st_arr3_1 after 40 ns ; -- when 3 => correct := s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; st_arr3_select <= transport 3 ; -- s_st_arr3 <= -- c_st_arr3_1 after 5 ns ; -- when 4 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 5 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr3_select <= transport 4 ; -- s_st_arr3 <= -- c_st_arr3_1 after 100 ns ; -- when 5 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 100 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Old transactions were removed on a " & "concurrent signal asg", correct ) ; st_arr3_select <= transport 5 ; -- s_st_arr3 <= -- c_st_arr3_2 after 10 ns , -- c_st_arr3_1 after 20 ns , -- c_st_arr3_2 after 30 ns , -- c_st_arr3_1 after 40 ns ; -- when 6 => correct := correct and s_st_arr3 = c_st_arr3_2 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "One inertial transaction occurred on a " & "concurrent signal asg", correct ) ; st_arr3_select <= transport 6 ; -- Last transaction above is marked -- s_st_arr3 <= -- c_st_arr3_1 after 40 ns ; -- when 7 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 30 ns) = Std.Standard.Now ; -- when 8 => correct := correct and s_st_arr3 = c_st_arr3_1 and (s_st_arr3_savt + 10 ns) = Std.Standard.Now ; test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", correct ) ; -- when others => -- No more transactions should have occurred test_report ( "ARCH00382" , "Inertial semantics check on a concurrent " & "signal asg", false ) ; -- end case ; -- s_st_arr3_savt <= transport Std.Standard.Now ; chk_st_arr3 <= transport s_st_arr3_cnt after (1 us - Std.Standard.Now) ; s_st_arr3_cnt <= transport s_st_arr3_cnt + 1 ; wait until (not s_st_arr3'Quiet) and (s_st_arr3_savt /= Std.Standard.Now) ; -- end process CHG17 ; -- PGEN_CHKP_17 : process ( chk_st_arr3 ) begin if Std.Standard.Now > 0 ns then test_report ( "P17" , "Inertial transactions completed entirely", chk_st_arr3 = 8 ) ; end if ; end process PGEN_CHKP_17 ; -- -- s_st_arr3 <= c_st_arr3_2 after 10 ns, c_st_arr3_1 after 20 ns when st_arr3_select = 1 else -- c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns when st_arr3_select = 2 else -- c_st_arr3_1 after 5 ns when st_arr3_select = 3 else -- c_st_arr3_1 after 100 ns when st_arr3_select = 4 else -- c_st_arr3_2 after 10 ns , c_st_arr3_1 after 20 ns , c_st_arr3_2 after 30 ns , c_st_arr3_1 after 40 ns when st_arr3_select = 5 else -- -- Last transaction above is marked c_st_arr3_1 after 40 ns ; -- end ARCH00382 ; -- -- use WORK.STANDARD_TYPES.all ; entity ENT00382_Test_Bench is end ENT00382_Test_Bench ; -- -- architecture ARCH00382_Test_Bench of ENT00382_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00382 ( ARCH00382 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00382_Test_Bench ;

entity t1 is end entity; architecture a of t1 is constant SimulationTime_c : time := 0 fs; begin end;

------------------------------------------------------------------------------- -- Title : Testbench for design "SinGen" ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library ieee_proposed; use ieee_proposed.fixed_float_types.all; use ieee_proposed.fixed_pkg.all; use work.Global.all; ------------------------------------------------------------------------------- entity SinGen_tb is end entity SinGen_tb; ------------------------------------------------------------------------------- architecture Bhv of SinGen_tb is -- component generics constant periode_g : time := 100 us; constant sample_time_g : time := 200 ns; -- component ports signal data_o : audio_data_t; signal data_valid_o : std_ulogic; -- clock signal Clk : std_logic := '1'; begin -- architecture Bhv -- component instantiation DUT : entity work.SinGen generic map ( periode_g => periode_g, sample_time_g => sample_time_g) port map ( clk_i => Clk, data_o => data_o, data_valid_o => data_valid_o); -- clock generation Clk <= not Clk after 10 ns; -- waveform generation WaveGen_Proc : process begin -- insert signal assignments here wait; end process WaveGen_Proc; end architecture Bhv; -------------------------------------------------------------------------------

------------------------------------------------------------------------------- -- -- Project: <Floating Point Unit Core> -- -- Description: division entity for the division unit ------------------------------------------------------------------------------- -- -- 100101011010011100100 -- 110000111011100100000 -- 100000111011000101101 -- 100010111100101111001 -- 110000111011101101001 -- 010000001011101001010 -- 110100111001001100001 -- 110111010000001100111 -- 110110111110001011101 -- 101110110010111101000 -- 100000010111000000000 -- -- Author: Jidan Al-eryani -- E-mail: [email protected] -- -- Copyright (C) 2006 -- -- This source file may be used and distributed without -- restriction provided that this copyright statement is not -- removed from the file and that any derivative work contains -- the original copyright notice and the associated disclaimer. -- -- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY -- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR -- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE -- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT -- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; library work; use work.fpupack.all; entity serial_div is port( clk_i : in std_logic; dvdnd_i : in std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0); -- hidden(1) & fraction(23) dvsor_i : in std_logic_vector(FRAC_WIDTH+3 downto 0); sign_dvd_i : in std_logic; sign_div_i : in std_logic; start_i : in std_logic; ready_o : out std_logic; qutnt_o : out std_logic_vector(FRAC_WIDTH+3 downto 0); rmndr_o : out std_logic_vector(FRAC_WIDTH+3 downto 0); sign_o : out std_logic; div_zero_o : out std_logic ); end serial_div; architecture rtl of serial_div is type t_state is (waiting,busy); signal s_qutnt_o, s_rmndr_o : std_logic_vector(FRAC_WIDTH+3 downto 0); signal s_dvdnd_i : std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0); signal s_dvsor_i : std_logic_vector(FRAC_WIDTH+3 downto 0); signal s_sign_dvd_i, s_sign_div_i, s_sign_o : std_logic; signal s_div_zero_o : std_logic; signal s_start_i, s_ready_o : std_logic; signal s_state : t_state; signal s_count : integer range 0 to FRAC_WIDTH+3; signal s_dvd : std_logic_vector(FRAC_WIDTH+3 downto 0); begin -- Input Register process(clk_i) begin if rising_edge(clk_i) then s_dvdnd_i <= dvdnd_i; s_dvsor_i <= dvsor_i; s_sign_dvd_i<= sign_dvd_i; s_sign_div_i<= sign_div_i; s_start_i <= start_i; end if; end process; -- Output Register --process(clk_i) --begin -- if rising_edge(clk_i) then qutnt_o <= s_qutnt_o; rmndr_o <= s_rmndr_o; sign_o <= s_sign_o; ready_o <= s_ready_o; div_zero_o <= s_div_zero_o; -- end if; --end process; s_sign_o <= sign_dvd_i xor sign_div_i; s_div_zero_o <= '1' when or_reduce(s_dvsor_i)='0' and or_reduce(s_dvdnd_i)='1' else '0'; -- FSM process(clk_i) begin if rising_edge(clk_i) then if s_start_i ='1' then s_state <= busy; s_count <= 26; elsif s_count=0 and s_state=busy then s_state <= waiting; s_ready_o <= '1'; s_count <=26; elsif s_state=busy then s_count <= s_count - 1; else s_state <= waiting; s_ready_o <= '0'; end if; end if; end process; process(clk_i) variable v_div : std_logic_vector(26 downto 0); begin if rising_edge(clk_i) then if s_state=busy then if s_count=26 then v_div := "000" & s_dvdnd_i(49 downto 26); else v_div:= s_dvd; end if; if v_div < s_dvsor_i then s_qutnt_o(s_count) <= '0'; else s_qutnt_o(s_count) <= '1'; v_div:=v_div-s_dvsor_i; end if; s_rmndr_o <= v_div; s_dvd <= v_div(25 downto 0)&'0'; end if; end if; end process; end rtl;

-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- not in book entity computer_system is end entity computer_system; -- end not in book architecture abstract of computer_system is subtype word is bit_vector(31 downto 0); signal address : natural; signal read_data, write_data : word; signal mem_read, mem_write : bit := '0'; signal mem_ready : bit := '0'; begin cpu : process is variable instr_reg : word; variable PC : natural; -- . . . -- other declarations begin loop address <= PC; mem_read <= '1'; wait until mem_ready = '1'; instr_reg := read_data; mem_read <= '0'; wait until mem_ready = '0'; PC := PC + 4; -- . . . -- execute the instruction end loop; end process cpu; memory : process is type memory_array is array (0 to 2**14 - 1) of word; variable store : memory_array := ( -- . . . -- not in book 0 => X"0000_0000", 1 => X"0000_0004", 2 => X"0000_0008", 3 => X"0000_000C", 4 => X"0000_0010", 5 => X"0000_0014", others => X"0000_0000" -- end not in book ); begin wait until mem_read = '1' or mem_write = '1'; if mem_read = '1' then read_data <= store( address / 4 ); mem_ready <= '1'; wait until mem_read = '0'; mem_ready <= '0'; else -- . . . -- perform write access end if; end process memory; end architecture abstract;

library verilog; use verilog.vl_types.all; entity pll_dps_lcell_comb is generic( family : string := "Stratix V"; lut_mask : vl_logic_vector(0 to 63) := (Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0, Hi1, Hi0); dont_touch : string := "on" ); port( dataa : in vl_logic; datab : in vl_logic; datac : in vl_logic; datad : in vl_logic; datae : in vl_logic; dataf : in vl_logic; combout : out vl_logic ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of family : constant is 1; attribute mti_svvh_generic_type of lut_mask : constant is 1; attribute mti_svvh_generic_type of dont_touch : constant is 1; end pll_dps_lcell_comb;

library verilog; use verilog.vl_types.all; entity EX_MEM is port( Clk : in vl_logic; stall : in vl_logic; flush : in vl_logic; Branch_addr_EX : in vl_logic_vector(31 downto 0); op_EX : in vl_logic_vector(5 downto 0); Condition_EX : in vl_logic_vector(2 downto 0); Branch_EX : in vl_logic; MemWrite_EX : in vl_logic; RegWrite_EX : in vl_logic; MemRead_EX : in vl_logic; MemData_EX : in vl_logic_vector(31 downto 0); WBData_EX : in vl_logic_vector(31 downto 0); Less_EX : in vl_logic; Zero_EX : in vl_logic; Overflow_EX : in vl_logic; Rd_EX : in vl_logic_vector(4 downto 0); Branch_addr_MEM : out vl_logic_vector(31 downto 0); op_MEM : out vl_logic_vector(5 downto 0); Condition_MEM : out vl_logic_vector(2 downto 0); Branch_MEM : out vl_logic; MemWrite_MEM : out vl_logic; RegWrite_MEM : out vl_logic; MemRead_MEM : out vl_logic; MemData_MEM : out vl_logic_vector(31 downto 0); WBData_MEM : out vl_logic_vector(31 downto 0); Less_MEM : out vl_logic; Zero_MEM : out vl_logic; Overflow_MEM : out vl_logic; Rd_MEM : out vl_logic_vector(4 downto 0) ); end EX_MEM;

---- -- Original author: Blake Johnson -- Copyright 2015,2016 Raytheon BBN Technologies -- -- A basic down counter. ---- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity DownCounter is generic ( nbits : natural := 8 ); port ( clk : in std_logic; rst : in std_logic; en : in std_logic; load_value : in std_logic_vector(nbits-1 downto 0); load : in std_logic; Q : out std_logic_vector(nbits-1 downto 0) ); end DownCounter; architecture arch of DownCounter is signal value : std_logic_vector(nbits-1 downto 0) := (others => '0'); begin Q <= value; main: process ( clk ) begin if rising_edge(clk) then if rst = '1' then value <= (others => '0'); else if load = '1' then value <= load_value; elsif en = '1' then value <= std_logic_vector(unsigned(value) - 1); end if; end if; end if; end process; end arch;

------------------------------------------------------------------------------- -- axi_datamover_mm2s_full_wrap.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mm2s_full_wrap.vhd -- -- Description: -- This file implements the DataMover MM2S Full Wrapper. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -- axi_datamover Library Modules library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_reset; use axi_datamover_v5_1.axi_datamover_cmd_status; use axi_datamover_v5_1.axi_datamover_pcc; use axi_datamover_v5_1.axi_datamover_addr_cntl; use axi_datamover_v5_1.axi_datamover_rddata_cntl; use axi_datamover_v5_1.axi_datamover_rd_status_cntl; use axi_datamover_v5_1.axi_datamover_mm2s_dre; Use axi_datamover_v5_1.axi_datamover_rd_sf; use axi_datamover_v5_1.axi_datamover_skid_buf; ------------------------------------------------------------------------------- entity axi_datamover_mm2s_full_wrap is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 1; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Lite MM2S functionality C_MM2S_ARID : Integer range 0 to 255 := 8; -- Specifies the constant value to output on -- the ARID output port C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_MM2S_MDATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_MM2S_SDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_TAG_WIDTH : Integer range 1 to 8 := 4 ; -- Width of the TAG field C_INCLUDE_MM2S_GP_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the incllusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit Store and Forward -- 1 = Include Store and Forward C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_SKID_BUF : string := "11111"; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input --------------------------------- mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- MM2S Halt request input control -------------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------------- -- Error discrete output ------------------------------------ mm2s_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------------------- -- Optional MM2S Command and Status Clock and Reset --------- -- Used when C_MM2S_STSCMD_IS_ASYNC = 1 -- mm2s_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) ---------------------------------------------------- mm2s_cmd_wvalid : in std_logic; -- mm2s_cmd_wready : out std_logic; -- mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_MM2S_ADDR_WIDTH+36)-1 downto 0); -- ------------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------- mm2s_sts_wvalid : out std_logic; -- mm2s_sts_wready : in std_logic; -- mm2s_sts_wdata : out std_logic_vector(7 downto 0); -- mm2s_sts_wstrb : out std_logic_vector(0 downto 0); -- mm2s_sts_wlast : out std_logic; -- --------------------------------------------------------------- -- Address Posting contols ------------------------------------ mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- --------------------------------------------------------------- -- MM2S AXI Address Channel I/O --------------------------------------- mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- -- mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------ -- Currently unsupported AXI Address Channel output signals ------------ -- addr2axi_alock : out std_logic_vector(2 downto 0); -- -- addr2axi_acache : out std_logic_vector(4 downto 0); -- -- addr2axi_aqos : out std_logic_vector(3 downto 0); -- -- addr2axi_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------------ -- MM2S AXI MMap Read Data Channel I/O ----------------------------------------- mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); -- mm2s_rresp : In std_logic_vector(1 downto 0); -- mm2s_rlast : In std_logic; -- mm2s_rvalid : In std_logic; -- mm2s_rready : Out std_logic; -- --------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------- mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); -- mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); -- mm2s_strm_wlast : Out std_logic; -- mm2s_strm_wvalid : Out std_logic; -- mm2s_strm_wready : In std_logic; -- ---------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------ ); end entity axi_datamover_mm2s_full_wrap; architecture implementation of axi_datamover_mm2s_full_wrap is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ---------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_calc_rdmux_sel_bits -- -- Function Description: -- This function calculates the number of address bits needed for -- the Read data mux select control. -- ------------------------------------------------------------------- function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is Variable num_addr_bits_needed : Integer range 1 to 7 := 1; begin case mmap_dwidth_value is when 32 => num_addr_bits_needed := 2; when 64 => num_addr_bits_needed := 3; when 128 => num_addr_bits_needed := 4; when 256 => num_addr_bits_needed := 5; when 512 => num_addr_bits_needed := 6; when others => -- 1024 bits num_addr_bits_needed := 7; end case; Return (num_addr_bits_needed); end function func_calc_rdmux_sel_bits; ------------------------------------------------------------------- -- Function -- -- Function Name: func_include_dre -- -- Function Description: -- This function desides if conditions are right for allowing DRE -- inclusion. -- ------------------------------------------------------------------- function func_include_dre (need_dre : integer; needed_data_width : integer) return integer is Variable include_dre : Integer := 0; begin If (need_dre = 1 and needed_data_width < 128 and needed_data_width > 8) Then include_dre := 1; Else include_dre := 0; End if; Return (include_dre); end function func_include_dre; ------------------------------------------------------------------- -- Function -- -- Function Name: func_get_align_width -- -- Function Description: -- This function calculates the needed DRE alignment port width\ -- based upon the inclusion of DRE and the needed bit width of the -- DRE. -- ------------------------------------------------------------------- function func_get_align_width (dre_included : integer; dre_data_width : integer) return integer is Variable align_port_width : Integer := 1; begin if (dre_included = 1) then If (dre_data_width = 64) Then align_port_width := 3; Elsif (dre_data_width = 32) Then align_port_width := 2; else -- 16 bit data width align_port_width := 1; End if; else -- no DRE align_port_width := 1; end if; Return (align_port_width); end function func_get_align_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_rnd2pwr_of_2 -- -- Function Description: -- Rounds the input value up to the nearest power of 2 between -- 128 and 8192. -- ------------------------------------------------------------------- function funct_rnd2pwr_of_2 (input_value : integer) return integer is Variable temp_pwr2 : Integer := 128; begin if (input_value <= 128) then temp_pwr2 := 128; elsif (input_value <= 256) then temp_pwr2 := 256; elsif (input_value <= 512) then temp_pwr2 := 512; elsif (input_value <= 1024) then temp_pwr2 := 1024; elsif (input_value <= 2048) then temp_pwr2 := 2048; elsif (input_value <= 4096) then temp_pwr2 := 4096; else temp_pwr2 := 8192; end if; Return (temp_pwr2); end function funct_rnd2pwr_of_2; ------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_sf_offset_width -- -- Function Description: -- This function calculates the address offset width needed by -- the GP Store and Forward module with data packing. -- ------------------------------------------------------------------- function funct_get_sf_offset_width (mmap_dwidth : integer; stream_dwidth : integer) return integer is Constant FCONST_WIDTH_RATIO : integer := mmap_dwidth/stream_dwidth; Variable fvar_temp_offset_width : Integer := 1; begin case FCONST_WIDTH_RATIO is when 1 => fvar_temp_offset_width := 1; when 2 => fvar_temp_offset_width := 1; when 4 => fvar_temp_offset_width := 2; when 8 => fvar_temp_offset_width := 3; when 16 => fvar_temp_offset_width := 4; when 32 => fvar_temp_offset_width := 5; when 64 => fvar_temp_offset_width := 6; when others => -- 128 ratio fvar_temp_offset_width := 7; end case; Return (fvar_temp_offset_width); end function funct_get_sf_offset_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_stream_width2use -- -- Function Description: -- This function calculates the Stream width to use for MM2S -- modules upstream from the downsizing Store and Forward. If -- Store and Forward is present, then the effective native width -- is the MMAP data width. If no Store and Forward then the Stream -- width is the input Native Data width from the User. -- ------------------------------------------------------------------- function funct_get_stream_width2use (mmap_data_width : integer; stream_data_width : integer; sf_enabled : integer) return integer is Variable fvar_temp_width : Integer := 32; begin If (sf_enabled = 1) Then fvar_temp_width := mmap_data_width; Else fvar_temp_width := stream_data_width; End if; Return (fvar_temp_width); end function funct_get_stream_width2use; -- Constant Declarations ---------------------------------------- Constant SF_UPSIZED_SDATA_WIDTH : integer := funct_get_stream_width2use(C_MM2S_MDATA_WIDTH, C_MM2S_SDATA_WIDTH, C_INCLUDE_MM2S_GP_SF); Constant LOGIC_LOW : std_logic := '0'; Constant LOGIC_HIGH : std_logic := '1'; Constant INCLUDE_MM2S : integer range 0 to 2 := C_INCLUDE_MM2S; Constant IS_MM2S : integer range 0 to 1 := 1; Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID; Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH; Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH; Constant MM2S_MDATA_WIDTH : integer range 32 to 1024 := C_MM2S_MDATA_WIDTH; Constant MM2S_SDATA_WIDTH : integer range 8 to 1024 := C_MM2S_SDATA_WIDTH; Constant MM2S_TAG_WIDTH : integer range 1 to 8 := C_TAG_WIDTH; Constant MM2S_CMD_WIDTH : integer := (MM2S_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32); Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := C_INCLUDE_MM2S_STSFIFO; Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_MM2S_STSCMD_FIFO_DEPTH; Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := C_MM2S_STSCMD_IS_ASYNC; Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := C_INCLUDE_MM2S_DRE; Constant MM2S_BURST_SIZE : integer range 2 to 256 := C_MM2S_BURST_SIZE; Constant ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH; Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := ADDR_CNTL_FIFO_DEPTH; Constant SEL_ADDR_WIDTH : integer range 2 to 7 := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH); Constant MM2S_BTT_USED : integer range 8 to 23 := C_MM2S_BTT_USED; Constant NO_INDET_BTT : integer range 0 to 1 := 0; Constant INCLUDE_DRE : integer range 0 to 1 := func_include_dre(C_INCLUDE_MM2S_DRE, C_MM2S_SDATA_WIDTH); Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := func_get_align_width(INCLUDE_DRE, C_MM2S_SDATA_WIDTH); -- Calculates the minimum needed depth of the Store and Forward FIFO -- based on the MM2S pipeline depth and the max allowed Burst length Constant PIPEDEPTH_BURST_LEN_PROD : integer := (ADDR_CNTL_FIFO_DEPTH+2) * MM2S_BURST_SIZE; -- Assigns the depth of the optional Store and Forward FIFO to the nearest -- power of 2 Constant SF_FIFO_DEPTH : integer range 128 to 8192 := funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD); -- Calculate the width of the Store and Forward Starting Address Offset bus Constant SF_STRT_OFFSET_WIDTH : integer := funct_get_sf_offset_width(MM2S_MDATA_WIDTH, MM2S_SDATA_WIDTH); -- Signal Declarations ------------------------------------------ signal sig_cmd_stat_rst_user : std_logic := '0'; signal sig_cmd_stat_rst_int : std_logic := '0'; signal sig_mmap_rst : std_logic := '0'; signal sig_stream_rst : std_logic := '0'; signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cache_data : std_logic_vector(7 downto 0) := (others => '0'); signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd2mstr_cmd_valid : std_logic := '0'; signal sig_mst2cmd_cmd_ready : std_logic := '0'; signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal first_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal last_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0'); signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0'); signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0'); signal sig_mstr2addr_cmd_cmplt : std_logic := '0'; signal sig_mstr2addr_calc_error : std_logic := '0'; signal sig_mstr2addr_cmd_valid : std_logic := '0'; signal sig_addr2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0'); signal sig_mstr2data_strt_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_last_strb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mstr2data_drr : std_logic := '0'; signal sig_mstr2data_eof : std_logic := '0'; signal sig_mstr2data_sequential : std_logic := '0'; signal sig_mstr2data_calc_error : std_logic := '0'; signal sig_mstr2data_cmd_cmplt : std_logic := '0'; signal sig_mstr2data_cmd_valid : std_logic := '0'; signal sig_data2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2data_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2data_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_addr2data_addr_posted : std_logic := '0'; signal sig_data2all_dcntlr_halted : std_logic := '0'; signal sig_addr2rsc_calc_error : std_logic := '0'; signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0'; signal sig_data2rsc_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data2rsc_calc_err : std_logic := '0'; signal sig_data2rsc_okay : std_logic := '0'; signal sig_data2rsc_decerr : std_logic := '0'; signal sig_data2rsc_slverr : std_logic := '0'; signal sig_data2rsc_cmd_cmplt : std_logic := '0'; signal sig_rsc2data_ready : std_logic := '0'; signal sig_data2rsc_valid : std_logic := '0'; signal sig_calc2dm_calc_err : std_logic := '0'; signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_stat2rsc_status_ready : std_logic := '0'; signal sig_rsc2stat_status_valid : std_logic := '0'; signal sig_rsc2mstr_halt_pipe : std_logic := '0'; signal sig_mstr2data_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2addr_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0'); signal sig_sf2rdc_wready : std_logic := '0'; signal sig_rdc2sf_wvalid : std_logic := '0'; signal sig_rdc2sf_wdata : std_logic_vector(SF_UPSIZED_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2sf_wstrb : std_logic_vector((SF_UPSIZED_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_rdc2sf_wlast : std_logic := '0'; signal sig_skid2dre_wready : std_logic := '0'; signal sig_dre2skid_wvalid : std_logic := '0'; signal sig_dre2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2skid_wlast : std_logic := '0'; signal sig_dre2sf_wready : std_logic := '0'; signal sig_sf2dre_wvalid : std_logic := '0'; signal sig_sf2dre_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_sf2dre_wlast : std_logic := '0'; signal sig_rdc2dre_new_align : std_logic := '0'; signal sig_rdc2dre_use_autodest : std_logic := '0'; signal sig_rdc2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_rdc2dre_flush : std_logic := '0'; signal sig_sf2dre_new_align : std_logic := '0'; signal sig_sf2dre_use_autodest : std_logic := '0'; signal sig_sf2dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_sf2dre_flush : std_logic := '0'; signal sig_dre_new_align : std_logic := '0'; signal sig_dre_use_autodest : std_logic := '0'; signal sig_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush : std_logic := '0'; signal sig_rst2all_stop_request : std_logic := '0'; signal sig_data2rst_stop_cmplt : std_logic := '0'; signal sig_addr2rst_stop_cmplt : std_logic := '0'; signal sig_data2addr_stop_req : std_logic := '0'; signal sig_data2skid_halt : std_logic := '0'; signal sig_sf_allow_addr_req : std_logic := '0'; signal sig_mm2s_allow_addr_req : std_logic := '0'; signal sig_addr_req_posted : std_logic := '0'; signal sig_rd_xfer_cmplt : std_logic := '0'; signal sig_sf2mstr_cmd_ready : std_logic := '0'; signal sig_mstr2sf_cmd_valid : std_logic := '0'; signal sig_mstr2sf_tag : std_logic_vector(MM2S_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_src_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_dre_dest_align : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_mstr2sf_btt : std_logic_vector(MM2S_BTT_USED-1 downto 0) := (others => '0'); signal sig_mstr2sf_drr : std_logic := '0'; signal sig_mstr2sf_eof : std_logic := '0'; signal sig_mstr2sf_calc_error : std_logic := '0'; signal sig_mstr2sf_strt_offset : std_logic_vector(SF_STRT_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_data2sf_cmd_cmplt : std_logic := '0'; signal sig_cache2mstr_command : std_logic_vector (7 downto 0); signal mm2s_arcache_int : std_logic_vector (3 downto 0); signal mm2s_aruser_int : std_logic_vector (3 downto 0); begin --(architecture implementation) -- Debug vector output mm2s_dbg_data <= sig_dbg_data_mux_out; -- Note that only the mm2s_dbg_sel(0) is used at this time sig_dbg_data_mux_out <= sig_dbg_data_1 When (mm2s_dbg_sel(0) = '1') else sig_dbg_data_0 ; sig_dbg_data_0 <= X"BEEF1111" ; -- 32 bit Constant indicating MM2S Full type sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ; sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ; sig_dbg_data_1(2) <= sig_mmap_rst ; sig_dbg_data_1(3) <= sig_stream_rst ; sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ; sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ; sig_dbg_data_1(6) <= sig_stat2rsc_status_ready; sig_dbg_data_1(7) <= sig_rsc2stat_status_valid; sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake -- Spare bits in debug1 sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate begin -- Cache signal tie-off mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters sig_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values end generate GEN_CACHE; GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate begin -- Cache signal tie-off mm2s_arcache <= mm2s_arcache_int; -- Cache from Desc mm2s_aruser <= mm2s_aruser_int; -- Cache from Desc -- sig_cache_data <= mm2s_cmd_wdata(103 downto 96); -- This is the xUser and xCache values sig_cache_data <= mm2s_cmd_wdata(79 downto 72); -- This is the xUser and xCache values end generate GEN_CACHE2; -- Internal error output discrete ------------------------------ mm2s_err <= sig_calc2dm_calc_err; -- Rip the used portion of the Command Interface Command Data -- and throw away the padding sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0); ------------------------------------------------------------ -- Instance: I_RESET -- -- Description: -- Reset Block -- ------------------------------------------------------------ I_RESET : entity axi_datamover_v5_1.axi_datamover_reset generic map ( C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ) port map ( primary_aclk => mm2s_aclk , primary_aresetn => mm2s_aresetn , secondary_awclk => mm2s_cmdsts_awclk , secondary_aresetn => mm2s_cmdsts_aresetn , halt_req => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , flush_stop_request => sig_rst2all_stop_request , data_cntlr_stopped => sig_data2rst_stop_cmplt , addr_cntlr_stopped => sig_addr2rst_stop_cmplt , aux1_stopped => LOGIC_HIGH , aux2_stopped => LOGIC_HIGH , cmd_stat_rst_user => sig_cmd_stat_rst_user , cmd_stat_rst_int => sig_cmd_stat_rst_int , mmap_rst => sig_mmap_rst , stream_rst => sig_stream_rst ); ------------------------------------------------------------ -- Instance: I_CMD_STATUS -- -- Description: -- Command and Status Interface Block -- ------------------------------------------------------------ I_CMD_STATUS : entity axi_datamover_v5_1.axi_datamover_cmd_status generic map ( C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO , C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH , C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_STS_WIDTH => MM2S_STS_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , secondary_awclk => mm2s_cmdsts_awclk , user_reset => sig_cmd_stat_rst_user , internal_reset => sig_cmd_stat_rst_int , cmd_wvalid => mm2s_cmd_wvalid , cmd_wready => mm2s_cmd_wready , cmd_wdata => sig_mm2s_cmd_wdata , cache_data => sig_cache_data , sts_wvalid => mm2s_sts_wvalid , sts_wready => mm2s_sts_wready , sts_wdata => mm2s_sts_wdata , sts_wstrb => mm2s_sts_wstrb , sts_wlast => mm2s_sts_wlast , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid , cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready , mstr2stat_status => sig_rsc2stat_status , stat2mstr_status_ready => sig_stat2rsc_status_ready , mst2stst_status_valid => sig_rsc2stat_status_valid ); ------------------------------------------------------------ -- Instance: I_RD_STATUS_CNTLR -- -- Description: -- Read Status Controller Block -- ------------------------------------------------------------ I_RD_STATUS_CNTLR : entity axi_datamover_v5_1.axi_datamover_rd_status_cntl generic map ( C_STS_WIDTH => MM2S_STS_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , calc2rsc_calc_error => sig_calc2dm_calc_err , addr2rsc_calc_error => sig_addr2rsc_calc_error , addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty , data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_error => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2stat_status => sig_rsc2stat_status , stat2rsc_status_ready => sig_stat2rsc_status_ready , rsc2stat_status_valid => sig_rsc2stat_status_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- Instance: I_MSTR_PCC -- -- Description: -- Predictive Command Calculator Block -- ------------------------------------------------------------ I_MSTR_PCC : entity axi_datamover_v5_1.axi_datamover_pcc generic map ( C_IS_MM2S => IS_MM2S , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_CMD_WIDTH => MM2S_CMD_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_BTT_USED => MM2S_BTT_USED , C_SUPPORT_INDET_BTT => NO_INDET_BTT , C_NATIVE_XFER_WIDTH => SF_UPSIZED_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH ) port map ( -- Clock input primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , cmd2mstr_command => sig_cmd2mstr_command , cache2mstr_command => sig_cache2mstr_command , cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid , mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , calc_error => sig_calc2dm_calc_err , dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_btt => sig_mstr2sf_btt , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_cmd_cmplt => open , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset ); ------------------------------------------------------------ -- Instance: I_ADDR_CNTL -- -- Description: -- Address Controller Block -- ------------------------------------------------------------ I_ADDR_CNTL : entity axi_datamover_v5_1.axi_datamover_addr_cntl generic map ( C_ADDR_FIFO_DEPTH => ADDR_CNTL_FIFO_DEPTH , C_ADDR_WIDTH => MM2S_ADDR_WIDTH , C_ADDR_ID => MM2S_ARID_VALUE , C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , addr2axi_aid => mm2s_arid , addr2axi_aaddr => mm2s_araddr , addr2axi_alen => mm2s_arlen , addr2axi_asize => mm2s_arsize , addr2axi_aburst => mm2s_arburst , addr2axi_aprot => mm2s_arprot , addr2axi_avalid => mm2s_arvalid , addr2axi_acache => mm2s_arcache_int , addr2axi_auser => mm2s_aruser_int , axi2addr_aready => mm2s_arready , mstr2addr_tag => sig_mstr2addr_tag , mstr2addr_addr => sig_mstr2addr_addr , mstr2addr_len => sig_mstr2addr_len , mstr2addr_size => sig_mstr2addr_size , mstr2addr_burst => sig_mstr2addr_burst , mstr2addr_cache => sig_mstr2addr_cache , mstr2addr_user => sig_mstr2addr_user , mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt , mstr2addr_calc_error => sig_mstr2addr_calc_error , mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid , addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready , addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt , allow_addr_req => sig_mm2s_allow_addr_req , addr_req_posted => sig_addr_req_posted , addr2data_addr_posted => sig_addr2data_addr_posted , data2addr_data_rdy => LOGIC_LOW , data2addr_stop_req => sig_data2addr_stop_req , addr2stat_calc_error => sig_addr2rsc_calc_error , addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty ); ------------------------------------------------------------ -- Instance: I_RD_DATA_CNTL -- -- Description: -- Read Data Controller Block -- ------------------------------------------------------------ I_RD_DATA_CNTL : entity axi_datamover_v5_1.axi_datamover_rddata_cntl generic map ( C_INCLUDE_DRE => INCLUDE_DRE , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH , C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => SF_UPSIZED_SDATA_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset ----------------------------------- primary_aclk => mm2s_aclk , mmap_reset => sig_mmap_rst , -- Soft Shutdown Interface ----------------------------- rst2data_stop_request => sig_rst2all_stop_request , data2addr_stop_req => sig_data2addr_stop_req , data2rst_stop_cmplt => sig_data2rst_stop_cmplt , -- External Address Pipelining Contol support mm2s_rd_xfer_cmplt => sig_rd_xfer_cmplt , -- AXI Read Data Channel I/O ------------------------------- mm2s_rdata => mm2s_rdata , mm2s_rresp => mm2s_rresp , mm2s_rlast => mm2s_rlast , mm2s_rvalid => mm2s_rvalid , mm2s_rready => mm2s_rready , -- MM2S DRE Control ----------------------------------- mm2s_dre_new_align => sig_rdc2dre_new_align , mm2s_dre_use_autodest => sig_rdc2dre_use_autodest , mm2s_dre_src_align => sig_rdc2dre_src_align , mm2s_dre_dest_align => sig_rdc2dre_dest_align , mm2s_dre_flush => sig_rdc2dre_flush , -- AXI Master Stream ----------------------------------- mm2s_strm_wvalid => sig_rdc2sf_wvalid , mm2s_strm_wready => sig_sf2rdc_wready , mm2s_strm_wdata => sig_rdc2sf_wdata , mm2s_strm_wstrb => sig_rdc2sf_wstrb , mm2s_strm_wlast => sig_rdc2sf_wlast , -- MM2S Store and Forward Supplimental Control ---------- mm2s_data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , -- Command Calculator Interface -------------------------- mstr2data_tag => sig_mstr2data_tag , mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb , mstr2data_len => sig_mstr2data_len , mstr2data_strt_strb => sig_mstr2data_strt_strb , mstr2data_last_strb => sig_mstr2data_last_strb , mstr2data_drr => sig_mstr2data_drr , mstr2data_eof => sig_mstr2data_eof , mstr2data_sequential => sig_mstr2data_sequential , mstr2data_calc_error => sig_mstr2data_calc_error , mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt , mstr2data_cmd_valid => sig_mstr2data_cmd_valid , data2mstr_cmd_ready => sig_data2mstr_cmd_ready , mstr2data_dre_src_align => sig_mstr2data_dre_src_align , mstr2data_dre_dest_align => sig_mstr2data_dre_dest_align , -- Address Controller Interface -------------------------- addr2data_addr_posted => sig_addr2data_addr_posted , -- Data Controller Halted Status data2all_dcntlr_halted => sig_data2all_dcntlr_halted , -- Output Stream Skid Buffer Halt control data2skid_halt => sig_data2skid_halt , -- Read Status Controller Interface -------------------------- data2rsc_tag => sig_data2rsc_tag , data2rsc_calc_err => sig_data2rsc_calc_err , data2rsc_okay => sig_data2rsc_okay , data2rsc_decerr => sig_data2rsc_decerr , data2rsc_slverr => sig_data2rsc_slverr , data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt , rsc2data_ready => sig_rsc2data_ready , data2rsc_valid => sig_data2rsc_valid , rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe ); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_SF -- -- If Generate Description: -- Include the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 1) generate begin -- Merge external address posting control with the -- Store and Forward address posting control sig_mm2s_allow_addr_req <= sig_sf_allow_addr_req and mm2s_allow_addr_req; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; sig_dre_new_align <= sig_sf2dre_new_align ; sig_dre_use_autodest <= sig_sf2dre_use_autodest ; sig_dre_src_align <= sig_sf2dre_src_align ; sig_dre_dest_align <= sig_sf2dre_dest_align ; sig_dre_flush <= sig_sf2dre_flush ; ------------------------------------------------------------ -- Instance: I_RD_SF -- -- Description: -- Instance for the MM2S Store and Forward module with -- downsizer support. -- ------------------------------------------------------------ I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf generic map ( C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , C_MAX_BURST_LEN => MM2S_BURST_SIZE , C_DRE_IS_USED => INCLUDE_DRE , C_DRE_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH , C_DRE_ALIGN_WIDTH => DRE_ALIGN_WIDTH , C_MMAP_DWIDTH => MM2S_MDATA_WIDTH , C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , C_STRT_SF_OFFSET_WIDTH => SF_STRT_OFFSET_WIDTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_FAMILY => C_FAMILY ) port map ( -- Clock and Reset inputs ------------------------------- aclk => mm2s_aclk , reset => sig_mmap_rst , -- DataMover Read Side Address Pipelining Control Interface ok_to_post_rd_addr => sig_sf_allow_addr_req , rd_addr_posted => sig_addr_req_posted , rd_xfer_cmplt => sig_rd_xfer_cmplt , -- Read Side Stream In from DataMover MM2S Read Data Controller ----- sf2sin_tready => sig_sf2rdc_wready , sin2sf_tvalid => sig_rdc2sf_wvalid , sin2sf_tdata => sig_rdc2sf_wdata , sin2sf_tkeep => sig_rdc2sf_wstrb , sin2sf_tlast => sig_rdc2sf_wlast , -- RDC Store and Forward Supplimental Controls ---------- data2sf_cmd_cmplt => sig_data2sf_cmd_cmplt , data2sf_dre_flush => sig_rdc2dre_flush , -- DRE Control Interface from the Command Calculator ----------------------------- dre2mstr_cmd_ready => sig_sf2mstr_cmd_ready , mstr2dre_cmd_valid => sig_mstr2sf_cmd_valid , mstr2dre_tag => sig_mstr2sf_tag , mstr2dre_dre_src_align => sig_mstr2sf_dre_src_align , mstr2dre_dre_dest_align => sig_mstr2sf_dre_dest_align , mstr2dre_drr => sig_mstr2sf_drr , mstr2dre_eof => sig_mstr2sf_eof , mstr2dre_calc_error => sig_mstr2sf_calc_error , mstr2dre_strt_offset => sig_mstr2sf_strt_offset , -- MM2S DRE Control ------------------------------------------------------------- sf2dre_new_align => sig_sf2dre_new_align , sf2dre_use_autodest => sig_sf2dre_use_autodest , sf2dre_src_align => sig_sf2dre_src_align , sf2dre_dest_align => sig_sf2dre_dest_align , sf2dre_flush => sig_sf2dre_flush , -- Stream Out ---------------------------------- sout2sf_tready => sig_dre2sf_wready , sf2sout_tvalid => sig_sf2dre_wvalid , sf2sout_tdata => sig_sf2dre_wdata , sf2sout_tkeep => sig_sf2dre_wstrb , sf2sout_tlast => sig_sf2dre_wlast ); -- ------------------------------------------------------------ -- -- Instance: I_RD_SF -- -- -- -- Description: -- -- Instance for the MM2S Store and Forward module. -- -- -- ------------------------------------------------------------ -- I_RD_SF : entity axi_datamover_v5_1.axi_datamover_rd_sf -- generic map ( -- -- C_SF_FIFO_DEPTH => SF_FIFO_DEPTH , -- C_MAX_BURST_LEN => MM2S_BURST_SIZE , -- C_DRE_IS_USED => INCLUDE_DRE , -- C_STREAM_DWIDTH => MM2S_SDATA_WIDTH , -- C_FAMILY => C_FAMILY -- ) -- port map ( -- -- -- Clock and Reset inputs ------------------------------- -- aclk => mm2s_aclk , -- reset => sig_mmap_rst , -- -- -- -- DataMover Read Side Address Pipelining Control Interface -- ok_to_post_rd_addr => sig_sf_allow_addr_req , -- rd_addr_posted => sig_addr_req_posted , -- rd_xfer_cmplt => sig_rd_xfer_cmplt , -- -- -- -- -- Read Side Stream In from DataMover MM2S ----- -- sf2sin_tready => sig_sf2dre_wready , -- sin2sf_tvalid => sig_dre2sf_wvalid , -- sin2sf_tdata => sig_dre2sf_wdata , -- sin2sf_tkeep => sig_dre2sf_wstrb , -- sin2sf_tlast => sig_dre2sf_wlast , -- -- -- -- -- Stream Out ---------------------------------- -- sout2sf_tready => sig_skid2sf_wready , -- sf2sout_tvalid => sig_sf2skid_wvalid , -- sf2sout_tdata => sig_sf2skid_wdata , -- sf2sout_tkeep => sig_sf2skid_wstrb , -- sf2sout_tlast => sig_sf2skid_wlast -- -- ); end generate GEN_INCLUDE_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_SF -- -- If Generate Description: -- Omit the MM2S Store and Forward function -- -- ------------------------------------------------------------ GEN_NO_MM2S_SF : if (C_INCLUDE_MM2S_GP_SF = 0) generate begin -- Allow external address posting control -- Ignore Store and Forward Control sig_mm2s_allow_addr_req <= mm2s_allow_addr_req ; sig_sf_allow_addr_req <= '0' ; -- Address Posting support outputs mm2s_addr_req_posted <= sig_addr_req_posted ; mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt ; -- DRE Control Bus (Connect to the Read data Controller) sig_dre_new_align <= sig_rdc2dre_new_align ; sig_dre_use_autodest <= sig_rdc2dre_use_autodest ; sig_dre_src_align <= sig_rdc2dre_src_align ; sig_dre_dest_align <= sig_rdc2dre_dest_align ; sig_dre_flush <= sig_rdc2dre_flush ; -- Just pass stream signals through sig_sf2rdc_wready <= sig_dre2sf_wready ; sig_sf2dre_wvalid <= sig_rdc2sf_wvalid ; sig_sf2dre_wdata <= sig_rdc2sf_wdata ; sig_sf2dre_wstrb <= sig_rdc2sf_wstrb ; sig_sf2dre_wlast <= sig_rdc2sf_wlast ; -- Always enable the DRE Cmd bus for loading to keep from -- stalling the PCC module sig_sf2mstr_cmd_ready <= LOGIC_HIGH; end generate GEN_NO_MM2S_SF; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_MM2S_DRE -- -- If Generate Description: -- Include the MM2S DRE -- -- ------------------------------------------------------------ GEN_INCLUDE_MM2S_DRE : if (INCLUDE_DRE = 1) generate begin ------------------------------------------------------------ -- Instance: I_DRE64 -- -- Description: -- Instance for the MM2S DRE whach can support widths of -- 16 bits to 64 bits. -- ------------------------------------------------------------ I_DRE_16_to_64 : entity axi_datamover_v5_1.axi_datamover_mm2s_dre generic map ( C_DWIDTH => MM2S_SDATA_WIDTH , C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ) port map ( -- Control inputs dre_clk => mm2s_aclk , dre_rst => sig_stream_rst , dre_new_align => sig_dre_new_align , dre_use_autodest => sig_dre_use_autodest , dre_src_align => sig_dre_src_align , dre_dest_align => sig_dre_dest_align , dre_flush => sig_dre_flush , -- Stream Inputs dre_in_tstrb => sig_sf2dre_wstrb , dre_in_tdata => sig_sf2dre_wdata , dre_in_tlast => sig_sf2dre_wlast , dre_in_tvalid => sig_sf2dre_wvalid , dre_in_tready => sig_dre2sf_wready , -- Stream Outputs dre_out_tstrb => sig_dre2skid_wstrb , dre_out_tdata => sig_dre2skid_wdata , dre_out_tlast => sig_dre2skid_wlast , dre_out_tvalid => sig_dre2skid_wvalid , dre_out_tready => sig_skid2dre_wready ); end generate GEN_INCLUDE_MM2S_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_MM2S_DRE -- -- If Generate Description: -- Omit the MM2S DRE and housekeep the signals that it -- needs to output. -- ------------------------------------------------------------ GEN_NO_MM2S_DRE : if (INCLUDE_DRE = 0) generate begin -- Just pass stream signals through from the Store -- and Forward module sig_dre2sf_wready <= sig_skid2dre_wready ; sig_dre2skid_wvalid <= sig_sf2dre_wvalid ; sig_dre2skid_wdata <= sig_sf2dre_wdata ; sig_dre2skid_wstrb <= sig_sf2dre_wstrb ; sig_dre2skid_wlast <= sig_sf2dre_wlast ; end generate GEN_NO_MM2S_DRE; ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '1' generate begin ------------------------------------------------------------ -- Instance: I_MM2S_SKID_BUF -- -- Description: -- Instance for the MM2S Skid Buffer which provides for -- registerd Master Stream outputs and supports bi-dir -- throttling. -- ------------------------------------------------------------ I_MM2S_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf generic map ( C_WDATA_WIDTH => MM2S_SDATA_WIDTH ) port map ( -- System Ports aclk => mm2s_aclk , arst => sig_stream_rst , -- Shutdown control (assert for 1 clk pulse) skid_stop => sig_data2skid_halt , -- Slave Side (Stream Data Input) s_valid => sig_dre2skid_wvalid , s_ready => sig_skid2dre_wready , s_data => sig_dre2skid_wdata , s_strb => sig_dre2skid_wstrb , s_last => sig_dre2skid_wlast , -- Master Side (Stream Data Output m_valid => mm2s_strm_wvalid , m_ready => mm2s_strm_wready , m_data => mm2s_strm_wdata , m_strb => mm2s_strm_wstrb , m_last => mm2s_strm_wlast ); end generate ENABLE_AXIS_SKID; DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(5) = '0' generate begin mm2s_strm_wvalid <= sig_dre2skid_wvalid; sig_skid2dre_wready <= mm2s_strm_wready; mm2s_strm_wdata <= sig_dre2skid_wdata; mm2s_strm_wstrb <= sig_dre2skid_wstrb; mm2s_strm_wlast <= sig_dre2skid_wlast; end generate DISABLE_AXIS_SKID; end implementation;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; library work; use work.array_t.all; entity fir_sol is Port ( Reset : in STD_LOGIC; Clk : in STD_LOGIC; Input : in array32_t(0 to 9); Output : out STD_LOGIC_VECTOR (31 downto 0) ); end fir_sol; architecture Structural of fir_sol is -- adding the components to the Design -- component adder Port ( A : in STD_LOGIC_VECTOR (31 downto 0); B : in STD_LOGIC_VECTOR (31 downto 0); O : out STD_LOGIC_VECTOR (31 downto 0)); end component; component reg Port ( Reset : in STD_LOGIC; Clk : in STD_LOGIC; Load : in STD_LOGIC; Din : in STD_LOGIC_VECTOR (31 downto 0); Dout : out STD_LOGIC_VECTOR (31 downto 0)); end component; signal mout : array32_t(0 to 30);-- just a big array i will use as much as i need from it , for the first one i will use from 0to 2 and for the second input i will use fro 3to 5 and like that a multiples of 3 signal aout : array32_t(0 to 25); begin -- the equivlant to multiplication of X(0)*b(0) where b(0) = 3 which is 11 in binary that mean shift X(0) by two and add to X(0) --std_logic_vector(unsigned(inputA) srl to_integer(unsigned(inputB))); mout(1)<=std_logic_vector(unsigned(Input(0)) sll 1); add0: adder port map ( A => mout(1), B => Input(0), O => aout(0) ); -- the same for a(1)but with 23 = 11001 left shift by 3 and 4 and 0 mout(3)<=std_logic_vector(unsigned(Input(1)) sll 3); mout(4)<=std_logic_vector(unsigned(Input(1)) sll 4); add1: adder port map ( A => mout(3), B => mout(4), O => mout(5) ); add2: adder port map ( A => mout(5), B => Input(1), O => aout(1) ); -- the same for a(2)but with 96 = 110 0000 left shift by 5 and 6 mout(6)<=std_logic_vector(unsigned(Input(2)) sll 5); mout(7)<=std_logic_vector(unsigned(Input(2)) sll 6); add3: adder port map ( A => mout(6), B => mout(7), O => aout(2) ); -- the same for a(3)but with 384 = 1 1000 0000 left shift by 7 and 8 mout(9)<=std_logic_vector(unsigned(Input(3)) sll 7); mout(10)<=std_logic_vector(unsigned(Input(3)) sll 8); add4: adder port map ( A => mout(9), B => mout(10), O => aout(3) ); -- the same for a(4)but with 3073 = 1100 0000 0001 left shift by 10 and 11 and add a(4) mout(12)<=std_logic_vector(unsigned(Input(4)) sll 10); mout(13)<=std_logic_vector(unsigned(Input(4)) sll 11); add5: adder port map ( A => mout(12), B => mout(13), O => mout(14) ); add6: adder port map ( A => mout(14), B => Input(4), O => aout(4) ); -- the same for a(5)but with 3073 = 1100 0000 0001 left shift by 10 and 11 and add a(5) mout(15)<=std_logic_vector(unsigned(Input(5)) sll 10); mout(16)<=std_logic_vector(unsigned(Input(5)) sll 11); add7: adder port map ( A => mout(15), B => mout(16), O => mout(17) ); add8: adder port map ( A => mout(17), B => Input(5), O => aout(5) ); -- the same for a(6)but with 384 = 1 1000 0000 left shift by 7 and 8 mout(18)<=std_logic_vector(unsigned(Input(6)) sll 7); mout(19)<=std_logic_vector(unsigned(Input(6)) sll 8); add9: adder port map ( A => mout(18), B => mout(19), O => aout(6) ); -- the same for a(7)but with 96 = 110 0000 left shift by 5 and 6 mout(21)<=std_logic_vector(unsigned(Input(7)) sll 5); mout(22)<=std_logic_vector(unsigned(Input(7)) sll 6); add10: adder port map ( A => mout(21), B => mout(22), O => aout(7) ); -- the same for a(8)but with 25 = 11001 left shift by 3 and 4 and 0 mout(24)<=std_logic_vector(unsigned(Input(8)) sll 3); mout(25)<=std_logic_vector(unsigned(Input(8)) sll 4); add11: adder port map ( A => mout(24), B => mout(25), O => mout(26) ); add112: adder port map ( A => mout(26), B => Input(8), O => aout(8) ); -- the same for a(9)but with 3 = 11 left shift by 1 and 0 mout(27)<=std_logic_vector(unsigned(Input(9)) sll 1); add12: adder port map ( A => mout(27), B => Input(9), O => aout(9) ); ---adding the whole results add13: adder port map ( A => aout(0), B => aout(1), O => aout(10) ); add14: adder port map ( A => aout(2), B => aout(3), O => aout(11) ); add15: adder port map ( A => aout(4), B => aout(5), O => aout(12) ); add115: adder port map ( A => aout(6), B => aout(7), O => aout(13) ); add16:adder port map ( A => aout(8), B => aout(9), O => aout(14) ); add117: adder port map ( A => aout(10), B => aout(11), O => aout(15) ); add118: adder port map ( A => aout(12), B => aout(13), O => aout(16) ); add17: adder port map ( A => aout(15), B => aout(16), O => aout(17) ); add18: adder port map ( A => aout(14), B => aout(17), O => aout(18) ); reg3:reg port map ( Reset => Reset, Clk => Clk , Load =>'1', Din => aout(18), Dout => aout(20) ); Output<=aout(20); end Structural;

-- This is a 16 bit Linear Feedback Shift Register library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity LFSR16 is port( CLK : in std_logic; RESET : in std_logic; LD : in std_logic; EN : in std_logic; DIN : in std_logic_vector (0 to 15); PRN : out std_logic_vector (0 to 15); ZERO_D : out std_logic); end LFSR16; architecture RTL of LFSR16 is signal t_prn : std_logic_vector(0 to 15); begin -- Continuous assignments : PRN <= t_prn; ZERO_D <= '1' when (t_prn = "0000000000000000") else '0'; -- LFSR process : process(CLK,RESET) begin if RESET='1' then t_prn <= "0000000000000001"; -- load 1 at reset elsif rising_edge (CLK) then if (LD = '1') then -- load a new seed when ld is active t_prn <= DIN; elsif (EN = '1') then -- shift when enabled t_prn(0) <= t_prn(15) xor t_prn(4) xor t_prn(2) xor t_prn(1); t_prn(1 to 15) <= t_prn(0 to 14); end if; end if; end process; end RTL;

library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ; use work.fixed_pkg.all; entity EffectEcho is generic ( wordLength : natural := 16; constantsWordLength : natural := 16 ); port ( input : in std_logic_vector(wordLength-1 downto 0); output : out std_logic_vector(wordLength-1 downto 0); clk : in std_logic; reset : in std_logic ); end entity ; -- EffectEcho architecture arch of EffectEcho is COMPONENT blk_mem_gen_0 PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; constant delayDuration : natural := 2; constant decayGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(-0.5, constantsWordLength); constant directGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(0.8, constantsWordLength); constant echoGain : std_logic_vector(wordLength-1 downto 0) := real_to_fixed(0.5, constantsWordLength); -- 2 second max delay constant addressWidth : natural := 17; constant addressMax : natural := 44100; signal feedback : std_logic_vector(wordLength-1 downto 0); signal directGained : std_logic_vector(wordLength-1 downto 0); signal delayedGained : std_logic_vector(wordLength-1 downto 0); signal delayed : std_logic_vector(wordLength-1 downto 0); signal feedbackDirectSum : std_logic_vector(wordLength-1 downto 0); signal writeBus : std_logic_vector(wordLength-1 downto 0); signal readBus : std_logic_vector(wordLength-1 downto 0); signal writeEnable : std_logic_vector(0 downto 0); signal memoryAddress : std_logic_vector(addressWidth-1 downto 0); type state_type is (readStart, readWait, read, writeDone); constant waitTime : natural := 4; type reg_type is record state : state_type; waitCounter : natural range 0 to waitTime; address : unsigned(addressWidth-1 downto 0); writeEnable : std_logic; delayedOutput : std_logic_vector(wordLength-1 downto 0); end record; signal r, rin : reg_type; begin -- Summation feedbackSum : entity work.AdderSat generic map ( wordLength => wordLength ) port map ( a => input, b => feedback, s => feedbackDirectSum ); outputSum : entity work.AdderSat generic map ( wordLength => wordLength ) port map ( a => directGained, b => delayedGained, s => output ); -- Gains directMult : entity work.Multiplier generic map ( X_WIDTH => wordLength, X_FRACTION => wordLength-1, Y_WIDTH => constantsWordLength, Y_FRACTION => constantsWordLength-1, S_WIDTH => wordLength, S_FRACTION => wordLength-1 ) port map ( x => input, y => directGain, s => directGained ); feedbackMult : entity work.Multiplier generic map ( X_WIDTH => wordLength, X_FRACTION => wordLength-1, Y_WIDTH => constantsWordLength, Y_FRACTION => constantsWordLength-1, S_WIDTH => wordLength, S_FRACTION => wordLength-1 ) port map ( x => delayed, y => decayGain, s => feedback ); echoMult : entity work.Multiplier generic map ( X_WIDTH => wordLength, X_FRACTION => wordLength-1, Y_WIDTH => constantsWordLength, Y_FRACTION => constantsWordLength-1, S_WIDTH => wordLength, S_FRACTION => wordLength-1 ) port map ( x => delayed, y => echoGain, s => delayedGained ); -- Delay writeBus <= feedbackDirectSum; writeEnable <= (others => r.writeEnable); delayed <= r.delayedOutput; memoryAddress <= std_logic_vector(r.address); memory: blk_mem_gen_0 port map ( dina => writeBus, wea => writeEnable, doutb => readBus, clka => clk, clkb => clk, addra => memoryAddress, addrb => memoryAddress ); clk_proc : process( clk, reset ) begin if(reset = '1') then r.state <= readStart; r.address <= (others => '0'); r.writeEnable <= '0'; r.delayedOutput <= (others => '0'); elsif(rising_edge(clk)) then r <= rin; end if; end process ; -- clk_proc comb_proc : process( r, rin, readBus) variable v : reg_type; begin v := r; v.writeEnable := '0'; case r.state is when readStart => v.state := readWait; v.waitCounter := 0; when readWait => -- Wait some cycles before reading if(r.waitCounter >= waitTime) then v.state := read; else v.waitCounter := r.waitCounter + 1; end if; when read => v.state := writeDone; -- Write the new value v.writeEnable := '1'; -- Result is ready, read it. v.delayedOutput := readBus; when writeDone => v.state := readStart; if(r.address = addressMax-1) then v.address := (others => '0'); else v.address := v.address + 1; end if; when others => -- Don't care end case; rin <= v; end process ; -- comb_proc end architecture ; -- arch

library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity fsm is port( clock: in std_logic; input: in std_logic_vector(3 downto 0); output: out std_logic_vector(1 downto 0) ); end fsm; architecture behaviour of fsm is type state is (init0, init1, init2, init4, IOwait, RMACK, WMACK, read0, read1, write0); signal current_state, next_state: state; begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= init0; output <= "--"; case current_state is when init0 => if std_match(input, "--00") then next_state <= init1; output <= "00"; end if; when init1 => if std_match(input, "0100") then next_state <= init1; output <= "00"; elsif std_match(input, "--1-") then next_state <= init2; output <= "10"; end if; when init2 => if std_match(input, "1-10") then next_state <= init4; output <= "10"; end if; when init4 => if std_match(input, "-111") then next_state <= init4; output <= "10"; elsif std_match(input, "--01") then next_state <= IOwait; output <= "01"; end if; when IOwait => if std_match(input, "000-") then next_state <= IOwait; output <= "01"; elsif std_match(input, "100-") then next_state <= init1; output <= "01"; elsif std_match(input, "0110") then next_state <= read0; output <= "00"; elsif std_match(input, "1100") then next_state <= write0; output <= "11"; elsif std_match(input, "0111") then next_state <= RMACK; output <= "11"; elsif std_match(input, "1101") then next_state <= WMACK; output <= "00"; elsif std_match(input, "-01-") then next_state <= init2; output <= "01"; end if; when RMACK => if std_match(input, "0010") then next_state <= RMACK; output <= "11"; elsif std_match(input, "0111") then next_state <= read0; output <= "00"; end if; when WMACK => if std_match(input, "1100") then next_state <= WMACK; output <= "00"; elsif std_match(input, "1001") then next_state <= write0; output <= "01"; end if; when read0 => if std_match(input, "0001") then next_state <= read1; output <= "11"; end if; when read1 => if std_match(input, "0010") then next_state <= IOwait; output <= "01"; end if; when write0 => if std_match(input, "0100") then next_state <= IOwait; output <= "01"; end if; end case; end process; end behaviour;

----------------------------------------------------------------------------------------- -- Project : Invent a Chip -- Module : 7-Segment Display -- Author : Jan Dürre -- Last update : 22.07.2014 -- Description : - ----------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.iac_pkg.all; entity seven_seg is port( -- global signals clock : in std_ulogic; reset_n : in std_ulogic; -- bus interface iobus_cs : in std_ulogic; iobus_wr : in std_ulogic; iobus_addr : in std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0); iobus_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0); iobus_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0); -- 7-Seg hex0_n : out std_ulogic_vector(6 downto 0); hex1_n : out std_ulogic_vector(6 downto 0); hex2_n : out std_ulogic_vector(6 downto 0); hex3_n : out std_ulogic_vector(6 downto 0); hex4_n : out std_ulogic_vector(6 downto 0); hex5_n : out std_ulogic_vector(6 downto 0); hex6_n : out std_ulogic_vector(6 downto 0); hex7_n : out std_ulogic_vector(6 downto 0) ); end seven_seg; architecture rtl of seven_seg is -- array for easier use of hex0_n to hex7_n type seg_t is array (0 to 3) of std_ulogic_vector(6 downto 0); signal hex_seg, dec_seg : seg_t; -- 7-Segment Displays -- [][] [][] | [][][][] -- hex-display | decimal-display (-999 to 999) -- A4A3A2A1 | A0 -- +-----+ -- | 0 | -- | 5 1 | -- | 6 | -- | 4 2 | -- | 3 | -- +-----+ -- register for each hex-display type hex_display_t is array (0 to 3) of std_ulogic_vector(3 downto 0); signal hex_display, hex_display_nxt : hex_display_t; -- register for decimal-display and sign-symbol signal dec_display, dec_display_nxt : std_ulogic_vector(to_log2(1000)-1 downto 0); -- 0...999 signal dec_sign, dec_sign_nxt : std_ulogic; -- register to active 7-seg-displays signal display_active, display_active_nxt : std_ulogic_vector(4 downto 0); begin -- connect and invert signal seg to output hex0_n <= not dec_seg(0); hex1_n <= not dec_seg(1); hex2_n <= not dec_seg(2); hex3_n <= not dec_seg(3); hex4_n <= not hex_seg(0); hex5_n <= not hex_seg(1); hex6_n <= not hex_seg(2); hex7_n <= not hex_seg(3); -- sequential process process(clock, reset_n) begin -- async reset if reset_n = '0' then hex_display <= (others => (others => '0')); dec_display <= (others => '0'); dec_sign <= '0'; display_active <= (others =>'0'); elsif rising_edge(clock) then hex_display <= hex_display_nxt; dec_display <= dec_display_nxt; dec_sign <= dec_sign_nxt; display_active <= display_active_nxt; end if; end process; -- bus interface process(hex_display, dec_display, dec_sign, iobus_cs, iobus_addr, iobus_din, iobus_wr, display_active) begin -- standard: hold register values hex_display_nxt <= hex_display; dec_display_nxt <= dec_display; dec_sign_nxt <= dec_sign; display_active_nxt <= display_active; -- dout always "0..0", no readable registers available iobus_dout <= (others => '0'); -- chip select if iobus_cs = '1' then -- write (no read allowed) if iobus_wr = '1' then -- decode LSB: choose if hex_display or dec_display is changed if iobus_addr(0) = '1' then -- dec -- check MSB for positive or negative number if iobus_din(iobus_din'length-1) = '0' then dec_display_nxt <= iobus_din(dec_display'length-1 downto 0); dec_sign_nxt <= '0'; else -- save positive value dec_display_nxt <= std_ulogic_vector(-signed(iobus_din(dec_display'length-1 downto 0))); dec_sign_nxt <= '1'; end if; -- activate dec-display display_active_nxt(0) <= '1'; else -- hex -- check bits 1 to 4 of iobus_addr for i in 0 to 3 loop -- check if register should be changed if iobus_addr(i+1) = '1' then -- write date to array hex_display_nxt(i) <= iobus_din(i*4 + 3 downto i*4); -- activate display display_active_nxt(i+1) <= '1'; end if; end loop; end if; end if; end if; end process; -- decode LUT for hex-displays process(hex_display, display_active) begin -- for each hex-display for i in 0 to 3 loop -- check if display is active / has been written to if display_active(i+1) = '1' then case hex_display(i) is when "0000" => hex_seg(i) <= "0111111"; -- 0 when "0001" => hex_seg(i) <= "0000110"; -- 1 when "0010" => hex_seg(i) <= "1011011"; -- 2 when "0011" => hex_seg(i) <= "1001111"; -- 3 when "0100" => hex_seg(i) <= "1100110"; -- 4 when "0101" => hex_seg(i) <= "1101101"; -- 5 when "0110" => hex_seg(i) <= "1111101"; -- 6 when "0111" => hex_seg(i) <= "0000111"; -- 7 when "1000" => hex_seg(i) <= "1111111"; -- 8 when "1001" => hex_seg(i) <= "1101111"; -- 9 when "1010" => hex_seg(i) <= "1110111"; -- A when "1011" => hex_seg(i) <= "1111100"; -- b when "1100" => hex_seg(i) <= "0111001"; -- C when "1101" => hex_seg(i) <= "1011110"; -- d when "1110" => hex_seg(i) <= "1111001"; -- E when "1111" => hex_seg(i) <= "1110001"; -- F when others => hex_seg(i) <= "1111001"; -- wrong value: display E end case; -- deactivate display else hex_seg(i) <= (others => '0'); end if; end loop; end process; -- decode LUT for dec-display process(dec_display, dec_sign, display_active) variable bcd : std_ulogic_vector(11 downto 0); begin -- check if display is active / has been written to if display_active(0) = '1' then -- if value is too big if unsigned(dec_display) > to_unsigned(999, dec_display'length) then -- display E (for "Error") dec_seg(0) <= "1111001"; dec_seg(1) <= "0000000"; dec_seg(2) <= "0000000"; dec_seg(3) <= "0000000"; else -- convert binary to bcd bcd := to_bcd(dec_display, 3); -- for each bcd digit for i in 0 to 2 loop if bcd((i+1)*4 -1 downto i*4) = "0000" then dec_seg(i) <= "0111111"; -- 0 elsif bcd((i+1)*4 -1 downto i*4) = "0001" then dec_seg(i) <= "0000110"; -- 1 elsif bcd((i+1)*4 -1 downto i*4) = "0010" then dec_seg(i) <= "1011011"; -- 2 elsif bcd((i+1)*4 -1 downto i*4) = "0011" then dec_seg(i) <= "1001111"; -- 3 elsif bcd((i+1)*4 -1 downto i*4) = "0100" then dec_seg(i) <= "1100110"; -- 4 elsif bcd((i+1)*4 -1 downto i*4) = "0101" then dec_seg(i) <= "1101101"; -- 5 elsif bcd((i+1)*4 -1 downto i*4) = "0110" then dec_seg(i) <= "1111101"; -- 6 elsif bcd((i+1)*4 -1 downto i*4) = "0111" then dec_seg(i) <= "0000111"; -- 7 elsif bcd((i+1)*4 -1 downto i*4) = "1000" then dec_seg(i) <= "1111111"; -- 8 elsif bcd((i+1)*4 -1 downto i*4) = "1001" then dec_seg(i) <= "1101111"; -- 9 else dec_seg(i) <= "1111001"; -- wrong value: display E end if; end loop; -- sign-symbol if dec_sign = '1' then dec_seg(3) <= "1000000"; else -- turn off sign-symbol dec_seg(3) <= (others => '0'); end if; end if; -- deactivate display else dec_seg(0) <= (others => '0'); dec_seg(1) <= (others => '0'); dec_seg(2) <= (others => '0'); dec_seg(3) <= (others => '0'); end if; end process; end rtl;

-- ----------------------------------------------------------------------- -- -- Turbo Chameleon -- -- Multi purpose FPGA expansion for the Commodore 64 computer -- -- ----------------------------------------------------------------------- -- Copyright 2005-2021 by Peter Wendrich ([email protected]) -- http://www.syntiac.com/chameleon.html -- -- This source file is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This source file is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- ----------------------------------------------------------------------- -- -- Part of the Gigatron emulator. -- SRAM emulation mapped to FPGA blockram. -- -- ----------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- ----------------------------------------------------------------------- entity gigatron_ram is generic ( abits : integer := 15; dbits : integer := 8 ); port ( clk : in std_logic; we : in std_logic; a : in unsigned(abits-1 downto 0); d : in unsigned(dbits-1 downto 0); q : out unsigned(dbits-1 downto 0) ); end entity; -- ----------------------------------------------------------------------- architecture rtl of gigatron_ram is constant ramsize : integer := 2**abits; type ram_t is array(0 to ramsize-1) of unsigned(d'range); signal ram_reg : ram_t := (others => (others => '0')); signal q_reg : unsigned(q'range); begin q <= q_reg; process(clk) begin if rising_edge(clk) then if we = '1' then ram_reg(to_integer(a)) <= d; end if; q_reg <= ram_reg(to_integer(a)); end if; end process; end architecture;

-- Template for VGA output by: Rene Kristensen -- This design template uses gated clocks which generally are bad design practice. -- This implies that the template design is not optimized for speed and will only serve for educational purpose. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity vga is port (clk,reset : in std_logic; red, green, blue : out std_logic_vector(9 downto 0); hsync, vsync, clockOut, blank, compSync: out std_logic); end vga; architecture testGenerator of vga is -- horizontal Timing constants for 640 x 480 @ 60Hz constant hFrontPorch : natural := 16; -- units are number of 25 MHz clocks constant hBackPorch : natural := 48; constant hDataLen : natural := 640; constant hSynWidth : natural := 96; -- vertical Timing constants for 640 x 480 @ 60Hz constant vFrontPorch : natural := 10; -- units are number of lines constant vBackPorch : natural := 33; constant vDataLen : natural := 480; constant vSynWidth : natural := 2; -- signal declaration signal hSyncCounter, vSyncCounter : integer range 0 to 1023; -- contrain integer to 10 bit. signal hSyncOut,vSyncOut,clk25,vBlank,hBlank : std_logic; -- attributes ensuring the signals defined below are not reduced away before simulation. attribute keep: boolean; -- don't reduce vSyncCounter and hSyncCounter signals away, so we can watch these signals i simulator attribute keep of vSyncCounter : signal is true; -- || -- attribute keep of hSyncCounter: signal is true; -- || -- -- INSERT YOUR PROCEDURE HERE. -- Your procedure should circular increment syncCounter, produce blanking and sync output. begin clkdiv: process (reset,clk) -- creates a 25 MHz pixel clock (clk25) from a 50 MHz input (clk). begin if (reset = '0') then clk25 <= '0'; elsif rising_edge(clk) then clk25 <= not clk25; end if; end process; -- horizontal process using the generic syncGenerator function to generate a proper hsync pulse. hsyn: process (reset,clk25) -- reacts on reset and 25 MHz clock. begin if reset = '0' then hSyncCounter <= 0; elsif rising_edge(clk25) then syncGenerator(hSyncCounter,hSyncOut,hBlank,hFrontPorch,hBackPorch,hDataLen,hSynWidth); -- generates active low pulse after every line end if; end process; -- vertical process using the generic syncGenerator function to generate a proper vsync pulse. vsyn: process (reset,hSyncOut) -- reacts on reset and hsync (meaning every line). begin if reset = '0' then vSyncCounter <= 0; elsif rising_edge(hSyncOut) then syncGenerator(vSyncCounter,vSyncOut,vBlank,vFrontPorch,vBackPorch,vDataLen,vSynWidth); -- generates active low pulse after every picture end if; end process; color: process (reset, hSyncCounter,vSyncCounter) -- draws italian flag color scheme begin if ((hSyncCounter > hBackPorch) and (hSyncCounter <= hBackPorch+213)) then red <= (others => '0'); -- Green green <= (others => '1'); blue <= (others => '0'); elsif ((hSyncCounter > hBackPorch+213) and (hSyncCounter <= hBackPorch+426)) then red <= (others => '1'); -- White green <= (others => '1'); blue <= (others => '1'); else red <= (others => '1'); -- Red green <= (others => '0'); blue <= (others => '0'); end if; end process; vsync <= vSyncOut; -- connect vsync to entity hsync <= hSyncOut; -- connect hsync to entity clockOut <= clk25; -- 25 MHz clock for DAC blank <= not (vBlank or hBlank); -- active low blanking. compSync <= '1'; -- Never perform any composite sync. end testGenerator;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.io_bus_pkg.all; entity uart_peripheral_io is generic ( g_tx_fifo : boolean := true; g_divisor : natural := 417 ); port ( clock : in std_logic; reset : in std_logic; io_req : in t_io_req; io_resp : out t_io_resp; irq : out std_logic; txd : out std_logic; rxd : in std_logic := '1'; rts : out std_logic; cts : in std_logic := '1' ); end uart_peripheral_io; architecture gideon of uart_peripheral_io is signal dotx : std_logic; signal done : std_logic; signal rxchar : std_logic_vector(7 downto 0); signal rx_ack : std_logic; signal rxfifo_get : std_logic; signal rxfifo_dout : std_logic_vector(7 downto 0); signal rxfifo_full : std_logic; signal rxfifo_dav : std_logic; signal overflow : std_logic; signal flags : std_logic_vector(7 downto 0); signal imask : std_logic_vector(7 downto 6); signal rdata_mux : std_logic_vector(7 downto 0); signal txfifo_get : std_logic; signal txfifo_put : std_logic; signal txfifo_dout : std_logic_vector(7 downto 0); signal txfifo_full : std_logic := '1'; signal txfifo_dav : std_logic; signal dotx_d : std_logic; signal txchar : std_logic_vector(7 downto 0); constant c_uart_data : unsigned(1 downto 0) := "00"; constant c_uart_get : unsigned(1 downto 0) := "01"; constant c_uart_flags : unsigned(1 downto 0) := "10"; constant c_uart_imask : unsigned(1 downto 0) := "11"; begin my_tx: entity work.tx generic map (g_divisor) port map ( clk => clock, reset => reset, dotx => dotx, txchar => txchar, cts => cts, txd => txd, done => done ); my_rx: entity work.rx generic map (g_divisor) port map ( clk => clock, reset => reset, rxd => rxd, rxchar => rxchar, rx_ack => rx_ack ); my_rxfifo: entity work.srl_fifo generic map ( Width => 8, Threshold => 12 ) port map ( clock => clock, reset => reset, GetElement => rxfifo_get, PutElement => rx_ack, FlushFifo => '0', DataIn => rxchar, DataOut => rxfifo_dout, SpaceInFifo => open, AlmostFull => rxfifo_full, DataInFifo => rxfifo_dav ); gentx: if g_tx_fifo generate my_txfifo: entity work.srl_fifo generic map ( Width => 8, Threshold => 12 ) port map ( clock => clock, reset => reset, GetElement => txfifo_get, PutElement => txfifo_put, FlushFifo => '0', DataIn => io_req.data, DataOut => txfifo_dout, SpaceInFifo => open, AlmostFull => txfifo_full, DataInFifo => txfifo_dav ); end generate; process(clock) begin if rising_edge(clock) then rxfifo_get <= '0'; dotx_d <= dotx; txfifo_get <= dotx_d; io_resp <= c_io_resp_init; if rxfifo_full='1' and rx_ack='1' then overflow <= '1'; end if; txfifo_put <= '0'; if g_tx_fifo then dotx <= txfifo_dav and done and not dotx; txchar <= txfifo_dout; else dotx <= '0'; -- default, overridden with write end if; if io_req.write='1' then io_resp.ack <= '1'; case io_req.address(1 downto 0) is when c_uart_data => -- dout if not g_tx_fifo then txchar <= io_req.data; dotx <= '1'; else -- there is a fifo txfifo_put <= '1'; end if; when c_uart_get => -- din rxfifo_get <= '1'; when c_uart_flags => -- clear flags overflow <= overflow and not io_req.data(0); when c_uart_imask => -- interrupt control imask <= io_req.data(7 downto 6); when others => null; end case; elsif io_req.read='1' then io_resp.ack <= '1'; io_resp.data <= rdata_mux; end if; if (flags(7 downto 6) and imask) /= "00" then irq <= '1'; else irq <= '0'; end if; if reset='1' then overflow <= '0'; imask <= (others => '0'); end if; end if; end process; flags(0) <= overflow; flags(1) <= '0'; flags(2) <= '0'; flags(3) <= '0'; flags(4) <= txfifo_full; flags(5) <= rxfifo_full; flags(6) <= done; flags(7) <= rxfifo_dav; rts <= not rxfifo_full; with io_req.address(1 downto 0) select rdata_mux <= rxfifo_dout when c_uart_data, flags when c_uart_flags, imask & "000000" when c_uart_imask, X"00" when others; end gideon;

-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA library ieee; use ieee.std_logic_1164.all; package synchronize is procedure init_synchronize ( signal synch : out std_logic ); procedure begin_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ); procedure end_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ); end package synchronize; package body synchronize is -- code from book procedure init_synchronize ( signal synch : out std_logic ) is begin synch <= '0'; end procedure init_synchronize; procedure begin_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ) is begin synch <= 'Z' after Tdelay; wait until synch = 'H'; end procedure begin_synchronize; procedure end_synchronize ( signal synch : inout std_logic; Tdelay : in delay_length := 0 fs ) is begin synch <= '0' after Tdelay; wait until synch = '0'; end procedure end_synchronize; -- end code from book end package body synchronize;

--------------------------------------------------------------------------- -- -- Title: Hardware Thread User Logic Exit Thread -- To be used as a place holder, and size estimate for HWTI -- --------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_misc.all; library Unisim; use Unisim.all; --------------------------------------------------------------------------- -- Port declarations --------------------------------------------------------------------------- -- Definition of Ports: -- -- Misc. Signals -- clock -- -- HWTI to HWTUL interconnect -- intrfc2thrd_address 32 bits memory -- intrfc2thrd_value 32 bits memory function -- intrfc2thrd_function 16 bits control -- intrfc2thrd_goWait 1 bits control -- -- HWTUL to HWTI interconnect -- thrd2intrfc_address 32 bits memory -- thrd2intrfc_value 32 bits memory function -- thrd2intrfc_function 16 bits function -- thrd2intrfc_opcode 6 bits memory function -- --------------------------------------------------------------------------- -- Thread Manager Entity section --------------------------------------------------------------------------- entity user_logic_hwtul is port ( clock : in std_logic; intrfc2thrd_address : in std_logic_vector(0 to 31); intrfc2thrd_value : in std_logic_vector(0 to 31); intrfc2thrd_function : in std_logic_vector(0 to 15); intrfc2thrd_goWait : in std_logic; thrd2intrfc_address : out std_logic_vector(0 to 31); thrd2intrfc_value : out std_logic_vector(0 to 31); thrd2intrfc_function : out std_logic_vector(0 to 15); thrd2intrfc_opcode : out std_logic_vector(0 to 5) ); end entity user_logic_hwtul; --------------------------------------------------------------------------- -- Architecture section --------------------------------------------------------------------------- architecture IMP of user_logic_hwtul is --------------------------------------------------------------------------- -- Signal declarations --------------------------------------------------------------------------- type state_machine is ( FUNCTION_RESET, FUNCTION_USER_SELECT, FUNCTION_START, FUNCTION_EXIT, STATE_1, STATE_2, STATE_3, STATE_4, STATE_5, STATE_6, STATE_7, STATE_8, STATE_9, STATE_10, STATE_11, STATE_12, STATE_13, STATE_14, STATE_15, STATE_16, STATE_17, STATE_18, STATE_19, STATE_20, WAIT_STATE, ERROR_STATE); -- Function definitions constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000"; constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001"; constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002"; constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003"; constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101"; constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102"; constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103"; constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104"; constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105"; constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106"; constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107"; constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108"; constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109"; constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110"; constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111"; constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112"; constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113"; constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114"; constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115"; constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116"; constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117"; constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118"; constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119"; constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120"; -- Range 0003 to 7999 reserved for user logic's state machine -- Range 8000 to 9999 reserved for system calls constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000"; constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001"; constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010"; constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011"; constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012"; constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013"; constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014"; constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015"; constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016"; constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020"; constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021"; constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022"; constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023"; constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030"; constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031"; constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032"; constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033"; constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034"; constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040"; constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041"; constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042"; constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043"; constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050"; constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051"; constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052"; constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053"; constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054"; -- Ranged A000 to FFFF reserved for supported library calls constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000"; constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001"; constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002"; -- user_opcode Constants constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000"; -- Memory sub-interface specific opcodes constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001"; constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010"; constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011"; constant OPCODE_READ : std_logic_vector(0 to 5) := "000100"; constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101"; constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110"; -- Function sub-interface specific opcodes constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000"; constant OPCODE_POP : std_logic_vector(0 to 5) := "010001"; constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010"; constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011"; constant Z32 : std_logic_vector(0 to 31) := (others => '0'); signal current_state, next_state : state_machine := FUNCTION_RESET; signal return_state, return_state_next: state_machine := FUNCTION_RESET; signal toUser_address : std_logic_vector(0 to 31); signal toUser_value : std_logic_vector(0 to 31); signal toUser_function : std_logic_vector(0 to 15); signal toUser_goWait : std_logic; signal retVal, retVal_next : std_logic_vector(0 to 31); signal arg, arg_next : std_logic_vector(0 to 31); signal reg1, reg1_next : std_logic_vector(0 to 31); signal reg2, reg2_next : std_logic_vector(0 to 31); signal reg3, reg3_next : std_logic_vector(0 to 31); signal reg4, reg4_next : std_logic_vector(0 to 31); signal reg5, reg5_next : std_logic_vector(0 to 31); signal reg6, reg6_next : std_logic_vector(0 to 31); signal reg7, reg7_next : std_logic_vector(0 to 31); signal reg8, reg8_next : std_logic_vector(0 to 31); --------------------------------------------------------------------------- -- Begin architecture --------------------------------------------------------------------------- begin -- architecture IMP HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is begin if (clock'event and (clock = '1')) then toUser_address <= intrfc2thrd_address; toUser_value <= intrfc2thrd_value; toUser_function <= intrfc2thrd_function; toUser_goWait <= intrfc2thrd_goWait; return_state <= return_state_next; retVal <= retVal_next; arg <= arg_next; reg1 <= reg1_next; reg2 <= reg2_next; reg3 <= reg3_next; reg4 <= reg4_next; reg5 <= reg5_next; reg6 <= reg6_next; reg7 <= reg7_next; reg8 <= reg8_next; -- Find out if the HWTI is tell us what to do if (intrfc2thrd_goWait = '1') then case intrfc2thrd_function is -- Typically the HWTI will tell us to control our own destiny when U_FUNCTION_USER_SELECT => current_state <= next_state; -- List all the functions the HWTI could tell us to run when U_FUNCTION_RESET => current_state <= FUNCTION_RESET; when U_FUNCTION_START => current_state <= FUNCTION_START; when U_STATE_1 => current_state <= STATE_1; when U_STATE_2 => current_state <= STATE_2; when U_STATE_3 => current_state <= STATE_3; when U_STATE_4 => current_state <= STATE_4; when U_STATE_5 => current_state <= STATE_5; when U_STATE_6 => current_state <= STATE_6; when U_STATE_7 => current_state <= STATE_7; when U_STATE_8 => current_state <= STATE_8; when U_STATE_9 => current_state <= STATE_9; when U_STATE_10 => current_state <= STATE_10; when U_STATE_11 => current_state <= STATE_11; when U_STATE_12 => current_state <= STATE_12; when U_STATE_13 => current_state <= STATE_13; when U_STATE_14 => current_state <= STATE_14; when U_STATE_15 => current_state <= STATE_15; when U_STATE_16 => current_state <= STATE_16; when U_STATE_17 => current_state <= STATE_17; when U_STATE_18 => current_state <= STATE_18; when U_STATE_19 => current_state <= STATE_19; when U_STATE_20 => current_state <= STATE_20; -- If the HWTI tells us to do something we don't know, error when OTHERS => current_state <= ERROR_STATE; end case; else current_state <= WAIT_STATE; end if; end if; end process HWTUL_STATE_PROCESS; HWTUL_STATE_MACHINE : process (clock) is begin -- Default register assignments thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse thrd2intrfc_address <= Z32; thrd2intrfc_value <= Z32; thrd2intrfc_function <= U_FUNCTION_USER_SELECT; return_state_next <= return_state; next_state <= current_state; retVal_next <= retVal; arg_next <= arg; reg1_next <= reg1; reg2_next <= reg2; reg3_next <= reg3; reg4_next <= reg4; reg5_next <= reg5; reg6_next <= reg6; reg7_next <= reg7; reg8_next <= reg8; -- attr_destroy_3.c -- The state machine case current_state is when FUNCTION_RESET => --Set default values thrd2intrfc_opcode <= OPCODE_NOOP; thrd2intrfc_address <= Z32; thrd2intrfc_value <= Z32; thrd2intrfc_function <= U_FUNCTION_START; -- hthread_attr_t * attr = (hthread_attr_t *) arg when FUNCTION_START => -- Pop the argument thrd2intrfc_value <= Z32; thrd2intrfc_opcode <= OPCODE_POP; next_state <= WAIT_STATE; return_state_next <= STATE_1; -- hthread_attr_init( attr ); when STATE_1 => -- Push the argument to hthread_attr_init arg_next <= intrfc2thrd_value; thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= intrfc2thrd_value; next_state <= WAIT_STATE; return_state_next <= STATE_2; when STATE_2 => -- Call hthread_attr_init thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT; thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3; next_state <= WAIT_STATE; -- retVal = hthread_attr_destroy( attr ); when STATE_3 => -- Push the argument to hthread_attr_init thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= arg; next_state <= WAIT_STATE; return_state_next <= STATE_4; when STATE_4 => -- Call hthread_attr_destroy thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_DESTROY; thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5; next_state <= WAIT_STATE; when STATE_5 => retVal_next <= intrfc2thrd_value; next_state <= FUNCTION_EXIT; when FUNCTION_EXIT => --Same as hthread_exit( (void *) retVal ); thrd2intrfc_value <= retVal; thrd2intrfc_opcode <= OPCODE_RETURN; next_state <= WAIT_STATE; when WAIT_STATE => next_state <= return_state; when ERROR_STATE => next_state <= ERROR_STATE; when others => next_state <= ERROR_STATE; end case; end process HWTUL_STATE_MACHINE; end architecture IMP;

library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.NUMERIC_STD.all; use work.pico_cpu.all; --ALU entity entity ALU is generic (BitWidth: integer); port ( A: in std_logic_vector (BitWidth-1 downto 0); B: in std_logic_vector (BitWidth-1 downto 0); Command: in std_logic_vector (3 downto 0); Cflag_in: in std_logic; Cflag_out: out std_logic; Result: out std_logic_vector (BitWidth-1 downto 0) ); end ALU; --Architecture of the DPU architecture RTL of ALU is --------------------------------------------- -- Signals --------------------------------------------- signal AddSub_result: std_logic_vector (BitWidth-1 downto 0) := (others => '0'); signal Cout,Add_Sub: std_logic := '0'; begin --------------------------------------------- -- component instantiation --------------------------------------------- Adder_comp: Adder_Sub generic map (BitWidth => BitWidth) port map (A,B,Add_Sub,AddSub_result,Cout); --------------------------------------------- Cflag_out <= Cout; PROC_ALU: process(Command,A,B,AddSub_result,Cflag_in) begin Add_Sub <= '0'; --adding by default case Command is WHEN "0000" => Result<= AddSub_result; --add WHEN "0001" => Add_Sub <= '1'; Result<= AddSub_result; -- Subtract WHEN "0010" => Result<= A; --Bypass A WHEN "0011" => Result<= B; --Bypass B WHEN "0100" => Result<= A and B; --And WHEN "0101" => Result<= A or B; --or WHEN "0110" => Result<= A xor B; --xor WHEN "0111" => Result<= '0' & A(BitWidth-1 downto 1) ; --shift right WHEN "1000" => Result<= A(BitWidth-2 downto 0)& '0' ; --shift left WHEN "1001" => Result<= not A +1; --negation WHEN "1010" => Result<= A(BitWidth-1) & A(BitWidth-1 downto 1) ; --shift right Arith WHEN "1011" => Result<= A(BitWidth-1) & A(BitWidth-3 downto 0)& A(0) ; --shift left Arith WHEN "1100" => Result<= not(A); --Not of A WHEN "1101" => Result<= (others => '0'); --Clear ACC WHEN "1110" => Result<= Cflag_in & A(BitWidth-1 downto 1); -- RRC WHEN "1111" => Result<= A(BitWidth-2 downto 0)& Cflag_in ; -- RLC WHEN OTHERS => Result<= (others => '0'); END CASE; end process PROC_ALU; end RTL;

-- ------------------------------------------------------------- -- -- Generated Configuration for pads_eastnord -- -- Generated -- by: wig -- on: Thu Jan 19 07:44:48 2006 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio2.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: pads_eastnord-struct-conf-c.vhd,v 1.4 2006/01/19 08:50:41 wig Exp $ -- $Date: 2006/01/19 08:50:41 $ -- $Log: pads_eastnord-struct-conf-c.vhd,v $ -- Revision 1.4 2006/01/19 08:50:41 wig -- Updated testcases, left 6 failing now (constant, bitsplice/X, ...) -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.43 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/conf -- -- Start of Generated Configuration pads_eastnord_struct_conf / pads_eastnord -- configuration pads_eastnord_struct_conf of pads_eastnord is for struct -- Generated Configuration for ioc_db2o_10 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_11 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_12 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_13 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_14 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_db2o_15 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_10 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_11 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_12 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_13 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_14 : ioc use configuration work.ioc_rtl_conf; end for; for ioc_dbo_15 : ioc use configuration work.ioc_rtl_conf; end for; end for; end pads_eastnord_struct_conf; -- -- End of Generated Configuration pads_eastnord_struct_conf -- -- --!End of Configuration/ies -- --------------------------------------------------------------

-------------------------------------------------------------------------------- -- Entity: mem_io_synth -- Date:2016-07-17 -- Author: Gideon -- -- Description: Testbench for altera io for ddr -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mem_io_synth is port ( ref_clock : in std_logic := '0'; ref_reset : in std_logic; sys_clock : out std_logic; sys_reset : out std_logic; write_data : out std_logic_vector(15 downto 0); read_data : out std_logic_vector(15 downto 0); do_read : out std_logic; rdata_valid : out std_logic; mode : in std_logic_vector(1 downto 0) := "00"; measurement : out std_logic_vector(11 downto 0); SDRAM_CLK : inout std_logic := 'Z'; SDRAM_CLKn : inout std_logic := 'Z'; SDRAM_A : out std_logic_vector(7 downto 0); SDRAM_DQ : inout std_logic_vector(3 downto 0); SDRAM_DQS : inout std_logic ); end entity; architecture arch of mem_io_synth is signal sys_clock_i : std_logic; signal sys_reset_i : std_logic; signal phasecounterselect : std_logic_vector(2 downto 0) := (others => '0'); signal phasestep : std_logic := '0'; signal phaseupdown : std_logic := '0'; signal phasedone : std_logic := '0'; signal addr_first : std_logic_vector(7 downto 0) := X"00"; signal addr_second : std_logic_vector(7 downto 0) := X"00"; signal wdata : std_logic_vector(15 downto 0) := X"0000"; signal wdata_oe : std_logic; signal counter : unsigned(4 downto 0) := (others => '0'); begin i_mut: entity work.mem_io port map ( ref_clock => ref_clock, ref_reset => ref_reset, sys_clock => sys_clock_i, sys_reset => sys_reset_i, phasecounterselect => phasecounterselect, phasestep => phasestep, phaseupdown => phaseupdown, phasedone => phasedone, mode => mode, measurement => measurement, addr_first => addr_first, addr_second => addr_second, wdata => wdata, wdata_oe => wdata_oe, rdata => read_data, mem_clk_p => SDRAM_CLK, mem_clk_n => SDRAM_CLKn, mem_addr => SDRAM_A, mem_dq => SDRAM_DQ, mem_dqs => SDRAM_DQS ); process(sys_clock_i, phasedone) begin if rising_edge(sys_clock_i) then counter <= counter + 1; wdata_oe <= '0'; addr_first <= (others => '1'); addr_second <= (others => '1'); do_read <= '0'; rdata_valid <= '0'; case counter is when "01101" => addr_first(7) <= '0'; addr_first(5) <= '0'; -- write when "01110" => wdata <= wdata(0) & wdata(15 downto 1); wdata_oe <= '1'; when "01111" => addr_first(7) <= '0'; addr_first(6) <= '0'; -- row when "10000" => addr_first(7) <= '0'; addr_first(4) <= '0'; -- read do_read <= '1'; when "10100" => rdata_valid <= '1'; when "10111" => phasecounterselect <= "101"; -- read clock phasestep <= '1'; when "01100" => phasecounterselect <= "110"; -- measure phasestep <= '1'; when others => null; end case; if sys_reset_i = '1' then phasestep <= '0'; wdata <= X"B769"; end if; end if; if phasedone = '0' then phasestep <= '0'; end if; end process; sys_clock <= sys_clock_i; sys_reset <= sys_reset_i; write_data <= wdata; end arch;

------------------------------------------------------------------ -- _____ -- / \ -- /____ \____ -- / \===\ \==/ -- /___\===\___\/ AVNET -- \======/ -- \====/ ----------------------------------------------------------------- -- -- This design is the property of Avnet. Publication of this -- design is not authorized without written consent from Avnet. -- -- Please direct any questions to: [email protected] -- -- Disclaimer: -- Avnet, Inc. makes no warranty for the use of this code or design. -- This code is provided "As Is". Avnet, Inc assumes no responsibility for -- any errors, which may appear in this code, nor does it make a commitment -- to update the information contained herein. Avnet, Inc specifically -- disclaims any implied warranties of fitness for a particular purpose. -- Copyright(c) 2011 Avnet, Inc. -- All rights reserved. -- ------------------------------------------------------------------ -- -- Create Date: Sep 15, 2011 -- Design Name: FMC-IMAGEON -- Module Name: user_logic.vhd -- Project Name: FMC-IMAGEON -- Target Devices: Virtex-6 -- Kintex-7, Zynq -- Avnet Boards: FMC-IMAGEON -- -- Tool versions: ISE 14.1 -- -- Description: FMC-IMAGEON VITA receiver - User Logic. -- This layer implements the following programming model -- 0x00 - SPI_CONTROL -- [ 0] VITA_RESET -- [ 1] SPI_RESET -- [ 8] SPI_STATUS_BUSY -- [ 9] SPI_STATUS_ERROR -- [16] SPI_TXFIFO_FULL -- [24] SPI_RXFIFO_EMPTY -- 0x04 - SPI_TIMING[15:0] -- 0x08 - SPI_TXFIFO_DATA[31:0] -- 0x0C - SPI_RXFIFO_DATA[31:0] -- 0x10 - ISERDES_CONTROL -- [ 0] ISERDES_RESET -- [ 1] ISERDES_AUTO_ALIGN -- [ 2] ISERDES_ALIGN_START -- [ 3] ISERDES_FIFO_ENABLE -- [ 8] ISERDES_CLK_READY -- [ 9] ISERDES_ALIGN_BUSY -- [10] ISERDES_ALIGNED -- [23:16] ISERDES_TXCLK_STATUS -- [31:24] ISERDES_RXCLK_STATUS -- 0x14 - ISERDES_TRAINING -- 0x18 - ISERDES_MANUAL_TAP -- 0x1C - {unused} -- 0x20 - DECODER_CONTROL -- [0] DECODER_RESET -- [1] DECODER_ENABLE -- 0x24 - DECODER_STARTODDEVEN -- 0x28 - DECODER_CODES_LS_LE -- [15: 0] CODE_LS -- [31:16] CODE_LE -- 0x2C - DECODER_CODES_FS_FE -- [15: 0] CODE_FS -- [31:16] CODE_FE -- 0x30 - DECODER_CODES_BL_IMG -- [15: 0] CODE_BL -- [31:16] CODE_IMG -- 0x34 - DECODER_CODES_TR_CRC -- [15: 0] CODE_TR -- [31:16] CODE_CRC -- 0x38 - DECODER_CNT_BLACK_LINES -- 0x3C - DECODER_CNT_IMAGE_LINES -- 0x40 - DECODER_CNT_BLACK_PIXELS -- 0x44 - DECODER_CNT_IMAGE_PIXELS -- 0x48 - DECODER_CNT_FRAMES -- 0x4C - DECODER_CNT_WINDOWS -- 0x50 - DECODER_CNT_CLOCKS -- 0x54 - DECODER_CNT_START_LINES -- 0x58 - DECODER_CNT_END_LINES -- 0x5C - SYNCGEN_DELAY -- [15: 0] DELAY -- 0x60 - SYNCGEN_HTIMING1 -- [15: 0] HACTIVE -- [31:16] HFPORCH -- 0x64 - SYNCGEN_HTIMING2 -- [15: 0] HSYNC -- [31:16] HBPORCH -- 0x68 - SYNCGEN_VTIMING1 -- [15: 0] VACTIVE -- [31:16] VFPORCH -- 0x6C - SYNCGEN_VTIMING2 -- [15: 0] VSYNC -- [31:16] VBPORCH -- 0x70 - CRC_CONTROL -- [0] CRC_RESET -- [1] CRC_INITVALUE -- 0x74 - CRC_STATUS -- 0x78 - REMAPPER_CONTROL[7:0] -- [2:0] REMAPPER_WRITE_CFG -- [6:4] REMAPPER_MODE -- 0x7C - {unused} -- 0x80 - FPN_PRNU_VALUES[ 31: 0] -- [ 7: 0] PRNU_0 -- [15: 8] FPN_0 -- [23:16] PRNU_1 -- [31:24] FPN_1 -- 0x84 - FPN_PRNU_VALUES[ 63: 32] -- [ 7: 0] PRNU_2 -- [15: 8] FPN_2 -- [23:16] PRNU_3 -- [31:24] FPN_3 -- 0x88 - FPN_PRNU_VALUES[ 95: 64] -- 0x8C - FPN_PRNU_VALUES[127: 96] -- 0x90 - FPN_PRNU_VALUES[159:128] -- 0x94 - FPN_PRNU_VALUES[191:160] -- 0x98 - FPN_PRNU_VALUES[223:192] -- 0x9C - FPN_PRNU_VALUES[255:224] -- [ 7: 0] PRNU_14 -- [15: 8] FPN_14 -- [23:16] PRNU_15 -- [31:24] FPN_15 -- 0xA0 - {unused} -- 0xA4 - {unused} -- 0xA8 - {unused} -- 0xAC - {unused} -- 0xB0 - {unused} -- 0xB4 - {unused} -- 0xB8 - {unused} -- 0xBC - {unused} -- 0xC0 - DECODER_CNT_MONITOR0_HIGH -- 0xC4 - DECODER_CNT_MONITOR0_LOW -- 0xC8 - DECODER_CNT_MONITOR1_HIGH -- 0xCC - DECODER_CNT_MONITOR1_LOW -- 0xD0 - {unused} -- 0xD4 - {unused} -- 0xD8 - {unused} -- 0xDC - TRIGGEN_EXT_DEBOUNCE -- 0xE0 - TRIGGEN_CONTROL -- [ 2: 0] TRIGGEN_ENABLE -- [ 6: 4] TRIGGEN_SYNC2READOUT -- [ 8] TRIGGEN_READOUTTRIGGER -- [ 16] TRIGGEN_EXT_POLARITY -- [ 24] TRIGGEN_CNT_UPDATE -- [30:28] TRIGGEN_GEN_POLARITY -- 0xE4 - TRIGGEN_DEFAULT_FREQ -- 0xE8 - TRIGGEN_TRIG0_HIGH -- 0xEC - TRIGGEN_TRIG0_LOW -- 0xF0 - TRIGGEN_TRIG1_HIGH -- 0xF4 - TRIGGEN_TRIG1_LOW -- 0xF8 - TRIGGEN_TRIG2_HIGH -- 0xFC - TRIGGEN_TRIG2_LOW -- -- -- Dependencies: -- -- Revision: Sep 15, 2011: 1.00 Initial version: -- - VITA SPI controller -- Sep 22, 2011: 1.01 Added: -- - ISERDES interface -- Sep 28, 2011: 1.02 Added: -- - sync channel decoder -- - crc checker -- - data remapper -- Oct 20, 2011: 1.03 Modify: -- - iserdes (use BUFR) -- Oct 21, 2011: 1.04 Added: -- - fpn prnu correction -- Nov 03, 2011: 1.05 Added: -- - trigger generator -- Dec 19, 2011: 1.06 Modified: -- - port to Kintex-7 -- Jan 12, 2012: 1.07 Added: -- - new fsync output port -- Modify: -- - syncgen -- Feb 06, 2012: 1.08 Modify: -- - triggergenerator -- (new version with debounce logic) -- - new C_XSVI_DIRECT_OUTPUT option -- Feb 22, 2012: 1.09 Modified -- - port to Zynq -- - new C_XSVI_USE_SYNCGEN option -- May 13, 2012: 1.10 Optimize -- - remove one layer of registers -- May 28, 2012: 1.11 Added -- - host_triggen_cnt_update -- (for simultaneous update of high/low values) -- - host_triggen_gen_polarity -- Jun 01, 2012: 1.12 Modify: -- - Move syncgen after demux_fifo -- - Increase size of demux_fifo -- (to tolerate jitter in video timing from sensor) -- - Add programmable delay on framestart for syncgen -- Jul 31, 2012: 1.13 Modify: -- - define clk200, clk, clk4x with SIGIS = CLK -- - define reset with SIGIS = RST -- - port to Spartan-6 -- ------------------------------------------------------------------ ------------------------------------------------------------------------------ -- user_logic.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: user_logic.vhd -- Version: 1.00.a -- Description: User logic. -- Date: Thu Sep 15 13:07:23 2011 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ -- DO NOT EDIT BELOW THIS LINE -------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; -- DO NOT EDIT ABOVE THIS LINE -------------------- --USER libraries added here library fmc_imageon_vita_receiver_v1_13_a; use fmc_imageon_vita_receiver_v1_13_a.fmc_imageon_vita_core; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_NUM_REG -- Number of software accessible registers -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- Bus2IP_Clk -- Bus to IP clock -- Bus2IP_Resetn -- Bus to IP reset -- Bus2IP_Addr -- Bus to IP address bus -- Bus2IP_CS -- Bus to IP chip select -- Bus2IP_RNW -- Bus to IP read/not write -- Bus2IP_Data -- Bus to IP data bus -- Bus2IP_BE -- Bus to IP byte enables -- Bus2IP_RdCE -- Bus to IP read chip enable -- Bus2IP_WrCE -- Bus to IP write chip enable -- IP2Bus_Data -- IP to Bus data bus -- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement -- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement -- IP2Bus_Error -- IP to Bus error response ------------------------------------------------------------------------------ entity user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here C_XSVI_DATA_WIDTH : integer := 10; C_XSVI_DIRECT_OUTPUT : integer := 0; C_XSVI_USE_SYNCGEN : integer := 1; C_FAMILY : string := "virtex6"; -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 64; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here clk200 : in std_logic; clk : in std_logic; clk4x : in std_logic; reset : in std_logic; oe : in std_logic; -- I/O pins io_vita_clk_pll : out std_logic; io_vita_reset_n : out std_logic; io_vita_spi_sclk : out std_logic; io_vita_spi_ssel_n : out std_logic; io_vita_spi_mosi : out std_logic; io_vita_spi_miso : in std_logic; io_vita_trigger : out std_logic_vector(2 downto 0); io_vita_monitor : in std_logic_vector(1 downto 0); io_vita_clk_out_p : in std_logic; io_vita_clk_out_n : in std_logic; io_vita_sync_p : in std_logic; io_vita_sync_n : in std_logic; io_vita_data_p : in std_logic_vector(7 downto 0); io_vita_data_n : in std_logic_vector(7 downto 0); -- Trigger Port trigger1 : in std_logic; -- Frame Sync Port fsync : out std_logic; -- XSVI Port xsvi_vsync_o : out std_logic; xsvi_hsync_o : out std_logic; xsvi_vblank_o : out std_logic; xsvi_hblank_o : out std_logic; xsvi_active_video_o : out std_logic; xsvi_video_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0); -- Debug Ports debug_host_o : out std_logic_vector(231 downto 0); debug_spi_o : out std_logic_vector( 95 downto 0); debug_iserdes_o : out std_logic_vector(229 downto 0); debug_decoder_o : out std_logic_vector(186 downto 0); debug_crc_o : out std_logic_vector( 87 downto 0); debug_triggen_o : out std_logic_vector( 9 downto 0); debug_video_o : out std_logic_vector( 31 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Addr : in std_logic_vector(0 to 31); Bus2IP_CS : in std_logic_vector(0 to 0); Bus2IP_RNW : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of Bus2IP_Clk : signal is "CLK"; attribute SIGIS of Bus2IP_Resetn : signal is "RST"; end entity user_logic; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of user_logic is --USER signal declarations added here, as needed for user logic ------------------------------------------ -- Signals for user logic slave model s/w accessible register example ------------------------------------------ signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg30 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg31 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg32 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg33 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg34 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg35 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg36 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg37 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg38 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg39 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg55 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg56 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg57 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg58 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg59 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg60 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg61 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg62 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg63 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg_write_sel : std_logic_vector(63 downto 0); signal slv_reg_read_sel : std_logic_vector(63 downto 0); signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_read_ack : std_logic; signal slv_write_ack : std_logic; signal slv_reg4_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg4_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg5_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg6_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg8_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg9_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg10_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg11_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg12_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg13_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg14_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg15_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg16_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg17_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg18_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg19_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg20_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg21_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg22_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg23_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg24_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg25_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg26_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg27_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg28_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg29_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg30_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg32_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg33_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg34_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg35_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg36_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg37_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg38_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg39_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg48_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg49_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg50_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg51_r1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- signal slv_reg55_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg56_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg57_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg58_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg59_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg60_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg61_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg62_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); signal slv_reg63_w1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0); -- HOST Interface - VITA signal host_vita_reset : std_logic; -- HOST Interface - SPI signal host_spi_clk : std_logic; signal host_spi_reset : std_logic; signal host_spi_timing : std_logic_vector(15 downto 0); signal host_spi_status_busy : std_logic; signal host_spi_status_error : std_logic; signal host_spi_txfifo_clk : std_logic; signal host_spi_txfifo_wen_a1 : std_logic; signal host_spi_txfifo_wen : std_logic; signal host_spi_txfifo_din : std_logic_vector(31 downto 0); signal host_spi_txfifo_full : std_logic; signal host_spi_rxfifo_clk : std_logic; signal host_spi_rxfifo_ren : std_logic; signal host_spi_rxfifo_dout : std_logic_vector(31 downto 0); signal host_spi_rxfifo_empty : std_logic; -- HOST Interface - ISERDES signal host_iserdes_reset : std_logic; signal host_iserdes_auto_align : std_logic; signal host_iserdes_align_start : std_logic; signal host_iserdes_fifo_enable : std_logic; signal host_iserdes_manual_tap : std_logic_vector(9 downto 0); signal host_iserdes_training : std_logic_vector(9 downto 0); -- signal host_iserdes_clk_ready : std_logic; signal host_iserdes_clk_status : std_logic_vector(15 downto 0); signal host_iserdes_align_busy : std_logic; signal host_iserdes_aligned : std_logic; -- HOST Interface - Sync Channel Decoder signal host_decoder_reset : std_logic; signal host_decoder_enable : std_logic; signal host_decoder_startoddeven : std_logic_vector(31 downto 0); signal host_decoder_code_ls : std_logic_vector(9 downto 0); signal host_decoder_code_le : std_logic_vector(9 downto 0); signal host_decoder_code_fs : std_logic_vector(9 downto 0); signal host_decoder_code_fe : std_logic_vector(9 downto 0); signal host_decoder_code_bl : std_logic_vector(9 downto 0); signal host_decoder_code_img : std_logic_vector(9 downto 0); signal host_decoder_code_tr : std_logic_vector(9 downto 0); signal host_decoder_code_crc : std_logic_vector(9 downto 0); signal host_decoder_frame_start : std_logic; signal host_decoder_cnt_black_lines : std_logic_vector(31 downto 0); signal host_decoder_cnt_image_lines : std_logic_vector(31 downto 0); signal host_decoder_cnt_black_pixels : std_logic_vector(31 downto 0); signal host_decoder_cnt_image_pixels : std_logic_vector(31 downto 0); signal host_decoder_cnt_frames : std_logic_vector(31 downto 0); signal host_decoder_cnt_windows : std_logic_vector(31 downto 0); signal host_decoder_cnt_clocks : std_logic_vector(31 downto 0); signal host_decoder_cnt_start_lines : std_logic_vector(31 downto 0); signal host_decoder_cnt_end_lines : std_logic_vector(31 downto 0); signal host_decoder_cnt_monitor0high : std_logic_vector(31 downto 0); signal host_decoder_cnt_monitor0low : std_logic_vector(31 downto 0); signal host_decoder_cnt_monitor1high : std_logic_vector(31 downto 0); signal host_decoder_cnt_monitor1low : std_logic_vector(31 downto 0); -- HOST Interface - CRC Checker signal host_crc_reset : std_logic; signal host_crc_initvalue : std_logic; signal host_crc_status : std_logic_vector(31 downto 0); -- HOST Interface - Data Channel Remapper signal host_remapper_write_cfg : std_logic_vector(2 downto 0); signal host_remapper_mode : std_logic_vector(2 downto 0); -- HOST Interface - Trigger Generator signal host_triggen_enable : std_logic_vector(2 downto 0); signal host_triggen_sync2readout : std_logic_vector(2 downto 0); signal host_triggen_readouttrigger : std_logic; signal host_triggen_default_freq : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger0high : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger0low : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger1high : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger1low : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger2high : std_logic_vector(31 downto 0); signal host_triggen_cnt_trigger2low : std_logic_vector(31 downto 0); signal host_triggen_ext_debounce : std_logic_vector(31 downto 0); signal host_triggen_ext_polarity : std_logic; signal host_triggen_cnt_update : std_logic; signal host_triggen_gen_polarity : std_logic_vector(2 downto 0); -- HOST Interface - FPN/PRNU Correction signal host_fpn_prnu_values : std_logic_vector((16*16)-1 downto 0); -- HOST Interface - Sync Generator signal host_syncgen_delay : std_logic_vector(15 downto 0); signal host_syncgen_hactive : std_logic_vector(15 downto 0); signal host_syncgen_hfporch : std_logic_vector(15 downto 0); signal host_syncgen_hsync : std_logic_vector(15 downto 0); signal host_syncgen_hbporch : std_logic_vector(15 downto 0); signal host_syncgen_vactive : std_logic_vector(15 downto 0); signal host_syncgen_vfporch : std_logic_vector(15 downto 0); signal host_syncgen_vsync : std_logic_vector(15 downto 0); signal host_syncgen_vbporch : std_logic_vector(15 downto 0); begin --USER logic implementation added here ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- -- Note: -- The example code presented here is to show you one way of reading/writing -- software accessible registers implemented in the user logic slave model. -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond -- to one software accessible register by the top level template. For example, -- if you have four 32 bit software accessible registers in the user logic, -- you are basically operating on the following memory mapped registers: -- -- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register -- "1000" C_BASEADDR + 0x0 -- "0100" C_BASEADDR + 0x4 -- "0010" C_BASEADDR + 0x8 -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ slv_reg_write_sel <= Bus2IP_WrCE(63 downto 0); slv_reg_read_sel <= Bus2IP_RdCE(63 downto 0); slv_write_ack <= Bus2IP_WrCE( 0) or Bus2IP_WrCE( 1) or Bus2IP_WrCE( 2) or Bus2IP_WrCE( 3) or Bus2IP_WrCE( 4) or Bus2IP_WrCE( 5) or Bus2IP_WrCE( 6) or Bus2IP_WrCE( 7) or Bus2IP_WrCE( 8) or Bus2IP_WrCE( 9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31) or Bus2IP_WrCE(32) or Bus2IP_WrCE(33) or Bus2IP_WrCE(34) or Bus2IP_WrCE(35) or Bus2IP_WrCE(36) or Bus2IP_WrCE(37) or Bus2IP_WrCE(38) or Bus2IP_WrCE(39) or Bus2IP_WrCE(40) or Bus2IP_WrCE(41) or Bus2IP_WrCE(42) or Bus2IP_WrCE(43) or Bus2IP_WrCE(44) or Bus2IP_WrCE(45) or Bus2IP_WrCE(46) or Bus2IP_WrCE(47) or Bus2IP_WrCE(48) or Bus2IP_WrCE(49) or Bus2IP_WrCE(50) or Bus2IP_WrCE(51) or Bus2IP_WrCE(52) or Bus2IP_WrCE(53) or Bus2IP_WrCE(54) or Bus2IP_WrCE(55) or Bus2IP_WrCE(56) or Bus2IP_WrCE(57) or Bus2IP_WrCE(58) or Bus2IP_WrCE(59) or Bus2IP_WrCE(60) or Bus2IP_WrCE(61) or Bus2IP_WrCE(62) or Bus2IP_WrCE(63); slv_read_ack <= Bus2IP_RdCE( 0) or Bus2IP_RdCE( 1) or Bus2IP_RdCE( 2) or Bus2IP_RdCE( 3) or Bus2IP_RdCE( 4) or Bus2IP_RdCE( 5) or Bus2IP_RdCE( 6) or Bus2IP_RdCE( 7) or Bus2IP_RdCE( 8) or Bus2IP_RdCE( 9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31) or Bus2IP_RdCE(32) or Bus2IP_RdCE(33) or Bus2IP_RdCE(34) or Bus2IP_RdCE(35) or Bus2IP_RdCE(36) or Bus2IP_RdCE(37) or Bus2IP_RdCE(38) or Bus2IP_RdCE(39) or Bus2IP_RdCE(40) or Bus2IP_RdCE(41) or Bus2IP_RdCE(42) or Bus2IP_RdCE(43) or Bus2IP_RdCE(44) or Bus2IP_RdCE(45) or Bus2IP_RdCE(46) or Bus2IP_RdCE(47) or Bus2IP_RdCE(48) or Bus2IP_RdCE(49) or Bus2IP_RdCE(50) or Bus2IP_RdCE(51) or Bus2IP_RdCE(52) or Bus2IP_RdCE(53) or Bus2IP_RdCE(54) or Bus2IP_RdCE(55) or Bus2IP_RdCE(56) or Bus2IP_RdCE(57) or Bus2IP_RdCE(58) or Bus2IP_RdCE(59) or Bus2IP_RdCE(60) or Bus2IP_RdCE(61) or Bus2IP_RdCE(62) or Bus2IP_RdCE(63); -- implement slave model software accessible register(s) SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then slv_reg0 <= (others => '0'); slv_reg1 <= (others => '0'); slv_reg2 <= (others => '0'); slv_reg3 <= (others => '0'); slv_reg4 <= (others => '0'); slv_reg5 <= (others => '0'); slv_reg6 <= (others => '0'); slv_reg7 <= (others => '0'); slv_reg8 <= (others => '0'); slv_reg9 <= (others => '0'); slv_reg10 <= (others => '0'); slv_reg11 <= (others => '0'); slv_reg12 <= (others => '0'); slv_reg13 <= (others => '0'); slv_reg14 <= (others => '0'); slv_reg15 <= (others => '0'); slv_reg16 <= (others => '0'); slv_reg17 <= (others => '0'); slv_reg18 <= (others => '0'); slv_reg19 <= (others => '0'); slv_reg20 <= (others => '0'); slv_reg21 <= (others => '0'); slv_reg22 <= (others => '0'); slv_reg23 <= (others => '0'); slv_reg24 <= (others => '0'); slv_reg25 <= (others => '0'); slv_reg26 <= (others => '0'); slv_reg27 <= (others => '0'); slv_reg28 <= (others => '0'); slv_reg29 <= (others => '0'); slv_reg30 <= (others => '0'); slv_reg31 <= (others => '0'); slv_reg32 <= (others => '0'); slv_reg33 <= (others => '0'); slv_reg34 <= (others => '0'); slv_reg35 <= (others => '0'); slv_reg36 <= (others => '0'); slv_reg37 <= (others => '0'); slv_reg38 <= (others => '0'); slv_reg39 <= (others => '0'); -- slv_reg55 <= (others => '0'); slv_reg56 <= (others => '0'); slv_reg57 <= (others => '0'); slv_reg58 <= (others => '0'); slv_reg59 <= (others => '0'); slv_reg60 <= (others => '0'); slv_reg61 <= (others => '0'); slv_reg62 <= (others => '0'); slv_reg63 <= (others => '0'); else case slv_reg_write_sel is when "1000000000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0100000000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0010000000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0001000000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000100000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000010000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000001000000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000100000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000010000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000001000000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000100000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000010000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000001000000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000100000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000010000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000001000000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000100000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg16(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000010000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg17(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000001000000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg18(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000100000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg19(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000010000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg20(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000001000000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg21(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000100000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg22(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000010000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg23(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000001000000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg24(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000100000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg25(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000010000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000001000000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000100000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000010000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000001000000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000100000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg31(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000010000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg32(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000001000000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg33(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000100000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg34(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000010000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg35(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000001000000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg36(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000100000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg37(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000010000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg38(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000001000000000000000000000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg39(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; -- when "0000000000000000000000000000000000000000000000000000000100000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg55(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000010000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg56(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000001000000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg57(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000100000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg58(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000010000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg59(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000001000" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg60(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000000100" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg61(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000000010" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg62(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when "0000000000000000000000000000000000000000000000000000000000000001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then slv_reg63(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); end if; end loop; when others => null; end case; end if; end if; end process SLAVE_REG_WRITE_PROC; -- implement slave model software accessible register(s) read mux SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31, slv_reg32, slv_reg33, slv_reg34, slv_reg35, slv_reg36, slv_reg37, slv_reg38, slv_reg39 ) is begin case slv_reg_read_sel is when "1000000000000000000000000000000000000000000000000000000000000000" => --slv_ip2bus_data <= slv_reg0; -- 0x00 - SPI_CONTROL -- [ 0] VITA_RESET -- [ 1] SPI_RESET -- [ 8] SPI_STATUS_BUSY -- [ 9] SPI_STATUS_ERROR -- [16] SPI_TXFIFO_FULL -- [24] SPI_RXFIFO_EMPTY slv_ip2bus_data <= "0000000" & host_spi_rxfifo_empty & "0000000" & host_spi_txfifo_full & "000000" & host_spi_status_error & host_spi_status_busy & "000000" & host_spi_reset & host_vita_reset; when "0100000000000000000000000000000000000000000000000000000000000000" => -- 0x04 - SPI_TIMING[15:0] slv_ip2bus_data <= slv_reg1; when "0010000000000000000000000000000000000000000000000000000000000000" => -- 0x08 - SPI_TXFIFO_DATA[31:0] slv_ip2bus_data <= slv_reg2; when "0001000000000000000000000000000000000000000000000000000000000000" => --slv_ip2bus_data <= slv_reg3; -- 0x0C - SPI_RXFIFO_DATA[31:0] slv_ip2bus_data <= host_spi_rxfifo_dout; when "0000100000000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg4_r1; when "0000010000000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg5; when "0000001000000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg6; when "0000000100000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg7; when "0000000010000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg8; when "0000000001000000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg9; when "0000000000100000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg10; when "0000000000010000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg11; when "0000000000001000000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg12; when "0000000000000100000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg13; when "0000000000000010000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg14_r1; when "0000000000000001000000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg15_r1; when "0000000000000000100000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg16_r1; when "0000000000000000010000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg17_r1; when "0000000000000000001000000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg18_r1; when "0000000000000000000100000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg19_r1; when "0000000000000000000010000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg20_r1; when "0000000000000000000001000000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg21_r1; when "0000000000000000000000100000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg22_r1; when "0000000000000000000000010000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg23; when "0000000000000000000000001000000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg24; when "0000000000000000000000000100000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg25; when "0000000000000000000000000010000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg26; when "0000000000000000000000000001000000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg27; when "0000000000000000000000000000100000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg28; when "0000000000000000000000000000010000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg29_r1; when "0000000000000000000000000000001000000000000000000000000000000000" => slv_ip2bus_data <= slv_reg30; when "0000000000000000000000000000000100000000000000000000000000000000" => slv_ip2bus_data <= slv_reg31; when "0000000000000000000000000000000010000000000000000000000000000000" => slv_ip2bus_data <= slv_reg32; when "0000000000000000000000000000000001000000000000000000000000000000" => slv_ip2bus_data <= slv_reg33; when "0000000000000000000000000000000000100000000000000000000000000000" => slv_ip2bus_data <= slv_reg34; when "0000000000000000000000000000000000010000000000000000000000000000" => slv_ip2bus_data <= slv_reg35; when "0000000000000000000000000000000000001000000000000000000000000000" => slv_ip2bus_data <= slv_reg36; when "0000000000000000000000000000000000000100000000000000000000000000" => slv_ip2bus_data <= slv_reg37; when "0000000000000000000000000000000000000010000000000000000000000000" => slv_ip2bus_data <= slv_reg38; when "0000000000000000000000000000000000000001000000000000000000000000" => slv_ip2bus_data <= slv_reg39; -- when "0000000000000000000000000000000000000000000000001000000000000000" => slv_ip2bus_data <= slv_reg48_r1; when "0000000000000000000000000000000000000000000000000100000000000000" => slv_ip2bus_data <= slv_reg49_r1; when "0000000000000000000000000000000000000000000000000010000000000000" => slv_ip2bus_data <= slv_reg50_r1; when "0000000000000000000000000000000000000000000000000001000000000000" => slv_ip2bus_data <= slv_reg51_r1; -- when "0000000000000000000000000000000000000000000000000000000100000000" => slv_ip2bus_data <= slv_reg55; when "0000000000000000000000000000000000000000000000000000000010000000" => slv_ip2bus_data <= slv_reg56; when "0000000000000000000000000000000000000000000000000000000001000000" => slv_ip2bus_data <= slv_reg57; when "0000000000000000000000000000000000000000000000000000000000100000" => slv_ip2bus_data <= slv_reg58; when "0000000000000000000000000000000000000000000000000000000000010000" => slv_ip2bus_data <= slv_reg59; when "0000000000000000000000000000000000000000000000000000000000001000" => slv_ip2bus_data <= slv_reg60; when "0000000000000000000000000000000000000000000000000000000000000100" => slv_ip2bus_data <= slv_reg61; when "0000000000000000000000000000000000000000000000000000000000000010" => slv_ip2bus_data <= slv_reg62; when "0000000000000000000000000000000000000000000000000000000000000001" => slv_ip2bus_data <= slv_reg63; when others => slv_ip2bus_data <= (others => '0'); end case; end process SLAVE_REG_READ_PROC; ------------------------------------------ -- Example code to drive IP to Bus signals ------------------------------------------ IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0'); IP2Bus_WrAck <= slv_write_ack; IP2Bus_RdAck <= slv_read_ack; IP2Bus_Error <= '0'; -- -- HOST Interface - SPI -- host_spi_clk <= Bus2IP_Clk; host_spi_txfifo_clk <= Bus2IP_Clk; host_spi_rxfifo_clk <= Bus2IP_Clk; host_spi_process : process ( Bus2IP_Clk ) begin if Bus2IP_Clk'event and Bus2IP_Clk = '1' then if Bus2IP_Resetn = '0' then host_vita_reset <= '0'; host_spi_reset <= '0'; host_spi_timing <= (others => '0'); host_spi_txfifo_wen_a1 <= '0'; host_spi_txfifo_wen <= '0'; host_spi_txfifo_din <= (others => '0'); host_spi_rxfifo_ren <= '0'; else -- 0x00 - SPI_CONTROL -- [ 0] VITA_RESET -- [ 1] SPI_RESET -- [ 8] SPI_STATUS_BUSY -- [ 9] SPI_STATUS_ERROR -- [16] SPI_TXFIFO_FULL -- [24] SPI_RXFIFO_EMPTY host_vita_reset <= slv_reg0(0); host_spi_reset <= slv_reg0(1); host_spi_timing <= slv_reg1(15 downto 0); -- slv_reg2 is valid 1 cycle after slv_reg_write_sel(63-2) host_spi_txfifo_wen_a1 <= slv_reg_write_sel(63-2); host_spi_txfifo_wen <= host_spi_txfifo_wen_a1; host_spi_txfifo_din <= slv_reg2; -- use write to pop value from RXFIFO ... host_spi_rxfifo_ren <= slv_reg_write_sel(63-3); end if; end if; end process host_spi_process; slv_reg4_w1 <= slv_reg4; slv_reg5_w1 <= slv_reg5; slv_reg6_w1 <= slv_reg6; slv_reg8_w1 <= slv_reg8; slv_reg9_w1 <= slv_reg9; slv_reg10_w1 <= slv_reg10; slv_reg11_w1 <= slv_reg11; slv_reg12_w1 <= slv_reg12; slv_reg13_w1 <= slv_reg13; slv_reg23_w1 <= slv_reg23; slv_reg24_w1 <= slv_reg24; slv_reg25_w1 <= slv_reg25; slv_reg26_w1 <= slv_reg26; slv_reg27_w1 <= slv_reg27; slv_reg28_w1 <= slv_reg28; slv_reg30_w1 <= slv_reg30; -- slv_reg32_w1 <= slv_reg32; slv_reg33_w1 <= slv_reg33; slv_reg34_w1 <= slv_reg34; slv_reg35_w1 <= slv_reg35; slv_reg36_w1 <= slv_reg36; slv_reg37_w1 <= slv_reg37; slv_reg38_w1 <= slv_reg38; slv_reg39_w1 <= slv_reg39; -- slv_reg55_w1 <= slv_reg55; slv_reg56_w1 <= slv_reg56; slv_reg57_w1 <= slv_reg57; slv_reg58_w1 <= slv_reg58; slv_reg59_w1 <= slv_reg59; slv_reg60_w1 <= slv_reg60; slv_reg61_w1 <= slv_reg61; slv_reg62_w1 <= slv_reg62; slv_reg63_w1 <= slv_reg63; host_iserdes_process : process ( clk ) begin if clk'event and clk = '1' then if reset = '1' then -- slv_reg4_w1 <= (others => '0'); slv_reg4_r1 <= (others => '0'); -- slv_reg5_w1 <= (others => '0'); -- slv_reg6_w1 <= (others => '0'); -- slv_reg8_w1 <= (others => '0'); -- slv_reg9_w1 <= (others => '0'); -- slv_reg10_w1 <= (others => '0'); -- slv_reg11_w1 <= (others => '0'); -- slv_reg12_w1 <= (others => '0'); -- slv_reg13_w1 <= (others => '0'); slv_reg14_r1 <= (others => '0'); slv_reg15_r1 <= (others => '0'); slv_reg16_r1 <= (others => '0'); slv_reg17_r1 <= (others => '0'); slv_reg18_r1 <= (others => '0'); slv_reg19_r1 <= (others => '0'); slv_reg20_r1 <= (others => '0'); slv_reg21_r1 <= (others => '0'); slv_reg22_r1 <= (others => '0'); -- slv_reg23_w1 <= (others => '0'); -- slv_reg24_w1 <= (others => '0'); -- slv_reg25_w1 <= (others => '0'); -- slv_reg26_w1 <= (others => '0'); -- slv_reg27_w1 <= (others => '0'); -- slv_reg28_w1 <= (others => '0'); slv_reg29_r1 <= (others => '0'); -- slv_reg30_w1 <= (others => '0'); -- -- slv_reg32_w1 <= (others => '0'); -- slv_reg33_w1 <= (others => '0'); -- slv_reg34_w1 <= (others => '0'); -- slv_reg35_w1 <= (others => '0'); -- slv_reg36_w1 <= (others => '0'); -- slv_reg37_w1 <= (others => '0'); -- slv_reg38_w1 <= (others => '0'); -- slv_reg39_w1 <= (others => '0'); -- slv_reg48_r1 <= (others => '0'); slv_reg49_r1 <= (others => '0'); slv_reg50_r1 <= (others => '0'); slv_reg51_r1 <= (others => '0'); -- -- slv_reg55_w1 <= (others => '0'); -- slv_reg56_w1 <= (others => '0'); -- slv_reg57_w1 <= (others => '0'); -- slv_reg58_w1 <= (others => '0'); -- slv_reg59_w1 <= (others => '0'); -- slv_reg60_w1 <= (others => '0'); -- slv_reg61_w1 <= (others => '0'); -- slv_reg62_w1 <= (others => '0'); -- slv_reg63_w1 <= (others => '0'); -- host_iserdes_reset <= '0'; host_iserdes_auto_align <= '0'; host_iserdes_align_start <= '0'; host_iserdes_fifo_enable <= '0'; host_iserdes_training <= (others => '0'); host_iserdes_manual_tap <= (others => '0'); -- host_fpn_prnu_values <= (others => '0'); -- host_triggen_enable <= (others => '0'); host_triggen_sync2readout <= (others => '0'); host_triggen_readouttrigger <= '0'; host_triggen_default_freq <= (others => '0'); host_triggen_cnt_trigger0high <= (others => '0'); host_triggen_cnt_trigger0low <= (others => '0'); host_triggen_cnt_trigger1high <= (others => '0'); host_triggen_cnt_trigger1low <= (others => '0'); host_triggen_cnt_trigger2high <= (others => '0'); host_triggen_cnt_trigger2low <= (others => '0'); host_triggen_ext_debounce <= (others => '0'); host_triggen_ext_polarity <= '0'; host_triggen_cnt_update <= '0'; else -- slv_reg4_w1 <= slv_reg4; -- slv_reg5_w1 <= slv_reg5; -- slv_reg6_w1 <= slv_reg6; -- slv_reg8_w1 <= slv_reg8; -- slv_reg9_w1 <= slv_reg9; -- slv_reg10_w1 <= slv_reg10; -- slv_reg11_w1 <= slv_reg11; -- slv_reg12_w1 <= slv_reg12; -- slv_reg13_w1 <= slv_reg13; -- slv_reg23_w1 <= slv_reg23; -- slv_reg24_w1 <= slv_reg24; -- slv_reg25_w1 <= slv_reg25; -- slv_reg26_w1 <= slv_reg26; -- slv_reg27_w1 <= slv_reg27; -- slv_reg28_w1 <= slv_reg28; -- slv_reg30_w1 <= slv_reg30; -- -- slv_reg32_w1 <= slv_reg32; -- slv_reg33_w1 <= slv_reg33; -- slv_reg34_w1 <= slv_reg34; -- slv_reg35_w1 <= slv_reg35; -- slv_reg36_w1 <= slv_reg36; -- slv_reg37_w1 <= slv_reg37; -- slv_reg38_w1 <= slv_reg38; -- slv_reg39_w1 <= slv_reg39; -- -- slv_reg55_w1 <= slv_reg55; -- slv_reg56_w1 <= slv_reg56; -- slv_reg57_w1 <= slv_reg57; -- slv_reg58_w1 <= slv_reg58; -- slv_reg59_w1 <= slv_reg59; -- slv_reg60_w1 <= slv_reg60; -- slv_reg61_w1 <= slv_reg61; -- slv_reg62_w1 <= slv_reg62; -- slv_reg63_w1 <= slv_reg63; -- -- 0x10 - ISERDES_CONTROL -- [ 0] ISERDES_RESET -- [ 1] ISERDES_AUTO_ALIGN -- [ 2] ISERDES_ALIGN_START -- [ 3] ISERDES_FIFO_ENABLE -- [ 8] ISERDES_CLK_READY -- [ 9] ISERDES_ALIGN_BUSY -- [10] ISERDES_ALIGNED -- [23:16] ISERDES_TXCLK_STATUS -- [31:24] ISERDES_RXCLK_STATUS host_iserdes_reset <= slv_reg4_w1(0); host_iserdes_auto_align <= slv_reg4_w1(1); host_iserdes_align_start <= slv_reg4_w1(2); host_iserdes_fifo_enable <= slv_reg4_w1(3); slv_reg4_r1 <= host_iserdes_clk_status & "00000" & host_iserdes_aligned & host_iserdes_align_busy & host_iserdes_clk_ready & "0000" & host_iserdes_fifo_enable & host_iserdes_align_start & host_iserdes_auto_align & host_iserdes_reset; -- -- 0x14 - ISERDES_TRAINING host_iserdes_training <= slv_reg5_w1(9 downto 0); -- -- 0x18 - ISERDES_MANUAL_TAP host_iserdes_manual_tap <= slv_reg6_w1(9 downto 0); -- -- 0x20 - DECODER_CONTROL[7:0] -- [0] DECODER_RESET -- [1] DECODER_ENABLE host_decoder_reset <= slv_reg8_w1(0); host_decoder_enable <= slv_reg8_w1(1); -- -- 0x24 - DECODER_STARTODDEVEN host_decoder_startoddeven <= slv_reg9_w1; -- -- 0x28 - DECODER_CODES_LS_LE host_decoder_code_ls <= slv_reg10_w1( 9 downto 0); host_decoder_code_le <= slv_reg10_w1(25 downto 16); -- -- 0x2C - DECODER_CODES_FS_FE host_decoder_code_fs <= slv_reg11_w1( 9 downto 0); host_decoder_code_fe <= slv_reg11_w1(25 downto 16); -- -- 0x30 - DECODER_CODES_BL_IMG host_decoder_code_bl <= slv_reg12_w1( 9 downto 0); host_decoder_code_img <= slv_reg12_w1(25 downto 16); -- -- 0x34 - DECODER_CODES_TR_CRC host_decoder_code_tr <= slv_reg13_w1( 9 downto 0); host_decoder_code_crc <= slv_reg13_w1(25 downto 16); if ( host_decoder_frame_start = '1' ) then -- -- 0x38 - DECODER_CNT_BLACK_LINES slv_reg14_r1 <= host_decoder_cnt_black_lines; -- -- 0x3C - DECODER_CNT_IMAGE_LINES slv_reg15_r1 <= host_decoder_cnt_image_lines; -- -- 0x40 - DECODER_CNT_BLACK_PIXELS slv_reg16_r1 <= host_decoder_cnt_black_pixels; -- -- 0x44 - DECODER_CNT_IMAGE_PIXELS slv_reg17_r1 <= host_decoder_cnt_image_pixels; -- -- 0x48 - DECODER_CNT_FRAMES slv_reg18_r1 <= host_decoder_cnt_frames; -- -- 0x4C - DECODER_CNT_WINDOWS slv_reg19_r1 <= host_decoder_cnt_windows; -- -- 0x50 - DECODER_CNT_CLOCKS slv_reg20_r1 <= host_decoder_cnt_clocks; -- -- 0x54 - DECODER_CNT_START_LINES slv_reg21_r1 <= host_decoder_cnt_start_lines; -- -- 0x58 - DECODER_CNT_END_LINES slv_reg22_r1 <= host_decoder_cnt_end_lines; end if; --if ( host_decoder_frame_start = '1' ) then -- 0x5C - SYNCGEN_DELAY -- [15: 0] DELAY host_syncgen_delay <= slv_reg23_w1(15 downto 0); -- 0x60 - SYNCGEN_HTIMING1 -- [15: 0] HACTIVE -- [31:16] HFPORCH -- 0x64 - SYNCGEN_HTIMING2 -- [15: 0] HSYNC -- [31:16] HBPORCH -- 0x68 - SYNCGEN_VTIMING1 -- [15: 0] VACTIVE -- [31:16] VFPORCH -- 0x6C - SYNCGEN_VTIMING2 -- [15: 0] VSYNC -- [31:16] VBPORCH host_syncgen_hactive <= slv_reg24_w1(15 downto 0); host_syncgen_hfporch <= slv_reg24_w1(31 downto 16); host_syncgen_hsync <= slv_reg25_w1(15 downto 0); host_syncgen_hbporch <= slv_reg25_w1(31 downto 16); host_syncgen_vactive <= slv_reg26_w1(15 downto 0); host_syncgen_vfporch <= slv_reg26_w1(31 downto 16); host_syncgen_vsync <= slv_reg27_w1(15 downto 0); host_syncgen_vbporch <= slv_reg27_w1(31 downto 16); -- -- 0x70 - CRC_CONTROL[7:0] -- [0] CRC_RESET -- [1] CRC_INITVALUE host_crc_reset <= slv_reg28_w1(0); host_crc_initvalue <= slv_reg28_w1(1); -- -- 0x74 - CRC_STATUS slv_reg29_r1 <= host_crc_status; -- -- 0x78 - REMAPPER_CONTROL[7:0] -- [2:0] REMAPPER_WRITE_CFG -- [6:4] REMAPPER_MODE host_remapper_write_cfg <= slv_reg30_w1(2 downto 0); host_remapper_mode <= slv_reg30_w1(6 downto 4); -- 0x80 - FPN_PRNU_VALUES[ 31: 0] -- 0x84 - FPN_PRNU_VALUES[ 63: 32] -- 0x88 - FPN_PRNU_VALUES[ 95: 64] -- 0x8C - FPN_PRNU_VALUES[127: 96] -- 0x90 - FPN_PRNU_VALUES[159:128] -- 0x94 - FPN_PRNU_VALUES[191:160] -- 0x98 - FPN_PRNU_VALUES[223:192] -- 0x9C - FPN_PRNU_VALUES[255:224] host_fpn_prnu_values( 31 downto 0) <= slv_reg32_w1; host_fpn_prnu_values( 63 downto 32) <= slv_reg33_w1; host_fpn_prnu_values( 95 downto 64) <= slv_reg34_w1; host_fpn_prnu_values(127 downto 96) <= slv_reg35_w1; host_fpn_prnu_values(159 downto 128) <= slv_reg36_w1; host_fpn_prnu_values(191 downto 160) <= slv_reg37_w1; host_fpn_prnu_values(223 downto 192) <= slv_reg38_w1; host_fpn_prnu_values(255 downto 224) <= slv_reg39_w1; -- -- 0xC0 - DECODER_CNT_MONITOR0_HIGH slv_reg48_r1 <= host_decoder_cnt_monitor0high; -- -- 0xC4 - DECODER_CNT_MONITOR0_LOW slv_reg49_r1 <= host_decoder_cnt_monitor0low; -- -- 0xC8 - DECODER_CNT_MONITOR1_HIGH slv_reg50_r1 <= host_decoder_cnt_monitor1high; -- -- 0xCC - DECODER_CNT_MONITOR1_LOW slv_reg51_r1 <= host_decoder_cnt_monitor1low; -- -- 0xDC - TRIGGEN_EXT_DEBOUNCE host_triggen_ext_debounce <= slv_reg55_w1; -- -- 0xE0 - TRIGGEN_CONTROL -- [ 2: 0] TRIGGEN_ENABLE -- [ 6: 4] TRIGGEN_SYNC2READOUT -- [ 8] TRIGGEN_READOUTTRIGGER -- [ 16] TRIGGEN_EXT_POLARITY -- [ 24] TRIGGEN_CNT_UPDATE -- [30:28] TRIGGEN_GEN_POLARITY host_triggen_enable <= slv_reg56_w1(2 downto 0); host_triggen_sync2readout <= slv_reg56_w1(6 downto 4); host_triggen_readouttrigger <= slv_reg56_w1(8); host_triggen_ext_polarity <= slv_reg56_w1(16); host_triggen_cnt_update <= slv_reg56_w1(24); host_triggen_gen_polarity <= slv_reg56_w1(30 downto 28); -- -- 0xE4 - TRIGGEN_DEFAULT_FREQ host_triggen_default_freq <= slv_reg57_w1; -- if ( host_triggen_cnt_update = '1' ) then -- -- 0xE8 - TRIGGEN_TRIG0_HIGH host_triggen_cnt_trigger0high <= slv_reg58_w1; -- -- 0xEC - TRIGGEN_TRIG0_LOW host_triggen_cnt_trigger0low <= slv_reg59_w1; -- -- 0xF0 - TRIGGEN_TRIG1_HIGH host_triggen_cnt_trigger1high <= slv_reg60_w1; -- -- 0xF4 - TRIGGEN_TRIG1_LOW host_triggen_cnt_trigger1low <= slv_reg61_w1; -- -- 0xF8 - TRIGGEN_TRIG2_HIGH host_triggen_cnt_trigger2high <= slv_reg62_w1; -- -- 0xFC - TRIGGEN_TRIG2_LOW host_triggen_cnt_trigger2low <= slv_reg63_w1; -- end if; -- if ( host_triggen_cnt_update == '1' ) then end if; end if; end process host_iserdes_process; ------------------------------------------ -- VITA Receiver Core Logic ------------------------------------------ VITA_CORE_I : entity fmc_imageon_vita_receiver_v1_13_a.fmc_imageon_vita_core generic map ( C_XSVI_DATA_WIDTH => C_XSVI_DATA_WIDTH, C_XSVI_DIRECT_OUTPUT => C_XSVI_DIRECT_OUTPUT, C_XSVI_USE_SYNCGEN => C_XSVI_USE_SYNCGEN, C_FAMILY => C_FAMILY ) port map ( clk200 => clk200, clk => clk, clk4x => clk4x, reset => reset, oe => oe, -- HOST Interface - VITA host_vita_reset => host_vita_reset, -- HOST Interface - SPI host_spi_clk => host_spi_clk, host_spi_reset => host_spi_reset, host_spi_timing => host_spi_timing, host_spi_status_busy => host_spi_status_busy, host_spi_status_error => host_spi_status_error, host_spi_txfifo_clk => host_spi_txfifo_clk, host_spi_txfifo_wen => host_spi_txfifo_wen, host_spi_txfifo_din => host_spi_txfifo_din, host_spi_txfifo_full => host_spi_txfifo_full, host_spi_rxfifo_clk => host_spi_rxfifo_clk, host_spi_rxfifo_ren => host_spi_rxfifo_ren, host_spi_rxfifo_dout => host_spi_rxfifo_dout, host_spi_rxfifo_empty => host_spi_rxfifo_empty, -- HOST Interface - ISERDES host_iserdes_reset => host_iserdes_reset, host_iserdes_auto_align => host_iserdes_auto_align, host_iserdes_align_start => host_iserdes_align_start, host_iserdes_fifo_enable => host_iserdes_fifo_enable, host_iserdes_manual_tap => host_iserdes_manual_tap, host_iserdes_training => host_iserdes_training, host_iserdes_clk_ready => host_iserdes_clk_ready, host_iserdes_clk_status => host_iserdes_clk_status, host_iserdes_align_busy => host_iserdes_align_busy, host_iserdes_aligned => host_iserdes_aligned, -- HOST Interface - Sync Channel Decoder host_decoder_reset => host_decoder_reset, host_decoder_enable => host_decoder_enable, host_decoder_startoddeven => host_decoder_startoddeven, host_decoder_code_ls => host_decoder_code_ls, host_decoder_code_le => host_decoder_code_le, host_decoder_code_fs => host_decoder_code_fs, host_decoder_code_fe => host_decoder_code_fe, host_decoder_code_bl => host_decoder_code_bl, host_decoder_code_img => host_decoder_code_img, host_decoder_code_tr => host_decoder_code_tr, host_decoder_code_crc => host_decoder_code_crc, host_decoder_frame_start => host_decoder_frame_start, host_decoder_cnt_black_lines => host_decoder_cnt_black_lines, host_decoder_cnt_image_lines => host_decoder_cnt_image_lines, host_decoder_cnt_black_pixels => host_decoder_cnt_black_pixels, host_decoder_cnt_image_pixels => host_decoder_cnt_image_pixels, host_decoder_cnt_frames => host_decoder_cnt_frames, host_decoder_cnt_windows => host_decoder_cnt_windows, host_decoder_cnt_clocks => host_decoder_cnt_clocks, host_decoder_cnt_start_lines => host_decoder_cnt_start_lines, host_decoder_cnt_end_lines => host_decoder_cnt_end_lines, host_decoder_cnt_monitor0high => host_decoder_cnt_monitor0high, host_decoder_cnt_monitor0low => host_decoder_cnt_monitor0low, host_decoder_cnt_monitor1high => host_decoder_cnt_monitor1high, host_decoder_cnt_monitor1low => host_decoder_cnt_monitor1low, -- HOST Interface - CRC Checker host_crc_reset => host_crc_reset, host_crc_initvalue => host_crc_initvalue, host_crc_status => host_crc_status, -- HOST Interface - Data Channel Remapper host_remapper_write_cfg => host_remapper_write_cfg, host_remapper_mode => host_remapper_mode, -- HOST Interface - Trigger Generator host_triggen_enable => host_triggen_enable, host_triggen_sync2readout => host_triggen_sync2readout, host_triggen_readouttrigger => host_triggen_readouttrigger, host_triggen_default_freq => host_triggen_default_freq, host_triggen_cnt_trigger0high => host_triggen_cnt_trigger0high, host_triggen_cnt_trigger0low => host_triggen_cnt_trigger0low, host_triggen_cnt_trigger1high => host_triggen_cnt_trigger1high, host_triggen_cnt_trigger1low => host_triggen_cnt_trigger1low, host_triggen_cnt_trigger2high => host_triggen_cnt_trigger2high, host_triggen_cnt_trigger2low => host_triggen_cnt_trigger2low, host_triggen_ext_debounce => host_triggen_ext_debounce, host_triggen_ext_polarity => host_triggen_ext_polarity, host_triggen_gen_polarity => host_triggen_gen_polarity, -- HOST Interface - FPN/PRNU Correction host_fpn_prnu_values => host_fpn_prnu_values, -- HOST Interface - Sync Generator host_syncgen_delay => host_syncgen_delay, host_syncgen_hactive => host_syncgen_hactive, host_syncgen_hfporch => host_syncgen_hfporch, host_syncgen_hsync => host_syncgen_hsync, host_syncgen_hbporch => host_syncgen_hbporch, host_syncgen_vactive => host_syncgen_vactive, host_syncgen_vfporch => host_syncgen_vfporch, host_syncgen_vsync => host_syncgen_vsync, host_syncgen_vbporch => host_syncgen_vbporch, -- I/O pins io_vita_clk_pll => io_vita_clk_pll, io_vita_reset_n => io_vita_reset_n, io_vita_spi_sclk => io_vita_spi_sclk, io_vita_spi_ssel_n => io_vita_spi_ssel_n, io_vita_spi_mosi => io_vita_spi_mosi, io_vita_spi_miso => io_vita_spi_miso, io_vita_trigger => io_vita_trigger, io_vita_monitor => io_vita_monitor, io_vita_clk_out_p => io_vita_clk_out_p, io_vita_clk_out_n => io_vita_clk_out_n, io_vita_sync_p => io_vita_sync_p, io_vita_sync_n => io_vita_sync_n, io_vita_data_p => io_vita_data_p, io_vita_data_n => io_vita_data_n, -- Trigger Port trigger1 => trigger1, -- Frame Sync Port fsync => fsync, -- XSVI Port xsvi_vsync_o => xsvi_vsync_o, xsvi_hsync_o => xsvi_hsync_o, xsvi_vblank_o => xsvi_vblank_o, xsvi_hblank_o => xsvi_hblank_o, xsvi_active_video_o => xsvi_active_video_o, xsvi_video_data_o => xsvi_video_data_o, -- Debug Port debug_spi_o => debug_spi_o, debug_iserdes_o => debug_iserdes_o, debug_decoder_o => debug_decoder_o, debug_crc_o => debug_crc_o, debug_triggen_o => debug_triggen_o, debug_video_o => debug_video_o ); -- -- Debug Port -- Can be used to connect to ChipScope for debugging. -- Having a port makes these signals accessible for debug via EDK. -- debug_host_l : process (Bus2IP_Clk) begin if Rising_Edge(Bus2IP_Clk) then debug_host_o( 31 downto 0) <= Bus2IP_Addr; debug_host_o( 63 downto 32) <= Bus2IP_Data; debug_host_o( 95 downto 64) <= slv_ip2bus_data; debug_host_o(159 downto 96) <= Bus2IP_WrCE; debug_host_o(223 downto 160) <= Bus2IP_RdCE; debug_host_o( 224) <= Bus2IP_CS(0); debug_host_o( 225) <= Bus2IP_RNW; debug_host_o(229 downto 226) <= Bus2IP_BE; debug_host_o( 230) <= slv_write_ack; debug_host_o( 231) <= slv_read_ack; end if; end process; end IMP;

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Martin Zabel -- -- Module: Clock Generator for Memory Test on Spartan-3E Starter Kit -- -- Description: -- ------------------------------------ -- DCM configuration for module 'memtest_s3esk'. -- -- The DCMs dcm_mem* have either unstable input clocks upon configuration and/or -- external feedback, and thus must be reset accordingly. So we do not use -- the STARTUP_WAIT feature at all. -- -- After startup the clocks are unstable. Thus, the logic -- clocked by clk_* must be hold in reset until rst_* is deasserted. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ ------------------------------------------------------------------------------- -- Naming Conventions: -- (Based on: Keating and Bricaud: "Reuse Methodology Manual") -- -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: all UPPERCASE -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- output of a register: "*_r" -- asynchronous signal: "*_a" -- pipelined or register delay signals: "*_p#" -- data before being registered into register with the same name: "*_nxt" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- tristate internal signal "*_z" ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.ALL; entity memtest_s3esk_clockgen is port ( clk_in : in std_logic; sd_ck_fb : in std_logic; user_rst : in std_logic; clk_sys : out std_logic; clk_mem : out std_logic; clk_mem_n : out std_logic; clk_mem90 : out std_logic; clk_mem90_n : out std_logic; clk_memfb90 : out std_logic; clk_memfb90_n : out std_logic; rst_sys : out std_logic; rst_mem : out std_logic; rst_mem90 : out std_logic; rst_mem180 : out std_logic; rst_mem270 : out std_logic; rst_memfb90 : out std_logic; rst_memfb270 : out std_logic; locked : out std_logic); end memtest_s3esk_clockgen; library unisim; use unisim.VComponents.all; architecture rtl of memtest_s3esk_clockgen is -- input buffer signal clk_in_bufo : std_logic; signal sd_ck_fb_bufo : std_logic; -- clock buffer inputs signal clk_sys_bufi : std_logic; signal clk_dv_bufi : std_logic; signal clk_mem_bufi : std_logic; signal clk_mem90_bufi : std_logic; signal clk_memfb90_bufi : std_logic; signal clk_memfb90_n_bufi : std_logic; -- global clocks (internal signals) signal clk_sys_i : std_logic; signal clk_mem_i : std_logic; signal clk_mem_n_i : std_logic; signal clk_mem90_i : std_logic; signal clk_mem90_n_i : std_logic; signal clk_memfb90_i : std_logic; signal clk_memfb90_n_i : std_logic; -- dcm reset signal dcm_mem_rst : std_logic; signal dcm_memfb_rst : std_logic; -- locked signals signal dcm_sys_locked : std_logic; signal dcm_mem_locked : std_logic; signal dcm_mem90_locked : std_logic; signal dcm_memfb_locked : std_logic; -- reset synchronizers for clk_sys, clk_mem* and clk_memfb* signal rst_sys_r : std_logic_vector(1 downto 0); signal rst_mem_r : std_logic_vector(1 downto 0); signal rst_mem90_r : std_logic_vector(1 downto 0); signal rst_mem180_r : std_logic_vector(1 downto 0); signal rst_mem270_r : std_logic_vector(1 downto 0); signal rst_memfb90_r : std_logic_vector(1 downto 0); signal rst_memfb270_r : std_logic_vector(1 downto 0); -- internal version of output signals signal locked_i : std_logic; -- do reset signal do_rst : std_logic; begin ----------------------------------------------------------------------------- -- 0. Input Clock buffer and system clock. ----------------------------------------------------------------------------- clk_in_buf : IBUFG port map ( I => clk_in, O => clk_in_bufo); ----------------------------------------------------------------------------- -- 1. System clock. ----------------------------------------------------------------------------- dcm_sys : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.0, -- period of input clock (50 Mhz) DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, CLK_FEEDBACK => "1X", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "NONE", PHASE_SHIFT => 0, CLKDV_DIVIDE => 2.0, FACTORY_JF => X"C080") -- ? port map ( CLK0 => clk_sys_bufi, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => clk_dv_bufi, CLKFX => open, CLKFX180 => open, LOCKED => dcm_sys_locked, PSDONE => open, STATUS => open, CLKFB => clk_sys_i, CLKIN => clk_in_bufo, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => '0'); clk_sys_buf : BUFG port map ( I => clk_sys_bufi, O => clk_sys_i); clk_sys <= clk_sys_i; -- clk_sys is stable as soon as GWE (Global Write Enable) is asserted. -- See documentation in file header. ----------------------------------------------------------------------------- -- 2. Generate memory clocks. -- -- The reset logic for this DCM has to wait until clk_sys gets stable. -- The reset must be asserted for three valid CLKIN cycles or longer. -- -- IMPORTANT NOTE: -- Yes dcm_mem and dcm_mem90 might be merged, if doubled input clock is -- generated by dcm_sys and then clk0 and clk90 DCM outputs are used. But -- these requires a DCM input clock of 100 MHz, which is out of specification -- for Spartan-3E stepping 0. ----------------------------------------------------------------------------- dcm_mem_rst_gen : SRLC16E generic map ( INIT => x"FFFF") -- hold reset for 16 clock cycles port map ( clk => clk_sys_i, ce => dcm_sys_locked, -- wait until clk_sys is stable d => '0', -- finished a0 => '1', a1 => '1', a2 => '1', a3 => '1', q => open, q15 => dcm_mem_rst); dcm_mem : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.0, -- 50 MHz DLL_FREQUENCY_MODE => "LOW", -- no specification found in manual DUTY_CYCLE_CORRECTION => FALSE, -- already 50 % CLK_FEEDBACK => "2X", DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "NONE", PHASE_SHIFT => 0, FACTORY_JF => X"C080") -- ? port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => clk_mem_bufi, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm_mem_locked, PSDONE => open, STATUS => open, CLKFB => clk_mem_i, CLKIN => clk_sys_i, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => dcm_mem_rst); dcm_mem90 : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.0, -- 50 MHz DLL_FREQUENCY_MODE => "LOW", -- no specification found in manual DUTY_CYCLE_CORRECTION => FALSE, -- already 50 % CLK_FEEDBACK => "2X", DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 32, -- 90° @ CLK2x FACTORY_JF => X"C080") -- ? port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => clk_mem90_bufi, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm_mem90_locked, PSDONE => open, STATUS => open, CLKFB => clk_mem90_i, CLKIN => clk_sys_i, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => dcm_mem_rst); clk_mem_buf : BUFG port map ( I => clk_mem_bufi, O => clk_mem_i); clk_mem_n_i <= not clk_mem_i; clk_mem90_buf : BUFG port map ( I => clk_mem90_bufi, O => clk_mem90_i); clk_mem90_n_i <= not clk_mem90_i; clk_mem <= clk_mem_i; clk_mem_n <= clk_mem_n_i; clk_mem90 <= clk_mem90_i; clk_mem90_n <= clk_mem90_n_i; ----------------------------------------------------------------------------- -- 3. Synchronized read clock for DDR-SDRAM controller. -- -- The reset logic for this DCM has to wait until clk_mem gets stable. -- The reset must be asserted for three valid CLKIN cycles or longer. -- Due to the external feedback, the number of cycles should be greater. ----------------------------------------------------------------------------- dcm_memfb_rst_gen : SRLC16E generic map ( INIT => x"FFFF") -- hold reset for 16 clock cycles port map ( clk => clk_mem_i, ce => dcm_mem_locked, -- wait until clk_mem is stable d => '0', -- finished a0 => '1', a1 => '1', a2 => '1', a3 => '1', q => open, q15 => dcm_memfb_rst); sd_ck_fb_buf : IBUFG port map ( I => sd_ck_fb, O => sd_ck_fb_bufo); dcm_memfb : DCM_SP generic map ( CLKIN_DIVIDE_BY_2 => TRUE, CLKIN_PERIOD => 10.0, -- period of input clock (100 Mhz) DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => FALSE, -- already 50 % CLK_FEEDBACK => "2X", DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- no deskew CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 32+5, -- 90° +/- x @ CLK2X FACTORY_JF => X"C080") port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => clk_memfb90_bufi, CLK2X180 => clk_memfb90_n_bufi, CLK90 => open, CLKDV => open, CLKFX => open, CLKFX180 => open, LOCKED => dcm_memfb_locked, PSDONE => open, STATUS => open, CLKFB => clk_memfb90_i, CLKIN => sd_ck_fb_bufo, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => dcm_memfb_rst); clk_memfb90_buf : BUFG port map ( I => clk_memfb90_bufi, O => clk_memfb90_i); clk_memfb90_n_buf : BUFG port map ( I => clk_memfb90_n_bufi, O => clk_memfb90_n_i); clk_memfb90 <= clk_memfb90_i; clk_memfb90_n <= clk_memfb90_n_i; ----------------------------------------------------------------------------- -- 4. Locked & Resets -- -- Coordinated Reset removal: -- - First, remove reset of clk_mem*, because it always waits for commands -- before it writes anything to the read FIFO. -- - Second, remove reset from clk_sys because it writes to the command FIFO -- as soon as possible. But at this time, the rst_rd from that FIFO must -- not be asserted, so that the write_addr is correctly transfered between -- the clock domains (gray-encoding is kept). ----------------------------------------------------------------------------- locked_i <= dcm_sys_locked and dcm_mem_locked and dcm_mem90_locked and dcm_memfb_locked; locked <= locked_i; do_rst <= (not locked_i) or user_rst; -- synchronize locked_i with clock domain clk_sys process (do_rst, clk_sys_i) begin -- process if do_rst = '1' then rst_sys_r <= (others => '1'); elsif rising_edge(clk_sys_i) then rst_sys_r(0) <= rst_mem_r(rst_mem_r'left); -- release as second rst_sys_r(rst_sys_r'left downto 1) <= rst_sys_r(rst_sys_r'left-1 downto 0); end if; end process; rst_sys <= rst_sys_r(rst_sys_r'left); -- synchronize locked_i with clock domain clk_mem process (do_rst, clk_mem_i) begin -- process if do_rst = '1' then rst_mem_r <= (others => '1'); elsif rising_edge(clk_mem_i) then rst_mem_r(0) <= '0'; rst_mem_r(rst_mem_r'left downto 1) <= rst_mem_r(rst_mem_r'left-1 downto 0); end if; end process; rst_mem <= rst_mem_r(rst_mem_r'left); -- synchronize locked_i with clock domain clk_mem90 process (do_rst, clk_mem90_i) begin -- process if do_rst = '1' then rst_mem90_r <= (others => '1'); elsif rising_edge(clk_mem90_i) then rst_mem90_r(0) <= '0'; rst_mem90_r(rst_mem90_r'left downto 1) <= rst_mem90_r(rst_mem90_r'left-1 downto 0); end if; end process; rst_mem90 <= rst_mem90_r(rst_mem90_r'left); -- synchronize locked_i with clock domain clk_mem_n process (do_rst, clk_mem_n_i) begin -- process if do_rst = '1' then rst_mem180_r <= (others => '1'); elsif falling_edge(clk_mem_n_i) then rst_mem180_r(0) <= '0'; rst_mem180_r(rst_mem180_r'left downto 1) <= rst_mem180_r(rst_mem180_r'left-1 downto 0); end if; end process; rst_mem180 <= rst_mem180_r(rst_mem180_r'left); -- synchronize locked_i with clock domain clk_mem90_n process (do_rst, clk_mem90_n_i) begin -- process if do_rst = '1' then rst_mem270_r <= (others => '1'); elsif falling_edge(clk_mem90_n_i) then rst_mem270_r(0) <= '0'; rst_mem270_r(rst_mem270_r'left downto 1) <= rst_mem270_r(rst_mem270_r'left-1 downto 0); end if; end process; rst_mem270 <= rst_mem270_r(rst_mem270_r'left); -- synchronize locked_i with clock domain clk_memfb90 process (do_rst, clk_memfb90_i) begin -- process if do_rst = '1' then rst_memfb90_r <= (others => '1'); elsif rising_edge(clk_memfb90_i) then rst_memfb90_r(0) <= '0'; rst_memfb90_r(rst_memfb90_r'left downto 1) <= rst_memfb90_r(rst_memfb90_r'left-1 downto 0); end if; end process; rst_memfb90 <= rst_memfb90_r(rst_memfb90_r'left); -- synchronize locked_i with clock domain clk_memfb90_n process (do_rst, clk_memfb90_n_i) begin -- process if do_rst = '1' then rst_memfb270_r <= (others => '1'); elsif rising_edge(clk_memfb90_n_i) then rst_memfb270_r(0) <= '0'; rst_memfb270_r(rst_memfb270_r'left downto 1) <= rst_memfb270_r(rst_memfb270_r'left-1 downto 0); end if; end process; rst_memfb270 <= rst_memfb270_r(rst_memfb270_r'left); end rtl;

library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity mul_383 is port ( result : out std_logic_vector(30 downto 0); in_a : in std_logic_vector(30 downto 0); in_b : in std_logic_vector(14 downto 0) ); end mul_383; architecture augh of mul_383 is signal tmp_res : signed(45 downto 0); begin -- The actual multiplication tmp_res <= signed(in_a) * signed(in_b); -- Set the output result <= std_logic_vector(tmp_res(30 downto 0)); end architecture;

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.4 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Loop_loop_height_lbW_rom is generic( dwidth : integer := 8; awidth : integer := 8; mem_size : integer := 256 ); port ( addr0 : in std_logic_vector(awidth-1 downto 0); ce0 : in std_logic; q0 : out std_logic_vector(dwidth-1 downto 0); clk : in std_logic ); end entity; architecture rtl of Loop_loop_height_lbW_rom is signal addr0_tmp : std_logic_vector(awidth-1 downto 0); type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0); signal mem : mem_array := ( 0 => "00000000", 1 => "00000010", 2 => "00000100", 3 => "00000110", 4 => "00001000", 5 => "00001010", 6 => "00001100", 7 => "00001110", 8 => "00010000", 9 => "00010010", 10 => "00010100", 11 => "00010110", 12 => "00010111", 13 => "00011001", 14 => "00011011", 15 => "00011101", 16 => "00011111", 17 => "00100001", 18 => "00100011", 19 => "00100101", 20 => "00100110", 21 => "00101000", 22 => "00101010", 23 => "00101100", 24 => "00101110", 25 => "00110000", 26 => "00110001", 27 => "00110011", 28 => "00110101", 29 => "00110111", 30 => "00111000", 31 => "00111010", 32 => "00111100", 33 => "00111110", 34 => "00111111", 35 => "01000001", 36 => "01000011", 37 => "01000101", 38 => "01000110", 39 => "01001000", 40 => "01001010", 41 => "01001011", 42 => "01001101", 43 => "01001111", 44 => "01010000", 45 => "01010010", 46 => "01010100", 47 => "01010101", 48 => "01010111", 49 => "01011001", 50 => "01011010", 51 => "01011100", 52 => "01011101", 53 => "01011111", 54 => "01100001", 55 => "01100010", 56 => "01100100", 57 => "01100101", 58 => "01100111", 59 => "01101000", 60 => "01101010", 61 => "01101011", 62 => "01101101", 63 => "01101110", 64 => "01110000", 65 => "01110001", 66 => "01110011", 67 => "01110100", 68 => "01110110", 69 => "01110111", 70 => "01111001", 71 => "01111010", 72 => "01111100", 73 => "01111101", 74 => "01111111", 75 => "10000000", 76 => "10000001", 77 => "10000011", 78 => "10000100", 79 => "10000110", 80 => "10000111", 81 => "10001000", 82 => "10001010", 83 => "10001011", 84 => "10001100", 85 => "10001110", 86 => "10001111", 87 => "10010000", 88 => "10010010", 89 => "10010011", 90 => "10010100", 91 => "10010110", 92 => "10010111", 93 => "10011000", 94 => "10011001", 95 => "10011011", 96 => "10011100", 97 => "10011101", 98 => "10011110", 99 => "10100000", 100 => "10100001", 101 => "10100010", 102 => "10100011", 103 => "10100100", 104 => "10100110", 105 => "10100111", 106 => "10101000", 107 => "10101001", 108 => "10101010", 109 => "10101011", 110 => "10101101", 111 => "10101110", 112 => "10101111", 113 => "10110000", 114 => "10110001", 115 => "10110010", 116 => "10110011", 117 => "10110100", 118 => "10110101", 119 => "10110110", 120 => "10111000", 121 => "10111001", 122 => "10111010", 123 => "10111011", 124 => "10111100", 125 => "10111101", 126 => "10111110", 127 => "10111111", 128 => "11000000", 129 => "11000001", 130 => "11000010", 131 => "11000011", 132 => "11000100", 133 => "11000101", 134 => "11000110", 135 to 136=> "11000111", 137 => "11001000", 138 => "11001001", 139 => "11001010", 140 => "11001011", 141 => "11001100", 142 => "11001101", 143 => "11001110", 144 => "11001111", 145 to 146=> "11010000", 147 => "11010001", 148 => "11010010", 149 => "11010011", 150 => "11010100", 151 to 152=> "11010101", 153 => "11010110", 154 => "11010111", 155 => "11011000", 156 to 157=> "11011001", 158 => "11011010", 159 => "11011011", 160 to 161=> "11011100", 162 => "11011101", 163 => "11011110", 164 to 165=> "11011111", 166 => "11100000", 167 to 168=> "11100001", 169 => "11100010", 170 to 171=> "11100011", 172 => "11100100", 173 to 174=> "11100101", 175 => "11100110", 176 to 177=> "11100111", 178 to 179=> "11101000", 180 => "11101001", 181 to 182=> "11101010", 183 to 184=> "11101011", 185 to 186=> "11101100", 187 to 188=> "11101101", 189 to 190=> "11101110", 191 to 192=> "11101111", 193 to 194=> "11110000", 195 to 196=> "11110001", 197 to 198=> "11110010", 199 to 200=> "11110011", 201 to 203=> "11110100", 204 to 205=> "11110101", 206 to 208=> "11110110", 209 to 211=> "11110111", 212 to 214=> "11111000", 215 to 217=> "11111001", 218 to 221=> "11111010", 222 to 225=> "11111011", 226 to 229=> "11111100", 230 to 235=> "11111101", 236 to 243=> "11111110", 244 to 255=> "11111111" ); begin memory_access_guard_0: process (addr0) begin addr0_tmp <= addr0; --synthesis translate_off if (CONV_INTEGER(addr0) > mem_size-1) then addr0_tmp <= (others => '0'); else addr0_tmp <= addr0; end if; --synthesis translate_on end process; p_rom_access: process (clk) begin if (clk'event and clk = '1') then if (ce0 = '1') then q0 <= mem(CONV_INTEGER(addr0_tmp)); end if; end if; end process; end rtl; Library IEEE; use IEEE.std_logic_1164.all; entity Loop_loop_height_lbW is generic ( DataWidth : INTEGER := 8; AddressRange : INTEGER := 256; AddressWidth : INTEGER := 8); port ( reset : IN STD_LOGIC; clk : IN STD_LOGIC; address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0); ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0)); end entity; architecture arch of Loop_loop_height_lbW is component Loop_loop_height_lbW_rom is port ( clk : IN STD_LOGIC; addr0 : IN STD_LOGIC_VECTOR; ce0 : IN STD_LOGIC; q0 : OUT STD_LOGIC_VECTOR); end component; begin Loop_loop_height_lbW_rom_U : component Loop_loop_height_lbW_rom port map ( clk => clk, addr0 => address0, ce0 => ce0, q0 => q0); end architecture;

package body package0 is function fn0 (param0 : bit_vector) return bit is begin -- function code end fn0;

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Tue Sep 19 00:29:48 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_2_sim_netlist.vhdl -- Design : zynq_design_1_processing_system7_0_2 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is port ( CAN0_PHY_TX : out STD_LOGIC; CAN0_PHY_RX : in STD_LOGIC; CAN1_PHY_TX : out STD_LOGIC; CAN1_PHY_RX : in STD_LOGIC; ENET0_GMII_TX_EN : out STD_LOGIC; ENET0_GMII_TX_ER : out STD_LOGIC; ENET0_MDIO_MDC : out STD_LOGIC; ENET0_MDIO_O : out STD_LOGIC; ENET0_MDIO_T : out STD_LOGIC; ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET0_SOF_RX : out STD_LOGIC; ENET0_SOF_TX : out STD_LOGIC; ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET0_GMII_COL : in STD_LOGIC; ENET0_GMII_CRS : in STD_LOGIC; ENET0_GMII_RX_CLK : in STD_LOGIC; ENET0_GMII_RX_DV : in STD_LOGIC; ENET0_GMII_RX_ER : in STD_LOGIC; ENET0_GMII_TX_CLK : in STD_LOGIC; ENET0_MDIO_I : in STD_LOGIC; ENET0_EXT_INTIN : in STD_LOGIC; ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_TX_EN : out STD_LOGIC; ENET1_GMII_TX_ER : out STD_LOGIC; ENET1_MDIO_MDC : out STD_LOGIC; ENET1_MDIO_O : out STD_LOGIC; ENET1_MDIO_T : out STD_LOGIC; ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; ENET1_SOF_RX : out STD_LOGIC; ENET1_SOF_TX : out STD_LOGIC; ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); ENET1_GMII_COL : in STD_LOGIC; ENET1_GMII_CRS : in STD_LOGIC; ENET1_GMII_RX_CLK : in STD_LOGIC; ENET1_GMII_RX_DV : in STD_LOGIC; ENET1_GMII_RX_ER : in STD_LOGIC; ENET1_GMII_TX_CLK : in STD_LOGIC; ENET1_MDIO_I : in STD_LOGIC; ENET1_EXT_INTIN : in STD_LOGIC; ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; I2C1_SDA_I : in STD_LOGIC; I2C1_SDA_O : out STD_LOGIC; I2C1_SDA_T : out STD_LOGIC; I2C1_SCL_I : in STD_LOGIC; I2C1_SCL_O : out STD_LOGIC; I2C1_SCL_T : out STD_LOGIC; PJTAG_TCK : in STD_LOGIC; PJTAG_TMS : in STD_LOGIC; PJTAG_TDI : in STD_LOGIC; PJTAG_TDO : out STD_LOGIC; SDIO0_CLK : out STD_LOGIC; SDIO0_CLK_FB : in STD_LOGIC; SDIO0_CMD_O : out STD_LOGIC; SDIO0_CMD_I : in STD_LOGIC; SDIO0_CMD_T : out STD_LOGIC; SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO0_LED : out STD_LOGIC; SDIO0_CDN : in STD_LOGIC; SDIO0_WP : in STD_LOGIC; SDIO0_BUSPOW : out STD_LOGIC; SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SDIO1_CLK : out STD_LOGIC; SDIO1_CLK_FB : in STD_LOGIC; SDIO1_CMD_O : out STD_LOGIC; SDIO1_CMD_I : in STD_LOGIC; SDIO1_CMD_T : out STD_LOGIC; SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); SDIO1_LED : out STD_LOGIC; SDIO1_CDN : in STD_LOGIC; SDIO1_WP : in STD_LOGIC; SDIO1_BUSPOW : out STD_LOGIC; SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); SPI0_SCLK_I : in STD_LOGIC; SPI0_SCLK_O : out STD_LOGIC; SPI0_SCLK_T : out STD_LOGIC; SPI0_MOSI_I : in STD_LOGIC; SPI0_MOSI_O : out STD_LOGIC; SPI0_MOSI_T : out STD_LOGIC; SPI0_MISO_I : in STD_LOGIC; SPI0_MISO_O : out STD_LOGIC; SPI0_MISO_T : out STD_LOGIC; SPI0_SS_I : in STD_LOGIC; SPI0_SS_O : out STD_LOGIC; SPI0_SS1_O : out STD_LOGIC; SPI0_SS2_O : out STD_LOGIC; SPI0_SS_T : out STD_LOGIC; SPI1_SCLK_I : in STD_LOGIC; SPI1_SCLK_O : out STD_LOGIC; SPI1_SCLK_T : out STD_LOGIC; SPI1_MOSI_I : in STD_LOGIC; SPI1_MOSI_O : out STD_LOGIC; SPI1_MOSI_T : out STD_LOGIC; SPI1_MISO_I : in STD_LOGIC; SPI1_MISO_O : out STD_LOGIC; SPI1_MISO_T : out STD_LOGIC; SPI1_SS_I : in STD_LOGIC; SPI1_SS_O : out STD_LOGIC; SPI1_SS1_O : out STD_LOGIC; SPI1_SS2_O : out STD_LOGIC; SPI1_SS_T : out STD_LOGIC; UART0_DTRN : out STD_LOGIC; UART0_RTSN : out STD_LOGIC; UART0_TX : out STD_LOGIC; UART0_CTSN : in STD_LOGIC; UART0_DCDN : in STD_LOGIC; UART0_DSRN : in STD_LOGIC; UART0_RIN : in STD_LOGIC; UART0_RX : in STD_LOGIC; UART1_DTRN : out STD_LOGIC; UART1_RTSN : out STD_LOGIC; UART1_TX : out STD_LOGIC; UART1_CTSN : in STD_LOGIC; UART1_DCDN : in STD_LOGIC; UART1_DSRN : in STD_LOGIC; UART1_RIN : in STD_LOGIC; UART1_RX : in STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; TTC0_CLK0_IN : in STD_LOGIC; TTC0_CLK1_IN : in STD_LOGIC; TTC0_CLK2_IN : in STD_LOGIC; TTC1_WAVE0_OUT : out STD_LOGIC; TTC1_WAVE1_OUT : out STD_LOGIC; TTC1_WAVE2_OUT : out STD_LOGIC; TTC1_CLK0_IN : in STD_LOGIC; TTC1_CLK1_IN : in STD_LOGIC; TTC1_CLK2_IN : in STD_LOGIC; WDT_CLK_IN : in STD_LOGIC; WDT_RST_OUT : out STD_LOGIC; TRACE_CLK : in STD_LOGIC; TRACE_CTL : out STD_LOGIC; TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); TRACE_CLK_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB1_VBUS_PWRSELECT : out STD_LOGIC; USB1_VBUS_PWRFAULT : in STD_LOGIC; SRAM_INTIN : in STD_LOGIC; M_AXI_GP0_ARESETN : out STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARESETN : out STD_LOGIC; M_AXI_GP1_ARVALID : out STD_LOGIC; M_AXI_GP1_AWVALID : out STD_LOGIC; M_AXI_GP1_BREADY : out STD_LOGIC; M_AXI_GP1_RREADY : out STD_LOGIC; M_AXI_GP1_WLAST : out STD_LOGIC; M_AXI_GP1_WVALID : out STD_LOGIC; M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP1_ACLK : in STD_LOGIC; M_AXI_GP1_ARREADY : in STD_LOGIC; M_AXI_GP1_AWREADY : in STD_LOGIC; M_AXI_GP1_BVALID : in STD_LOGIC; M_AXI_GP1_RLAST : in STD_LOGIC; M_AXI_GP1_RVALID : in STD_LOGIC; M_AXI_GP1_WREADY : in STD_LOGIC; M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARESETN : out STD_LOGIC; S_AXI_GP0_ARREADY : out STD_LOGIC; S_AXI_GP0_AWREADY : out STD_LOGIC; S_AXI_GP0_BVALID : out STD_LOGIC; S_AXI_GP0_RLAST : out STD_LOGIC; S_AXI_GP0_RVALID : out STD_LOGIC; S_AXI_GP0_WREADY : out STD_LOGIC; S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_ACLK : in STD_LOGIC; S_AXI_GP0_ARVALID : in STD_LOGIC; S_AXI_GP0_AWVALID : in STD_LOGIC; S_AXI_GP0_BREADY : in STD_LOGIC; S_AXI_GP0_RREADY : in STD_LOGIC; S_AXI_GP0_WLAST : in STD_LOGIC; S_AXI_GP0_WVALID : in STD_LOGIC; S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ARESETN : out STD_LOGIC; S_AXI_GP1_ARREADY : out STD_LOGIC; S_AXI_GP1_AWREADY : out STD_LOGIC; S_AXI_GP1_BVALID : out STD_LOGIC; S_AXI_GP1_RLAST : out STD_LOGIC; S_AXI_GP1_RVALID : out STD_LOGIC; S_AXI_GP1_WREADY : out STD_LOGIC; S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_ACLK : in STD_LOGIC; S_AXI_GP1_ARVALID : in STD_LOGIC; S_AXI_GP1_AWVALID : in STD_LOGIC; S_AXI_GP1_BREADY : in STD_LOGIC; S_AXI_GP1_RREADY : in STD_LOGIC; S_AXI_GP1_WLAST : in STD_LOGIC; S_AXI_GP1_WVALID : in STD_LOGIC; S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_ACP_ARESETN : out STD_LOGIC; S_AXI_ACP_ARREADY : out STD_LOGIC; S_AXI_ACP_AWREADY : out STD_LOGIC; S_AXI_ACP_BVALID : out STD_LOGIC; S_AXI_ACP_RLAST : out STD_LOGIC; S_AXI_ACP_RVALID : out STD_LOGIC; S_AXI_ACP_WREADY : out STD_LOGIC; S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_ACLK : in STD_LOGIC; S_AXI_ACP_ARVALID : in STD_LOGIC; S_AXI_ACP_AWVALID : in STD_LOGIC; S_AXI_ACP_BREADY : in STD_LOGIC; S_AXI_ACP_RREADY : in STD_LOGIC; S_AXI_ACP_WLAST : in STD_LOGIC; S_AXI_ACP_WVALID : in STD_LOGIC; S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_ARESETN : out STD_LOGIC; S_AXI_HP0_ARREADY : out STD_LOGIC; S_AXI_HP0_AWREADY : out STD_LOGIC; S_AXI_HP0_BVALID : out STD_LOGIC; S_AXI_HP0_RLAST : out STD_LOGIC; S_AXI_HP0_RVALID : out STD_LOGIC; S_AXI_HP0_WREADY : out STD_LOGIC; S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_ACLK : in STD_LOGIC; S_AXI_HP0_ARVALID : in STD_LOGIC; S_AXI_HP0_AWVALID : in STD_LOGIC; S_AXI_HP0_BREADY : in STD_LOGIC; S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_RREADY : in STD_LOGIC; S_AXI_HP0_WLAST : in STD_LOGIC; S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP0_WVALID : in STD_LOGIC; S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_ARESETN : out STD_LOGIC; S_AXI_HP1_ARREADY : out STD_LOGIC; S_AXI_HP1_AWREADY : out STD_LOGIC; S_AXI_HP1_BVALID : out STD_LOGIC; S_AXI_HP1_RLAST : out STD_LOGIC; S_AXI_HP1_RVALID : out STD_LOGIC; S_AXI_HP1_WREADY : out STD_LOGIC; S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_ACLK : in STD_LOGIC; S_AXI_HP1_ARVALID : in STD_LOGIC; S_AXI_HP1_AWVALID : in STD_LOGIC; S_AXI_HP1_BREADY : in STD_LOGIC; S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_RREADY : in STD_LOGIC; S_AXI_HP1_WLAST : in STD_LOGIC; S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP1_WVALID : in STD_LOGIC; S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_ARESETN : out STD_LOGIC; S_AXI_HP2_ARREADY : out STD_LOGIC; S_AXI_HP2_AWREADY : out STD_LOGIC; S_AXI_HP2_BVALID : out STD_LOGIC; S_AXI_HP2_RLAST : out STD_LOGIC; S_AXI_HP2_RVALID : out STD_LOGIC; S_AXI_HP2_WREADY : out STD_LOGIC; S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_ACLK : in STD_LOGIC; S_AXI_HP2_ARVALID : in STD_LOGIC; S_AXI_HP2_AWVALID : in STD_LOGIC; S_AXI_HP2_BREADY : in STD_LOGIC; S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_RREADY : in STD_LOGIC; S_AXI_HP2_WLAST : in STD_LOGIC; S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP2_WVALID : in STD_LOGIC; S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_ARESETN : out STD_LOGIC; S_AXI_HP3_ARREADY : out STD_LOGIC; S_AXI_HP3_AWREADY : out STD_LOGIC; S_AXI_HP3_BVALID : out STD_LOGIC; S_AXI_HP3_RLAST : out STD_LOGIC; S_AXI_HP3_RVALID : out STD_LOGIC; S_AXI_HP3_WREADY : out STD_LOGIC; S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_ACLK : in STD_LOGIC; S_AXI_HP3_ARVALID : in STD_LOGIC; S_AXI_HP3_AWVALID : in STD_LOGIC; S_AXI_HP3_BREADY : in STD_LOGIC; S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_RREADY : in STD_LOGIC; S_AXI_HP3_WLAST : in STD_LOGIC; S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; S_AXI_HP3_WVALID : in STD_LOGIC; S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); IRQ_P2F_DMAC_ABORT : out STD_LOGIC; IRQ_P2F_DMAC0 : out STD_LOGIC; IRQ_P2F_DMAC1 : out STD_LOGIC; IRQ_P2F_DMAC2 : out STD_LOGIC; IRQ_P2F_DMAC3 : out STD_LOGIC; IRQ_P2F_DMAC4 : out STD_LOGIC; IRQ_P2F_DMAC5 : out STD_LOGIC; IRQ_P2F_DMAC6 : out STD_LOGIC; IRQ_P2F_DMAC7 : out STD_LOGIC; IRQ_P2F_SMC : out STD_LOGIC; IRQ_P2F_QSPI : out STD_LOGIC; IRQ_P2F_CTI : out STD_LOGIC; IRQ_P2F_GPIO : out STD_LOGIC; IRQ_P2F_USB0 : out STD_LOGIC; IRQ_P2F_ENET0 : out STD_LOGIC; IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; IRQ_P2F_SDIO0 : out STD_LOGIC; IRQ_P2F_I2C0 : out STD_LOGIC; IRQ_P2F_SPI0 : out STD_LOGIC; IRQ_P2F_UART0 : out STD_LOGIC; IRQ_P2F_CAN0 : out STD_LOGIC; IRQ_P2F_USB1 : out STD_LOGIC; IRQ_P2F_ENET1 : out STD_LOGIC; IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; IRQ_P2F_SDIO1 : out STD_LOGIC; IRQ_P2F_I2C1 : out STD_LOGIC; IRQ_P2F_SPI1 : out STD_LOGIC; IRQ_P2F_UART1 : out STD_LOGIC; IRQ_P2F_CAN1 : out STD_LOGIC; IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 ); Core0_nFIQ : in STD_LOGIC; Core0_nIRQ : in STD_LOGIC; Core1_nFIQ : in STD_LOGIC; Core1_nIRQ : in STD_LOGIC; DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA0_DAVALID : out STD_LOGIC; DMA0_DRREADY : out STD_LOGIC; DMA0_RSTN : out STD_LOGIC; DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DAVALID : out STD_LOGIC; DMA1_DRREADY : out STD_LOGIC; DMA1_RSTN : out STD_LOGIC; DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DAVALID : out STD_LOGIC; DMA2_DRREADY : out STD_LOGIC; DMA2_RSTN : out STD_LOGIC; DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DAVALID : out STD_LOGIC; DMA3_DRREADY : out STD_LOGIC; DMA3_RSTN : out STD_LOGIC; DMA0_ACLK : in STD_LOGIC; DMA0_DAREADY : in STD_LOGIC; DMA0_DRLAST : in STD_LOGIC; DMA0_DRVALID : in STD_LOGIC; DMA1_ACLK : in STD_LOGIC; DMA1_DAREADY : in STD_LOGIC; DMA1_DRLAST : in STD_LOGIC; DMA1_DRVALID : in STD_LOGIC; DMA2_ACLK : in STD_LOGIC; DMA2_DAREADY : in STD_LOGIC; DMA2_DRLAST : in STD_LOGIC; DMA2_DRVALID : in STD_LOGIC; DMA3_ACLK : in STD_LOGIC; DMA3_DAREADY : in STD_LOGIC; DMA3_DRLAST : in STD_LOGIC; DMA3_DRVALID : in STD_LOGIC; DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); FCLK_CLK3 : out STD_LOGIC; FCLK_CLK2 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_CLK0 : out STD_LOGIC; FCLK_CLKTRIG3_N : in STD_LOGIC; FCLK_CLKTRIG2_N : in STD_LOGIC; FCLK_CLKTRIG1_N : in STD_LOGIC; FCLK_CLKTRIG0_N : in STD_LOGIC; FCLK_RESET3_N : out STD_LOGIC; FCLK_RESET2_N : out STD_LOGIC; FCLK_RESET1_N : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMD_TRACEIN_VALID : in STD_LOGIC; FTMD_TRACEIN_CLK : in STD_LOGIC; FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); FTMT_F2P_TRIG_0 : in STD_LOGIC; FTMT_F2P_TRIGACK_0 : out STD_LOGIC; FTMT_F2P_TRIG_1 : in STD_LOGIC; FTMT_F2P_TRIGACK_1 : out STD_LOGIC; FTMT_F2P_TRIG_2 : in STD_LOGIC; FTMT_F2P_TRIGACK_2 : out STD_LOGIC; FTMT_F2P_TRIG_3 : in STD_LOGIC; FTMT_F2P_TRIGACK_3 : out STD_LOGIC; FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); FTMT_P2F_TRIGACK_0 : in STD_LOGIC; FTMT_P2F_TRIG_0 : out STD_LOGIC; FTMT_P2F_TRIGACK_1 : in STD_LOGIC; FTMT_P2F_TRIG_1 : out STD_LOGIC; FTMT_P2F_TRIGACK_2 : in STD_LOGIC; FTMT_P2F_TRIG_2 : out STD_LOGIC; FTMT_P2F_TRIGACK_3 : in STD_LOGIC; FTMT_P2F_TRIG_3 : out STD_LOGIC; FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); FPGA_IDLE_N : in STD_LOGIC; EVENT_EVENTO : out STD_LOGIC; EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); EVENT_EVENTI : in STD_LOGIC; DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zynq_design_1_processing_system7_0_2.hwdef"; attribute POWER : string; attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal ENET0_MDIO_T_n : STD_LOGIC; signal ENET1_MDIO_T_n : STD_LOGIC; signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 ); signal I2C0_SCL_T_n : STD_LOGIC; signal I2C0_SDA_T_n : STD_LOGIC; signal I2C1_SCL_T_n : STD_LOGIC; signal I2C1_SDA_T_n : STD_LOGIC; signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal SDIO0_CMD_T_n : STD_LOGIC; signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SDIO1_CMD_T_n : STD_LOGIC; signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal SPI0_MISO_T_n : STD_LOGIC; signal SPI0_MOSI_T_n : STD_LOGIC; signal SPI0_SCLK_T_n : STD_LOGIC; signal SPI0_SS_T_n : STD_LOGIC; signal SPI1_MISO_T_n : STD_LOGIC; signal SPI1_MOSI_T_n : STD_LOGIC; signal SPI1_SCLK_T_n : STD_LOGIC; signal SPI1_SS_T_n : STD_LOGIC; signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true"; signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true"; signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true"; signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true"; signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true"; signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true"; signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true"; signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC; attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true"; signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true"; signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true"; signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true"; signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true"; signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true"; signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true"; signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true"; signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true"; signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); signal buffered_DDR_CAS_n : STD_LOGIC; signal buffered_DDR_CKE : STD_LOGIC; signal buffered_DDR_CS_n : STD_LOGIC; signal buffered_DDR_Clk : STD_LOGIC; signal buffered_DDR_Clk_n : STD_LOGIC; signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); signal buffered_DDR_DRSTB : STD_LOGIC; signal buffered_DDR_ODT : STD_LOGIC; signal buffered_DDR_RAS_n : STD_LOGIC; signal buffered_DDR_VRN : STD_LOGIC; signal buffered_DDR_VRP : STD_LOGIC; signal buffered_DDR_WEB : STD_LOGIC; signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); signal buffered_PS_CLK : STD_LOGIC; signal buffered_PS_PORB : STD_LOGIC; signal buffered_PS_SRSTB : STD_LOGIC; signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); attribute BOX_TYPE : string; attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; begin ENET0_GMII_TXD(7) <= \<const0>\; ENET0_GMII_TXD(6) <= \<const0>\; ENET0_GMII_TXD(5) <= \<const0>\; ENET0_GMII_TXD(4) <= \<const0>\; ENET0_GMII_TXD(3) <= \<const0>\; ENET0_GMII_TXD(2) <= \<const0>\; ENET0_GMII_TXD(1) <= \<const0>\; ENET0_GMII_TXD(0) <= \<const0>\; ENET0_GMII_TX_EN <= \<const0>\; ENET0_GMII_TX_ER <= \<const0>\; ENET1_GMII_TXD(7) <= \<const0>\; ENET1_GMII_TXD(6) <= \<const0>\; ENET1_GMII_TXD(5) <= \<const0>\; ENET1_GMII_TXD(4) <= \<const0>\; ENET1_GMII_TXD(3) <= \<const0>\; ENET1_GMII_TXD(2) <= \<const0>\; ENET1_GMII_TXD(1) <= \<const0>\; ENET1_GMII_TXD(0) <= \<const0>\; ENET1_GMII_TX_EN <= \<const0>\; ENET1_GMII_TX_ER <= \<const0>\; M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); M_AXI_GP0_ARCACHE(1) <= \<const1>\; M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); M_AXI_GP0_ARSIZE(2) <= \<const0>\; M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); M_AXI_GP0_AWCACHE(1) <= \<const1>\; M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); M_AXI_GP0_AWSIZE(2) <= \<const0>\; M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2); M_AXI_GP1_ARCACHE(1) <= \<const1>\; M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0); M_AXI_GP1_ARSIZE(2) <= \<const0>\; M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0); M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2); M_AXI_GP1_AWCACHE(1) <= \<const1>\; M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0); M_AXI_GP1_AWSIZE(2) <= \<const0>\; M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0); PJTAG_TDO <= \<const0>\; TRACE_CLK_OUT <= \<const0>\; TRACE_CTL <= \TRACE_CTL_PIPE[0]\; TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0); DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CAS_n, PAD => DDR_CAS_n ); DDR_CKE_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CKE, PAD => DDR_CKE ); DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_CS_n, PAD => DDR_CS_n ); DDR_Clk_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk, PAD => DDR_Clk ); DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Clk_n, PAD => DDR_Clk_n ); DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DRSTB, PAD => DDR_DRSTB ); DDR_ODT_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_ODT, PAD => DDR_ODT ); DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_RAS_n, PAD => DDR_RAS_n ); DDR_VRN_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRN, PAD => DDR_VRN ); DDR_VRP_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_VRP, PAD => DDR_VRP ); DDR_WEB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_WEB, PAD => DDR_WEB ); ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET0_MDIO_T_n, O => ENET0_MDIO_T ); ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ENET1_MDIO_T_n, O => ENET1_MDIO_T ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(0), O => GPIO_T(0) ); \GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(10), O => GPIO_T(10) ); \GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(11), O => GPIO_T(11) ); \GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(12), O => GPIO_T(12) ); \GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(13), O => GPIO_T(13) ); \GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(14), O => GPIO_T(14) ); \GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(15), O => GPIO_T(15) ); \GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(16), O => GPIO_T(16) ); \GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(17), O => GPIO_T(17) ); \GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(18), O => GPIO_T(18) ); \GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(19), O => GPIO_T(19) ); \GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(1), O => GPIO_T(1) ); \GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(20), O => GPIO_T(20) ); \GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(21), O => GPIO_T(21) ); \GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(22), O => GPIO_T(22) ); \GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(23), O => GPIO_T(23) ); \GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(24), O => GPIO_T(24) ); \GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(25), O => GPIO_T(25) ); \GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(26), O => GPIO_T(26) ); \GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(27), O => GPIO_T(27) ); \GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(28), O => GPIO_T(28) ); \GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(29), O => GPIO_T(29) ); \GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(2), O => GPIO_T(2) ); \GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(30), O => GPIO_T(30) ); \GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(31), O => GPIO_T(31) ); \GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(32), O => GPIO_T(32) ); \GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(33), O => GPIO_T(33) ); \GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(34), O => GPIO_T(34) ); \GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(35), O => GPIO_T(35) ); \GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(36), O => GPIO_T(36) ); \GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(37), O => GPIO_T(37) ); \GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(38), O => GPIO_T(38) ); \GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(39), O => GPIO_T(39) ); \GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(3), O => GPIO_T(3) ); \GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(40), O => GPIO_T(40) ); \GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(41), O => GPIO_T(41) ); \GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(42), O => GPIO_T(42) ); \GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(43), O => GPIO_T(43) ); \GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(44), O => GPIO_T(44) ); \GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(45), O => GPIO_T(45) ); \GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(46), O => GPIO_T(46) ); \GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(47), O => GPIO_T(47) ); \GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(48), O => GPIO_T(48) ); \GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(49), O => GPIO_T(49) ); \GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(4), O => GPIO_T(4) ); \GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(50), O => GPIO_T(50) ); \GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(51), O => GPIO_T(51) ); \GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(52), O => GPIO_T(52) ); \GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(53), O => GPIO_T(53) ); \GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(54), O => GPIO_T(54) ); \GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(55), O => GPIO_T(55) ); \GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(56), O => GPIO_T(56) ); \GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(57), O => GPIO_T(57) ); \GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(58), O => GPIO_T(58) ); \GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(59), O => GPIO_T(59) ); \GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(5), O => GPIO_T(5) ); \GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(60), O => GPIO_T(60) ); \GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(61), O => GPIO_T(61) ); \GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(62), O => GPIO_T(62) ); \GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(63), O => GPIO_T(63) ); \GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(6), O => GPIO_T(6) ); \GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(7), O => GPIO_T(7) ); \GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(8), O => GPIO_T(8) ); \GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gpio_out_t_n(9), O => GPIO_T(9) ); I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SCL_T_n, O => I2C0_SCL_T ); I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C0_SDA_T_n, O => I2C0_SDA_T ); I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SCL_T_n, O => I2C1_SCL_T ); I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => I2C1_SDA_T_n, O => I2C1_SDA_T ); PS7_i: unisim.vcomponents.PS7 port map ( DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), DDRARB(3 downto 0) => DDR_ARB(3 downto 0), DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), DDRCASB => buffered_DDR_CAS_n, DDRCKE => buffered_DDR_CKE, DDRCKN => buffered_DDR_Clk_n, DDRCKP => buffered_DDR_Clk, DDRCSB => buffered_DDR_CS_n, DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), DDRDRSTB => buffered_DDR_DRSTB, DDRODT => buffered_DDR_ODT, DDRRASB => buffered_DDR_RAS_n, DDRVRN => buffered_DDR_VRN, DDRVRP => buffered_DDR_VRP, DDRWEB => buffered_DDR_WEB, DMA0ACLK => DMA0_ACLK, DMA0DAREADY => DMA0_DAREADY, DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0), DMA0DAVALID => DMA0_DAVALID, DMA0DRLAST => DMA0_DRLAST, DMA0DRREADY => DMA0_DRREADY, DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0), DMA0DRVALID => DMA0_DRVALID, DMA0RSTN => DMA0_RSTN, DMA1ACLK => DMA1_ACLK, DMA1DAREADY => DMA1_DAREADY, DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0), DMA1DAVALID => DMA1_DAVALID, DMA1DRLAST => DMA1_DRLAST, DMA1DRREADY => DMA1_DRREADY, DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0), DMA1DRVALID => DMA1_DRVALID, DMA1RSTN => DMA1_RSTN, DMA2ACLK => DMA2_ACLK, DMA2DAREADY => DMA2_DAREADY, DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0), DMA2DAVALID => DMA2_DAVALID, DMA2DRLAST => DMA2_DRLAST, DMA2DRREADY => DMA2_DRREADY, DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0), DMA2DRVALID => DMA2_DRVALID, DMA2RSTN => DMA2_RSTN, DMA3ACLK => DMA3_ACLK, DMA3DAREADY => DMA3_DAREADY, DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0), DMA3DAVALID => DMA3_DAVALID, DMA3DRLAST => DMA3_DRLAST, DMA3DRREADY => DMA3_DRREADY, DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0), DMA3DRVALID => DMA3_DRVALID, DMA3RSTN => DMA3_RSTN, EMIOCAN0PHYRX => CAN0_PHY_RX, EMIOCAN0PHYTX => CAN0_PHY_TX, EMIOCAN1PHYRX => CAN1_PHY_RX, EMIOCAN1PHYTX => CAN1_PHY_TX, EMIOENET0EXTINTIN => ENET0_EXT_INTIN, EMIOENET0GMIICOL => '0', EMIOENET0GMIICRS => '0', EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK, EMIOENET0GMIIRXD(7 downto 0) => B"00000000", EMIOENET0GMIIRXDV => '0', EMIOENET0GMIIRXER => '0', EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK, EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, EMIOENET0MDIOI => ENET0_MDIO_I, EMIOENET0MDIOMDC => ENET0_MDIO_MDC, EMIOENET0MDIOO => ENET0_MDIO_O, EMIOENET0MDIOTN => ENET0_MDIO_T_n, EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX, EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX, EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX, EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX, EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX, EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX, EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX, EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX, EMIOENET0SOFRX => ENET0_SOF_RX, EMIOENET0SOFTX => ENET0_SOF_TX, EMIOENET1EXTINTIN => ENET1_EXT_INTIN, EMIOENET1GMIICOL => '0', EMIOENET1GMIICRS => '0', EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK, EMIOENET1GMIIRXD(7 downto 0) => B"00000000", EMIOENET1GMIIRXDV => '0', EMIOENET1GMIIRXER => '0', EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK, EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, EMIOENET1MDIOI => ENET1_MDIO_I, EMIOENET1MDIOMDC => ENET1_MDIO_MDC, EMIOENET1MDIOO => ENET1_MDIO_O, EMIOENET1MDIOTN => ENET1_MDIO_T_n, EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX, EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX, EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX, EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX, EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX, EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX, EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX, EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX, EMIOENET1SOFRX => ENET1_SOF_RX, EMIOENET1SOFTX => ENET1_SOF_TX, EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0), EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0), EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0), EMIOI2C0SCLI => I2C0_SCL_I, EMIOI2C0SCLO => I2C0_SCL_O, EMIOI2C0SCLTN => I2C0_SCL_T_n, EMIOI2C0SDAI => I2C0_SDA_I, EMIOI2C0SDAO => I2C0_SDA_O, EMIOI2C0SDATN => I2C0_SDA_T_n, EMIOI2C1SCLI => I2C1_SCL_I, EMIOI2C1SCLO => I2C1_SCL_O, EMIOI2C1SCLTN => I2C1_SCL_T_n, EMIOI2C1SDAI => I2C1_SDA_I, EMIOI2C1SDAO => I2C1_SDA_O, EMIOI2C1SDATN => I2C1_SDA_T_n, EMIOPJTAGTCK => PJTAG_TCK, EMIOPJTAGTDI => PJTAG_TDI, EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, EMIOPJTAGTMS => PJTAG_TMS, EMIOSDIO0BUSPOW => SDIO0_BUSPOW, EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0), EMIOSDIO0CDN => SDIO0_CDN, EMIOSDIO0CLK => SDIO0_CLK, EMIOSDIO0CLKFB => SDIO0_CLK_FB, EMIOSDIO0CMDI => SDIO0_CMD_I, EMIOSDIO0CMDO => SDIO0_CMD_O, EMIOSDIO0CMDTN => SDIO0_CMD_T_n, EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0), EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0), EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0), EMIOSDIO0LED => SDIO0_LED, EMIOSDIO0WP => SDIO0_WP, EMIOSDIO1BUSPOW => SDIO1_BUSPOW, EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0), EMIOSDIO1CDN => SDIO1_CDN, EMIOSDIO1CLK => SDIO1_CLK, EMIOSDIO1CLKFB => SDIO1_CLK_FB, EMIOSDIO1CMDI => SDIO1_CMD_I, EMIOSDIO1CMDO => SDIO1_CMD_O, EMIOSDIO1CMDTN => SDIO1_CMD_T_n, EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0), EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0), EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0), EMIOSDIO1LED => SDIO1_LED, EMIOSDIO1WP => SDIO1_WP, EMIOSPI0MI => SPI0_MISO_I, EMIOSPI0MO => SPI0_MOSI_O, EMIOSPI0MOTN => SPI0_MOSI_T_n, EMIOSPI0SCLKI => SPI0_SCLK_I, EMIOSPI0SCLKO => SPI0_SCLK_O, EMIOSPI0SCLKTN => SPI0_SCLK_T_n, EMIOSPI0SI => SPI0_MOSI_I, EMIOSPI0SO => SPI0_MISO_O, EMIOSPI0SSIN => SPI0_SS_I, EMIOSPI0SSNTN => SPI0_SS_T_n, EMIOSPI0SSON(2) => SPI0_SS2_O, EMIOSPI0SSON(1) => SPI0_SS1_O, EMIOSPI0SSON(0) => SPI0_SS_O, EMIOSPI0STN => SPI0_MISO_T_n, EMIOSPI1MI => SPI1_MISO_I, EMIOSPI1MO => SPI1_MOSI_O, EMIOSPI1MOTN => SPI1_MOSI_T_n, EMIOSPI1SCLKI => SPI1_SCLK_I, EMIOSPI1SCLKO => SPI1_SCLK_O, EMIOSPI1SCLKTN => SPI1_SCLK_T_n, EMIOSPI1SI => SPI1_MOSI_I, EMIOSPI1SO => SPI1_MISO_O, EMIOSPI1SSIN => SPI1_SS_I, EMIOSPI1SSNTN => SPI1_SS_T_n, EMIOSPI1SSON(2) => SPI1_SS2_O, EMIOSPI1SSON(1) => SPI1_SS1_O, EMIOSPI1SSON(0) => SPI1_SS_O, EMIOSPI1STN => SPI1_MISO_T_n, EMIOSRAMINTIN => SRAM_INTIN, EMIOTRACECLK => TRACE_CLK, EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), EMIOTTC0CLKI(2) => TTC0_CLK2_IN, EMIOTTC0CLKI(1) => TTC0_CLK1_IN, EMIOTTC0CLKI(0) => TTC0_CLK0_IN, EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT, EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT, EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT, EMIOTTC1CLKI(2) => TTC1_CLK2_IN, EMIOTTC1CLKI(1) => TTC1_CLK1_IN, EMIOTTC1CLKI(0) => TTC1_CLK0_IN, EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT, EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT, EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT, EMIOUART0CTSN => UART0_CTSN, EMIOUART0DCDN => UART0_DCDN, EMIOUART0DSRN => UART0_DSRN, EMIOUART0DTRN => UART0_DTRN, EMIOUART0RIN => UART0_RIN, EMIOUART0RTSN => UART0_RTSN, EMIOUART0RX => UART0_RX, EMIOUART0TX => UART0_TX, EMIOUART1CTSN => UART1_CTSN, EMIOUART1DCDN => UART1_DCDN, EMIOUART1DSRN => UART1_DSRN, EMIOUART1DTRN => UART1_DTRN, EMIOUART1RIN => UART1_RIN, EMIOUART1RTSN => UART1_RTSN, EMIOUART1RX => UART1_RX, EMIOUART1TX => UART1_TX, EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT, EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT, EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT, EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT, EMIOWDTCLKI => WDT_CLK_IN, EMIOWDTRSTO => WDT_RST_OUT, EVENTEVENTI => EVENT_EVENTI, EVENTEVENTO => EVENT_EVENTO, EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0), EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0), FCLKCLK(3) => FCLK_CLK3, FCLKCLK(2) => FCLK_CLK2, FCLKCLK(1) => FCLK_CLK1, FCLKCLK(0) => FCLK_CLK_unbuffered(0), FCLKCLKTRIGN(3 downto 0) => B"0000", FCLKRESETN(3) => FCLK_RESET3_N, FCLKRESETN(2) => FCLK_RESET2_N, FCLKRESETN(1) => FCLK_RESET1_N, FCLKRESETN(0) => FCLK_RESET0_N, FPGAIDLEN => FPGA_IDLE_N, FTMDTRACEINATID(3 downto 0) => B"0000", FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK, FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000", FTMDTRACEINVALID => '0', FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0), FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3, FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2, FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1, FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0, FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3, FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2, FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1, FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0, FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0), FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3, FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2, FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1, FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0, FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3, FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2, FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1, FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0, IRQF2P(19) => Core1_nFIQ, IRQF2P(18) => Core0_nFIQ, IRQF2P(17) => Core1_nIRQ, IRQF2P(16) => Core0_nIRQ, IRQF2P(15 downto 1) => B"000000000000000", IRQF2P(0) => IRQ_F2P(0), IRQP2F(28) => IRQ_P2F_DMAC_ABORT, IRQP2F(27) => IRQ_P2F_DMAC7, IRQP2F(26) => IRQ_P2F_DMAC6, IRQP2F(25) => IRQ_P2F_DMAC5, IRQP2F(24) => IRQ_P2F_DMAC4, IRQP2F(23) => IRQ_P2F_DMAC3, IRQP2F(22) => IRQ_P2F_DMAC2, IRQP2F(21) => IRQ_P2F_DMAC1, IRQP2F(20) => IRQ_P2F_DMAC0, IRQP2F(19) => IRQ_P2F_SMC, IRQP2F(18) => IRQ_P2F_QSPI, IRQP2F(17) => IRQ_P2F_CTI, IRQP2F(16) => IRQ_P2F_GPIO, IRQP2F(15) => IRQ_P2F_USB0, IRQP2F(14) => IRQ_P2F_ENET0, IRQP2F(13) => IRQ_P2F_ENET_WAKE0, IRQP2F(12) => IRQ_P2F_SDIO0, IRQP2F(11) => IRQ_P2F_I2C0, IRQP2F(10) => IRQ_P2F_SPI0, IRQP2F(9) => IRQ_P2F_UART0, IRQP2F(8) => IRQ_P2F_CAN0, IRQP2F(7) => IRQ_P2F_USB1, IRQP2F(6) => IRQ_P2F_ENET1, IRQP2F(5) => IRQ_P2F_ENET_WAKE1, IRQP2F(4) => IRQ_P2F_SDIO1, IRQP2F(3) => IRQ_P2F_I2C1, IRQP2F(2) => IRQ_P2F_SPI1, IRQP2F(1) => IRQ_P2F_UART1, IRQP2F(0) => IRQ_P2F_CAN1, MAXIGP0ACLK => M_AXI_GP0_ACLK, MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1), MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0), MAXIGP0ARESETN => M_AXI_GP0_ARESETN, MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), MAXIGP0ARREADY => M_AXI_GP0_ARREADY, MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), MAXIGP0ARVALID => M_AXI_GP0_ARVALID, MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1), MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0), MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), MAXIGP0AWREADY => M_AXI_GP0_AWREADY, MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), MAXIGP0AWVALID => M_AXI_GP0_AWVALID, MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), MAXIGP0BREADY => M_AXI_GP0_BREADY, MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), MAXIGP0BVALID => M_AXI_GP0_BVALID, MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), MAXIGP0RLAST => M_AXI_GP0_RLAST, MAXIGP0RREADY => M_AXI_GP0_RREADY, MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), MAXIGP0RVALID => M_AXI_GP0_RVALID, MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), MAXIGP0WLAST => M_AXI_GP0_WLAST, MAXIGP0WREADY => M_AXI_GP0_WREADY, MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), MAXIGP0WVALID => M_AXI_GP0_WVALID, MAXIGP1ACLK => M_AXI_GP1_ACLK, MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2), MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1), MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0), MAXIGP1ARESETN => M_AXI_GP1_ARESETN, MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), MAXIGP1ARREADY => M_AXI_GP1_ARREADY, MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0), MAXIGP1ARVALID => M_AXI_GP1_ARVALID, MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2), MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1), MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0), MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), MAXIGP1AWREADY => M_AXI_GP1_AWREADY, MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0), MAXIGP1AWVALID => M_AXI_GP1_AWVALID, MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), MAXIGP1BREADY => M_AXI_GP1_BREADY, MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), MAXIGP1BVALID => M_AXI_GP1_BVALID, MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), MAXIGP1RLAST => M_AXI_GP1_RLAST, MAXIGP1RREADY => M_AXI_GP1_RREADY, MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), MAXIGP1RVALID => M_AXI_GP1_RVALID, MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), MAXIGP1WLAST => M_AXI_GP1_WLAST, MAXIGP1WREADY => M_AXI_GP1_WREADY, MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), MAXIGP1WVALID => M_AXI_GP1_WVALID, MIO(53 downto 0) => buffered_MIO(53 downto 0), PSCLK => buffered_PS_CLK, PSPORB => buffered_PS_PORB, PSSRSTB => buffered_PS_SRSTB, SAXIACPACLK => S_AXI_ACP_ACLK, SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0), SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0), SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0), SAXIACPARESETN => S_AXI_ACP_ARESETN, SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0), SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0), SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0), SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0), SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0), SAXIACPARREADY => S_AXI_ACP_ARREADY, SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0), SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0), SAXIACPARVALID => S_AXI_ACP_ARVALID, SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0), SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0), SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0), SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0), SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0), SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0), SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0), SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0), SAXIACPAWREADY => S_AXI_ACP_AWREADY, SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0), SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0), SAXIACPAWVALID => S_AXI_ACP_AWVALID, SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0), SAXIACPBREADY => S_AXI_ACP_BREADY, SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0), SAXIACPBVALID => S_AXI_ACP_BVALID, SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0), SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0), SAXIACPRLAST => S_AXI_ACP_RLAST, SAXIACPRREADY => S_AXI_ACP_RREADY, SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0), SAXIACPRVALID => S_AXI_ACP_RVALID, SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0), SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0), SAXIACPWLAST => S_AXI_ACP_WLAST, SAXIACPWREADY => S_AXI_ACP_WREADY, SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0), SAXIACPWVALID => S_AXI_ACP_WVALID, SAXIGP0ACLK => S_AXI_GP0_ACLK, SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0), SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0), SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0), SAXIGP0ARESETN => S_AXI_GP0_ARESETN, SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0), SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0), SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0), SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0), SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0), SAXIGP0ARREADY => S_AXI_GP0_ARREADY, SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0), SAXIGP0ARVALID => S_AXI_GP0_ARVALID, SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0), SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0), SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0), SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0), SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0), SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0), SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0), SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0), SAXIGP0AWREADY => S_AXI_GP0_AWREADY, SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0), SAXIGP0AWVALID => S_AXI_GP0_AWVALID, SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0), SAXIGP0BREADY => S_AXI_GP0_BREADY, SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0), SAXIGP0BVALID => S_AXI_GP0_BVALID, SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0), SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0), SAXIGP0RLAST => S_AXI_GP0_RLAST, SAXIGP0RREADY => S_AXI_GP0_RREADY, SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0), SAXIGP0RVALID => S_AXI_GP0_RVALID, SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0), SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0), SAXIGP0WLAST => S_AXI_GP0_WLAST, SAXIGP0WREADY => S_AXI_GP0_WREADY, SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0), SAXIGP0WVALID => S_AXI_GP0_WVALID, SAXIGP1ACLK => S_AXI_GP1_ACLK, SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0), SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0), SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0), SAXIGP1ARESETN => S_AXI_GP1_ARESETN, SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0), SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0), SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0), SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0), SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0), SAXIGP1ARREADY => S_AXI_GP1_ARREADY, SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0), SAXIGP1ARVALID => S_AXI_GP1_ARVALID, SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0), SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0), SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0), SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0), SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0), SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0), SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0), SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0), SAXIGP1AWREADY => S_AXI_GP1_AWREADY, SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0), SAXIGP1AWVALID => S_AXI_GP1_AWVALID, SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0), SAXIGP1BREADY => S_AXI_GP1_BREADY, SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0), SAXIGP1BVALID => S_AXI_GP1_BVALID, SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0), SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0), SAXIGP1RLAST => S_AXI_GP1_RLAST, SAXIGP1RREADY => S_AXI_GP1_RREADY, SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0), SAXIGP1RVALID => S_AXI_GP1_RVALID, SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0), SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0), SAXIGP1WLAST => S_AXI_GP1_WLAST, SAXIGP1WREADY => S_AXI_GP1_WREADY, SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0), SAXIGP1WVALID => S_AXI_GP1_WVALID, SAXIHP0ACLK => S_AXI_HP0_ACLK, SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), SAXIHP0ARESETN => S_AXI_HP0_ARESETN, SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), SAXIHP0ARREADY => S_AXI_HP0_ARREADY, SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0), SAXIHP0ARVALID => S_AXI_HP0_ARVALID, SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), SAXIHP0AWREADY => S_AXI_HP0_AWREADY, SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0), SAXIHP0AWVALID => S_AXI_HP0_AWVALID, SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), SAXIHP0BREADY => S_AXI_HP0_BREADY, SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), SAXIHP0BVALID => S_AXI_HP0_BVALID, SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0), SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN, SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), SAXIHP0RLAST => S_AXI_HP0_RLAST, SAXIHP0RREADY => S_AXI_HP0_RREADY, SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), SAXIHP0RVALID => S_AXI_HP0_RVALID, SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0), SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), SAXIHP0WLAST => S_AXI_HP0_WLAST, SAXIHP0WREADY => S_AXI_HP0_WREADY, SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN, SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0), SAXIHP0WVALID => S_AXI_HP0_WVALID, SAXIHP1ACLK => S_AXI_HP1_ACLK, SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), SAXIHP1ARESETN => S_AXI_HP1_ARESETN, SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), SAXIHP1ARREADY => S_AXI_HP1_ARREADY, SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0), SAXIHP1ARVALID => S_AXI_HP1_ARVALID, SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), SAXIHP1AWREADY => S_AXI_HP1_AWREADY, SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0), SAXIHP1AWVALID => S_AXI_HP1_AWVALID, SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), SAXIHP1BREADY => S_AXI_HP1_BREADY, SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), SAXIHP1BVALID => S_AXI_HP1_BVALID, SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN, SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), SAXIHP1RLAST => S_AXI_HP1_RLAST, SAXIHP1RREADY => S_AXI_HP1_RREADY, SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), SAXIHP1RVALID => S_AXI_HP1_RVALID, SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), SAXIHP1WLAST => S_AXI_HP1_WLAST, SAXIHP1WREADY => S_AXI_HP1_WREADY, SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN, SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), SAXIHP1WVALID => S_AXI_HP1_WVALID, SAXIHP2ACLK => S_AXI_HP2_ACLK, SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0), SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0), SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0), SAXIHP2ARESETN => S_AXI_HP2_ARESETN, SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0), SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0), SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0), SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0), SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0), SAXIHP2ARREADY => S_AXI_HP2_ARREADY, SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0), SAXIHP2ARVALID => S_AXI_HP2_ARVALID, SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0), SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0), SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0), SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0), SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0), SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0), SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0), SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0), SAXIHP2AWREADY => S_AXI_HP2_AWREADY, SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0), SAXIHP2AWVALID => S_AXI_HP2_AWVALID, SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0), SAXIHP2BREADY => S_AXI_HP2_BREADY, SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0), SAXIHP2BVALID => S_AXI_HP2_BVALID, SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0), SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0), SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0), SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN, SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0), SAXIHP2RLAST => S_AXI_HP2_RLAST, SAXIHP2RREADY => S_AXI_HP2_RREADY, SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0), SAXIHP2RVALID => S_AXI_HP2_RVALID, SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0), SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0), SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0), SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0), SAXIHP2WLAST => S_AXI_HP2_WLAST, SAXIHP2WREADY => S_AXI_HP2_WREADY, SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN, SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0), SAXIHP2WVALID => S_AXI_HP2_WVALID, SAXIHP3ACLK => S_AXI_HP3_ACLK, SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0), SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0), SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0), SAXIHP3ARESETN => S_AXI_HP3_ARESETN, SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0), SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0), SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0), SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0), SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0), SAXIHP3ARREADY => S_AXI_HP3_ARREADY, SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0), SAXIHP3ARVALID => S_AXI_HP3_ARVALID, SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0), SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0), SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0), SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0), SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0), SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0), SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0), SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0), SAXIHP3AWREADY => S_AXI_HP3_AWREADY, SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0), SAXIHP3AWVALID => S_AXI_HP3_AWVALID, SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0), SAXIHP3BREADY => S_AXI_HP3_BREADY, SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0), SAXIHP3BVALID => S_AXI_HP3_BVALID, SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0), SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0), SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0), SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN, SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0), SAXIHP3RLAST => S_AXI_HP3_RLAST, SAXIHP3RREADY => S_AXI_HP3_RREADY, SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0), SAXIHP3RVALID => S_AXI_HP3_RVALID, SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0), SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0), SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0), SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0), SAXIHP3WLAST => S_AXI_HP3_WLAST, SAXIHP3WREADY => S_AXI_HP3_WREADY, SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN, SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0), SAXIHP3WVALID => S_AXI_HP3_WVALID ); PS_CLK_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_CLK, PAD => PS_CLK ); PS_PORB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_PORB, PAD => PS_PORB ); PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF port map ( IO => buffered_PS_SRSTB, PAD => PS_SRSTB ); SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_CMD_T_n, O => SDIO0_CMD_T ); \SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(0), O => SDIO0_DATA_T(0) ); \SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(1), O => SDIO0_DATA_T(1) ); \SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(2), O => SDIO0_DATA_T(2) ); \SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO0_DATA_T_n(3), O => SDIO0_DATA_T(3) ); SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_CMD_T_n, O => SDIO1_CMD_T ); \SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(0), O => SDIO1_DATA_T(0) ); \SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(1), O => SDIO1_DATA_T(1) ); \SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(2), O => SDIO1_DATA_T(2) ); \SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SDIO1_DATA_T_n(3), O => SDIO1_DATA_T(3) ); SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MISO_T_n, O => SPI0_MISO_T ); SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_MOSI_T_n, O => SPI0_MOSI_T ); SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SCLK_T_n, O => SPI0_SCLK_T ); SPI0_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI0_SS_T_n, O => SPI0_SS_T ); SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MISO_T_n, O => SPI1_MISO_T ); SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_MOSI_T_n, O => SPI1_MOSI_T ); SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SCLK_T_n, O => SPI1_SCLK_T ); SPI1_SS_T_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => SPI1_SS_T_n, O => SPI1_SS_T ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG port map ( I => FCLK_CLK_unbuffered(0), O => FCLK_CLK0 ); \genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(0), PAD => MIO(0) ); \genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(10), PAD => MIO(10) ); \genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(11), PAD => MIO(11) ); \genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(12), PAD => MIO(12) ); \genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(13), PAD => MIO(13) ); \genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(14), PAD => MIO(14) ); \genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(15), PAD => MIO(15) ); \genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(16), PAD => MIO(16) ); \genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(17), PAD => MIO(17) ); \genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(18), PAD => MIO(18) ); \genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(19), PAD => MIO(19) ); \genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(1), PAD => MIO(1) ); \genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(20), PAD => MIO(20) ); \genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(21), PAD => MIO(21) ); \genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(22), PAD => MIO(22) ); \genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(23), PAD => MIO(23) ); \genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(24), PAD => MIO(24) ); \genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(25), PAD => MIO(25) ); \genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(26), PAD => MIO(26) ); \genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(27), PAD => MIO(27) ); \genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(28), PAD => MIO(28) ); \genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(29), PAD => MIO(29) ); \genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(2), PAD => MIO(2) ); \genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(30), PAD => MIO(30) ); \genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(31), PAD => MIO(31) ); \genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(32), PAD => MIO(32) ); \genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(33), PAD => MIO(33) ); \genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(34), PAD => MIO(34) ); \genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(35), PAD => MIO(35) ); \genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(36), PAD => MIO(36) ); \genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(37), PAD => MIO(37) ); \genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(38), PAD => MIO(38) ); \genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(39), PAD => MIO(39) ); \genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(3), PAD => MIO(3) ); \genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(40), PAD => MIO(40) ); \genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(41), PAD => MIO(41) ); \genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(42), PAD => MIO(42) ); \genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(43), PAD => MIO(43) ); \genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(44), PAD => MIO(44) ); \genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(45), PAD => MIO(45) ); \genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(46), PAD => MIO(46) ); \genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(47), PAD => MIO(47) ); \genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(48), PAD => MIO(48) ); \genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(49), PAD => MIO(49) ); \genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(4), PAD => MIO(4) ); \genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(50), PAD => MIO(50) ); \genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(51), PAD => MIO(51) ); \genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(52), PAD => MIO(52) ); \genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(53), PAD => MIO(53) ); \genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(5), PAD => MIO(5) ); \genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(6), PAD => MIO(6) ); \genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(7), PAD => MIO(7) ); \genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(8), PAD => MIO(8) ); \genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_MIO(9), PAD => MIO(9) ); \genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(0), PAD => DDR_BankAddr(0) ); \genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(1), PAD => DDR_BankAddr(1) ); \genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_BankAddr(2), PAD => DDR_BankAddr(2) ); \genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(0), PAD => DDR_Addr(0) ); \genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(10), PAD => DDR_Addr(10) ); \genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(11), PAD => DDR_Addr(11) ); \genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(12), PAD => DDR_Addr(12) ); \genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(13), PAD => DDR_Addr(13) ); \genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(14), PAD => DDR_Addr(14) ); \genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(1), PAD => DDR_Addr(1) ); \genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(2), PAD => DDR_Addr(2) ); \genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(3), PAD => DDR_Addr(3) ); \genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(4), PAD => DDR_Addr(4) ); \genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(5), PAD => DDR_Addr(5) ); \genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(6), PAD => DDR_Addr(6) ); \genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(7), PAD => DDR_Addr(7) ); \genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(8), PAD => DDR_Addr(8) ); \genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_Addr(9), PAD => DDR_Addr(9) ); \genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(0), PAD => DDR_DM(0) ); \genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(1), PAD => DDR_DM(1) ); \genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(2), PAD => DDR_DM(2) ); \genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DM(3), PAD => DDR_DM(3) ); \genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(0), PAD => DDR_DQ(0) ); \genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(10), PAD => DDR_DQ(10) ); \genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(11), PAD => DDR_DQ(11) ); \genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(12), PAD => DDR_DQ(12) ); \genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(13), PAD => DDR_DQ(13) ); \genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(14), PAD => DDR_DQ(14) ); \genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(15), PAD => DDR_DQ(15) ); \genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(16), PAD => DDR_DQ(16) ); \genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(17), PAD => DDR_DQ(17) ); \genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(18), PAD => DDR_DQ(18) ); \genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(19), PAD => DDR_DQ(19) ); \genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(1), PAD => DDR_DQ(1) ); \genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(20), PAD => DDR_DQ(20) ); \genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(21), PAD => DDR_DQ(21) ); \genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(22), PAD => DDR_DQ(22) ); \genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(23), PAD => DDR_DQ(23) ); \genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(24), PAD => DDR_DQ(24) ); \genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(25), PAD => DDR_DQ(25) ); \genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(26), PAD => DDR_DQ(26) ); \genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(27), PAD => DDR_DQ(27) ); \genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(28), PAD => DDR_DQ(28) ); \genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(29), PAD => DDR_DQ(29) ); \genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(2), PAD => DDR_DQ(2) ); \genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(30), PAD => DDR_DQ(30) ); \genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(31), PAD => DDR_DQ(31) ); \genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(3), PAD => DDR_DQ(3) ); \genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(4), PAD => DDR_DQ(4) ); \genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(5), PAD => DDR_DQ(5) ); \genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(6), PAD => DDR_DQ(6) ); \genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(7), PAD => DDR_DQ(7) ); \genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(8), PAD => DDR_DQ(8) ); \genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQ(9), PAD => DDR_DQ(9) ); \genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(0), PAD => DDR_DQS_n(0) ); \genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(1), PAD => DDR_DQS_n(1) ); \genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(2), PAD => DDR_DQS_n(2) ); \genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS_n(3), PAD => DDR_DQS_n(3) ); \genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(0), PAD => DDR_DQS(0) ); \genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(1), PAD => DDR_DQS(1) ); \genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(2), PAD => DDR_DQS(2) ); \genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF port map ( IO => buffered_DDR_DQS(3), PAD => DDR_DQS(3) ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[0]\ ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(1) ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(1) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[7]\(0) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(1) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[6]\(0) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(1) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[5]\(0) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(1) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[4]\(0) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(1) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[3]\(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[0]\(0) ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(1) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[2]\(0) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(1) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_DATA_PIPE[1]\(0) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[7]\ ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[6]\ ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[5]\ ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[4]\ ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[3]\ ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[2]\ ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => \TRACE_CTL_PIPE[1]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}"; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_DM_WIDTH : integer; attribute C_DM_WIDTH of inst : label is 4; attribute C_DQS_WIDTH : integer; attribute C_DQS_WIDTH of inst : label is 4; attribute C_DQ_WIDTH : integer; attribute C_DQ_WIDTH of inst : label is 32; attribute C_EMIO_GPIO_WIDTH : integer; attribute C_EMIO_GPIO_WIDTH of inst : label is 64; attribute C_EN_EMIO_ENET0 : integer; attribute C_EN_EMIO_ENET0 of inst : label is 0; attribute C_EN_EMIO_ENET1 : integer; attribute C_EN_EMIO_ENET1 of inst : label is 0; attribute C_EN_EMIO_PJTAG : integer; attribute C_EN_EMIO_PJTAG of inst : label is 0; attribute C_EN_EMIO_TRACE : integer; attribute C_EN_EMIO_TRACE of inst : label is 0; attribute C_FCLK_CLK0_BUF : string; attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; attribute C_FCLK_CLK1_BUF : string; attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK2_BUF : string; attribute C_FCLK_CLK2_BUF of inst : label is "FALSE"; attribute C_FCLK_CLK3_BUF : string; attribute C_FCLK_CLK3_BUF of inst : label is "FALSE"; attribute C_GP0_EN_MODIFIABLE_TXN : integer; attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_GP1_EN_MODIFIABLE_TXN : integer; attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1; attribute C_INCLUDE_ACP_TRANS_CHECK : integer; attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; attribute C_INCLUDE_TRACE_BUFFER : integer; attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; attribute C_IRQ_F2P_MODE : string; attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; attribute C_MIO_PRIMITIVE : integer; attribute C_MIO_PRIMITIVE of inst : label is 54; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP0_ID_WIDTH : integer; attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; attribute C_M_AXI_GP1_ID_WIDTH : integer; attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; attribute C_NUM_F2P_INTR_INPUTS : integer; attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1; attribute C_PACKAGE_NAME : string; attribute C_PACKAGE_NAME of inst : label is "clg484"; attribute C_PS7_SI_REV : string; attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; attribute C_S_AXI_ACP_ARUSER_VAL : integer; attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_AWUSER_VAL : integer; attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; attribute C_S_AXI_ACP_ID_WIDTH : integer; attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; attribute C_S_AXI_GP0_ID_WIDTH : integer; attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_GP1_ID_WIDTH : integer; attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP0_DATA_WIDTH : integer; attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP0_ID_WIDTH : integer; attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP1_DATA_WIDTH : integer; attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP1_ID_WIDTH : integer; attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP2_DATA_WIDTH : integer; attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP2_ID_WIDTH : integer; attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; attribute C_S_AXI_HP3_DATA_WIDTH : integer; attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; attribute C_S_AXI_HP3_ID_WIDTH : integer; attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; attribute C_TRACE_BUFFER_FIFO_SIZE : integer; attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; attribute C_TRACE_INTERNAL_WIDTH : integer; attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; attribute C_TRACE_PIPELINE_WIDTH : integer; attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; attribute C_USE_AXI_NONSECURE : integer; attribute C_USE_AXI_NONSECURE of inst : label is 0; attribute C_USE_DEFAULT_ACP_USER_VAL : integer; attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; attribute C_USE_M_AXI_GP0 : integer; attribute C_USE_M_AXI_GP0 of inst : label is 1; attribute C_USE_M_AXI_GP1 : integer; attribute C_USE_M_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_ACP : integer; attribute C_USE_S_AXI_ACP of inst : label is 0; attribute C_USE_S_AXI_GP0 : integer; attribute C_USE_S_AXI_GP0 of inst : label is 0; attribute C_USE_S_AXI_GP1 : integer; attribute C_USE_S_AXI_GP1 of inst : label is 0; attribute C_USE_S_AXI_HP0 : integer; attribute C_USE_S_AXI_HP0 of inst : label is 0; attribute C_USE_S_AXI_HP1 : integer; attribute C_USE_S_AXI_HP1 of inst : label is 0; attribute C_USE_S_AXI_HP2 : integer; attribute C_USE_S_AXI_HP2 of inst : label is 0; attribute C_USE_S_AXI_HP3 : integer; attribute C_USE_S_AXI_HP3 of inst : label is 0; attribute HW_HANDOFF : string; attribute HW_HANDOFF of inst : label is "zynq_design_1_processing_system7_0_2.hwdef"; attribute POWER : string; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 port map ( CAN0_PHY_RX => '0', CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, CAN1_PHY_RX => '0', CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, Core0_nFIQ => '0', Core0_nIRQ => '0', Core1_nFIQ => '0', Core1_nIRQ => '0', DDR_ARB(3 downto 0) => B"0000", DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), DDR_CAS_n => DDR_CAS_n, DDR_CKE => DDR_CKE, DDR_CS_n => DDR_CS_n, DDR_Clk => DDR_Clk, DDR_Clk_n => DDR_Clk_n, DDR_DM(3 downto 0) => DDR_DM(3 downto 0), DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), DDR_DRSTB => DDR_DRSTB, DDR_ODT => DDR_ODT, DDR_RAS_n => DDR_RAS_n, DDR_VRN => DDR_VRN, DDR_VRP => DDR_VRP, DDR_WEB => DDR_WEB, DMA0_ACLK => '0', DMA0_DAREADY => '0', DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, DMA0_DRLAST => '0', DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, DMA0_DRTYPE(1 downto 0) => B"00", DMA0_DRVALID => '0', DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, DMA1_ACLK => '0', DMA1_DAREADY => '0', DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, DMA1_DRLAST => '0', DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, DMA1_DRTYPE(1 downto 0) => B"00", DMA1_DRVALID => '0', DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, DMA2_ACLK => '0', DMA2_DAREADY => '0', DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, DMA2_DRLAST => '0', DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, DMA2_DRTYPE(1 downto 0) => B"00", DMA2_DRVALID => '0', DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, DMA3_ACLK => '0', DMA3_DAREADY => '0', DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, DMA3_DRLAST => '0', DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, DMA3_DRTYPE(1 downto 0) => B"00", DMA3_DRVALID => '0', DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, ENET0_EXT_INTIN => '0', ENET0_GMII_COL => '0', ENET0_GMII_CRS => '0', ENET0_GMII_RXD(7 downto 0) => B"00000000", ENET0_GMII_RX_CLK => '0', ENET0_GMII_RX_DV => '0', ENET0_GMII_RX_ER => '0', ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), ENET0_GMII_TX_CLK => '0', ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, ENET0_MDIO_I => '0', ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED, ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED, ENET1_EXT_INTIN => '0', ENET1_GMII_COL => '0', ENET1_GMII_CRS => '0', ENET1_GMII_RXD(7 downto 0) => B"00000000", ENET1_GMII_RX_CLK => '0', ENET1_GMII_RX_DV => '0', ENET1_GMII_RX_ER => '0', ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), ENET1_GMII_TX_CLK => '0', ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, ENET1_MDIO_I => '0', ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, EVENT_EVENTI => '0', EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), FCLK_CLK0 => FCLK_CLK0, FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, FCLK_CLKTRIG0_N => '0', FCLK_CLKTRIG1_N => '0', FCLK_CLKTRIG2_N => '0', FCLK_CLKTRIG3_N => '0', FCLK_RESET0_N => FCLK_RESET0_N, FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, FPGA_IDLE_N => '0', FTMD_TRACEIN_ATID(3 downto 0) => B"0000", FTMD_TRACEIN_CLK => '0', FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000", FTMD_TRACEIN_VALID => '0', FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000", FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, FTMT_F2P_TRIG_0 => '0', FTMT_F2P_TRIG_1 => '0', FTMT_F2P_TRIG_2 => '0', FTMT_F2P_TRIG_3 => '0', FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), FTMT_P2F_TRIGACK_0 => '0', FTMT_P2F_TRIGACK_1 => '0', FTMT_P2F_TRIGACK_2 => '0', FTMT_P2F_TRIGACK_3 => '0', FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0), GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0), I2C0_SCL_I => '0', I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED, I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED, I2C0_SDA_I => '0', I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED, I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED, I2C1_SCL_I => '0', I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, I2C1_SDA_I => '0', I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, IRQ_F2P(0) => '0', IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, MIO(53 downto 0) => MIO(53 downto 0), M_AXI_GP0_ACLK => M_AXI_GP0_ACLK, M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0), M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY, M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0), M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID, M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0), M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY, M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0), M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID, M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), M_AXI_GP0_BREADY => M_AXI_GP0_BREADY, M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), M_AXI_GP0_BVALID => M_AXI_GP0_BVALID, M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), M_AXI_GP0_RLAST => M_AXI_GP0_RLAST, M_AXI_GP0_RREADY => M_AXI_GP0_RREADY, M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), M_AXI_GP0_RVALID => M_AXI_GP0_RVALID, M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), M_AXI_GP0_WLAST => M_AXI_GP0_WLAST, M_AXI_GP0_WREADY => M_AXI_GP0_WREADY, M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), M_AXI_GP0_WVALID => M_AXI_GP0_WVALID, M_AXI_GP1_ACLK => '0', M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0), M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_ARREADY => '0', M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED, M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0), M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0), M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0), M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0), M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0), M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0), M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0), M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0), M_AXI_GP1_AWREADY => '0', M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0), M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED, M_AXI_GP1_BID(11 downto 0) => B"000000000000", M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED, M_AXI_GP1_BRESP(1 downto 0) => B"00", M_AXI_GP1_BVALID => '0', M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000", M_AXI_GP1_RID(11 downto 0) => B"000000000000", M_AXI_GP1_RLAST => '0', M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED, M_AXI_GP1_RRESP(1 downto 0) => B"00", M_AXI_GP1_RVALID => '0', M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0), M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0), M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED, M_AXI_GP1_WREADY => '0', M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0), M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED, PJTAG_TCK => '0', PJTAG_TDI => '0', PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, PJTAG_TMS => '0', PS_CLK => PS_CLK, PS_PORB => PS_PORB, PS_SRSTB => PS_SRSTB, SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), SDIO0_CDN => '0', SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, SDIO0_CLK_FB => '0', SDIO0_CMD_I => '0', SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, SDIO0_DATA_I(3 downto 0) => B"0000", SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, SDIO0_WP => '0', SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), SDIO1_CDN => '0', SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, SDIO1_CLK_FB => '0', SDIO1_CMD_I => '0', SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, SDIO1_DATA_I(3 downto 0) => B"0000", SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, SDIO1_WP => '0', SPI0_MISO_I => '0', SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, SPI0_MOSI_I => '0', SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, SPI0_SCLK_I => '0', SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, SPI0_SS_I => '0', SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, SPI1_MISO_I => '0', SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, SPI1_MOSI_I => '0', SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, SPI1_SCLK_I => '0', SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, SPI1_SS_I => '0', SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, SRAM_INTIN => '0', S_AXI_ACP_ACLK => '0', S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_ARBURST(1 downto 0) => B"00", S_AXI_ACP_ARCACHE(3 downto 0) => B"0000", S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, S_AXI_ACP_ARID(2 downto 0) => B"000", S_AXI_ACP_ARLEN(3 downto 0) => B"0000", S_AXI_ACP_ARLOCK(1 downto 0) => B"00", S_AXI_ACP_ARPROT(2 downto 0) => B"000", S_AXI_ACP_ARQOS(3 downto 0) => B"0000", S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, S_AXI_ACP_ARSIZE(2 downto 0) => B"000", S_AXI_ACP_ARUSER(4 downto 0) => B"00000", S_AXI_ACP_ARVALID => '0', S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_ACP_AWBURST(1 downto 0) => B"00", S_AXI_ACP_AWCACHE(3 downto 0) => B"0000", S_AXI_ACP_AWID(2 downto 0) => B"000", S_AXI_ACP_AWLEN(3 downto 0) => B"0000", S_AXI_ACP_AWLOCK(1 downto 0) => B"00", S_AXI_ACP_AWPROT(2 downto 0) => B"000", S_AXI_ACP_AWQOS(3 downto 0) => B"0000", S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, S_AXI_ACP_AWSIZE(2 downto 0) => B"000", S_AXI_ACP_AWUSER(4 downto 0) => B"00000", S_AXI_ACP_AWVALID => '0', S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), S_AXI_ACP_BREADY => '0', S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, S_AXI_ACP_RREADY => '0', S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_ACP_WID(2 downto 0) => B"000", S_AXI_ACP_WLAST => '0', S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, S_AXI_ACP_WSTRB(7 downto 0) => B"00000000", S_AXI_ACP_WVALID => '0', S_AXI_GP0_ACLK => '0', S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_ARBURST(1 downto 0) => B"00", S_AXI_GP0_ARCACHE(3 downto 0) => B"0000", S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, S_AXI_GP0_ARID(5 downto 0) => B"000000", S_AXI_GP0_ARLEN(3 downto 0) => B"0000", S_AXI_GP0_ARLOCK(1 downto 0) => B"00", S_AXI_GP0_ARPROT(2 downto 0) => B"000", S_AXI_GP0_ARQOS(3 downto 0) => B"0000", S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, S_AXI_GP0_ARSIZE(2 downto 0) => B"000", S_AXI_GP0_ARVALID => '0', S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_AWBURST(1 downto 0) => B"00", S_AXI_GP0_AWCACHE(3 downto 0) => B"0000", S_AXI_GP0_AWID(5 downto 0) => B"000000", S_AXI_GP0_AWLEN(3 downto 0) => B"0000", S_AXI_GP0_AWLOCK(1 downto 0) => B"00", S_AXI_GP0_AWPROT(2 downto 0) => B"000", S_AXI_GP0_AWQOS(3 downto 0) => B"0000", S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, S_AXI_GP0_AWSIZE(2 downto 0) => B"000", S_AXI_GP0_AWVALID => '0', S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), S_AXI_GP0_BREADY => '0', S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, S_AXI_GP0_RREADY => '0', S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP0_WID(5 downto 0) => B"000000", S_AXI_GP0_WLAST => '0', S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, S_AXI_GP0_WSTRB(3 downto 0) => B"0000", S_AXI_GP0_WVALID => '0', S_AXI_GP1_ACLK => '0', S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_ARBURST(1 downto 0) => B"00", S_AXI_GP1_ARCACHE(3 downto 0) => B"0000", S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, S_AXI_GP1_ARID(5 downto 0) => B"000000", S_AXI_GP1_ARLEN(3 downto 0) => B"0000", S_AXI_GP1_ARLOCK(1 downto 0) => B"00", S_AXI_GP1_ARPROT(2 downto 0) => B"000", S_AXI_GP1_ARQOS(3 downto 0) => B"0000", S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, S_AXI_GP1_ARSIZE(2 downto 0) => B"000", S_AXI_GP1_ARVALID => '0', S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_AWBURST(1 downto 0) => B"00", S_AXI_GP1_AWCACHE(3 downto 0) => B"0000", S_AXI_GP1_AWID(5 downto 0) => B"000000", S_AXI_GP1_AWLEN(3 downto 0) => B"0000", S_AXI_GP1_AWLOCK(1 downto 0) => B"00", S_AXI_GP1_AWPROT(2 downto 0) => B"000", S_AXI_GP1_AWQOS(3 downto 0) => B"0000", S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, S_AXI_GP1_AWSIZE(2 downto 0) => B"000", S_AXI_GP1_AWVALID => '0', S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), S_AXI_GP1_BREADY => '0', S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, S_AXI_GP1_RREADY => '0', S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000", S_AXI_GP1_WID(5 downto 0) => B"000000", S_AXI_GP1_WLAST => '0', S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, S_AXI_GP1_WSTRB(3 downto 0) => B"0000", S_AXI_GP1_WVALID => '0', S_AXI_HP0_ACLK => '0', S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_ARBURST(1 downto 0) => B"00", S_AXI_HP0_ARCACHE(3 downto 0) => B"0000", S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, S_AXI_HP0_ARID(5 downto 0) => B"000000", S_AXI_HP0_ARLEN(3 downto 0) => B"0000", S_AXI_HP0_ARLOCK(1 downto 0) => B"00", S_AXI_HP0_ARPROT(2 downto 0) => B"000", S_AXI_HP0_ARQOS(3 downto 0) => B"0000", S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED, S_AXI_HP0_ARSIZE(2 downto 0) => B"000", S_AXI_HP0_ARVALID => '0', S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP0_AWBURST(1 downto 0) => B"00", S_AXI_HP0_AWCACHE(3 downto 0) => B"0000", S_AXI_HP0_AWID(5 downto 0) => B"000000", S_AXI_HP0_AWLEN(3 downto 0) => B"0000", S_AXI_HP0_AWLOCK(1 downto 0) => B"00", S_AXI_HP0_AWPROT(2 downto 0) => B"000", S_AXI_HP0_AWQOS(3 downto 0) => B"0000", S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED, S_AXI_HP0_AWSIZE(2 downto 0) => B"000", S_AXI_HP0_AWVALID => '0', S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0), S_AXI_HP0_BREADY => '0', S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED, S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP0_RDISSUECAP1_EN => '0', S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0), S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED, S_AXI_HP0_RREADY => '0', S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED, S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP0_WID(5 downto 0) => B"000000", S_AXI_HP0_WLAST => '0', S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED, S_AXI_HP0_WRISSUECAP1_EN => '0', S_AXI_HP0_WSTRB(7 downto 0) => B"00000000", S_AXI_HP0_WVALID => '0', S_AXI_HP1_ACLK => '0', S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_ARBURST(1 downto 0) => B"00", S_AXI_HP1_ARCACHE(3 downto 0) => B"0000", S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, S_AXI_HP1_ARID(5 downto 0) => B"000000", S_AXI_HP1_ARLEN(3 downto 0) => B"0000", S_AXI_HP1_ARLOCK(1 downto 0) => B"00", S_AXI_HP1_ARPROT(2 downto 0) => B"000", S_AXI_HP1_ARQOS(3 downto 0) => B"0000", S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED, S_AXI_HP1_ARSIZE(2 downto 0) => B"000", S_AXI_HP1_ARVALID => '0', S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP1_AWBURST(1 downto 0) => B"00", S_AXI_HP1_AWCACHE(3 downto 0) => B"0000", S_AXI_HP1_AWID(5 downto 0) => B"000000", S_AXI_HP1_AWLEN(3 downto 0) => B"0000", S_AXI_HP1_AWLOCK(1 downto 0) => B"00", S_AXI_HP1_AWPROT(2 downto 0) => B"000", S_AXI_HP1_AWQOS(3 downto 0) => B"0000", S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED, S_AXI_HP1_AWSIZE(2 downto 0) => B"000", S_AXI_HP1_AWVALID => '0', S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0), S_AXI_HP1_BREADY => '0', S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED, S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP1_RDISSUECAP1_EN => '0', S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0), S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED, S_AXI_HP1_RREADY => '0', S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED, S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP1_WID(5 downto 0) => B"000000", S_AXI_HP1_WLAST => '0', S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED, S_AXI_HP1_WRISSUECAP1_EN => '0', S_AXI_HP1_WSTRB(7 downto 0) => B"00000000", S_AXI_HP1_WVALID => '0', S_AXI_HP2_ACLK => '0', S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_ARBURST(1 downto 0) => B"00", S_AXI_HP2_ARCACHE(3 downto 0) => B"0000", S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, S_AXI_HP2_ARID(5 downto 0) => B"000000", S_AXI_HP2_ARLEN(3 downto 0) => B"0000", S_AXI_HP2_ARLOCK(1 downto 0) => B"00", S_AXI_HP2_ARPROT(2 downto 0) => B"000", S_AXI_HP2_ARQOS(3 downto 0) => B"0000", S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, S_AXI_HP2_ARSIZE(2 downto 0) => B"000", S_AXI_HP2_ARVALID => '0', S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP2_AWBURST(1 downto 0) => B"00", S_AXI_HP2_AWCACHE(3 downto 0) => B"0000", S_AXI_HP2_AWID(5 downto 0) => B"000000", S_AXI_HP2_AWLEN(3 downto 0) => B"0000", S_AXI_HP2_AWLOCK(1 downto 0) => B"00", S_AXI_HP2_AWPROT(2 downto 0) => B"000", S_AXI_HP2_AWQOS(3 downto 0) => B"0000", S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, S_AXI_HP2_AWSIZE(2 downto 0) => B"000", S_AXI_HP2_AWVALID => '0', S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), S_AXI_HP2_BREADY => '0', S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP2_RDISSUECAP1_EN => '0', S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, S_AXI_HP2_RREADY => '0', S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP2_WID(5 downto 0) => B"000000", S_AXI_HP2_WLAST => '0', S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, S_AXI_HP2_WRISSUECAP1_EN => '0', S_AXI_HP2_WSTRB(7 downto 0) => B"00000000", S_AXI_HP2_WVALID => '0', S_AXI_HP3_ACLK => '0', S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_ARBURST(1 downto 0) => B"00", S_AXI_HP3_ARCACHE(3 downto 0) => B"0000", S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, S_AXI_HP3_ARID(5 downto 0) => B"000000", S_AXI_HP3_ARLEN(3 downto 0) => B"0000", S_AXI_HP3_ARLOCK(1 downto 0) => B"00", S_AXI_HP3_ARPROT(2 downto 0) => B"000", S_AXI_HP3_ARQOS(3 downto 0) => B"0000", S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, S_AXI_HP3_ARSIZE(2 downto 0) => B"000", S_AXI_HP3_ARVALID => '0', S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000", S_AXI_HP3_AWBURST(1 downto 0) => B"00", S_AXI_HP3_AWCACHE(3 downto 0) => B"0000", S_AXI_HP3_AWID(5 downto 0) => B"000000", S_AXI_HP3_AWLEN(3 downto 0) => B"0000", S_AXI_HP3_AWLOCK(1 downto 0) => B"00", S_AXI_HP3_AWPROT(2 downto 0) => B"000", S_AXI_HP3_AWQOS(3 downto 0) => B"0000", S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, S_AXI_HP3_AWSIZE(2 downto 0) => B"000", S_AXI_HP3_AWVALID => '0', S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), S_AXI_HP3_BREADY => '0', S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), S_AXI_HP3_RDISSUECAP1_EN => '0', S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, S_AXI_HP3_RREADY => '0', S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", S_AXI_HP3_WID(5 downto 0) => B"000000", S_AXI_HP3_WLAST => '0', S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, S_AXI_HP3_WRISSUECAP1_EN => '0', S_AXI_HP3_WSTRB(7 downto 0) => B"00000000", S_AXI_HP3_WVALID => '0', TRACE_CLK => '0', TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), TTC0_CLK0_IN => '0', TTC0_CLK1_IN => '0', TTC0_CLK2_IN => '0', TTC0_WAVE0_OUT => TTC0_WAVE0_OUT, TTC0_WAVE1_OUT => TTC0_WAVE1_OUT, TTC0_WAVE2_OUT => TTC0_WAVE2_OUT, TTC1_CLK0_IN => '0', TTC1_CLK1_IN => '0', TTC1_CLK2_IN => '0', TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, UART0_CTSN => '0', UART0_DCDN => '0', UART0_DSRN => '0', UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, UART0_RIN => '0', UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, UART0_RX => '1', UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, UART1_CTSN => '0', UART1_DCDN => '0', UART1_DSRN => '0', UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, UART1_RIN => '0', UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, UART1_RX => '1', UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT, USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT, USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0), USB1_VBUS_PWRFAULT => '0', USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED, WDT_CLK_IN => '0', WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED ); end STRUCTURE;

-- An 8-bit register entity to make the code smaller and closer to the drawing library IEEE; use IEEE.STD_LOGIC_1164.all; entity reg8bits is port ( rst : in std_logic; ck : in std_logic; ce : in std_logic; di : in std_logic_vector(7 downto 0); do : out std_logic_vector(7 downto 0) ); end entity; -- This is a behaviorial description of a register. However, all -- the synthesis tools will be able to infer a flip-flop with synchronous reset -- and clock enable architecture rtl of reg8bits is begin reg: process(ck) is begin if rising_edge(ck) then if rst = '1' then do <= x"00"; else if ce = '1' then do <= di; end if; end if; end if; end process; end architecture rtl;

entity FIFO is port ( WR_EN_I : in std_logic; DATA_O : out std_logic_vector(31 downto 0); RD_EN_IO : inout std_logic; DATA_O : out std_logic_vector(31 downto 0) ); end entity FIFO; entity FIFO is port ( WR_EN : in std_logic; DATA : out std_logic_vector(31 downto 0); RD_EN : in std_logic; DATA : out std_logic_vector(31 downto 0) ); end entity FIFO;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 05/23/2015 03:41:27 PM -- Design Name: -- Module Name: InstructionDecoder - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity InstructionDecoder is port ( TimingSignals : in BIT_VECTOR(7 downto 0); -- The 8 different timing states Instruction : in BIT_VECTOR(7 downto 0); -- The instruction to execute Flags : in BIT_VECTOR(7 downto 0); -- Content of the FLAGS register - needed for conditional jumps -- ============================================================== -- The various control lines of the CPU which go low/high -- depending on the timing state and the instruction to execute: -- ============================================================== Load_PC : out BIT; Select_PC : out BIT; Load_SRAM: out BIT; Select_SRAM: out BIT; Return_SRAM: out BIT; Load_INC: out BIT; Select_INC: out BIT; Load_INSTR: out BIT; Select_INSTR_To_DataBus: out BIT; Select_INSTR_To_ALU: out BIT; Load_A_From_DataBus: out BIT; Select_A_To_ALU: out BIT; Load_B_From_DataBus: out BIT; Select_B_To_ALU: out BIT; Load_C_From_DataBus: out BIT; Load_InternalA_From_DataBus: out BIT; Select_InternalA_To_DataBus: out BIT; Load_Flags: out BIT; Select_A_To_DataBus: out BIT; Select_B_To_DataBus: out BIT; Select_C_To_DataBus: out BIT; Load_D_From_DataBus: out BIT; Select_D_To_DataBus: out BIT; Load_E_From_DataBus: out BIT; Select_E_To_DataBus: out BIT; Load_F_From_DataBus: out BIT; Select_F_To_DataBus: out BIT; Load_G_From_DataBus: out BIT; Select_G_To_DataBus: out BIT; Load_H_From_DataBus: out BIT; Select_H_To_DataBus: out BIT; load_M_From_AddressBus: out BIT; select_M_To_AddressBus: out BIT; load_XL_From_DataBus: out BIT; load_XH_From_DataBus: out BIT; load_X_From_AddressBus: out BIT; select_XL_To_DataBus: out BIT; select_XH_To_DataBus: out BIT; select_X_To_AddressBus: out BIT; Load_J_From_AddressBus: out BIT; Select_J_To_AddressBus: out BIT; Load_SP_From_AddressBus: out BIT; Select_SP_To_AddressBus: out BIT; Load_BP_From_AddressBus: out BIT; Select_BP_To_AddressBus: out BIT; Load_Y_From_AddressBus: out BIT; Select_Y_To_AddressBus: out BIT; Load_Z_From_AddressBus: out BIT; Select_Z_To_AddressBus: out BIT; Load_Adder16Bit_InputA: out BIT; Select_Adder16Bit_InputA: out BIT; Load_Adder16Bit_InputB: out BIT; Select_Adder16Bit_InputB: out BIT; Load_Adder16Bit_OutputC: out BIT; Select_Adder16Bit_OutputC: out BIT; load_FlagsSaved_From_FlagsRegister: out BIT; load_FlagsSaved_To_FlagsRegister: out BIT; Load_FlagsFromDataBus: out BIT; Select_FlagsToFlagsBus: out BIT; Load_FlagsFromFlagsBus: out BIT; Select_FlagsToDataBus: out BIT; Select_Flags: out BIT; Select_PortA_To_DataBus: out BIT; Select_PortB_To_DataBus: out BIT; Load_PortC_From_DataBus: out BIT; Load_PortD_From_DataBus: out BIT; StopCPU: out BIT ); end InstructionDecoder; architecture Behavioral of InstructionDecoder is component Decoder3to8 is Port ( F : in BIT_VECTOR(2 downto 0); -- 3-Bit Function Code (Input) X : out BIT_VECTOR(7 downto 0); -- 8-Bit State (Output) Started: in BIT -- Is the CPU already running? ); end component Decoder3to8; signal NegatedInstruction : BIT_VECTOR(7 downto 0); signal NegatedFlags : BIT_VECTOR(7 downto 0); signal instruction_SETAB: BIT; signal instruction_ALU: BIT; signal instruction_MOV: BIT; signal instruction_MOV16: BIT; signal instruction_LOAD: BIT; signal instruction_STORE: BIT; signal instruction_JMP: BIT; signal instruction_HLT: BIT; signal instruction_JZ: BIT; signal instruction_JNZ: BIT; signal instruction_JNS: BIT; signal instruction_JNC: BIT; signal instruction_SAVE_FLAGS: BIT; signal instruction_RESTORE_FLAGS: BIT; signal instruction_NOP: BIT; signal instruction_FLAGS_TO_OUTBUFFER: BIT; signal instruction_INBUFFER_TO_FLAGS: BIT; signal instruction_ADDER_16BIT: BIT; signal instruction_STORE_FLAGS: BIT; signal instruction_LOAD_FLAGS: BIT; signal instruction_IN: BIT; signal instruction_OUT: BIT; -- Internal ALU instructions signal instruction_MOV_ALU_IN: BIT; signal instruction_MOV_ALU_OUT: BIT; signal instruction_MOV_ALU_C_TO_AB: BIT; signal MOV_DestinationRegister: BIT_VECTOR(7 downto 0); signal MOV_SourceRegister: BIT_VECTOR(7 downto 0); signal MOV16_DestinationRegister: BIT_VECTOR(7 downto 0); signal MOV16_SourceRegister: BIT_VECTOR(7 downto 0); -- Used by the Fetch/Increment cycle signal Select_SRAM_FETCH: BIT; signal Load_PC_FETCH: BIT; signal Select_PC_FETCH: BIT; signal Return_SRAM_FETCH: BIT; -- Used by the SETAB opcode signal Load_A_From_DataBus_SETAB: BIT; signal Load_B_From_DataBus_SETAB: BIT; -- Used by the ALU opcode signal Load_C_From_DataBus_ALU: BIT; signal Load_Flags_From_ALU: BIT; -- Used by the MOV opcode signal Select_D_To_DataBus_MOV: BIT; signal Select_E_To_DataBus_MOV: BIT; signal Select_F_To_DataBus_MOV: BIT; signal Select_G_To_DataBus_MOV: BIT; signal Select_H_To_DataBus_MOV: BIT; signal Select_SP_To_DataBus_MOV: BIT; signal Select_XL_To_DataBus_MOV: BIT; signal Select_XH_To_DataBus_MOV: BIT; signal Load_D_From_DataBus_MOV: BIT; signal Load_E_From_DataBus_MOV: BIT; signal Load_F_From_DataBus_MOV: BIT; signal Load_G_From_DataBus_MOV: BIT; signal Load_H_From_DataBus_MOV: BIT; signal Load_SP_From_DataBus_MOV: BIT; signal Load_XL_From_DataBus_MOV: BIT; signal Load_XH_From_DataBus_MOV: BIT; signal Load_J_From_DataBus_MOV: BIT; -- Used by the MOV16 opcode signal Select_M_To_AddressBus_MOV16: BIT; signal Select_X_To_AddressBus_MOV16: BIT; signal Load_M_From_AddressBus_MOV16: BIT; signal Load_X_From_AddressBus_MOV16: BIT; signal Select_J_To_AddressBus_MOV16: BIT; signal Load_J_From_AddressBus_MOV16: BIT; signal Select_SP_To_AddressBus_MOV16: BIT; signal Load_SP_From_AddressBus_MOV16: BIT; signal Select_PC_To_AddressBus_MOV16: BIT; signal Load_PC_From_AddressBus_MOV16: BIT; signal Select_BP_To_AddressBus_MOV16: BIT; signal Load_BP_From_AddressBus_MOV16: BIT; signal Select_Y_To_AddressBus_MOV16: BIT; signal Load_Y_From_AddressBus_MOV16: BIT; signal Select_Z_To_AddressBus_MOV16: BIT; signal Load_Z_From_AddressBus_MOV16: BIT; -- Used by the LOAD opcode signal Select_SRAM_LOAD: BIT; signal Return_SRAM_LOAD: BIT; signal Load_D_From_DataBus_LOAD: BIT; signal Load_E_From_DataBus_LOAD: BIT; signal Load_F_From_DataBus_LOAD: BIT; signal Load_G_From_DataBus_LOAD: BIT; signal Load_H_From_DataBus_LOAD: BIT; signal Load_XL_From_DataBus_LOAD: BIT; signal Load_XH_From_DataBus_LOAD: BIT; signal Select_M_To_AddressBus_LOAD: BIT; -- Used by the STORE opcode signal Load_SRAM_LOAD: BIT; signal Select_D_To_DataBus_STORE: BIT; signal Select_E_To_DataBus_STORE: BIT; signal Select_F_To_DataBus_STORE: BIT; signal Select_G_To_DataBus_STORE: BIT; signal Select_H_To_DataBus_STORE: BIT; signal Select_XL_To_DataBus_STORE: BIT; signal Select_XH_To_DataBus_STORE: BIT; signal Select_M_To_AddressBus_STORE: BIT; signal Load_SRAM_STORE: BIT; -- Used by the LOAD_FLAGS opcode signal Load_SRAM_STORE_FLAGS: BIT; signal Select_M_To_AddressBus_STORE_FLAGS: BIT; -- Used by the STORE_FLAGS opcode signal Select_SRAM_LOAD_FLAGS: BIT; signal Select_M_To_AddressBus_LOAD_FLAGS: BIT; signal Return_SRAM_LOAD_FLAGS: BIT; -- Used by the JMP opcode signal Load_PC_JMP: BIT; signal Select_J_To_AddressBus_JMP: BIT; -- Used by the JZ opcode signal Load_PC_JZ: BIT; signal Select_J_To_AddressBus_JZ: BIT; signal Select_Flags_JZ: BIT; -- Used by the JNS opcode signal Load_PC_JNS: BIT; signal Select_J_To_AddressBus_JNS: BIT; signal Select_Flags_JNS: BIT; -- Used by the JNC opcode signal Load_PC_JNC: BIT; signal Select_J_To_AddressBus_JNC: BIT; signal Select_Flags_JNC: BIT; -- Used by the JNZ opcode signal Load_PC_JNZ: BIT; signal Select_J_To_AddressBus_JNZ: BIT; signal Select_Flags_JNZ: BIT; -- Used by the SAVE_FLAGS opcode signal Select_Flags_SAVE_FLAGS: BIT; -- Used by the RESTORE_FLAGS opcode signal Load_Flags_SAVE_FLAGS: BIT; -- Used by the INBUFFER_TO_FLAGS opcode signal Load_Flags_INBUFFER_TO_FLAGS: BIT; -- Used by the FLAGS_TO_DATABUS opcode signal Select_Flags_FLAGS_TO_OUTBUFFER: BIT; -- Used by the MOV_ALU_IN opcode signal Select_D_To_DataBus_MOV_ALU_IN: BIT; signal Select_E_To_DataBus_MOV_ALU_IN: BIT; signal Select_F_To_DataBus_MOV_ALU_IN: BIT; signal Select_G_To_DataBus_MOV_ALU_IN: BIT; signal Select_H_To_DataBus_MOV_ALU_IN: BIT; signal Select_XL_To_DataBus_MOV_ALU_IN: BIT; signal Select_XH_To_DataBus_MOV_ALU_IN: BIT; signal Select_SP_To_DataBus_MOV_ALU_IN: BIT; signal Load_A_From_DataBus_MOV_ALU_IN: BIT; signal Load_B_From_DataBus_MOV_ALU_IN: BIT; signal MOV_ALU_IN_SourceRegister: BIT_VECTOR(7 downto 0); -- Used by the MOV_ALU_OUT opcode signal Load_D_From_DataBus_MOV_ALU_OUT: BIT; signal Load_E_From_DataBus_MOV_ALU_OUT: BIT; signal Load_F_From_DataBus_MOV_ALU_OUT: BIT; signal Load_G_From_DataBus_MOV_ALU_OUT: BIT; signal Load_H_From_DataBus_MOV_ALU_OUT: BIT; signal Load_XL_From_DataBus_MOV_ALU_OUT: BIT; signal Load_XH_From_DataBus_MOV_ALU_OUT: BIT; signal Load_SP_From_DataBus_MOV_ALU_OUT: BIT; signal Load_J_From_DataBus_MOV_ALU_OUT: BIT; signal Select_C_To_DataBus_MOV_ALU_OUT: BIT; signal MOV_ALU_OUT_DestinationRegister: BIT_VECTOR(7 downto 0); -- Used by the MOV_ALU_C_TO_AB opcode signal Load_A_From_DataBus_MOV_ALU_C_TO_AB: BIT; signal Load_B_From_DataBus_MOV_ALU_C_TO_AB: BIT; signal Select_C_To_DataBus_MOV_ALU_C_TO_AB: BIT; -- Used by the ADDER_16BIT opcode signal Select_D_To_DataBus_ADDER_16BIT: BIT; signal Select_X_To_AddressBus_ADDER_16BIT: BIT; signal Load_X_From_AddressBus_ADDER_16BIT: BIT; signal Select_J_To_AddressBus_ADDER_16BIT: BIT; -- Used by the IN opcode signal Load_XL_From_DataBus_IN: BIT; -- Used by the OUT opcode signal Select_XL_To_DataBus_OUT: BIT; begin -- Negate the instruction, so that we can afterwards probe -- for a specific instruction NegatedInstruction <= not(Instruction); -- Negate the FLAGS NegatedFlags <= not(Flags); -- ================================================================ -- The following section implements the Fetch/Increment operations -- ================================================================ Load_PC_FETCH <= TimingSignals(2); -- State #3 Select_PC_FETCH <= TimingSignals(0) or -- State #1 TimingSignals(1); -- State #2 -- We request the data from the RAM in the states #1 and #2 Select_SRAM_FETCH <= TimingSignals(0) or -- State #1 TimingSignals(1); -- State #2 -- Because the RAM has a latency of 1 clock cycle, we only return the -- requested data from the RAM in state #2 (data in state #1 is still unstable!!!) Return_SRAM_FETCH <= TimingSignals(1); -- State #2 Load_INC <= TimingSignals(0); -- State #1 Select_INC <= TimingSignals(2); -- State #3 Load_INSTR <= TimingSignals(1); -- State #2 -- ============================================================ -- Now we have to decode the instruction to enable the correct -- Control Lines based on the provided timing signal -- ============================================================ -- --------------------------------------- -- Instruction "SETAB" - Format: 111DVVVV -- --------------------------------------- -- 111: OpCode -- D: Destination ('0' = Register A, '1' = Register B) -- VVVV: 4-bit value -- Check if we execute the "SETAB" instruction - OpCode "111" instruction_SETAB <= Instruction(7) and Instruction(6) and Instruction(5); -- The "Select_INSTR" control line goes high, when we execute the -- instruction "SETAB" and the time state is #4 -- This gates the instruction from the instruction register onto the data bus Select_INSTR_To_DataBus <= instruction_SETAB and TimingSignals(3); -- The instruction from the data bus is loaded into the register "Internal A" Load_InternalA_From_DataBus <= instruction_SETAB and TimingSignals(3); -- The first 4 bits from the register "Internal A" are gated back to the data bus Select_InternalA_To_DataBus <= instruction_SETAB and TimingSignals(4); -- The "Load_A" control line goes high, when we execute the -- instruction "SETAB" and the time state is #4 -- This loads the data currently stored on the data bus into the Register "A" Load_A_From_DataBus_SETAB <= instruction_SETAB and TimingSignals(4) and NegatedInstruction(4); -- The "Load_B" control line goes high, when we execute the -- instruction "SETAB" and the time state is #4 -- This loads the data currently stored on the data bus into the Register "B" Load_B_From_DataBus_SETAB <= instruction_SETAB and TimingSignals(4) and Instruction(4); -- --------------------------------------- -- Instruction "ALU" - Format: 1000FFFF -- --------------------------------------- -- 1000: OpCode -- FFFF: 4-bit function code -- Check if we execute the "ALU" instruction - OpoCode "1000" instruction_ALU <= Instruction(7) and NegatedInstruction(6) and NegatedInstruction(5) and NegatedInstruction(4); instruction_NOP <= NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- The "Select_A_To_ALU" and "Select_B_To_ALU" control lines are going high, when we execute -- the instruction "ALU" and the time state is #4 or #5. -- This transfers the content of the Register A and Register B into the ALU -- for execution. Select_A_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4)); Select_B_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4)); -- The "SELECT_INSTR" control line goes high, when we execute the instruction "ALU" -- and the time state is #4 or #5. -- This transfers the 4-bit function code of the Instruction Register into the ALU -- for execution. Select_INSTR_To_ALU <= instruction_ALU and (TimingSignals(3) or TimingSignals(4)); -- The "Select C" control line goes high, when we execute the instruction -- "ALU" and the time state is #5. -- This transfers the result of the ALU into the Register C. Load_C_From_DataBus_ALU <= instruction_ALU and TimingSignals(4); -- This transfers the result of the ALU Flags into the register FLAGS Load_Flags_From_ALU <= instruction_ALU and TimingSignals(4) and not(instruction_NOP); -- ------------------------------------------------- -- Instruction "MOV_ALU_C_TO_AB" - Format: 1010111D -- ------------------------------------------------- -- 1010111: OpCode -- D: Destination Register -- => "0": Register A -- => "1": Register B -- Check if we execute the "MOV_ALU_OUT" instruction - OpCode "1010111" instruction_MOV_ALU_C_TO_AB <= Instruction(7) and NegatedInstruction(6) and Instruction(5) and NegatedInstruction(4) and Instruction(3) and Instruction(2) and Instruction(1); Load_A_From_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); Load_B_From_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and Instruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the register C of the ALU to the data bus Select_C_To_DataBus_MOV_ALU_C_TO_AB <= instruction_MOV_ALU_C_TO_AB and (TimingSignals(4) or TimingSignals(5)); -- -------------------------------------------- -- Instruction "MOV_ALU_OUT" - Format: 11011DDD -- -------------------------------------------- -- 11011: OpCode -- DDD: Destination Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not yet used> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "MOV_ALU_OUT" instruction - OpCode "11011" instruction_MOV_ALU_OUT <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and Instruction(4) and Instruction(3); -- Decode the destination and source register from the provided instruction DestinationRegisterDecoder_MOV_ALU_OUT: Decoder3to8 port map(Instruction(2 downto 0), MOV_ALU_OUT_DestinationRegister, '1'); -- Load the specified register from the data bus Load_D_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(0) and (TimingSignals(4) or TimingSignals(5)); Load_E_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(1) and (TimingSignals(4) or TimingSignals(5)); Load_F_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(2) and (TimingSignals(4) or TimingSignals(5)); Load_G_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(3) and (TimingSignals(4) or TimingSignals(5)); Load_H_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(4) and (TimingSignals(4) or TimingSignals(5)); Load_XL_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(6) and (TimingSignals(4) or TimingSignals(5)); Load_XH_From_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and MOV_ALU_OUT_DestinationRegister(7) and (TimingSignals(4) or TimingSignals(5)); -- Select the register C of the ALU to the data bus Select_C_To_DataBus_MOV_ALU_OUT <= instruction_MOV_ALU_OUT and (TimingSignals(4) or TimingSignals(5)); -- -------------------------------------------- -- Instruction "MOV_ALU_IN" - Format: 1011DSSS -- -------------------------------------------- -- 1011: OpCode -- D: Destination Register -- => "0": Register A -- => "1": Register B -- SSS: Source Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not yet used> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "MOV_ALU_IN" instruction - OpCode "1011" instruction_MOV_ALU_IN <= Instruction(7) and NegatedInstruction(6) and Instruction(5) and Instruction(4); -- Decode the destination and source register from the provided instruction SourceRegisterDecoder_MOV_ALU_IN: Decoder3to8 port map(Instruction(2 downto 0), MOV_ALU_IN_SourceRegister, '1'); -- Latch the specified register onto the data bus Select_D_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5)); Select_E_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5)); Select_F_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5)); Select_G_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5)); Select_H_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5)); Select_XL_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5)); Select_XH_To_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and MOV_ALU_IN_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5)); -- Load the specified register from the data bus Load_A_From_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and NegatedInstruction(3) and TimingSignals(4); Load_B_From_DataBus_MOV_ALU_IN <= instruction_MOV_ALU_IN and Instruction(3) and TimingSignals(4); -- --------------------------------------- -- Instruction "MOV" - Format: 00DDDSSS -- --------------------------------------- -- 00: OpCode -- DDD: Destination Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not yet used> -- => "110": Register XL -- => "111": Register XH -- SSS: Source Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not yet used> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "MOV" instruction - OpCode "00" instruction_MOV <= NegatedInstruction(7) and NegatedInstruction(6); -- Decode the destination and source register from the provided instruction DestinationRegisterDecoder: Decoder3to8 port map(Instruction(5 downto 3), MOV_DestinationRegister, '1'); SourceRegisterDecoder: Decoder3to8 port map(Instruction(2 downto 0), MOV_SourceRegister, '1'); -- Gate the specified register onto the data bus Select_D_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5)); Select_E_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5)); Select_F_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5)); Select_G_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5)); Select_H_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5)); Select_XL_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5)); Select_XH_To_DataBus_MOV <= instruction_MOV and MOV_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5)); -- Load the specified register from the data bus Load_D_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(0) and TimingSignals(4); Load_E_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(1) and TimingSignals(4); Load_F_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(2) and TimingSignals(4); Load_G_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(3) and TimingSignals(4); Load_H_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(4) and TimingSignals(4); Load_XL_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(6) and TimingSignals(4); Load_XH_From_DataBus_MOV <= instruction_MOV and MOV_DestinationRegister(7) and TimingSignals(4); -- --------------------------------------- -- Instruction "MOV16" - Format: 01DDDSSS -- --------------------------------------- -- 01: OpCode -- DDD: Destination Register -- => "000": Register M -- => "001": Register X -- => "010": Register J -- => "011": Register SP -- => "100": Register PC -- => "101": Register BP -- => "110": Register Y -- => "111": Register Z -- SSS: Source Register -- => "000": Register M -- => "001": Register X -- => "010": Register J -- => "011": Register SP -- => "100": Register PC -- => "101": Register BP -- => "110": Register Y -- => "111": Register Z -- Check if we execute the "MOV16" instruction - OpCode "01" instruction_MOV16 <= NegatedInstruction(7) and Instruction(6); -- Decode the destination and source register from the provided instruction DestinationRegisterDecoderMOV16: Decoder3to8 port map(Instruction(5 downto 3), MOV16_DestinationRegister, '1'); SourceRegisterDecoderMOV16: Decoder3to8 port map(Instruction(2 downto 0), MOV16_SourceRegister, '1'); -- Gate the specified register onto the data bus Select_M_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(0) and (TimingSignals(4) or TimingSignals(5)); Select_X_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(1) and (TimingSignals(4) or TimingSignals(5)); Select_J_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(2) and (TimingSignals(4) or TimingSignals(5)); Select_SP_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(3) and (TimingSignals(4) or TimingSignals(5)); Select_PC_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(4) and (TimingSignals(4) or TimingSignals(5)); Select_BP_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(5) and (TimingSignals(4) or TimingSignals(5)); Select_Y_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(6) and (TimingSignals(4) or TimingSignals(5)); Select_Z_To_AddressBus_MOV16 <= instruction_MOV16 and MOV16_SourceRegister(7) and (TimingSignals(4) or TimingSignals(5)); -- Load the specified register from the data bus Load_M_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(0) and TimingSignals(4); Load_X_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(1) and TimingSignals(4); Load_J_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(2) and TimingSignals(4); Load_SP_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(3) and TimingSignals(4); Load_PC_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(4) and TimingSignals(4); Load_BP_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(5) and TimingSignals(4); Load_Y_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(6) and TimingSignals(4); Load_Z_From_AddressBus_MOV16 <= instruction_MOV16 and MOV16_DestinationRegister(7) and TimingSignals(4); -- ------------------------------------- -- Instruction "HLT" - Format: 11000011 -- ------------------------------------- -- Stops the execution of the CPU. -- 11010011: OpCode -- Check if we execute the "HLT" instruction - OpCode "11010011" instruction_HLT <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and Instruction(1) and Instruction(0); -- Stops the CPU execution StopCPU <= instruction_HLT; -- --------------------------------------- -- Instruction "LOAD" - Format: 10010DDD -- --------------------------------------- -- Loads a 8-bit value from SRAM memory into the specified register. -- The SRAM memory address is stored in the register "M". -- The transfer of the data to the register from the SRAM memory is done through the data bus. -- 10010: OpCode -- DDD: Destination Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not used...> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "LOAD" instruction - OpCode "10010" instruction_LOAD <= Instruction(7) and NegatedInstruction(6) and NegatedInstruction(5) and Instruction(4) and NegatedInstruction(3); -- Latch the SRAM memory address from register M onto the address bus Select_M_To_AddressBus_LOAD <= instruction_LOAD and (TimingSignals(4) or TimingSignals(5)); -- Request the 8-bit from the RAM memory in the states #5, #6, and #7 Select_SRAM_LOAD <= instruction_LOAD and (TimingSignals(4) or TimingSignals(5) or TimingSignals(6)); -- Because the RAM has a latency of 1 clock cycle, we only return the -- requested data from the RAM in state #7 (data in state #5, #6 is still unstable!!!) -- This finally places the requested RAM data onto the data bus Return_SRAM_LOAD <= TimingSignals(6); -- State #7 -- Load the Register D from the data bus Load_D_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- Load the Register E from the data bus Load_E_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0); -- Load the Register F from the data bus Load_F_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and NegatedInstruction(2) and Instruction(1) and NegatedInstruction(0); -- Load the Register G from the data bus Load_G_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and NegatedInstruction(2) and Instruction(1) and Instruction(0); -- Load the Register H from the data bus Load_H_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and Instruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- Load the Register XL from the data bus Load_XL_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and Instruction(2) and Instruction(1) and NegatedInstruction(0); -- Load the Register XL from the data bus Load_XH_From_DataBus_LOAD <= instruction_LOAD and TimingSignals(6) and Instruction(2) and Instruction(1) and Instruction(0); -- --------------------------------------- -- Instruction "STORE" - Format: 10011SSS -- --------------------------------------- -- Save a 8-bit value to SRAM memory from the specified register. -- The SRAM memory address is stored in the register "M". -- The transfer of the data from the register into the SRAM memory is done through the data bus. -- 10011: OpCode -- SSS: Source Register -- => "000": Register D -- => "001": Register E -- => "010": Register F -- => "011": Register G -- => "100": Register H -- => "101": <Not used...> -- => "110": Register XL -- => "111": Register XH -- Check if we execute the "STORE" instruction - OpCode "10011" instruction_STORE <= Instruction(7) and NegatedInstruction(6) and NegatedInstruction(5) and Instruction(4) and Instruction(3); -- Selects the content of the register "M" onto the address bus Select_M_To_AddressBus_STORE <= instruction_STORE and (TimingSignals(4) or TimingSignals(5)); -- Select the Register D to the data bus Select_D_To_DataBus_STORE <= instruction_STORE and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register E to the data bus Select_E_To_DataBus_STORE <= instruction_STORE and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register F to the data bus Select_F_To_DataBus_STORE <= instruction_STORE and NegatedInstruction(2) and Instruction(1) and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register G to the data bus Select_G_To_DataBus_STORE <= instruction_STORE and NegatedInstruction(2) and Instruction(1) and Instruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register H to the data bus Select_H_To_DataBus_STORE <= instruction_STORE and Instruction(2) and NegatedInstruction(1) and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register XL to the data bus Select_XL_To_DataBus_STORE <= instruction_STORE and Instruction(2) and Instruction(1) and NegatedInstruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Select the Register XH to the data bus Select_XH_To_DataBus_STORE <= instruction_STORE and Instruction(2) and Instruction(1) and Instruction(0) and (TimingSignals(4) or TimingSignals(5)); -- Enables the Load Line of the RAM memory and transfers the data from the data bus into -- the memory address provided in register M Load_SRAM_STORE <= instruction_STORE and TimingSignals(5); -- --------------------------------------------- -- Instruction "STORE_FLAGS" - Format: 11001001 -- --------------------------------------------- -- Selects the flags from the "FlagsOutBuffer" register onto the data bus -- and stores it in the RAM. -- 11001001: OpCode -- Check if we execute the "STORE_FLAGS" instruction - OpCode "11001001" instruction_STORE_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0); -- Selects the content of the register "M" onto the address bus Select_M_To_AddressBus_STORE_FLAGS <= instruction_STORE_FLAGS and (TimingSignals(4) or TimingSignals(5)); -- Selects the flags from the "FlagsOutBuffer" onto the data bus Select_FlagsToDataBus <= instruction_STORE_FLAGS and (TimingSignals(4) or TimingSignals(5)); -- Enables the Load Line of the RAM memory and transfers the data from the data bus into -- the memory address provided in register M Load_SRAM_STORE_FLAGS <= instruction_STORE_FLAGS and TimingSignals(5); -- --------------------------------------------- -- Instruction "LOAD_FLAGS" - Format: 11001010 -- --------------------------------------------- -- Loads the flags from the RAM and writes them into the "FlagsInBuffer" register. -- and stores it onto the stack -- 11001010: OpCode -- Check if we execute the "STORE_FLAGS" instruction - OpCode "11001010" instruction_LOAD_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and NegatedInstruction(2) and Instruction(1) and NegatedInstruction(0); -- Latch the SRAM memory address from register M onto the address bus Select_M_To_AddressBus_LOAD_FLAGS <= instruction_LOAD_FLAGS and (TimingSignals(4) or TimingSignals(5)); -- Request the 8-bit from the RAM memory in the states #5, #6, and #7 Select_SRAM_LOAD_FLAGS <= instruction_LOAD_FLAGS and (TimingSignals(4) or TimingSignals(5) or TimingSignals(6)); -- Because the RAM has a latency of 1 clock cycle, we only return the -- requested data from the RAM in state #7 (data in state #5, #6 is still unstable!!!) -- This finally places the requested RAM data onto the data bus Return_SRAM_LOAD_FLAGS <= TimingSignals(6); -- State #7 -- Selects the flags from the "FlagsOutBuffer" onto the data bus Load_FlagsFromDataBus <= instruction_LOAD_FLAGS and TimingSignals(6); -- --------------------------------------- -- Instruction "JMP" - Format: 11000010 -- --------------------------------------- -- Unconditional jump to the address in the program code that is stored in the register "J". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11000010: OpCode -- Check if we execute the "JMP" instruction - OpCode "11000010" instruction_JMP <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and Instruction(1) and NegatedInstruction(0); -- Select the target jump address to the address bus Select_J_To_AddressBus_JMP <= instruction_JMP and (TimingSignals(4) or TimingSignals(5)); -- Load the Program Counter from the address bus Load_PC_JMP <= instruction_JMP and TimingSignals(5); -- -------------------------------------------- -- Instruction "SAVE_FLAGS" - Format: 11000100 -- -------------------------------------------- -- Saves the current content of the flags register into the "SavedFlags" register -- 11000100: OpCode -- Check if we execute the "SAVE_FLAGS" instruction - OpCode "11000100" instruction_SAVE_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and Instruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- Enables the Select Line of the flags register to load the flags into the "SavedFlags" register Select_Flags_SAVE_FLAGS <= instruction_SAVE_FLAGS and TimingSignals(4); -- Enables the Load Line of the "SavedFlags" register to load the flags into the "SavedFlags" register Load_FlagsSaved_From_FlagsRegister <= instruction_SAVE_FLAGS and TimingSignals(4); -- ----------------------------------------------- -- Instruction "RESTORE_FLAGS" - Format: 11000101 -- ----------------------------------------------- -- Saves the current content of the flags register into the "SavedFlags" register -- 11000101: OpCode -- Check if we execute the "RESTORE_FLAGS" instruction - OpCode "11000101" instruction_RESTORE_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and Instruction(2) and NegatedInstruction(1) and Instruction(0); -- Enables the Load Line of the flags register to load the "SavedFlags" register into the flags register Load_Flags_SAVE_FLAGS <= instruction_RESTORE_FLAGS and TimingSignals(4); -- Enables the Select Line of the "SavedFlags" register to load the "SavedFlags" register into the flags register Load_FlagsSaved_To_FlagsRegister <= instruction_RESTORE_FLAGS and TimingSignals(4); -- ---------------------------------------------------- -- Instruction "FLAGS_TO_OUTBUFFER" - Format: 11000110 -- ---------------------------------------------------- -- Writes the current content of the flags register onto the data bus -- 11000110: OpCode -- Check if we execute the "FLAGS_TO_OUTBUFFER" instruction - OpCode "11000110" instruction_FLAGS_TO_OUTBUFFER <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and Instruction(2) and Instruction(1) and NegatedInstruction(0); -- Selects the content from the Flags register onto the Flags Bus Select_Flags_FLAGS_TO_OUTBUFFER <= instruction_FLAGS_TO_OUTBUFFER and TimingSignals(4); -- Loads the content from the Flags Bus into the "FlagsOutBuffer" register Load_FlagsFromFlagsBus <= instruction_FLAGS_TO_OUTBUFFER and TimingSignals(4); -- --------------------------------------------------- -- Instruction "INBUFFER_TO_FLAGS" - Format: 11000111 -- --------------------------------------------------- -- Writes the current content of the flags register onto the data bus -- 11000111: OpCode -- Check if we execute the "FLAGS_TO_INBUFFER" instruction - OpCode "11000111" instruction_INBUFFER_TO_FLAGS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and Instruction(2) and Instruction(1) and Instruction(0); -- Selects the content from the "FlagsInBuffer" register to the Flags Bus Select_FlagsToFlagsBus <= instruction_INBUFFER_TO_FLAGS and TimingSignals(4); -- Loads the content from the Flags Bus into the Flags register Load_Flags_INBUFFER_TO_FLAGS <= instruction_INBUFFER_TO_FLAGS and TimingSignals(4); -- --------------------------------------- -- Instruction "JZ" - Format: 11000000 -- --------------------------------------- -- Conditional jump to the address in the program code that is stored in the register "J". -- The jump is only executed if the Zero-Flag in the FLAGS register is set to "1". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11000000: OpCode -- Check if we execute the "JZ" instruction - OpCode "11000000" instruction_JZ <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0); Select_Flags_JZ <= instruction_JZ and (TimingSignals(5) or TimingSignals(6) or TimingSignals(7)); -- Select the target jump address to the address bus Select_J_To_AddressBus_JZ <= instruction_JZ and Flags(1) and (TimingSignals(6) or TimingSignals(7)); -- Load the Program Counter from the address bus Load_PC_JZ <= instruction_JZ and Flags(1) and TimingSignals(7); -- --------------------------------------- -- Instruction "JNS" - Format: 11001011 -- --------------------------------------- -- Conditional jump to the address in the program code that is stored in the register "J". -- The jump is only executed if the Sign-Flag in the FLAGS register is set to "0". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11001011: OpCode -- Check if we execute the "JNS" instruction - OpCode "11001011" instruction_JNS <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and NegatedInstruction(2) and Instruction(1) and Instruction(0); Select_Flags_JNS <= instruction_JNS and (TimingSignals(5) or TimingSignals(6) or TimingSignals(7)); -- Select the target jump address to the address bus Select_J_To_AddressBus_JNS <= instruction_JNS and (not Flags(0)) and (TimingSignals(6) or TimingSignals(7)); -- Load the Program Counter from the address bus Load_PC_JNS <= instruction_JNS and (not Flags(0)) and TimingSignals(7); -- --------------------------------------- -- Instruction "JNC" - Format: 11010001 -- --------------------------------------- -- Conditional jump to the address in the program code that is stored in the register "J". -- The jump is only executed if the Carry-Flag in the FLAGS register is set to "0". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11001011: OpCode -- Check if we execute the "JNC" instruction - OpCode "11010001" instruction_JNC <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and Instruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0); Select_Flags_JNC <= instruction_JNC and (TimingSignals(5) or TimingSignals(6) or TimingSignals(7)); -- Select the target jump address to the address bus Select_J_To_AddressBus_JNC <= instruction_JNC and (not Flags(2)) and (TimingSignals(6) or TimingSignals(7)); -- Load the Program Counter from the address bus Load_PC_JNC <= instruction_JNC and (not Flags(2)) and TimingSignals(7); -- --------------------------------------- -- Instruction "JNZ" - Format: 11000001 -- --------------------------------------- -- Conditional jump to the address in the program code that is stored in the register "J". -- The jump is only executed if the Zero-Flag in the FLAGS register is set to "0". -- The memory address from register "J" is loaded into the program counter. -- In the next machine cycle the execution continues at the new program counter position. -- 11000001: OpCode -- Check if we execute the "JNZ" instruction - OpCode "11000001" instruction_JNZ <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and NegatedInstruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and Instruction(0); Select_Flags_JNZ <= instruction_JNZ and (TimingSignals(5) or TimingSignals(6) or TimingSignals(7)); -- Select the target jump address to the address bus Select_J_To_AddressBus_JNZ <= instruction_JNZ and NegatedFlags(1) and (TimingSignals(6) or TimingSignals(7)); -- Load the Program Counter from the address bus Load_PC_JNZ <= instruction_JNZ and NegatedFlags(1) and TimingSignals(7); -- --------------------------------------------- -- Instruction "16BIT_ADDER" - Format: 11001000 -- --------------------------------------------- -- Performs a 16-bit addition between the 16-bit value in register "X" and the -- 8-bit value in register "D". -- The result of the addition is put back into register "X". -- 11001000: OpCode -- Check if we execute the "16BIT_ADDER" instruction - OpCode "11001000" instruction_ADDER_16BIT <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and NegatedInstruction(2) and NegatedInstruction(1) and NegatedInstruction(0); -- Select the content of register "X" to the address bus Select_X_To_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and TimingSignals(3); -- Load the A input of the 16-bit Adder from the address bus Load_Adder16Bit_InputA <= instruction_ADDER_16BIT and TimingSignals(3); -- Select the content of register "J" to the address bus Select_J_To_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and TimingSignals(4); -- Load the B input of the 16-bit Adder from the address bus Load_Adder16Bit_InputB <= instruction_ADDER_16BIT and TimingSignals(4); -- Select the A input into the 16-bit Adder Select_Adder16Bit_InputA <= instruction_ADDER_16BIT and (TimingSignals(5) or TimingSignals(6)); -- Select the B input into the 16-bit Adder Select_Adder16Bit_InputB <= instruction_ADDER_16BIT and (TimingSignals(5) or TimingSignals(6)); -- Load the output from the 16-bit adder into the C output Load_Adder16Bit_OutputC <= instruction_ADDER_16BIT and TimingSignals(6); -- Select the output from the C output onto the address bus Select_Adder16Bit_OutputC <= instruction_ADDER_16BIT and TimingSignals(7); -- Load the content from the address bus into the register "X" Load_X_From_AddressBus_ADDER_16BIT <= instruction_ADDER_16BIT and TimingSignals(7); -- --------------------------------------------- -- Instruction "IN" - Format: 1100110P -- --------------------------------------------- -- Reads from the specified input port and places the read value into the specified register. -- 1100110P: OpCode -- P: Port - "0" -> Input Port A, "1" -> Input Port B -- Check if we execute the "IN" instruction - OpCode "1101" instruction_IN <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and Instruction(2) and NegatedInstruction(1); -- Select the input value from Input Port A to the data bus Select_PortA_To_DataBus <= instruction_IN and NegatedInstruction(0) and (TimingSignals(3) or TimingSignals(4)); -- Select the input value from Input Port B to the data bus Select_PortB_To_DataBus <= instruction_IN and Instruction(0) and (TimingSignals(3) or TimingSignals(4)); -- Load the Register XL from the data bus Load_XL_From_DataBus_IN <= instruction_IN and TimingSignals(4); -- --------------------------------------------- -- Instruction "OUT" - Format: 1100111P -- --------------------------------------------- -- Reads from the specified input port and places the read value into the specified register. -- 1100111P: OpCode -- P: Port - "0" -> Output Port C, "1" -> Output Port D -- Check if we execute the "IN" instruction - OpCode "1100111" instruction_OUT <= Instruction(7) and Instruction(6) and NegatedInstruction(5) and NegatedInstruction(4) and Instruction(3) and Instruction(2) and Instruction(1); -- Select the register XL to the data bus Select_XL_To_DataBus_OUT <= instruction_OUT and (TimingSignals(3) or TimingSignals(4)); -- Select the output value from the data bus into the Output Port C Load_PortC_From_DataBus <= instruction_OUT and NegatedInstruction(0) and TimingSignals(4); -- Select the output value from the data bus into the Output Port D Load_PortD_From_DataBus <= instruction_OUT and Instruction(0) and TimingSignals(4); -- ================================================================ -- The following section enables the final CPU control lines -- ================================================================ -- Enable/Disable Load Line of register A Load_A_From_DataBus <= Load_A_From_DataBus_SETAB or Load_A_From_DataBus_MOV_ALU_IN or Load_A_From_DataBus_MOV_ALU_C_TO_AB; -- Enable/Disable Load Line of register B Load_B_From_DataBus <= Load_B_From_DataBus_SETAB or Load_B_From_DataBus_MOV_ALU_IN or Load_B_From_DataBus_MOV_ALU_C_TO_AB; -- Enable/Disable Load Line of register C Load_C_From_DataBus <= Load_C_From_DataBus_ALU; -- Enable/Disable Load Line of register D Load_D_From_DataBus <= Load_D_From_DataBus_MOV_ALU_OUT or Load_D_From_DataBus_MOV or Load_D_From_DataBus_LOAD; -- Enable/Disable Load Line of register E Load_E_From_DataBus <= Load_E_From_DataBus_MOV_ALU_OUT or Load_E_From_DataBus_MOV or Load_E_From_DataBus_LOAD; -- Enable/Disable Load Line of register F Load_F_From_DataBus <= Load_F_From_DataBus_MOV_ALU_OUT or Load_F_From_DataBus_MOV or Load_F_From_DataBus_LOAD; -- Enable/Disable Load Line of register G Load_G_From_DataBus <= Load_G_From_DataBus_MOV_ALU_OUT or Load_G_From_DataBus_MOV or Load_G_From_DataBus_LOAD; -- Enable/Disable Load Line of register H Load_H_From_DataBus <= Load_H_From_DataBus_MOV_ALU_OUT or Load_H_From_DataBus_MOV or Load_H_From_DataBus_LOAD; -- Enable/Disable Load Line of register XL Load_XL_From_DataBus <= Load_XL_From_DataBus_MOV_ALU_OUT or Load_XL_From_DataBus_MOV or Load_XL_From_DataBus_LOAD or Load_XL_From_DataBus_IN; -- Enable/Disable Load Line of register XH Load_XH_From_DataBus <= Load_XH_From_DataBus_MOV_ALU_OUT or Load_XH_From_DataBus_MOV or Load_XH_From_DataBus_LOAD; -- Enable/Disable the Load Line of register M Load_M_From_AddressBus <= Load_M_From_AddressBus_MOV16; -- Enable/Disable the Load Line of register X Load_X_From_AddressBus <= Load_X_From_AddressBus_MOV16 or Load_X_From_AddressBus_ADDER_16BIT; -- Enable/Disable Load Line of register J Load_J_From_AddressBus <= Load_J_From_AddressBus_MOV16; -- Enable/Disable Load Line of register SP Load_SP_From_AddressBus <= Load_SP_From_AddressBus_MOV16; -- Enable/Disable Load Line of register BP Load_BP_From_AddressBus <= Load_BP_From_AddressBus_MOV16; -- Enable/Disable Load Line of register Y Load_Y_From_AddressBus <= Load_Y_From_AddressBus_MOV16; -- Enable/Disable Load Line of register Z Load_Z_From_AddressBus <= Load_Z_From_AddressBus_MOV16; -- Enable/Disable Select Line of register C Select_C_To_DataBus <= Select_C_To_DataBus_MOV_ALU_OUT or Select_C_To_DataBus_MOV_ALU_C_TO_AB; -- Enable/Disable Select Line of register D Select_D_To_DataBus <= Select_D_To_DataBus_MOV_ALU_IN or Select_D_To_DataBus_MOV or Select_D_To_DataBus_STORE or Select_D_To_DataBus_ADDER_16BIT; -- Enable/Disable Select Line of register E Select_E_To_DataBus <= Select_E_To_DataBus_MOV_ALU_IN or Select_E_To_DataBus_MOV or Select_E_To_DataBus_STORE; -- Enable/Disable Select Line of register F Select_F_To_DataBus <= Select_F_To_DataBus_MOV_ALU_IN or Select_F_To_DataBus_MOV or Select_F_To_DataBus_STORE; -- Enable/Disable Select Line of register G Select_G_To_DataBus <= Select_G_To_DataBus_MOV_ALU_IN or Select_G_To_DataBus_MOV or Select_G_To_DataBus_STORE; -- Enable/Disable Select Line of register H Select_H_To_DataBus <= Select_H_To_DataBus_MOV_ALU_IN or Select_H_To_DataBus_MOV or Select_H_To_DataBus_STORE; -- Enable/Disable Select Line of register XL Select_XL_To_DataBus <= Select_XL_To_DataBus_MOV_ALU_IN or Select_XL_To_DataBus_MOV or Select_XL_To_DataBus_STORE or Select_XL_To_DataBus_OUT; -- Enable/Disable Select Line of register XH Select_XH_To_DataBus <= Select_XH_To_DataBus_MOV_ALU_IN or Select_XH_To_DataBus_MOV or Select_XH_To_DataBus_STORE; -- Enable/Disable the Select Line of register M Select_M_To_AddressBus <= Select_M_To_AddressBus_MOV16 or Select_M_To_AddressBus_LOAD or Select_M_To_AddressBus_LOAD_FLAGS or Select_M_To_AddressBus_STORE or Select_M_To_AddressBus_STORE_FLAGS; -- Enable/Disable the Select Line of register X Select_X_To_AddressBus <= Select_X_To_AddressBus_MOV16 or Select_X_To_AddressBus_ADDER_16BIT or Select_X_To_AddressBus_ADDER_16BIT; -- Enable/Disable Select Line of register SP Select_SP_To_AddressBus <= Select_SP_To_AddressBus_MOV16; -- Enable/Disable Select Line of register BP Select_BP_To_AddressBus <= Select_BP_To_AddressBus_MOV16; -- Enable/Disable Select Line of register Y Select_Y_To_AddressBus <= Select_Y_To_AddressBus_MOV16; -- Enable/Disable Select Line of register Z Select_Z_To_AddressBus <= Select_Z_To_AddressBus_MOV16; -- Enable/Disable Select Line of register J Select_J_To_AddressBus <= Select_J_To_AddressBus_MOV16 or Select_J_To_AddressBus_JMP or Select_J_To_AddressBus_JZ or Select_J_To_AddressBus_JNS or Select_J_To_AddressBus_JNZ or Select_J_To_AddressBus_JNC or Select_J_To_AddressBus_ADDER_16BIT; -- Enables the Select Line of the flags register Select_Flags <= Select_Flags_JZ or Select_Flags_SAVE_FLAGS or Select_Flags_JNZ or Select_Flags_JNS or Select_Flags_JNC or Select_Flags_FLAGS_TO_OUTBUFFER; -- Enables the Load Line of the flags register Load_Flags <= Load_Flags_From_ALU or Load_Flags_SAVE_FLAGS or Load_Flags_INBUFFER_TO_FLAGS; -- Requests the data from the RAM to the data bus Select_SRAM <= Select_SRAM_FETCH or Select_SRAM_LOAD or Select_SRAM_LOAD_FLAGS; -- Loads the data from the data bus into the RAM Load_SRAM <= Load_SRAM_STORE or Load_SRAM_STORE_FLAGS; -- Returns the requested data from the RAM onto the data bus Return_SRAM <= Return_SRAM_FETCH or Return_SRAM_LOAD or Return_SRAM_LOAD_FLAGS; -- Enable/Disable the Load Line of the Program Counter Load_PC <= Load_PC_FETCH or Load_PC_JMP or Load_PC_JZ or Load_PC_JNS or Load_PC_JNZ or Load_PC_JNC or Load_PC_From_AddressBus_MOV16; -- Enable/Disable the Load Line of the Program Counter Select_PC <= Select_PC_FETCH or Select_PC_To_AddressBus_MOV16; end Behavioral;

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY char_7seg IS PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); Display : OUT STD_LOGIC_VECTOR(0 TO 6)); END char_7seg; ARCHITECTURE Behavior OF char_7seg IS BEGIN -- Behavior Display(0) <= C(0); Display(1) <= NOT(C(1)) OR C(0); Display(2) <= C(0); Display(3) <= C(0); Display(4) <= C(1); Display(5) <= C(1); Display(6) <= NOT(C(1)) OR C(0); END Behavior;

-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Checker -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: checker.vhd -- -- Description: -- Checker -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY work; USE work.BMG_TB_PKG.ALL; ENTITY CHECKER IS GENERIC ( WRITE_WIDTH : INTEGER :=32; READ_WIDTH : INTEGER :=32 ); PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; EN : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR STATUS : OUT STD_LOGIC:= '0' ); END CHECKER; ARCHITECTURE CHECKER_ARCH OF CHECKER IS SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); SIGNAL EN_R : STD_LOGIC := '0'; SIGNAL EN_2R : STD_LOGIC := '0'; --DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT --IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) --IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); SIGNAL ERR_HOLD : STD_LOGIC :='0'; SIGNAL ERR_DET : STD_LOGIC :='0'; BEGIN PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST= '1') THEN EN_R <= '0'; EN_2R <= '0'; DATA_IN_R <= (OTHERS=>'0'); ELSE EN_R <= EN; EN_2R <= EN_R; DATA_IN_R <= DATA_IN; END IF; END IF; END PROCESS; EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, DOUT_WIDTH => READ_WIDTH, DATA_PART_CNT => DATA_PART_CNT, SEED => 2 ) PORT MAP ( CLK => CLK, RST => RST, EN => EN_2R, DATA_OUT => EXPECTED_DATA ); PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(EN_2R='1') THEN IF(EXPECTED_DATA = DATA_IN_R) THEN ERR_DET<='0'; ELSE ERR_DET<= '1'; END IF; END IF; END IF; END PROCESS; PROCESS(CLK,RST) BEGIN IF(RST='1') THEN ERR_HOLD <= '0'; ELSIF(RISING_EDGE(CLK)) THEN ERR_HOLD <= ERR_HOLD OR ERR_DET ; END IF; END PROCESS; STATUS <= ERR_HOLD; END ARCHITECTURE;