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-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inductor is
port (terminal n1, n2: electrical);
end entity inductor;
----------------------------------------------------------------
architecture integral_form of inductor is
constant L: inductance := 0.5;
quantity branch_voltage across branch_current through n1 to n2;
begin
branch_current == branch_voltage'integ / L;
end architecture integral_form;
|
-- NEED RESULT: ENT00236.P00236: Associated composite buffer ports with static subtypes passed
-- NEED RESULT: ENT00236: Associated composite buffer ports with static subtypes passed
-- NEED RESULT: ENT00236.P00236: Associated composite buffer ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00236
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00236(ARCH00236)
-- ENT00236_Test_Bench(ARCH00236_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00236 is
port (
toggle : buffer switch := down;
i_bit_vector_1, i_bit_vector_2 : buffer bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : buffer string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : buffer t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : buffer st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : buffer t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : buffer st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : buffer t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : buffer st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : buffer t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : buffer st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : buffer t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : buffer st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : buffer t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : buffer st_arr3
:= c_st_arr3_1
) ;
begin
end ENT00236 ;
--
architecture ARCH00236 of ENT00236 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_bit_vector_1 = c_st_bit_vector_1
and i_bit_vector_2 = c_st_bit_vector_1 ;
correct := correct and i_string_1 = c_st_string_1
and i_string_2 = c_st_string_1 ;
correct := correct and i_t_rec1_1 = c_st_rec1_1
and i_t_rec1_2 = c_st_rec1_1 ;
correct := correct and i_st_rec1_1 = c_st_rec1_1
and i_st_rec1_2 = c_st_rec1_1 ;
correct := correct and i_t_rec2_1 = c_st_rec2_1
and i_t_rec2_2 = c_st_rec2_1 ;
correct := correct and i_st_rec2_1 = c_st_rec2_1
and i_st_rec2_2 = c_st_rec2_1 ;
correct := correct and i_t_rec3_1 = c_st_rec3_1
and i_t_rec3_2 = c_st_rec3_1 ;
correct := correct and i_st_rec3_1 = c_st_rec3_1
and i_st_rec3_2 = c_st_rec3_1 ;
correct := correct and i_t_arr1_1 = c_st_arr1_1
and i_t_arr1_2 = c_st_arr1_1 ;
correct := correct and i_st_arr1_1 = c_st_arr1_1
and i_st_arr1_2 = c_st_arr1_1 ;
correct := correct and i_t_arr2_1 = c_st_arr2_1
and i_t_arr2_2 = c_st_arr2_1 ;
correct := correct and i_st_arr2_1 = c_st_arr2_1
and i_st_arr2_2 = c_st_arr2_1 ;
correct := correct and i_t_arr3_1 = c_st_arr3_1
and i_t_arr3_2 = c_st_arr3_1 ;
correct := correct and i_st_arr3_1 = c_st_arr3_1
and i_st_arr3_2 = c_st_arr3_1 ;
--
test_report ( "ENT00236" ,
"Associated composite buffer ports with static subtypes" ,
correct) ;
--
toggle <= up ;
i_bit_vector_1 <= c_st_bit_vector_2 ;
i_bit_vector_2 <= c_st_bit_vector_2 ;
i_string_1 <= c_st_string_2 ;
i_string_2 <= c_st_string_2 ;
i_t_rec1_1 <= c_st_rec1_2 ;
i_t_rec1_2 <= c_st_rec1_2 ;
i_st_rec1_1 <= c_st_rec1_2 ;
i_st_rec1_2 <= c_st_rec1_2 ;
i_t_rec2_1 <= c_st_rec2_2 ;
i_t_rec2_2 <= c_st_rec2_2 ;
i_st_rec2_1 <= c_st_rec2_2 ;
i_st_rec2_2 <= c_st_rec2_2 ;
i_t_rec3_1 <= c_st_rec3_2 ;
i_t_rec3_2 <= c_st_rec3_2 ;
i_st_rec3_1 <= c_st_rec3_2 ;
i_st_rec3_2 <= c_st_rec3_2 ;
i_t_arr1_1 <= c_st_arr1_2 ;
i_t_arr1_2 <= c_st_arr1_2 ;
i_st_arr1_1 <= c_st_arr1_2 ;
i_st_arr1_2 <= c_st_arr1_2 ;
i_t_arr2_1 <= c_st_arr2_2 ;
i_t_arr2_2 <= c_st_arr2_2 ;
i_st_arr2_1 <= c_st_arr2_2 ;
i_st_arr2_2 <= c_st_arr2_2 ;
i_t_arr3_1 <= c_st_arr3_2 ;
i_t_arr3_2 <= c_st_arr3_2 ;
i_st_arr3_1 <= c_st_arr3_2 ;
i_st_arr3_2 <= c_st_arr3_2 ;
wait ;
end process ;
end ARCH00236 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00236_Test_Bench is
end ENT00236_Test_Bench ;
--
architecture ARCH00236_Test_Bench of ENT00236_Test_Bench is
begin
L1:
block
signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector
:= c_st_bit_vector_1 ;
signal i_string_1, i_string_2 : st_string
:= c_st_string_1 ;
signal i_t_rec1_1, i_t_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_st_rec1_1, i_st_rec1_2 : st_rec1
:= c_st_rec1_1 ;
signal i_t_rec2_1, i_t_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_st_rec2_1, i_st_rec2_2 : st_rec2
:= c_st_rec2_1 ;
signal i_t_rec3_1, i_t_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_st_rec3_1, i_st_rec3_2 : st_rec3
:= c_st_rec3_1 ;
signal i_t_arr1_1, i_t_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_st_arr1_1, i_st_arr1_2 : st_arr1
:= c_st_arr1_1 ;
signal i_t_arr2_1, i_t_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_st_arr2_1, i_st_arr2_2 : st_arr2
:= c_st_arr2_1 ;
signal i_t_arr3_1, i_t_arr3_2 : st_arr3
:= c_st_arr3_1 ;
signal i_st_arr3_1, i_st_arr3_2 : st_arr3
:= c_st_arr3_1 ;
--
component UUT
port (
toggle : buffer switch ;
i_bit_vector_1, i_bit_vector_2 : buffer bit_vector
:= c_st_bit_vector_1
;
i_string_1, i_string_2 : buffer string
:= c_st_string_1
;
i_t_rec1_1, i_t_rec1_2 : buffer t_rec1
:= c_st_rec1_1
;
i_st_rec1_1, i_st_rec1_2 : buffer st_rec1
:= c_st_rec1_1
;
i_t_rec2_1, i_t_rec2_2 : buffer t_rec2
:= c_st_rec2_1
;
i_st_rec2_1, i_st_rec2_2 : buffer st_rec2
:= c_st_rec2_1
;
i_t_rec3_1, i_t_rec3_2 : buffer t_rec3
:= c_st_rec3_1
;
i_st_rec3_1, i_st_rec3_2 : buffer st_rec3
:= c_st_rec3_1
;
i_t_arr1_1, i_t_arr1_2 : buffer t_arr1
:= c_st_arr1_1
;
i_st_arr1_1, i_st_arr1_2 : buffer st_arr1
:= c_st_arr1_1
;
i_t_arr2_1, i_t_arr2_2 : buffer t_arr2
:= c_st_arr2_1
;
i_st_arr2_1, i_st_arr2_2 : buffer st_arr2
:= c_st_arr2_1
;
i_t_arr3_1, i_t_arr3_2 : buffer t_arr3
:= c_st_arr3_1
;
i_st_arr3_1, i_st_arr3_2 : buffer st_arr3
:= c_st_arr3_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00236 ( ARCH00236 ) ;
--
begin
CIS1 : UUT
port map (
toggle ,
i_bit_vector_1, i_bit_vector_2,
i_string_1, i_string_2,
i_t_rec1_1, i_t_rec1_2,
i_st_rec1_1, i_st_rec1_2,
i_t_rec2_1, i_t_rec2_2,
i_st_rec2_1, i_st_rec2_2,
i_t_rec3_1, i_t_rec3_2,
i_st_rec3_1, i_st_rec3_2,
i_t_arr1_1, i_t_arr1_2,
i_st_arr1_1, i_st_arr1_2,
i_t_arr2_1, i_t_arr2_2,
i_st_arr2_1, i_st_arr2_2,
i_t_arr3_1, i_t_arr3_2,
i_st_arr3_1, i_st_arr3_2
) ;
P00236 :
process ( toggle )
variable correct : boolean := true ;
begin
if toggle = up then
correct := correct and i_bit_vector_1 = c_st_bit_vector_2
and i_bit_vector_2 = c_st_bit_vector_2 ;
correct := correct and i_string_1 = c_st_string_2
and i_string_2 = c_st_string_2 ;
correct := correct and i_t_rec1_1 = c_st_rec1_2
and i_t_rec1_2 = c_st_rec1_2 ;
correct := correct and i_st_rec1_1 = c_st_rec1_2
and i_st_rec1_2 = c_st_rec1_2 ;
correct := correct and i_t_rec2_1 = c_st_rec2_2
and i_t_rec2_2 = c_st_rec2_2 ;
correct := correct and i_st_rec2_1 = c_st_rec2_2
and i_st_rec2_2 = c_st_rec2_2 ;
correct := correct and i_t_rec3_1 = c_st_rec3_2
and i_t_rec3_2 = c_st_rec3_2 ;
correct := correct and i_st_rec3_1 = c_st_rec3_2
and i_st_rec3_2 = c_st_rec3_2 ;
correct := correct and i_t_arr1_1 = c_st_arr1_2
and i_t_arr1_2 = c_st_arr1_2 ;
correct := correct and i_st_arr1_1 = c_st_arr1_2
and i_st_arr1_2 = c_st_arr1_2 ;
correct := correct and i_t_arr2_1 = c_st_arr2_2
and i_t_arr2_2 = c_st_arr2_2 ;
correct := correct and i_st_arr2_1 = c_st_arr2_2
and i_st_arr2_2 = c_st_arr2_2 ;
correct := correct and i_t_arr3_1 = c_st_arr3_2
and i_t_arr3_2 = c_st_arr3_2 ;
correct := correct and i_st_arr3_1 = c_st_arr3_2
and i_st_arr3_2 = c_st_arr3_2 ;
end if ;
--
test_report ( "ENT00236.P00236" ,
"Associated composite buffer ports with static subtypes",
correct) ;
end process P00236 ;
end block L1 ;
end ARCH00236_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1022.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p10n02i01022pkg is
procedure check (x: in integer; y: in boolean);
end c06s03b00x00p10n02i01022pkg;
use work.c06s03b00x00p10n02i01022pkg.all;
ENTITY c06s03b00x00p10n02i01022ent IS
END c06s03b00x00p10n02i01022ent;
ARCHITECTURE c06s03b00x00p10n02i01022arch OF c06s03b00x00p10n02i01022ent IS
constant p: integer := 3;
constant q: boolean := true;
BEGIN
TESTING: PROCESS
variable p: integer;
variable q: boolean;
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p10n02i01022 - An expanded name is used outside the named construct."
severity ERROR;
wait;
END PROCESS TESTING;
check (TESTING.p, TESTING.q); -- Failure_here
END c06s03b00x00p10n02i01022arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1022.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p10n02i01022pkg is
procedure check (x: in integer; y: in boolean);
end c06s03b00x00p10n02i01022pkg;
use work.c06s03b00x00p10n02i01022pkg.all;
ENTITY c06s03b00x00p10n02i01022ent IS
END c06s03b00x00p10n02i01022ent;
ARCHITECTURE c06s03b00x00p10n02i01022arch OF c06s03b00x00p10n02i01022ent IS
constant p: integer := 3;
constant q: boolean := true;
BEGIN
TESTING: PROCESS
variable p: integer;
variable q: boolean;
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p10n02i01022 - An expanded name is used outside the named construct."
severity ERROR;
wait;
END PROCESS TESTING;
check (TESTING.p, TESTING.q); -- Failure_here
END c06s03b00x00p10n02i01022arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1022.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p10n02i01022pkg is
procedure check (x: in integer; y: in boolean);
end c06s03b00x00p10n02i01022pkg;
use work.c06s03b00x00p10n02i01022pkg.all;
ENTITY c06s03b00x00p10n02i01022ent IS
END c06s03b00x00p10n02i01022ent;
ARCHITECTURE c06s03b00x00p10n02i01022arch OF c06s03b00x00p10n02i01022ent IS
constant p: integer := 3;
constant q: boolean := true;
BEGIN
TESTING: PROCESS
variable p: integer;
variable q: boolean;
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p10n02i01022 - An expanded name is used outside the named construct."
severity ERROR;
wait;
END PROCESS TESTING;
check (TESTING.p, TESTING.q); -- Failure_here
END c06s03b00x00p10n02i01022arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:46 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_sim_netlist.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0_ov7670_vga is
port (
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 );
active : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_vga_0_0_ov7670_vga : entity is "ov7670_vga";
end system_ov7670_vga_0_0_ov7670_vga;
architecture STRUCTURE of system_ov7670_vga_0_0_ov7670_vga is
signal cycle : STD_LOGIC;
signal \data_pair[15]_i_1_n_0\ : STD_LOGIC;
signal \data_pair[7]_i_1_n_0\ : STD_LOGIC;
signal \data_pair_reg_n_0_[0]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[10]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[11]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[12]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[13]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[14]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[15]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[1]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[2]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[3]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[4]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[5]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[6]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[7]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[8]\ : STD_LOGIC;
signal \data_pair_reg_n_0_[9]\ : STD_LOGIC;
signal rgb_regn_0_0 : STD_LOGIC;
begin
cycle_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_x2,
CE => '1',
D => \data_pair[7]_i_1_n_0\,
Q => cycle,
R => '0'
);
\data_pair[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => cycle,
I1 => active,
O => \data_pair[15]_i_1_n_0\
);
\data_pair[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => active,
I1 => cycle,
O => \data_pair[7]_i_1_n_0\
);
\data_pair_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[0]\,
R => '0'
);
\data_pair_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[10]\,
R => '0'
);
\data_pair_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[11]\,
R => '0'
);
\data_pair_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[12]\,
R => '0'
);
\data_pair_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[13]\,
R => '0'
);
\data_pair_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[14]\,
R => '0'
);
\data_pair_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[15]\,
R => '0'
);
\data_pair_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[1]\,
R => '0'
);
\data_pair_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(2),
Q => \data_pair_reg_n_0_[2]\,
R => '0'
);
\data_pair_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(3),
Q => \data_pair_reg_n_0_[3]\,
R => '0'
);
\data_pair_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(4),
Q => \data_pair_reg_n_0_[4]\,
R => '0'
);
\data_pair_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(5),
Q => \data_pair_reg_n_0_[5]\,
R => '0'
);
\data_pair_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(6),
Q => \data_pair_reg_n_0_[6]\,
R => '0'
);
\data_pair_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[7]_i_1_n_0\,
D => data(7),
Q => \data_pair_reg_n_0_[7]\,
R => '0'
);
\data_pair_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(0),
Q => \data_pair_reg_n_0_[8]\,
R => '0'
);
\data_pair_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_x2,
CE => \data_pair[15]_i_1_n_0\,
D => data(1),
Q => \data_pair_reg_n_0_[9]\,
R => '0'
);
\rgb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[0]\,
Q => rgb(0),
R => '0'
);
\rgb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[10]\,
Q => rgb(10),
R => '0'
);
\rgb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[11]\,
Q => rgb(11),
R => '0'
);
\rgb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[12]\,
Q => rgb(12),
R => '0'
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[13]\,
Q => rgb(13),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[14]\,
Q => rgb(14),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[15]\,
Q => rgb(15),
R => '0'
);
\rgb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[1]\,
Q => rgb(1),
R => '0'
);
\rgb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[2]\,
Q => rgb(2),
R => '0'
);
\rgb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[3]\,
Q => rgb(3),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[4]\,
Q => rgb(4),
R => '0'
);
\rgb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[5]\,
Q => rgb(5),
R => '0'
);
\rgb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[6]\,
Q => rgb(6),
R => '0'
);
\rgb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[7]\,
Q => rgb(7),
R => '0'
);
\rgb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[8]\,
Q => rgb(8),
R => '0'
);
\rgb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => rgb_regn_0_0,
CE => cycle,
D => \data_pair_reg_n_0_[9]\,
Q => rgb(9),
R => '0'
);
rgb_regi_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => clk_x2,
O => rgb_regn_0_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_vga_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_vga_0_0 : entity is "system_ov7670_vga_0_0,ov7670_vga,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_vga_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_vga_0_0 : entity is "ov7670_vga,Vivado 2016.4";
end system_ov7670_vga_0_0;
architecture STRUCTURE of system_ov7670_vga_0_0 is
begin
U0: entity work.system_ov7670_vga_0_0_ov7670_vga
port map (
active => active,
clk_x2 => clk_x2,
data(7 downto 0) => data(7 downto 0),
rgb(15 downto 0) => rgb(15 downto 0)
);
end STRUCTURE;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 17:41:33 10/05/2015
-- Design Name:
-- Module Name: P15_Counters - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: 4 bits counters
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity P15_Counters is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Seg : out STD_LOGIC_VECTOR (7 downto 0);
Disp : out STD_LOGIC_VECTOR (3 downto 0));
end P15_Counters;
architecture Behavioral of P15_Counters is
-- embedded signal for the counter
signal count : STD_LOGIC_VECTOR (3 downto 0);
-- embedded signal used by frequency devider
signal frequency_counter : integer range 0 to 100000000;
signal onehz: STD_LOGIC;
begin
-- define a frequency devider for 100,000,000 to 1
Frequency_devider: process(Rst, Clk)
begin
if(rising_edge(Clk)) then
--check if a counter has reached final value
if(frequency_counter = 100000000) then
frequency_counter <= 1;
onehz <= '1';
else
frequency_counter <= frequency_counter + 1;
onehz <= '0';
end if;
end if;
end process Frequency_devider;
--
----define the binary counter
---- Bad approach a embeeded signal is used as a clock signal. this can crate metastability problem
--Binary_counter: process(Rst, onehz)
--begin
-- --Asynchronouse reset
-- if (Rst = '1') then
-- --fill ccount with zeros using aggregate
-- count <= (others => '0');
-- elsif (rising_edge(onehz)) then
-- count <= count + 1;
-- end if;
--end process Binary_counter;
--define the binary counter
-- good approach use the embedded signal as an enable
Binary_counter: process(Rst, Clk, onehz)
begin
--Asynchronouse reset
if (Rst = '1') then
--fill ccount with zeros using aggregate
count <= (others => '0');
elsif (rising_edge(Clk) and onehz = '1') then
count <= count + 1;
end if;
end process Binary_counter;
-- seven segment decoder
-- C&P 7seg decoder
decodercase: process(count)
VARIABLE bufer: STD_LOGIC_VECTOR (7 downto 0);
begin
case(count) is
when "0000" => bufer:= "11000000";
when "0001" => bufer:= "11111001";
when "0010" => bufer:= "10100100";
when "0011" => bufer:= "10110000";
when "0100" => bufer:= "10011001";
when "0101" => bufer:= "10010010";
when "0110" => bufer:= "10000010";
when "0111" => bufer:= "11111000";
when "1000" => bufer:= "10000000";
when "1001" => bufer:= "10011000";
when "1010" => bufer:= "10001000";
when "1011" => bufer:= "10000011";
when "1100" => bufer:= "11000110";
when "1101" => bufer:= "10100001";
when "1110" => bufer:= "10000110";
when "1111" => bufer:= "10001110";
when others => bufer:= "10111111";
end case;
Seg <= bufer;
end process decodercase;
disp <= "1110";
end Behavioral;
|
--------------------------------------------------------------------------------
-- Title : PCIe simulation model
-- Project : -
--------------------------------------------------------------------------------
-- File : pcie_sim.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2017-05-26
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6
-- Synthesis : -
--------------------------------------------------------------------------------
-- Description :
-- PCIe simulation model for x1, x2, x4 and x8 configurations.
-- The BFM shared memory is configured to be 2 MBytes. It is mapped into
-- the first 2 MBytes of I/O space and also the first 2 MBytes of memory
-- space. The BFM is assigned to device number 0 on internal bus number 0.
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
-- Copyright (C) 2017, MEN Mikro Elektronik Nuremberg GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.altpcietb_bfm_constants.all;
use work.altpcietb_bfm_log.all;
use work.altpcietb_bfm_shmem.all;
use work.altpcietb_bfm_rdwr.all;
use work.altpcietb_bfm_configure.all;
use work.utils_pkg.all;
use work.pcie_sim_pkg.all;
use work.print_pkg.all;
use work.terminal_pkg.all;
entity pcie_sim is
generic(
BFM_LANE_WIDTH : integer range 8 downto 0 := 1 -- set configuration: 1=x1, 2=x2, 4=x4 and 8=x8
);
port(
rst_i : in std_logic;
pcie_rstn_i : in std_logic;
clk_i : in std_logic;
ep_clk250_i : in std_logic; -- endpoint SERDES 250MHz clk output
ep_clk500_i : in std_logic; -- endpoint SERDES 500MHz clk output
-- PCIe lanes
bfm_tx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
bfm_rx_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0);
-- PCIe SERDES connection, in/out references are BFM view
ep_rate_ext_i : in std_logic; -- endpoint rate_ext
ep_powerdown_ext_i : in std_logic_vector(2*BFM_LANE_WIDTH -1 downto 0); -- 2bits per lane, [1:0]=lane0, [3:2]=lane1 etc.
ep_txdatak_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdata_i : in std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_txcompl_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txelecidle_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_txdetectrx_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxpolarity_i : in std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_ltssm_i : in std_logic_vector(4 downto 0);
ep_rxvalid_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_rxstatus_o : out std_logic_vector(3*BFM_LANE_WIDTH -1 downto 0); -- 3bits per lane, [2:0]=lane0, [5:3]=lane1 etc.
ep_rxdatak_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bits per lane, [0]=lane0, [1]=lane1 etc.
ep_rxdata_o : out std_logic_vector(8*BFM_LANE_WIDTH -1 downto 0); -- 8bits per lane, [7:0]=lane0, [15:8]=lane1 etc.
ep_rxelecidle_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
ep_phystatus_o : out std_logic_vector(BFM_LANE_WIDTH -1 downto 0); -- 1bit per lane, [0]=lane0, [1]=lane1 etc.
-- MEN terminal connection, in/out references are terminal view
term_out : in terminal_out_type;
term_in : out terminal_in_type
);
end entity pcie_sim;
architecture pcie_sim_arch of pcie_sim is
type bar_addr_array is array (5 downto 0) of std_logic_vector(31 downto 0);
type bar_limit_array is array (5 downto 0) of natural;
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
component altpcietb_bfm_rp_top_x8_pipen1b is
port(
signal rxdata4_ext : in std_logic_vector(7 downto 0);
signal rx_in7 : in std_logic;
signal phystatus5_ext : in std_logic;
signal rxdata5_ext : in std_logic_vector(7 downto 0);
signal phystatus1_ext : in std_logic;
signal pipe_mode : in std_logic;
signal rxstatus3_ext : in std_logic_vector(2 downto 0);
signal pcie_rstn : in std_logic;
signal rxelecidle7_ext : in std_logic;
signal rxelecidle0_ext : in std_logic;
signal clk500_in : in std_logic;
signal rxelecidle3_ext : in std_logic;
signal rxdatak1_ext : in std_logic;
signal phystatus0_ext : in std_logic;
signal rx_in0 : in std_logic;
signal rx_in5 : in std_logic;
signal rxelecidle5_ext : in std_logic;
signal rxvalid1_ext : in std_logic;
signal rx_in2 : in std_logic;
signal rx_in3 : in std_logic;
signal rxdatak3_ext : in std_logic;
signal clk250_in : in std_logic;
signal phystatus6_ext : in std_logic;
signal rxdata6_ext : in std_logic_vector(7 downto 0);
signal rxdata3_ext : in std_logic_vector(7 downto 0);
signal rxstatus5_ext : in std_logic_vector(2 downto 0);
signal rxstatus1_ext : in std_logic_vector(2 downto 0);
signal rxdata0_ext : in std_logic_vector(7 downto 0);
signal rxvalid7_ext : in std_logic;
signal phystatus7_ext : in std_logic;
signal rxdata2_ext : in std_logic_vector(7 downto 0);
signal rxvalid5_ext : in std_logic;
signal rxvalid0_ext : in std_logic;
signal rxdatak2_ext : in std_logic;
signal rxstatus4_ext : in std_logic_vector(2 downto 0);
signal rxdatak7_ext : in std_logic;
signal rxstatus0_ext : in std_logic_vector(2 downto 0);
signal phystatus3_ext : in std_logic;
signal rxelecidle4_ext : in std_logic;
signal phystatus2_ext : in std_logic;
signal rxvalid4_ext : in std_logic;
signal rx_in6 : in std_logic;
signal rx_in1 : in std_logic;
signal rxstatus2_ext : in std_logic_vector(2 downto 0);
signal rxdata7_ext : in std_logic_vector(7 downto 0);
signal rxdatak0_ext : in std_logic;
signal rxelecidle1_ext : in std_logic;
signal rxdata1_ext : in std_logic_vector(7 downto 0);
signal rxstatus6_ext : in std_logic_vector(2 downto 0);
signal test_in : in std_logic_vector(31 downto 0);
signal rx_in4 : in std_logic;
signal rxdatak4_ext : in std_logic;
signal rxelecidle2_ext : in std_logic;
signal rxdatak5_ext : in std_logic;
signal rxstatus7_ext : in std_logic_vector(2 downto 0);
signal rxelecidle6_ext : in std_logic;
signal rxvalid3_ext : in std_logic;
signal rxvalid2_ext : in std_logic;
signal phystatus4_ext : in std_logic;
signal rxvalid6_ext : in std_logic;
signal local_rstn : in std_logic;
signal rxdatak6_ext : in std_logic;
signal tx_out6 : out std_logic;
signal tx_out4 : out std_logic;
signal txdatak4_ext : out std_logic;
signal txelecidle0_ext : out std_logic;
signal txdatak1_ext : out std_logic;
signal test_out : out std_logic_vector(511 downto 0);
signal txelecidle2_ext : out std_logic;
signal txdatak7_ext : out std_logic;
signal txdatak2_ext : out std_logic;
signal txcompl4_ext : out std_logic;
signal rxpolarity5_ext : out std_logic;
signal rxpolarity4_ext : out std_logic;
signal powerdown7_ext : out std_logic_vector(1 downto 0);
signal txdetectrx7_ext : out std_logic;
signal txelecidle1_ext : out std_logic;
signal tx_out3 : out std_logic;
signal rxpolarity3_ext : out std_logic;
signal txdata0_ext : out std_logic_vector(7 downto 0);
signal txdetectrx1_ext : out std_logic;
signal powerdown0_ext : out std_logic_vector(1 downto 0);
signal txdata1_ext : out std_logic_vector(7 downto 0);
signal txdatak6_ext : out std_logic;
signal txdata3_ext : out std_logic_vector(7 downto 0);
signal txcompl7_ext : out std_logic;
signal txdata4_ext : out std_logic_vector(7 downto 0);
signal powerdown3_ext : out std_logic_vector(1 downto 0);
signal txcompl5_ext : out std_logic;
signal txcompl0_ext : out std_logic;
signal txdetectrx5_ext : out std_logic;
signal txcompl1_ext : out std_logic;
signal powerdown1_ext : out std_logic_vector(1 downto 0);
signal txelecidle7_ext : out std_logic;
signal swdn_out : out std_logic_vector(5 downto 0);
signal txelecidle6_ext : out std_logic;
signal tx_out0 : out std_logic;
signal powerdown6_ext : out std_logic_vector(1 downto 0);
signal rxpolarity0_ext : out std_logic;
signal tx_out2 : out std_logic;
signal txdetectrx2_ext : out std_logic;
signal txdata5_ext : out std_logic_vector(7 downto 0);
signal txelecidle3_ext : out std_logic;
signal txdatak3_ext : out std_logic;
signal txdetectrx0_ext : out std_logic;
signal rxpolarity6_ext : out std_logic;
signal powerdown2_ext : out std_logic_vector(1 downto 0);
signal rate_ext : out std_logic;
signal txcompl3_ext : out std_logic;
signal txdetectrx6_ext : out std_logic;
signal tx_out5 : out std_logic;
signal rxpolarity2_ext : out std_logic;
signal tx_out7 : out std_logic;
signal tx_out1 : out std_logic;
signal txdetectrx3_ext : out std_logic;
signal txdata6_ext : out std_logic_vector(7 downto 0);
signal txcompl2_ext : out std_logic;
signal rxpolarity1_ext : out std_logic;
signal txelecidle4_ext : out std_logic;
signal txdata2_ext : out std_logic_vector(7 downto 0);
signal powerdown4_ext : out std_logic_vector(1 downto 0);
signal txcompl6_ext : out std_logic;
signal txdatak5_ext : out std_logic;
signal txdata7_ext : out std_logic_vector(7 downto 0);
signal txdatak0_ext : out std_logic;
signal rxpolarity7_ext : out std_logic;
signal powerdown5_ext : out std_logic_vector(1 downto 0);
signal txdetectrx4_ext : out std_logic;
signal txelecidle5_ext : out std_logic
);
end component altpcietb_bfm_rp_top_x8_pipen1b;
component altpcietb_pipe_phy is
generic(
APIPE_WIDTH : natural;
BPIPE_WIDTH : natural;
LANE_NUM : natural
);
port(
signal b_powerdown : in std_logic_vector(1 downto 0);
signal a_txdatak : in std_logic_vector(0 downto 0);
signal pipe_mode : in std_logic;
signal a_powerdown : in std_logic_vector(1 downto 0);
signal b_txcompl : in std_logic;
signal b_lane_conn : in std_logic;
signal b_txdetectrx : in std_logic;
signal pclk_a : in std_logic;
signal b_txelecidle : in std_logic;
signal a_lane_conn : in std_logic;
signal resetn : in std_logic;
signal a_txdata : in std_logic_vector(7 downto 0);
signal b_rate : in std_logic;
signal a_txcompl : in std_logic;
signal pclk_b : in std_logic;
signal a_txelecidle : in std_logic;
signal a_txdetectrx : in std_logic;
signal a_rxpolarity : in std_logic;
signal b_txdata : in std_logic_vector(7 downto 0);
signal b_rxpolarity : in std_logic;
signal b_txdatak : in std_logic_vector(0 downto 0);
signal a_rate : in std_logic;
signal a_rxvalid : out std_logic;
signal a_rxstatus : out std_logic_vector(2 downto 0);
signal b_phystatus : out std_logic;
signal b_rxvalid : out std_logic;
signal a_rxdatak : out std_logic_vector(0 downto 0);
signal b_rxelecidle : out std_logic;
signal b_rxdatak : out std_logic_vector(0 downto 0);
signal a_rxdata : out std_logic_vector(7 downto 0);
signal b_rxdata : out std_logic_vector(7 downto 0);
signal a_rxelecidle : out std_logic;
signal a_phystatus : out std_logic;
signal b_rxstatus : out std_logic_vector(2 downto 0)
);
end component altpcietb_pipe_phy;
component altpcietb_ltssm_mon is
port(
signal rp_clk : in std_logic;
signal ep_ltssm : in std_logic_vector (4 downto 0);
signal rstn : in std_logic;
signal rp_ltssm : in std_logic_vector (4 downto 0);
signal dummy_out : out std_logic
);
end component altpcietb_ltssm_mon;
-- +----------------------------------------------------------------------------
-- | functions
-- +----------------------------------------------------------------------------
function get_bar_limit(bar_addr : std_logic_vector(31 downto 0); bar_num : natural)
return natural is
variable var_log2_size : natural;
variable var_is_mem : std_logic;
variable var_is_pref : std_logic;
variable var_is_64b : std_logic;
begin
ebfm_cfg_decode_bar(
bar_table => BAR_TABLE_POINTER,
bar_num => bar_num,
log2_size => var_log2_size,
is_mem => var_is_mem,
is_pref => var_is_pref,
is_64b => var_is_64b
);
return var_log2_size;
end function get_bar_limit;
-- +----------------------------------------------------------------------------
-- | procedures
-- +----------------------------------------------------------------------------
procedure get_pcie_addr_and_offset(
pcie_addr : in std_logic_vector(31 downto 0);
bar_addr : in bar_addr_array;
bar_limit : in bar_limit_array;
bar_num : out natural;
bar_offset : out natural
) is
variable var_act_limit : natural := 0;
variable var_act_addr : std_logic_vector(31 downto 0) := (others => '0');
variable var_act_offset : std_logic_vector(31 downto 0) := (others => '0');
variable var_bar_num : natural := 6;
begin
-- loop through all BARs and check for matches
-- address must match from MSB of address to actual limit value
-- address offset for BAR is from limit downto 0
loop_1 : for i in 0 to 5 loop
var_act_limit := bar_limit(i);
var_act_offset := ZERO_32BIT(31 downto var_act_limit) & pcie_addr(var_act_limit -1 downto 0);
var_act_addr := pcie_addr(31 downto var_act_limit) & ZERO_32BIT(var_act_limit -1 downto 0);
if bar_addr(i) = var_act_addr then
var_bar_num := i;
exit loop_1;
else
-- set to invalid value to denote error condition
var_bar_num := 6;
end if;
end loop;
if var_bar_num = 6 then
report "ERROR (pcie_sim.vhd->get_pcie_addr_and_offset(): given PCIe address does not match stored BAR addresses" severity error;
else
bar_num := var_bar_num;
bar_offset := to_integer(unsigned(var_act_offset));
end if;
end procedure get_pcie_addr_and_offset;
-- +----------------------------------------------------------------------------
-- | constants
-- +----------------------------------------------------------------------------
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
-- BFM connections
signal bfm_rate_int : std_logic;
signal bfm_pipe_mode_int : std_logic;
signal bfm_pclk_int : std_logic;
signal lane_pclk_int : std_logic;
signal bfm_rstn_delayed : std_logic := '0';
signal bfm_txcompl_0_int : std_logic;
signal bfm_txcompl_1_int : std_logic;
signal bfm_txcompl_2_int : std_logic;
signal bfm_txcompl_3_int : std_logic;
signal bfm_txcompl_4_int : std_logic;
signal bfm_txcompl_5_int : std_logic;
signal bfm_txcompl_6_int : std_logic;
signal bfm_txcompl_7_int : std_logic;
signal bfm_txdetectrx_0_int : std_logic;
signal bfm_txdetectrx_1_int : std_logic;
signal bfm_txdetectrx_2_int : std_logic;
signal bfm_txdetectrx_3_int : std_logic;
signal bfm_txdetectrx_4_int : std_logic;
signal bfm_txdetectrx_5_int : std_logic;
signal bfm_txdetectrx_6_int : std_logic;
signal bfm_txdetectrx_7_int : std_logic;
signal bfm_txelecidle_0_int : std_logic;
signal bfm_txelecidle_1_int : std_logic;
signal bfm_txelecidle_2_int : std_logic;
signal bfm_txelecidle_3_int : std_logic;
signal bfm_txelecidle_4_int : std_logic;
signal bfm_txelecidle_5_int : std_logic;
signal bfm_txelecidle_6_int : std_logic;
signal bfm_txelecidle_7_int : std_logic;
signal bfm_rxpolarity_0_int : std_logic;
signal bfm_rxpolarity_1_int : std_logic;
signal bfm_rxpolarity_2_int : std_logic;
signal bfm_rxpolarity_3_int : std_logic;
signal bfm_rxpolarity_4_int : std_logic;
signal bfm_rxpolarity_5_int : std_logic;
signal bfm_rxpolarity_6_int : std_logic;
signal bfm_rxpolarity_7_int : std_logic;
signal bfm_phystatus_0_int : std_logic;
signal bfm_phystatus_1_int : std_logic;
signal bfm_phystatus_2_int : std_logic;
signal bfm_phystatus_3_int : std_logic;
signal bfm_phystatus_4_int : std_logic;
signal bfm_phystatus_5_int : std_logic;
signal bfm_phystatus_6_int : std_logic;
signal bfm_phystatus_7_int : std_logic;
signal bfm_rxvalid_0_int : std_logic;
signal bfm_rxvalid_1_int : std_logic;
signal bfm_rxvalid_2_int : std_logic;
signal bfm_rxvalid_3_int : std_logic;
signal bfm_rxvalid_4_int : std_logic;
signal bfm_rxvalid_5_int : std_logic;
signal bfm_rxvalid_6_int : std_logic;
signal bfm_rxvalid_7_int : std_logic;
signal bfm_rxelecidle_0_int : std_logic;
signal bfm_rxelecidle_1_int : std_logic;
signal bfm_rxelecidle_2_int : std_logic;
signal bfm_rxelecidle_3_int : std_logic;
signal bfm_rxelecidle_4_int : std_logic;
signal bfm_rxelecidle_5_int : std_logic;
signal bfm_rxelecidle_6_int : std_logic;
signal bfm_rxelecidle_7_int : std_logic;
signal bfm_rxdatak_0_int : std_logic;
signal bfm_rxdatak_1_int : std_logic;
signal bfm_rxdatak_2_int : std_logic;
signal bfm_rxdatak_3_int : std_logic;
signal bfm_rxdatak_4_int : std_logic;
signal bfm_rxdatak_5_int : std_logic;
signal bfm_rxdatak_6_int : std_logic;
signal bfm_rxdatak_7_int : std_logic;
signal bfm_rx_int : std_logic_vector(7 downto 0) := (others => '1');
signal bfm_tx_int : std_logic_vector(7 downto 0) := (others => 'Z');
signal bfm_test_in_int : std_logic_vector(31 downto 0);
signal bfm_irq_int : std_logic_vector(5 downto 0);
signal bfm_ltssm_rp : std_logic_vector(4 downto 0);
signal test_out_int : std_logic_vector(511 downto 0);
signal bfm_txdata_0_int : std_logic_vector(7 downto 0);
signal bfm_txdata_1_int : std_logic_vector(7 downto 0);
signal bfm_txdata_2_int : std_logic_vector(7 downto 0);
signal bfm_txdata_3_int : std_logic_vector(7 downto 0);
signal bfm_txdata_4_int : std_logic_vector(7 downto 0);
signal bfm_txdata_5_int : std_logic_vector(7 downto 0);
signal bfm_txdata_6_int : std_logic_vector(7 downto 0);
signal bfm_txdata_7_int : std_logic_vector(7 downto 0);
signal bfm_txdatak_0_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_1_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_2_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_3_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_4_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_5_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_6_int : std_logic_vector(0 downto 0);
signal bfm_txdatak_7_int : std_logic_vector(0 downto 0);
signal bfm_powerdown_0_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_1_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_2_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_3_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_4_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_5_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_6_int : std_logic_vector(1 downto 0);
signal bfm_powerdown_7_int : std_logic_vector(1 downto 0);
signal bfm_rxdata_0_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_1_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_2_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_3_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_4_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_5_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_6_int : std_logic_vector(7 downto 0);
signal bfm_rxdata_7_int : std_logic_vector(7 downto 0);
signal bfm_rxstatus_0_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_1_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_2_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_3_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_4_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_5_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_6_int : std_logic_vector(2 downto 0);
signal bfm_rxstatus_7_int : std_logic_vector(2 downto 0);
signal bar_addr : bar_addr_array;
signal bar_limit : bar_limit_array;
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
assert (BFM_LANE_WIDTH = 1 or BFM_LANE_WIDTH = 2 or BFM_LANE_WIDTH = 4 or BFM_LANE_WIDTH = 8)
report "ERROR (pcie_sim.vhd): invalid value for generic BFM_LANE_WIDTH; use 1, 2, 4, or 8!" severity failure;
-- clock switch
bfm_pclk_int <= ep_clk500_i when bfm_rate_int = '1' else ep_clk250_i;
lane_pclk_int <= ep_clk500_i when ep_rate_ext_i = '1' else ep_clk250_i;
-- delay reset for BFM by 100 ns
bfm_rstn_delayed <= transport pcie_rstn_i after 100 ns;
bfm_pipe_mode_int <= '1';
bfm_test_in_int(31 downto 8) <= (others => '0');
bfm_test_in_int(7) <= not bfm_pipe_mode_int; -- disable entrance to low power mode
bfm_test_in_int(6) <= '0';
bfm_test_in_int(5) <= '1'; -- disable polling.compliance
bfm_test_in_int(4) <= '0';
bfm_test_in_int(3) <= not bfm_pipe_mode_int; -- forces all lanes to detect the receiver
bfm_test_in_int(2 downto 1) <= (others => '0');
bfm_test_in_int(0) <= '1'; -- speed up simulation by making counters faster than normal
bfm_ltssm_rp <= test_out_int(324 downto 320);
bfm_rx_o(BFM_LANE_WIDTH -1 downto 0) <= bfm_rx_int(BFM_LANE_WIDTH -1 downto 0);
bfm_tx_int(BFM_LANE_WIDTH -1 downto 0) <= bfm_tx_i(BFM_LANE_WIDTH -1 downto 0);
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
main : process
variable first_be_en : std_logic_vector(3 downto 0);
variable byte_count : integer;
variable addr32_int : std_logic_vector(31 downto 0);
variable bfm_id : integer := 0;
variable success_int : boolean := false;
variable return_data32 : std_logic_vector(31 downto 0) := (others => '0');
variable return_data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable data_vec : dword_vector(BFM_BUFFER_MAX_SIZE downto 0);
variable var_bar_num : natural;
variable var_bar_offset : natural;
variable var_bar0_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar1_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar2_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar3_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar4_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar5_addr : std_logic_vector(31 downto 0) := x"ffff_ffff";
variable var_bar0_limit : natural := 0;
variable var_bar1_limit : natural := 0;
variable var_bar2_limit : natural := 0;
variable var_bar3_limit : natural := 0;
variable var_bar4_limit : natural := 0;
variable var_bar5_limit : natural := 0;
begin
-- reset all
term_in.busy <= '1';
term_in.done <= true;
wait until rst_i = '0';
wait_clk(clk_i,1);
if term_out.start /= true then
wait until term_out.start = true;
end if;
loop
wait on term_out.start;
term_in.busy <= '1';
term_in.err <= 0;
success_int := false;
---------------------------
-- check for wrong values
---------------------------
assert term_out.typ <= 2 report "ERROR (pcie_sim): illegal value for signal term_out.typ" severity failure;
assert term_out.wr <= 2 report "ERROR (pcie_sim): illegal value for signal term_out.wr" severity failure;
if term_out.typ = 0 then
assert term_out.numb = 1 report "ERROR (pcie_sim): illegal combination for signals term_out.typ and term_out.numb => bytewise burst is impossible" severity failure;
end if;
if term_out.typ = 1 then
assert term_out.numb = 1 report "ERROR (pcie_sim): illegal combination for signals term_out.typ and term_out.numb => wordwise burst is impossible" severity failure;
end if;
assert term_out.numb <= 1024 report "ERROR (pcie_sim): maximum value for signal term_out.numb is 1024" severity failure;
----------------------------
-- set values for this run
----------------------------
addr32_int := term_out.adr(31 downto 2) & "00";
bfm_id := to_integer(unsigned(term_out.tga(3 downto 2)));
if term_out.typ = 0 then -- byte
byte_count := 1;
if term_out.adr(1 downto 0) = "01" then
first_be_en := "0010";
elsif term_out.adr(1 downto 0) = "10" then
first_be_en := "0100";
elsif term_out.adr(1 downto 0) = "11" then
first_be_en := "1000";
else
first_be_en := "0001";
end if;
elsif term_out.typ = 1 then -- word
byte_count := 2;
if term_out.adr(1) = '0' then
first_be_en := "0011";
else
first_be_en := "1100";
end if;
else -- long word
byte_count := term_out.numb *4;
first_be_en := x"F";
end if;
for i in 0 to term_out.numb -1 loop
data_vec(i) := std_logic_vector(unsigned(term_out.dat) + to_unsigned(i,32));
return_data_vec(i) := (others => '0');
wait for 0 ns;
end loop;
if term_out.wr = 0 then -- read
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
report "ERROR(pcie_sim): I/O transfer not supported" severity error;
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
get_pcie_addr_and_offset(
pcie_addr => addr32_int,
bar_addr => bar_addr,
bar_limit => bar_limit,
bar_num => var_bar_num,
bar_offset => var_bar_offset
);
if term_out.numb = 1 then
bfm_rd_mem32(
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_en => first_be_en,
ref_data32 => term_out.dat,
data32_out => return_data32,
success => success_int
);
else
bfm_rd_mem32(
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_count => byte_count,
ref_data32 => data_vec,
data32_out => return_data_vec,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
return_data32 := x"FADE_FADE";
bfm_rd_config(
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
ref_data32 => term_out.dat,
data32_out => return_data32,
success => success_int
);
else
assert false report "ERROR (pcie_sim): term_out.tga(1 downto 0) = 11 is reserved for reads" severity failure;
end if;
elsif term_out.wr = 1 then -- write
if term_out.tga(1 downto 0) = IO_TRANSFER then -- I/O
report "ERROR(pcie_sim): I/O transfer not supported" severity error;
elsif term_out.tga(1 downto 0) = MEM32_TRANSFER then -- memory
get_pcie_addr_and_offset(
pcie_addr => term_out.adr,
bar_addr => bar_addr,
bar_limit => bar_limit,
bar_num => var_bar_num,
bar_offset => var_bar_offset
);
if term_out.numb = 1 then
bfm_wr_mem32(
pcie_addr => term_out.adr(1 downto 0),
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_count => byte_count,
data32 => term_out.dat,
success => success_int
);
else
bfm_wr_mem32(
bar_num => var_bar_num,
bar_offset => var_bar_offset,
byte_count => byte_count,
data32 => data_vec,
success => success_int
);
end if;
elsif term_out.tga(1 downto 0) = CONFIG_TRANSFER then -- configuration type 0
bfm_wr_config(
byte_en => first_be_en,
pcie_addr => addr32_int(31 downto 2),
data32 => term_out.dat,
success => success_int
);
else
-- => term_out.tga(1 downto 0) = SETUP_CYCLE then -- BFM setup
if term_out.txt >= 2 then
print("pcie_sim.vhd: starting SETUP_CYCLE");
end if;
if term_out.adr(2 downto 0) = "000" then -- BAR0
var_bar0_addr := term_out.dat;
var_bar0_limit := get_bar_limit(bar_addr => var_bar0_addr, bar_num => 0);
bar_addr(0) <= var_bar0_addr;
bar_limit(0) <= var_bar0_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "001" then -- BAR1
var_bar1_addr := term_out.dat;
var_bar1_limit := get_bar_limit(bar_addr => var_bar1_addr, bar_num => 1);
bar_addr(1) <= var_bar1_addr;
bar_limit(1) <= var_bar1_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "010" then -- BAR2
var_bar2_addr := term_out.dat;
var_bar2_limit := get_bar_limit(bar_addr => var_bar2_addr, bar_num => 2);
bar_addr(2) <= var_bar2_addr;
bar_limit(2) <= var_bar2_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "011" then -- BAR3
var_bar3_addr := term_out.dat;
var_bar3_limit := get_bar_limit(bar_addr => var_bar3_addr, bar_num => 3);
bar_addr(3) <= var_bar3_addr;
bar_limit(3) <= var_bar3_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "100" then -- BAR4
var_bar4_addr := term_out.dat;
var_bar4_limit := get_bar_limit(bar_addr => var_bar4_addr, bar_num => 4);
bar_addr(4) <= var_bar4_addr;
bar_limit(4) <= var_bar4_limit;
success_int := true;
elsif term_out.adr(2 downto 0) = "101" then -- BAR5
var_bar5_addr := term_out.dat;
var_bar5_limit := get_bar_limit(bar_addr => var_bar5_addr, bar_num => 5);
bar_addr(5) <= var_bar5_addr;
bar_limit(5) <= var_bar5_limit;
success_int := true;
else
report "ERROR: pcie_sim.vhd: term_out.tga is set to SETUP_CYCLE but term_out.adr has an invalid value!" &
" Use values 000 to 101." severity error;
end if;
wait_clk(clk_i,1);
end if;
else -- wait
wait_clk(clk_i,term_out.numb);
end if;
--------------------------------------
-- return values and finish transfer
--------------------------------------
term_in.dat <= return_data32;
if success_int then
term_in.err <= 0;
else
term_in.err <= 1;
end if;
term_in.busy <= '0';
term_in.done <= term_out.start;
end loop;
end process main;
-- +----------------------------------------------------------------------------
-- | component instanciation section
-- +----------------------------------------------------------------------------
bfm_inst: altpcietb_bfm_rp_top_x8_pipen1b
port map(
pcie_rstn => bfm_rstn_delayed, --pcie_rstn_i,
local_rstn => '1',
clk250_in => ep_clk250_i,
clk500_in => ep_clk500_i,
pipe_mode => bfm_pipe_mode_int,
rxdata4_ext => bfm_rxdata_4_int,
rx_in7 => bfm_rx_int(7),
phystatus5_ext => bfm_phystatus_5_int,
rxdata5_ext => bfm_rxdata_5_int,
phystatus1_ext => bfm_phystatus_1_int,
rxstatus3_ext => bfm_rxstatus_3_int,
rxelecidle7_ext => bfm_rxelecidle_7_int,
rxelecidle0_ext => bfm_rxelecidle_0_int,
rxelecidle3_ext => bfm_rxelecidle_3_int,
rxdatak1_ext => bfm_rxdatak_1_int,
phystatus0_ext => bfm_phystatus_0_int,
rx_in0 => bfm_rx_int(0),
rx_in5 => bfm_rx_int(5),
rxelecidle5_ext => bfm_rxelecidle_5_int,
rxvalid1_ext => bfm_rxvalid_1_int,
rx_in2 => bfm_rx_int(2),
rx_in3 => bfm_rx_int(3),
rxdatak3_ext => bfm_rxdatak_3_int,
phystatus6_ext => bfm_phystatus_6_int,
rxdata6_ext => bfm_rxdata_6_int,
rxdata3_ext => bfm_rxdata_3_int,
rxstatus5_ext => bfm_rxstatus_5_int,
rxstatus1_ext => bfm_rxstatus_1_int,
rxdata0_ext => bfm_rxdata_0_int,
rxvalid7_ext => bfm_rxvalid_7_int,
phystatus7_ext => bfm_phystatus_7_int,
rxdata2_ext => bfm_rxdata_2_int,
rxvalid5_ext => bfm_rxvalid_5_int,
rxvalid0_ext => bfm_rxvalid_0_int,
rxdatak2_ext => bfm_rxdatak_2_int,
rxstatus4_ext => bfm_rxstatus_4_int,
rxdatak7_ext => bfm_rxdatak_7_int,
rxstatus0_ext => bfm_rxstatus_0_int,
phystatus3_ext => bfm_phystatus_3_int,
rxelecidle4_ext => bfm_rxelecidle_4_int,
phystatus2_ext => bfm_phystatus_2_int,
rxvalid4_ext => bfm_rxvalid_4_int,
rx_in6 => bfm_rx_int(6),
rx_in1 => bfm_rx_int(1),
rxstatus2_ext => bfm_rxstatus_2_int,
rxdata7_ext => bfm_rxdata_7_int,
rxdatak0_ext => bfm_rxdatak_0_int,
rxelecidle1_ext => bfm_rxelecidle_1_int,
rxdata1_ext => bfm_rxdata_1_int,
rxstatus6_ext => bfm_rxstatus_6_int,
test_in => bfm_test_in_int,
rx_in4 => bfm_rx_int(4),
rxdatak4_ext => bfm_rxdatak_4_int,
rxelecidle2_ext => bfm_rxelecidle_2_int,
rxdatak5_ext => bfm_rxdatak_5_int,
rxstatus7_ext => bfm_rxstatus_7_int,
rxelecidle6_ext => bfm_rxelecidle_6_int,
rxvalid3_ext => bfm_rxvalid_3_int,
rxvalid2_ext => bfm_rxvalid_2_int,
phystatus4_ext => bfm_phystatus_4_int,
rxvalid6_ext => bfm_rxvalid_6_int,
rxdatak6_ext => bfm_rxdatak_6_int,
tx_out6 => bfm_tx_int(6),
tx_out4 => bfm_tx_int(4),
txdatak4_ext => bfm_txdatak_4_int(0),
txelecidle0_ext => bfm_txelecidle_0_int,
txdatak1_ext => bfm_txdatak_1_int(0),
test_out => test_out_int,
txelecidle2_ext => bfm_txelecidle_2_int,
txdatak7_ext => bfm_txdatak_7_int(0),
txdatak2_ext => bfm_txdatak_2_int(0),
txcompl4_ext => bfm_txcompl_4_int,
rxpolarity5_ext => bfm_rxpolarity_5_int,
rxpolarity4_ext => bfm_rxpolarity_4_int,
powerdown7_ext => bfm_powerdown_7_int,
txdetectrx7_ext => bfm_txdetectrx_7_int,
txelecidle1_ext => bfm_txelecidle_1_int,
tx_out3 => bfm_tx_int(3),
rxpolarity3_ext => bfm_rxpolarity_3_int,
txdata0_ext => bfm_txdata_0_int,
txdetectrx1_ext => bfm_txdetectrx_1_int,
powerdown0_ext => bfm_powerdown_0_int,
txdata1_ext => bfm_txdata_1_int,
txdatak6_ext => bfm_txdatak_6_int(0),
txdata3_ext => bfm_txdata_3_int,
txcompl7_ext => bfm_txcompl_7_int,
txdata4_ext => bfm_txdata_4_int,
powerdown3_ext => bfm_powerdown_3_int,
txcompl5_ext => bfm_txcompl_5_int,
txcompl0_ext => bfm_txcompl_0_int,
txdetectrx5_ext => bfm_txdetectrx_5_int,
txcompl1_ext => bfm_txcompl_1_int,
powerdown1_ext => bfm_powerdown_1_int,
txelecidle7_ext => bfm_txelecidle_7_int,
swdn_out => bfm_irq_int,
txelecidle6_ext => bfm_txelecidle_6_int,
tx_out0 => bfm_tx_int(0),
powerdown6_ext => bfm_powerdown_6_int,
rxpolarity0_ext => bfm_rxpolarity_0_int,
tx_out2 => bfm_tx_int(2),
txdetectrx2_ext => bfm_txdetectrx_2_int,
txdata5_ext => bfm_txdata_5_int,
txelecidle3_ext => bfm_txelecidle_3_int,
txdatak3_ext => bfm_txdatak_3_int(0),
txdetectrx0_ext => bfm_txdetectrx_0_int,
rxpolarity6_ext => bfm_rxpolarity_6_int,
powerdown2_ext => bfm_powerdown_2_int,
rate_ext => bfm_rate_int,
txcompl3_ext => bfm_txcompl_3_int,
txdetectrx6_ext => bfm_txdetectrx_6_int,
tx_out5 => bfm_tx_int(5),
rxpolarity2_ext => bfm_rxpolarity_2_int,
tx_out7 => bfm_tx_int(7),
tx_out1 => bfm_tx_int(1),
txdetectrx3_ext => bfm_txdetectrx_3_int,
txdata6_ext => bfm_txdata_6_int,
txcompl2_ext => bfm_txcompl_2_int,
rxpolarity1_ext => bfm_rxpolarity_1_int,
txelecidle4_ext => bfm_txelecidle_4_int,
txdata2_ext => bfm_txdata_2_int,
powerdown4_ext => bfm_powerdown_4_int,
txcompl6_ext => bfm_txcompl_6_int,
txdatak5_ext => bfm_txdatak_5_int(0),
txdata7_ext => bfm_txdata_7_int,
txdatak0_ext => bfm_txdatak_0_int(0),
rxpolarity7_ext => bfm_rxpolarity_7_int,
powerdown5_ext => bfm_powerdown_5_int,
txdetectrx4_ext => bfm_txdetectrx_4_int,
txelecidle5_ext => bfm_txelecidle_5_int
);
----------------------
-- use LTSSM monitor
----------------------
ltssm_mon : altpcietb_ltssm_mon
port map(
ep_ltssm => ep_ltssm_i,
rp_clk => bfm_pclk_int,
rp_ltssm => bfm_ltssm_rp,
rstn => pcie_rstn_i,
dummy_out => open
);
------------------------
-- manage unused lanes
------------------------
--manage_lanes: if BFM_LANE_WIDTH = 1 generate
manage_x1_lanes: if BFM_LANE_WIDTH = 1 generate
-- x1 configuration, BFM connected with 1 lane, using dummy transceiver for lanes 2 to 8
x1_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x1_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_1_int,
b_txcompl => bfm_txcompl_1_int,
b_txdetectrx => bfm_txdetectrx_1_int,
b_txelecidle => bfm_txelecidle_1_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_1_int,
b_rxpolarity => bfm_rxpolarity_1_int,
b_txdatak => bfm_txdatak_1_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_1_int,
b_rxvalid => bfm_rxvalid_1_int,
b_rxelecidle => bfm_rxelecidle_1_int,
b_rxdatak(0) => bfm_rxdatak_1_int,
b_rxdata => bfm_rxdata_1_int,
b_rxstatus => bfm_rxstatus_1_int
);
x1_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_2_int,
b_txcompl => bfm_txcompl_2_int,
b_txdetectrx => bfm_txdetectrx_2_int,
b_txelecidle => bfm_txelecidle_2_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_2_int,
b_rxpolarity => bfm_rxpolarity_2_int,
b_txdatak => bfm_txdatak_2_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_2_int,
b_rxvalid => bfm_rxvalid_2_int,
b_rxelecidle => bfm_rxelecidle_2_int,
b_rxdatak(0) => bfm_rxdatak_2_int,
b_rxdata => bfm_rxdata_2_int,
b_rxstatus => bfm_rxstatus_2_int
);
x1_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_3_int,
b_txcompl => bfm_txcompl_3_int,
b_txdetectrx => bfm_txdetectrx_3_int,
b_txelecidle => bfm_txelecidle_3_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_3_int,
b_rxpolarity => bfm_rxpolarity_3_int,
b_txdatak => bfm_txdatak_3_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_3_int,
b_rxvalid => bfm_rxvalid_3_int,
b_rxelecidle => bfm_rxelecidle_3_int,
b_rxdatak(0) => bfm_rxdatak_3_int,
b_rxdata => bfm_rxdata_3_int,
b_rxstatus => bfm_rxstatus_3_int
);
x1_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x1_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x1_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x1_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
end generate manage_x1_lanes;
--elsif BFM_LANE_WIDTH = 2 generate
manage_x2_lanes : if BFM_LANE_WIDTH = 2 generate
-- x2 configuration, BFM connected with 2 lanes, using dummy transceiver for lanes 3 to 8
x2_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x2_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(3 downto 2),
a_txdatak(0) => ep_txdatak_i(1),
a_txdata => ep_txdata_i(15 downto 8),
a_txcompl => ep_txcompl_i(1),
a_txelecidle => ep_txelecidle_i(1),
a_txdetectrx => ep_txdetectrx_i(1),
a_rxpolarity => ep_rxpolarity_i(1),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(1),
a_rxstatus => ep_rxstatus_o(5 downto 3),
a_rxdatak(0) => ep_rxdatak_o(1),
a_rxdata => ep_rxdata_o(15 downto 8),
a_rxelecidle => ep_rxelecidle_o(1),
a_phystatus => ep_phystatus_o(1),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x2_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_2_int,
b_txcompl => bfm_txcompl_2_int,
b_txdetectrx => bfm_txdetectrx_2_int,
b_txelecidle => bfm_txelecidle_2_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_2_int,
b_rxpolarity => bfm_rxpolarity_2_int,
b_txdatak => bfm_txdatak_2_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_2_int,
b_rxvalid => bfm_rxvalid_2_int,
b_rxelecidle => bfm_rxelecidle_2_int,
b_rxdatak(0) => bfm_rxdatak_2_int,
b_rxdata => bfm_rxdata_2_int,
b_rxstatus => bfm_rxstatus_2_int
);
x2_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_3_int,
b_txcompl => bfm_txcompl_3_int,
b_txdetectrx => bfm_txdetectrx_3_int,
b_txelecidle => bfm_txelecidle_3_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_3_int,
b_rxpolarity => bfm_rxpolarity_3_int,
b_txdatak => bfm_txdatak_3_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_3_int,
b_rxvalid => bfm_rxvalid_3_int,
b_rxelecidle => bfm_rxelecidle_3_int,
b_rxdatak(0) => bfm_rxdatak_3_int,
b_rxdata => bfm_rxdata_3_int,
b_rxstatus => bfm_rxstatus_3_int
);
x2_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x2_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x2_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x2_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
end generate manage_x2_lanes;
--elsif BFM_LANE_WIDTH = 4 generate
manage_x4_lanes: if BFM_LANE_WIDTH = 4 generate
-- x4 configuration, BFM connected with 4 lanes, using dummy transceiver for lanes 5 to 8
x4_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(3 downto 2),
a_txdatak(0) => ep_txdatak_i(1),
a_txdata => ep_txdata_i(15 downto 8),
a_txcompl => ep_txcompl_i(1),
a_txelecidle => ep_txelecidle_i(1),
a_txdetectrx => ep_txdetectrx_i(1),
a_rxpolarity => ep_rxpolarity_i(1),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(1),
a_rxstatus => ep_rxstatus_o(5 downto 3),
a_rxdatak(0) => ep_rxdatak_o(1),
a_rxdata => ep_rxdata_o(15 downto 8),
a_rxelecidle => ep_rxelecidle_o(1),
a_phystatus => ep_phystatus_o(1),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(5 downto 4),
a_txdatak(0) => ep_txdatak_i(2),
a_txdata => ep_txdata_i(23 downto 16),
a_txcompl => ep_txcompl_i(2),
a_txelecidle => ep_txelecidle_i(2),
a_txdetectrx => ep_txdetectrx_i(2),
a_rxpolarity => ep_rxpolarity_i(2),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(2),
a_rxstatus => ep_rxstatus_o(8 downto 6),
a_rxdatak(0) => ep_rxdatak_o(2),
a_rxdata => ep_rxdata_o(23 downto 16),
a_rxelecidle => ep_rxelecidle_o(2),
a_phystatus => ep_phystatus_o(2),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(7 downto 6),
a_txdatak(0) => ep_txdatak_i(3),
a_txdata => ep_txdata_i(31 downto 24),
a_txcompl => ep_txcompl_i(3),
a_txelecidle => ep_txelecidle_i(3),
a_txdetectrx => ep_txdetectrx_i(3),
a_rxpolarity => ep_rxpolarity_i(3),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(3),
a_rxstatus => ep_rxstatus_o(11 downto 9),
a_rxdatak(0) => ep_rxdatak_o(3),
a_rxdata => ep_rxdata_o(31 downto 24),
a_rxelecidle => ep_rxelecidle_o(3),
a_phystatus => ep_phystatus_o(3),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x4_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x4_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x4_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x4_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '0', -- nothing connected on side A
a_rate => '0',
a_powerdown => (others => '0'),
a_txdatak => (others => '0'),
a_txdata => (others => '0'),
a_txcompl => '0',
a_txelecidle => '0',
a_txdetectrx => '0',
a_rxpolarity => '0',
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => open,
a_rxstatus => open,
a_rxdatak => open,
a_rxdata => open,
a_rxelecidle => open,
a_phystatus => open,
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
end generate manage_x4_lanes;
--else generate
manage_x8_lanes: if BFM_LANE_WIDTH = 8 generate
-- x8 configuration, BFM connected with maximum lanes, no dummy transceiver necessary
x8_lane_0 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 0
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(1 downto 0),
a_txdatak(0) => ep_txdatak_i(0),
a_txdata => ep_txdata_i(7 downto 0),
a_txcompl => ep_txcompl_i(0),
a_txelecidle => ep_txelecidle_i(0),
a_txdetectrx => ep_txdetectrx_i(0),
a_rxpolarity => ep_rxpolarity_i(0),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(0),
a_rxstatus => ep_rxstatus_o(2 downto 0),
a_rxdatak(0) => ep_rxdatak_o(0),
a_rxdata => ep_rxdata_o(7 downto 0),
a_rxelecidle => ep_rxelecidle_o(0),
a_phystatus => ep_phystatus_o(0),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_1 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 1
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(3 downto 2),
a_txdatak(0) => ep_txdatak_i(1),
a_txdata => ep_txdata_i(15 downto 8),
a_txcompl => ep_txcompl_i(1),
a_txelecidle => ep_txelecidle_i(1),
a_txdetectrx => ep_txdetectrx_i(1),
a_rxpolarity => ep_rxpolarity_i(1),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(1),
a_rxstatus => ep_rxstatus_o(5 downto 3),
a_rxdatak(0) => ep_rxdatak_o(1),
a_rxdata => ep_rxdata_o(15 downto 8),
a_rxelecidle => ep_rxelecidle_o(1),
a_phystatus => ep_phystatus_o(1),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_2 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 2
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(5 downto 4),
a_txdatak(0) => ep_txdatak_i(2),
a_txdata => ep_txdata_i(23 downto 16),
a_txcompl => ep_txcompl_i(2),
a_txelecidle => ep_txelecidle_i(2),
a_txdetectrx => ep_txdetectrx_i(2),
a_rxpolarity => ep_rxpolarity_i(2),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(2),
a_rxstatus => ep_rxstatus_o(8 downto 6),
a_rxdatak(0) => ep_rxdatak_o(2),
a_rxdata => ep_rxdata_o(23 downto 16),
a_rxelecidle => ep_rxelecidle_o(2),
a_phystatus => ep_phystatus_o(2),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_3 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 3
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(7 downto 6),
a_txdatak(0) => ep_txdatak_i(3),
a_txdata => ep_txdata_i(31 downto 24),
a_txcompl => ep_txcompl_i(3),
a_txelecidle => ep_txelecidle_i(3),
a_txdetectrx => ep_txdetectrx_i(3),
a_rxpolarity => ep_rxpolarity_i(3),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_0_int,
b_txcompl => bfm_txcompl_0_int,
b_txdetectrx => bfm_txdetectrx_0_int,
b_txelecidle => bfm_txelecidle_0_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_0_int,
b_rxpolarity => bfm_rxpolarity_0_int,
b_txdatak => bfm_txdatak_0_int,
a_rxvalid => ep_rxvalid_o(3),
a_rxstatus => ep_rxstatus_o(11 downto 9),
a_rxdatak(0) => ep_rxdatak_o(3),
a_rxdata => ep_rxdata_o(31 downto 24),
a_rxelecidle => ep_rxelecidle_o(3),
a_phystatus => ep_phystatus_o(3),
b_phystatus => bfm_phystatus_0_int,
b_rxvalid => bfm_rxvalid_0_int,
b_rxelecidle => bfm_rxelecidle_0_int,
b_rxdatak(0) => bfm_rxdatak_0_int,
b_rxdata => bfm_rxdata_0_int,
b_rxstatus => bfm_rxstatus_0_int
);
x8_lane_4 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 4
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(9 downto 8),
a_txdatak(0) => ep_txdatak_i(4),
a_txdata => ep_txdata_i(39 downto 32),
a_txcompl => ep_txcompl_i(4),
a_txelecidle => ep_txelecidle_i(4),
a_txdetectrx => ep_txdetectrx_i(4),
a_rxpolarity => ep_rxpolarity_i(4),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_4_int,
b_txcompl => bfm_txcompl_4_int,
b_txdetectrx => bfm_txdetectrx_4_int,
b_txelecidle => bfm_txelecidle_4_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_4_int,
b_rxpolarity => bfm_rxpolarity_4_int,
b_txdatak => bfm_txdatak_4_int,
a_rxvalid => ep_rxvalid_o(4),
a_rxstatus => ep_rxstatus_o(14 downto 12),
a_rxdatak(0) => ep_rxdatak_o(4),
a_rxdata => ep_rxdata_o(39 downto 32),
a_rxelecidle => ep_rxelecidle_o(4),
a_phystatus => ep_phystatus_o(4),
b_phystatus => bfm_phystatus_4_int,
b_rxvalid => bfm_rxvalid_4_int,
b_rxelecidle => bfm_rxelecidle_4_int,
b_rxdatak(0) => bfm_rxdatak_4_int,
b_rxdata => bfm_rxdata_4_int,
b_rxstatus => bfm_rxstatus_4_int
);
x8_lane_5 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 5
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(11 downto 10),
a_txdatak(0) => ep_txdatak_i(5),
a_txdata => ep_txdata_i(47 downto 40),
a_txcompl => ep_txcompl_i(5),
a_txelecidle => ep_txelecidle_i(5),
a_txdetectrx => ep_txdetectrx_i(5),
a_rxpolarity => ep_rxpolarity_i(5),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_5_int,
b_txcompl => bfm_txcompl_5_int,
b_txdetectrx => bfm_txdetectrx_5_int,
b_txelecidle => bfm_txelecidle_5_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_5_int,
b_rxpolarity => bfm_rxpolarity_5_int,
b_txdatak => bfm_txdatak_5_int,
a_rxvalid => ep_rxvalid_o(5),
a_rxstatus => ep_rxstatus_o(17 downto 15),
a_rxdatak(0) => ep_rxdatak_o(5),
a_rxdata => ep_rxdata_o(47 downto 40),
a_rxelecidle => ep_rxelecidle_o(5),
a_phystatus => ep_phystatus_o(5),
b_phystatus => bfm_phystatus_5_int,
b_rxvalid => bfm_rxvalid_5_int,
b_rxelecidle => bfm_rxelecidle_5_int,
b_rxdatak(0) => bfm_rxdatak_5_int,
b_rxdata => bfm_rxdata_5_int,
b_rxstatus => bfm_rxstatus_5_int
);
x8_lane_6 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 6
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(13 downto 12),
a_txdatak(0) => ep_txdatak_i(6),
a_txdata => ep_txdata_i(55 downto 48),
a_txcompl => ep_txcompl_i(6),
a_txelecidle => ep_txelecidle_i(6),
a_txdetectrx => ep_txdetectrx_i(6),
a_rxpolarity => ep_rxpolarity_i(6),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_6_int,
b_txcompl => bfm_txcompl_6_int,
b_txdetectrx => bfm_txdetectrx_6_int,
b_txelecidle => bfm_txelecidle_6_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_6_int,
b_rxpolarity => bfm_rxpolarity_6_int,
b_txdatak => bfm_txdatak_6_int,
a_rxvalid => ep_rxvalid_o(6),
a_rxstatus => ep_rxstatus_o(20 downto 18),
a_rxdatak(0) => ep_rxdatak_o(6),
a_rxdata => ep_rxdata_o(55 downto 48),
a_rxelecidle => ep_rxelecidle_o(6),
a_phystatus => ep_phystatus_o(6),
b_phystatus => bfm_phystatus_6_int,
b_rxvalid => bfm_rxvalid_6_int,
b_rxelecidle => bfm_rxelecidle_6_int,
b_rxdatak(0) => bfm_rxdatak_6_int,
b_rxdata => bfm_rxdata_6_int,
b_rxstatus => bfm_rxstatus_6_int
);
x8_lane_7 : altpcietb_pipe_phy
generic map(
APIPE_WIDTH => 8,
BPIPE_WIDTH => 8,
LANE_NUM => 7
)
port map(
resetn => pcie_rstn_i,
pclk_a => lane_pclk_int,
pclk_b => bfm_pclk_int,
pipe_mode => bfm_pipe_mode_int,
a_lane_conn => '1', -- endpoint connected on side A
a_rate => ep_rate_ext_i,
a_powerdown => ep_powerdown_ext_i(15 downto 14),
a_txdatak(0) => ep_txdatak_i(7),
a_txdata => ep_txdata_i(63 downto 56),
a_txcompl => ep_txcompl_i(7),
a_txelecidle => ep_txelecidle_i(7),
a_txdetectrx => ep_txdetectrx_i(7),
a_rxpolarity => ep_rxpolarity_i(7),
b_lane_conn => '1', -- BFM connected on side B
b_powerdown => bfm_powerdown_7_int,
b_txcompl => bfm_txcompl_7_int,
b_txdetectrx => bfm_txdetectrx_7_int,
b_txelecidle => bfm_txelecidle_7_int,
b_rate => bfm_rate_int,
b_txdata => bfm_txdata_7_int,
b_rxpolarity => bfm_rxpolarity_7_int,
b_txdatak => bfm_txdatak_7_int,
a_rxvalid => ep_rxvalid_o(7),
a_rxstatus => ep_rxstatus_o(23 downto 21),
a_rxdatak(0) => ep_rxdatak_o(7),
a_rxdata => ep_rxdata_o(63 downto 56),
a_rxelecidle => ep_rxelecidle_o(7),
a_phystatus => ep_phystatus_o(7),
b_phystatus => bfm_phystatus_7_int,
b_rxvalid => bfm_rxvalid_7_int,
b_rxelecidle => bfm_rxelecidle_7_int,
b_rxdatak(0) => bfm_rxdatak_7_int,
b_rxdata => bfm_rxdata_7_int,
b_rxstatus => bfm_rxstatus_7_int
);
--end generate manage_lanes;
end generate manage_x8_lanes;
end architecture pcie_sim_arch;
|
<<<<<<< HEAD
--Test bench for i2c interface
--by: Jie (Jack) Zhang MWL-MIT
=======
--------------------------------------------------------------------------------
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
<<<<<<< HEAD
=======
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
ENTITY TB_i2c IS
END TB_i2c;
ARCHITECTURE behavior OF TB_i2c IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2c_master
generic(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 500_000); --speed the i2c bus (scl) will run at in Hz
port(
clk : IN std_logic;
reset : IN std_logic;
ena : IN std_logic;
devid : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --device id of target slave
addr : IN std_logic_vector(7 downto 0);
rw : IN std_logic;
data_wr : IN std_logic_vector(7 downto 0);
busy : OUT std_logic;
data_rd : OUT std_logic_vector(7 downto 0);
ack_error : BUFFER std_logic;
<<<<<<< HEAD
rd_from_remote : in std_logic;
=======
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
sda : INOUT std_logic;
scl : INOUT std_logic
);
END COMPONENT;
--slave device
component i2c_slave is
generic(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
<<<<<<< HEAD
bus_clk : INTEGER := 500_000; --speed the i2c bus (scl) will run at in Hz
ID : std_logic_vector(6 downto 0) := "1010101"); --Device specific ID
=======
bus_clk : INTEGER := 500_000); --speed the i2c bus (scl) will run at in Hz
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
port (
clk : IN STD_LOGIC; --system clock
reset : IN STD_LOGIC; --active high reset
sda : INOUT STD_LOGIC; --serial data i2c bus
scl : INOUT STD_LOGIC; --serial clock i2c bus
wr_enb : out std_logic; --0: write to slave 1: read from slave
rd_enb : out std_logic;
addrout : out std_logic_vector(7 downto 0);
regin : in std_logic_vector(7 downto 0); --register values to send through i2c
regout : out std_logic_vector(7 downto 0)
);
end component;
<<<<<<< HEAD
component i2c_master_init is
port(
clk : in std_logic; --same clock for the i2c interface
reset : in std_logic;
busy : in std_logic;
ack_error : in std_logic;
i2c_ena_o : out std_logic;
rw_o : out std_logic;
device_id_o : out std_logic_vector(6 downto 0);
addr_o : out std_logic_vector(7 downto 0);
value_o : out std_logic_vector(7 downto 0);
user_rw : in std_logic;
user_device_id : in std_logic_vector(6 downto 0);
user_addr : in std_logic_vector(7 downto 0);
user_value : in std_logic_vector(7 downto 0)
);
end component;
=======
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal ena : std_logic := '0';
signal devid : std_logic_vector(6 downto 0) := (others => '0');
signal addr : std_logic_vector(7 downto 0) := (others => '0');
signal rw : std_logic := '0';
signal data_wr : std_logic_vector(7 downto 0) := (others => '0');
signal wr_enb : std_logic; --0: write to slave 1: read from slave
signal rd_enb : std_logic;
signal addrout : std_logic_vector(7 downto 0);
signal regin : std_logic_vector(7 downto 0); --register values to send through i2c
signal regout : std_logic_vector(7 downto 0);
--BiDirs
signal sda : std_logic;
signal scl : std_logic;
--Outputs
signal busy : std_logic;
signal data_rd : std_logic_vector(7 downto 0);
signal ack_error : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut_i2c_master: i2c_master PORT MAP (
clk => clk,
reset => reset,
ena => ena,
devid => devid,
addr => addr,
rw => rw,
data_wr => data_wr,
busy => busy,
data_rd => data_rd,
ack_error => ack_error,
<<<<<<< HEAD
rd_from_remote => '0',
=======
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
sda => sda,
scl => scl
);
-- slave module
<<<<<<< HEAD
uut_i2c_slave_des : i2c_slave generic map (
ID => "1100000"
)port map (
clk => clk,
reset => reset, --active high reset
sda => sda, --serial data i2c bus
scl => scl, --serial clock i2c bus
wr_enb => wr_enb,
rd_enb => rd_enb,
addrout => open,
regin => "10111001",
regout => open
);
uut_i2c_slave_ser : i2c_slave generic map (
ID => "1011000"
)port map (
clk => clk,
reset => reset, --active high reset
sda => sda, --serial data i2c bus
scl => scl, --serial clock i2c bus
wr_enb => wr_enb,
rd_enb => rd_enb,
addrout => open,
regin => regin,
regout => open
);
uut_i2c_slave_remote : i2c_slave generic map (
ID => "1010000"
)port map (
=======
uut_i2c_slave : i2c_slave port map (
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
clk => clk,
reset => reset, --active high reset
sda => sda, --serial data i2c bus
scl => scl, --serial clock i2c bus
wr_enb => wr_enb,
rd_enb => rd_enb,
addrout => addrout,
<<<<<<< HEAD
regin => "10111001",
regout => regout
);
control_init : i2c_master_init port map(
clk => clk,
reset => reset,
busy => busy,
ack_error => ack_error,
i2c_ena_o => ena,
rw_o => rw,
device_id_o => devid,
addr_o => addr,
value_o => data_wr,
user_rw => '1',
user_device_id => "1010000",
user_addr => "00110110",
user_value => "01110100"
);
=======
regin => regin,
regout => regout
);
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
scl <= 'H';
sda <= 'H';
reset <= '1';
<<<<<<< HEAD
wait for 100 ns;
reset <= '0';
regin <= "10101100";
wait for clk_period*10;
wait for clk_period*100;
-- insert stimulus here
wait for 200 us;
scl <= '0';
wait for 200 us;
scl <= 'H';
=======
addr <= "11001011";
devid <= "1010101";
data_wr <= "01011100";
ena <= '0';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
ena <= '1';
wait for clk_period*100;
ena <= '0';
-- insert stimulus here
>>>>>>> 9e62c29c2a11e27a321e2c4a2c9d40dc76aee79c
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.1
-- \ \ Application : xaw2vhdl
-- / / Filename : clk_gen.vhd
-- /___/ /\ Timestamp : 10/18/2012 18:56:08
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st /home/chris/makestuff/hdl/apps/readback/vhdl/s3board/./clk_gen.xaw /home/chris/makestuff/hdl/apps/readback/vhdl/s3board/./clk_gen
--Design Name: clk_gen
--Device: xc3s200-4ft256
--
-- Module clk_gen
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity clk_gen is
port ( clk_in : in std_logic;
clk000_out : out std_logic;
clk180_out : out std_logic;
locked_out : out std_logic);
end clk_gen;
architecture BEHAVIORAL of clk_gen is
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal CLK180_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
clk000_out <= CLKFB_IN;
CLKIN_IBUFG_INST : IBUFG
port map (I=>clk_in,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
CLK180_BUFG_INST : BUFG
port map (I=>CLK180_BUF,
O=>clk180_out);
DCM_INST : DCM
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.833,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"8080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>CLK180_BUF,
CLK270=>open,
LOCKED=>locked_out,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to SGMII interface
------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This is the top level vhdl example design for the
-- Ethernet 1000BASE-X PCS/PMA core.
--
-- This design example instantiates IOB flip-flops
-- and input/output buffers on the GMII.
--
-- A Transmitter Elastic Buffer is instantiated on the Tx
-- GMII path to perform clock compenstation between the
-- core and the external MAC driving the Tx GMII.
--
-- This design example can be synthesised.
--
--
--
-- ----------------------------------------------------------------
-- | Example Design |
-- | |
-- | ---------------------------------------------- |
-- | | Core Block (wrapper) | |
-- | | | |
-- | | -------------- -------------- | |
-- | | | Core | | tranceiver | | |
-- | | | | | | | |
-- | --------- | | | | | | |
-- | | | | | | | | | |
-- | | Tx | | | | | | | |
-- ---->|Elastic|----->| GMII |--------->| TXP |--------->
-- | |Buffer | | | Tx | | TXN | | |
-- | | | | | | | | | |
-- | --------- | | | | | | |
-- | GMII | | | | | | |
-- | IOBs | | | | | | |
-- | | | | | | | |
-- | | | GMII | | RXP | | |
-- <-------------------| Rx |<---------| RXN |<---------
-- | | | | | | | |
-- | | -------------- -------------- | |
-- | | | |
-- | ---------------------------------------------- |
-- | |
-- ----------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library eth;
use eth.grethpkg.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example design
--------------------------------------------------------------------------------
entity sgmii_vc707 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
abits : integer := 8;
autonegotiation : integer := 1;
pirq : integer := 0;
debugmem : integer := 0;
tech : integer := 0;
simulation : integer := 0
);
port(
-- Tranceiver Interface
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
-- GMII Interface (client MAC <=> PCS)
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- Asynchronous reset for entire core.
reset : in std_logic;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end sgmii_vc707;
architecture top_level of sgmii_vc707 is
------------------------------------------------------------------------------
-- Component Declaration for the Core Block (core wrapper).
------------------------------------------------------------------------------
component sgmii
port(
-- Transceiver Interface
------------------------
gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver
gtrefclk_bufg : in std_logic;
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
cplllock : out std_logic;
mmcm_reset : out std_logic;
txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
rxoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
userclk : in std_logic; -- 62.5MHz clock.
userclk2 : in std_logic; -- 125MHz clock.
rxuserclk : in std_logic; -- 125MHz clock.
rxuserclk2 : in std_logic; -- 125MHz clock.
independent_clock_bufg : in std_logic;
pma_reset : in std_logic; -- transceiver PMA reset signal
mmcm_locked : in std_logic; -- Locked signal from MMCM
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: MDIO Interface
-----------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutclk_in : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutrefclk_in : in std_logic -- Input from PMD to indicate presence of optical input.
);
end component;
component MMCME2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
--CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
--CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
--CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
--CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
--CLKOUT3_USE_FINE_PS : boolean := FALSE;
--CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
--CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
--CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
--CLKOUT6_USE_FINE_PS : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
--SS_EN : string := "FALSE";
SS_MODE : string := "CENTER_HIGH";
SS_MOD_PERIOD : integer := 10000
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
----- component IBUFDS_GTE2 -----
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
----- component BUFHCE -----
component BUFHCE
generic (
CE_TYPE : string := "SYNC";
INIT_OUT : integer := 0
);
port (
O : out std_ulogic;
CE : in std_ulogic;
I : in std_ulogic
);
end component;
----- component BUFGMUX -----
component BUFGMUX
generic (
CLK_SEL_TYPE : string := "ASYNC"
);
port (
O : out std_ulogic := '0';
I0 : in std_ulogic := '0';
I1 : in std_ulogic := '0';
S : in std_ulogic := '0'
);
end component;
----- component ODDR -----
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type sgmiiregs is record
irq : std_logic_vector(31 downto 0); -- interrupt
mask : std_logic_vector(31 downto 0); -- interrupt enable
configuration_vector : std_logic_vector( 4 downto 0);
an_adv_config_vector : std_logic_vector(15 downto 0);
end record;
-- APB and RGMII control register
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES_configuration_vector : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(autonegotiation,1)) & "0000";
constant RES : sgmiiregs :=
( irq => (others => '0'), mask => (others => '0'),
configuration_vector => RES_configuration_vector, an_adv_config_vector => "0001100000000001");
type rxregs is record
gmii_rxd : std_logic_vector(7 downto 0);
gmii_rxd_int : std_logic_vector(7 downto 0);
gmii_rx_dv : std_logic;
gmii_rx_er : std_logic;
count : integer;
gmii_dv : std_logic;
keepalive : integer;
end record;
constant RESRX : rxregs :=
( gmii_rxd => (others => '0'), gmii_rxd_int => (others => '0'),
gmii_rx_dv => '0', gmii_rx_er => '0',
count => 0, gmii_dv => '0', keepalive => 0
);
type txregs is record
gmii_txd : std_logic_vector(7 downto 0);
gmii_txd_int : std_logic_vector(7 downto 0);
gmii_tx_en : std_logic;
gmii_tx_en_int : std_logic;
gmii_tx_er : std_logic;
count : integer;
cnt_en : std_logic;
keepalive : integer;
end record;
constant RESTX : txregs :=
( gmii_txd => (others => '0'), gmii_txd_int => (others => '0'),
gmii_tx_en => '0', gmii_tx_en_int => '0', gmii_tx_er => '0',
count => 0, cnt_en => '0', keepalive => 0
);
------------------------------------------------------------------------------
-- internal signals used in this top level example design.
------------------------------------------------------------------------------
-- clock generation signals for tranceiver
signal gtrefclk : std_logic;
signal txoutclk : std_logic;
signal rxoutclk : std_logic;
signal resetdone : std_logic;
signal mmcm_locked : std_logic;
signal mmcm_reset : std_logic;
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal userclk : std_logic;
signal userclk2 : std_logic;
signal rxuserclk : std_logic;
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0);
signal pma_reset : std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic;
signal sgmii_clk_f : std_logic;
signal sgmii_clk_en : std_logic;
-- GMII signals
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal gmii_isolate : std_logic;
-- Internal GMII signals from Xilinx SGMII block
signal gmii_rxd_int : std_logic_vector(7 downto 0);
signal gmii_rx_dv_int : std_logic;
signal gmii_rx_er_int : std_logic;
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal status_vector_apb : std_logic_vector(15 downto 0);
signal status_vector_apb1 : std_logic_vector(31 downto 0);
signal status_vector_apb2 : std_logic_vector(31 downto 0);
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
-- Configuration register
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal configuration_vector : std_logic_vector(4 downto 0);
signal an_interrupt : std_logic;
signal an_adv_config_vector : std_logic_vector(15 downto 0);
signal an_restart_config : std_logic;
signal link_timer_value : std_logic_vector(8 downto 0);
signal synchronization_done : std_logic;
signal linkup : std_logic;
signal signal_detect : std_logic;
-- Route gtrefclk through an IBUFG.
signal gtrefclk_buf_i : std_logic;
signal r, rin : sgmiiregs;
signal rrx,rinrx : rxregs;
signal rtx, rintx : txregs;
signal cnt_en : std_logic;
signal usr2rstn : std_logic;
-- debug signal
signal WMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioWrEn : std_logic;
signal WMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiWrEn : std_logic;
signal RMemRgmiiiRead : std_logic;
signal RMemRgmiioRead : std_logic;
begin
-----------------------------------------------------------------------------
-- Default for VC707
-----------------------------------------------------------------------------
-- Remove AN during simulation i.e. "00000"
configuration_vector <= "10000" when (autonegotiation = 1) else "00000";
-- Configuration for Xilinx SGMII IP. See doc for SGMII IP for more information
an_adv_config_vector <= "0001100000000001";
an_restart_config <= '0';
link_timer_value <= "000110010";
-- Core Status vector outputs
synchronization_done <= status_vector_int(1);
linkup <= status_vector_int(0);
signal_detect <= '1';
gmiii.gtx_clk <= userclk2;
gmiii.tx_clk <= userclk2;
gmiii.rx_clk <= userclk2;
gmiii.rmii_clk <= userclk2;
gmiii.rxd <= gmii_rxd;
gmiii.rx_dv <= gmii_rx_dv;
gmiii.rx_er <= gmii_rx_er;
gmiii.rx_en <= gmii_rx_dv or sgmii_clk_en;
--gmiii.tx_dv <= '1';
gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1';
-- GMII output controlled via generics
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
-- Not used
gmiii.rx_col <= '0';
gmiii.rx_crs <= '0';
gmiii.tx_clk_90 <= '0';
sgmiio.mdio_o <= gmiio.mdio_o;
sgmiio.mdio_oe <= gmiio.mdio_oe;
gmiii.mdio_i <= sgmiii.mdio_i;
sgmiio.mdc <= gmiio.mdc;
gmiii.mdint <= sgmiii.mdint;
sgmiio.reset <= apb_rstn;
-----------------------------------------------------------------------------
-- Transceiver Clock Management
-----------------------------------------------------------------------------
sgmii1 : if simulation = 1 generate
end generate;
sgmii0 : if simulation = 0 generate
-- Clock circuitry for the GT Transceiver uses a differential input clock.
-- gtrefclk is routed to the tranceiver.
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => sgmiii.clkp,
IB => sgmiii.clkn,
CEB => '0',
O => gtrefclk_buf_i,
ODIV2 => open
);
bufhce_gtrefclk : BUFHCE
port map (
I => gtrefclk_buf_i,
CE => '1',
O => gtrefclk
);
-- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
-- routed to an MMCM module where it is used to create phase and frequency
-- related 62.5MHz and 125MHz clock sources
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
--CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
-- STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_PHASE => 0.000,
--CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.5,
--CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.5,
--CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => open,
CLKOUT0 => clkout0,
CLKOUT0B => open,
CLKOUT1 => clkout1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => txoutclk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => mmcm_reset);
--mmcm_reset <= reset or (not resetdone);
mmcm_reset <= reset;
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_userclk: BUFG
port map (
I => clkout1,
O => userclk
);
-- This 125MHz clock is placed onto global clock routing and is then used
-- to clock all Ethernet core logic.
bufg_userclk2: BUFG
port map (
I => clkout0,
O => userclk2
);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_rxuserclk: BUFG
port map (
I => rxoutclk,
O => rxuserclk
);
end generate;
-----------------------------------------------------------------------------
-- Sync Reset for user clock
-----------------------------------------------------------------------------
userclk2_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(apb_rstn, userclk2, '1', usr2rstn, open);
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(reset, apb_clk)
begin
if (reset = '1') then
pma_reset_pipe <= "1111";
elsif apb_clk'event and apb_clk = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
------------------------------------------------------------------------------
-- GMII (Aeroflex Gaisler) to GMII (Xilinx) style
------------------------------------------------------------------------------
-- 10/100Mbit TX Loic
process (usr2rstn,rtx,gmiio)
variable v : txregs;
begin
v := rtx;
v.cnt_en := '0';
v.gmii_tx_en_int := gmiio.tx_en;
if (gmiio.tx_en = '1' and rtx.gmii_tx_en_int = '0') then
v.count := 0;
elsif (v.count >= 9) and gmiio.speed = '1' then
v.count := 0;
elsif (v.count >= 99) and gmiio.speed = '0' then
v.count := 0;
else
v.count := rtx.count + 1;
end if;
case v.count is
when 0 =>
v.gmii_txd_int(3 downto 0) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
when 5 =>
if gmiio.speed = '1' then
v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
end if;
when 50=>
if gmiio.speed = '0' then
v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
end if;
when 9 =>
if gmiio.speed = '1' then
v.gmii_txd := v.gmii_txd_int;
v.gmii_tx_en := '1';
v.gmii_tx_er := gmiio.tx_er;
if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if;
if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if;
end if;
when 99 =>
if gmiio.speed = '0' then
v.gmii_txd := v.gmii_txd_int;
v.gmii_tx_en := '1';
v.gmii_tx_er := gmiio.tx_er;
if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if;
if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if;
end if;
when others =>
null;
end case;
if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '1') then
v.keepalive := 2;
end if;
if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '0' and rtx.keepalive = 0) then
v := RESTX;
end if;
-- reset operation
if (not RESET_ALL) and (usr2rstn = '0') then
v := RESTX;
end if;
-- update registers
rintx <= v;
end process;
txegs : process(userclk2)
begin
if rising_edge(userclk2) then
rtx <= rintx;
if RESET_ALL and usr2rstn = '0' then
rtx <= RESTX;
end if;
end if;
end process;
-- 1000Mbit TX Logic (Bypass)
-- n/a
-- TX Mux Select
cnt_en <= '1' when (gmiio.gbit = '1') else rtx.cnt_en;
gmii_txd <= gmiio.txd when (gmiio.gbit = '1') else rtx.gmii_txd;
gmii_tx_en <= gmiio.tx_en when (gmiio.gbit = '1') else rtx.gmii_tx_en;
gmii_tx_er <= gmiio.tx_er when (gmiio.gbit = '1') else rtx.gmii_tx_er;
------------------------------------------------------------------------------
-- Instantiate the Core Block (core wrapper).
------------------------------------------------------------------------------
speed_is_10_100 <= not gmiio.gbit;
speed_is_100 <= gmiio.speed;
core_wrapper : sgmii
port map (
gtrefclk => gtrefclk,
gtrefclk_bufg => gtrefclk,
txp => sgmiio.txp,
txn => sgmiio.txn,
rxp => sgmiii.rxp,
rxn => sgmiii.rxn,
resetdone => resetdone,
cplllock => OPEN ,
mmcm_reset => OPEN ,
txoutclk => txoutclk,
rxoutclk => rxoutclk ,
userclk => userclk,
userclk2 => userclk2,
rxuserclk => rxuserclk ,
rxuserclk2 => rxuserclk ,
independent_clock_bufg => apb_clk,
pma_reset => pma_reset,
mmcm_locked => mmcm_locked,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => sgmii_clk_en,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => configuration_vector,
an_interrupt => an_interrupt,
an_adv_config_vector => an_adv_config_vector,
an_restart_config => an_restart_config,
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
status_vector => status_vector_int,
reset => reset,
signal_detect => signal_detect,
gt0_qplloutclk_in => '0',
gt0_qplloutrefclk_in => '0'
);
------------------------------------------------------------------------------
-- GMII (Xilinx) to GMII (Aeroflex Gailers) style
------------------------------------------------------------------------------
---- 10/100Mbit RX Loic
process (usr2rstn,rrx,gmii_rx_dv_int,gmii_rxd_int,gmii_rx_er_int,sgmii_clk_en)
variable v : rxregs;
begin
v := rrx;
if (gmii_rx_dv_int = '1' and sgmii_clk_en = '1') then
v.count := 0;
v.gmii_rxd_int := gmii_rxd_int;
v.gmii_dv := '1';
v.keepalive := 1;
elsif (v.count >= 9) and gmiio.speed = '1' then
v.count := 0;
v.keepalive := rrx.keepalive - 1;
elsif (v.count >= 99) and gmiio.speed = '0' then
v.count := 0;
v.keepalive := rrx.keepalive - 1;
else
v.count := rrx.count + 1;
end if;
case v.count is
when 0 =>
v.gmii_rxd := v.gmii_rxd_int(3 downto 0) & v.gmii_rxd_int(3 downto 0);
v.gmii_rx_dv := v.gmii_dv;
when 5 =>
if gmiio.speed = '1' then
v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4);
v.gmii_rx_dv := v.gmii_dv;
v.gmii_dv := '0';
end if;
when 50 =>
if gmiio.speed = '0' then
v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4);
v.gmii_rx_dv := v.gmii_dv;
v.gmii_dv := '0';
end if;
when others =>
v.gmii_rxd := v.gmii_rxd;
v.gmii_rx_dv := '0';
end case;
v.gmii_rx_er := gmii_rx_er_int;
if (rrx.keepalive = 0 and gmii_rx_dv_int = '0') then
v := RESRX;
end if;
-- reset operation
if (not RESET_ALL) and (usr2rstn = '0') then
v := RESRX;
end if;
-- update registers
rinrx <= v;
end process;
rx100regs : process(userclk2)
begin
if rising_edge(userclk2) then
rrx <= rinrx;
if RESET_ALL and usr2rstn = '0' then
rrx <= RESRX;
end if;
end if;
end process;
---- 1000Mbit RX Logic (Bypass)
-- n/a
---- RX Mux Select
gmii_rxd <= gmii_rxd_int when (gmiio.gbit = '1') else rinrx.gmii_rxd;
gmii_rx_dv <= gmii_rx_dv_int when (gmiio.gbit = '1') else rinrx.gmii_rx_dv;
gmii_rx_er <= gmii_rx_er_int when (gmiio.gbit = '1') else rinrx.gmii_rx_er;
-----------------------------------------------------------------------------
-- Extra registers to ease CDC placement
-----------------------------------------------------------------------------
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb <= status_vector_int;
end if;
end process;
---------------------------------------------------------------------------------------
-- APB Section
---------------------------------------------------------------------------------------
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- Extra registers to ease CDC placement
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb1 <= (others => '0');
status_vector_apb2 <= (others => '0');
-- Register to detect a speed change
status_vector_apb1(15 downto 0) <= status_vector_apb;
status_vector_apb2 <= status_vector_apb1;
end if;
end process;
rgmiiapb : process(apb_rstn, r, apbi, status_vector_apb1, status_vector_apb2, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead )
variable rdata : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : sgmiiregs;
begin
v := r;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
rdata := (others => '0');
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(31 downto 0) := status_vector_apb2;
when "000001" =>
rdata(31 downto 0) := r.irq;
v.irq := (others => '0'); -- Interrupt is clear on read
when "000010" =>
rdata(31 downto 0) := r.mask;
when "000011" =>
rdata(4 downto 0) := r.configuration_vector;
when "000100" =>
rdata(15 downto 0) := r.an_adv_config_vector;
when "000101" =>
if (autonegotiation /= 0) then rdata(0) := '1'; else rdata(0) := '0'; end if;
if (debugmem /= 0) then rdata(1) := '1'; else rdata(1) := '0'; end if;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
null;
when "000001" =>
null;
when "000010" =>
v.mask := apbi.pwdata(31 downto 0);
when "000011" =>
v.configuration_vector := apbi.pwdata(4 downto 0);
when "000100" =>
v.an_adv_config_vector := apbi.pwdata(15 downto 0);
when "000101" =>
null;
when others =>
null;
end case;
end if;
-- Check interrupts
for i in 0 to status_vector_apb2'length-1 loop
if ((status_vector_apb1(i) xor status_vector_apb2(i)) and v.mask(i)) = '1' then
v.irq(i) := '1';
end if;
end loop;
-- reset operation
if (not RESET_ALL) and (apb_rstn = '0') then
v := RES;
end if;
-- update registers
rin <= v;
-- drive outputs
if apbi.psel(pindex) = '0' then
apbo.prdata <= (others => '0');
elsif RMemRgmiiiRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiiiData;
elsif RMemRgmiioRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiioData;
else
apbo.prdata <= rdata;
end if;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= orv(v.irq);
end process;
regs : process(apb_clk)
begin
if rising_edge(apb_clk) then
r <= rin;
if RESET_ALL and apb_rstn = '0' then
r <= RES;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- Debug Mem
---------------------------------------------------------------------------------------
debugmem1 : if (debugmem /= 0) generate
-- Write GMII IN data
process (userclk2)
begin -- process
if rising_edge(userclk2) then
WMemRgmiioData(15 downto 0) <= '0' & '0' & '0' & sgmii_clk_en & '0' & '0' & gmii_tx_er & gmii_tx_en & gmii_txd;
if (gmii_tx_en = '1') and ((WMemRgmiioAddr < "0111111110") or (WMemRgmiioAddr = "1111111111")) then
WMemRgmiioAddr <= WMemRgmiioAddr + 1;
WMemRgmiioWrEn <= '1';
else
if (gmii_tx_en = '0') then
WMemRgmiioAddr <= (others => '1');
else
WMemRgmiioAddr <= WMemRgmiioAddr;
end if;
WMemRgmiioWrEn <= '0';
end if;
if usr2rstn = '0' then
WMemRgmiioAddr <= (others => '0');
WMemRgmiioWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiioRead <= apbi.paddr(10) and apbi.psel(pindex);
RMemRgmiioAddr <= "00" & apbi.paddr(10-1 downto 2);
gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData,
userclk2, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData);
-- Write GMII IN data
process (userclk2)
begin -- process
if rising_edge(userclk2) then
if (gmii_rx_dv = '1') then
WMemRgmiiiData(15 downto 0) <= '0' & '0' & '0' &sgmii_clk_en & "00" & gmii_rx_er & gmii_rx_dv & gmii_rxd;
elsif (gmii_rx_dv_int = '0') then
WMemRgmiiiData(15 downto 0) <= (others => '0');
else
WMemRgmiiiData <= WMemRgmiiiData;
end if;
if (gmii_rx_dv = '1') and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then
WMemRgmiiiAddr <= WMemRgmiiiAddr + 1;
WMemRgmiiiWrEn <= '1';
else
if (gmii_rx_dv_int = '0') then
WMemRgmiiiAddr <= (others => '1');
WMemRgmiiiWrEn <= '0';
else
WMemRgmiiiAddr <= WMemRgmiiiAddr;
WMemRgmiiiWrEn <= '0';
end if;
end if;
if usr2rstn = '0' then
WMemRgmiiiAddr <= (others => '0');
WMemRgmiiiWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiiiRead <= apbi.paddr(11) and apbi.psel(pindex);
RMemRgmiiiAddr <= "00" & apbi.paddr(10-1 downto 2);
rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData,
userclk2, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sgmii" & tost(pindex) &
": SGMII rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end top_level;
|
-- $Id: slvtypes.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: slvtypes
-- Description: Short names for std_logic types.
-- This package simply defines short hands for the std_logic
-- types. slbit and slv are just aliases for std_logic and
-- std_logic_vector. slv<n> are subtype definitions for
-- commonly used (n downto 0) vectors
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-08-24 162 1.0.4 add slv60 and 64
-- 2008-08-22 161 1.0.3 add slvnn_m subtypes from pdp11 package
-- 2008-03-24 129 1.0.2 add slv31
-- 2007-12-08 100 1.0.1 add slv1
-- 2007-06-02 44 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package slvtypes is
subtype slbit is std_logic; -- bit
subtype slv is std_logic_vector; -- vector
subtype slv1 is std_logic_vector( 0 downto 0); -- 1 bit word
subtype slv2 is std_logic_vector( 1 downto 0); -- 2 bit word
subtype slv3 is std_logic_vector( 2 downto 0); -- 3 bit word
subtype slv4 is std_logic_vector( 3 downto 0); -- 4 bit word
subtype slv5 is std_logic_vector( 4 downto 0); -- 5 bit word
subtype slv6 is std_logic_vector( 5 downto 0); -- 6 bit word
subtype slv7 is std_logic_vector( 6 downto 0); -- 7 bit word
subtype slv8 is std_logic_vector( 7 downto 0); -- 8 bit word
subtype slv9 is std_logic_vector( 8 downto 0); -- 9 bit word
subtype slv10 is std_logic_vector( 9 downto 0); -- 10 bit word
subtype slv11 is std_logic_vector(10 downto 0); -- 11 bit word
subtype slv12 is std_logic_vector(11 downto 0); -- 12 bit word
subtype slv13 is std_logic_vector(12 downto 0); -- 13 bit word
subtype slv14 is std_logic_vector(13 downto 0); -- 14 bit word
subtype slv15 is std_logic_vector(14 downto 0); -- 15 bit word
subtype slv16 is std_logic_vector(15 downto 0); -- 16 bit word
subtype slv17 is std_logic_vector(16 downto 0); -- 17 bit word
subtype slv18 is std_logic_vector(17 downto 0); -- 18 bit word
subtype slv19 is std_logic_vector(18 downto 0); -- 19 bit word
subtype slv20 is std_logic_vector(19 downto 0); -- 20 bit word
subtype slv21 is std_logic_vector(20 downto 0); -- 21 bit word
subtype slv22 is std_logic_vector(21 downto 0); -- 22 bit word
subtype slv23 is std_logic_vector(22 downto 0); -- 23 bit word
subtype slv24 is std_logic_vector(23 downto 0); -- 24 bit word
subtype slv31 is std_logic_vector(30 downto 0); -- 31 bit word
subtype slv32 is std_logic_vector(31 downto 0); -- 32 bit word
subtype slv60 is std_logic_vector(59 downto 0); -- 59 bit word
subtype slv64 is std_logic_vector(63 downto 0); -- 63 bit word
subtype slv8_1 is std_logic_vector(7 downto 1); -- 8 bit word, 1 lsb drop
subtype slv9_2 is std_logic_vector(8 downto 2); -- 9 bit word, 2 lsb drop
subtype slv13_1 is std_logic_vector(12 downto 1); -- 13 bit word, 1 lsb drop
subtype slv16_1 is std_logic_vector(15 downto 1); -- 16 bit word, 1 lsb drop
subtype slv18_1 is std_logic_vector(17 downto 1); -- 18 bit word, 1 lsb drop
subtype slv22_1 is std_logic_vector(21 downto 1); -- 22 bit word, 1 lsb drop
end package slvtypes;
|
-- $Id: slvtypes.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: slvtypes
-- Description: Short names for std_logic types.
-- This package simply defines short hands for the std_logic
-- types. slbit and slv are just aliases for std_logic and
-- std_logic_vector. slv<n> are subtype definitions for
-- commonly used (n downto 0) vectors
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2008-08-24 162 1.0.4 add slv60 and 64
-- 2008-08-22 161 1.0.3 add slvnn_m subtypes from pdp11 package
-- 2008-03-24 129 1.0.2 add slv31
-- 2007-12-08 100 1.0.1 add slv1
-- 2007-06-02 44 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package slvtypes is
subtype slbit is std_logic; -- bit
subtype slv is std_logic_vector; -- vector
subtype slv1 is std_logic_vector( 0 downto 0); -- 1 bit word
subtype slv2 is std_logic_vector( 1 downto 0); -- 2 bit word
subtype slv3 is std_logic_vector( 2 downto 0); -- 3 bit word
subtype slv4 is std_logic_vector( 3 downto 0); -- 4 bit word
subtype slv5 is std_logic_vector( 4 downto 0); -- 5 bit word
subtype slv6 is std_logic_vector( 5 downto 0); -- 6 bit word
subtype slv7 is std_logic_vector( 6 downto 0); -- 7 bit word
subtype slv8 is std_logic_vector( 7 downto 0); -- 8 bit word
subtype slv9 is std_logic_vector( 8 downto 0); -- 9 bit word
subtype slv10 is std_logic_vector( 9 downto 0); -- 10 bit word
subtype slv11 is std_logic_vector(10 downto 0); -- 11 bit word
subtype slv12 is std_logic_vector(11 downto 0); -- 12 bit word
subtype slv13 is std_logic_vector(12 downto 0); -- 13 bit word
subtype slv14 is std_logic_vector(13 downto 0); -- 14 bit word
subtype slv15 is std_logic_vector(14 downto 0); -- 15 bit word
subtype slv16 is std_logic_vector(15 downto 0); -- 16 bit word
subtype slv17 is std_logic_vector(16 downto 0); -- 17 bit word
subtype slv18 is std_logic_vector(17 downto 0); -- 18 bit word
subtype slv19 is std_logic_vector(18 downto 0); -- 19 bit word
subtype slv20 is std_logic_vector(19 downto 0); -- 20 bit word
subtype slv21 is std_logic_vector(20 downto 0); -- 21 bit word
subtype slv22 is std_logic_vector(21 downto 0); -- 22 bit word
subtype slv23 is std_logic_vector(22 downto 0); -- 23 bit word
subtype slv24 is std_logic_vector(23 downto 0); -- 24 bit word
subtype slv31 is std_logic_vector(30 downto 0); -- 31 bit word
subtype slv32 is std_logic_vector(31 downto 0); -- 32 bit word
subtype slv60 is std_logic_vector(59 downto 0); -- 59 bit word
subtype slv64 is std_logic_vector(63 downto 0); -- 63 bit word
subtype slv8_1 is std_logic_vector(7 downto 1); -- 8 bit word, 1 lsb drop
subtype slv9_2 is std_logic_vector(8 downto 2); -- 9 bit word, 2 lsb drop
subtype slv13_1 is std_logic_vector(12 downto 1); -- 13 bit word, 1 lsb drop
subtype slv16_1 is std_logic_vector(15 downto 1); -- 16 bit word, 1 lsb drop
subtype slv18_1 is std_logic_vector(17 downto 1); -- 18 bit word, 1 lsb drop
subtype slv22_1 is std_logic_vector(21 downto 1); -- 22 bit word, 1 lsb drop
end package slvtypes;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part2 IS
PORT(
BUTTONS : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LED : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
DISP: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
clk_in : IN STD_LOGIC
);
END part2;
ARCHITECTURE Behaviour of part2 IS
SIGNAL s_m: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL HOLD_LOW, s_z : STD_LOGIC;
SIGNAL s_ao, s_ai: STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL HEX_0, HEX_1, BLANK: STD_LOGIC_VECTOR (6 DOWNTO 0);
COMPONENT circuita PORT ( INPUT : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
OUTPUT : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); END COMPONENT;
COMPONENT segseven PORT ( SW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT circuitb PORT ( SW : IN STD_LOGIC;
LEDSEG : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); END COMPONENT;
COMPONENT comparator PORT ( INPUT : IN STD_LOGIC_VECTOR (3 DOWNTO 0); OUTPUT : OUT STD_LOGIC ); END COMPONENT;
COMPONENT mplex PORT ( V : IN STD_LOGIC_VECTOR (1 DOWNTO 0); M : OUT STD_LOGIC; Z : IN STD_LOGIC ); END COMPONENT;
COMPONENT DE1_disp PORT ( HEX0, HEX1, HEX2, HEX3 : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
clk : IN STD_LOGIC;
HEX : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
DISPn: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT;
BEGIN
HOLD_LOW <='0';
BLANK <= "1111111";
S0 : segseven PORT MAP (SW=>s_m, LEDSEG=>HEX_0);
S1 : circuitb PORT MAP (SW=>s_z, LEDSEG=>HEX_1);
DE1: DE1_disp PORT MAP (HEX0=>HEX_0, HEX1=>HEX_1, HEX2=>BLANK, HEX3=>BLANK, clk=>clk_in,HEX=>LED,DISPn=>DISP);
C0 : comparator PORT MAP (INPUT=>BUTTONS,OUTPUT=>s_z);
C1 : circuita PORT MAP (INPUT(2)=>BUTTONS(2),INPUT(1)=>BUTTONS(1),INPUT(0)=>BUTTONS(0),OUTPUT=>s_ao);
M3 : mplex PORT MAP (V(0) =>BUTTONS(3), V(1)=> HOLD_LOW, M=>s_m(3), Z=>s_z);
M2 : mplex PORT MAP (V(0) =>BUTTONS(2), V(1)=> s_ao(2), M=>s_m(2), Z=>s_z);
M1 : mplex PORT MAP (V(0) =>BUTTONS(1), V(1)=> s_ao(1), M=>s_m(1), Z=>s_z);
M0 : mplex PORT MAP (V(0) =>BUTTONS(0), V(1)=> s_ao(0), M=>s_m(0), Z=>s_z);
END Behaviour; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2249.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02249ent IS
END c07s02b06x00p01n01i02249ent;
ARCHITECTURE c07s02b06x00p01n01i02249arch OF c07s02b06x00p01n01i02249ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
type WORDPTR is access WORD;
variable WORDPTRV,
WORDPTR2V: WORDPTR;
variable k : integer;
BEGIN
k := WORDPTRV mod WORDPTR2V;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02249 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02249arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2249.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02249ent IS
END c07s02b06x00p01n01i02249ent;
ARCHITECTURE c07s02b06x00p01n01i02249arch OF c07s02b06x00p01n01i02249ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
type WORDPTR is access WORD;
variable WORDPTRV,
WORDPTR2V: WORDPTR;
variable k : integer;
BEGIN
k := WORDPTRV mod WORDPTR2V;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02249 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02249arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2249.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02249ent IS
END c07s02b06x00p01n01i02249ent;
ARCHITECTURE c07s02b06x00p01n01i02249arch OF c07s02b06x00p01n01i02249ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
type WORDPTR is access WORD;
variable WORDPTRV,
WORDPTR2V: WORDPTR;
variable k : integer;
BEGIN
k := WORDPTRV mod WORDPTR2V;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02249 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02249arch;
|
package vital1 is
TYPE VitalTransitionType IS ( tr01, tr10, tr0z, trz1, tr1z, trz0,
tr0X, trx1, tr1x, trx0, trxz, trzx);
SUBTYPE VitalDelayType IS TIME;
TYPE VitalDelayType01 IS ARRAY (VitalTransitionType RANGE tr01 to tr10)
OF TIME; -- OK
end package;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 37
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 37
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity proc_common_v3_00_a.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
|
-- VHDL que verifica se o caractere eh valido
library ieee;
use ieee.std_logic_1164.all;
entity valida_caractere is
port(
caractere : in std_logic_vector(6 downto 0);
caractere_valido : out std_logic
);
end valida_caractere;
architecture estrutural of valida_caractere is
signal sinal_caractere_valido: std_logic := '0';
begin
process (caractere)
begin
case caractere is
when "0110111" =>
sinal_caractere_valido <= '1';
when "0111000" =>
sinal_caractere_valido <= '1';
when "0111001" =>
sinal_caractere_valido <= '1';
when "0110100" =>
sinal_caractere_valido <= '1';
when "0110101" =>
sinal_caractere_valido <= '1';
when "0110110" =>
sinal_caractere_valido <= '1';
when "0110001" =>
sinal_caractere_valido <= '1';
when "0110010" =>
sinal_caractere_valido <= '1';
when "0110011" =>
sinal_caractere_valido <= '1';
when others =>
sinal_caractere_valido <= '0';
end case;
caractere_valido <= sinal_caractere_valido;
end process;
end estrutural;
|
entity repro3 is
end repro3;
architecture behav of repro3 is
type my_rec is record
a : bit;
w : bit_vector;
end record;
procedure check (v : my_rec) is
begin
assert v = ('0', "10");
end check;
procedure pack (a : bit; w : bit_vector) is
begin
check (v.a => a,
v.w => w);
end pack;
begin
process
begin
pack ('0', "01");
wait;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity test_mux is
end entity test_mux;
architecture behavioural of test_mux is
component MUX is
port (
selector : in std_logic;
input_a : in std_logic_vector(7 downto 0);
input_b : in std_logic_vector(7 downto 0);
output : out std_logic_vector(7 downto 0)
);
end component MUX;
signal selector : std_logic;
signal input_a : std_logic_vector(7 downto 0);
signal input_b : std_logic_vector(7 downto 0);
signal output : std_logic_vector(7 downto 0);
begin
multiplexer : MUX port map (selector, input_a, input_b, output);
process
begin
input_a <= "00001111";
input_b <= "11110000";
selector <= '0';
wait for 1 ns;
assert output = input_a
report "MUX should output input_a when selector is zero" severity error;
selector <= '1';
wait for 1 ns;
assert output = input_b
report "MUX should output input_b when selector is zero" severity error;
wait;
end process;
end behavioural;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 18 23:19:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_sim_netlist.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0_vga_color_test is
port (
rgb : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk_25 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_color_test_0_0_vga_color_test : entity is "vga_color_test";
end system_vga_color_test_0_0_vga_color_test;
architecture STRUCTURE of system_vga_color_test_0_0_vga_color_test is
signal \rgb[13]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_1_n_0\ : STD_LOGIC;
signal \rgb[14]_i_2_n_0\ : STD_LOGIC;
signal \rgb[14]_i_3_n_0\ : STD_LOGIC;
signal \rgb[14]_i_4_n_0\ : STD_LOGIC;
signal \rgb[14]_i_5_n_0\ : STD_LOGIC;
signal \rgb[14]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_1_n_0\ : STD_LOGIC;
signal \rgb[15]_i_2_n_0\ : STD_LOGIC;
signal \rgb[15]_i_3_n_0\ : STD_LOGIC;
signal \rgb[15]_i_4_n_0\ : STD_LOGIC;
signal \rgb[15]_i_5_n_0\ : STD_LOGIC;
signal \rgb[15]_i_6_n_0\ : STD_LOGIC;
signal \rgb[15]_i_7_n_0\ : STD_LOGIC;
signal \rgb[21]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_10_n_0\ : STD_LOGIC;
signal \rgb[22]_i_11_n_0\ : STD_LOGIC;
signal \rgb[22]_i_1_n_0\ : STD_LOGIC;
signal \rgb[22]_i_2_n_0\ : STD_LOGIC;
signal \rgb[22]_i_3_n_0\ : STD_LOGIC;
signal \rgb[22]_i_4_n_0\ : STD_LOGIC;
signal \rgb[22]_i_5_n_0\ : STD_LOGIC;
signal \rgb[22]_i_6_n_0\ : STD_LOGIC;
signal \rgb[22]_i_7_n_0\ : STD_LOGIC;
signal \rgb[22]_i_8_n_0\ : STD_LOGIC;
signal \rgb[22]_i_9_n_0\ : STD_LOGIC;
signal \rgb[23]_i_10_n_0\ : STD_LOGIC;
signal \rgb[23]_i_11_n_0\ : STD_LOGIC;
signal \rgb[23]_i_12_n_0\ : STD_LOGIC;
signal \rgb[23]_i_13_n_0\ : STD_LOGIC;
signal \rgb[23]_i_14_n_0\ : STD_LOGIC;
signal \rgb[23]_i_15_n_0\ : STD_LOGIC;
signal \rgb[23]_i_16_n_0\ : STD_LOGIC;
signal \rgb[23]_i_17_n_0\ : STD_LOGIC;
signal \rgb[23]_i_18_n_0\ : STD_LOGIC;
signal \rgb[23]_i_1_n_0\ : STD_LOGIC;
signal \rgb[23]_i_2_n_0\ : STD_LOGIC;
signal \rgb[23]_i_3_n_0\ : STD_LOGIC;
signal \rgb[23]_i_4_n_0\ : STD_LOGIC;
signal \rgb[23]_i_5_n_0\ : STD_LOGIC;
signal \rgb[23]_i_6_n_0\ : STD_LOGIC;
signal \rgb[23]_i_7_n_0\ : STD_LOGIC;
signal \rgb[23]_i_8_n_0\ : STD_LOGIC;
signal \rgb[23]_i_9_n_0\ : STD_LOGIC;
signal \rgb[4]_i_1_n_0\ : STD_LOGIC;
signal \rgb[4]_i_2_n_0\ : STD_LOGIC;
signal \rgb[5]_i_1_n_0\ : STD_LOGIC;
signal \rgb[5]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_1_n_0\ : STD_LOGIC;
signal \rgb[6]_i_2_n_0\ : STD_LOGIC;
signal \rgb[6]_i_3_n_0\ : STD_LOGIC;
signal \rgb[6]_i_4_n_0\ : STD_LOGIC;
signal \rgb[6]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_1_n_0\ : STD_LOGIC;
signal \rgb[7]_i_2_n_0\ : STD_LOGIC;
signal \rgb[7]_i_3_n_0\ : STD_LOGIC;
signal \rgb[7]_i_4_n_0\ : STD_LOGIC;
signal \rgb[7]_i_5_n_0\ : STD_LOGIC;
signal \rgb[7]_i_6_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rgb[14]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[14]_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[15]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[15]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[15]_i_5\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[15]_i_6\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[15]_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[22]_i_10\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[22]_i_11\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rgb[23]_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \rgb[23]_i_11\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rgb[23]_i_14\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_15\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[23]_i_17\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \rgb[23]_i_18\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rgb[23]_i_6\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \rgb[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rgb[6]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rgb[6]_i_4\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rgb[6]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \rgb[7]_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rgb[7]_i_4\ : label is "soft_lutpair5";
begin
\rgb[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5555FF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
O => \rgb[13]_i_1_n_0\
);
\rgb[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFF02"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => \rgb[14]_i_2_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[22]_i_3_n_0\,
I4 => \rgb[22]_i_2_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[14]_i_1_n_0\
);
\rgb[14]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"02F20202"
)
port map (
I0 => \rgb[14]_i_4_n_0\,
I1 => \rgb[23]_i_11_n_0\,
I2 => xaddr(9),
I3 => \rgb[14]_i_5_n_0\,
I4 => \rgb[23]_i_10_n_0\,
O => \rgb[14]_i_2_n_0\
);
\rgb[14]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
O => \rgb[14]_i_3_n_0\
);
\rgb[14]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFEFEFEFEEE"
)
port map (
I0 => xaddr(4),
I1 => xaddr(5),
I2 => xaddr(3),
I3 => xaddr(0),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[14]_i_4_n_0\
);
\rgb[14]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFF8"
)
port map (
I0 => xaddr(2),
I1 => xaddr(5),
I2 => xaddr(7),
I3 => xaddr(6),
I4 => xaddr(8),
O => \rgb[14]_i_5_n_0\
);
\rgb[14]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888A888A8888888"
)
port map (
I0 => yaddr(5),
I1 => yaddr(4),
I2 => yaddr(2),
I3 => yaddr(3),
I4 => yaddr(1),
I5 => yaddr(0),
O => \rgb[14]_i_6_n_0\
);
\rgb[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF55455545"
)
port map (
I0 => \rgb[23]_i_4_n_0\,
I1 => \rgb[22]_i_2_n_0\,
I2 => \rgb[15]_i_2_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[15]_i_4_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[15]_i_1_n_0\
);
\rgb[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[23]_i_12_n_0\,
O => \rgb[15]_i_2_n_0\
);
\rgb[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA88888"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => xaddr(9),
I2 => xaddr(6),
I3 => xaddr(7),
I4 => xaddr(8),
O => \rgb[15]_i_3_n_0\
);
\rgb[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"ECEEEEEEECECECEC"
)
port map (
I0 => xaddr(8),
I1 => xaddr(9),
I2 => xaddr(7),
I3 => \rgb[15]_i_5_n_0\,
I4 => \rgb[15]_i_6_n_0\,
I5 => \rgb[15]_i_7_n_0\,
O => \rgb[15]_i_4_n_0\
);
\rgb[15]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(0),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[15]_i_5_n_0\
);
\rgb[15]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => xaddr(5),
I1 => xaddr(4),
O => \rgb[15]_i_6_n_0\
);
\rgb[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => xaddr(6),
I1 => xaddr(5),
I2 => xaddr(4),
I3 => xaddr(3),
O => \rgb[15]_i_7_n_0\
);
\rgb[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFBF0FB"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_4_n_0\,
I2 => \rgb[23]_i_2_n_0\,
I3 => \rgb[23]_i_6_n_0\,
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[21]_i_1_n_0\
);
\rgb[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFF00FFEF"
)
port map (
I0 => \rgb[22]_i_2_n_0\,
I1 => \rgb[22]_i_3_n_0\,
I2 => \rgb[22]_i_4_n_0\,
I3 => \rgb[23]_i_2_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[22]_i_1_n_0\
);
\rgb[22]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => xaddr(9),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[22]_i_10_n_0\
);
\rgb[22]_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"0070"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(8),
I3 => xaddr(5),
O => \rgb[22]_i_11_n_0\
);
\rgb[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAABABAB"
)
port map (
I0 => \rgb[22]_i_5_n_0\,
I1 => xaddr(8),
I2 => xaddr(9),
I3 => xaddr(6),
I4 => xaddr(7),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_2_n_0\
);
\rgb[22]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000FD0000"
)
port map (
I0 => \rgb[23]_i_15_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[22]_i_7_n_0\,
I4 => xaddr(9),
I5 => \rgb[22]_i_6_n_0\,
O => \rgb[22]_i_3_n_0\
);
\rgb[22]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_8_n_0\,
I3 => \rgb[14]_i_3_n_0\,
O => \rgb[22]_i_4_n_0\
);
\rgb[22]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200030003"
)
port map (
I0 => \rgb[15]_i_5_n_0\,
I1 => xaddr(9),
I2 => xaddr(8),
I3 => xaddr(5),
I4 => xaddr(3),
I5 => xaddr(4),
O => \rgb[22]_i_5_n_0\
);
\rgb[22]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"111111111111111F"
)
port map (
I0 => \rgb[14]_i_6_n_0\,
I1 => yaddr(6),
I2 => \rgb[22]_i_9_n_0\,
I3 => xaddr(7),
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[22]_i_6_n_0\
);
\rgb[22]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFEFEFFFFFFFF"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
I3 => xaddr(5),
I4 => xaddr(2),
I5 => \rgb[23]_i_10_n_0\,
O => \rgb[22]_i_7_n_0\
);
\rgb[22]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"5515551555151515"
)
port map (
I0 => \rgb[23]_i_14_n_0\,
I1 => \rgb[22]_i_10_n_0\,
I2 => \rgb[22]_i_11_n_0\,
I3 => xaddr(4),
I4 => xaddr(1),
I5 => xaddr(2),
O => \rgb[22]_i_8_n_0\
);
\rgb[22]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCC000088800000"
)
port map (
I0 => xaddr(3),
I1 => xaddr(6),
I2 => xaddr(2),
I3 => xaddr(1),
I4 => xaddr(5),
I5 => xaddr(4),
O => \rgb[22]_i_9_n_0\
);
\rgb[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAAEAAAEAAAE"
)
port map (
I0 => \rgb[23]_i_2_n_0\,
I1 => \rgb[23]_i_3_n_0\,
I2 => \rgb[23]_i_4_n_0\,
I3 => \rgb[23]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_1_n_0\
);
\rgb[23]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xaddr(3),
I1 => xaddr(4),
I2 => xaddr(5),
O => \rgb[23]_i_10_n_0\
);
\rgb[23]_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => xaddr(8),
I1 => xaddr(6),
I2 => xaddr(7),
O => \rgb[23]_i_11_n_0\
);
\rgb[23]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => yaddr(6),
I1 => \rgb[14]_i_6_n_0\,
O => \rgb[23]_i_12_n_0\
);
\rgb[23]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0515555515155555"
)
port map (
I0 => \rgb[23]_i_18_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[23]_i_17_n_0\,
I4 => xaddr(6),
I5 => xaddr(3),
O => \rgb[23]_i_13_n_0\
);
\rgb[23]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => xaddr(9),
I1 => xaddr(8),
O => \rgb[23]_i_14_n_0\
);
\rgb[23]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => xaddr(3),
I1 => xaddr(1),
I2 => xaddr(2),
O => \rgb[23]_i_15_n_0\
);
\rgb[23]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(7),
I1 => xaddr(6),
O => \rgb[23]_i_16_n_0\
);
\rgb[23]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
O => \rgb[23]_i_17_n_0\
);
\rgb[23]_i_18\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => xaddr(7),
I1 => xaddr(8),
I2 => xaddr(9),
O => \rgb[23]_i_18_n_0\
);
\rgb[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000022222"
)
port map (
I0 => \rgb[15]_i_4_n_0\,
I1 => yaddr(6),
I2 => yaddr(4),
I3 => yaddr(3),
I4 => yaddr(5),
I5 => \rgb[23]_i_8_n_0\,
O => \rgb[23]_i_2_n_0\
);
\rgb[23]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAFFFB"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_9_n_0\,
I3 => xaddr(9),
I4 => \rgb[23]_i_7_n_0\,
O => \rgb[23]_i_3_n_0\
);
\rgb[23]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004440"
)
port map (
I0 => xaddr(9),
I1 => \rgb[23]_i_9_n_0\,
I2 => \rgb[23]_i_10_n_0\,
I3 => \rgb[23]_i_11_n_0\,
I4 => \rgb[23]_i_12_n_0\,
O => \rgb[23]_i_4_n_0\
);
\rgb[23]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0057FFFF00570057"
)
port map (
I0 => yaddr(5),
I1 => yaddr(3),
I2 => yaddr(4),
I3 => yaddr(6),
I4 => \rgb[23]_i_12_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[23]_i_5_n_0\
);
\rgb[23]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"0155"
)
port map (
I0 => yaddr(6),
I1 => yaddr(4),
I2 => yaddr(3),
I3 => yaddr(5),
O => \rgb[23]_i_6_n_0\
);
\rgb[23]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"40CC44CC44CC44CC"
)
port map (
I0 => xaddr(6),
I1 => \rgb[23]_i_14_n_0\,
I2 => \rgb[23]_i_15_n_0\,
I3 => xaddr(7),
I4 => xaddr(4),
I5 => xaddr(5),
O => \rgb[23]_i_7_n_0\
);
\rgb[23]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFD500000000"
)
port map (
I0 => \rgb[23]_i_10_n_0\,
I1 => xaddr(2),
I2 => xaddr(5),
I3 => \rgb[23]_i_16_n_0\,
I4 => xaddr(8),
I5 => xaddr(9),
O => \rgb[23]_i_8_n_0\
);
\rgb[23]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFFE0"
)
port map (
I0 => \rgb[23]_i_17_n_0\,
I1 => xaddr(0),
I2 => xaddr(3),
I3 => xaddr(5),
I4 => xaddr(4),
I5 => \rgb[23]_i_11_n_0\,
O => \rgb[23]_i_9_n_0\
);
\rgb[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"04770404"
)
port map (
I0 => \rgb[6]_i_2_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[4]_i_2_n_0\,
I4 => \rgb[5]_i_2_n_0\,
O => \rgb[4]_i_1_n_0\
);
\rgb[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF2F2FFFFF202F"
)
port map (
I0 => \rgb[22]_i_8_n_0\,
I1 => \rgb[15]_i_4_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[6]_i_5_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[23]_i_13_n_0\,
O => \rgb[4]_i_2_n_0\
);
\rgb[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAFEAAAAAAAA"
)
port map (
I0 => \rgb[7]_i_4_n_0\,
I1 => \rgb[15]_i_2_n_0\,
I2 => \rgb[15]_i_4_n_0\,
I3 => \rgb[15]_i_3_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[5]_i_2_n_0\,
O => \rgb[5]_i_1_n_0\
);
\rgb[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F7F0F7F"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[23]_i_12_n_0\,
I3 => \rgb[23]_i_7_n_0\,
I4 => \rgb[7]_i_3_n_0\,
O => \rgb[5]_i_2_n_0\
);
\rgb[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000FFFFF0045"
)
port map (
I0 => \rgb[14]_i_3_n_0\,
I1 => \rgb[7]_i_3_n_0\,
I2 => \rgb[23]_i_7_n_0\,
I3 => \rgb[6]_i_2_n_0\,
I4 => \rgb[6]_i_3_n_0\,
I5 => \rgb[23]_i_6_n_0\,
O => \rgb[6]_i_1_n_0\
);
\rgb[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => \rgb[14]_i_2_n_0\,
I1 => \rgb[22]_i_8_n_0\,
I2 => \rgb[7]_i_6_n_0\,
O => \rgb[6]_i_2_n_0\
);
\rgb[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF0002"
)
port map (
I0 => xaddr(9),
I1 => \rgb[22]_i_7_n_0\,
I2 => \rgb[6]_i_4_n_0\,
I3 => \rgb[22]_i_6_n_0\,
I4 => \rgb[6]_i_5_n_0\,
O => \rgb[6]_i_3_n_0\
);
\rgb[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000007"
)
port map (
I0 => xaddr(2),
I1 => xaddr(1),
I2 => xaddr(3),
I3 => xaddr(4),
I4 => xaddr(5),
O => \rgb[6]_i_4_n_0\
);
\rgb[6]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0057"
)
port map (
I0 => xaddr(8),
I1 => xaddr(7),
I2 => xaddr(6),
I3 => xaddr(9),
O => \rgb[6]_i_5_n_0\
);
\rgb[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222A"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => yaddr(5),
I2 => yaddr(3),
I3 => yaddr(4),
I4 => yaddr(6),
O => \rgb[7]_i_1_n_0\
);
\rgb[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000000FB"
)
port map (
I0 => \rgb[7]_i_3_n_0\,
I1 => \rgb[23]_i_7_n_0\,
I2 => \rgb[14]_i_3_n_0\,
I3 => \rgb[23]_i_4_n_0\,
I4 => \rgb[23]_i_6_n_0\,
I5 => \rgb[7]_i_4_n_0\,
O => \rgb[7]_i_2_n_0\
);
\rgb[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000000D"
)
port map (
I0 => xaddr(6),
I1 => \rgb[7]_i_5_n_0\,
I2 => xaddr(9),
I3 => xaddr(8),
I4 => xaddr(7),
O => \rgb[7]_i_3_n_0\
);
\rgb[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000444"
)
port map (
I0 => \rgb[23]_i_7_n_0\,
I1 => \rgb[23]_i_6_n_0\,
I2 => \rgb[7]_i_6_n_0\,
I3 => \rgb[22]_i_8_n_0\,
I4 => \rgb[14]_i_2_n_0\,
O => \rgb[7]_i_4_n_0\
);
\rgb[7]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"1515155515155555"
)
port map (
I0 => xaddr(5),
I1 => xaddr(3),
I2 => xaddr(4),
I3 => xaddr(0),
I4 => xaddr(2),
I5 => xaddr(1),
O => \rgb[7]_i_5_n_0\
);
\rgb[7]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000007F55"
)
port map (
I0 => \rgb[15]_i_7_n_0\,
I1 => xaddr(4),
I2 => xaddr(5),
I3 => \rgb[15]_i_5_n_0\,
I4 => xaddr(7),
I5 => xaddr(9),
O => \rgb[7]_i_6_n_0\
);
\rgb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[13]_i_1_n_0\,
Q => rgb(4),
R => '0'
);
\rgb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[14]_i_1_n_0\,
Q => rgb(5),
R => '0'
);
\rgb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[15]_i_1_n_0\,
Q => rgb(6),
R => '0'
);
\rgb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[21]_i_1_n_0\,
Q => rgb(7),
R => '0'
);
\rgb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[22]_i_1_n_0\,
Q => rgb(8),
R => '0'
);
\rgb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk_25,
CE => '1',
D => \rgb[23]_i_1_n_0\,
Q => rgb(9),
R => '0'
);
\rgb_reg[4]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[4]_i_1_n_0\,
Q => rgb(0),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[5]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[5]_i_1_n_0\,
Q => rgb(1),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[6]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[6]_i_1_n_0\,
Q => rgb(2),
S => \rgb[7]_i_1_n_0\
);
\rgb_reg[7]\: unisim.vcomponents.FDSE
port map (
C => clk_25,
CE => '1',
D => \rgb[7]_i_2_n_0\,
Q => rgb(3),
S => \rgb[7]_i_1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_color_test_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_color_test_0_0 : entity is "system_vga_color_test_0_0,vga_color_test,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_color_test_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_color_test_0_0 : entity is "vga_color_test,Vivado 2016.4";
end system_vga_color_test_0_0;
architecture STRUCTURE of system_vga_color_test_0_0 is
signal \^rgb\ : STD_LOGIC_VECTOR ( 23 downto 3 );
begin
rgb(23 downto 22) <= \^rgb\(23 downto 22);
rgb(21) <= \^rgb\(20);
rgb(20) <= \^rgb\(20);
rgb(19) <= \^rgb\(20);
rgb(18) <= \^rgb\(20);
rgb(17) <= \^rgb\(20);
rgb(16) <= \^rgb\(20);
rgb(15 downto 14) <= \^rgb\(15 downto 14);
rgb(13) <= \^rgb\(12);
rgb(12) <= \^rgb\(12);
rgb(11) <= \^rgb\(12);
rgb(10) <= \^rgb\(12);
rgb(9) <= \^rgb\(12);
rgb(8) <= \^rgb\(12);
rgb(7 downto 5) <= \^rgb\(7 downto 5);
rgb(4) <= \^rgb\(3);
rgb(3) <= \^rgb\(3);
rgb(2) <= \^rgb\(3);
rgb(1) <= \^rgb\(3);
rgb(0) <= \^rgb\(3);
U0: entity work.system_vga_color_test_0_0_vga_color_test
port map (
clk_25 => clk_25,
rgb(9 downto 8) => \^rgb\(23 downto 22),
rgb(7) => \^rgb\(20),
rgb(6 downto 5) => \^rgb\(15 downto 14),
rgb(4) => \^rgb\(12),
rgb(3 downto 1) => \^rgb\(7 downto 5),
rgb(0) => \^rgb\(3),
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(6 downto 0) => yaddr(9 downto 3)
);
end STRUCTURE;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00343
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00343(ARCH00343)
-- ENT00343_Test_Bench(ARCH00343_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00343 is
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr2 : inout st_arr2
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
--
end ENT00343 ;
--
--
architecture ARCH00343 of ENT00343 is
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr2_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_boolean_vector )
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb) <= transport
-- c_st_boolean_vector_2(lowb) after 10 ns,
-- c_st_boolean_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb) <= transport
-- c_st_boolean_vector_2(lowb) after 10 ns ,
-- c_st_boolean_vector_1(lowb) after 20 ns ,
-- c_st_boolean_vector_2(lowb) after 30 ns ,
-- c_st_boolean_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb) =
c_st_boolean_vector_2(lowb) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb) <= transport
-- c_st_boolean_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb) =
c_st_boolean_vector_1(lowb) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_boolean_vector(lowb) <= transport
c_st_boolean_vector_2(lowb) after 10 ns,
c_st_boolean_vector_1(lowb) after 20 ns
when st_boolean_vector_select = 1 else
--
c_st_boolean_vector_2(lowb) after 10 ns ,
c_st_boolean_vector_1(lowb) after 20 ns ,
c_st_boolean_vector_2(lowb) after 30 ns ,
c_st_boolean_vector_1(lowb) after 40 ns
when st_boolean_vector_select = 2 else
--
c_st_boolean_vector_1(lowb) after 5 ns ;
--
CHG2 :
process ( s_st_severity_level_vector )
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb) <= transport
-- c_st_severity_level_vector_2(lowb) after 10 ns,
-- c_st_severity_level_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb) <= transport
-- c_st_severity_level_vector_2(lowb) after 10 ns ,
-- c_st_severity_level_vector_1(lowb) after 20 ns ,
-- c_st_severity_level_vector_2(lowb) after 30 ns ,
-- c_st_severity_level_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_2(lowb) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb) <= transport
-- c_st_severity_level_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb) =
c_st_severity_level_vector_1(lowb) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_severity_level_vector(lowb) <= transport
c_st_severity_level_vector_2(lowb) after 10 ns,
c_st_severity_level_vector_1(lowb) after 20 ns
when st_severity_level_vector_select = 1 else
--
c_st_severity_level_vector_2(lowb) after 10 ns ,
c_st_severity_level_vector_1(lowb) after 20 ns ,
c_st_severity_level_vector_2(lowb) after 30 ns ,
c_st_severity_level_vector_1(lowb) after 40 ns
when st_severity_level_vector_select = 2 else
--
c_st_severity_level_vector_1(lowb) after 5 ns ;
--
CHG3 :
process ( s_st_string )
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb) <= transport
-- c_st_string_2(highb) after 10 ns,
-- c_st_string_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb) <= transport
-- c_st_string_2(highb) after 10 ns ,
-- c_st_string_1(highb) after 20 ns ,
-- c_st_string_2(highb) after 30 ns ,
-- c_st_string_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb) =
c_st_string_2(highb) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb) <= transport
-- c_st_string_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb) =
c_st_string_1(highb) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_string(highb) <= transport
c_st_string_2(highb) after 10 ns,
c_st_string_1(highb) after 20 ns
when st_string_select = 1 else
--
c_st_string_2(highb) after 10 ns ,
c_st_string_1(highb) after 20 ns ,
c_st_string_2(highb) after 30 ns ,
c_st_string_1(highb) after 40 ns
when st_string_select = 2 else
--
c_st_string_1(highb) after 5 ns ;
--
CHG4 :
process ( s_st_enum1_vector )
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb) <= transport
-- c_st_enum1_vector_2(highb) after 10 ns,
-- c_st_enum1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb) <= transport
-- c_st_enum1_vector_2(highb) after 10 ns ,
-- c_st_enum1_vector_1(highb) after 20 ns ,
-- c_st_enum1_vector_2(highb) after 30 ns ,
-- c_st_enum1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb) =
c_st_enum1_vector_2(highb) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb) <= transport
-- c_st_enum1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb) =
c_st_enum1_vector_1(highb) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_st_enum1_vector(highb) <= transport
c_st_enum1_vector_2(highb) after 10 ns,
c_st_enum1_vector_1(highb) after 20 ns
when st_enum1_vector_select = 1 else
--
c_st_enum1_vector_2(highb) after 10 ns ,
c_st_enum1_vector_1(highb) after 20 ns ,
c_st_enum1_vector_2(highb) after 30 ns ,
c_st_enum1_vector_1(highb) after 40 ns
when st_enum1_vector_select = 2 else
--
c_st_enum1_vector_1(highb) after 5 ns ;
--
CHG5 :
process ( s_st_integer_vector )
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb) <= transport
-- c_st_integer_vector_2(lowb) after 10 ns,
-- c_st_integer_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb) <= transport
-- c_st_integer_vector_2(lowb) after 10 ns ,
-- c_st_integer_vector_1(lowb) after 20 ns ,
-- c_st_integer_vector_2(lowb) after 30 ns ,
-- c_st_integer_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb) =
c_st_integer_vector_2(lowb) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb) <= transport
-- c_st_integer_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb) =
c_st_integer_vector_1(lowb) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_integer_vector(lowb) <= transport
c_st_integer_vector_2(lowb) after 10 ns,
c_st_integer_vector_1(lowb) after 20 ns
when st_integer_vector_select = 1 else
--
c_st_integer_vector_2(lowb) after 10 ns ,
c_st_integer_vector_1(lowb) after 20 ns ,
c_st_integer_vector_2(lowb) after 30 ns ,
c_st_integer_vector_1(lowb) after 40 ns
when st_integer_vector_select = 2 else
--
c_st_integer_vector_1(lowb) after 5 ns ;
--
CHG6 :
process ( s_st_time_vector )
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb) <= transport
-- c_st_time_vector_2(lowb) after 10 ns,
-- c_st_time_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb) <= transport
-- c_st_time_vector_2(lowb) after 10 ns ,
-- c_st_time_vector_1(lowb) after 20 ns ,
-- c_st_time_vector_2(lowb) after 30 ns ,
-- c_st_time_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb) =
c_st_time_vector_2(lowb) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb) <= transport
-- c_st_time_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb) =
c_st_time_vector_1(lowb) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_st_time_vector(lowb) <= transport
c_st_time_vector_2(lowb) after 10 ns,
c_st_time_vector_1(lowb) after 20 ns
when st_time_vector_select = 1 else
--
c_st_time_vector_2(lowb) after 10 ns ,
c_st_time_vector_1(lowb) after 20 ns ,
c_st_time_vector_2(lowb) after 30 ns ,
c_st_time_vector_1(lowb) after 40 ns
when st_time_vector_select = 2 else
--
c_st_time_vector_1(lowb) after 5 ns ;
--
CHG7 :
process ( s_st_real_vector )
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb) <= transport
-- c_st_real_vector_2(highb) after 10 ns,
-- c_st_real_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb) <= transport
-- c_st_real_vector_2(highb) after 10 ns ,
-- c_st_real_vector_1(highb) after 20 ns ,
-- c_st_real_vector_2(highb) after 30 ns ,
-- c_st_real_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb) =
c_st_real_vector_2(highb) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb) <= transport
-- c_st_real_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb) =
c_st_real_vector_1(highb) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_real_vector(highb) <= transport
c_st_real_vector_2(highb) after 10 ns,
c_st_real_vector_1(highb) after 20 ns
when st_real_vector_select = 1 else
--
c_st_real_vector_2(highb) after 10 ns ,
c_st_real_vector_1(highb) after 20 ns ,
c_st_real_vector_2(highb) after 30 ns ,
c_st_real_vector_1(highb) after 40 ns
when st_real_vector_select = 2 else
--
c_st_real_vector_1(highb) after 5 ns ;
--
CHG8 :
process ( s_st_rec1_vector )
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb) <= transport
-- c_st_rec1_vector_2(highb) after 10 ns,
-- c_st_rec1_vector_1(highb) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb) <= transport
-- c_st_rec1_vector_2(highb) after 10 ns ,
-- c_st_rec1_vector_1(highb) after 20 ns ,
-- c_st_rec1_vector_2(highb) after 30 ns ,
-- c_st_rec1_vector_1(highb) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb) =
c_st_rec1_vector_2(highb) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb) <= transport
-- c_st_rec1_vector_1(highb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb) =
c_st_rec1_vector_1(highb) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_st_rec1_vector(highb) <= transport
c_st_rec1_vector_2(highb) after 10 ns,
c_st_rec1_vector_1(highb) after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(highb) after 10 ns ,
c_st_rec1_vector_1(highb) after 20 ns ,
c_st_rec1_vector_2(highb) after 30 ns ,
c_st_rec1_vector_1(highb) after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(highb) after 5 ns ;
--
CHG9 :
process ( s_st_arr2_vector )
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb) <= transport
-- c_st_arr2_vector_2(lowb) after 10 ns,
-- c_st_arr2_vector_1(lowb) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb) <= transport
-- c_st_arr2_vector_2(lowb) after 10 ns ,
-- c_st_arr2_vector_1(lowb) after 20 ns ,
-- c_st_arr2_vector_2(lowb) after 30 ns ,
-- c_st_arr2_vector_1(lowb) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb) =
c_st_arr2_vector_2(lowb) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb) <= transport
-- c_st_arr2_vector_1(lowb) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb) =
c_st_arr2_vector_1(lowb) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_arr2_vector(lowb) <= transport
c_st_arr2_vector_2(lowb) after 10 ns,
c_st_arr2_vector_1(lowb) after 20 ns
when st_arr2_vector_select = 1 else
--
c_st_arr2_vector_2(lowb) after 10 ns ,
c_st_arr2_vector_1(lowb) after 20 ns ,
c_st_arr2_vector_2(lowb) after 30 ns ,
c_st_arr2_vector_1(lowb) after 40 ns
when st_arr2_vector_select = 2 else
--
c_st_arr2_vector_1(lowb) after 5 ns ;
--
CHG10 :
process ( s_st_arr2 )
variable correct : boolean ;
begin
case s_st_arr2_cnt is
when 0
=> null ;
-- s_st_arr2(highb,false) <= transport
-- c_st_arr2_2(highb,false) after 10 ns,
-- c_st_arr2_1(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00343.P10" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_select <= transport 2 ;
-- s_st_arr2(highb,false) <= transport
-- c_st_arr2_2(highb,false) after 10 ns ,
-- c_st_arr2_1(highb,false) after 20 ns ,
-- c_st_arr2_2(highb,false) after 30 ns ,
-- c_st_arr2_1(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2(highb,false) =
c_st_arr2_2(highb,false) and
(s_st_arr2_savt + 10 ns) = Std.Standard.Now ;
st_arr2_select <= transport 3 ;
-- s_st_arr2(highb,false) <= transport
-- c_st_arr2_1(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2(highb,false) =
c_st_arr2_1(highb,false) and
(s_st_arr2_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00343" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00343" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_savt <= transport Std.Standard.Now ;
chk_st_arr2 <= transport s_st_arr2_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_cnt <= transport s_st_arr2_cnt + 1 ;
--
end process CHG10 ;
--
PGEN_CHKP_10 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions completed entirely",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
--
s_st_arr2(highb,false) <= transport
c_st_arr2_2(highb,false) after 10 ns,
c_st_arr2_1(highb,false) after 20 ns
when st_arr2_select = 1 else
--
c_st_arr2_2(highb,false) after 10 ns ,
c_st_arr2_1(highb,false) after 20 ns ,
c_st_arr2_2(highb,false) after 30 ns ,
c_st_arr2_1(highb,false) after 40 ns
when st_arr2_select = 2 else
--
c_st_arr2_1(highb,false) after 5 ns ;
--
end ARCH00343 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00343_Test_Bench is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
--
end ENT00343_Test_Bench ;
--
--
architecture ARCH00343_Test_Bench of ENT00343_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_boolean_vector : inout st_boolean_vector
; s_st_severity_level_vector : inout st_severity_level_vector
; s_st_string : inout st_string
; s_st_enum1_vector : inout st_enum1_vector
; s_st_integer_vector : inout st_integer_vector
; s_st_time_vector : inout st_time_vector
; s_st_real_vector : inout st_real_vector
; s_st_rec1_vector : inout st_rec1_vector
; s_st_arr2_vector : inout st_arr2_vector
; s_st_arr2 : inout st_arr2
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00343 ( ARCH00343 ) ;
begin
CIS1 : UUT
port map (
s_st_boolean_vector
, s_st_severity_level_vector
, s_st_string
, s_st_enum1_vector
, s_st_integer_vector
, s_st_time_vector
, s_st_real_vector
, s_st_rec1_vector
, s_st_arr2_vector
, s_st_arr2
)
;
end block L1 ;
end ARCH00343_Test_Bench ;
|
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YokYXxfIAdGhW46qR9GisxlYy33lOgFlpQV36dAF47xLuuPH6b08/Wf4/sOcfUykov8PJdBKoWSZ
Rx5MnhpO1fXsXh4xXJLFwZ0T4Vy8OGkPqF/2Y4xK2qm7Wc4fa3N6FSL4XmQQC81llR8B0nMlGgyO
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2hsJSYqxP8T3QNYAk2IOTPvP4Z7ml/lBz2umlSaSf6Mux64wCXYrcanfnitnaJtbNfPzXGGgkY/3
T6+169P3rqjR25sirga7nBzkJ6g52E4WLTUEbNZBA0Mk365xNBVj/sARuhMykRczeJoqj4qp2fsf
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CN5mH9L3sV9NioSYC0sAVZwYimb7CPdNH4rREwKSpWlnBJ2xKsz8isYuRri/1XdePmgEWsFZYLet
`protect end_protected
|
-------------------------------------------------------------------------------
-- Title : Transmitter for ultrasonic beacons
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
--
-- Register description
--
-- offset | Meaning
-- -------+---------
-- 0x00 | Fractional Clock Divider MUL value
-- 0x01 | Fractional Clock Divider DIV value
-- 0x02 | Bit pattern 0
-- 0x03 | Bit pattern 1
-- 0x04 | Bit pattern 2
-- 0x05 | Bit pattern 3
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012, 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.utils_pkg.all;
use work.motor_control_pkg.all; -- for half_bridge_type
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity uss_tx_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF# -- Base address at the internal data bus
);
port (
-- Ports to the ultrasonic transmitters
uss_tx0_out_p : out half_bridge_type;
uss_tx1_out_p : out half_bridge_type;
uss_tx2_out_p : out half_bridge_type;
-- Output of the clock enable signal
clk_uss_enable_p : out std_logic;
-- signals to and from the internal parallel bus
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end uss_tx_module;
-------------------------------------------------------------------------------
architecture behavioral of uss_tx_module is
-- types for states
-- none
-- record for internal states
-- none
-----------------------------------------------------------------------------
-- internal signals
-----------------------------------------------------------------------------
-- access to the internal register
constant REG_ADDR_BIT : natural := 3; -- 2**3 = 8 registers for mul and div value
constant BITPATTERN_WIDTH : positive := 64; -- Width of the bit pattern to send
signal reg_o : reg_file_type(((2**REG_ADDR_BIT)-1) downto 0) := (others => (others => '0'));
signal reg_i : reg_file_type(((2**REG_ADDR_BIT)-1) downto 0) := (others => (others => '0'));
signal clk_mul : std_logic_vector(15 downto 0);
signal clk_div : std_logic_vector(15 downto 0);
signal pattern : std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
signal bitstream : std_logic;
signal clk_bit : std_logic;
signal modulation : std_logic_vector(2 downto 0); -- Modulation of the US carrier
signal clk_uss_enable : std_logic := '0';
signal clk_uss : std_logic := '0'; -- Clock signal with 50% duty cycle
signal clk_uss_n : std_logic;
signal uss_tx_high : std_logic; -- With deadtime, for H-bridges
signal uss_tx_low : std_logic; -- With deadtime, for H-bridges
begin -- behavioral
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- register for access to and from STM
reg_file_1 : reg_file
generic map (
BASE_ADDRESS => BASE_ADDRESS,
REG_ADDR_BIT => REG_ADDR_BIT
)
port map (
bus_o => bus_o,
bus_i => bus_i,
reg_o => reg_o,
reg_i => reg_i,
clk => clk
);
-- Serialise the bit pattern to a bit stream
serialiser : entity work.serialiser
generic map (
BITPATTERN_WIDTH => BITPATTERN_WIDTH)
port map (
pattern_in_p => pattern,
bitstream_out_p => bitstream,
clk_bit => clk_bit,
clk => clk);
-- Bit clock (2000 bps)
-- 50 MHz / 25000 = 2000
clock_divider : entity work.clock_divider
generic map (
DIV => 25000)
port map (
clk_out_p => clk_bit,
clk => clk);
-- clock generation of clk_uss_tx (carrier)
fractional_clock_divider_variable_1 : fractional_clock_divider_variable
generic map (
WIDTH => 16)
port map (
div => clk_div,
mul => clk_mul,
clk_out_p => clk_uss_enable,
clk => clk);
-- generate a signal with a 50% duty-cycle from the enable signal
process (clk, clk_uss_enable)
begin
if rising_edge(clk) then
if clk_uss_enable = '1' then
clk_uss <= not clk_uss;
end if;
end if;
end process;
-- generate clocks with deadtime
clk_uss_n <= not clk_uss;
-- output to the H-bridges
deadtime_on : deadtime
generic map (
T_DEAD => 250) -- 5000ns
port map (
in_p => clk_uss_n,
out_p => uss_tx_low,
clk => clk);
deadtime_off : deadtime
generic map (
T_DEAD => 250) -- 5000ns
port map (
in_p => clk_uss,
out_p => uss_tx_high,
clk => clk);
-----------------------------------------------------------------------------
-- Mapping of signals between components and module ports
-----------------------------------------------------------------------------
clk_mul <= reg_o(0);
clk_div <= reg_o(1);
pattern(15 downto 0) <= reg_o(2);
pattern(31 downto 16) <= reg_o(3);
pattern(47 downto 32) <= reg_o(4);
pattern(63 downto 48) <= reg_o(5);
clk_uss_enable_p <= clk_uss_enable;
-----------------------------------------------------------------------------
-- Drive Ultrasonic transmitters
-----------------------------------------------------------------------------
modulation(0) <= bitstream;
modulation(1) <= bitstream;
modulation(2) <= bitstream;
uss_tx0_out_p.high <= uss_tx_high and modulation(0);
uss_tx1_out_p.high <= uss_tx_high and modulation(1);
uss_tx2_out_p.high <= uss_tx_high and modulation(2);
uss_tx0_out_p.low <= uss_tx_low and modulation(0);
uss_tx1_out_p.low <= uss_tx_low and modulation(1);
uss_tx2_out_p.low <= uss_tx_low and modulation(2);
end behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4_block.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF2_4_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_3_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_3_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_11_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_11_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_3_im_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block IS
-- Signals
SIGNAL dout_3_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_3_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_11_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_11_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL dout_3_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_3_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_4_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_4_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
BEGIN
dout_3_re_signed <= signed(dout_3_re);
din1_re <= resize(dout_3_re_signed, 20);
dout_3_im_signed <= signed(dout_3_im);
din1_im <= resize(dout_3_im_signed, 20);
dout_11_re_signed <= signed(dout_11_re);
din2_re <= resize(dout_11_re_signed, 20);
dout_11_im_signed <= signed(dout_11_im);
din2_im <= resize(dout_11_im_signed, 20);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 21);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_3)
VARIABLE add_cast : signed(20 DOWNTO 0);
VARIABLE add_cast_0 : signed(20 DOWNTO 0);
VARIABLE add_cast_1 : signed(20 DOWNTO 0);
VARIABLE add_cast_2 : signed(20 DOWNTO 0);
VARIABLE sub_cast : signed(20 DOWNTO 0);
VARIABLE sub_cast_0 : signed(20 DOWNTO 0);
VARIABLE sub_cast_1 : signed(20 DOWNTO 0);
VARIABLE sub_cast_2 : signed(20 DOWNTO 0);
VARIABLE add_cast_3 : signed(20 DOWNTO 0);
VARIABLE add_cast_4 : signed(20 DOWNTO 0);
VARIABLE add_cast_5 : signed(20 DOWNTO 0);
VARIABLE add_cast_6 : signed(20 DOWNTO 0);
VARIABLE sub_cast_3 : signed(20 DOWNTO 0);
VARIABLE sub_cast_4 : signed(20 DOWNTO 0);
VARIABLE sub_cast_5 : signed(20 DOWNTO 0);
VARIABLE sub_cast_6 : signed(20 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_3 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(din1_re, 21);
add_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(din1_re, 21);
sub_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(din1_im, 21);
add_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(din1_im, 21);
sub_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(din1_re, 21);
add_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(din1_re, 21);
sub_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(din1_im, 21);
add_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(din1_im, 21);
sub_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
dout_3_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(19 DOWNTO 0);
dout_3_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(19 DOWNTO 0);
dout_4_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(19 DOWNTO 0);
dout_4_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(19 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
dout_3_re_1 <= std_logic_vector(dout_3_re_tmp);
dout_3_im_1 <= std_logic_vector(dout_3_im_tmp);
END rtl;
|
------------------------------------------------------------------------------
-- "std_logic_1164_additions" package contains the additions to the standard
-- "std_logic_1164" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee_proposed.std_logic_1164_additions.all;
-- Last Modified: $Date: 2010/09/22 18:32:33 $
-- RCS ID: $Id: std_logic_1164_additions.vhdl,v 1.13 2010/09/22 18:32:33 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package std_logic_1164_additions is
-- NOTE that in the new std_logic_1164, STD_LOGIC_VECTOR is a resolved
-- subtype of STD_ULOGIC_VECTOR. Thus there is no need for funcitons which
-- take inputs in STD_LOGIC_VECTOR.
-- For compatability with VHDL-2002, I have replicated all of these funcitons
-- here for STD_LOGIC_VECTOR.
-- new aliases
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bv is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_LOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_bit_vector is ieee.std_logic_1164.To_bitvector [STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_slv is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [BIT_VECTOR return STD_LOGIC_VECTOR];
alias to_std_logic_vector is ieee.std_logic_1164.To_StdLogicVector [STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_sulv is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [BIT_VECTOR return STD_ULOGIC_VECTOR];
alias to_std_ulogic_vector is ieee.std_logic_1164.To_StdULogicVector [STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- vector-reduction functions.
-- "and" functions default to "1", or defaults to "0"
-------------------------------------------------------------------
-----------------------------------------------------------------------------
-- %%% Replace the "_reduce" functions with the ones commented out below.
-----------------------------------------------------------------------------
-- function "and" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "and" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nand" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "or" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "nor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xor" ( l : std_ulogic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_logic_vector ) RETURN std_ulogic;
-- function "xnor" ( l : std_ulogic_vector ) RETURN std_ulogic;
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC;
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- ?= operators, same functionality as 1076.3 1994 std_match
-------------------------------------------------------------------
-- FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic;
-- FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic;
-- FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic;
-- FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic;
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC;
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC;
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC;
-- "??" operator, converts a std_ulogic to a boolean.
--%%% Uncomment the following operators
-- FUNCTION "??" (S : STD_ULOGIC) RETURN BOOLEAN;
--%%% REMOVE the following funciton (for testing only)
function \??\ (S : STD_ULOGIC) return BOOLEAN;
-- rtl_synthesis off
-- pragma synthesis_off
function to_string (value : STD_ULOGIC) return STRING;
function to_string (value : STD_ULOGIC_VECTOR) return STRING;
function to_string (value : STD_LOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_LOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_LOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_LOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_LOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_LOGIC_VECTOR, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function maximum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function maximum (l, r : STD_ULOGIC) return STD_ULOGIC;
function minimum (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function minimum (l, r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function minimum (l, r : STD_ULOGIC) return STD_ULOGIC;
end package std_logic_1164_additions;
package body std_logic_1164_additions is
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := XMAP; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-- end Bugzilla issue #148
-------------------------------------------------------------------
-------------------------------------------------------------------
-- overloaded shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_LOGIC_VECTOR; r : INTEGER) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- vector/scalar overloaded logical operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_LOGIC_VECTOR; r : STD_ULOGIC) return STD_LOGIC_VECTOR is
alias lv : STD_LOGIC_VECTOR (1 to l'length) is l;
variable result : STD_LOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
alias rv : STD_LOGIC_VECTOR (1 to r'length) is r;
variable result : STD_LOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- vector-reduction functions
-------------------------------------------------------------------
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function and_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return and_reduce (to_StdULogicVector (l));
end function and_reduce;
-------------------------------------------------------------------
function and_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := (l(i) and result);
end loop;
return result;
end function and_reduce;
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function nand_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(to_StdULogicVector(l)));
end function nand_reduce;
-------------------------------------------------------------------
function nand_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not (and_reduce(l));
end function nand_reduce;
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function or_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return or_reduce (to_StdULogicVector (l));
end function or_reduce;
-------------------------------------------------------------------
function or_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) or result);
end loop;
return result;
end function or_reduce;
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function nor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(To_StdULogicVector(l)));
end function nor_reduce;
-------------------------------------------------------------------
function nor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function xor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return xor_reduce (to_StdULogicVector (l));
end function xor_reduce;
-------------------------------------------------------------------
function xor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := (l(i) xor result);
end loop;
return result;
end function xor_reduce;
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function xnor_reduce (l : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(To_StdULogicVector(l)));
end function xnor_reduce;
-------------------------------------------------------------------
function xnor_reduce (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% End "remove the following functions"
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_logic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_LOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_LOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic_vector ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
alias lv : STD_ULOGIC_VECTOR(1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR(1 to r'length) is r;
variable result, result1 : STD_ULOGIC;
begin
-- Logically identical to an "=" operator.
if ((l'length < 1) and (r'length < 1)) then
-- VHDL-2008 LRM 9.2.3 Two NULL arrays of the same type are equal
return '1';
elsif lv'length /= rv'length then
-- Two arrays of different lengths are false
return '0';
else
result := '1';
for i in lv'low to lv'high loop
result1 := match_logic_table(lv(i), rv(i));
result := result and result1;
end loop;
return result;
end if;
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_logic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_LOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic_vector ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return not \?=\ (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- Table for the ?< function (Section 9.2.3)
constant qlt : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'X'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '0', '0', 'X', 'X', '0', '0', 'X'), -- | H |
('X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- %%% FUNCTION "?>" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not (qlt (l, r) or match_logic_table (l,r));
end function \?>\;
-- %%% END FUNCTION "?>";
-- %%% FUNCTION "?>=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?>=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return not qlt (l, r);
end function \?>=\;
-- %%% END FUNCTION "?>=";
-- %%% FUNCTION "?<" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r);
end function \?<\;
-- %%% END FUNCTION "?<";
-- %%% FUNCTION "?<=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?<=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return qlt (l, r) or match_logic_table (l,r);
end function \?<=\;
-- %%% END FUNCTION "?<=";
-- "??" operator, converts a std_ulogic to a boolean.
-- %%% FUNCTION "??"
function \??\ (S : STD_ULOGIC) return BOOLEAN is
begin
return S = '1' or S = 'H';
end function \??\;
-- %%% END FUNCTION "??";
-- rtl_synthesis off
-- pragma synthesis_off
-----------------------------------------------------------------------------
-- This section copied from "std_logic_textio"
-----------------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- null STRING
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
good := false;
else
if char_to_MVL9plus(c) = error then
good := false;
else
VALUE := char_to_MVL9(c);
good := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := false;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
return;
elsif c = '_' then
if i = 0 then -- Begins with an "_"
return;
elsif lastu then -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
good := true;
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
Skip_whitespace (L);
read (l, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Short read, Space encounted in input string"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(l, MVL9_to_char(VALUE), justified, field);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_ULOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(l, s, justified, field);
end procedure WRITE;
-- Read and Write procedures for STD_LOGIC_VECTOR
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
READ (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
variable m : STD_LOGIC_VECTOR(1 to VALUE'length) := VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, justified, field);
end procedure WRITE;
-----------------------------------------------------------------------
-- Alias for bread and bwrite are provided with call out the read and
-- write functions.
-----------------------------------------------------------------------
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-- Hex Read and Write procedures for STD_LOGIC_VECTOR
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
HREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure HREAD;
procedure HWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring(VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- Octal Read and Write procedures for STD_LOGIC_VECTOR
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue, GOOD => GOOD);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_LOGIC_VECTOR) is
variable ivalue : STD_ULOGIC_VECTOR (VALUE'range);
begin
OREAD (L => L, VALUE => ivalue);
VALUE := to_stdlogicvector (ivalue);
end procedure OREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_LOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
-----------------------------------------------------------------------------
-- New string functions for vhdl-200x fast track
-----------------------------------------------------------------------------
function to_string (value : STD_ULOGIC) return STRING is
variable result : STRING (1 to 1);
begin
result (1) := MVL9_to_char (value);
return result;
end function to_string;
-------------------------------------------------------------------
-- TO_STRING (an alias called "to_bstring" is provide)
-------------------------------------------------------------------
function to_string (value : STD_ULOGIC_VECTOR) return STRING is
alias ivalue : STD_ULOGIC_VECTOR(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char(iValue(i));
end loop;
return result;
end if;
end function to_string;
-------------------------------------------------------------------
-- TO_HSTRING
-------------------------------------------------------------------
function to_hstring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_ULOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
-------------------------------------------------------------------
-- TO_OSTRING
-------------------------------------------------------------------
function to_ostring (value : STD_ULOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_ULOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_string (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_string (to_stdulogicvector (value));
end function to_string;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_hstring (to_stdulogicvector (value));
end function to_hstring;
function to_ostring (value : STD_LOGIC_VECTOR) return STRING is
begin
return to_ostring (to_stdulogicvector (value));
end function to_ostring;
-- rtl_synthesis on
-- pragma synthesis_on
function maximum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
function maximum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
-- std_logic_vector output
function minimum (L, R : STD_ULOGIC) return STD_ULOGIC is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
end package body std_logic_1164_additions;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rgbfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF rgbfifo_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: rgbfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: rgbfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: rgbfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
rgbfifo_inst : rgbfifo_exdes
PORT MAP (
CLK => clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rgbfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF rgbfifo_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: rgbfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: rgbfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: rgbfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
rgbfifo_inst : rgbfifo_exdes
PORT MAP (
CLK => clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rgbfifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF rgbfifo_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL almost_full : STD_LOGIC;
SIGNAL almost_empty : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
almost_empty_i <= almost_empty;
almost_full_i <= almost_full;
fg_dg_nv: rgbfifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 8,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: rgbfifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: rgbfifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 8,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 11,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
rgbfifo_inst : rgbfifo_exdes
PORT MAP (
CLK => clk_i,
VALID => valid,
ALMOST_FULL => almost_full,
ALMOST_EMPTY => almost_empty,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Package: components
-- File: components.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Component declaration of Cypress sync-sram
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package components is
component cy7c1354
generic (
fname : string := "ram.srec"; -- File to read from
-- Constant parameters
addr_bits : INTEGER := 18;
data_bits : INTEGER := 36;
-- Timing parameters for -5 (225 Mhz)
tCYC : TIME := 4.4 ns;
tCH : TIME := 1.8 ns;
tCL : TIME := 1.8 ns;
tCO : TIME := 2.8 ns;
tAS : TIME := 1.4 ns;
tCENS : TIME := 1.4 ns;
tWES : TIME := 1.4 ns;
tDS : TIME := 1.4 ns;
tAH : TIME := 0.4 ns;
tCENH : TIME := 0.4 ns;
tWEH : TIME := 0.4 ns;
tDH : TIME := 0.4 ns
-- Timing parameters for -5 (200 Mhz)
--tCYC : TIME := 5.0 ns;
--tCH : TIME := 2.0 ns;
--tCL : TIME := 2.0 ns;
--tCO : TIME := 3.2 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
-- Timing parameters for -5 (166 Mhz)
--tCYC : TIME := 6.0 ns;
--tCH : TIME := 2.4 ns;
--tCL : TIME := 2.4 ns;
--tCO : TIME := 3.5 ns;
--tAS : TIME := 1.5 ns;
--tCENS : TIME := 1.5 ns;
--tWES : TIME := 1.5 ns;
--tDS : TIME := 1.5 ns;
--tAH : TIME := 0.5 ns;
--tCENH : TIME := 0.5 ns;
--tWEH : TIME := 0.5 ns;
--tDH : TIME := 0.5 ns
);
-- Port Declarations
PORT (
Dq : INOUT STD_LOGIC_VECTOR ((data_bits - 1) DOWNTO 0); -- Data I/O
Addr : IN STD_LOGIC_VECTOR ((addr_bits - 1) DOWNTO 0); -- Address
Mode : IN STD_LOGIC := '1'; -- Burst Mode
Clk : IN STD_LOGIC; -- Clk
CEN_n : IN STD_LOGIC; -- CEN#
AdvLd_n : IN STD_LOGIC; -- Adv/Ld#
Bwa_n : IN STD_LOGIC; -- Bwa#
Bwb_n : IN STD_LOGIC; -- BWb#
Bwc_n : IN STD_LOGIC; -- Bwc#
Bwd_n : IN STD_LOGIC; -- BWd#
Rw_n : IN STD_LOGIC; -- RW#
Oe_n : IN STD_LOGIC; -- OE#
Ce1_n : IN STD_LOGIC; -- CE1#
Ce2 : IN STD_LOGIC; -- CE2
Ce3_n : IN STD_LOGIC; -- CE3#
Zz : IN STD_LOGIC -- Snooze Mode
);
end component;
component CY7C1380D
GENERIC (
fname : string := "ram.srec"; -- File to read from
-- Constant Parameters
addr_bits : INTEGER := 19; -- This is external address
data_bits : INTEGER := 36;
--Clock timings for 250Mhz
Cyp_tCO : TIME := 2.6 ns; -- Data Output Valid After CLK Rise
Cyp_tCYC : TIME := 4.0 ns; -- Clock cycle time
Cyp_tCH : TIME := 1.7 ns; -- Clock HIGH time
Cyp_tCL : TIME := 1.7 ns; -- Clock LOW time
Cyp_tCHZ : TIME := 2.6 ns; -- Clock to High-Z
Cyp_tCLZ : TIME := 1.0 ns; -- Clock to Low-Z
Cyp_tOEHZ : TIME := 2.6 ns; -- OE# HIGH to Output High-Z
Cyp_tOELZ : TIME := 0.0 ns; -- OE# LOW to Output Low-Z
Cyp_tOEV : TIME := 2.6 ns; -- OE# LOW to Output Valid
Cyp_tAS : TIME := 1.2 ns; -- Address Set-up Before CLK Rise
Cyp_tADS : TIME := 1.2 ns; -- ADSC#, ADSP# Set-up Before CLK Rise
Cyp_tADVS : TIME := 1.2 ns; -- ADV# Set-up Before CLK Rise
Cyp_tWES : TIME := 1.2 ns; -- BWx#, GW#, BWE# Set-up Before CLK Rise
Cyp_tDS : TIME := 1.2 ns; -- Data Input Set-up Before CLK Rise
Cyp_tCES : TIME := 1.2 ns; -- Chip Enable Set-up
Cyp_tAH : TIME := 0.3 ns; -- Address Hold After CLK Rise
Cyp_tADH : TIME := 0.3 ns; -- ADSC#, ADSP# Hold After CLK Rise
Cyp_tADVH : TIME := 0.3 ns; -- ADV# Hold After CLK Rise
Cyp_tWEH : TIME := 0.3 ns; -- BWx#, GW#, BWE# Hold After CLK Rise
Cyp_tDH : TIME := 0.3 ns; -- Data Input Hold After CLK Rise
Cyp_tCEH : TIME := 0.3 ns -- Chip Enable Hold After CLK Rise
);
PORT (iZZ : IN STD_LOGIC;
iMode : IN STD_LOGIC;
iADDR : IN STD_LOGIC_VECTOR ((addr_bits -1) downto 0);
inGW : IN STD_LOGIC;
inBWE : IN STD_LOGIC;
inBWd : IN STD_LOGIC;
inBWc : IN STD_LOGIC;
inBWb : IN STD_LOGIC;
inBWa : IN STD_LOGIC;
inCE1 : IN STD_LOGIC;
iCE2 : IN STD_LOGIC;
inCE3 : IN STD_LOGIC;
inADSP : IN STD_LOGIC;
inADSC : IN STD_LOGIC;
inADV : IN STD_LOGIC;
inOE : IN STD_LOGIC;
ioDQ : INOUT STD_LOGIC_VECTOR ((data_bits-1) downto 0);
iCLK : IN STD_LOGIC);
end component;
end;
-- pragma translate_on
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cordic_lib.all;
--library ieee_proposed;
--use ieee_proposed.float_pkg.all;
library floatfixlib;
use floatfixlib.float_pkg.all;
entity tp4 is
generic(
N_BITS_COORD : integer := 32 --- REVISAR
);
port(
clk_i: in std_logic; -- Clock general
data_i: in std_logic; -- Entrada de datos
rst_i: in std_logic; -- Botón de reset
--rot_on, rot_vel: in std_logic; -- Switches y botones para controlar la rotación
--rot_x_on, rot_y_on, rot_z_on: in std_logic;
rot_x_ng, rot_y_ng, rot_z_ng: in std_logic;
inc_alfa, inc_beta, inc_gama: in std_logic;
rst_angs_i: in std_logic;
data_volt_out: out std_logic;
hs, vs: out std_logic; -- Output para el display VGA
red_o: out std_logic_vector(2 downto 0);
grn_o: out std_logic_vector(2 downto 0);
blu_o: out std_logic_vector(1 downto 0);
a,b,c,d,e,f,g,dp: out std_logic -- Segmentos del display de 7 segmentos
);
attribute loc: string;
attribute slew: string;
attribute drive: string;
attribute iostandard: string;
attribute CLOCK_DEDICATED_ROUTE: string;
attribute CLOCK_DEDICATED_ROUTE of rst_i: signal is "false";
-- Mapeo de pines para el kit Nexys 2 (spartan 3E)
-- https://reference.digilentinc.com/_media/nexys:nexys2:nexys2_rm.pdf
attribute loc of clk_i: signal is "B8";
attribute loc of data_i: signal is "L15"; -- Pin físico de entrada de datos
-- VGA
attribute loc of hs: signal is "T4";
attribute loc of vs: signal is "U3";
attribute loc of red_o: signal is "R8 T8 R9";
attribute loc of grn_o: signal is "P6 P8 N8";
attribute loc of blu_o: signal is "U4 U5";
-- Switches
-- attribute loc of rot_on: signal is "R17"; -- Prender rotación constante
-- attribute loc of rot_vel: signal is "N17"; -- Velocidad lenta o rápida
-- attribute loc of rot_x_on: signal is "L13"; -- Rotación en x
-- attribute loc of rot_y_on: signal is "K17"; -- Rotación en y
-- attribute loc of rot_z_on: signal is "H18"; -- Rotación en z
attribute loc of rot_x_ng: signal is "L14"; -- Rotación negativa en x
attribute loc of rot_y_ng: signal is "K18"; -- Rotación negativa en y
attribute loc of rot_z_ng: signal is "G18"; -- Rotación negativa en z
-- Botones
attribute loc of rst_i: signal is "B18"; -- Botón para resetear todo
attribute loc of inc_alfa: signal is "H13";
attribute loc of inc_beta: signal is "E18";
attribute loc of inc_gama: signal is "D18";
-- attribute loc of rst_angs_i: signal is "B18"; -- Reseteo a posición inicial
-- Apagar los segmentos del display
attribute loc of a: signal is "L18";
attribute loc of b: signal is "F18";
attribute loc of c: signal is "D17";
attribute loc of d: signal is "D16";
attribute loc of e: signal is "G14";
attribute loc of f: signal is "J17";
attribute loc of g: signal is "H14";
attribute loc of dp: signal is "C17";
end;
architecture tp4_arq of tp4 is
-- signal rot_ena: std_logic := '0'; -- Enable de rotar
signal ena_o: std_logic := '0';
signal ram_int_refresh, rst_pdram: std_logic := '0';
signal alfa, beta, gama: t_float;
signal pos_leida, pos_rotada: t_pos;
signal vec_pos_pixel: t_vec;
signal dir_pixel: t_dir;
signal pix_x, pix_y: std_logic_vector(9 downto 0) := (others => '0');
signal pix_on: std_logic := '0';
signal RxRdy: std_logic := '0'; -- Si el próximo dato está listo para leerse
---Falta un bit para saber si se terminó de leer [todos los] datos?
signal Dout_uart: std_logic_vector(15 downto 0) := (others => '0');
signal pos_mem_leida: t_pos_mem := (others => (others => '0'));
signal rst_angs: std_logic := '0';
begin
-- *** RECIBIR Y GUARDAR ***
-- UART para recibir los datos de la PC y mandarlos a la RAM externa
uart: entity work.data_acq_unit
port map(
clk => clk_i,
rst => rst_i,
rx => data_i,
data_out_16bits => Dout_uart,
data_ready => RxRdy
);
--- Se guarda un dato de lectura listo en memoria [interna]. Paralelamente, continuamente se escriben en vector pos_leida los datos ya guardados
ram_int: entity work.ram_interna
generic map(
N_BITS => N_BITS_COORD,
CANT_P => 100
) port map(
clk => clk_i,
rst => rst_i,
Rx => RxRdy,
Din => Dout_uart,
Dout => pos_mem_leida,
Rdy => ena_o,
barrido => ram_int_refresh
);
-- Paso a formato punto flotante
process(pos_mem_leida)
begin
--- pos_leida(i) <= to_float(std_logic_vector(to_signed(to_integer(signed(pos_mem_leida(i))),N_BITS_COORD)));
pos_leida(1) <= to_float(pos_mem_leida(1));
pos_leida(2) <= to_float(pos_mem_leida(2));
pos_leida(3) <= to_float(pos_mem_leida(3));
end process;
-- *** LEER Y ROTAR ***
--- Si hiciéramos rotación constante:
--- 3 contadores de pasos angulares en cada eje,
--- se multiplican a la velocidad de rotación (lenta o rápida según rot_vel),
--- y eso son los 3 ángulos: alfa, beta, gama.
rst_angs <= rst_angs_i or rst_i;
-- Obtengo los ángulos de rotación para cada eje
angles: entity work.det_angulos
port map(
clk_i,
'0',---APAGO PARA TESTEAR---ena_o, -- and rot_ena,
rst_angs,
inc_alfa, inc_beta, inc_gama,
rot_x_ng, rot_y_ng, rot_z_ng,
alfa, beta, gama
);
-- Roto la posición leída según los ángulos de rotación
---rotador: entity work.rotador3d COMENTADA para probar sintetizar
--- port map(
--- ena => ena_o, ---ena => rot_ena,
--- pos_in => pos_leida,
--- alfa => alfa,
--- beta => beta,
--- gama => gama,
---
--- pos_rotada => pos_rotada
--- );
pos_rotada <= pos_leida;---
-- Aplano a ejes (y,z)
vec_pos_pixel(1) <= pos_rotada(2);
vec_pos_pixel(2) <= pos_rotada(3);
-- Para la posición rotada genero la dirección en memoria correspondiente
gen_dir: entity work.gen_dirs
port map(
pos_2d => vec_pos_pixel,
dir => dir_pixel
);
---rst_pdram <= ram_int_refresh or rst_i;
----APAGO BARRIDO para tests
rst_pdram <= '0';
-- Prendo el bit para la posición apropiada en la dual port ram
ram_video: entity work.video_ram
port map (
clock => clk_i,
write_enable => ena_o, ---Chequear
barrido => rst_pdram,
A_row => dir_pixel(2),
B_row => pix_y,
A_col => dir_pixel(1),
B_col => pix_x,
data_A => '1',
data_B => pix_on
);
--pix_on <= pix_on and ena_o;---Quilombo?
-- *** IMPRIMIR *** [De acá en más, se tratan los ejes como (x,y)]
-- VGA
vga: entity work.VGA_ctrl
port map(
mclk => clk_i,
red_i => pix_on, --- 1 si hay algo, 0 si no
grn_i => pix_on, --- 1 si hay algo, 0 si no
blu_i => pix_on,---'1',
hs => hs,
vs => vs,
red_o => red_o,
grn_o => grn_o,
blu_o => blu_o,
pixel_row => pix_y, -- y del píxel que se está imprimiendo
pixel_col => pix_x -- x del píxel que se está imprimiendo
);
-- Apago todos los segmentos del display de 7 segmentos
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
dp <= '1';
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async
-- File: ahb2avl_async.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynchronous AHB to Avalon-MM interface based on ddr2spa
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end;
architecture struct of ahb2avl_async is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(avldbits);
constant l2ahbw: integer := log2(ahbbits);
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s;
constant wbuf_rdbits: integer := avldbits;
constant wbuf_wabits: integer := 1+l2blen-5;
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := avldbits;
signal request : ddr_request_type;
signal start_tog : std_ulogic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_ulogic;
signal gnd: std_logic_vector(3 downto 0);
signal vcc: std_ulogic;
begin
gnd <= (others => '0');
vcc <= '1';
fe0: ddr2spax_ahb
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
ioaddr => 0,
iomask => 0,
burstlen => burstlen,
nosync => nosync,
ahbbits => ahbbits,
devid => GAISLER_AHB2AVLA,
ddrbits => avldbits/2
)
port map (
rst => rst_ahb,
clk_ahb => clk_ahb,
ahbsi => ahbsi,
ahbso => ahbso,
request => request,
start_tog => start_tog,
response => response,
wbwaddr => wbwaddr,
wbwdata => wbwdata,
wbwrite => wbwrite,
wbwritebig => wbwritebig,
rbraddr => rbraddr,
rbrdata => rbrdata,
hwidth => gnd(0),
beid => gnd(3 downto 0)
);
be0: ahb2avl_async_be
generic map (
avldbits => avldbits,
avlabits => avlabits,
ahbbits => ahbbits,
burstlen => burstlen,
nosync => nosync
)
port map (
rst => rst_avl,
clk => clk_avl,
avlsi => avlsi,
avlso => avlso,
request => request,
start_tog => start_tog,
response => response,
wbraddr => wbraddr,
wbrdata => wbrdata,
rbwaddr => rbwaddr,
rbwdata => rbwdata,
rbwrite => rbwrite
);
wbuf: ddr2buf
generic map (tech => 0, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => 0, testen => 0)
port map ( rclk => clk_avl, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata,
testin => ahbsi.testin);
rbuf: ddr2buf
generic map (tech => 0, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => 0, testen => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_avl, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata,
testin => ahbsi.testin);
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ASL64CoreAndMemory is
PORT (
in0 : IN std_logic_vector(31 DOWNTO 0);
in1 : IN std_logic_vector(31 DOWNTO 0);
in2 : IN std_logic_vector(31 DOWNTO 0);
out0 : OUT std_logic_vector(31 DOWNTO 0);
out1 : OUT std_logic_vector(31 DOWNTO 0);
out2 : OUT std_logic_vector(31 DOWNTO 0);
frame_pointer : IN std_logic_vector(31 DOWNTO 0);
frame_pointer_out : OUT std_logic_vector(31 DOWNTO 0);
rst : IN std_logic;
clck : IN std_logic;
mem_wait : IN std_logic;
mem_push : IN std_logic_vector(31 DOWNTO 0)
);
end ASL64CoreAndMemory;
architecture Structure of ASL64CoreAndMemory is
component GreenDroidASL64Core
PORT (
i00 : IN std_logic_vector(31 DOWNTO 0);
i01 : IN std_logic_vector(31 DOWNTO 0);
i02 : IN std_logic_vector(31 DOWNTO 0);
r00 : OUT std_logic_vector(31 DOWNTO 0);
r01 : OUT std_logic_vector(31 DOWNTO 0);
r02 : OUT std_logic_vector(31 DOWNTO 0);
FP : IN std_logic_vector(31 DOWNTO 0);
FPout : OUT std_logic_vector(31 DOWNTO 0);
M_ADDR : OUT std_logic_vector(31 DOWNTO 0);
M_DATA : INOUT std_logic_vector(31 DOWNTO 0);
M_RD : INOUT std_logic;
M_WR : INOUT std_logic;
M_RDY : IN std_logic;
reset : IN std_logic;
CLK : IN std_logic
);
end component;
component mem
PORT (
M_ADDR : IN std_logic_vector(31 DOWNTO 0);
M_DATA : INOUT std_logic_vector(31 DOWNTO 0);
M_RD : IN std_logic;
M_WR : IN std_logic;
M_RDY : OUT std_logic;
MWAIT : IN std_logic;
MDAT : IN std_logic_vector(31 DOWNTO 0)
);
end component;
signal sig_M_ADDR, sig_M_DATA : std_logic_vector(31 DOWNTO 0);
signal sig_M_RD, sig_M_WR, sig_M_RDY : std_logic;
begin
Core: GreenDroidASL64Core
port map (
i00 => in0, i01 => in1, i02 => in2,
r00 => out0, r01 => out1, r02 => out2,
FP => frame_pointer, FPout => frame_pointer_out,
M_ADDR => sig_M_ADDR,
M_DATA => sig_M_DATA,
M_RD => sig_M_RD,
M_WR => sig_M_WR,
M_RDY => sig_M_RDY,
reset => rst,
CLK => clck
);
mymem: mem
port map(
M_ADDR => sig_M_ADDR,
M_DATA => sig_M_DATA,
M_RD => sig_M_RD,
M_WR => sig_M_WR,
M_RDY => sig_M_RDY,
MWAIT => mem_wait,
MDAT => mem_push
);
end Structure;
|
architecture test of test2 is
shared variable foo, foo2 : bar := baz;
begin end;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY drigmorn1_top IS
PORT(
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
BEGIN
END struct;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : string_methods_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
package string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
);
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural;
function get_string_between_delimeters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string;
function get_procedure_name_from_instance_name(
val : string
) return string;
function get_process_name_from_instance_name(
val : string
) return string;
function get_entity_name_from_instance_name(
val : string
) return string;
function return_string_if_true(
val : string;
return_val : boolean
) return string;
function to_upper(
val : string
) return string;
function fill_string(
val : character;
width : natural
) return string;
function replace_backslash_n_with_lf(
source : string
) return string;
function remove_initial_chars(
source : string;
num : natural
) return string;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc...
constant line_width : natural
) return string;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix)
constant alignment_pos2 : natural;
constant line_width : natural
);
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
);
function replace(
val : string;
target_char : character;
exchange_char : character
) return string;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
);
--========================================================
-- Handle missing overloads from 'standard_additions'
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side := right;
format: t_format_string := AS_IS
) return string;
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural := 0;
justified : side := right
) return string;
function to_string(
val : t_msg_id;
width : natural := 0;
justified : side := right
) return string;
function to_string(
val : t_enabled
) return string;
function to_string(
val : t_attention;
width : natural := 0;
justified : side := right
) return string;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
);
function ascii_to_char(
ascii_pos : integer range 0 to 255;
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character;
function char_to_ascii(
char : character
) return integer;
-- return string with only valid ascii characters
function to_string(
val : string
) return string;
end package string_methods_pkg;
package body string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
) is
begin
assert val
report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > "
& scope & LF & C_LOG_PREFIX & " " & msg & LF
severity severeness;
end;
function to_upper(
val : string
) return string is
variable v_result : string (val'range) := val;
variable char : character;
begin
for i in val'range loop
-- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit)
if ( v_result(i) >= 'a' and v_result(i) <= 'z') then
v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') );
end if;
end loop;
return v_result;
end to_upper;
function fill_string(
val : character;
width : natural
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
else
for i in 1 to width loop
v_result(i) := val;
end loop;
end if;
return v_result;
end fill_string;
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string is
constant val_length : natural := val'length;
variable result : string(1 to width) := (others => ' ');
begin
-- return val if width is too small
if val_length >= width then
if (format = TRUNCATE) then
return val(1 to width);
else
return val;
end if;
end if;
if justified = left then
result(1 to val_length) := val;
elsif justified = right then
result(width - val_length + 1 to width) := val;
end if;
return result;
end function;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'right downto a_vector'left loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) /= '0' and a_vector(i) /= ' ') then
return i;
end if;
end loop;
return result_if_not_found;
end;
function string_contains_char(
val : string;
char : character
) return boolean is
alias a_val : string(1 to val'length) is val;
begin
if (val'length = 0) then
return false;
else
for i in val'left to val'right loop
if (val(i) = char) then
return true;
end if;
end loop;
-- falls through only if not found
return false;
end if;
end;
-- get_*_name
-- Note: for sub-programs the following is given: library:package:procedure:object
-- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object
-- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg'
-- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name)
function get_string_between_delimeters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string is
variable v_left : natural := 0;
variable v_right : natural := 0;
variable v_start : natural := val'length;
variable v_occurrence : natural := 0;
alias a_val : string(1 to val'length) is val;
begin
bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimeters()");
bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimeters()");
loop
-- RIGHT
v_left := 0; -- default
v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0);
if v_right > 0 then -- i.e. found
L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter
if (a_val(i) = delim_left) then
v_left := i;
v_start := i; -- Previous end delimeter could also be a start delimeter for next section
v_occurrence := v_occurrence + 1;
exit L1;
end if;
end loop; -- searching backwards
end if;
if v_right = 0 or v_left = 0 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
if v_occurrence = occurrence then
-- Match
if (v_right - v_left) < 2 then
return ""; -- no chars in between delimeters
else
return a_val(v_left+1 to v_right-1);
end if;
end if;
if v_start < 3 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
end loop; -- Will continue until match or not found
end;
-- ':sbi_tb(func):i_test_harness@test_harness(struct):i2_sbi_vvc@sbi_vvc(struct):p_constructor:instance'
-- ':sbi_tb:i_test_harness:i1_sbi_vvc:p_constructor:instance'
-- - Process name: Search for 2nd last param in path name
-- - Entity name: Search for 3nd last param in path name
--':bitvis_vip_sbi:sbi_bfm_pkg:sbi_write[unsigned,std_logic_vector,string,std_logic,std_logic,unsigned,
-- std_logic,std_logic,std_logic,std_logic_vector,time,string,t_msg_id_panel,t_sbi_config]:msg'
-- - Procedure name: Search for 2nd last param in path name and remove all inside []
function get_procedure_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()");
write(v_line, get_string_between_delimeters(val, ':', '[', RIGHT));
if (string_contains_char(val, '@')) then
write(v_msg_line, string'("Must be called with <sub-program object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()");
return v_line.all;
end;
function get_process_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()");
write(v_line, get_string_between_delimeters(val, ':', ':', RIGHT));
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <process-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()");
return v_line.all;
end;
function get_entity_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()");
if string_contains_char(val, '@') then -- for path with instantiations
write(v_line, get_string_between_delimeters(val, '@', '(', RIGHT));
else -- for path with only a single entity
write(v_line, get_string_between_delimeters(val, ':', '(', RIGHT));
end if;
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()");
return v_line.all;
end;
function adjust_leading_0(
val : string;
format : t_format_zeros := SKIP_LEADING_0
) return string is
alias a_val : string(1 to val'length) is val;
constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1);
begin
if val'length <= 1 then
return val;
end if;
if format = SKIP_LEADING_0 then
return a_val(leftmost_non_zero to val'length);
else
return a_val;
end if;
end function;
function return_string_if_true(
val : string;
return_val : boolean
) return string is
begin
if return_val then
return val;
else
return "";
end if;
end function;
function replace_backslash_n_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_N_AS_LF then
loop
v_source_idx := v_source_idx + 1;
v_dest_idx := v_dest_idx + 1;
if (v_source_idx < source'length) then
if (source(v_source_idx to v_source_idx +1) /= "\n") then
v_dest(v_dest_idx) := source(v_source_idx);
else
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 1; -- Additional increment as two chars (\n) are consumed
if (v_source_idx = source'length) then
exit;
end if;
end if;
else
-- Final character in string
v_dest(v_dest_idx) := source(v_source_idx);
exit;
end if;
end loop;
else
v_dest := source;
v_dest_idx := source'length;
end if;
return v_dest(1 to v_dest_idx);
end if;
end;
function remove_initial_chars(
source : string;
num : natural
) return string is
begin
if source'length <= num then
return "";
else
return source(1 + num to source'right);
end if;
end;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) return string is
variable v_text_lines : line;
variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions
variable v_result_width : natural;
begin
write(v_text_lines, text_string);
wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width);
v_result_width := v_text_lines'length;
bitvis_assert(v_result_width <= v_result'length, FAILURE,
" String is too long after wrapping. Increase v_result string size.", "wrap_lines()");
v_result(1 to v_result_width) := v_text_lines.all;
deallocate(v_text_lines);
return v_result(1 to v_result_width);
end;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
variable v_line_no : natural := 0;
variable v_last_string_wrap : natural := 0;
variable v_min_string_wrap : natural;
variable v_max_string_wrap : natural;
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line: loop -- For every tekstline found in text_lines
v_line_no := v_line_no + 1;
-- Find position to wrap in v_string
if (v_line_no = 1) then
v_min_string_wrap := 1; -- Minimum 1 character of input line
v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width);
write(text_lines, fill_string(' ', alignment_pos1 - 1));
else
v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line
v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width);
write(text_lines, fill_string(' ', alignment_pos2 - 1));
end if;
-- 1. First handle any potential explicit line feed in the current maximum text line
-- Search forward for potential LF
for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part
v_last_string_wrap := i;
next l_line; -- next line
end if;
end loop;
-- 2. Then check if remaining text fits into a single text line
if (v_string_width <= v_max_string_wrap) then
-- No (more) wrapping required
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
exit; -- No more lines
end if;
-- 3. Search for blanks from char after max msg width and downwards (in the left direction)
for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop
if (character(v_string(i)) = ' ') then
write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF
v_last_string_wrap := i;
if (i = v_string_width ) then
exit l_line;
end if;
-- Skip any potential extra blanks in the string
for j in (i+1) to v_string_width loop
if (v_string(j) = ' ') then
v_last_string_wrap := j;
if (j = v_string_width ) then
exit l_line;
end if;
else
write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string
exit;
end if;
end loop;
next l_line; -- next line
end if;
end loop;
-- 4. At this point no LF or blank is found in the searched section of the string.
-- Hence just break the string - and continue.
write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination
v_last_string_wrap := v_max_string_wrap;
end loop;
end;
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
constant prefix_width : natural := prefix'length;
variable v_last_string_wrap : natural := 0;
variable i : natural := 0; -- for indexing v_string
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line : loop
-- 1. Write prefix
write(text_lines, prefix);
-- 2. Write rest of text line (or rest of input line if no LF)
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i));
v_last_string_wrap := i;
exit l_char;
end if;
else
-- 3. Reached end of string. Hence just write the rest.
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
-- But ensure new line with prefix if ending with LF
if (v_string(i) = LF) then
write(text_lines, prefix);
end if;
exit l_char;
end if;
end loop;
if (i = v_string_width) then
exit;
end if;
end loop;
end;
function replace(
val : string;
target_char : character;
exchange_char : character
) return string is
variable result : string(1 to val'length) := val;
begin
for i in val'range loop
if val(i) = target_char then
result(i) := exchange_char;
end if;
end loop;
return result;
end;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
) is
variable v_string : string(1 to text_line'length) := text_line.all;
variable v_string_width : natural := text_line'length;
variable i : natural := 0; -- for indexing v_string
begin
if v_string_width > 0 then
deallocate(text_line); -- empty the line prior to filling it up again
-- 1. Loop through string and replace characters
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = target_char) then
v_string(i) := exchange_char;
end if;
else
-- 2. Reached end of string. Hence just write the new string.
write(text_line, v_string);
exit l_char;
end if;
end loop;
end if;
end;
--========================================================
-- Handle missing overloads from 'standard_additions' + advanced overloads
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
alias a_val : std_logic_vector(val'length - 1 downto 0) is val;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if radix = BIN then
if prefix = INCL_RADIX then
write(v_line, string'("b"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(val), format));
elsif radix = HEX then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_hstring(val), format));
elsif radix = DEC then
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
-- Assuming that val is not signed
if (val'length > 31) then
write(v_line, to_hstring(val) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format));
end if;
elsif radix = HEX_BIN_IF_INVALID then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
end if;
if is_x(val) then
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'("""")); -- terminate hex value
end if;
write(v_line, string'(" (b"""));
write(v_line, adjust_leading_0(to_string(val), format));
write(v_line, string'(""""));
write(v_line, string'(")"));
else
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'(""""));
end if;
end if;
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
begin
return to_string(std_logic_vector(val), radix, format, prefix);
end;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
-- Support negative numbers by _not_ using the slv overload when converting to decimal
if radix = DEC then
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
if (val'length > 32) then
write(v_line, to_string(std_logic_vector(val),radix, format, prefix) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format));
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
else -- No decimal convertion: May be treated as slv, so use the slv overload
return to_string(std_logic_vector(val), radix, format, prefix);
end if;
end;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural := 0;
justified : side := right
) return string is
constant inner_string : string := t_alert_level'image(val);
begin
return to_upper(justify(inner_string, width, justified));
end function;
function to_string(
val : t_msg_id;
width : natural := 0;
justified : side := right
) return string is
constant inner_string : string := t_msg_id'image(val);
begin
return to_upper(justify(inner_string, width, justified));
end function;
function to_string(
val : t_enabled
) return string is
begin
return to_upper(t_enabled'image(val));
end;
function to_string(
val : t_attention;
width : natural := 0;
justified : side := right
) return string is
begin
return to_upper(justify(t_attention'image(val), width, justified));
end;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
) is
variable v_line : line;
variable v_line_copy : line;
variable v_all_ok : boolean := true;
variable v_header : string(1 to 42);
constant prefix : string := C_LOG_PREFIX & " ";
begin
if order = INTERMEDIATE then
v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS ***";
else -- order=FINAL
v_header := "*** FINAL SUMMARY OF ALL ALERTS *** ";
end if;
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
v_header & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
for i in t_alert_level'left to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
for j in t_attention'left to t_attention'right loop
write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT) & " ");
end loop;
if (val(i)(REGARD) = val(i)(EXPECT)) then
write(v_line, " ok " & LF);
else
write(v_line, " *** " & to_string(i,0) & " *** " & LF);
if (i > MANUAL_CHECK) then
v_all_ok := false;
end if;
end if;
end loop;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
-- Print a conclusion when called from the FINAL part of the test sequncer
-- but not when called from in the middle of the test sequence (order=INTERMEDIATE)
if order = FINAL then
if v_all_ok then
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF);
else
write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
end if;
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all & lf); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end;
-- Convert from ASCII to character
-- Inputs:
-- ascii_pos (integer) : ASCII number input
-- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters:
-- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos
-- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable
function ascii_to_char(
ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character is
variable v_printable : boolean := true;
begin
if ascii_pos < 32 or -- NUL, SOH, STX etc
(ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159
v_printable := false;
end if;
if ascii_allow = ALLOW_ALL or
(ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then
return character'val(ascii_pos);
else
return ' '; -- Must return something when invisible control signals
end if;
end;
-- Convert from character to ASCII integer
function char_to_ascii(
char : character
) return integer is
begin
return character'pos(char);
end;
-- return string with only valid ascii characters
function to_string(
val : string
) return string is
variable v_new_string : string(1 to val'length);
variable v_char_idx : natural := 0;
variable v_ascii_pos : natural;
begin
for i in val'range loop
v_ascii_pos := character'pos(val(i));
if v_ascii_pos < 32 or -- NUL, SOH, STX etc
(v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159
-- illegal char
null;
else
-- legal char
v_char_idx := v_char_idx + 1;
v_new_string(v_char_idx) := val(i);
end if;
end loop;
if v_char_idx = 0 then
return "";
else
return v_new_string(1 to v_char_idx);
end if;
end;
end package body string_methods_pkg;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : string_methods_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
package string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
);
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural;
function get_string_between_delimeters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string;
function get_procedure_name_from_instance_name(
val : string
) return string;
function get_process_name_from_instance_name(
val : string
) return string;
function get_entity_name_from_instance_name(
val : string
) return string;
function return_string_if_true(
val : string;
return_val : boolean
) return string;
function to_upper(
val : string
) return string;
function fill_string(
val : character;
width : natural
) return string;
function replace_backslash_n_with_lf(
source : string
) return string;
function remove_initial_chars(
source : string;
num : natural
) return string;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc...
constant line_width : natural
) return string;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix)
constant alignment_pos2 : natural;
constant line_width : natural
);
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
);
function replace(
val : string;
target_char : character;
exchange_char : character
) return string;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
);
--========================================================
-- Handle missing overloads from 'standard_additions'
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side := right;
format: t_format_string := AS_IS
) return string;
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural := 0;
justified : side := right
) return string;
function to_string(
val : t_msg_id;
width : natural := 0;
justified : side := right
) return string;
function to_string(
val : t_enabled
) return string;
function to_string(
val : t_attention;
width : natural := 0;
justified : side := right
) return string;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
);
function ascii_to_char(
ascii_pos : integer range 0 to 255;
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character;
function char_to_ascii(
char : character
) return integer;
-- return string with only valid ascii characters
function to_string(
val : string
) return string;
end package string_methods_pkg;
package body string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
) is
begin
assert val
report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > "
& scope & LF & C_LOG_PREFIX & " " & msg & LF
severity severeness;
end;
function to_upper(
val : string
) return string is
variable v_result : string (val'range) := val;
variable char : character;
begin
for i in val'range loop
-- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit)
if ( v_result(i) >= 'a' and v_result(i) <= 'z') then
v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') );
end if;
end loop;
return v_result;
end to_upper;
function fill_string(
val : character;
width : natural
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
else
for i in 1 to width loop
v_result(i) := val;
end loop;
end if;
return v_result;
end fill_string;
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string is
constant val_length : natural := val'length;
variable result : string(1 to width) := (others => ' ');
begin
-- return val if width is too small
if val_length >= width then
if (format = TRUNCATE) then
return val(1 to width);
else
return val;
end if;
end if;
if justified = left then
result(1 to val_length) := val;
elsif justified = right then
result(width - val_length + 1 to width) := val;
end if;
return result;
end function;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'right downto a_vector'left loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) /= '0' and a_vector(i) /= ' ') then
return i;
end if;
end loop;
return result_if_not_found;
end;
function string_contains_char(
val : string;
char : character
) return boolean is
alias a_val : string(1 to val'length) is val;
begin
if (val'length = 0) then
return false;
else
for i in val'left to val'right loop
if (val(i) = char) then
return true;
end if;
end loop;
-- falls through only if not found
return false;
end if;
end;
-- get_*_name
-- Note: for sub-programs the following is given: library:package:procedure:object
-- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object
-- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg'
-- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name)
function get_string_between_delimeters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string is
variable v_left : natural := 0;
variable v_right : natural := 0;
variable v_start : natural := val'length;
variable v_occurrence : natural := 0;
alias a_val : string(1 to val'length) is val;
begin
bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimeters()");
bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimeters()");
loop
-- RIGHT
v_left := 0; -- default
v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0);
if v_right > 0 then -- i.e. found
L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter
if (a_val(i) = delim_left) then
v_left := i;
v_start := i; -- Previous end delimeter could also be a start delimeter for next section
v_occurrence := v_occurrence + 1;
exit L1;
end if;
end loop; -- searching backwards
end if;
if v_right = 0 or v_left = 0 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
if v_occurrence = occurrence then
-- Match
if (v_right - v_left) < 2 then
return ""; -- no chars in between delimeters
else
return a_val(v_left+1 to v_right-1);
end if;
end if;
if v_start < 3 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
end loop; -- Will continue until match or not found
end;
-- ':sbi_tb(func):i_test_harness@test_harness(struct):i2_sbi_vvc@sbi_vvc(struct):p_constructor:instance'
-- ':sbi_tb:i_test_harness:i1_sbi_vvc:p_constructor:instance'
-- - Process name: Search for 2nd last param in path name
-- - Entity name: Search for 3nd last param in path name
--':bitvis_vip_sbi:sbi_bfm_pkg:sbi_write[unsigned,std_logic_vector,string,std_logic,std_logic,unsigned,
-- std_logic,std_logic,std_logic,std_logic_vector,time,string,t_msg_id_panel,t_sbi_config]:msg'
-- - Procedure name: Search for 2nd last param in path name and remove all inside []
function get_procedure_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()");
write(v_line, get_string_between_delimeters(val, ':', '[', RIGHT));
if (string_contains_char(val, '@')) then
write(v_msg_line, string'("Must be called with <sub-program object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()");
return v_line.all;
end;
function get_process_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()");
write(v_line, get_string_between_delimeters(val, ':', ':', RIGHT));
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <process-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()");
return v_line.all;
end;
function get_entity_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()");
if string_contains_char(val, '@') then -- for path with instantiations
write(v_line, get_string_between_delimeters(val, '@', '(', RIGHT));
else -- for path with only a single entity
write(v_line, get_string_between_delimeters(val, ':', '(', RIGHT));
end if;
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()");
return v_line.all;
end;
function adjust_leading_0(
val : string;
format : t_format_zeros := SKIP_LEADING_0
) return string is
alias a_val : string(1 to val'length) is val;
constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1);
begin
if val'length <= 1 then
return val;
end if;
if format = SKIP_LEADING_0 then
return a_val(leftmost_non_zero to val'length);
else
return a_val;
end if;
end function;
function return_string_if_true(
val : string;
return_val : boolean
) return string is
begin
if return_val then
return val;
else
return "";
end if;
end function;
function replace_backslash_n_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_N_AS_LF then
loop
v_source_idx := v_source_idx + 1;
v_dest_idx := v_dest_idx + 1;
if (v_source_idx < source'length) then
if (source(v_source_idx to v_source_idx +1) /= "\n") then
v_dest(v_dest_idx) := source(v_source_idx);
else
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 1; -- Additional increment as two chars (\n) are consumed
if (v_source_idx = source'length) then
exit;
end if;
end if;
else
-- Final character in string
v_dest(v_dest_idx) := source(v_source_idx);
exit;
end if;
end loop;
else
v_dest := source;
v_dest_idx := source'length;
end if;
return v_dest(1 to v_dest_idx);
end if;
end;
function remove_initial_chars(
source : string;
num : natural
) return string is
begin
if source'length <= num then
return "";
else
return source(1 + num to source'right);
end if;
end;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) return string is
variable v_text_lines : line;
variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions
variable v_result_width : natural;
begin
write(v_text_lines, text_string);
wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width);
v_result_width := v_text_lines'length;
bitvis_assert(v_result_width <= v_result'length, FAILURE,
" String is too long after wrapping. Increase v_result string size.", "wrap_lines()");
v_result(1 to v_result_width) := v_text_lines.all;
deallocate(v_text_lines);
return v_result(1 to v_result_width);
end;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
variable v_line_no : natural := 0;
variable v_last_string_wrap : natural := 0;
variable v_min_string_wrap : natural;
variable v_max_string_wrap : natural;
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line: loop -- For every tekstline found in text_lines
v_line_no := v_line_no + 1;
-- Find position to wrap in v_string
if (v_line_no = 1) then
v_min_string_wrap := 1; -- Minimum 1 character of input line
v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width);
write(text_lines, fill_string(' ', alignment_pos1 - 1));
else
v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line
v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width);
write(text_lines, fill_string(' ', alignment_pos2 - 1));
end if;
-- 1. First handle any potential explicit line feed in the current maximum text line
-- Search forward for potential LF
for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part
v_last_string_wrap := i;
next l_line; -- next line
end if;
end loop;
-- 2. Then check if remaining text fits into a single text line
if (v_string_width <= v_max_string_wrap) then
-- No (more) wrapping required
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
exit; -- No more lines
end if;
-- 3. Search for blanks from char after max msg width and downwards (in the left direction)
for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop
if (character(v_string(i)) = ' ') then
write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF
v_last_string_wrap := i;
if (i = v_string_width ) then
exit l_line;
end if;
-- Skip any potential extra blanks in the string
for j in (i+1) to v_string_width loop
if (v_string(j) = ' ') then
v_last_string_wrap := j;
if (j = v_string_width ) then
exit l_line;
end if;
else
write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string
exit;
end if;
end loop;
next l_line; -- next line
end if;
end loop;
-- 4. At this point no LF or blank is found in the searched section of the string.
-- Hence just break the string - and continue.
write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination
v_last_string_wrap := v_max_string_wrap;
end loop;
end;
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
constant prefix_width : natural := prefix'length;
variable v_last_string_wrap : natural := 0;
variable i : natural := 0; -- for indexing v_string
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line : loop
-- 1. Write prefix
write(text_lines, prefix);
-- 2. Write rest of text line (or rest of input line if no LF)
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i));
v_last_string_wrap := i;
exit l_char;
end if;
else
-- 3. Reached end of string. Hence just write the rest.
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
-- But ensure new line with prefix if ending with LF
if (v_string(i) = LF) then
write(text_lines, prefix);
end if;
exit l_char;
end if;
end loop;
if (i = v_string_width) then
exit;
end if;
end loop;
end;
function replace(
val : string;
target_char : character;
exchange_char : character
) return string is
variable result : string(1 to val'length) := val;
begin
for i in val'range loop
if val(i) = target_char then
result(i) := exchange_char;
end if;
end loop;
return result;
end;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
) is
variable v_string : string(1 to text_line'length) := text_line.all;
variable v_string_width : natural := text_line'length;
variable i : natural := 0; -- for indexing v_string
begin
if v_string_width > 0 then
deallocate(text_line); -- empty the line prior to filling it up again
-- 1. Loop through string and replace characters
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = target_char) then
v_string(i) := exchange_char;
end if;
else
-- 2. Reached end of string. Hence just write the new string.
write(text_line, v_string);
exit l_char;
end if;
end loop;
end if;
end;
--========================================================
-- Handle missing overloads from 'standard_additions' + advanced overloads
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
alias a_val : std_logic_vector(val'length - 1 downto 0) is val;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if radix = BIN then
if prefix = INCL_RADIX then
write(v_line, string'("b"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(val), format));
elsif radix = HEX then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_hstring(val), format));
elsif radix = DEC then
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
-- Assuming that val is not signed
if (val'length > 31) then
write(v_line, to_hstring(val) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format));
end if;
elsif radix = HEX_BIN_IF_INVALID then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
end if;
if is_x(val) then
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'("""")); -- terminate hex value
end if;
write(v_line, string'(" (b"""));
write(v_line, adjust_leading_0(to_string(val), format));
write(v_line, string'(""""));
write(v_line, string'(")"));
else
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'(""""));
end if;
end if;
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
begin
return to_string(std_logic_vector(val), radix, format, prefix);
end;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
-- Support negative numbers by _not_ using the slv overload when converting to decimal
if radix = DEC then
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
if (val'length > 32) then
write(v_line, to_string(std_logic_vector(val),radix, format, prefix) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format));
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
else -- No decimal convertion: May be treated as slv, so use the slv overload
return to_string(std_logic_vector(val), radix, format, prefix);
end if;
end;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural := 0;
justified : side := right
) return string is
constant inner_string : string := t_alert_level'image(val);
begin
return to_upper(justify(inner_string, width, justified));
end function;
function to_string(
val : t_msg_id;
width : natural := 0;
justified : side := right
) return string is
constant inner_string : string := t_msg_id'image(val);
begin
return to_upper(justify(inner_string, width, justified));
end function;
function to_string(
val : t_enabled
) return string is
begin
return to_upper(t_enabled'image(val));
end;
function to_string(
val : t_attention;
width : natural := 0;
justified : side := right
) return string is
begin
return to_upper(justify(t_attention'image(val), width, justified));
end;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
) is
variable v_line : line;
variable v_line_copy : line;
variable v_all_ok : boolean := true;
variable v_header : string(1 to 42);
constant prefix : string := C_LOG_PREFIX & " ";
begin
if order = INTERMEDIATE then
v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS ***";
else -- order=FINAL
v_header := "*** FINAL SUMMARY OF ALL ALERTS *** ";
end if;
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
v_header & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
for i in t_alert_level'left to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
for j in t_attention'left to t_attention'right loop
write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT) & " ");
end loop;
if (val(i)(REGARD) = val(i)(EXPECT)) then
write(v_line, " ok " & LF);
else
write(v_line, " *** " & to_string(i,0) & " *** " & LF);
if (i > MANUAL_CHECK) then
v_all_ok := false;
end if;
end if;
end loop;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
-- Print a conclusion when called from the FINAL part of the test sequncer
-- but not when called from in the middle of the test sequence (order=INTERMEDIATE)
if order = FINAL then
if v_all_ok then
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF);
else
write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
end if;
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all & lf); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end;
-- Convert from ASCII to character
-- Inputs:
-- ascii_pos (integer) : ASCII number input
-- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters:
-- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos
-- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable
function ascii_to_char(
ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character is
variable v_printable : boolean := true;
begin
if ascii_pos < 32 or -- NUL, SOH, STX etc
(ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159
v_printable := false;
end if;
if ascii_allow = ALLOW_ALL or
(ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then
return character'val(ascii_pos);
else
return ' '; -- Must return something when invisible control signals
end if;
end;
-- Convert from character to ASCII integer
function char_to_ascii(
char : character
) return integer is
begin
return character'pos(char);
end;
-- return string with only valid ascii characters
function to_string(
val : string
) return string is
variable v_new_string : string(1 to val'length);
variable v_char_idx : natural := 0;
variable v_ascii_pos : natural;
begin
for i in val'range loop
v_ascii_pos := character'pos(val(i));
if v_ascii_pos < 32 or -- NUL, SOH, STX etc
(v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159
-- illegal char
null;
else
-- legal char
v_char_idx := v_char_idx + 1;
v_new_string(v_char_idx) := val(i);
end if;
end loop;
if v_char_idx = 0 then
return "";
else
return v_new_string(1 to v_char_idx);
end if;
end;
end package body string_methods_pkg;
|
--========================================================================================================================
-- Copyright (c) 2015 by Bitvis AS. All rights reserved.
-- A free license is hereby granted, free of charge, to any person obtaining
-- a copy of this VHDL code and associated documentation files (for 'Bitvis Utility Library'),
-- to use, copy, modify, merge, publish and/or distribute - subject to the following conditions:
-- - This copyright notice shall be included as is in all copies or substantial portions of the code and documentation
-- - The files included in Bitvis Utility Library may only be used as a part of this library as a whole
-- - The License file may not be modified
-- - The calls in the code to the license file ('show_license') may not be removed or modified.
-- - No other conditions whatsoever may be added to those of this License
-- BITVIS UTILITY LIBRARY AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH BITVIS UTILITY LIBRARY.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis Utility Library : string_methods_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use ieee_proposed.std_logic_1164_additions.all;
use ieee_proposed.standard_textio_additions.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
package string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
);
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural;
function get_string_between_delimeters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string;
function get_procedure_name_from_instance_name(
val : string
) return string;
function get_process_name_from_instance_name(
val : string
) return string;
function get_entity_name_from_instance_name(
val : string
) return string;
function return_string_if_true(
val : string;
return_val : boolean
) return string;
function to_upper(
val : string
) return string;
function fill_string(
val : character;
width : natural
) return string;
function replace_backslash_n_with_lf(
source : string
) return string;
function remove_initial_chars(
source : string;
num : natural
) return string;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc...
constant line_width : natural
) return string;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix)
constant alignment_pos2 : natural;
constant line_width : natural
);
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
);
function replace(
val : string;
target_char : character;
exchange_char : character
) return string;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
);
--========================================================
-- Handle missing overloads from 'standard_additions'
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side := right;
format: t_format_string := AS_IS
) return string;
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural := 0;
justified : side := right
) return string;
function to_string(
val : t_msg_id;
width : natural := 0;
justified : side := right
) return string;
function to_string(
val : t_enabled
) return string;
function to_string(
val : t_attention;
width : natural := 0;
justified : side := right
) return string;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
);
function ascii_to_char(
ascii_pos : integer range 0 to 255;
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character;
function char_to_ascii(
char : character
) return integer;
-- return string with only valid ascii characters
function to_string(
val : string
) return string;
end package string_methods_pkg;
package body string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
) is
begin
assert val
report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > "
& scope & LF & C_LOG_PREFIX & " " & msg & LF
severity severeness;
end;
function to_upper(
val : string
) return string is
variable v_result : string (val'range) := val;
variable char : character;
begin
for i in val'range loop
-- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit)
if ( v_result(i) >= 'a' and v_result(i) <= 'z') then
v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') );
end if;
end loop;
return v_result;
end to_upper;
function fill_string(
val : character;
width : natural
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
else
for i in 1 to width loop
v_result(i) := val;
end loop;
end if;
return v_result;
end fill_string;
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string is
constant val_length : natural := val'length;
variable result : string(1 to width) := (others => ' ');
begin
-- return val if width is too small
if val_length >= width then
if (format = TRUNCATE) then
return val(1 to width);
else
return val;
end if;
end if;
if justified = left then
result(1 to val_length) := val;
elsif justified = right then
result(width - val_length + 1 to width) := val;
end if;
return result;
end function;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'right downto a_vector'left loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) /= '0' and a_vector(i) /= ' ') then
return i;
end if;
end loop;
return result_if_not_found;
end;
function string_contains_char(
val : string;
char : character
) return boolean is
alias a_val : string(1 to val'length) is val;
begin
if (val'length = 0) then
return false;
else
for i in val'left to val'right loop
if (val(i) = char) then
return true;
end if;
end loop;
-- falls through only if not found
return false;
end if;
end;
-- get_*_name
-- Note: for sub-programs the following is given: library:package:procedure:object
-- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object
-- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg'
-- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name)
function get_string_between_delimeters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string is
variable v_left : natural := 0;
variable v_right : natural := 0;
variable v_start : natural := val'length;
variable v_occurrence : natural := 0;
alias a_val : string(1 to val'length) is val;
begin
bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimeters()");
bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimeters()");
loop
-- RIGHT
v_left := 0; -- default
v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0);
if v_right > 0 then -- i.e. found
L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter
if (a_val(i) = delim_left) then
v_left := i;
v_start := i; -- Previous end delimeter could also be a start delimeter for next section
v_occurrence := v_occurrence + 1;
exit L1;
end if;
end loop; -- searching backwards
end if;
if v_right = 0 or v_left = 0 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
if v_occurrence = occurrence then
-- Match
if (v_right - v_left) < 2 then
return ""; -- no chars in between delimeters
else
return a_val(v_left+1 to v_right-1);
end if;
end if;
if v_start < 3 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
end loop; -- Will continue until match or not found
end;
-- ':sbi_tb(func):i_test_harness@test_harness(struct):i2_sbi_vvc@sbi_vvc(struct):p_constructor:instance'
-- ':sbi_tb:i_test_harness:i1_sbi_vvc:p_constructor:instance'
-- - Process name: Search for 2nd last param in path name
-- - Entity name: Search for 3nd last param in path name
--':bitvis_vip_sbi:sbi_bfm_pkg:sbi_write[unsigned,std_logic_vector,string,std_logic,std_logic,unsigned,
-- std_logic,std_logic,std_logic,std_logic_vector,time,string,t_msg_id_panel,t_sbi_config]:msg'
-- - Procedure name: Search for 2nd last param in path name and remove all inside []
function get_procedure_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()");
write(v_line, get_string_between_delimeters(val, ':', '[', RIGHT));
if (string_contains_char(val, '@')) then
write(v_msg_line, string'("Must be called with <sub-program object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()");
return v_line.all;
end;
function get_process_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()");
write(v_line, get_string_between_delimeters(val, ':', ':', RIGHT));
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <process-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()");
return v_line.all;
end;
function get_entity_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()");
if string_contains_char(val, '@') then -- for path with instantiations
write(v_line, get_string_between_delimeters(val, '@', '(', RIGHT));
else -- for path with only a single entity
write(v_line, get_string_between_delimeters(val, ':', '(', RIGHT));
end if;
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()");
return v_line.all;
end;
function adjust_leading_0(
val : string;
format : t_format_zeros := SKIP_LEADING_0
) return string is
alias a_val : string(1 to val'length) is val;
constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1);
begin
if val'length <= 1 then
return val;
end if;
if format = SKIP_LEADING_0 then
return a_val(leftmost_non_zero to val'length);
else
return a_val;
end if;
end function;
function return_string_if_true(
val : string;
return_val : boolean
) return string is
begin
if return_val then
return val;
else
return "";
end if;
end function;
function replace_backslash_n_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_N_AS_LF then
loop
v_source_idx := v_source_idx + 1;
v_dest_idx := v_dest_idx + 1;
if (v_source_idx < source'length) then
if (source(v_source_idx to v_source_idx +1) /= "\n") then
v_dest(v_dest_idx) := source(v_source_idx);
else
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 1; -- Additional increment as two chars (\n) are consumed
if (v_source_idx = source'length) then
exit;
end if;
end if;
else
-- Final character in string
v_dest(v_dest_idx) := source(v_source_idx);
exit;
end if;
end loop;
else
v_dest := source;
v_dest_idx := source'length;
end if;
return v_dest(1 to v_dest_idx);
end if;
end;
function remove_initial_chars(
source : string;
num : natural
) return string is
begin
if source'length <= num then
return "";
else
return source(1 + num to source'right);
end if;
end;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) return string is
variable v_text_lines : line;
variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions
variable v_result_width : natural;
begin
write(v_text_lines, text_string);
wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width);
v_result_width := v_text_lines'length;
bitvis_assert(v_result_width <= v_result'length, FAILURE,
" String is too long after wrapping. Increase v_result string size.", "wrap_lines()");
v_result(1 to v_result_width) := v_text_lines.all;
deallocate(v_text_lines);
return v_result(1 to v_result_width);
end;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
variable v_line_no : natural := 0;
variable v_last_string_wrap : natural := 0;
variable v_min_string_wrap : natural;
variable v_max_string_wrap : natural;
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line: loop -- For every tekstline found in text_lines
v_line_no := v_line_no + 1;
-- Find position to wrap in v_string
if (v_line_no = 1) then
v_min_string_wrap := 1; -- Minimum 1 character of input line
v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width);
write(text_lines, fill_string(' ', alignment_pos1 - 1));
else
v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line
v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width);
write(text_lines, fill_string(' ', alignment_pos2 - 1));
end if;
-- 1. First handle any potential explicit line feed in the current maximum text line
-- Search forward for potential LF
for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part
v_last_string_wrap := i;
next l_line; -- next line
end if;
end loop;
-- 2. Then check if remaining text fits into a single text line
if (v_string_width <= v_max_string_wrap) then
-- No (more) wrapping required
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
exit; -- No more lines
end if;
-- 3. Search for blanks from char after max msg width and downwards (in the left direction)
for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop
if (character(v_string(i)) = ' ') then
write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF
v_last_string_wrap := i;
if (i = v_string_width ) then
exit l_line;
end if;
-- Skip any potential extra blanks in the string
for j in (i+1) to v_string_width loop
if (v_string(j) = ' ') then
v_last_string_wrap := j;
if (j = v_string_width ) then
exit l_line;
end if;
else
write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string
exit;
end if;
end loop;
next l_line; -- next line
end if;
end loop;
-- 4. At this point no LF or blank is found in the searched section of the string.
-- Hence just break the string - and continue.
write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination
v_last_string_wrap := v_max_string_wrap;
end loop;
end;
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
) is
variable v_string : string(1 to text_lines'length) := text_lines.all;
variable v_string_width : natural := text_lines'length;
constant prefix_width : natural := prefix'length;
variable v_last_string_wrap : natural := 0;
variable i : natural := 0; -- for indexing v_string
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line : loop
-- 1. Write prefix
write(text_lines, prefix);
-- 2. Write rest of text line (or rest of input line if no LF)
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i));
v_last_string_wrap := i;
exit l_char;
end if;
else
-- 3. Reached end of string. Hence just write the rest.
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
-- But ensure new line with prefix if ending with LF
if (v_string(i) = LF) then
write(text_lines, prefix);
end if;
exit l_char;
end if;
end loop;
if (i = v_string_width) then
exit;
end if;
end loop;
end;
function replace(
val : string;
target_char : character;
exchange_char : character
) return string is
variable result : string(1 to val'length) := val;
begin
for i in val'range loop
if val(i) = target_char then
result(i) := exchange_char;
end if;
end loop;
return result;
end;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
) is
variable v_string : string(1 to text_line'length) := text_line.all;
variable v_string_width : natural := text_line'length;
variable i : natural := 0; -- for indexing v_string
begin
if v_string_width > 0 then
deallocate(text_line); -- empty the line prior to filling it up again
-- 1. Loop through string and replace characters
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = target_char) then
v_string(i) := exchange_char;
end if;
else
-- 2. Reached end of string. Hence just write the new string.
write(text_line, v_string);
exit l_char;
end if;
end loop;
end if;
end;
--========================================================
-- Handle missing overloads from 'standard_additions' + advanced overloads
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
alias a_val : std_logic_vector(val'length - 1 downto 0) is val;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if radix = BIN then
if prefix = INCL_RADIX then
write(v_line, string'("b"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(val), format));
elsif radix = HEX then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_hstring(val), format));
elsif radix = DEC then
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
-- Assuming that val is not signed
if (val'length > 31) then
write(v_line, to_hstring(val) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format));
end if;
elsif radix = HEX_BIN_IF_INVALID then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
end if;
if is_x(val) then
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'("""")); -- terminate hex value
end if;
write(v_line, string'(" (b"""));
write(v_line, adjust_leading_0(to_string(val), format));
write(v_line, string'(""""));
write(v_line, string'(")"));
else
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'(""""));
end if;
end if;
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
begin
return to_string(std_logic_vector(val), radix, format, prefix);
end;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := AS_IS; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
-- Support negative numbers by _not_ using the slv overload when converting to decimal
if radix = DEC then
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
if (val'length > 32) then
write(v_line, to_string(std_logic_vector(val),radix, format, prefix) & " (too wide to be converted to integer)" );
else
write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format));
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
else -- No decimal convertion: May be treated as slv, so use the slv overload
return to_string(std_logic_vector(val), radix, format, prefix);
end if;
end;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural := 0;
justified : side := right
) return string is
constant inner_string : string := t_alert_level'image(val);
begin
return to_upper(justify(inner_string, width, justified));
end function;
function to_string(
val : t_msg_id;
width : natural := 0;
justified : side := right
) return string is
constant inner_string : string := t_msg_id'image(val);
begin
return to_upper(justify(inner_string, width, justified));
end function;
function to_string(
val : t_enabled
) return string is
begin
return to_upper(t_enabled'image(val));
end;
function to_string(
val : t_attention;
width : natural := 0;
justified : side := right
) return string is
begin
return to_upper(justify(t_attention'image(val), width, justified));
end;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
) is
variable v_line : line;
variable v_line_copy : line;
variable v_all_ok : boolean := true;
variable v_header : string(1 to 42);
constant prefix : string := C_LOG_PREFIX & " ";
begin
if order = INTERMEDIATE then
v_header := "*** INTERMEDIATE SUMMARY OF ALL ALERTS ***";
else -- order=FINAL
v_header := "*** FINAL SUMMARY OF ALL ALERTS *** ";
end if;
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
v_header & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
for i in t_alert_level'left to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
for j in t_attention'left to t_attention'right loop
write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT) & " ");
end loop;
if (val(i)(REGARD) = val(i)(EXPECT)) then
write(v_line, " ok " & LF);
else
write(v_line, " *** " & to_string(i,0) & " *** " & LF);
if (i > MANUAL_CHECK) then
v_all_ok := false;
end if;
end if;
end loop;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
-- Print a conclusion when called from the FINAL part of the test sequncer
-- but not when called from in the middle of the test sequence (order=INTERMEDIATE)
if order = FINAL then
if v_all_ok then
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF);
else
write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
end if;
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all & lf); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
end;
-- Convert from ASCII to character
-- Inputs:
-- ascii_pos (integer) : ASCII number input
-- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters:
-- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos
-- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable
function ascii_to_char(
ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character is
variable v_printable : boolean := true;
begin
if ascii_pos < 32 or -- NUL, SOH, STX etc
(ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159
v_printable := false;
end if;
if ascii_allow = ALLOW_ALL or
(ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then
return character'val(ascii_pos);
else
return ' '; -- Must return something when invisible control signals
end if;
end;
-- Convert from character to ASCII integer
function char_to_ascii(
char : character
) return integer is
begin
return character'pos(char);
end;
-- return string with only valid ascii characters
function to_string(
val : string
) return string is
variable v_new_string : string(1 to val'length);
variable v_char_idx : natural := 0;
variable v_ascii_pos : natural;
begin
for i in val'range loop
v_ascii_pos := character'pos(val(i));
if v_ascii_pos < 32 or -- NUL, SOH, STX etc
(v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159
-- illegal char
null;
else
-- legal char
v_char_idx := v_char_idx + 1;
v_new_string(v_char_idx) := val(i);
end if;
end loop;
if v_char_idx = 0 then
return "";
else
return v_new_string(1 to v_char_idx);
end if;
end;
end package body string_methods_pkg;
|
entity bounds15 is
end entity;
architecture test of bounds15 is
function fact(n : natural) return positive is
begin
if n = 0 then
return 1;
else
return n * fact(n - 1);
end if;
end function;
begin
process is
variable x : integer;
begin
x := 5;
report integer'image(fact(x));
x := 0;
report integer'image(fact(x));
x := -1;
report integer'image(fact(x)); -- Error
wait;
end process;
end architecture;
|
entity bounds15 is
end entity;
architecture test of bounds15 is
function fact(n : natural) return positive is
begin
if n = 0 then
return 1;
else
return n * fact(n - 1);
end if;
end function;
begin
process is
variable x : integer;
begin
x := 5;
report integer'image(fact(x));
x := 0;
report integer'image(fact(x));
x := -1;
report integer'image(fact(x)); -- Error
wait;
end process;
end architecture;
|
entity bounds15 is
end entity;
architecture test of bounds15 is
function fact(n : natural) return positive is
begin
if n = 0 then
return 1;
else
return n * fact(n - 1);
end if;
end function;
begin
process is
variable x : integer;
begin
x := 5;
report integer'image(fact(x));
x := 0;
report integer'image(fact(x));
x := -1;
report integer'image(fact(x)); -- Error
wait;
end process;
end architecture;
|
entity bounds15 is
end entity;
architecture test of bounds15 is
function fact(n : natural) return positive is
begin
if n = 0 then
return 1;
else
return n * fact(n - 1);
end if;
end function;
begin
process is
variable x : integer;
begin
x := 5;
report integer'image(fact(x));
x := 0;
report integer'image(fact(x));
x := -1;
report integer'image(fact(x)); -- Error
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.memory_types.all;
entity VGA_ROM is
generic (
contents : vga_memory
);
port (
clock : in std_logic;
enable : in std_logic;
address : in natural range vga_memory'range;
data : out std_logic_vector(7 downto 0)
);
end entity VGA_ROM;
architecture behavioural of VGA_ROM is
constant storage : vga_memory := contents;
begin
process(clock)
begin
if rising_edge(clock) then
if enable = '1' then
data <= storage(address);
else
data <= (others => '0');
end if;
end if;
end process;
end behavioural;
|
library ieee;
use ieee.std_logic_1164.all;
use work.rec04_pkg.all;
entity rec04 is
port (inp : std_logic;
o : out myrec);
end rec04;
architecture behav of rec04 is
begin
o.b <= not inp;
o.a <= "0001" when inp = '1' else "1000";
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sdram_driver is
port(
clk_100: in std_logic;
res: in std_logic;
address: in std_logic_vector(22 downto 0);
data_in: in std_logic_vector(31 downto 0);
data_out: out std_logic_vector(31 downto 0);
busy: out std_logic;
wr_req: in std_logic;
rd_req: in std_logic;
data_out_ready: out std_logic;
ack: out std_logic;
sdram_ras_n: out std_logic;
sdram_cas_n: out std_logic;
sdram_we_n: out std_logic;
sdram_addr: out std_logic_vector(12 downto 0);
sdram_ba: out std_logic_vector(1 downto 0);
sdram_data: inout std_logic_vector(7 downto 0)
);
end entity sdram_driver;
architecture sdram_driver_arch of sdram_driver is
component data_io_buff is
port(
datain: in std_logic_vector (15 downto 0);
oe: in std_logic_vector (15 downto 0);
dataio: inout std_logic_vector (15 downto 0);
dataout: out std_logic_vector (15 downto 0)
);
end component;
--data from sdram (registered)
signal captured_data: std_logic_vector(7 downto 0);
--oe control signal for bidir buff
signal bidir_buff_oe, bidir_buff_oe_buff: std_logic;
--datainput to bidir buff
signal bidir_buff_datain, bidir_buff_datain_buff: std_logic_vector(7 downto 0);
--unregistered output from bidirbuff
signal sdram_dataout: std_logic_vector(7 downto 0);
--these signals are controling control outputs for sdram
signal sdram_addr_unbuff: std_logic_vector(12 downto 0);
signal sdram_ba_unbuff: std_logic_vector(1 downto 0);
signal sdram_control: std_logic_vector(2 downto 0);
--comands for sdram maped into vectors
constant com_device_deselect: std_logic_vector(2 downto 0):= "000";
constant com_no_operation: std_logic_vector(2 downto 0):= "111";
constant com_burst_stop: std_logic_vector(2 downto 0):= "110";
constant com_read: std_logic_vector(2 downto 0):= "101"; --bank and A0..A9 must be valid; A10 must be low
constant com_read_precharge: std_logic_vector(2 downto 0):= "101"; --A10 must be high
constant com_write: std_logic_vector(2 downto 0):= "100"; --A10 must be low
constant com_write_precharge: std_logic_vector(2 downto 0):= "100";--A10 must be high
constant com_bank_active: std_logic_vector(2 downto 0):= "011"; --bank and addr must be valid
constant com_precharge_select_bank: std_logic_vector(2 downto 0):= "010";--bank valid and A10 low; rest of addr dont care
constant com_precharge_all_banks: std_logic_vector(2 downto 0):= "010"; --A10 high; others dont care
constant com_cbr_auto_refresh: std_logic_vector(2 downto 0):= "001"; --everything dont care
constant com_mode_reg_set: std_logic_vector(2 downto 0):= "000"; --bank low; A10 low; A0..A9 valid
--put this constant on address bus it is configuration register
-- CAS = 2; burst = 4 words;
constant mode_register: std_logic_vector(12 downto 0) := "0000000100010";
--this signal is we into output register
signal write_input_data_reg: std_logic;
--clean refresh counter
signal refresh_counter_clean: std_logic;
--signalize refresh need
signal force_refresh: std_logic;
--for init seq
signal init_counter_val: unsigned(17 downto 0);
signal init_counter_clean: std_logic; -- clean startup counter
--main sdram FSM
type sdram_fsm_state_type is (
init_delay, init_precharge, init_precharge_wait,
init_refresh_0, init_refresh_1,
init_refresh_2, init_refresh_3,
init_refresh_4, init_refresh_5,
init_refresh_6, init_refresh_7,
init_refresh_0_wait, init_refresh_1_wait,
init_refresh_2_wait, init_refresh_3_wait,
init_refresh_4_wait, init_refresh_5_wait,
init_refresh_6_wait, init_refresh_7_wait,
init_mode_reg, init_mode_reg_wait, idle,
autorefresh, autorefresh_wait,
bank_active, bank_active_nop0, bank_active_nop1,
write_data, write_nop_0, write_nop_1, write_nop_2, write_nop_3, write_nop_4, write_nop_5, write_nop_6,
read_command, read_nop_0, read_nop_1, read_nop_2, read_nop_3, read_nop_4, read_nop_5, read_nop_6, read_completed
);
signal fsm_state: sdram_fsm_state_type := init_delay;
attribute FSM_ENCODING : string;
attribute FSM_ENCODING of fsm_state : signal is "ONE-HOT";
--address parts
signal address_ba: std_logic_vector(1 downto 0);
signal address_row: std_logic_vector(12 downto 0);
signal address_col: std_logic_vector(9 downto 0);
--signals from command register
signal cmd_wr_req: std_logic;
--~ signal cmd_rd_req: std_logic;
signal cmd_address: std_logic_vector(22 downto 0);
signal cmd_data_in: std_logic_vector(31 downto 0);
signal write_cmd_reg: std_logic;
begin
--split address into multiple parts
address_ba <= cmd_address(22 downto 21);
address_row <= cmd_address(20 downto 8);
address_col <= cmd_address(7 downto 0) & "00";
--bidirectional buffer for DQ pins
sdram_dataout <= sdram_data;
sdram_data <= bidir_buff_datain_buff when bidir_buff_oe_buff = '1' else (others => 'Z');
process(clk_100) is
variable bidir_buff_oe_var: std_logic := '0';
begin
if rising_edge(clk_100) then
if res = '1' then
bidir_buff_oe_var := '0';
else
bidir_buff_oe_var := bidir_buff_oe;
end if;
end if;
bidir_buff_oe_buff <= bidir_buff_oe_var;
end process;
process(clk_100) is
variable bidir_buff_datain_var: std_logic_vector(7 downto 0) := x"00";
begin
if rising_edge(clk_100) then
if res = '1' then
bidir_buff_datain_var := (others => '0');
else
bidir_buff_datain_var := bidir_buff_datain;
end if;
end if;
bidir_buff_datain_buff <= bidir_buff_datain_var;
end process;
--register input data from sdram
process(clk_100) is
variable captured_data_var: std_logic_vector(7 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
captured_data_var := (others => '0');
else
captured_data_var := sdram_dataout;
end if;
end if;
captured_data <= captured_data_var;
end process;
--this is register for dataout
process(clk_100) is
variable input_data_register_var_low: std_logic_vector(7 downto 0) := (others => '0');
variable input_data_register_var_mlow: std_logic_vector(7 downto 0) := (others => '0');
variable input_data_register_var_mhigh: std_logic_vector(7 downto 0) := (others => '0');
variable input_data_register_var_high: std_logic_vector(7 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
input_data_register_var_low := (others => '0');
input_data_register_var_mlow := (others => '0');
input_data_register_var_mhigh := (others => '0');
input_data_register_var_high := (others => '0');
elsif write_input_data_reg = '1' then
input_data_register_var_high := input_data_register_var_mhigh;
input_data_register_var_mhigh := input_data_register_var_mlow;
input_data_register_var_mlow := input_data_register_var_low;
input_data_register_var_low := captured_data;
end if;
end if;
data_out <= input_data_register_var_high & input_data_register_var_mhigh & input_data_register_var_mlow & input_data_register_var_low;
end process;
--register all outputs
process(clk_100) is
variable sdram_ras_n_var: std_logic := '1';
variable sdram_cas_n_var: std_logic := '1';
variable sdram_we_n_var: std_logic := '1';
variable sdram_addr_var: std_logic_vector(12 downto 0) := (others => '0');
variable sdram_ba_var: std_logic_vector(1 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
sdram_ras_n_var := '1';
sdram_cas_n_var := '1';
sdram_we_n_var := '1';
sdram_addr_var := (others => '0');
sdram_ba_var := (others => '0');
else
sdram_addr_var := sdram_addr_unbuff;
sdram_ba_var := sdram_ba_unbuff;
sdram_ras_n_var := sdram_control(2);
sdram_cas_n_var := sdram_control(1);
sdram_we_n_var := sdram_control(0);
end if;
end if;
sdram_ras_n <= sdram_ras_n_var;
sdram_cas_n <= sdram_cas_n_var;
sdram_we_n <= sdram_we_n_var;
sdram_addr <= sdram_addr_var;
sdram_ba <= sdram_ba_var;
end process;
--refresh counter
process(clk_100) is
variable counter_var: unsigned(12 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' or refresh_counter_clean = '1' then
counter_var := (others => '0');
else
counter_var := counter_var + 1;
end if;
end if;
--refresh is needed each 7.8125 us
--this call it each 4.096 us
force_refresh <= counter_var(12);
end process;
--startup counter
process(clk_100) is
variable counter_var: unsigned(17 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' or init_counter_clean = '1' then
counter_var := (others => '0');
else
counter_var := counter_var + 1;
end if;
end if;
init_counter_val <= counter_var;
end process;
--register for command
process(clk_100) is
variable wr_req_var: std_logic := '0';
--~ variable rd_req_var: std_logic := '0';
variable address_var: std_logic_vector(22 downto 0) := (others => '0');
variable data_in_var: std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(clk_100) then
if res = '1' then
wr_req_var := '0';
--~ rd_req_var := '0';
address_var := (others => '0');
data_in_var := (others => '0');
elsif write_cmd_reg = '1' then
wr_req_var := wr_req;
--~ rd_req_var := rd_req;
address_var := address;
data_in_var := data_in;
end if;
end if;
cmd_wr_req <= wr_req_var;
--~ cmd_rd_req <= rd_req_var;
cmd_address <= address_var;
cmd_data_in <= data_in_var;
end process;
--main fsm
process(clk_100) is
begin
if rising_edge(clk_100) then
if res = '1' then
fsm_state <= init_delay;
else
case fsm_state is
when init_delay =>
if init_counter_val = 200000 then
fsm_state <= init_precharge;
else
fsm_state <= init_delay;
end if;
when init_precharge =>
fsm_state <= init_precharge_wait;
when init_precharge_wait =>
if init_counter_val = 2 then
fsm_state <= init_refresh_0;
else
fsm_state <= init_precharge_wait;
end if;
when init_refresh_0 =>
fsm_state <= init_refresh_0_wait;
when init_refresh_0_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_1;
else
fsm_state <= init_refresh_0_wait;
end if;
when init_refresh_1 =>
fsm_state <= init_refresh_1_wait;
when init_refresh_1_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_2;
else
fsm_state <= init_refresh_1_wait;
end if;
when init_refresh_2 =>
fsm_state <= init_refresh_2_wait;
when init_refresh_2_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_3;
else
fsm_state <= init_refresh_2_wait;
end if;
when init_refresh_3 =>
fsm_state <= init_refresh_3_wait;
when init_refresh_3_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_4;
else
fsm_state <= init_refresh_3_wait;
end if;
when init_refresh_4 =>
fsm_state <= init_refresh_4_wait;
when init_refresh_4_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_5;
else
fsm_state <= init_refresh_4_wait;
end if;
when init_refresh_5 =>
fsm_state <= init_refresh_5_wait;
when init_refresh_5_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_6;
else
fsm_state <= init_refresh_5_wait;
end if;
when init_refresh_6 =>
fsm_state <= init_refresh_6_wait;
when init_refresh_6_wait =>
if init_counter_val = 7 then
fsm_state <= init_refresh_7;
else
fsm_state <= init_refresh_6_wait;
end if;
when init_refresh_7 =>
fsm_state <= init_refresh_7_wait;
when init_refresh_7_wait =>
if init_counter_val = 7 then
fsm_state <= init_mode_reg;
else
fsm_state <= init_refresh_7_wait;
end if;
when init_mode_reg =>
fsm_state <= init_mode_reg_wait;
when init_mode_reg_wait =>
if init_counter_val = 7 then
fsm_state <= idle;
else
fsm_state <= init_mode_reg_wait;
end if;
--there is idle process
when idle =>
if force_refresh = '1' then
fsm_state <= autorefresh;
elsif wr_req = '1' or rd_req = '1' then
fsm_state <= bank_active;
else
fsm_state <= idle;
end if;
--autorefresh stage
when autorefresh =>
fsm_state <= autorefresh_wait;
when autorefresh_wait =>
if init_counter_val = 7 then
fsm_state <= idle;
else
fsm_state <= autorefresh_wait;
end if;
--active bank and row
when bank_active =>
fsm_state <= bank_active_nop0;
when bank_active_nop0 =>
fsm_state <= bank_active_nop1;
when bank_active_nop1 =>
if cmd_wr_req = '1' then
fsm_state <= write_data;
else
fsm_state <= read_command;
end if;
-- write data into sdram
when write_data =>
fsm_state <= write_nop_0;
when write_nop_0 =>
fsm_state <= write_nop_1;
when write_nop_1 =>
fsm_state <= write_nop_2;
when write_nop_2 =>
fsm_state <= write_nop_3;
when write_nop_3 =>
fsm_state <= write_nop_4;
when write_nop_4 =>
fsm_state <= write_nop_5;
when write_nop_5 =>
fsm_state <= write_nop_6;
when write_nop_6 =>
fsm_state <= idle;
--read data block
when read_command =>
fsm_state <= read_nop_0;
when read_nop_0 =>
fsm_state <= read_nop_1;
when read_nop_1 =>
fsm_state <= read_nop_2;
when read_nop_2 =>
fsm_state <= read_nop_3;
when read_nop_3 =>
fsm_state <= read_nop_4;
when read_nop_4 =>
fsm_state <= read_nop_5;
when read_nop_5 =>
fsm_state <= read_nop_6;
when read_nop_6 =>
fsm_state <= read_completed;
when read_completed =>
fsm_state <= idle;
end case;
end if;
end if;
end process;
process(fsm_state, address_row, address_ba, address_col, cmd_data_in) is
begin
case fsm_state is
when init_delay =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_precharge =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_precharge_all_banks;
sdram_addr_unbuff <= "0010000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_precharge_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_0 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_0_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_1 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_1_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_2 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_2_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_3 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_3_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_4 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_4_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_5 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_5_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_6 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_6_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_7 =>
init_counter_clean <= '1';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_refresh_7_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_mode_reg =>
init_counter_clean <= '1';
refresh_counter_clean <= '1';
bidir_buff_oe <= '0';
sdram_control <= com_mode_reg_set;
sdram_addr_unbuff <= mode_register;
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when init_mode_reg_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when idle =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '0';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '1';
ack <= '0';
when autorefresh =>
init_counter_clean <= '1';
refresh_counter_clean <= '1';
bidir_buff_oe <= '0';
sdram_control <= com_cbr_auto_refresh;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when autorefresh_wait =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when bank_active =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_bank_active;
sdram_addr_unbuff <= address_row;
sdram_ba_unbuff <= address_ba;
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '1';
when bank_active_nop0 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when bank_active_nop1 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_data =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_write_precharge;
sdram_addr_unbuff <= "001" & address_col;
sdram_ba_unbuff <= address_ba;
bidir_buff_datain <= cmd_data_in(31 downto 24);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_0 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= cmd_data_in(23 downto 16);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_1 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= cmd_data_in(15 downto 8);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_2 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '1';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= cmd_data_in(7 downto 0);
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_3 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_4 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_5 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when write_nop_6 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_command =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_read_precharge;
sdram_addr_unbuff <= "001" & address_col;
sdram_ba_unbuff <= address_ba;
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_0 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_1 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_2 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_3 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_4 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_5 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_nop_6 =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '1';
data_out_ready <= '0';
write_cmd_reg <= '0';
ack <= '0';
when read_completed =>
init_counter_clean <= '0';
refresh_counter_clean <= '0';
bidir_buff_oe <= '0';
sdram_control <= com_no_operation;
sdram_addr_unbuff <= "0000000000000";
sdram_ba_unbuff <= "00";
bidir_buff_datain <= x"00";
busy <= '1';
write_input_data_reg <= '0';
data_out_ready <= '1';
write_cmd_reg <= '0';
ack <= '0';
end case;
end process;
end architecture sdram_driver_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc524.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00524ent IS
END c03s03b00x00p03n04i00524ent;
ARCHITECTURE c03s03b00x00p03n04i00524arch OF c03s03b00x00p03n04i00524ent IS
BEGIN
TESTING: PROCESS
type integer_ptr is access integer;
variable v_integer_ptr1: integer_ptr := new integer'(365);
variable v_integer_ptr2: integer_ptr;
variable v_integer_ptr3: integer_ptr := v_integer_ptr1;
type int is range -500 to 500;
type int_ptr is access int;
variable v_int_ptr1: int_ptr := new int'(365);
variable v_int_ptr2: int_ptr;
variable v_int_ptr3: int_ptr := v_int_ptr1;
variable v_int_ptr4: int_ptr := new int'(-365);
variable OKtest : integer := 0;
BEGIN
assert v_integer_ptr1.all = 365;
if (v_integer_ptr1.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_integer_ptr2 = null;
if (v_integer_ptr2 = null) then
Oktest := OKtest + 1;
end if;
assert v_integer_ptr3.all = 365;
if (v_integer_ptr3.all = 365) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr1.all + v_integer_ptr3.all) = 730;
if ((v_integer_ptr1.all + v_integer_ptr3.all) = 730) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr1.all - v_integer_ptr3.all) = 0;
if ((v_integer_ptr1.all - v_integer_ptr3.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr3.all * v_integer_ptr1.all) = 133225;
if ((v_integer_ptr3.all * v_integer_ptr1.all) = 133225) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr3.all / v_integer_ptr1.all) = 1;
if ((v_integer_ptr3.all / v_integer_ptr1.all) = 1) then
Oktest := OKtest + 1;
end if;
deallocate(v_integer_ptr2);
deallocate(v_integer_ptr1);
assert v_int_ptr1.all = 365;
if (v_int_ptr1.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr2 = null;
if (v_int_ptr2 = null) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr3.all = 365;
if (v_int_ptr3.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr4.all = -365;
if (v_int_ptr4.all = -365) then
Oktest := OKtest + 1;
end if;
v_int_ptr2 := new int'(100);
assert v_int_ptr2.all = 100;
if (v_int_ptr2.all = 100) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all + v_int_ptr3.all) = 730;
if ((v_int_ptr1.all + v_int_ptr3.all) = 730) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr2.all + v_int_ptr3.all) = 465;
if ((v_int_ptr2.all + v_int_ptr3.all) = 465) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all + v_int_ptr4.all) = 0;
if ((v_int_ptr1.all + v_int_ptr4.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all - v_int_ptr3.all) = 0;
if ((v_int_ptr1.all - v_int_ptr3.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr3.all * v_int_ptr1.all) = 133225;
if ((v_int_ptr3.all * v_int_ptr1.all) = 133225) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr3.all / v_int_ptr1.all) = 1;
if ((v_int_ptr3.all / v_int_ptr1.all) = 1) then
Oktest := OKtest + 1;
end if;
assert NOT(OKtest = 18)
report "***PASSED TEST: c03s03b00x00p03n04i00524"
severity NOTE;
assert (OKtest = 18)
report "***FAILED TEST: c03s03b00x00p03n04i00524 - Integer type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00524arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc524.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00524ent IS
END c03s03b00x00p03n04i00524ent;
ARCHITECTURE c03s03b00x00p03n04i00524arch OF c03s03b00x00p03n04i00524ent IS
BEGIN
TESTING: PROCESS
type integer_ptr is access integer;
variable v_integer_ptr1: integer_ptr := new integer'(365);
variable v_integer_ptr2: integer_ptr;
variable v_integer_ptr3: integer_ptr := v_integer_ptr1;
type int is range -500 to 500;
type int_ptr is access int;
variable v_int_ptr1: int_ptr := new int'(365);
variable v_int_ptr2: int_ptr;
variable v_int_ptr3: int_ptr := v_int_ptr1;
variable v_int_ptr4: int_ptr := new int'(-365);
variable OKtest : integer := 0;
BEGIN
assert v_integer_ptr1.all = 365;
if (v_integer_ptr1.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_integer_ptr2 = null;
if (v_integer_ptr2 = null) then
Oktest := OKtest + 1;
end if;
assert v_integer_ptr3.all = 365;
if (v_integer_ptr3.all = 365) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr1.all + v_integer_ptr3.all) = 730;
if ((v_integer_ptr1.all + v_integer_ptr3.all) = 730) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr1.all - v_integer_ptr3.all) = 0;
if ((v_integer_ptr1.all - v_integer_ptr3.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr3.all * v_integer_ptr1.all) = 133225;
if ((v_integer_ptr3.all * v_integer_ptr1.all) = 133225) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr3.all / v_integer_ptr1.all) = 1;
if ((v_integer_ptr3.all / v_integer_ptr1.all) = 1) then
Oktest := OKtest + 1;
end if;
deallocate(v_integer_ptr2);
deallocate(v_integer_ptr1);
assert v_int_ptr1.all = 365;
if (v_int_ptr1.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr2 = null;
if (v_int_ptr2 = null) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr3.all = 365;
if (v_int_ptr3.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr4.all = -365;
if (v_int_ptr4.all = -365) then
Oktest := OKtest + 1;
end if;
v_int_ptr2 := new int'(100);
assert v_int_ptr2.all = 100;
if (v_int_ptr2.all = 100) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all + v_int_ptr3.all) = 730;
if ((v_int_ptr1.all + v_int_ptr3.all) = 730) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr2.all + v_int_ptr3.all) = 465;
if ((v_int_ptr2.all + v_int_ptr3.all) = 465) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all + v_int_ptr4.all) = 0;
if ((v_int_ptr1.all + v_int_ptr4.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all - v_int_ptr3.all) = 0;
if ((v_int_ptr1.all - v_int_ptr3.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr3.all * v_int_ptr1.all) = 133225;
if ((v_int_ptr3.all * v_int_ptr1.all) = 133225) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr3.all / v_int_ptr1.all) = 1;
if ((v_int_ptr3.all / v_int_ptr1.all) = 1) then
Oktest := OKtest + 1;
end if;
assert NOT(OKtest = 18)
report "***PASSED TEST: c03s03b00x00p03n04i00524"
severity NOTE;
assert (OKtest = 18)
report "***FAILED TEST: c03s03b00x00p03n04i00524 - Integer type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00524arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc524.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00524ent IS
END c03s03b00x00p03n04i00524ent;
ARCHITECTURE c03s03b00x00p03n04i00524arch OF c03s03b00x00p03n04i00524ent IS
BEGIN
TESTING: PROCESS
type integer_ptr is access integer;
variable v_integer_ptr1: integer_ptr := new integer'(365);
variable v_integer_ptr2: integer_ptr;
variable v_integer_ptr3: integer_ptr := v_integer_ptr1;
type int is range -500 to 500;
type int_ptr is access int;
variable v_int_ptr1: int_ptr := new int'(365);
variable v_int_ptr2: int_ptr;
variable v_int_ptr3: int_ptr := v_int_ptr1;
variable v_int_ptr4: int_ptr := new int'(-365);
variable OKtest : integer := 0;
BEGIN
assert v_integer_ptr1.all = 365;
if (v_integer_ptr1.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_integer_ptr2 = null;
if (v_integer_ptr2 = null) then
Oktest := OKtest + 1;
end if;
assert v_integer_ptr3.all = 365;
if (v_integer_ptr3.all = 365) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr1.all + v_integer_ptr3.all) = 730;
if ((v_integer_ptr1.all + v_integer_ptr3.all) = 730) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr1.all - v_integer_ptr3.all) = 0;
if ((v_integer_ptr1.all - v_integer_ptr3.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr3.all * v_integer_ptr1.all) = 133225;
if ((v_integer_ptr3.all * v_integer_ptr1.all) = 133225) then
Oktest := OKtest + 1;
end if;
assert (v_integer_ptr3.all / v_integer_ptr1.all) = 1;
if ((v_integer_ptr3.all / v_integer_ptr1.all) = 1) then
Oktest := OKtest + 1;
end if;
deallocate(v_integer_ptr2);
deallocate(v_integer_ptr1);
assert v_int_ptr1.all = 365;
if (v_int_ptr1.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr2 = null;
if (v_int_ptr2 = null) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr3.all = 365;
if (v_int_ptr3.all = 365) then
Oktest := OKtest + 1;
end if;
assert v_int_ptr4.all = -365;
if (v_int_ptr4.all = -365) then
Oktest := OKtest + 1;
end if;
v_int_ptr2 := new int'(100);
assert v_int_ptr2.all = 100;
if (v_int_ptr2.all = 100) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all + v_int_ptr3.all) = 730;
if ((v_int_ptr1.all + v_int_ptr3.all) = 730) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr2.all + v_int_ptr3.all) = 465;
if ((v_int_ptr2.all + v_int_ptr3.all) = 465) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all + v_int_ptr4.all) = 0;
if ((v_int_ptr1.all + v_int_ptr4.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr1.all - v_int_ptr3.all) = 0;
if ((v_int_ptr1.all - v_int_ptr3.all) = 0) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr3.all * v_int_ptr1.all) = 133225;
if ((v_int_ptr3.all * v_int_ptr1.all) = 133225) then
Oktest := OKtest + 1;
end if;
assert (v_int_ptr3.all / v_int_ptr1.all) = 1;
if ((v_int_ptr3.all / v_int_ptr1.all) = 1) then
Oktest := OKtest + 1;
end if;
assert NOT(OKtest = 18)
report "***PASSED TEST: c03s03b00x00p03n04i00524"
severity NOTE;
assert (OKtest = 18)
report "***FAILED TEST: c03s03b00x00p03n04i00524 - Integer type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00524arch;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wr_status_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Status Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wr_status_cntl is
generic (
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if the Indeterminate BTT Module is enabled
-- for use (outside of this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8;
-- Specifies the depth of the internal status queue fifo
C_STS_WIDTH : Integer range 8 to 32 := 8;
-- sets the width of the Status ports
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Tag field in the Status reply
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA device family
);
port (
-- Clock and Reset inputs ------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- Soft Shutdown Control interface --------------------------------
--
rst2wsc_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
wsc2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Write status Controller --
-- has completed any pending transfers committed by the --
-- Address Controller after a stop has been requested by --
-- the Reset module. --
--
addr2wsc_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- write Status Controller that an address has been posted --
-- to the AXI Address Channel --
--------------------------------------------------------------------
-- Write Response Channel Interface -------------------------------
--
s2mm_bresp : In std_logic_vector(1 downto 0); --
-- The Write response value --
--
s2mm_bvalid : In std_logic ; --
-- Indication from the Write Response Channel that a new --
-- write status input is valid --
--
s2mm_bready : out std_logic ; --
-- Indication to the Write Response Channel that the --
-- Status module is ready for a new status input --
--------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------
--
calc2wsc_calc_error : in std_logic ; --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
---------------------------------------------------------------------
-- Address Controller Status ----------------------------------------
--
addr2wsc_calc_error : In std_logic ; --
-- Indication from the Address Channel Controller that it --
-- has encountered a calculation error from the command --
-- Calculator --
--
addr2wsc_fifo_empty : In std_logic ; --
-- Indication from the Address Controller FIFO that it --
-- is empty (no commands pending) --
---------------------------------------------------------------------
-- Data Controller Status ---------------------------------------------------------
--
data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_error : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has encountered a Calculation error in the command pipe --
--
data2wsc_last_error : In std_logic ; --
-- Indication from the Write Data Channel Controller that a --
-- premature TLAST assertion was encountered on the incoming --
-- Stream Channel --
--
data2wsc_cmd_cmplt : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- corresponding status is the final status for a parent --
-- command fetched from the command FIFO --
--
data2wsc_valid : In std_logic ; --
-- Indication from the Data Channel Controller FIFO that it --
-- has a new tag/error status to transfer --
--
wsc2data_ready : out std_logic ; --
-- Indication to the Data Channel Controller FIFO that the --
-- Status module is ready for a new tag/error status input --
--
--
data2wsc_eop : In std_logic; --
-- Input from the Write Data Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Store and --
-- Forward is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Input from the Write Data Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Store and --
-- Forward is enabled in the S2MM. --
------------------------------------------------------------------------------------
-- Command/Status Interface --------------------------------------------------------
--
wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- Read Status value collected during a Read Data transfer --
-- Output to the Command/Status Module --
--
stat2wsc_status_ready : In std_logic; --
-- Input from the Command/Status Module indicating that the --
-- Status Reg/FIFO is Full and cannot accept more staus writes --
--
wsc2stat_status_valid : Out std_logic ; --
-- Control Signal to Write the Status value to the Status --
-- Reg/FIFO --
------------------------------------------------------------------------------------
-- Address and Data Controller Pipe halt --------------------------------
--
wsc2mstr_halt_pipe : Out std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status pipe getting full at some point --
-------------------------------------------------------------------------
);
end entity axi_sg_wr_status_cntl;
architecture implementation of axi_sg_wr_status_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000";
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant STAT_REG_TAG_WIDTH : integer := 4;
Constant SYNC_FIFO_SELECT : integer := 0;
Constant SRL_FIFO_TYPE : integer := 2;
Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH;
Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH);
Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH);
Constant WRESP_WIDTH : integer := 2;
Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH;
Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_valid_status_rdy : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data_err_reg : std_logic := '0';
signal sig_data_last_err_reg : std_logic := '0';
signal sig_data_cmd_cmplt_reg : std_logic := '0';
signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_push_status : std_logic := '0';
Signal sig_status_push_ok : std_logic := '0';
signal sig_status_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_s2mm_bready : std_logic := '0';
signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_wresp_sfifo_wr_valid : std_logic := '0';
signal sig_wresp_sfifo_wr_ready : std_logic := '0';
signal sig_wresp_sfifo_wr_full : std_logic := '0';
signal sig_wresp_sfifo_rd_valid : std_logic := '0';
signal sig_wresp_sfifo_rd_ready : std_logic := '0';
signal sig_wresp_sfifo_rd_empty : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_no_posted_cmds : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_all_cmds_done : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_wr_valid : std_logic := '0';
signal sig_dcntl_sfifo_wr_ready : std_logic := '0';
signal sig_dcntl_sfifo_wr_full : std_logic := '0';
signal sig_dcntl_sfifo_rd_valid : std_logic := '0';
signal sig_dcntl_sfifo_rd_ready : std_logic := '0';
signal sig_dcntl_sfifo_rd_empty : std_logic := '0';
signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_statcnt : std_logic := '0';
signal sig_decr_statcnt : std_logic := '0';
signal sig_statcnt_eq_max : std_logic := '0';
signal sig_statcnt_eq_0 : std_logic := '0';
signal sig_statcnt_gt_eq_thres : std_logic := '0';
signal sig_wdc_status_going_full : std_logic := '0';
begin --(architecture implementation)
-- Assign the ready output to the AXI Write Response Channel
s2mm_bready <= sig_s2mm_bready or
sig_halt_reg; -- force bready if a Halt is requested
-- Assign the ready output to the Data Controller status interface
wsc2data_ready <= sig_wsc2data_ready;
-- Assign the status valid output control to the Status FIFO
wsc2stat_status_valid <= sig_status_valid ;
-- Formulate the status output value to the Status FIFO
wsc2stat_status <= sig_wsc2stat_status;
-- Formulate the status write request signal
sig_status_valid <= sig_push_status;
-- Indicate the desire to push a coelesced status word
-- to the Status FIFO
sig_push_status <= sig_coelsc_reg_full;
-- Detect that a push of a new status word is completing
sig_status_push_ok <= sig_status_valid and
stat2wsc_status_ready;
sig_pop_coelsc_reg <= sig_status_push_ok;
-- Signal a halt to the execution pipe if new status
-- is valid but the Status FIFO is not accepting it or
-- the WDC Status FIFO is going full
wsc2mstr_halt_pipe <= (sig_status_valid and
not(stat2wsc_status_ready)) or
sig_wdc_status_going_full;
-- Monitor the Status capture registers to detect a
-- qualified Status set and push to the coelescing register
-- when available to do so
sig_push_coelsc_reg <= sig_valid_status_rdy and
sig_coelsc_reg_empty;
-- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
-- pre CR616212 sig_dcntl_sfifo_rd_valid) or
-- pre CR616212 (sig_data_err_reg and
-- pre CR616212 sig_dcntl_sfifo_rd_valid);
sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and
sig_dcntl_sfifo_rd_valid) or
(sig_data_err_reg and
sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212
(sig_data_last_err_reg and -- Added for CR616212
sig_dcntl_sfifo_rd_valid); -- Added for CR616212
-- Decode the AXI MMap Read Respose
sig_decerr <= '1'
When sig_bresp_reg = DECERR
Else '0';
sig_slverr <= '1'
When sig_bresp_reg = SLVERR
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_LE_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is less than or equal to the available number
-- of bits in the Status word.
--
------------------------------------------------------------
GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_small;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_SMALL_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_small <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg;
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_LE_STAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_TAG_GT_STAT
--
-- If Generate Description:
-- Populates the TAG bits into the availble Status bits when
-- the TAG width is greater than the available number of
-- bits in the Status word. The upper bits of the TAG are
-- clipped off (discarded).
--
------------------------------------------------------------
GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate
-- local signals
signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0');
begin
sig_tag2status <= lsig_temp_tag_big;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: POPULATE_BIG_TAG
--
-- Process Description:
--
--
-------------------------------------------------------------
POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg)
begin
-- Set default value
lsig_temp_tag_big <= (others => '0');
-- Now overload actual TAG bits
lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0);
end process POPULATE_SMALL_TAG;
end generate GEN_TAG_GT_STAT;
-------------------------------------------------------------------------
-- Write Response Channel input FIFO and logic
-- BRESP is the only fifo data
sig_wresp_sfifo_in <= s2mm_bresp;
-- The fifo output is already in the right format
sig_bresp_reg <= sig_wresp_sfifo_out;
-- Write Side assignments
sig_wresp_sfifo_wr_valid <= s2mm_bvalid;
sig_s2mm_bready <= sig_wresp_sfifo_wr_ready;
-- read Side ready assignment
sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_WRESP_STATUS_FIFO
--
-- Description:
-- Instance for the AXI Write Response FIFO
--
------------------------------------------------------------
I_WRESP_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => WRESP_SFIFO_WIDTH ,
C_DEPTH => WRESP_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_wresp_sfifo_wr_valid ,
fifo_wr_tready => sig_wresp_sfifo_wr_ready ,
fifo_wr_tdata => sig_wresp_sfifo_in ,
fifo_wr_full => sig_wresp_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_wresp_sfifo_rd_valid ,
fifo_rd_tready => sig_wresp_sfifo_rd_ready ,
fifo_rd_tdata => sig_wresp_sfifo_out ,
fifo_rd_empty => sig_wresp_sfifo_rd_empty
);
-------- Write Data Controller Status FIFO Going Full Logic -------------
sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and
sig_dcntl_sfifo_wr_ready;
sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and
sig_dcntl_sfifo_rd_ready;
sig_statcnt_eq_max <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_MAX)
Else '0';
sig_statcnt_eq_0 <= '1'
when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO)
Else '0';
sig_statcnt_gt_eq_thres <= '1'
when (sig_wdc_statcnt >= DCNTL_HALT_THRES)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WDC_GOING_FULL_FLOP
--
-- Process Description:
-- Implements a flop for the WDC Status FIFO going full flag.
--
-------------------------------------------------------------
IMP_WDC_GOING_FULL_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_status_going_full <= '0';
else
sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres;
end if;
end if;
end process IMP_WDC_GOING_FULL_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DCNTL_FIFO_CNTR
--
-- Process Description:
-- Implements a simple counter keeping track of the number
-- of entries in the WDC Status FIFO. If the Status FIFO gets
-- too full, the S2MM Data Pipe has to be halted.
--
-------------------------------------------------------------
IMP_DCNTL_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wdc_statcnt <= (others => '0');
elsif (sig_incr_statcnt = '1' and
sig_decr_statcnt = '0' and
sig_statcnt_eq_max = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE;
elsif (sig_incr_statcnt = '0' and
sig_decr_statcnt = '1' and
sig_statcnt_eq_0 = '0') then
sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE;
else
null; -- Hold current count value
end if;
end if;
end process IMP_DCNTL_FIFO_CNTR;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- not enabled in the S2MM function.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
-- Local Constants
Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3;
Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0;
Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1;
Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2;
Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo data word
sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2
data2wsc_calc_error & -- bit 2
data2wsc_last_error & -- bit 1
data2wsc_cmd_cmplt ; -- bit 0
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto
DCNTL_SFIFO_TAG_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ;
sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX);
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_data_last_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ENABLE_INDET_BTT
--
-- If Generate Description:
-- Implements the logic needed when Indeterminate BTT is
-- enabled in the S2MM function. Primary difference is the
-- addition to the reported status of the End of Packet
-- marker (EOP) and the received byte count for the parent
-- command.
--
------------------------------------------------------------
GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- Local Constants
Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH +
C_SF_BYTES_RCVD_WIDTH + 3;
Constant SF_SFIFO_LS_TAG_INDEX : integer := 0;
Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1);
Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1;
Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1;
Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1;
Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+
(C_SF_BYTES_RCVD_WIDTH-1);
Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1;
Constant BYTES_RCVD_FIELD_WIDTH : integer := 23;
-- local signals
signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_data_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_coelsc_eop : std_logic := '0';
signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0');
begin
sig_wsc2stat_status <= sig_coelsc_eop &
sig_coelsc_bytes_rcvd_pad &
sig_coelsc_okay_reg &
sig_coelsc_slverr_reg &
sig_coelsc_decerr_reg &
sig_coelsc_interr_reg &
sig_tag2status;
-----------------------------------------------------------------------------
-- Data Controller Status FIFO and Logic
-- Concatonate Input bits to build Dcntl fifo input data word
sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit
data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7
data2wsc_cmd_cmplt & -- bit 6
data2wsc_calc_error & -- bit 4
data2wsc_tag; -- bits 0 to 3
-- Rip the DCntl fifo outputs back to constituant pieces
sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX);
sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto
SF_SFIFO_LS_BYTES_RCVD_INDEX);
sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX);
sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX);
sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto
SF_SFIFO_LS_TAG_INDEX) ;
-- Data Control Valid/Ready assignments
sig_dcntl_sfifo_wr_valid <= data2wsc_valid ;
sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready;
-- read side ready assignment
sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg;
------------------------------------------------------------
-- Instance: I_SF_DATA_CNTL_STATUS_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO when Store and
-- Forward is included.
--
------------------------------------------------------------
I_SF_DATA_CNTL_STATUS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => SF_DCNTL_SFIFO_WIDTH ,
C_DEPTH => DCNTL_SFIFO_DEPTH ,
C_IS_ASYNC => SYNC_FIFO_SELECT ,
C_PRIM_TYPE => SRL_FIFO_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid ,
fifo_wr_tready => sig_dcntl_sfifo_wr_ready ,
fifo_wr_tdata => sig_dcntl_sfifo_in ,
fifo_wr_full => sig_dcntl_sfifo_wr_full ,
-- Read Clock and reset (not used in Sync mode)
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid ,
fifo_rd_tready => sig_dcntl_sfifo_rd_ready ,
fifo_rd_tdata => sig_dcntl_sfifo_out ,
fifo_rd_empty => sig_dcntl_sfifo_rd_empty
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SF_STATUS_COELESC_REG
--
-- Process Description:
-- Implement error status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status FIFO.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
SF_STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_coelsc_reg = '1') then
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_bytes_rcvd <= (others => '0');
sig_coelsc_eop <= '0';
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_data_tag_reg;
sig_coelsc_interr_reg <= sig_data_err_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= not(sig_data_err_reg) and
(sig_decerr or
sig_coelsc_decerr_reg);
sig_coelsc_slverr_reg <= not(sig_data_err_reg) and
(sig_slverr or
sig_coelsc_slverr_reg);
sig_coelsc_okay_reg <= not(sig_decerr or
sig_coelsc_decerr_reg or
sig_slverr or
sig_coelsc_slverr_reg or
sig_data_err_reg or
sig_coelsc_interr_reg
);
sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd;
sig_coelsc_eop <= sig_data_eop;
sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg;
sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg);
else
null; -- hold current state
end if;
end if;
end process SF_STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_PAD_BYTES_RCVD
--
-- If Generate Description:
-- Pad the bytes received value with zeros to fill in the
-- status field width.
--
--
------------------------------------------------------------
SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto
C_SF_BYTES_RCVD_WIDTH) <= (others => '0');
sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd;
end generate SF_GEN_PAD_BYTES_RCVD;
------------------------------------------------------------
-- If Generate
--
-- Label: SF_GEN_NO_PAD_BYTES_RCVD
--
-- If Generate Description:
-- No padding required for the bytes received value.
--
--
------------------------------------------------------------
SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate
begin
sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required
end generate SF_GEN_NO_PAD_BYTES_RCVD;
end generate GEN_ENABLE_INDET_BTT;
------- Soft Shutdown Logic -------------------------------
-- Address Posted Counter Logic ---------------------t-----------------
-- Supports soft shutdown by tracking when all commited Write
-- transfers to the AXI Bus have had corresponding Write Status
-- Reponses Received.
sig_addr_posted <= addr2wsc_addr_posted ;
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_s2mm_bready and
s2mm_bvalid ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The counter is used to track flushing operations where all
-- transfers committed on the AXI Address Channel have to
-- be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
wsc2rst_stop_cmplt <= sig_all_cmds_done;
sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and
not(addr2wsc_calc_error)) or
(sig_addr_posted_cntr_eq_1 and
addr2wsc_calc_error);
sig_all_cmds_done <= sig_no_posted_cmds and
sig_halt_reg_dly3;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2wsc_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity grey_tb is
end entity;
architecture behav of grey_tb is
component grey is
port (
si : in std_logic_vector(2 downto 0);
so : out std_logic_vector(2 downto 0)
);
end component;
for grey_0 : grey use entity work.grey;
signal si, so : std_logic_vector(2 downto 0);
begin
grey_0: grey port map(si=>si, so=>so);
process
begin
si<="000";
wait for 5 ns;
si<="010";
wait for 5 ns;
si<="100";
wait for 5 ns;
si<="110";
wait for 5 ns;
wait;
end process;
end architecture;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Logic Unit
-- Operations - AND, OR, CMP, ANDI
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_Unit is
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (15 downto 0));
end Logic_Unit;
architecture Combinational of Logic_Unit is
signal cmp: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
with OP select
RESULT <=
A and B when "010", -- AND REG A, REG B
A or B when "011", -- OR REG A, REG B
A and B when OTHERS;-- ANDI REG A, IMMED
--Compare Operation
cmp(3) <= '1' when a<b else '0'; -- N when s<r
cmp(2) <= '1' when a=b else '0'; -- Z when s=r
-- Choose CCR output
with OP select
ccr <=
cmp when "100",
"0000" when OTHERS;
end Combinational;
|
-------------------------------------------------------------------------------
-- parity.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
architecture IMP of Parity is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
component MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF8;
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_FPGA : if (C_TARGET /= RTL) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MB_MUXF8
generic map(
C_TARGET => C_TARGET)
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- parity.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
architecture IMP of Parity is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
component MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF8;
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_FPGA : if (C_TARGET /= RTL) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MB_MUXF8
generic map(
C_TARGET => C_TARGET)
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- parity.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
architecture IMP of Parity is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
component MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF8;
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_FPGA : if (C_TARGET /= RTL) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MB_MUXF8
generic map(
C_TARGET => C_TARGET)
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- parity.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2015] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: parity.vhd
--
-- Description: Generate parity optimally for all target architectures
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- parity.vhd
-- xor18.vhd
-- parity_recursive_LUT6.vhd
--
-------------------------------------------------------------------------------
-- Author: stefana
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library lmb_bram_if_cntlr_v4_0;
use lmb_bram_if_cntlr_v4_0.lmb_bram_if_funcs.all;
entity Parity is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
C_SIZE : integer := 6
);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic
);
end entity Parity;
architecture IMP of Parity is
component MB_LUT6 is
generic (
C_TARGET : TARGET_FAMILY_TYPE;
INIT : bit_vector := X"0000000000000000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end component MB_LUT6;
component MB_MUXF7 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF7;
component MB_MUXF8 is
generic (
C_TARGET : TARGET_FAMILY_TYPE
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
S : in std_logic
);
end component MB_MUXF8;
-- Non-recursive loop implementation
function ParityGen (InA : std_logic_vector) return std_logic is
variable result : std_logic;
begin
result := '0';
for I in InA'range loop
result := result xor InA(I);
end loop;
return result;
end function ParityGen;
begin -- architecture IMP
Using_FPGA : if (C_TARGET /= RTL) generate
--------------------------------------------------------------------------------------------------
-- Single LUT6
--------------------------------------------------------------------------------------------------
Single_LUT6 : if C_SIZE > 1 and C_SIZE <= 6 generate
signal inA6 : std_logic_vector(0 to 5);
begin
Assign_InA : process (InA) is
begin
inA6 <= (others => '0');
inA6(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => Res,
I0 => inA6(5),
I1 => inA6(4),
I2 => inA6(3),
I3 => inA6(2),
I4 => inA6(1),
I5 => inA6(0));
end generate Single_LUT6;
--------------------------------------------------------------------------------------------------
-- Two LUT6 and one MUXF7
--------------------------------------------------------------------------------------------------
Use_MUXF7 : if C_SIZE = 7 generate
signal inA7 : std_logic_vector(0 to 6);
signal result6 : std_logic;
signal result6n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA7 <= (others => '0');
inA7(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
XOR6_LUT_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6n,
I0 => inA7(5),
I1 => inA7(4),
I2 => inA7(3),
I3 => inA7(2),
I4 => inA7(1),
I5 => inA7(0));
MUXF7_LUT : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => Res,
I0 => result6,
I1 => result6n,
S => inA7(6));
end generate Use_MUXF7;
--------------------------------------------------------------------------------------------------
-- Four LUT6, two MUXF7 and one MUXF8
--------------------------------------------------------------------------------------------------
Use_MUXF8 : if C_SIZE = 8 generate
signal inA8 : std_logic_vector(0 to 7);
signal result6_1 : std_logic;
signal result6_1n : std_logic;
signal result6_2 : std_logic;
signal result6_2n : std_logic;
signal result7_1 : std_logic;
signal result7_1n : std_logic;
begin
Assign_InA : process (InA) is
begin
inA8 <= (others => '0');
inA8(0 to InA'length - 1) <= InA;
end process Assign_InA;
XOR6_LUT1 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_1,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT2_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_1n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT1 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1,
I0 => result6_1,
I1 => result6_1n,
S => inA8(6));
XOR6_LUT3 : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"6996966996696996")
port map(
O => result6_2,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
XOR6_LUT4_N : MB_LUT6
generic map(
C_TARGET => C_TARGET,
INIT => X"9669699669969669")
port map(
O => result6_2n,
I0 => inA8(5),
I1 => inA8(4),
I2 => inA8(3),
I3 => inA8(2),
I4 => inA8(1),
I5 => inA8(0));
MUXF7_LUT2 : MB_MUXF7
generic map(
C_TARGET => C_TARGET)
port map (
O => result7_1n,
I0 => result6_2n,
I1 => result6_2,
S => inA8(6));
MUXF8_LUT : MB_MUXF8
generic map(
C_TARGET => C_TARGET)
port map (
O => res,
I0 => result7_1,
I1 => result7_1n,
S => inA8(7));
end generate Use_MUXF8;
end generate Using_FPGA;
Using_RTL: if ( C_TARGET = RTL ) generate
begin
Res <= ParityGen(InA);
end generate Using_RTL;
end architecture IMP;
|
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21712)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
-------------------------------------------------------------------------------
-- Title : Direct Digital Synthesis
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Description : DDS with RAM Table, Table can be defined over MM Interface
-- The Phase Increment and Enable can also be set over an extra MM Interface
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use work.sin_4096.all;
entity Dds is
generic (
-- number of bits for the streaming interface
data_width_g : natural := 24;
-- amount of bits for the phase register
phase_bits_g : natural := 20;
-- phase register dither bist
phase_dither_g : natural := 8;
-- number of bits for the waveform rom entries
wave_table_width_g : natural := 14;
-- number of wave table entries
wave_table_len_g : natural := 4096;
-- number of bits to address the wave table
-- shoud be log dualis of wave_table_len_g
wave_table_addr_bits_g : natural := 12
);
port (
csi_clk : in std_logic;
rsi_reset_n : in std_logic;
-- sample strobe
coe_sample_strobe : in std_logic;
-- Avalon MM Slave Port s0 - used for dds table
avs_s0_write : in std_logic;
avs_s0_address : in std_logic_vector(wave_table_addr_bits_g-1 downto 0);
avs_s0_writedata : in std_logic_vector(31 downto 0);
-- Avalon MM Slave Port s1 - used for phase increment and enable
-- not enable also clear the phase register
-- address + 0 => enable register (1 bit) : '1' => enable, '0' => not enable
-- address + 1 => phase increment (phase_bits_g bits) => 0 no phase increment
avs_s1_write : in std_logic;
avs_s1_address : in std_logic;
avs_s1_writedata : in std_logic_vector(31 downto 0);
-- Avalon ST source
aso_data : out std_logic_vector(data_width_g-1 downto 0);
aso_valid : out std_logic
);
end entity Dds;
|
entity test is
end test;
architecture only of test is
procedure doit is
begin
report "PROCEDURE CALLED!";
end procedure;
begin -- only
process
begin -- process doit
doit;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
procedure doit is
begin
report "PROCEDURE CALLED!";
end procedure;
begin -- only
process
begin -- process doit
doit;
report "TEST PASSED";
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
procedure doit is
begin
report "PROCEDURE CALLED!";
end procedure;
begin -- only
process
begin -- process doit
doit;
report "TEST PASSED";
wait;
end process;
end only;
|
-- NEED RESULT: ENT00252: Open scalar buffer ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00252
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00252(ARCH00252)
-- ENT00252_Test_Bench(ARCH00252_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00252 is
port (
toggle : buffer switch ;
i_boolean_1, i_boolean_2 : buffer boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : buffer bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : buffer severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : buffer character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : buffer t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : buffer st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : buffer integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : buffer t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : buffer st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : buffer time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : buffer t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : buffer st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : buffer real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : buffer t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : buffer st_real1
:= c_st_real1_1
) ;
begin
end ENT00252 ;
--
architecture ARCH00252 of ENT00252 is
begin
process
variable correct : boolean := true ;
begin
--
toggle <= up ;
i_boolean_1 <= c_boolean_2 ;
i_boolean_2 <= c_boolean_2 ;
i_bit_1 <= c_bit_2 ;
i_bit_2 <= c_bit_2 ;
i_severity_level_1 <= c_severity_level_2 ;
i_severity_level_2 <= c_severity_level_2 ;
i_character_1 <= c_character_2 ;
i_character_2 <= c_character_2 ;
i_t_enum1_1 <= c_t_enum1_2 ;
i_t_enum1_2 <= c_t_enum1_2 ;
i_st_enum1_1 <= c_st_enum1_2 ;
i_st_enum1_2 <= c_st_enum1_2 ;
i_integer_1 <= c_integer_2 ;
i_integer_2 <= c_integer_2 ;
i_t_int1_1 <= c_t_int1_2 ;
i_t_int1_2 <= c_t_int1_2 ;
i_st_int1_1 <= c_st_int1_2 ;
i_st_int1_2 <= c_st_int1_2 ;
i_time_1 <= c_time_2 ;
i_time_2 <= c_time_2 ;
i_t_phys1_1 <= c_t_phys1_2 ;
i_t_phys1_2 <= c_t_phys1_2 ;
i_st_phys1_1 <= c_st_phys1_2 ;
i_st_phys1_2 <= c_st_phys1_2 ;
i_real_1 <= c_real_2 ;
i_real_2 <= c_real_2 ;
i_t_real1_1 <= c_t_real1_2 ;
i_t_real1_2 <= c_t_real1_2 ;
i_st_real1_1 <= c_st_real1_2 ;
i_st_real1_2 <= c_st_real1_2 ;
test_report ( "ENT00252" ,
"Open scalar buffer ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00252 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00252_Test_Bench is
end ENT00252_Test_Bench ;
--
architecture ARCH00252_Test_Bench of ENT00252_Test_Bench is
begin
L1:
block
--
signal toggle : switch ;
--
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00252 ( ARCH00252 )
port map (
toggle ,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open
) ;
--
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00252_Test_Bench ;
|
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`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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vs1ltuvadEV+1Zgw212EABX80eLLQhd2hMblzMUC8zDaqjzevxy8gYNZvMSz+O5aOb04PT9LJ416
xlaIpycMMiRbrTgA4oxvju5Q8wVwnzxiwsCZD4zzRETaIs1dDqVhwddBkZIEE4YvuFZJbDeIERpP
/1x/11X2zLNf1ij+n/HvsH1PjdnIAIr94kQJIC2VZBu/JST1NwRoOFMeybLXlkdLW86SPfzMDyxB
Cu9GaVn9BMsMhf8jExy5SwUZwxq4hxgbfkonPl+SvUTMPl3HqjGshnGmE9fuoXnSH9kux1oNnxV0
rowIGrWCLIRuwZkOHZkVuJcuPBUourTqemnxJ4csUwVulli40g9XmQfaFvrkMMekUmXR/fP0KTbS
0pZ+YY9usMjrhiJ8lBPlLLChItWntQ37hIdE7pYny9iSCm2fGtmG5YA7ps3UMBxy5StUnVQ9j1v+
8jy771jc7o2Bk4j1e+PW8jVOyEJ2LeYDqQPDHd5UuvgVYI7pwoXdkwUNVpeIW3UGYDyx09Tz/dqU
ZQHl3tkayBLwOZ5j6hfR778iEywwHzGdMwVFkPu7K9zNKkxRyvD0BXJjNYWNLCR9mu8YyByt+7b1
tcUIKQ3PE6QDs1Qa4K99P3CiASdlw1VLloTFUDdR1bAQ0JiRwaXtz0ogW2pKvz3X1vJjp8NaCZAz
bmc3EEYczM8QLMpV2cAsJI26U034Q2ZVVAeuu+EL8HMqmVQARDI+9pxNSqj9L1IYyucMQADdv2JA
zjn6YzY=
`protect end_protected
|
-------------------------------------------------------------------------------
--
-- Title : and2
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : and2.vhd
-- Generated : Fri Oct 3 17:28:04 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {and2} architecture {and2}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity and2 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end and2;
--}} End of automatically maintained section
architecture and2 of and2 is
begin
Z <= A and B;
end and2;
|
-------------------------------------------------------------------------------
--
-- Title : and2
-- Design : lab2
-- Author : Dark MeFoDy
-- Company : BSUIR
--
-------------------------------------------------------------------------------
--
-- File : and2.vhd
-- Generated : Fri Oct 3 17:28:04 2014
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {and2} architecture {and2}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity and2 is
port(
A : in STD_LOGIC;
B : in STD_LOGIC;
Z : out STD_LOGIC
);
end and2;
--}} End of automatically maintained section
architecture and2 of and2 is
begin
Z <= A and B;
end and2;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity control_unit is
port ( Clk: in STD_LOGIC; Reset: in STD_LOGIC;
X: in STD_LOGIC_vector(4 downto 1);
Y: out STD_LOGIC_vector(12 downto 1));
end control_unit;
architecture control_unit of control_unit is
-- Òèï, èñïîëüçóþùèé ñèìâîëüíîå êîäèðîâàíèå ñîñòîÿíèé àâòîìàòà
type State_type is (a1, a2, a3, a4, a5, a6);
signal State, NextState: State_type;
begin
-- NextState logic (combinatorial)
Sreg0_NextState: process (State, x)
begin
-- èíèöèàëèçàöèÿ çíà÷åíèé âûõîäîâ
y <= (others => '0');
case State is
when a1 =>
NextState <= a2;
y(1) <= '1';
y(2) <= '1';
y(3) <= '1';
y(4) <= '1';
when a2=>
NextState <= a3;
if x(1) = '1' then
y(5) <= '1';
end if;
when a3=>
NextState <= a4;
y(6) <= '1';
y(7) <= '1';
y(8) <= '1';
when a4=>
NextState <= a5;
if x(2) = '1' then
y(9) <= '1';
else
y(10) <= '1';
end if;
when a5=>
if x(3) = '0' then
NextState <= a2;
elsif x(4) = '1' then
NextState <= a6;
y(11) <= '1';
else
NextState <= a6;
end if;
when a6=>
NextState <= a1;
y(12) <= '1';
when others => NextState <= a1;
-- ïðèñâîåíèå çíà÷åíèé âûõîäàì äëÿ ñîñòîÿíèÿ ïî óìîë÷àíèþ
--Óñòàíîâêà àâòîìàòà â íà÷àëüíîå ñîñòîÿíèå
end case;
end process;
Sreg0_CurrentState: process (Clk, reset)
begin
if Reset='0' then
State <= a1; -- íà÷àëüíîå ñîñòîÿíèå
elsif rising_edge(clk) then
State <= NextState;
end if;
end process;
end control_unit; |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_a
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-e.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $
-- $Date: 2005/11/30 14:04:01 $
-- $Log: ent_a-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:01 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_a
--
entity ent_a is
-- Generics:
-- No Generated Generics for Entity ent_a
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end ent_a;
--
-- End of Generated Entity ent_a
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
--************************************************************************************************
-- 16Kx16(32 KB) PM RAM for AVR Core(Xilinx)
-- Version 0.2
-- Designed by Ruslan Lepetenok
-- Modified 30.07.2005
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-- For Synplicity Synplify
--library virtexe;
--use virtexe.components.all;
-- Aldec
library unisim;
use unisim.vcomponents.all;
entity XPM16Kx16 is port(
cp2 : in std_logic;
ce : in std_logic;
address : in std_logic_vector(13 downto 0);
din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
weh : in std_logic;
wel : in std_logic
);
end XPM16Kx16;
architecture RTL of XPM16Kx16 is
type RAMBlDOut_Type is array(2**(address'length-9)-1 downto 0) of std_logic_vector(dout'range);
signal RAMBlDOut : RAMBlDOut_Type;
signal WEBL : std_logic_vector(2**(address'length-9)-1 downto 0);
signal WEBH : std_logic_vector(2**(address'length-9)-1 downto 0);
signal gnd : std_logic;
begin
gnd <= '0';
WEBH_Dcd:for i in WEBL'range generate
WEBL(i) <= '1' when (wel='1' and address(address'high downto 9)=i) else '0';
end generate ;
WEBL_Dcd:for i in WEBH'range generate
WEBH(i) <= '1' when (weh='1' and address(address'high downto 9)=i) else '0';
end generate ;
RAM_Inst:for i in 0 to 2**(address'length-9)-1 generate
RAM_ByteLow:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(7 downto 0),
ADDR => address(8 downto 0),
DI => din(7 downto 0),
EN => ce,
CLK => cp2,
WE => WEBL(i),
RST => gnd
);
RAM_ByteHigh:component RAMB4_S8 port map(
DO => RAMBlDOut(i)(15 downto 8),
ADDR => address(8 downto 0),
DI => din(15 downto 8),
EN => ce,
CLK => cp2,
WE => WEBH(i),
RST => gnd
);
end generate;
-- Output data mux
dout <= RAMBlDOut(CONV_INTEGER(address(address'high downto 9)));
end RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1310.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY vests8 IS
END vests8;
ARCHITECTURE c08s04b00x00p07n02i01310arch OF vests8 IS
type sigrec is
record
A1 : bit;
A2 : integer;
A3 : character;
A4 : boolean;
end record;
signal S1 : bit;
signal S2 : integer;
signal S3 : character;
signal S4 : boolean;
BEGIN
TESTING: PROCESS
BEGIN
(S1, S2, S3, S4) <= sigrec'('1', 1, '1', true);
wait for 1 ns;
assert NOT( (S1='1')and(S2=1)and(S3='1')and(S4=true) )
report "***PASSED TEST: c08s04b00x00p07n02i01310"
severity NOTE;
assert ( (S1='1')and(S2=1)and(S3='1')and(S4=true) )
report "***FAILED TEST: c08s04b00x00p07n02i01310 - A waveform element on the rigth-hand side must be the same as the base type of the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b00x00p07n02i01310arch;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_a
--
-- Generated
-- by: wig
-- on: Thu Mar 16 07:48:49 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -conf macro._MP_VHDL_USE_ENTY_MP_=Overwritten vhdl_enty from cmdline -conf macro._MP_VHDL_HOOK_ARCH_BODY_MP_=Use macro vhdl_hook_arch_body -conf macro._MP_ADD_MY_OWN_MP_=overloading my own macro -nodelta ../../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-e.vhd,v 1.1 2006/03/16 14:12:14 wig Exp $
-- $Date: 2006/03/16 14:12:14 $
-- $Log: ent_a-e.vhd,v $
-- Revision 1.1 2006/03/16 14:12:14 wig
-- Added testcase for command line -conf add/overload
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.77 2006/03/14 08:10:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- adding to vhdl_use_enty
library IEEE;
use IEEE.std_logic_1164.all;
-- Generated use statements
library wig;
use wig.test.all;
typedef use_enty_private std_ulogic_vector;
--
--
-- Start of Generated Entity ent_a
--
entity ent_a is
-- Generics:
-- No Generated Generics for Entity ent_a
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end ent_a;
--
-- End of Generated Entity ent_a
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( nzvc : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
rest : in STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC);
end PSR;
architecture Behavioral of PSR is
begin
process(clk,nzvc,ncwp,rest)
begin
if(rest = '1') then
cwp <='0';
c <= '0';
icc <= "0000";
elsif rising_edge(clk) then
c<=nzvc(0);
cwp<=ncwp;
icc <= nzvc;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PSR is
Port ( nzvc : in STD_LOGIC_VECTOR (3 downto 0);
clk : in STD_LOGIC;
cwp : out STD_LOGIC;
ncwp : in STD_LOGIC;
rest : in STD_LOGIC;
icc : out STD_LOGIC_VECTOR (3 downto 0);
c : out STD_LOGIC);
end PSR;
architecture Behavioral of PSR is
begin
process(clk,nzvc,ncwp,rest)
begin
if(rest = '1') then
cwp <='0';
c <= '0';
icc <= "0000";
elsif rising_edge(clk) then
c<=nzvc(0);
cwp<=ncwp;
icc <= nzvc;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : inductor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Inductor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity inductor is
generic (
ind : inductance; -- Nominal inductance
i_ic : real := real'low); -- Initial current (use IF statement below
-- to activate)
port (
terminal p1, p2 : electrical);
end entity inductor;
-------------------------------------------------------------------------------
-- Ideal Architecture (V = L * di/dt)
-- Includes initial condition
-------------------------------------------------------------------------------
architecture ideal of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal;
architecture ideal2 of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal2;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : capacitor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Capacitor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
generic ( cap : capacitance;
r_esr : resistance := 0.0;
v_ic : voltage := real'low );
port ( terminal p1, p2 : electrical );
end entity capacitor;
architecture esr of capacitor is
quantity v across i through p1 to p2;
quantity vc : voltage; -- Internal voltage across capacitor
begin
if domain = quiescent_domain and v_ic /= real'low use
vc == v_ic;
i == 0.0;
else
vc == v - (i * r_esr);
i == cap * vc'dot;
end use;
end architecture esr;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_constant.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Constant Voltage Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_constant is
generic (
level : voltage; -- Constant voltage value [Volts]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_constant;
-------------------------------------------------------------------------------
-- Ideal Architecture (I = constant)
-------------------------------------------------------------------------------
architecture ideal of v_constant is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
if domain = quiescent_domain or domain = time_domain use
v == level;
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity sw_LoopCtrl_wa is
generic (r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
sw_state : integer := 1);
port (terminal c, p1, p2 : electrical);
end entity sw_LoopCtrl_wa;
architecture ideal of sw_LoopCtrl_wa is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 : resistance;
begin
if (sw_state = 2) use
r1 == r_open;
r2 == r_closed;
else
r1 == r_closed;
r2 == r_open;
end use;
v1 == r1*i1;
v2 == r2*i2;
end architecture ideal;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity pwl_load_wa is
generic (
load_enable: string := "yes";
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time);
port (terminal p1, p2 : electrical);
end entity pwl_load_wa;
architecture ideal of pwl_load_wa is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
if load_enable = "yes" use
if domain = quiescent_domain or domain = frequency_domain use
v == i*res_init;
else
v == i*res_signal'ramp(1.0e-6, 1.0e-6);
end use;
else
i == 0.0;
end use;
-- purpose: Create Events to change resistance at specified times
-- type : combinational
-- inputs :
-- outputs: res
CreateEvent: process is
begin -- process CreateEvent
wait for t1;
res_signal <= res1;
wait for (t2-t1);
res_signal <= res2;
wait;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity buck_sw is
generic (
Vd : voltage := 0.7; -- Diode Voltage
Vramp : voltage := 2.5); -- P-P amplitude of ramp voltage
port (terminal input, output, ref, ctrl: electrical);
end entity buck_sw;
architecture average of buck_sw is
quantity Vout across Iout through output to ref;
quantity Vin across input to ref;
quantity Vctrl across ctrl to ref;
begin
Vout + Vd == Vctrl * Vin / Vramp; -- Averaged equation
end architecture average;
library IEEE;
library IEEE_proposed;
use ieee.math_real.all;
use IEEE_proposed.electrical_systems.all;
entity comp_2p2z is
generic (
gain : real := 100.0; -- High DC gain for good load regulation
fp1 : real := 7.5e3; -- Pole location to achieve crossover frequency
fp2 : real := 531.0e3;-- Pole location to cancel effect of ESR
fz1 : real := 403.0; -- Zero locations to cancel LC filter poles
fz2 : real := 403.0);
port (terminal input, output, ref : electrical);
end entity comp_2p2z;
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi*fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi*fp2;
constant wz1 : real := math_2_pi*fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi*fz2;
constant num : real_vector := (1.0, (wz1+wz2)/(wz1*wz2), 1.0/(wz1*wz2));
constant den : real_vector := (1.0e-9, 1.0, (wp1+wp2)/(wp1*wp2), 1.0/(wp1*wp2));
begin
vout == -1.0*gain*vin'ltf(num, den);
end architecture ltf;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS3_BuckConverter_average is
end TB_CS3_BuckConverter_average;
architecture TB_CS3_BuckConverter_average of TB_CS3_BuckConverter_average is
-- Component declarations
-- Signal declarations
terminal vcomp_out : electrical;
terminal vctrl : electrical;
terminal vctrl_init : electrical;
terminal vin : electrical;
terminal vmid : electrical;
terminal vout : electrical;
terminal vref : electrical;
begin
-- Signal assignments
-- Component instances
L1 : entity work.inductor(ideal)
generic map(
ind => 6.5e-3
)
port map(
p1 => vmid,
p2 => vout
);
C1 : entity work.capacitor(ESR)
generic map(
cap => 6.0e-6,
r_esr => 50.0e-3
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vctrl_1 : entity work.v_constant(ideal)
generic map(
level => 0.327
)
port map(
pos => vctrl_init,
neg => ELECTRICAL_REF
);
Vref_1 : entity work.v_constant(ideal)
generic map(
level => 4.8
)
port map(
pos => vref,
neg => ELECTRICAL_REF
);
sw2 : entity work.sw_LoopCtrl_wa(ideal)
generic map(
sw_state => 1
)
port map(
p2 => vctrl_init,
c => vctrl,
p1 => vcomp_out
);
Electrical_Load6 : entity work.pwl_load_wa(ideal)
generic map(
t2 => 30 ms,
res2 => 5.0,
t1 => 5ms,
res1 => 1.0,
res_init => 2.4,
load_enable => "yes"
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vin_1 : entity work.v_pulse(ideal)
generic map(
initial => 42.0,
pulse => 42.0,
delay => 10ms,
width => 100ms,
period => 1000ms
)
port map(
pos => vin,
neg => ELECTRICAL_REF
);
buck_sw2 : entity work.buck_sw(average)
port map(
ctrl => vctrl,
input => vin,
ref => ELECTRICAL_REF,
output => vmid
);
comp_2p2z4 : entity work.comp_2p2z(ltf)
generic map(
fz1 => 403.0,
fz2 => 403.0,
gain => 100.0
)
port map(
input => vout,
output => vcomp_out,
ref => vref
);
end TB_CS3_BuckConverter_average;
--
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : inductor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Inductor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity inductor is
generic (
ind : inductance; -- Nominal inductance
i_ic : real := real'low); -- Initial current (use IF statement below
-- to activate)
port (
terminal p1, p2 : electrical);
end entity inductor;
-------------------------------------------------------------------------------
-- Ideal Architecture (V = L * di/dt)
-- Includes initial condition
-------------------------------------------------------------------------------
architecture ideal of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal;
architecture ideal2 of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal2;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : capacitor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Capacitor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
generic ( cap : capacitance;
r_esr : resistance := 0.0;
v_ic : voltage := real'low );
port ( terminal p1, p2 : electrical );
end entity capacitor;
architecture esr of capacitor is
quantity v across i through p1 to p2;
quantity vc : voltage; -- Internal voltage across capacitor
begin
if domain = quiescent_domain and v_ic /= real'low use
vc == v_ic;
i == 0.0;
else
vc == v - (i * r_esr);
i == cap * vc'dot;
end use;
end architecture esr;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_constant.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Constant Voltage Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_constant is
generic (
level : voltage; -- Constant voltage value [Volts]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_constant;
-------------------------------------------------------------------------------
-- Ideal Architecture (I = constant)
-------------------------------------------------------------------------------
architecture ideal of v_constant is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
if domain = quiescent_domain or domain = time_domain use
v == level;
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity sw_LoopCtrl_wa is
generic (r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
sw_state : integer := 1);
port (terminal c, p1, p2 : electrical);
end entity sw_LoopCtrl_wa;
architecture ideal of sw_LoopCtrl_wa is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 : resistance;
begin
if (sw_state = 2) use
r1 == r_open;
r2 == r_closed;
else
r1 == r_closed;
r2 == r_open;
end use;
v1 == r1*i1;
v2 == r2*i2;
end architecture ideal;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity pwl_load_wa is
generic (
load_enable: string := "yes";
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time);
port (terminal p1, p2 : electrical);
end entity pwl_load_wa;
architecture ideal of pwl_load_wa is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
if load_enable = "yes" use
if domain = quiescent_domain or domain = frequency_domain use
v == i*res_init;
else
v == i*res_signal'ramp(1.0e-6, 1.0e-6);
end use;
else
i == 0.0;
end use;
-- purpose: Create Events to change resistance at specified times
-- type : combinational
-- inputs :
-- outputs: res
CreateEvent: process is
begin -- process CreateEvent
wait for t1;
res_signal <= res1;
wait for (t2-t1);
res_signal <= res2;
wait;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity buck_sw is
generic (
Vd : voltage := 0.7; -- Diode Voltage
Vramp : voltage := 2.5); -- P-P amplitude of ramp voltage
port (terminal input, output, ref, ctrl: electrical);
end entity buck_sw;
architecture average of buck_sw is
quantity Vout across Iout through output to ref;
quantity Vin across input to ref;
quantity Vctrl across ctrl to ref;
begin
Vout + Vd == Vctrl * Vin / Vramp; -- Averaged equation
end architecture average;
library IEEE;
library IEEE_proposed;
use ieee.math_real.all;
use IEEE_proposed.electrical_systems.all;
entity comp_2p2z is
generic (
gain : real := 100.0; -- High DC gain for good load regulation
fp1 : real := 7.5e3; -- Pole location to achieve crossover frequency
fp2 : real := 531.0e3;-- Pole location to cancel effect of ESR
fz1 : real := 403.0; -- Zero locations to cancel LC filter poles
fz2 : real := 403.0);
port (terminal input, output, ref : electrical);
end entity comp_2p2z;
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi*fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi*fp2;
constant wz1 : real := math_2_pi*fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi*fz2;
constant num : real_vector := (1.0, (wz1+wz2)/(wz1*wz2), 1.0/(wz1*wz2));
constant den : real_vector := (1.0e-9, 1.0, (wp1+wp2)/(wp1*wp2), 1.0/(wp1*wp2));
begin
vout == -1.0*gain*vin'ltf(num, den);
end architecture ltf;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS3_BuckConverter_average is
end TB_CS3_BuckConverter_average;
architecture TB_CS3_BuckConverter_average of TB_CS3_BuckConverter_average is
-- Component declarations
-- Signal declarations
terminal vcomp_out : electrical;
terminal vctrl : electrical;
terminal vctrl_init : electrical;
terminal vin : electrical;
terminal vmid : electrical;
terminal vout : electrical;
terminal vref : electrical;
begin
-- Signal assignments
-- Component instances
L1 : entity work.inductor(ideal)
generic map(
ind => 6.5e-3
)
port map(
p1 => vmid,
p2 => vout
);
C1 : entity work.capacitor(ESR)
generic map(
cap => 6.0e-6,
r_esr => 50.0e-3
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vctrl_1 : entity work.v_constant(ideal)
generic map(
level => 0.327
)
port map(
pos => vctrl_init,
neg => ELECTRICAL_REF
);
Vref_1 : entity work.v_constant(ideal)
generic map(
level => 4.8
)
port map(
pos => vref,
neg => ELECTRICAL_REF
);
sw2 : entity work.sw_LoopCtrl_wa(ideal)
generic map(
sw_state => 1
)
port map(
p2 => vctrl_init,
c => vctrl,
p1 => vcomp_out
);
Electrical_Load6 : entity work.pwl_load_wa(ideal)
generic map(
t2 => 30 ms,
res2 => 5.0,
t1 => 5ms,
res1 => 1.0,
res_init => 2.4,
load_enable => "yes"
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vin_1 : entity work.v_pulse(ideal)
generic map(
initial => 42.0,
pulse => 42.0,
delay => 10ms,
width => 100ms,
period => 1000ms
)
port map(
pos => vin,
neg => ELECTRICAL_REF
);
buck_sw2 : entity work.buck_sw(average)
port map(
ctrl => vctrl,
input => vin,
ref => ELECTRICAL_REF,
output => vmid
);
comp_2p2z4 : entity work.comp_2p2z(ltf)
generic map(
fz1 => 403.0,
fz2 => 403.0,
gain => 100.0
)
port map(
input => vout,
output => vcomp_out,
ref => vref
);
end TB_CS3_BuckConverter_average;
--
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : inductor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Inductor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity inductor is
generic (
ind : inductance; -- Nominal inductance
i_ic : real := real'low); -- Initial current (use IF statement below
-- to activate)
port (
terminal p1, p2 : electrical);
end entity inductor;
-------------------------------------------------------------------------------
-- Ideal Architecture (V = L * di/dt)
-- Includes initial condition
-------------------------------------------------------------------------------
architecture ideal of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal;
architecture ideal2 of inductor is
-- Declare Branch Quantities
quantity v across i through p1 to p2;
begin
if domain = quiescent_domain and i_ic /= real'low use
i == i_ic;
else
v == ind * i'dot; -- characteristic equation
end use;
end architecture ideal2;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : capacitor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Electrical Capacitor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity capacitor is
generic ( cap : capacitance;
r_esr : resistance := 0.0;
v_ic : voltage := real'low );
port ( terminal p1, p2 : electrical );
end entity capacitor;
architecture esr of capacitor is
quantity v across i through p1 to p2;
quantity vc : voltage; -- Internal voltage across capacitor
begin
if domain = quiescent_domain and v_ic /= real'low use
vc == v_ic;
i == 0.0;
else
vc == v - (i * r_esr);
i == cap * vc'dot;
end use;
end architecture esr;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_constant.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/03
-------------------------------------------------------------------------------
-- Description: Constant Voltage Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_constant is
generic (
level : voltage; -- Constant voltage value [Volts]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_constant;
-------------------------------------------------------------------------------
-- Ideal Architecture (I = constant)
-------------------------------------------------------------------------------
architecture ideal of v_constant is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
if domain = quiescent_domain or domain = time_domain use
v == level;
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity sw_LoopCtrl_wa is
generic (r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
sw_state : integer := 1);
port (terminal c, p1, p2 : electrical);
end entity sw_LoopCtrl_wa;
architecture ideal of sw_LoopCtrl_wa is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 : resistance;
begin
if (sw_state = 2) use
r1 == r_open;
r2 == r_closed;
else
r1 == r_closed;
r2 == r_open;
end use;
v1 == r1*i1;
v2 == r2*i2;
end architecture ideal;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity pwl_load_wa is
generic (
load_enable: string := "yes";
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time);
port (terminal p1, p2 : electrical);
end entity pwl_load_wa;
architecture ideal of pwl_load_wa is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
if load_enable = "yes" use
if domain = quiescent_domain or domain = frequency_domain use
v == i*res_init;
else
v == i*res_signal'ramp(1.0e-6, 1.0e-6);
end use;
else
i == 0.0;
end use;
-- purpose: Create Events to change resistance at specified times
-- type : combinational
-- inputs :
-- outputs: res
CreateEvent: process is
begin -- process CreateEvent
wait for t1;
res_signal <= res1;
wait for (t2-t1);
res_signal <= res2;
wait;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : v_pulse.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/07/09
-------------------------------------------------------------------------------
-- Description: Voltage Pulse Source
-- Includes Frequency Domain settings
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-- 2001/07/09 1.1 Mentor Graphics Changed input parameters to type
-- time. Uses time2real function.
-- Pulsewidth no longer includes
-- rise and fall times.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity v_pulse is
generic (
initial : voltage := 0.0; -- initial value [Volts]
pulse : voltage; -- pulsed value [Volts]
ti2p : time := 1ns; -- initial to pulse [Sec]
tp2i : time := 1ns; -- pulse to initial [Sec]
delay : time := 0ms; -- delay time [Sec]
width : time; -- duration of pulse [Sec]
period : time; -- period [Sec]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_pulse;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_pulse is
-- Declare Through and Across Branch Quantities
quantity v across i through pos to neg;
-- Declare quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
-- Signal used in CreateEvent process below
signal pulse_signal : voltage := initial;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
-- Note: these lines gave an error during simulation. Had to use a
-- function call instead.
-- constant ri2p : real := time'pos(ti2p) * 1.0e-15;
-- constant rp2i : real := time'pos(tp2i) * 1.0e-15;
-- Function to convert numbers of type TIME to type REAL
function time2real(tt : time) return real is
begin
return time'pos(tt) * 1.0e-15;
end time2real;
-- Convert ti2p and tp2i generics to type REAL (needed for 'RAMP attribute)
constant ri2p : real := time2real(ti2p);
constant rp2i : real := time2real(tp2i);
begin
if domain = quiescent_domain or domain = time_domain use
v == pulse_signal'ramp(ri2p, rp2i); -- create rise and fall transitions
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
-- purpose: Create events to define pulse shape
-- type : combinational
-- inputs :
-- outputs: pulse_signal
CreateEvent : process
begin
wait for delay;
loop
pulse_signal <= pulse;
wait for (width + ti2p);
pulse_signal <= initial;
wait for (period - width - ti2p);
end loop;
end process CreateEvent;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity buck_sw is
generic (
Vd : voltage := 0.7; -- Diode Voltage
Vramp : voltage := 2.5); -- P-P amplitude of ramp voltage
port (terminal input, output, ref, ctrl: electrical);
end entity buck_sw;
architecture average of buck_sw is
quantity Vout across Iout through output to ref;
quantity Vin across input to ref;
quantity Vctrl across ctrl to ref;
begin
Vout + Vd == Vctrl * Vin / Vramp; -- Averaged equation
end architecture average;
library IEEE;
library IEEE_proposed;
use ieee.math_real.all;
use IEEE_proposed.electrical_systems.all;
entity comp_2p2z is
generic (
gain : real := 100.0; -- High DC gain for good load regulation
fp1 : real := 7.5e3; -- Pole location to achieve crossover frequency
fp2 : real := 531.0e3;-- Pole location to cancel effect of ESR
fz1 : real := 403.0; -- Zero locations to cancel LC filter poles
fz2 : real := 403.0);
port (terminal input, output, ref : electrical);
end entity comp_2p2z;
architecture ltf of comp_2p2z is
quantity vin across input to ref;
quantity vout across iout through output to ref;
constant wp1 : real := math_2_pi*fp1; -- Pole freq (in radians)
constant wp2 : real := math_2_pi*fp2;
constant wz1 : real := math_2_pi*fz1; -- Zero freq (in radians)
constant wz2 : real := math_2_pi*fz2;
constant num : real_vector := (1.0, (wz1+wz2)/(wz1*wz2), 1.0/(wz1*wz2));
constant den : real_vector := (1.0e-9, 1.0, (wp1+wp2)/(wp1*wp2), 1.0/(wp1*wp2));
begin
vout == -1.0*gain*vin'ltf(num, den);
end architecture ltf;
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS3_BuckConverter_average is
end TB_CS3_BuckConverter_average;
architecture TB_CS3_BuckConverter_average of TB_CS3_BuckConverter_average is
-- Component declarations
-- Signal declarations
terminal vcomp_out : electrical;
terminal vctrl : electrical;
terminal vctrl_init : electrical;
terminal vin : electrical;
terminal vmid : electrical;
terminal vout : electrical;
terminal vref : electrical;
begin
-- Signal assignments
-- Component instances
L1 : entity work.inductor(ideal)
generic map(
ind => 6.5e-3
)
port map(
p1 => vmid,
p2 => vout
);
C1 : entity work.capacitor(ESR)
generic map(
cap => 6.0e-6,
r_esr => 50.0e-3
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vctrl_1 : entity work.v_constant(ideal)
generic map(
level => 0.327
)
port map(
pos => vctrl_init,
neg => ELECTRICAL_REF
);
Vref_1 : entity work.v_constant(ideal)
generic map(
level => 4.8
)
port map(
pos => vref,
neg => ELECTRICAL_REF
);
sw2 : entity work.sw_LoopCtrl_wa(ideal)
generic map(
sw_state => 1
)
port map(
p2 => vctrl_init,
c => vctrl,
p1 => vcomp_out
);
Electrical_Load6 : entity work.pwl_load_wa(ideal)
generic map(
t2 => 30 ms,
res2 => 5.0,
t1 => 5ms,
res1 => 1.0,
res_init => 2.4,
load_enable => "yes"
)
port map(
p1 => vout,
p2 => ELECTRICAL_REF
);
Vin_1 : entity work.v_pulse(ideal)
generic map(
initial => 42.0,
pulse => 42.0,
delay => 10ms,
width => 100ms,
period => 1000ms
)
port map(
pos => vin,
neg => ELECTRICAL_REF
);
buck_sw2 : entity work.buck_sw(average)
port map(
ctrl => vctrl,
input => vin,
ref => ELECTRICAL_REF,
output => vmid
);
comp_2p2z4 : entity work.comp_2p2z(ltf)
generic map(
fz1 => 403.0,
fz2 => 403.0,
gain => 100.0
)
port map(
input => vout,
output => vcomp_out,
ref => vref
);
end TB_CS3_BuckConverter_average;
--
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:18:39 12/23/2015
-- Design Name:
-- Module Name: module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control is
Port ( Clock : IN std_logic;
Initial : IN std_logic;
trafo : IN std_logic;
EN125 : out std_logic;
EN346 : out std_logic;
EN78 : out std_logic;
S : out std_logic_vector(1 downto 0);
S_t : out std_logic_vector(1 downto 0);
Result : out std_logic);
end control;
architecture Behavioral of control is
signal int_state_sig : std_logic_vector(2 downto 0) := "111" ;
signal S_sig :std_logic_vector(1 downto 0) := "00";
begin
S <= S_sig;
proc_counter: process (Clock, int_state_sig, Initial, trafo)
begin
if Clock = '1' and Clock'EVENT then
if trafo = '0' then
case int_state_sig is
when "000" => int_state_sig <= "001";
when "001" => int_state_sig <= "010";
when "010" => int_state_sig <= "011";
when "011" => int_state_sig <= "100";
when "100" => int_state_sig <= "101";
when "101" => int_state_sig <= "110";
when "110" => int_state_sig <= "111";
when "111" => if Initial = '1' then int_state_sig <= "000";
else int_state_sig <= "111";
end if;
when others => int_state_sig <= "111";
end case;
else
case int_state_sig is
when "000" => int_state_sig <= "001";
when "001" => int_state_sig <= "010";
when "010" => int_state_sig <= "011";
when "011" => int_state_sig <= "110";
when "110" => int_state_sig <= "111";
when "111" => if Initial = '1' then int_state_sig <= "000";
else int_state_sig <= "111";
end if;
when others => int_state_sig <= "111";
end case;
end if;
end if;
end process proc_counter;
register_enable_proc : process (int_state_sig, trafo)
begin
if trafo = '0' then
case int_state_sig is
when "000" => EN125 <= '1';
EN346 <= '0';
EN78 <= '0';
Result <= '0';
when "010" => EN125 <= '0';
EN346 <= '1';
EN78 <= '0';
Result <= '0';
when "100" => EN125 <= '0';
EN346 <= '0';
EN78 <= '1';
Result <= '0';
when "110" => EN125 <= '0';
EN346 <= '0';
EN78 <= '0';
Result <= '1';
when others => EN125 <= '0';
EN346 <= '0';
EN78 <= '0';
Result <= '0';
end case;
else
case int_state_sig is
when "000" => EN125 <= '1';
EN346 <= '0';
EN78 <= '0';
Result <= '0';
when "010" => EN125 <= '0';
EN346 <= '1';
EN78 <= '0';
Result <= '0';
when "110" => EN125 <= '0';
EN346 <= '0';
EN78 <= '0';
Result <= '1';
when others => EN125 <= '0';
EN346 <= '0';
EN78 <= '0';
Result <= '0';
end case;
end if;
end process register_enable_proc;
int_state_proc : process (int_state_sig, trafo)
begin
if trafo = '0' then
case int_state_sig is
when "000" => S_sig <= "00";
when "001" => S_sig <= "00";
when "010" => S_sig <= "01";
when "011" => S_sig <= "01";
when "100" => S_sig <= "10";
when "101" => S_sig <= "10";
when "110" => S_sig <= "11";
when "111" => S_sig <= "11";
when others => S_sig <= "00";
end case;
else
case int_state_sig is
when "000" => S_sig <= "00";
when "001" => S_sig <= "00";
when "010" => S_sig <= "01";
when "011" => S_sig <= "01";
when "110" => S_sig <= "11";
when "111" => S_sig <= "11";
when others => S_sig <= "00";
end case;
end if;
end process int_state_proc;
signal_S_t_proc : process (S_sig, trafo)
begin
if trafo = '0' then
S_t(1) <= S_sig(1);
S_t(0) <= S_sig(0);
else
S_t(1) <= S_sig(1);
S_t(0) <= not S_sig(0);
end if;
end process signal_S_t_proc;
end Behavioral;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.adjustable_pwm_pkg.ALL;
ENTITY adjustable_pwm_rtl_tb IS
END ENTITY adjustable_pwm_rtl_tb;
ARCHITECTURE sim OF adjustable_pwm_rtl_tb IS
--Sumulation Parameter:
CONSTANT main_period : TIME := 8 ns; -- 125MHz
CONSTANT frequency_resolution : INTEGER := 32;
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '0';
SIGNAL slv_frequency_divider : UNSIGNED(frequency_resolution-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL slv_ratio : UNSIGNED(frequency_resolution-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sl_pwm : STD_LOGIC := '0';
BEGIN
--create component
my_unit_under_test : adjustable_pwm
GENERIC MAP(frequency_resolution => frequency_resolution)
PORT MAP(
sl_clk => sl_clk,
sl_reset_n => sl_reset_n,
slv_frequency_divider => slv_frequency_divider,
slv_ratio => slv_ratio,
sl_pwm => sl_pwm
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 2*main_period;
sl_reset_n <= '1';
WAIT FOR 1000*main_period;
slv_frequency_divider <= to_unsigned(125,frequency_resolution);
WAIT FOR 1000*main_period;
slv_ratio <= to_unsigned(10,frequency_resolution);
WAIT FOR 1000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
-- Based on xwb_fabric_source.vhd from Tomasz Wlostowski
-- Modified by Lucas Russo <[email protected]>
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wb_stream_pkg.all;
entity xwb_stream_source is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
-- Decoded & buffered logic
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic_vector((c_wbs_data_width/8)-1 downto 0);
dreq_o : out std_logic
);
end xwb_stream_source;
architecture rtl of xwb_stream_source is
-- FIFO ranges and control bits location
constant c_data_lsb : natural := 0;
constant c_data_msb : natural := c_data_lsb + c_wbs_data_width - 1;
constant c_addr_lsb : natural := c_data_msb + 1;
constant c_addr_msb : natural := c_addr_lsb + c_wbs_address_width -1;
constant c_valid_bit : natural := c_addr_msb + 1;
constant c_sel_lsb : natural := c_valid_bit + 1;
constant c_sel_msb : natural := c_sel_lsb + (c_wbs_data_width/8) - 1;
constant c_eof_bit : natural := c_sel_msb + 1;
constant c_sof_bit : natural := c_eof_bit + 1;
constant c_logic_width : integer := c_sof_bit - c_valid_bit + 1;
constant c_fifo_width : integer := c_sof_bit - c_data_lsb + 1;
constant c_fifo_depth : integer := 32;
-- Signals
signal q_valid, full, we, rd, rd_d0 : std_logic;
signal fin, fout : std_logic_vector(c_fifo_width-1 downto 0);
signal pre_dvalid : std_logic;
signal pre_eof : std_logic;
signal pre_data : std_logic_vector(c_wbs_data_width-1 downto 0);
signal pre_addr : std_logic_vector(c_wbs_address_width-1 downto 0);
signal post_dvalid, post_eof, post_sof : std_logic;
signal post_eof_d : std_logic;
signal post_bytesel : std_logic_vector((c_wbs_data_width/8)-1 downto 0);
signal post_data : std_logic_vector(c_wbs_data_width-1 downto 0);
signal post_adr : std_logic_vector(c_wbs_address_width-1 downto 0);
signal err_status : t_wbs_status_reg;
signal cyc_int : std_logic;
begin -- rtl
err_status.error <= '1';
dreq_o <= not full;
rd <= not src_i.stall;
we <= sof_i or eof_i or error_i or dvalid_i;
pre_dvalid <= dvalid_i or error_i;
pre_data <= data_i when (error_i = '0') else f_marshall_wbs_status(err_status);
pre_addr <= addr_i when (error_i = '0') else std_logic_vector(c_WBS_STATUS);
pre_eof <= error_i or eof_i;
fin <= sof_i & pre_eof & bytesel_i & pre_dvalid & pre_addr & pre_data;
cmp_fifo : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid
);
post_sof <= fout(c_sof_bit);
post_eof <= fout(c_eof_bit);
post_dvalid <= fout(c_valid_bit);
post_bytesel <= fout(c_sel_msb downto c_sel_lsb);
post_data <= fout(c_data_msb downto c_data_lsb);
post_adr <= fout(c_addr_msb downto c_addr_lsb);
p_gen_cyc : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_int <= '0';
else
if(src_i.stall = '0' and q_valid = '1') then
-- SOF and SOF signals must be one clock cycle long
-- and must be asserted at the same clock edge as the valid
-- signal!
if(post_sof = '1') then --or post_eof = '1')then
cyc_int <= '1';
elsif(post_eof = '1') then
cyc_int <= '0';
end if;
end if;
end if;
end if;
end process;
src_o.cyc <= cyc_int or post_sof;
src_o.we <= '1';
src_o.stb <= post_dvalid and q_valid;
--src_o.sel <= almost_all_ones & not fout(c_sel_bit);
src_o.sel <= post_bytesel;
src_o.dat <= post_data;--fout(c_data_msb downto c_data_lsb);
src_o.adr <= post_adr;--fout(c_addr_msb downto c_addr_lsb);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.wb_stream_pkg.all;
entity wb_stream_source is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_dat_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
src_adr_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
src_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_ack_i : in std_logic;
src_err_i : in std_logic;
-- Decoded & buffered fabric
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic
);
end wb_stream_source;
architecture wrapper of wb_stream_source is
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic);
end component;
signal src_in : t_wbs_source_in;
signal src_out : t_wbs_source_out;
begin -- wrapper
cmp_stream_source_wrapper : xwb_stream_source
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
src_i => src_in,
src_o => src_out,
addr_i => addr_i,
data_i => data_i,
dvalid_i => dvalid_i,
sof_i => sof_i,
eof_i => eof_i,
error_i => error_i,
bytesel_i => bytesel_i,
dreq_o => dreq_o
);
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
src_we_o <= src_out.we;
src_sel_o <= src_out.sel;
src_adr_o <= src_out.adr;
src_dat_o <= src_out.dat;
src_in.rty <= '0';
src_in.err <= src_err_i;
src_in.ack <= src_ack_i;
src_in.stall <= src_stall_i;
end wrapper;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2416.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p10n02i02416ent IS
END c07s03b02x00p10n02i02416ent;
ARCHITECTURE c07s03b02x00p10n02i02416arch OF c07s03b02x00p10n02i02416ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_2 : real;
ele_3 : boolean;
end record;
variable v24 : rec;
BEGIN
v24 := (ele_2 => 23, ele_3 => True); -- Failure_here
-- ele_2 is real.
assert FALSE
report "***FAILED TEST: c07s03b02x00p10n02i02416 - Elements of an aggregate should have the same type as that determined by the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p10n02i02416arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2416.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p10n02i02416ent IS
END c07s03b02x00p10n02i02416ent;
ARCHITECTURE c07s03b02x00p10n02i02416arch OF c07s03b02x00p10n02i02416ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_2 : real;
ele_3 : boolean;
end record;
variable v24 : rec;
BEGIN
v24 := (ele_2 => 23, ele_3 => True); -- Failure_here
-- ele_2 is real.
assert FALSE
report "***FAILED TEST: c07s03b02x00p10n02i02416 - Elements of an aggregate should have the same type as that determined by the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p10n02i02416arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2416.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p10n02i02416ent IS
END c07s03b02x00p10n02i02416ent;
ARCHITECTURE c07s03b02x00p10n02i02416arch OF c07s03b02x00p10n02i02416ent IS
BEGIN
TESTING: PROCESS
type rec is record
ele_2 : real;
ele_3 : boolean;
end record;
variable v24 : rec;
BEGIN
v24 := (ele_2 => 23, ele_3 => True); -- Failure_here
-- ele_2 is real.
assert FALSE
report "***FAILED TEST: c07s03b02x00p10n02i02416 - Elements of an aggregate should have the same type as that determined by the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p10n02i02416arch;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity gfmapinv is port (
-- ah -> High Data Input (4 std_logic)
-- al -> Low Data Input (4 std_logic)
-- a -> Data Output (remapped back) (8 std_logic)
ah, al : in std_logic_vector (3 downto 0);
a : out std_logic_vector (7 downto 0) );
end gfmapinv;
-- Architecture of the Component
architecture a_gfmapinv of gfmapinv is
begin
-- Inverse Mapping Process
a(0) <= al(0) xor ah(0);
a(1) <= ah(0) xor ah(1) xor ah(3);
a(2) <= al(1) xor ah(3) xor ah(0) xor ah(1);
a(3) <= ah(0) xor ah(1) xor al(1) xor ah(2);
a(4) <= al(1) xor ah(3) xor ah(0) xor ah(1) xor al(3);
a(5) <= ah(0) xor ah(1) xor al(2);
a(6) <= al(1) xor ah(3) xor al(2) xor al(3) xor ah(0);
a(7) <= ah(0) xor ah(1) xor al(2) xor ah(3);
end a_gfmapinv;
|
-- Library Declaration
library IEEE;
use IEEE.std_logic_1164.all;
-- Component Declaration
entity gfmapinv is port (
-- ah -> High Data Input (4 std_logic)
-- al -> Low Data Input (4 std_logic)
-- a -> Data Output (remapped back) (8 std_logic)
ah, al : in std_logic_vector (3 downto 0);
a : out std_logic_vector (7 downto 0) );
end gfmapinv;
-- Architecture of the Component
architecture a_gfmapinv of gfmapinv is
begin
-- Inverse Mapping Process
a(0) <= al(0) xor ah(0);
a(1) <= ah(0) xor ah(1) xor ah(3);
a(2) <= al(1) xor ah(3) xor ah(0) xor ah(1);
a(3) <= ah(0) xor ah(1) xor al(1) xor ah(2);
a(4) <= al(1) xor ah(3) xor ah(0) xor ah(1) xor al(3);
a(5) <= ah(0) xor ah(1) xor al(2);
a(6) <= al(1) xor ah(3) xor al(2) xor al(3) xor ah(0);
a(7) <= ah(0) xor ah(1) xor al(2) xor ah(3);
end a_gfmapinv;
|
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_1
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_1
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
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-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
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-- ** "as-is" solely for use in developing programs and **
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-- ** code, or information as one possible implementation of **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
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-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
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-- ** done at the users sole risk and will be unsupported. **
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-- ** code and therefore cannot answer specific questions related **
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-- ** code IP shall only address issues and questions related **
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-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_1
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v12_0_5
-- - Added sleep, wr_rst_busy, and rd_rst_busy signals
-- - Changed FULL_FLAGS_RST_VAL to '1'
-- ^^^^^^
-- KARTHEEK 03/02/2016
-- - Update to use fifo_generator_v13_1_1
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library fifo_generator_v13_1_1;
use fifo_generator_v13_1_1.all;
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
-- changing this to C_FAMILY
Constant FAMILY_TO_USE : string := C_FAMILY; -- function from family_support.vhd
-- Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
-- lib_fifo supports all families
Constant FAMILY_IS_SUPPORTED : boolean := true;
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal WR_RST_BUSY : std_logic;
signal RD_RST_BUSY : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
-- GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
-- begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
-- DO_ASSERTION : process
-- begin
-- Wait until second rising clock edge to issue assertion
-- Wait until Clk = '1';
-- wait until Clk = '0';
-- Wait until Clk = '1';
-- Report an error in simulation environment
-- assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
-- severity ERROR;
-- Wait;-- halt this process
-- end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
-- Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
-- Almost_full <= '0' ; -- : out std_logic;
-- Full <= '0' ; -- : out std_logic;
-- Empty <= '1' ; -- : out std_logic;
-- Rd_ack <= '0' ; -- : out std_logic;
-- Wr_ack <= '0' ; -- : out std_logic;
-- Rd_err <= '1' ; -- : out std_logic;
-- Wr_err <= '1' ; -- : out std_logic
-- Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
-- end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
--UltraScale_device: if (FAMILY_TO_USE = "virtexu" or FAMILY_TO_USE = "kintexu" or FAMILY_TO_USE = "virtexuplus" or FAMILY_TO_USE = "kintexuplus" or FAMILY_TO_USE = "zynquplus") generate
UltraScale_device: if (FAMILY_TO_USE /= "virtex7" and FAMILY_TO_USE /= "kintex7" and FAMILY_TO_USE /= "artix7" and FAMILY_TO_USE /= "zynq") generate
begin
Full <= sig_full or WR_RST_BUSY;
end generate UltraScale_device;
--Series7_device: if (FAMILY_TO_USE /= "virtexu" and FAMILY_TO_USE /= "kintexu" and FAMILY_TO_USE /= "virtexuplus" and FAMILY_TO_USE /= "kintexuplus" and FAMILY_TO_USE/= "zynquplus") generate
Series7_device: if (FAMILY_TO_USE = "virtex7" or FAMILY_TO_USE = "kintex7" or FAMILY_TO_USE = "artix7" or FAMILY_TO_USE = "zynq") generate
begin
Full <= sig_full;
end generate Series7_device;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v13_1_1.fifo_generator_v13_1_1
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
sleep => '0',
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
wr_rst_busy => WR_RST_BUSY,
rd_rst_busy => RD_RST_BUSY,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
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