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--------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 19:20:36 09/09/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Levi/P12_Gray_to_Binary_Converter/Gray_to_Binary_Converter_TB.vhd
-- Project Name: P12_Gray_to_Binary_Converter
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Gray_to_Binary_Converter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Gray_to_Binary_Converter_TB IS
END Gray_to_Binary_Converter_TB;
ARCHITECTURE behavior OF Gray_to_Binary_Converter_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Gray_to_Binary_Converter
PORT(
Gray : IN std_logic_vector(3 downto 0);
Binary : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal Gray : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal Binary : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
-- constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Gray_to_Binary_Converter PORT MAP (
Gray => Gray,
Binary => Binary
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
--
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
Gray <= "0000"; wait for 100 ns;
Gray <= "0001"; wait for 100 ns;
Gray <= "0011"; wait for 100 ns;
Gray <= "0010"; wait for 100 ns;
Gray <= "0110"; wait for 100 ns;
Gray <= "0111"; wait for 100 ns;
Gray <= "0101"; wait for 100 ns;
Gray <= "0100"; wait for 100 ns;
Gray <= "1100"; wait for 100 ns;
Gray <= "1101"; wait for 100 ns;
Gray <= "1111"; wait for 100 ns;
Gray <= "1110"; wait for 100 ns;
Gray <= "1010"; wait for 100 ns;
Gray <= "1011"; wait for 100 ns;
Gray <= "1001"; wait for 100 ns;
Gray <= "1000"; wait for 100 ns;
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2414.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p10n01i02414ent IS
END c07s03b02x00p10n01i02414ent;
ARCHITECTURE c07s03b02x00p10n01i02414arch OF c07s03b02x00p10n01i02414ent IS
type s27 is array (1 to 4) of integer;
BEGIN
TESTING: PROCESS
variable V1 : s27 := (1, 2, 3, 4);
BEGIN
(v1(1) , v1(2)) := (v1(3), v1(4)); -- Failure_here
-- type of aggregate not
-- determinable from context
assert FALSE
report "***FAILED TEST: c07s03b02x00p10n01i02414 - Type of the aggregate must be determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p10n01i02414arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2414.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p10n01i02414ent IS
END c07s03b02x00p10n01i02414ent;
ARCHITECTURE c07s03b02x00p10n01i02414arch OF c07s03b02x00p10n01i02414ent IS
type s27 is array (1 to 4) of integer;
BEGIN
TESTING: PROCESS
variable V1 : s27 := (1, 2, 3, 4);
BEGIN
(v1(1) , v1(2)) := (v1(3), v1(4)); -- Failure_here
-- type of aggregate not
-- determinable from context
assert FALSE
report "***FAILED TEST: c07s03b02x00p10n01i02414 - Type of the aggregate must be determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p10n01i02414arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2414.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p10n01i02414ent IS
END c07s03b02x00p10n01i02414ent;
ARCHITECTURE c07s03b02x00p10n01i02414arch OF c07s03b02x00p10n01i02414ent IS
type s27 is array (1 to 4) of integer;
BEGIN
TESTING: PROCESS
variable V1 : s27 := (1, 2, 3, 4);
BEGIN
(v1(1) , v1(2)) := (v1(3), v1(4)); -- Failure_here
-- type of aggregate not
-- determinable from context
assert FALSE
report "***FAILED TEST: c07s03b02x00p10n01i02414 - Type of the aggregate must be determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p10n01i02414arch;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Reset_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when Reset_state =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END; |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Reset_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when Reset_state =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END; |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Reset_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when Reset_state =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END; |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Reset_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when Reset_state =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END; |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Reset_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when Reset_state =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END; |
--Copyright (C) 2016 Siavoosh Payandeh Azad, Behrad Niazmand
-- This design is based on the proposed method, discussed in the following publication:
-- "A Fault Prediction Module for a Fault Tolerant NoC Operation"
-- by Silveira, J.; Bodin, M.; Ferreira, J.M.; Cadore Pinheiro, A.; Webber, T.; Marcon, C.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, Intermittent, Faulty: out std_logic
);
end counter_threshold_classifier;
architecture behavior of counter_threshold_classifier is
signal faulty_counter_in, faulty_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal healthy_counter_in, healthy_counter_out: std_logic_vector(counter_depth-1 downto 0);
signal NET: std_logic; --no error threshold
signal DET: std_logic; --detected error threshold
signal reset_counters: std_logic;
TYPE STATE_TYPE IS (Healthy_state, Intermittent_state, Faulty_state, Reset_state);
SIGNAL state, next_state : STATE_TYPE := Healthy_state;
begin
process(clk, reset)begin
if reset = '0' then
faulty_counter_out <= (others => '0');
healthy_counter_out <= (others => '0');
state <= Reset_state;
elsif clk'event and clk = '1' then
faulty_counter_out <= faulty_counter_in;
healthy_counter_out <= healthy_counter_in;
state <= next_state;
end if;
end process;
process(faulty_packet, reset_counters, faulty_counter_out)begin
if reset_counters = '1' then
faulty_counter_in <= (others => '0');
elsif faulty_packet = '1' then
faulty_counter_in <= faulty_counter_out + 1;
else
faulty_counter_in <= faulty_counter_out;
end if;
end process;
process(Healthy_packet, reset_counters, healthy_counter_out,faulty_counter_out)begin
if reset_counters = '1' then
healthy_counter_in <= (others => '0');
elsif Healthy_packet = '1' and faulty_counter_out /= std_logic_vector(to_unsigned(0, faulty_counter_out'length)) then
healthy_counter_in <= healthy_counter_out + 1;
else
healthy_counter_in <= healthy_counter_out;
end if;
end process;
process(healthy_counter_out, faulty_counter_out) begin
reset_counters <= '0';
DET <= '0';
NET <= '0';
if healthy_counter_out = std_logic_vector(to_unsigned(healthy_counter_threshold, healthy_counter_out'length)) then
NET <= '1';
reset_counters <= '1';
end if;
if faulty_counter_out = std_logic_vector(to_unsigned(faulty_counter_threshold, faulty_counter_out'length)) then
DET <= '1';
reset_counters <= '1';
end if;
end process;
process (NET, DET, state)begin
Healthy <= '0';
Intermittent <= '0';
Faulty <= '0';
case state is
when Healthy_state =>
if NET = '1' then
next_state <= Healthy_state;
elsif DET = '1' then
next_state <= Intermittent_state;
Intermittent <= '1';
else
next_state <= Healthy_state;
end if;
when Intermittent_state =>
if NET = '1' then
next_state <= Healthy_state;
Healthy <= '1';
elsif DET = '1' then
next_state <= Faulty_state;
Faulty <= '1';
else
next_state <= Intermittent_state;
end if;
when Faulty_state =>
next_state <= Faulty_state;
when Reset_state =>
next_state <= Healthy_state;
Healthy <= '1';
end case;
end process;
END; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:19:18 09/27/2017
-- Design Name:
-- Module Name: Sumador32bit - Arq_Sumador32bit
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sumador32bit is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
Reset : in STD_LOGIC;
Result : out STD_LOGIC_VECTOR (31 downto 0));
end Sumador32bit;
architecture arq_Sumador32bit of Sumador32bit is
begin
process(Oper1,Oper2,Reset)
begin
if reset='1' then
Result<= "00000000000000000000000000000000";
else
Result<= Oper1 + Oper2;
end if;
end process;
end arq_Sumador32bit;
|
package sumpkg is
type int_vector is array (natural range <>) of integer;
function get_left(a : int_vector) return integer;
function get_right(a : int_vector) return integer;
function get_length(a : int_vector) return integer;
function sum(a : int_vector) return integer;
end package;
package body sumpkg is
function sum(a : int_vector) return integer is
variable result : integer := 0;
begin
for i in a'range loop
result := result + a(i);
end loop;
return result;
end function;
function get_left(a : int_vector) return integer is
begin
return a'left;
end function;
function get_right(a : int_vector) return integer is
begin
return a'right;
end function;
function get_length(a : int_vector) return integer is
begin
return a'length;
end function;
end package body;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1509.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01509ent IS
END c08s09b00x00p02n01i01509ent;
ARCHITECTURE c08s09b00x00p02n01i01509arch OF c08s09b00x00p02n01i01509ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
L1 :
while counter < 10 loop
counter := counter + 1;
end loop L1;
assert NOT( counter = 10 )
report "***PASSED TEST: c08s09b00x00p02n01i01509"
severity NOTE;
assert ( counter = 10 )
report "***FAILED TEST: c08s09b00x00p02n01i01509 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01509arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1509.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01509ent IS
END c08s09b00x00p02n01i01509ent;
ARCHITECTURE c08s09b00x00p02n01i01509arch OF c08s09b00x00p02n01i01509ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
L1 :
while counter < 10 loop
counter := counter + 1;
end loop L1;
assert NOT( counter = 10 )
report "***PASSED TEST: c08s09b00x00p02n01i01509"
severity NOTE;
assert ( counter = 10 )
report "***FAILED TEST: c08s09b00x00p02n01i01509 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01509arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1509.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01509ent IS
END c08s09b00x00p02n01i01509ent;
ARCHITECTURE c08s09b00x00p02n01i01509arch OF c08s09b00x00p02n01i01509ent IS
BEGIN
TESTING: PROCESS
variable counter : integer := 0;
BEGIN
L1 :
while counter < 10 loop
counter := counter + 1;
end loop L1;
assert NOT( counter = 10 )
report "***PASSED TEST: c08s09b00x00p02n01i01509"
severity NOTE;
assert ( counter = 10 )
report "***FAILED TEST: c08s09b00x00p02n01i01509 - In loop statement, the reserved word loop must be followed by a sequence of statements, and the reserved words end loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01509arch;
|
-- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____32.500______0.000______50.0______280.255____257.452
-- CLK_OUT2____25.000______0.000______50.0______306.503____257.452
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_6,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "HIGH",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 39,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 30,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 39,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => LOCKED,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
package p is
type int_ptr is access integer; -- OK
type bad1 is access foo; -- Error
type rec;
type rec_ptr is access rec;
type rec is record
value : integer;
link : rec_ptr;
end record;
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
type string_ptr is access string;
end package;
package body p is
procedure test is
variable v : int_ptr;
variable i : integer;
variable r : rec_ptr;
variable a : int_vec_ptr;
variable s : string_ptr;
begin
v := null; -- OK
i := null; -- Error
deallocate(v); -- OK
v := new integer; -- OK
v := new integer'(5); -- OK
v := new 5; -- Error
v := new i; -- Error
v.all := 5; -- OK
v := 5; -- Error
i := v.all + 5; -- OK
r := new rec; -- OK
r.all.value := 1; -- OK
r.value := 1; -- OK
r.link := r; -- OK
r.link := r.all; -- Error
i := r.value; -- OK
r := r.all.link; -- OK
a := new int_vec(1 to 3); -- OK
a.all(5) := 2; -- OK
a(5) := 2; -- OK
a(1 to 2) := (1, 2); -- OK
s := new string'(""); -- OK
s := new integer'(1); -- Error
s := new s(1 to 3); -- Error
end procedure;
procedure test2(x : inout rec_ptr) is
begin
x.value := x.value + 1;
end procedure;
procedure test3 is
type a;
type a is access integer; -- OK
variable v : a; -- OK
begin
end procedure;
type int_ptr_array is array (integer range <>) of int_ptr;
type int_ptr_array_ptr is access int_ptr_array;
procedure alloc_ptr_array(x : out int_ptr_array_ptr) is
begin
x := new int_ptr_array; -- Error
x := new int_ptr_array(1 to 3); -- OK
x.all := (null, null, null); -- OK
end procedure;
procedure tets4 is
type bvp is access bit_vector;
variable x : bvp(1 to 4) := new bit_vector'("1010"); -- OK
variable y : int_ptr(1 to 3) := int_ptr'(null); -- Error
begin
end procedure;
end package body;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Shift_Register_rst_n_bits
-- Module Name: Shift_Register_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Shift Register of size bits with reset signal, that only registers when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
--
-- The circuits parameters
--
-- size :
--
-- The size of the register in bits.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_register_rst_nbits is
Generic (size : integer);
Port (
data_in : in STD_LOGIC;
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0);
data_out : out STD_LOGIC
);
end shift_register_rst_nbits;
architecture Behavioral of shift_register_rst_nbits is
signal internal_value : STD_LOGIC_VECTOR((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= rst_value;
elsif(ce = '1') then
internal_value <= internal_value((size - 2) downto 0) & data_in;
else
null;
end if;
end if;
end process;
data_out <= internal_value(size - 1);
q <= internal_value;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library pvz;
use pvz.pvz_objects.all;
-- 逻辑部分
entity Logic is
port(
reset: in std_logic;
clock: in std_logic;
out_plants: out plant_matrix;
out_zombies: out zombie_vector;
new_plant: in std_logic; -- 新植物信号
new_plant_type: in std_logic_vector(1 downto 0); -- 新植物类型
new_plant_x, new_plant_y: in integer range 0 to M-1; -- 新植物坐标
out_lost : out std_logic; -- 输赢
out_round : out std_logic_vector(3 downto 0)
);
end entity;
architecture bhv of Logic is
signal count: std_logic_vector(30 downto 0);
signal pea_clk_count : std_logic_vector(10 downto 0);
signal zombie_count : std_logic_vector(5 downto 0);
signal pea_clk: std_logic;
signal plants: plant_matrix := (others => (others => ("01", "0000", M, '0', "0000")));
signal zombies: zombie_vector := (others => ("0000", 0));
signal passed_round : std_logic_vector(3 downto 0) := (others => '0'); -- 过去了多少轮
signal restart : std_logic := '0';
constant ROUND_CLK : integer := 20;
constant ZOMBIE_MOVE_COUNT : integer := 3;
constant NEW_ZOMBIE_Y : y_vector := (1, 3, 0, 4, 2, 3, 2, 0, 1, 4, 2, 4, 3, 1, 0, 1, 0, 3, 2, 4);
begin
out_zombies <= zombies;
out_plants <= plants;
process(clock)
begin
if (rising_edge(clock)) then
restart <= reset;
if (count = 32000000) then
count <= (others => '0');
pea_clk <= '1';
else
count <= count + 1;
pea_clk <= '0';
end if;
end if;
end process;
-- 处理豌豆
process(pea_clk, new_plant, reset)
variable p: plant;
variable x, y: integer range 0 to M-1;
constant NUT_HARM : integer := 1;
constant NORM_HARM : integer := 2;
variable has_lost : std_logic := '0';
variable new_y: integer range 0 to N-1;
begin
if (rising_edge(pea_clk)) then
if (restart='1') then
for i in 0 to N-1 loop
for j in 0 to M-1 loop
plants(i)(j).hp <= (others=>'0');
end loop;
end loop;
for i in 0 to N-1 loop
zombies(i).hp <= "0000";
end loop;
has_lost := '0';
out_lost <= '0';
passed_round <= (others => '0');
else
if (new_plant = '1') then
if (plants(new_plant_y)(new_plant_x).hp > 0 and new_plant_type = "10") then
plants(new_plant_y)(new_plant_x).with_sun <= '0';
plants(new_plant_y)(new_plant_x).cd <= "0000";
plants(new_plant_y)(new_plant_x).plant_type <= "10";
elsif (not(zombies(new_plant_y).x = new_plant_x and zombies(new_plant_y).hp > 0)) then
plants(new_plant_y)(new_plant_x).pea <= M;
plants(new_plant_y)(new_plant_x).with_sun <= '0';
plants(new_plant_y)(new_plant_x).cd <= "0100";
plants(new_plant_y)(new_plant_x).hp <= "1000";
plants(new_plant_y)(new_plant_x).plant_type <= new_plant_type;
end if;
end if;
-- 更新植物
if (reset='1') then
for i in 0 to N-1 loop
for j in 0 to M-1 loop
plants(i)(j).pea <= M;
plants(i)(j).with_sun <= '0';
plants(i)(j).cd <= "0000";
--plants(i*M + j).hp <= "0000";
end loop;
end loop;
else
for i in 0 to N-1 loop
for j in 0 to M-1 loop
p := plants(i)(j);
if (p.hp > 0 and p.plant_type = "00") then
if (zombies(i).hp > 0 and zombies(i).x >= j) then
if (p.pea = zombies(i).x or p.pea = zombies(i).x-1) then
plants(i)(j).pea <= M;
zombies(i).hp <= zombies(i).hp - 1;
elsif (plants(i)(j).pea < M) then
plants(i)(j).pea <= p.pea + 1;
elsif (p.cd = 0) then
plants(i)(j).pea <= j;
plants(i)(j).cd <= "1010";
end if;
elsif (p.pea < M) then
plants(i)(j).pea <= p.pea + 1;
end if;
if (p.cd > 0) then
plants(i)(j).cd <= p.cd - 1;
end if;
elsif (p.hp > 0 and p.plant_type = "10") then -- 向日葵产生阳光
if (p.cd = 0) then
if (p.with_sun = '1') then
plants(i)(j).with_sun <= '0';
elsif (p.with_sun = '0') then
plants(i)(j).with_sun <= '1';
end if;
plants(i)(j).cd <= "1010";
else
plants(i)(j).cd <= p.cd - 1;
end if;
end if;
end loop;
end loop;
end if;
-- 更新僵尸
if pea_clk_count=ROUND_CLK then
pea_clk_count <= (others => '0');
new_y := NEW_ZOMBIE_Y(conv_integer(unsigned(passed_round)));
passed_round <= passed_round + 1;
zombies(new_y).x <= M;
zombies(new_y).hp <= "0101";
else
pea_clk_count <= pea_clk_count + 1;
end if;
if (zombie_count=ZOMBIE_MOVE_COUNT) then
for i in 0 to N-1 loop
if (zombies(i).hp > 0) then
if (plants(i)(zombies(i).x-1).hp > 0) then
if (plants(i)(zombies(i).x-1).plant_type="01") then -- 坚果墙的防御力较高特殊处理
plants(i)(zombies(i).x-1).hp <= plants(i)(zombies(i).x-1).hp - NUT_HARM;
else
plants(i)(zombies(i).x-1).hp <= plants(i)(zombies(i).x-1).hp - NORM_HARM;
end if;
else
zombies(i).x <= zombies(i).x - 1;
end if;
end if;
end loop;
zombie_count <= (others=>'0');
else
zombie_count <= zombie_count + 1;
end if;
-- 判断是否输了
for i in 0 to N-1 loop
if (zombies(i).hp > 0 and zombies(i).x = 0 and plants(i)(zombies(i).x).hp = 0) then
has_lost := '1';
end if;
end loop;
out_lost <= has_lost;
end if;
end if;
end process;
process(passed_round)
begin
out_round <= passed_round;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2260.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p05n01i02260ent IS
END c07s02b06x00p05n01i02260ent;
ARCHITECTURE c07s02b06x00p05n01i02260arch OF c07s02b06x00p05n01i02260ent IS
BEGIN
TESTING: PROCESS
constant rem11 : integer := (1 - 4) rem (1 - 4);
constant rem12 : integer := (1 - 4) rem (2 - 4);
constant rem13 : integer := (1 - 4) rem (3 - 4);
constant rem15 : integer := (1 - 4) rem (5 - 4);
constant rem16 : integer := (1 - 4) rem (6 - 4);
constant rem17 : integer := (1 - 4) rem (7 - 4);
constant rem18 : integer := (1 - 4) rem (8 - 4);
constant rem19 : integer := (1 - 4) rem (9 - 4);
constant rem41 : integer := (4 - 4) rem (1 - 4);
constant rem42 : integer := (4 - 4) rem (2 - 4);
constant rem43 : integer := (4 - 4) rem (3 - 4);
constant rem45 : integer := (4 - 4) rem (5 - 4);
constant rem46 : integer := (4 - 4) rem (6 - 4);
constant rem47 : integer := (4 - 4) rem (7 - 4);
constant rem48 : integer := (4 - 4) rem (8 - 4);
constant rem49 : integer := (4 - 4) rem (9 - 4);
constant rem61 : integer := (6 - 4) rem (1 - 4);
constant rem62 : integer := (6 - 4) rem (2 - 4);
constant rem63 : integer := (6 - 4) rem (3 - 4);
constant rem65 : integer := (6 - 4) rem (5 - 4);
constant rem66 : integer := (6 - 4) rem (6 - 4);
constant rem67 : integer := (6 - 4) rem (7 - 4);
constant rem68 : integer := (6 - 4) rem (8 - 4);
constant rem69 : integer := (6 - 4) rem (9 - 4);
variable four : integer := 4;
BEGIN
assert rem11 = (1 - four) rem (1 - four);
assert rem12 = (1 - four) rem (2 - four);
assert rem13 = (1 - four) rem (3 - four);
assert rem15 = (1 - four) rem (5 - four);
assert rem16 = (1 - four) rem (6 - four);
assert rem17 = (1 - four) rem (7 - four);
assert rem18 = (1 - four) rem (8 - four);
assert rem19 = (1 - four) rem (9 - four);
assert rem41 = (4 - four) rem (1 - four);
assert rem42 = (4 - four) rem (2 - four);
assert rem43 = (4 - four) rem (3 - four);
assert rem45 = (4 - four) rem (5 - four);
assert rem46 = (4 - four) rem (6 - four);
assert rem47 = (4 - four) rem (7 - four);
assert rem48 = (4 - four) rem (8 - four);
assert rem49 = (4 - four) rem (9 - four);
assert rem61 = (6 - four) rem (1 - four);
assert rem62 = (6 - four) rem (2 - four);
assert rem63 = (6 - four) rem (3 - four);
assert rem65 = (6 - four) rem (5 - four);
assert rem66 = (6 - four) rem (6 - four);
assert rem67 = (6 - four) rem (7 - four);
assert rem68 = (6 - four) rem (8 - four);
assert rem69 = (6 - four) rem (9 - four);
assert NOT((rem11 = (1 - four) rem (1 - four)) and
( rem12 = (1 - four) rem (2 - four)) and
( rem13 = (1 - four) rem (3 - four)) and
( rem15 = (1 - four) rem (5 - four)) and
( rem16 = (1 - four) rem (6 - four)) and
( rem17 = (1 - four) rem (7 - four)) and
( rem18 = (1 - four) rem (8 - four)) and
( rem19 = (1 - four) rem (9 - four)) and
( rem41 = (4 - four) rem (1 - four)) and
( rem42 = (4 - four) rem (2 - four)) and
( rem43 = (4 - four) rem (3 - four)) and
( rem45 = (4 - four) rem (5 - four)) and
( rem46 = (4 - four) rem (6 - four)) and
( rem47 = (4 - four) rem (7 - four)) and
( rem48 = (4 - four) rem (8 - four)) and
( rem49 = (4 - four) rem (9 - four)) and
( rem61 = (6 - four) rem (1 - four)) and
( rem62 = (6 - four) rem (2 - four)) and
( rem63 = (6 - four) rem (3 - four)) and
( rem65 = (6 - four) rem (5 - four)) and
( rem66 = (6 - four) rem (6 - four)) and
( rem67 = (6 - four) rem (7 - four)) and
( rem68 = (6 - four) rem (8 - four)) and
( rem69 = (6 - four) rem (9 - four)) )
report "***PASSED TEST: c07s02b06x00p05n01i02260"
severity NOTE;
assert (( rem11 = (1 - four) rem (1 - four)) and
( rem12 = (1 - four) rem (2 - four)) and
( rem13 = (1 - four) rem (3 - four)) and
( rem15 = (1 - four) rem (5 - four)) and
( rem16 = (1 - four) rem (6 - four)) and
( rem17 = (1 - four) rem (7 - four)) and
( rem18 = (1 - four) rem (8 - four)) and
( rem19 = (1 - four) rem (9 - four)) and
( rem41 = (4 - four) rem (1 - four)) and
( rem42 = (4 - four) rem (2 - four)) and
( rem43 = (4 - four) rem (3 - four)) and
( rem45 = (4 - four) rem (5 - four)) and
( rem46 = (4 - four) rem (6 - four)) and
( rem47 = (4 - four) rem (7 - four)) and
( rem48 = (4 - four) rem (8 - four)) and
( rem49 = (4 - four) rem (9 - four)) and
( rem61 = (6 - four) rem (1 - four)) and
( rem62 = (6 - four) rem (2 - four)) and
( rem63 = (6 - four) rem (3 - four)) and
( rem65 = (6 - four) rem (5 - four)) and
( rem66 = (6 - four) rem (6 - four)) and
( rem67 = (6 - four) rem (7 - four)) and
( rem68 = (6 - four) rem (8 - four)) and
( rem69 = (6 - four) rem (9 - four)) )
report "***FAILED TEST: c07s02b06x00p05n01i02260 - Constant integer type rem test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p05n01i02260arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2260.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p05n01i02260ent IS
END c07s02b06x00p05n01i02260ent;
ARCHITECTURE c07s02b06x00p05n01i02260arch OF c07s02b06x00p05n01i02260ent IS
BEGIN
TESTING: PROCESS
constant rem11 : integer := (1 - 4) rem (1 - 4);
constant rem12 : integer := (1 - 4) rem (2 - 4);
constant rem13 : integer := (1 - 4) rem (3 - 4);
constant rem15 : integer := (1 - 4) rem (5 - 4);
constant rem16 : integer := (1 - 4) rem (6 - 4);
constant rem17 : integer := (1 - 4) rem (7 - 4);
constant rem18 : integer := (1 - 4) rem (8 - 4);
constant rem19 : integer := (1 - 4) rem (9 - 4);
constant rem41 : integer := (4 - 4) rem (1 - 4);
constant rem42 : integer := (4 - 4) rem (2 - 4);
constant rem43 : integer := (4 - 4) rem (3 - 4);
constant rem45 : integer := (4 - 4) rem (5 - 4);
constant rem46 : integer := (4 - 4) rem (6 - 4);
constant rem47 : integer := (4 - 4) rem (7 - 4);
constant rem48 : integer := (4 - 4) rem (8 - 4);
constant rem49 : integer := (4 - 4) rem (9 - 4);
constant rem61 : integer := (6 - 4) rem (1 - 4);
constant rem62 : integer := (6 - 4) rem (2 - 4);
constant rem63 : integer := (6 - 4) rem (3 - 4);
constant rem65 : integer := (6 - 4) rem (5 - 4);
constant rem66 : integer := (6 - 4) rem (6 - 4);
constant rem67 : integer := (6 - 4) rem (7 - 4);
constant rem68 : integer := (6 - 4) rem (8 - 4);
constant rem69 : integer := (6 - 4) rem (9 - 4);
variable four : integer := 4;
BEGIN
assert rem11 = (1 - four) rem (1 - four);
assert rem12 = (1 - four) rem (2 - four);
assert rem13 = (1 - four) rem (3 - four);
assert rem15 = (1 - four) rem (5 - four);
assert rem16 = (1 - four) rem (6 - four);
assert rem17 = (1 - four) rem (7 - four);
assert rem18 = (1 - four) rem (8 - four);
assert rem19 = (1 - four) rem (9 - four);
assert rem41 = (4 - four) rem (1 - four);
assert rem42 = (4 - four) rem (2 - four);
assert rem43 = (4 - four) rem (3 - four);
assert rem45 = (4 - four) rem (5 - four);
assert rem46 = (4 - four) rem (6 - four);
assert rem47 = (4 - four) rem (7 - four);
assert rem48 = (4 - four) rem (8 - four);
assert rem49 = (4 - four) rem (9 - four);
assert rem61 = (6 - four) rem (1 - four);
assert rem62 = (6 - four) rem (2 - four);
assert rem63 = (6 - four) rem (3 - four);
assert rem65 = (6 - four) rem (5 - four);
assert rem66 = (6 - four) rem (6 - four);
assert rem67 = (6 - four) rem (7 - four);
assert rem68 = (6 - four) rem (8 - four);
assert rem69 = (6 - four) rem (9 - four);
assert NOT((rem11 = (1 - four) rem (1 - four)) and
( rem12 = (1 - four) rem (2 - four)) and
( rem13 = (1 - four) rem (3 - four)) and
( rem15 = (1 - four) rem (5 - four)) and
( rem16 = (1 - four) rem (6 - four)) and
( rem17 = (1 - four) rem (7 - four)) and
( rem18 = (1 - four) rem (8 - four)) and
( rem19 = (1 - four) rem (9 - four)) and
( rem41 = (4 - four) rem (1 - four)) and
( rem42 = (4 - four) rem (2 - four)) and
( rem43 = (4 - four) rem (3 - four)) and
( rem45 = (4 - four) rem (5 - four)) and
( rem46 = (4 - four) rem (6 - four)) and
( rem47 = (4 - four) rem (7 - four)) and
( rem48 = (4 - four) rem (8 - four)) and
( rem49 = (4 - four) rem (9 - four)) and
( rem61 = (6 - four) rem (1 - four)) and
( rem62 = (6 - four) rem (2 - four)) and
( rem63 = (6 - four) rem (3 - four)) and
( rem65 = (6 - four) rem (5 - four)) and
( rem66 = (6 - four) rem (6 - four)) and
( rem67 = (6 - four) rem (7 - four)) and
( rem68 = (6 - four) rem (8 - four)) and
( rem69 = (6 - four) rem (9 - four)) )
report "***PASSED TEST: c07s02b06x00p05n01i02260"
severity NOTE;
assert (( rem11 = (1 - four) rem (1 - four)) and
( rem12 = (1 - four) rem (2 - four)) and
( rem13 = (1 - four) rem (3 - four)) and
( rem15 = (1 - four) rem (5 - four)) and
( rem16 = (1 - four) rem (6 - four)) and
( rem17 = (1 - four) rem (7 - four)) and
( rem18 = (1 - four) rem (8 - four)) and
( rem19 = (1 - four) rem (9 - four)) and
( rem41 = (4 - four) rem (1 - four)) and
( rem42 = (4 - four) rem (2 - four)) and
( rem43 = (4 - four) rem (3 - four)) and
( rem45 = (4 - four) rem (5 - four)) and
( rem46 = (4 - four) rem (6 - four)) and
( rem47 = (4 - four) rem (7 - four)) and
( rem48 = (4 - four) rem (8 - four)) and
( rem49 = (4 - four) rem (9 - four)) and
( rem61 = (6 - four) rem (1 - four)) and
( rem62 = (6 - four) rem (2 - four)) and
( rem63 = (6 - four) rem (3 - four)) and
( rem65 = (6 - four) rem (5 - four)) and
( rem66 = (6 - four) rem (6 - four)) and
( rem67 = (6 - four) rem (7 - four)) and
( rem68 = (6 - four) rem (8 - four)) and
( rem69 = (6 - four) rem (9 - four)) )
report "***FAILED TEST: c07s02b06x00p05n01i02260 - Constant integer type rem test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p05n01i02260arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2260.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p05n01i02260ent IS
END c07s02b06x00p05n01i02260ent;
ARCHITECTURE c07s02b06x00p05n01i02260arch OF c07s02b06x00p05n01i02260ent IS
BEGIN
TESTING: PROCESS
constant rem11 : integer := (1 - 4) rem (1 - 4);
constant rem12 : integer := (1 - 4) rem (2 - 4);
constant rem13 : integer := (1 - 4) rem (3 - 4);
constant rem15 : integer := (1 - 4) rem (5 - 4);
constant rem16 : integer := (1 - 4) rem (6 - 4);
constant rem17 : integer := (1 - 4) rem (7 - 4);
constant rem18 : integer := (1 - 4) rem (8 - 4);
constant rem19 : integer := (1 - 4) rem (9 - 4);
constant rem41 : integer := (4 - 4) rem (1 - 4);
constant rem42 : integer := (4 - 4) rem (2 - 4);
constant rem43 : integer := (4 - 4) rem (3 - 4);
constant rem45 : integer := (4 - 4) rem (5 - 4);
constant rem46 : integer := (4 - 4) rem (6 - 4);
constant rem47 : integer := (4 - 4) rem (7 - 4);
constant rem48 : integer := (4 - 4) rem (8 - 4);
constant rem49 : integer := (4 - 4) rem (9 - 4);
constant rem61 : integer := (6 - 4) rem (1 - 4);
constant rem62 : integer := (6 - 4) rem (2 - 4);
constant rem63 : integer := (6 - 4) rem (3 - 4);
constant rem65 : integer := (6 - 4) rem (5 - 4);
constant rem66 : integer := (6 - 4) rem (6 - 4);
constant rem67 : integer := (6 - 4) rem (7 - 4);
constant rem68 : integer := (6 - 4) rem (8 - 4);
constant rem69 : integer := (6 - 4) rem (9 - 4);
variable four : integer := 4;
BEGIN
assert rem11 = (1 - four) rem (1 - four);
assert rem12 = (1 - four) rem (2 - four);
assert rem13 = (1 - four) rem (3 - four);
assert rem15 = (1 - four) rem (5 - four);
assert rem16 = (1 - four) rem (6 - four);
assert rem17 = (1 - four) rem (7 - four);
assert rem18 = (1 - four) rem (8 - four);
assert rem19 = (1 - four) rem (9 - four);
assert rem41 = (4 - four) rem (1 - four);
assert rem42 = (4 - four) rem (2 - four);
assert rem43 = (4 - four) rem (3 - four);
assert rem45 = (4 - four) rem (5 - four);
assert rem46 = (4 - four) rem (6 - four);
assert rem47 = (4 - four) rem (7 - four);
assert rem48 = (4 - four) rem (8 - four);
assert rem49 = (4 - four) rem (9 - four);
assert rem61 = (6 - four) rem (1 - four);
assert rem62 = (6 - four) rem (2 - four);
assert rem63 = (6 - four) rem (3 - four);
assert rem65 = (6 - four) rem (5 - four);
assert rem66 = (6 - four) rem (6 - four);
assert rem67 = (6 - four) rem (7 - four);
assert rem68 = (6 - four) rem (8 - four);
assert rem69 = (6 - four) rem (9 - four);
assert NOT((rem11 = (1 - four) rem (1 - four)) and
( rem12 = (1 - four) rem (2 - four)) and
( rem13 = (1 - four) rem (3 - four)) and
( rem15 = (1 - four) rem (5 - four)) and
( rem16 = (1 - four) rem (6 - four)) and
( rem17 = (1 - four) rem (7 - four)) and
( rem18 = (1 - four) rem (8 - four)) and
( rem19 = (1 - four) rem (9 - four)) and
( rem41 = (4 - four) rem (1 - four)) and
( rem42 = (4 - four) rem (2 - four)) and
( rem43 = (4 - four) rem (3 - four)) and
( rem45 = (4 - four) rem (5 - four)) and
( rem46 = (4 - four) rem (6 - four)) and
( rem47 = (4 - four) rem (7 - four)) and
( rem48 = (4 - four) rem (8 - four)) and
( rem49 = (4 - four) rem (9 - four)) and
( rem61 = (6 - four) rem (1 - four)) and
( rem62 = (6 - four) rem (2 - four)) and
( rem63 = (6 - four) rem (3 - four)) and
( rem65 = (6 - four) rem (5 - four)) and
( rem66 = (6 - four) rem (6 - four)) and
( rem67 = (6 - four) rem (7 - four)) and
( rem68 = (6 - four) rem (8 - four)) and
( rem69 = (6 - four) rem (9 - four)) )
report "***PASSED TEST: c07s02b06x00p05n01i02260"
severity NOTE;
assert (( rem11 = (1 - four) rem (1 - four)) and
( rem12 = (1 - four) rem (2 - four)) and
( rem13 = (1 - four) rem (3 - four)) and
( rem15 = (1 - four) rem (5 - four)) and
( rem16 = (1 - four) rem (6 - four)) and
( rem17 = (1 - four) rem (7 - four)) and
( rem18 = (1 - four) rem (8 - four)) and
( rem19 = (1 - four) rem (9 - four)) and
( rem41 = (4 - four) rem (1 - four)) and
( rem42 = (4 - four) rem (2 - four)) and
( rem43 = (4 - four) rem (3 - four)) and
( rem45 = (4 - four) rem (5 - four)) and
( rem46 = (4 - four) rem (6 - four)) and
( rem47 = (4 - four) rem (7 - four)) and
( rem48 = (4 - four) rem (8 - four)) and
( rem49 = (4 - four) rem (9 - four)) and
( rem61 = (6 - four) rem (1 - four)) and
( rem62 = (6 - four) rem (2 - four)) and
( rem63 = (6 - four) rem (3 - four)) and
( rem65 = (6 - four) rem (5 - four)) and
( rem66 = (6 - four) rem (6 - four)) and
( rem67 = (6 - four) rem (7 - four)) and
( rem68 = (6 - four) rem (8 - four)) and
( rem69 = (6 - four) rem (9 - four)) )
report "***FAILED TEST: c07s02b06x00p05n01i02260 - Constant integer type rem test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p05n01i02260arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: uart_rx_tb
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Testbench for arith_counter_bcd
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.simulation.all;
use PoC.uart.all;
entity uart_rx_tb is
end entity;
architecture tb of uart_rx_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
constant BAUDRATE : BAUD := 4.2 MBd;
signal Clock : STD_LOGIC;
signal Reset : STD_LOGIC;
signal BitClock : STD_LOGIC;
signal BitClock_x8 : STD_LOGIC;
signal UART_RX : STD_LOGIC;
signal RX_Strobe : STD_LOGIC;
signal RX_Data : T_SLV_8;
function simGenerateWaveform_UART_Word(Data : T_SLV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
constant BIT_TIME : TIME := to_time(to_freq(Baudrate));
variable Result : T_SIM_WAVEFORM_SL(0 to 9) := (others => (Delay => BIT_TIME, Value => '-'));
begin
Result(0).Value := '0';
for i in Data'range loop
Result(i + 1).Value := Data(i);
end loop;
Result(9).Value := '1';
return Result;
end function;
function simGenerateWaveform_UART_Stream(Data : T_SLVV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
variable Result : T_SIM_WAVEFORM_SL(0 to (Data'length * 10) - 1);
begin
for i in Data'range loop
Result(i * 10 to ((i + 1) * 10) - 1) := simGenerateWaveform_UART_Word(Data(i), BAUDRATE);
end loop;
return Result;
end function;
constant DATA_STREAM : T_SLVV_8 := (x"12", x"45", x"FE", x"C4", x"02");
begin
simGenerateClock(Clock, CLOCK_FREQ);
simGenerateWaveform(Reset, simGenerateWaveform_Reset(Pause => 50 ns));
p1f: if true generate
simGenerateWaveform(UART_RX, simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE), '1');
end generate;
p1t: if false generate
process
constant wf : T_SIM_WAVEFORM_SL := simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE);
begin
simGenerateWaveform(UART_RX, wf, '1');
end process;
end generate;
bclk : entity PoC.uart_bclk
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE
)
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
bclk_x8 => BitClock_x8
);
RX : entity PoC.uart_rx
generic map (
OUT_REGS => FALSE
)
port map (
clk => Clock,
rst => Reset,
bclk_x8 => BitClock_x8,
dos => RX_Strobe,
dout => RX_Data,
rxd => UART_RX
);
process
begin
for i in DATA_STREAM'range loop
wait until rising_edge(Clock) and (RX_Strobe = '1');
report TIME'image(NOW) severity NOTE;
tbAssert((RX_Data = DATA_STREAM(i)), "Data Byte " & INTEGER'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h'));
end loop;
wait for 1 us;
simStop;
tbPrintResult;
wait;
end process;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Module: uart_rx_tb
--
-- Authors: Patrick Lehmann
--
-- Description:
-- ------------------------------------
-- Testbench for arith_counter_bcd
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.simulation.all;
use PoC.uart.all;
entity uart_rx_tb is
end entity;
architecture tb of uart_rx_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
constant BAUDRATE : BAUD := 4.2 MBd;
signal Clock : STD_LOGIC;
signal Reset : STD_LOGIC;
signal BitClock : STD_LOGIC;
signal BitClock_x8 : STD_LOGIC;
signal UART_RX : STD_LOGIC;
signal RX_Strobe : STD_LOGIC;
signal RX_Data : T_SLV_8;
function simGenerateWaveform_UART_Word(Data : T_SLV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
constant BIT_TIME : TIME := to_time(to_freq(Baudrate));
variable Result : T_SIM_WAVEFORM_SL(0 to 9) := (others => (Delay => BIT_TIME, Value => '-'));
begin
Result(0).Value := '0';
for i in Data'range loop
Result(i + 1).Value := Data(i);
end loop;
Result(9).Value := '1';
return Result;
end function;
function simGenerateWaveform_UART_Stream(Data : T_SLVV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is
variable Result : T_SIM_WAVEFORM_SL(0 to (Data'length * 10) - 1);
begin
for i in Data'range loop
Result(i * 10 to ((i + 1) * 10) - 1) := simGenerateWaveform_UART_Word(Data(i), BAUDRATE);
end loop;
return Result;
end function;
constant DATA_STREAM : T_SLVV_8 := (x"12", x"45", x"FE", x"C4", x"02");
begin
simGenerateClock(Clock, CLOCK_FREQ);
simGenerateWaveform(Reset, simGenerateWaveform_Reset(Pause => 50 ns));
p1f: if true generate
simGenerateWaveform(UART_RX, simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE), '1');
end generate;
p1t: if false generate
process
constant wf : T_SIM_WAVEFORM_SL := simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE);
begin
simGenerateWaveform(UART_RX, wf, '1');
end process;
end generate;
bclk : entity PoC.uart_bclk
generic map (
CLOCK_FREQ => CLOCK_FREQ,
BAUDRATE => BAUDRATE
)
port map (
clk => Clock,
rst => Reset,
bclk => BitClock,
bclk_x8 => BitClock_x8
);
RX : entity PoC.uart_rx
generic map (
OUT_REGS => FALSE
)
port map (
clk => Clock,
rst => Reset,
bclk_x8 => BitClock_x8,
dos => RX_Strobe,
dout => RX_Data,
rxd => UART_RX
);
process
begin
for i in DATA_STREAM'range loop
wait until rising_edge(Clock) and (RX_Strobe = '1');
report TIME'image(NOW) severity NOTE;
tbAssert((RX_Data = DATA_STREAM(i)), "Data Byte " & INTEGER'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h'));
end loop;
wait for 1 us;
simStop;
tbPrintResult;
wait;
end process;
end architecture;
|
--Top-Level Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--使用自定义程序包
USE WORK.MYTYPE.ALL;
ENTITY IMG_LSB IS
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
SEL: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
A_COL: IN COLOR;
A_ROW: IN COLOR;
B_COL: IN COLOR;
B_ROW: IN COLOR;
C_COL: IN COLOR;
C_ROW: IN COLOR;
R_OUT: OUT COLOR;
G_OUT: OUT COLOR;
B_OUT: OUT COLOR;
DETECT_RESULT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
XX: IN COLOR;
YY: IN COLOR;
ZZ: IN INTEGER RANGE 0 TO 2;
STR: IN STRING(1 TO 20);
HR_OUT: OUT COLOR;
HG_OUT: OUT COLOR;
HB_OUT: OUT COLOR;
STR_LEN: IN INTEGER RANGE 0 TO 8192;
CHAR_OUT: OUT CHARACTER);
END ENTITY IMG_LSB;
ARCHITECTURE ART OF IMG_LSB IS
COMPONENT CHOOSE
PORT(RESET: IN STD_LOGIC;
CLK: IN STD_LOGIC;
SEL: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
TO_TRANS: OUT STD_LOGIC;
TO_INSERT: OUT STD_LOGIC;
TO_DETECT: OUT STD_LOGIC;
TO_HIDE: OUT STD_LOGIC;
TO_UNHIDE: OUT STD_LOGIC);
END COMPONENT;
COMPONENT RGB2YUV
PORT(RESET: IN STD_LOGIC;
CLK: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
Y_OUT: OUT COLOR;
U_OUT: OUT COLOR;
V_OUT: OUT COLOR);
END COMPONENT;
COMPONENT LSB_INSERT
PORT(ENABLE: IN STD_LOGIC;
CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
Y_IN: IN COLOR;
U_IN: IN COLOR;
V_IN: IN COLOR;
A_COL: IN COLOR;
A_ROW: IN COLOR;
B_COL: IN COLOR;
B_ROW: IN COLOR;
C_COL: IN COLOR;
C_ROW: IN COLOR;
FIXED_Y_OUT: OUT COLOR;
U_OUT: OUT COLOR;
V_OUT: OUT COLOR);
END COMPONENT;
COMPONENT YUV2RGB
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
FIXED_Y_IN: IN COLOR;
U_IN: IN COLOR;
V_IN: IN COLOR;
R_OUT: OUT COLOR;
G_OUT: OUT COLOR;
B_OUT: OUT COLOR);
END COMPONENT;
COMPONENT LSB_DETECT
PORT(ENABLE: IN STD_LOGIC;
CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
Y_IN: IN COLOR;
RESULT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
COMPONENT HIDE_STR
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
XX: IN COLOR;
YY: IN COLOR;
ZZ: IN INTEGER RANGE 0 TO 2;
STR: IN STRING;
HR_OUT: OUT COLOR;
HG_OUT: OUT COLOR;
HB_OUT: OUT COLOR);
END COMPONENT;
COMPONENT UNHIDE_STR
PORT(CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
ENABLE: IN STD_LOGIC;
R_IN: IN COLOR;
G_IN: IN COLOR;
B_IN: IN COLOR;
XX: IN COLOR;
YY: IN COLOR;
ZZ: IN INTEGER RANGE 0 TO 2;
STR_LEN: IN INTEGER RANGE 0 TO 8192;
CHAR_OUT: OUT CHARACTER);
END COMPONENT;
SIGNAL TOIN_MID1: STD_LOGIC;
SIGNAL TODE_MID1: STD_LOGIC;
SIGNAL TOTR_MID1: STD_LOGIC;
SIGNAL TOHI_MID1: STD_LOGIC;
SIGNAL TOUN_MID1: STD_LOGIC;
SIGNAL Y_MID2: COLOR;
SIGNAL U_MID2: COLOR;
SIGNAL V_MID2: COLOR;
SIGNAL FIX_Y_MID3: COLOR;
SIGNAL U_MID3: COLOR;
SIGNAL V_MID3: COLOR;
BEGIN
INST_CHOOSE: CHOOSE PORT MAP(
CLK=>CLK,
RESET=>RESET,
SEL=>SEL,
TO_INSERT=>TOIN_MID1,
TO_DETECT=>TODE_MID1,
TO_TRANS=>TOTR_MID1,
TO_HIDE=>TOHI_MID1,
TO_UNHIDE=>TOUN_MID1
);
INST_RGB2YUV: RGB2YUV PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TOTR_MID1,
R_IN=>R_IN,
B_IN=>B_IN,
G_IN=>G_IN,
Y_OUT=>Y_MID2,
U_OUT=>U_MID2,
V_OUT=>V_MID2
);
INST_LSB_INSERT: LSB_INSERT PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TOIN_MID1,
Y_IN=>Y_MID2,
U_IN=>U_MID2,
V_IN=>V_MID2,
A_COL=>A_COL,
A_ROW=>A_ROW,
B_COL=>B_COL,
B_ROW=>B_ROW,
C_COL=>C_COL,
C_ROW=>C_ROW,
FIXED_Y_OUT=>FIX_Y_MID3,
U_OUT=>U_MID3,
V_OUT=>V_MID3
);
INST_YUV2RGB: YUV2RGB PORT MAP(
CLK=>CLK,
RESET=>RESET,
FIXED_Y_IN=>FIX_Y_MID3,
U_IN=>U_MID3,
V_IN=>V_MID3,
R_OUT=>R_OUT,
G_OUT=>G_OUT,
B_OUT=>B_OUT
);
INST_LSB_DETECT: LSB_DETECT PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TODE_MID1,
Y_IN=>Y_MID2,
RESULT=>DETECT_RESULT
);
INST_HIDE_STR: HIDE_STR PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TOHI_MID1,
R_IN=>R_IN,
G_IN=>G_IN,
B_IN=>B_IN,
XX=>XX,
YY=>YY,
ZZ=>ZZ,
STR=>STR,
HR_OUT=>HR_OUT,
HG_OUT=>HG_OUT,
HB_OUT=>HB_OUT
);
INST_UNHIDE_STR: UNHIDE_STR PORT MAP(
CLK=>CLK,
RESET=>RESET,
ENABLE=>TOUN_MID1,
R_IN=>R_IN,
G_IN=>G_IN,
B_IN=>B_IN,
XX=>XX,
YY=>YY,
ZZ=>ZZ,
STR_LEN=>STR_LEN,
CHAR_OUT=>CHAR_OUT
);
END ARCHITECTURE ART;
|
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hread(l, rectype);
hread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(l, recaddr(15 downto 0));
when "0010" =>
hread(l, recaddr(23 downto 0));
when "0011" =>
hread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(l, recdata);
if index < 32 then
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
END IF;
elsif(index < 1024) then
Bank_Load := recaddr(26 downto 25);
Rows_Load := recaddr(24 downto 12);
Cols_Load := recaddr(11 downto 3);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 1 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 1 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 1 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 1 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
END IF;
else
Bank_Load := recaddr(22 downto 21);
Rows_Load := '0' & recaddr(20 downto 9);
Cols_Load := '0' & recaddr(8 downto 1);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 7 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 7 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 7 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 7 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
|
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hread(l, rectype);
hread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(l, recaddr(15 downto 0));
when "0010" =>
hread(l, recaddr(23 downto 0));
when "0011" =>
hread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(l, recdata);
if index < 32 then
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
END IF;
elsif(index < 1024) then
Bank_Load := recaddr(26 downto 25);
Rows_Load := recaddr(24 downto 12);
Cols_Load := recaddr(11 downto 3);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 1 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 1 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 1 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 1 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
END IF;
else
Bank_Load := recaddr(22 downto 21);
Rows_Load := '0' & recaddr(20 downto 9);
Cols_Load := '0' & recaddr(8 downto 1);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 7 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 7 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 7 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 7 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
|
-- Author: Varun Nagpal
-- Net Id: vxn180010
-- VLSI Design Homework 1
-- 3rd Sept, 2018
--
-- Package: Modifiable Paramaters, non-modifiable constants and types (ports)
-- for the Generic Nth order (L = N+1 taps) Transposed Direct-form FIR-filter
--
-- Modifiable variables for Design of the FIR Filter:
-- FIR_ORDER = order of the filter (N). Note L = N+1 = taps
-- X_BIT_SIZE = bit width (n) of input samples (signed 2's complement)
-- H_BIT_SIZE = bit width (m) of coefficients (signed 2's complement)
--
-- Modifiable variables for testbench of the FIR Filter:
-- CLK_CYCLE_TIME = clock cycle time
-- CLK_HIGH_TIME = time for which clock is high
--
-- All remaining parameters in the package are non-modifiable constants which
-- must not be modified manually as there values are calculated during using values
-- of modifiable variables during compilation of VHDL files
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use ieee.std_logic_unsigned.all;
package fir_filter_shared_package is
-- modifiable variables for design of FIR filter
constant FIR_ORDER : natural := 3; -- order of the filter (N). Note L = N+1 = taps
constant X_BIT_SIZE : natural := 16; -- bit width (n) of input samples (signed 2's complement)
constant H_BIT_SIZE : natural := 16; -- bit width (m) of coefficients (signed 2's complement)
-- modifiable variables for testbench of FIR filter
constant CLK_CYCLE_TIME : time := 100 ns;
constant CLK_HIGH_TIME : time := 50 ns;
-- modifiable constants for testbench of FIR filter
constant CLK_LOW_TIME : time := CLK_CYCLE_TIME - CLK_HIGH_TIME;
-- non-modifiable constants
constant MULT_BIT_SIZE : natural := X_BIT_SIZE+H_BIT_SIZE; -- bit width (n+m) of signed multiplier
constant EXTR_BIT_SIZE : natural := natural(ceil(log2(real(FIR_ORDER+1))))-1; -- extra bits for accumulation = ceil(log2(L))-1
constant Y_BIT_SIZE : natural := MULT_BIT_SIZE+EXTR_BIT_SIZE; -- bit width of output samples (signed 2's complement) or signed adder
-- N = no. of register delays or additions
subtype ADD_REG_TYPE is signed(Y_BIT_SIZE-1 downto 0);
type ADD_REG_ARRAY is array (0 to FIR_ORDER) of ADD_REG_TYPE;
-- L = N+1 no. of taps or coefficients or multiplications
subtype MULT_SIG_TYPE is signed(MULT_BIT_SIZE-1 downto 0);
type MULT_SIG_ARRAY is array (0 to FIR_ORDER) of MULT_SIG_TYPE;
subtype COEFF_REG_TYPE is signed(H_BIT_SIZE-1 downto 0);
type COEFF_REG_ARRAY is array (0 to FIR_ORDER) of COEFF_REG_TYPE;
end fir_filter_shared_package;
package body fir_filter_shared_package is
-- empty
end fir_filter_shared_package; |
package fsm_pkg is
type fsm_state is
(
START,
S0,
S1,
S2,
S3
);
end package fsm_pkg;
|
package fsm_pkg is
type fsm_state is
(
START,
S0,
S1,
S2,
S3
);
end package fsm_pkg;
|
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clocks is
port (
clock_i : in std_logic; -- 21 MHz
por_i : in std_logic;
turbo_on_i : in std_logic; -- 0 = 3.57, 1 = 7.15
clock_vdp_o : out std_logic;
clock_5m_en_o : out std_logic;
clock_cpu_o : out std_logic;
clock_psg_en_o : out std_logic; -- 3.57 clock enable
clock_3m_o : out std_logic
);
end entity;
architecture rtl of clocks is
-- Clocks
signal clk1_cnt_q : unsigned(2 downto 0) := (others => '0');
signal clk2_cnt_q : unsigned(2 downto 0) := (others => '0');
signal pos_cnt3_q : unsigned(1 downto 0) := "00";
signal neg_cnt3_q : unsigned(1 downto 0) := "00";
signal div3_s : std_logic := '0';
signal clock_vdp_s : std_logic := '0';
signal clock_5m_en_s : std_logic := '0';
signal clock_3m_s : std_logic := '0';
signal clock_7m_s : std_logic := '0';
signal clock_psg_en_s : std_logic := '0';
-- Switcher
signal sw_ff_q : std_logic_vector(1 downto 0) := "11";
signal clock_out1_s : std_logic;
signal clock_out2_s : std_logic;
begin
-- clk1_cnt_q: 5 4 3 2 1 0
-- 0 and 3 = 3.57
-- 0, 2, 4 = 10.7
-- Clocks generation
process (por_i, clock_i)
begin
if por_i = '1' then
clk2_cnt_q <= (others => '0');
clock_5m_en_s <= '0';
elsif rising_edge(clock_i) then
clock_5m_en_s <= '0';
if clk2_cnt_q = 0 then
clk2_cnt_q <= "111";
else
clk2_cnt_q <= clk2_cnt_q - 1;
end if;
if clk2_cnt_q = 0 or clk2_cnt_q = 4 then
clock_5m_en_s <= '1'; -- Scandoubler: 5.37 MHz enable
end if;
end if;
end process;
process (por_i, clock_i)
begin
if por_i = '1' then
clk1_cnt_q <= (others => '0');
clock_vdp_s <= '0';
clock_3m_s <= '0';
pos_cnt3_q <= "00";
elsif rising_edge(clock_i) then
clock_psg_en_s <= '0'; -- PSG clock enable
if clk1_cnt_q = 0 then
clk1_cnt_q <= "101";
clock_psg_en_s <= '1'; -- PSG clock enable
else
clk1_cnt_q <= clk1_cnt_q - 1;
end if;
clock_vdp_s <= not clock_vdp_s; -- VDP: 10.7 MHz
if clk1_cnt_q = 0 or clk1_cnt_q = 3 then
clock_3m_s <= not clock_3m_s; -- 3.57 MHz
end if;
-- /3
if pos_cnt3_q = 2 then
pos_cnt3_q <= "00";
else
pos_cnt3_q <= pos_cnt3_q + 1;
end if;
end if;
end process;
-- /3
process (por_i, clock_i)
begin
if por_i = '1' then
neg_cnt3_q <= "00";
elsif falling_edge(clock_i) then
if neg_cnt3_q = 2 then
neg_cnt3_q <= "00";
else
neg_cnt3_q <= neg_cnt3_q + 1;
end if;
end if;
end process;
clock_7m_s <= '1' when pos_cnt3_q /= 2 and neg_cnt3_q /= 2 else '0';
-- Switcher
process(por_i, clock_out1_s)
begin
if por_i = '1' then
sw_ff_q <= "00";
elsif rising_edge(clock_out1_s) then
sw_ff_q(1) <= turbo_on_i;
sw_ff_q(0) <= sw_ff_q(1);
end if;
end process;
clock_out1_s <= clock_3m_s when sw_ff_q(1) = '0' else clock_7m_s;
-- Out
clock_vdp_o <= clock_vdp_s;
clock_5m_en_o <= clock_5m_en_s;
clock_psg_en_o <= clock_psg_en_s;
clock_3m_o <= clock_3m_s;
with sw_ff_q select
clock_cpu_o <=
clock_3m_s when "00",
clock_7m_s when "11",
'1' when others;
end architecture; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(19 downto 0);
signal data : std_logic_vector(31 downto 0);
signal mben : std_logic_vector(3 downto 0);
signal pio : std_logic_vector(17 downto 0);
signal ramsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal errorn : std_logic;
signal ps2clk : std_logic;
signal ps2data : std_logic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic;
signal vid_g : std_logic;
signal vid_b : std_logic;
signal switch : std_logic_vector(7 downto 0); -- switches
signal button : std_logic_vector(2 downto 0);
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst; dsuen <= '1'; dsubre <= '0';
rxd1 <= 'H';
ps2clk <= 'H'; ps2data <= 'H';
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
address(1 downto 0) <= "00";
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (rst, clk, errorn, address(19 downto 2), data,
ramsn, mben, oen, writen,
dsubre, dsuact, txd1, rxd1, pio, --switch, button,
ps2clk, ps2data,
vid_hsync, vid_vsync, vid_r, vid_g, vid_b
);
sram0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sdramfile)
port map (address(19 downto 2), data(31-i*16 downto 16-i*16),
mben(i*2), mben(i*2+1), ramsn(i), writen, oen);
end generate;
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '0' then wait on errorn; end if;
assert (to_x01(errorn) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait for 2500 ns;
dsurst <= '0';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
end ;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_9;
USE mult_gen_v12_0_9.mult_gen_v12_0_9;
ENTITY mult_gen_0 IS
PORT (
A : IN STD_LOGIC_VECTOR(32 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(53 DOWNTO 0)
);
END mult_gen_0;
ARCHITECTURE mult_gen_0_arch OF mult_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_9 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(32 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(53 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_9;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_9
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "artix7",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 0,
C_A_WIDTH => 33,
C_A_TYPE => 0,
C_B_WIDTH => 14,
C_B_TYPE => 0,
C_OUT_HIGH => 53,
C_OUT_LOW => 0,
C_MULT_TYPE => 1,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => '1',
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mult_gen_0_arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Entity: arith_addw
--
-- Description:
-- ------------------------------------
-- Implements wide addition providing several options all based
-- on an adaptation of a carry-select approach.
--
-- References:
-- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser:
-- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders,
-- FPL 2011.
-- -> ARCH: AAM, CAI, CCA
-- -> SKIPPING: CCC
--
-- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol:
-- A Novel Modular Adder for One Thousand Bits and More
-- Using Fast Carry Chains of Modern FPGAs, FPL 2014.
-- -> ARCH: PAI
-- -> SKIPPING: PPN_KS, PPN_BK
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
use PoC.arith.all;
entity arith_addw is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := AAM; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC; -- Carry Skip Scheme
P_INCLUSIVE : boolean := false -- Use Inclusive Propagate, i.e. c^1
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end entity;
use std.textio.all;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of arith_addw is
-- Determine Block Boundaries
type tBlocking_vector is array(tArch) of tBlocking;
constant DEFAULT_BLOCKING : tBlocking_vector := (AAM => ASC, CAI => DESC, PAI => DESC, CCA => DESC);
type integer_vector is array(natural range<>) of integer;
impure function compute_blocks return integer_vector is
variable bs : tBlocking := BLOCKING;
variable res : integer_vector(K-1 downto 0);
variable l : line;
begin
if bs = DFLT then
bs := DEFAULT_BLOCKING(ARCH);
end if;
case bs is
when FIX =>
assert N >= K
report "Cannot have more blocks than input bits."
severity failure;
for i in res'range loop
res(i) := ((i+1)*N+K/2)/K;
end loop;
when ASC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N-K*(K-1)/2)+K/2)/K + (i+1)*i/2;
end loop;
when DESC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N+K*(K-1)/2)+K/2)/K - (i+1)*i/2;
end loop;
when others =>
report "Unknown blocking scheme: "&tBlocking'image(bs) severity failure;
end case;
--synthesis translate_off
write(l, "Implementing "&integer'image(N)&"-bit wide adder: ARCH="&tArch'image(ARCH)&
", BLOCKING="&tBlocking'image(bs)&'[');
for i in K-1 downto 1 loop
write(l, res(i)-res(i-1));
write(l, ',');
end loop;
write(l, res(0));
write(l, "], SKIPPING="&tSkipping'image(SKIPPING));
writeline(output, l);
--synthesis translate_on
return res;
end compute_blocks;
constant BLOCKS : integer_vector(K-1 downto 0) := compute_blocks;
signal g : std_logic_vector(K-1 downto 1); -- Block Generate
signal p : std_logic_vector(K-1 downto 1); -- Block Propagate
signal c : std_logic_vector(K-1 downto 1); -- Block Carry-in
begin
-----------------------------------------------------------------------------
-- Rightmost Block + Carry Computation Core
blkCore: block
constant M : positive := BLOCKS(0); -- Rightmost Block Width
begin
-- Carry Computation with Carry Chain
genCCC: if SKIPPING = CCC generate
signal x, y : unsigned(K+M-2 downto 0);
signal z : unsigned(K+M-1 downto 0);
begin
x <= unsigned(g & a(M-1 downto 0));
genExcl: if not P_INCLUSIVE generate
y <= unsigned((g or p) & b(M-1 downto 0));
-- carry recovery for other blocks
c <= std_logic_vector(z(K+M-2 downto M)) xor p;
end generate genExcl;
genIncl: if P_INCLUSIVE generate
y <= unsigned(p & b(M-1 downto 0));
-- carry recovery for other blocks
c <= std_logic_vector(z(K+M-2 downto M)) xor (p xor g);
end generate genIncl;
z <= ('0' & x) + y + (0 to 0 => cin);
-- output of rightmost block
s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
-- carry output
cout <= z(z'left);
end generate genCCC;
-- LUT-based Carry Computations
genLUT: if SKIPPING /= CCC generate
signal z : unsigned(M downto 0);
begin
-- rightmost block
z <= unsigned('0' & a(M-1 downto 0)) + unsigned(b(M-1 downto 0)) + (0 to 0 => cin);
s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
-- Plain linear LUT-based Carry Forwarding
genPlain: if SKIPPING = PLAIN generate
signal t : std_logic_vector(K downto 1);
begin
-- carry forwarding
t(1) <= z(M);
t(K downto 2) <= g or (p and c);
c <= t(K-1 downto 1);
cout <= t(K);
end generate genPlain;
-- Kogge-Stone Parallel Prefix Network
genPPN_KS: if SKIPPING = PPN_KS generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to LEVELS);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & z(M);
genLevels: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
pp(i) <= (pp(i-1)(K-1 downto D) and pp(i-1)(K-D-1 downto 0)) & pp(i-1)(D-1 downto 0);
gg(i) <= (gg(i-1)(K-1 downto D) or (pp(i-1)(K-1 downto D) and gg(i-1)(K-D-1 downto 0))) & gg(i-1)(D-1 downto 0);
end generate genLevels;
c <= gg(LEVELS)(K-2 downto 0);
cout <= gg(LEVELS)(K-1);
end generate genPPN_KS;
-- Brent-Kung Parallel Prefix Network
genPPN_BK: if SKIPPING = PPN_BK generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to 2*LEVELS-1);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & z(M);
genMerge: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j mod (2*D) = 2*D-1 generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j mod (2*D) /= 2*D-1 generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genMerge;
genSpread: for i in LEVELS+1 to 2*LEVELS-1 generate
constant D : positive := 2**(2*LEVELS-i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j > D and (j+1) mod (2*D) = D generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j <= D or (j+1) mod (2*D) /= D generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genSpread;
c <= gg(gg'high)(K-2 downto 0);
cout <= gg(gg'high)(K-1);
end generate genPPN_BK;
end generate genLUT;
end block blkCore;
-----------------------------------------------------------------------------
-- Implement Carry-Select Variant
--
-- all but rightmost block, implementation architecture selected by ARCH
genBlocks: for i in 1 to K-1 generate
-- Covered Index Range
constant LO : positive := BLOCKS(i-1); -- Low Bit Index
constant HI : positive := BLOCKS(i)-1; -- High Bit Index
-- Internal Block Interface
signal aa : unsigned(HI downto LO);
signal bb : unsigned(HI downto LO);
signal ss : unsigned(HI downto LO);
begin
-- Connect common block interface
aa <= unsigned(a(HI downto LO));
bb <= unsigned(b(HI downto LO));
s(HI downto LO) <= std_logic_vector(ss);
-- ARCH-specific Implementations
--Add-Add-Multiplex
genAAM: if ARCH = AAM generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
signal s1 : unsigned(HI+1 downto LO); -- Block Sum (cin=1)
begin
s0 <= ('0' & aa) + bb;
s1 <= ('0' & aa) + bb + 1;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= s1(HI+1) xor s0(HI+1);
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= s1(HI+1);
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s1(HI downto LO);
end generate genAAM;
-- Compare-Add-Increment
genCAI: if ARCH = CAI generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
begin
s0 <= ('0' & aa) + bb;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when (aa xor bb) = (aa'range => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa >= not bb else '0';
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
end generate genCAI;
-- Propagate-Add-Increment
genPAI: if ARCH = PAI generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
begin
s0 <= ('0' & aa) + bb;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
'1' when s0(HI downto LO) = (HI downto LO => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
'1' when s0(HI downto LO) = (HI downto LO => '1') else g(i);
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
end generate genPAI;
-- Compare-Compare-Add
genCCA: if ARCH = CCA generate
g(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa > not bb else '0';
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when (aa xor bb) = (aa'range => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa >= not bb else '0';
end generate genIncl;
ss <= aa + bb + (0 to 0 => c(i));
end generate genCCA;
end generate genBlocks;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
--
-- Entity: arith_addw
--
-- Description:
-- ------------------------------------
-- Implements wide addition providing several options all based
-- on an adaptation of a carry-select approach.
--
-- References:
-- * Hong Diep Nguyen and Bogdan Pasca and Thomas B. Preusser:
-- FPGA-Specific Arithmetic Optimizations of Short-Latency Adders,
-- FPL 2011.
-- -> ARCH: AAM, CAI, CCA
-- -> SKIPPING: CCC
--
-- * Marcin Rogawski, Kris Gaj and Ekawat Homsirikamol:
-- A Novel Modular Adder for One Thousand Bits and More
-- Using Fast Carry Chains of Modern FPGAs, FPL 2014.
-- -> ARCH: PAI
-- -> SKIPPING: PPN_KS, PPN_BK
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.utils.all;
use PoC.arith.all;
entity arith_addw is
generic (
N : positive; -- Operand Width
K : positive; -- Block Count
ARCH : tArch := AAM; -- Architecture
BLOCKING : tBlocking := DFLT; -- Blocking Scheme
SKIPPING : tSkipping := CCC; -- Carry Skip Scheme
P_INCLUSIVE : boolean := false -- Use Inclusive Propagate, i.e. c^1
);
port (
a, b : in std_logic_vector(N-1 downto 0);
cin : in std_logic;
s : out std_logic_vector(N-1 downto 0);
cout : out std_logic
);
end entity;
use std.textio.all;
library IEEE;
use IEEE.numeric_std.all;
architecture rtl of arith_addw is
-- Determine Block Boundaries
type tBlocking_vector is array(tArch) of tBlocking;
constant DEFAULT_BLOCKING : tBlocking_vector := (AAM => ASC, CAI => DESC, PAI => DESC, CCA => DESC);
type integer_vector is array(natural range<>) of integer;
impure function compute_blocks return integer_vector is
variable bs : tBlocking := BLOCKING;
variable res : integer_vector(K-1 downto 0);
variable l : line;
begin
if bs = DFLT then
bs := DEFAULT_BLOCKING(ARCH);
end if;
case bs is
when FIX =>
assert N >= K
report "Cannot have more blocks than input bits."
severity failure;
for i in res'range loop
res(i) := ((i+1)*N+K/2)/K;
end loop;
when ASC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N-K*(K-1)/2)+K/2)/K + (i+1)*i/2;
end loop;
when DESC =>
assert N-K*(K-1)/2 >= K
report "Too few input bits to implement growing block sizes."
severity failure;
for i in res'range loop
res(i) := ((i+1)*(N+K*(K-1)/2)+K/2)/K - (i+1)*i/2;
end loop;
when others =>
report "Unknown blocking scheme: "&tBlocking'image(bs) severity failure;
end case;
--synthesis translate_off
write(l, "Implementing "&integer'image(N)&"-bit wide adder: ARCH="&tArch'image(ARCH)&
", BLOCKING="&tBlocking'image(bs)&'[');
for i in K-1 downto 1 loop
write(l, res(i)-res(i-1));
write(l, ',');
end loop;
write(l, res(0));
write(l, "], SKIPPING="&tSkipping'image(SKIPPING));
writeline(output, l);
--synthesis translate_on
return res;
end compute_blocks;
constant BLOCKS : integer_vector(K-1 downto 0) := compute_blocks;
signal g : std_logic_vector(K-1 downto 1); -- Block Generate
signal p : std_logic_vector(K-1 downto 1); -- Block Propagate
signal c : std_logic_vector(K-1 downto 1); -- Block Carry-in
begin
-----------------------------------------------------------------------------
-- Rightmost Block + Carry Computation Core
blkCore: block
constant M : positive := BLOCKS(0); -- Rightmost Block Width
begin
-- Carry Computation with Carry Chain
genCCC: if SKIPPING = CCC generate
signal x, y : unsigned(K+M-2 downto 0);
signal z : unsigned(K+M-1 downto 0);
begin
x <= unsigned(g & a(M-1 downto 0));
genExcl: if not P_INCLUSIVE generate
y <= unsigned((g or p) & b(M-1 downto 0));
-- carry recovery for other blocks
c <= std_logic_vector(z(K+M-2 downto M)) xor p;
end generate genExcl;
genIncl: if P_INCLUSIVE generate
y <= unsigned(p & b(M-1 downto 0));
-- carry recovery for other blocks
c <= std_logic_vector(z(K+M-2 downto M)) xor (p xor g);
end generate genIncl;
z <= ('0' & x) + y + (0 to 0 => cin);
-- output of rightmost block
s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
-- carry output
cout <= z(z'left);
end generate genCCC;
-- LUT-based Carry Computations
genLUT: if SKIPPING /= CCC generate
signal z : unsigned(M downto 0);
begin
-- rightmost block
z <= unsigned('0' & a(M-1 downto 0)) + unsigned(b(M-1 downto 0)) + (0 to 0 => cin);
s(M-1 downto 0) <= std_logic_vector(z(M-1 downto 0));
-- Plain linear LUT-based Carry Forwarding
genPlain: if SKIPPING = PLAIN generate
signal t : std_logic_vector(K downto 1);
begin
-- carry forwarding
t(1) <= z(M);
t(K downto 2) <= g or (p and c);
c <= t(K-1 downto 1);
cout <= t(K);
end generate genPlain;
-- Kogge-Stone Parallel Prefix Network
genPPN_KS: if SKIPPING = PPN_KS generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to LEVELS);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & z(M);
genLevels: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
pp(i) <= (pp(i-1)(K-1 downto D) and pp(i-1)(K-D-1 downto 0)) & pp(i-1)(D-1 downto 0);
gg(i) <= (gg(i-1)(K-1 downto D) or (pp(i-1)(K-1 downto D) and gg(i-1)(K-D-1 downto 0))) & gg(i-1)(D-1 downto 0);
end generate genLevels;
c <= gg(LEVELS)(K-2 downto 0);
cout <= gg(LEVELS)(K-1);
end generate genPPN_KS;
-- Brent-Kung Parallel Prefix Network
genPPN_BK: if SKIPPING = PPN_BK generate
subtype tLevel is std_logic_vector(K-1 downto 0);
type tLevels is array(natural range<>) of tLevel;
constant LEVELS : positive := log2ceil(K);
signal pp, gg : tLevels(0 to 2*LEVELS-1);
begin
-- carry forwarding
pp(0) <= p & 'X';
gg(0) <= g & z(M);
genMerge: for i in 1 to LEVELS generate
constant D : positive := 2**(i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j mod (2*D) = 2*D-1 generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j mod (2*D) /= 2*D-1 generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genMerge;
genSpread: for i in LEVELS+1 to 2*LEVELS-1 generate
constant D : positive := 2**(2*LEVELS-i-1);
begin
genBits: for j in 0 to K-1 generate
genOp: if j > D and (j+1) mod (2*D) = D generate
gg(i)(j) <= (pp(i-1)(j) and gg(i-1)(j-D)) or gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j) and pp(i-1)(j-D);
end generate;
genCp: if j <= D or (j+1) mod (2*D) /= D generate
gg(i)(j) <= gg(i-1)(j);
pp(i)(j) <= pp(i-1)(j);
end generate;
end generate;
end generate genSpread;
c <= gg(gg'high)(K-2 downto 0);
cout <= gg(gg'high)(K-1);
end generate genPPN_BK;
end generate genLUT;
end block blkCore;
-----------------------------------------------------------------------------
-- Implement Carry-Select Variant
--
-- all but rightmost block, implementation architecture selected by ARCH
genBlocks: for i in 1 to K-1 generate
-- Covered Index Range
constant LO : positive := BLOCKS(i-1); -- Low Bit Index
constant HI : positive := BLOCKS(i)-1; -- High Bit Index
-- Internal Block Interface
signal aa : unsigned(HI downto LO);
signal bb : unsigned(HI downto LO);
signal ss : unsigned(HI downto LO);
begin
-- Connect common block interface
aa <= unsigned(a(HI downto LO));
bb <= unsigned(b(HI downto LO));
s(HI downto LO) <= std_logic_vector(ss);
-- ARCH-specific Implementations
--Add-Add-Multiplex
genAAM: if ARCH = AAM generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
signal s1 : unsigned(HI+1 downto LO); -- Block Sum (cin=1)
begin
s0 <= ('0' & aa) + bb;
s1 <= ('0' & aa) + bb + 1;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= s1(HI+1) xor s0(HI+1);
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= s1(HI+1);
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s1(HI downto LO);
end generate genAAM;
-- Compare-Add-Increment
genCAI: if ARCH = CAI generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
begin
s0 <= ('0' & aa) + bb;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when (aa xor bb) = (aa'range => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa >= not bb else '0';
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
end generate genCAI;
-- Propagate-Add-Increment
genPAI: if ARCH = PAI generate
signal s0 : unsigned(HI+1 downto LO); -- Block Sum (cin=0)
begin
s0 <= ('0' & aa) + bb;
g(i) <= s0(HI+1);
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
'1' when s0(HI downto LO) = (HI downto LO => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(s0)) else
'1' when s0(HI downto LO) = (HI downto LO => '1') else g(i);
end generate genIncl;
ss <= s0(HI downto LO) when c(i) = '0' else s0(HI downto LO)+1;
end generate genPAI;
-- Compare-Compare-Add
genCCA: if ARCH = CCA generate
g(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa > not bb else '0';
genExcl: if not P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when (aa xor bb) = (aa'range => '1') else '0';
end generate genExcl;
genIncl: if P_INCLUSIVE generate
p(i) <= 'X' when Is_X(std_logic_vector(aa&bb)) else
'1' when aa >= not bb else '0';
end generate genIncl;
ss <= aa + bb + (0 to 0 => c(i));
end generate genCCA;
end generate genBlocks;
end architecture;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net7
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net9
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1984.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01984ent IS
END c07s02b02x00p02n01i01984ent;
ARCHITECTURE c07s02b02x00p02n01i01984arch OF c07s02b02x00p02n01i01984ent IS
BEGIN
TESTING: PROCESS
variable B1 : boolean := true;
variable B2 : boolean := false;
variable A1 : bit := '1';
variable A2 : bit := '0';
BEGIN
assert NOT( A1 = '1' and
'1' = A1 and
B2 = false and
false = B2 and
A1 /= A2 and
B1 /= B2 and
A2 < A1 and
B2 < B1 and
A1 > A2 and
B1 > B2 and
A2 <= A1 and
B2 <= B1 and
A1 >= A2 and
B1 >= B2 and
A1 <= A1 and
B1 <= B1 and
B2 <= B2 and
A2 <= A2 )
report "***PASSED TEST: c07s02b02x00p02n01i01984"
severity NOTE;
assert ( A1 = '1' and
'1' = A1 and
B2 = false and
false = B2 and
A1 /= A2 and
B1 /= B2 and
A2 < A1 and
B2 < B1 and
A1 > A2 and
B1 > B2 and
A2 <= A1 and
B2 <= B1 and
A1 >= A2 and
B1 >= B2 and
A1 <= A1 and
B1 <= B1 and
B2 <= B2 and
A2 <= A2 )
report "***FAILED TEST: c07s02b02x00p02n01i01984 - Relational operators true table test for data type of BIT and BOOLEAN failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01984arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1984.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01984ent IS
END c07s02b02x00p02n01i01984ent;
ARCHITECTURE c07s02b02x00p02n01i01984arch OF c07s02b02x00p02n01i01984ent IS
BEGIN
TESTING: PROCESS
variable B1 : boolean := true;
variable B2 : boolean := false;
variable A1 : bit := '1';
variable A2 : bit := '0';
BEGIN
assert NOT( A1 = '1' and
'1' = A1 and
B2 = false and
false = B2 and
A1 /= A2 and
B1 /= B2 and
A2 < A1 and
B2 < B1 and
A1 > A2 and
B1 > B2 and
A2 <= A1 and
B2 <= B1 and
A1 >= A2 and
B1 >= B2 and
A1 <= A1 and
B1 <= B1 and
B2 <= B2 and
A2 <= A2 )
report "***PASSED TEST: c07s02b02x00p02n01i01984"
severity NOTE;
assert ( A1 = '1' and
'1' = A1 and
B2 = false and
false = B2 and
A1 /= A2 and
B1 /= B2 and
A2 < A1 and
B2 < B1 and
A1 > A2 and
B1 > B2 and
A2 <= A1 and
B2 <= B1 and
A1 >= A2 and
B1 >= B2 and
A1 <= A1 and
B1 <= B1 and
B2 <= B2 and
A2 <= A2 )
report "***FAILED TEST: c07s02b02x00p02n01i01984 - Relational operators true table test for data type of BIT and BOOLEAN failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01984arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1984.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p02n01i01984ent IS
END c07s02b02x00p02n01i01984ent;
ARCHITECTURE c07s02b02x00p02n01i01984arch OF c07s02b02x00p02n01i01984ent IS
BEGIN
TESTING: PROCESS
variable B1 : boolean := true;
variable B2 : boolean := false;
variable A1 : bit := '1';
variable A2 : bit := '0';
BEGIN
assert NOT( A1 = '1' and
'1' = A1 and
B2 = false and
false = B2 and
A1 /= A2 and
B1 /= B2 and
A2 < A1 and
B2 < B1 and
A1 > A2 and
B1 > B2 and
A2 <= A1 and
B2 <= B1 and
A1 >= A2 and
B1 >= B2 and
A1 <= A1 and
B1 <= B1 and
B2 <= B2 and
A2 <= A2 )
report "***PASSED TEST: c07s02b02x00p02n01i01984"
severity NOTE;
assert ( A1 = '1' and
'1' = A1 and
B2 = false and
false = B2 and
A1 /= A2 and
B1 /= B2 and
A2 < A1 and
B2 < B1 and
A1 > A2 and
B1 > B2 and
A2 <= A1 and
B2 <= B1 and
A1 >= A2 and
B1 >= B2 and
A1 <= A1 and
B1 <= B1 and
B2 <= B2 and
A2 <= A2 )
report "***FAILED TEST: c07s02b02x00p02n01i01984 - Relational operators true table test for data type of BIT and BOOLEAN failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p02n01i01984arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2500.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p05n01i02500ent IS
END c07s03b03x00p05n01i02500ent;
ARCHITECTURE c07s03b03x00p05n01i02500arch OF c07s03b03x00p05n01i02500ent IS
BEGIN
TESTING: PROCESS
function f1(constant p : in STRING) return INTEGER is
begin
return P'LENGTH;
end;
constant C : STRING := "Testing";
BEGIN
wait for 5 ns;
assert NOT(f1(c) = c'LENGTH)
report "***PASSED TEST: c07s03b03x00p05n01i02500"
severity NOTE;
assert (f1(c) = c'LENGTH)
report "***FAILED TEST: c07s03b03x00p05n01i02500 - Evaluation of a function call with actual parameter expressions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p05n01i02500arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2500.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p05n01i02500ent IS
END c07s03b03x00p05n01i02500ent;
ARCHITECTURE c07s03b03x00p05n01i02500arch OF c07s03b03x00p05n01i02500ent IS
BEGIN
TESTING: PROCESS
function f1(constant p : in STRING) return INTEGER is
begin
return P'LENGTH;
end;
constant C : STRING := "Testing";
BEGIN
wait for 5 ns;
assert NOT(f1(c) = c'LENGTH)
report "***PASSED TEST: c07s03b03x00p05n01i02500"
severity NOTE;
assert (f1(c) = c'LENGTH)
report "***FAILED TEST: c07s03b03x00p05n01i02500 - Evaluation of a function call with actual parameter expressions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p05n01i02500arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2500.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p05n01i02500ent IS
END c07s03b03x00p05n01i02500ent;
ARCHITECTURE c07s03b03x00p05n01i02500arch OF c07s03b03x00p05n01i02500ent IS
BEGIN
TESTING: PROCESS
function f1(constant p : in STRING) return INTEGER is
begin
return P'LENGTH;
end;
constant C : STRING := "Testing";
BEGIN
wait for 5 ns;
assert NOT(f1(c) = c'LENGTH)
report "***PASSED TEST: c07s03b03x00p05n01i02500"
severity NOTE;
assert (f1(c) = c'LENGTH)
report "***FAILED TEST: c07s03b03x00p05n01i02500 - Evaluation of a function call with actual parameter expressions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p05n01i02500arch;
|
USE WORK.ALL; -- Search for components in work library
LIBRARY IEEE; -- These lines informs the the compiler thatthe library IEEE
-- is used
USE IEEE.std_logic_1164.all; -- contains some conversionfunctions
USE IEEE.numeric_std.all; -- contains more conversionfunctions
ENTITY test IS END test;
ARCHITECTURE ALUTest OF test IS
constant width : INTEGER := 8;
SIGNAL a,b,q:std_logic_vector(width-1 downto 0);
SIGNAL ctrl:std_logic_vector (1 DOWNTO 0);
SIGNAL cout,cin:std_logic:='0';
COMPONENT alu
GENERIC (size: INTEGER);
PORT (
a:IN std_logic_vector (size-1 downto 0);
b:IN std_logic_vector (size-1 downto 0);
ctrl:IN std_logic_vector (1 downto 0);
q:OUT std_logic_vector (size-1 downto 0);
cout:OUT std_logic);
END COMPONENT;
FUNCTION to_std_logicvector(a:INTEGER;length:NATURAL) RETURN std_logic_vector IS
-- This function converts an integer to a std_logicvecor oflength.
-- To do this conversion are conversion functions from
-- the IEEE package used.
BEGIN
RETURN std_logic_vector(to_signed(a,length));
END;
-- The statements inside a Procedure and a function is executed in sequence.
PROCEDURE behave_alu(a:INTEGER; b:INTEGER;ctrl:INTEGER;
q:OUT std_logic_vector(width-1 downto 0);
cout: OUT std_logic) IS
-- This is a behavioral model of the ALU.
VARIABLE ret: std_logic_vector(width downto 0);
BEGIN
CASE ctrl IS
-- width+1 for compensating for cout
WHEN 0 => ret := to_std_logicvector(a+b, width+1);
WHEN 1 => ret := to_std_logicvector(a-b,width+1);
ret(width):= not ret(width);
-- & means concatenation
WHEN 2 => ret :='0' &(to_std_logicvector(a,width) nand to_std_logicvector(b,width));
WHEN 3 => ret :='0' &(to_std_logicvector(a,width) nor to_std_logicvector(b,width));
WHEN OTHERS =>
ASSERT false
REPORT "CTRL out of range, testbench error"
SEVERITY error;
END CASE;
q := ret(width-1 downto 0);
cout := ret(width);
END;
BEGIN
-- The key world process means that the code inside the process
-- is executed serially.
PROCESS
-- These variables are only valid inside a processes.
-- The biggest difference from a signal in that they
-- are uppdated immediately. Not at the nearest break.
VARIABLE res:std_logic_vector ( width-1 downto 0);
VARIABLE int_CTRL: std_logic_vector ( 2 downto 0);
VARIABLE c:std_logic;
BEGIN
FOR i IN 0 TO width-1 LOOP
a<= to_std_logicvector(i,width);
FOR j IN 0 TO width LOOP
b<= to_std_logicvector(j,width);
FOR k IN 0 TO 3 LOOP
ctrl<= to_std_logicvector(k,3)(1 downto 0);
wait for 10 ns;
behave_alu(i,j,k,res,c);
-- Assert that q = res, otherwise is
-- the messaege ?wrong result from ALU?
-- displayed in ModelSim EE window.
ASSERT q = res
REPORT "wrong result from ALU"
SEVERITY warning;
ASSERT cout = c
REPORT "wrong carry from ALU"
SEVERITY warning;
END LOOP;
END LOOP;
END LOOP;
wait;
END PROCESS;
T1:alu GENERIC MAP(width) PORT MAP (a,b,ctrl,q, cout);
END ALUTest; |
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
entity memToRegMux is
port (
MemtoReg: in ctrl_t;
aluResult : in word_t;
memReadData : in word_t;
output : out word_t
);
end entity;
architecture behav of memToRegMux is
begin
output <= memReadData when MemtoReg = '1' else aluResult;
end architecture behav;
|
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`protect end_protected
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_uartlite:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_uartlite_v2_0;
USE axi_uartlite_v2_0.axi_uartlite;
ENTITY design_1_axi_uartlite_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END design_1_axi_uartlite_0_0;
ARCHITECTURE design_1_axi_uartlite_0_0_arch OF design_1_axi_uartlite_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_uartlite IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_BAUDRATE : INTEGER;
C_DATA_BITS : INTEGER;
C_USE_PARITY : INTEGER;
C_ODD_PARITY : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
interrupt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
rx : IN STD_LOGIC;
tx : OUT STD_LOGIC
);
END COMPONENT axi_uartlite;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "axi_uartlite,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_uartlite_0_0_arch : ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_uartlite_0_0_arch: ARCHITECTURE IS "design_1_axi_uartlite_0_0,axi_uartlite,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_uartlite,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ACLK_FREQ_HZ=100000000,C_S_AXI_ADDR_WIDTH=4,C_S_AXI_DATA_WIDTH=32,C_BAUDRATE=9600,C_DATA_BITS=8,C_USE_PARITY=0,C_ODD_PARITY=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT interrupt";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF rx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART RxD";
ATTRIBUTE X_INTERFACE_INFO OF tx: SIGNAL IS "xilinx.com:interface:uart:1.0 UART TxD";
BEGIN
U0 : axi_uartlite
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_S_AXI_ADDR_WIDTH => 4,
C_S_AXI_DATA_WIDTH => 32,
C_BAUDRATE => 9600,
C_DATA_BITS => 8,
C_USE_PARITY => 0,
C_ODD_PARITY => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
interrupt => interrupt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
rx => rx,
tx => tx
);
END design_1_axi_uartlite_0_0_arch;
|
architecture RTL of FIFO is
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
end procedure proc_name;
procedure proc_name (
constant a : in integer;
signal b : in std_logic;
variable c : in std_logic_vector(3 downto 0);
signal d : out std_logic) is
begin
END procedure proc_name;
function func1 return integer is begin End function func1;
begin
end architecture RTL;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Instruction_register IS
GENERIC(N : POSITIVE := 8);
PORT(
clk,rst,set : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
);
END ENTITY Instruction_register;
Architecture behavior OF Instruction_register IS
SIGNAL sint: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
shift : PROCESS (clk, rst, set)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF rst='1' THEN
sint <= (others=>'0');
ELSE
IF set = '1' THEN
sint <= din;
END IF;
END IF;
END IF;
END PROCESS shift;
dout <= sint;
END ARCHITECTURE behavior;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: tx_arbiter - Behavioral
--
-- Description: Control who has access to the transmit queue
-- The higher number bit in "request" have higher priority
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tx_arbiter is
generic (idle_time : std_logic_vector(5 downto 0));
Port ( clk : in STD_LOGIC;
ready : in STD_LOGIC;
ch0_request : in STD_LOGIC;
ch0_granted : out STD_LOGIC;
ch0_valid : in STD_LOGIC;
ch0_data : in STD_LOGIC_VECTOR (7 downto 0);
ch1_request : in STD_LOGIC;
ch1_granted : out STD_LOGIC;
ch1_valid : in STD_LOGIC;
ch1_data : in STD_LOGIC_VECTOR (7 downto 0);
ch2_request : in STD_LOGIC;
ch2_granted : out STD_LOGIC;
ch2_valid : in STD_LOGIC;
ch2_data : in STD_LOGIC_VECTOR (7 downto 0);
ch3_request : in STD_LOGIC;
ch3_granted : out STD_LOGIC;
ch3_valid : in STD_LOGIC;
ch3_data : in STD_LOGIC_VECTOR (7 downto 0);
merged_data_valid : out STD_LOGIC;
merged_data : out STD_LOGIC_VECTOR (7 downto 0));
end tx_arbiter;
architecture Behavioral of tx_arbiter is
signal count : unsigned(5 downto 0) := (others => '0');
signal request : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal grant : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
request(0) <= ch0_request;
ch0_granted <= grant(0) and request(0);
request(1) <= ch1_request;
ch1_granted <= grant(1) and request(1);
request(2) <= ch2_request;
ch2_granted <= grant(2) and request(2);
request(3) <= ch3_request;
ch3_granted <= grant(3) and request(3);
merged_data_valid <= ch0_valid or ch1_valid or ch2_valid or ch3_valid;
merged_data <= ch0_data or ch1_data or ch2_data or ch3_data;
process(clk)
begin
if rising_edge(clk) then
grant <= grant and request;
if count = 0 and ready = '1' then
if request(3) = '1' then
grant(3) <= '1';
count <= unsigned(idle_time);
elsif request(2) = '1' then
grant(2) <= '1';
count <= unsigned(idle_time);
elsif request(1) = '1' then
grant(1) <= '1';
count <= unsigned(idle_time);
elsif request(0) = '1' then
grant(0) <= '1';
count <= unsigned(idle_time);
end if;
elsif (grant and request) /= "00000000" then
count <= unsigned(idle_time)-2;
else
count <= count-1;
end if;
end if;
end process;
end Behavioral; |
package pack is
type rec is record
x, y : integer;
end record;
type rec_vec is array (integer range <>) of rec;
constant c : bit_vector(3 downto 0) := X"f";
constant d : rec_vec(1 to 2);
end package;
entity top is
end entity;
use work.pack.all;
architecture test of top is
signal x : bit := not c(1);
signal y : integer := d(1).x + 1;
begin
end architecture;
|
package pack is
type rec is record
x, y : integer;
end record;
type rec_vec is array (integer range <>) of rec;
constant c : bit_vector(3 downto 0) := X"f";
constant d : rec_vec(1 to 2);
end package;
entity top is
end entity;
use work.pack.all;
architecture test of top is
signal x : bit := not c(1);
signal y : integer := d(1).x + 1;
begin
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity LimitTo is
Generic(
VALID_BITS : positive
);
Port (
CLK : in std_logic;
RST : in std_logic; -- low active
VALID_IN : in std_logic; -- high active
READY_IN : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
VALID_OUT : out std_logic; -- high active
READY_OUT : out std_logic;
DATA_OUT : out std_logic_vector(31 downto 0)
);
end LimitTo;
architecture limit_to_behave of LimitTo is
begin
slice_full: if VALID_BITS >= 32 generate
begin
DATA_OUT <= DATA_IN;
end generate slice_full;
slice_limit: if VALID_BITS < 32 generate
begin
DATA_OUT <= (31 downto VALID_BITS => '0') & DATA_IN(VALID_BITS-1 downto 0);
end generate slice_limit;
VALID_OUT <= VALID_IN;
READY_OUT <= READY_IN;
end limit_to_behave;
|
-------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-- Moved to proc_common_v2_00_a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
|
-------------------------------------------------------------------------------
-- $Id: ipif_pkg.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- IPIF Common Library Package
-- Moved to proc_common_v2_00_a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end ipif_pkg;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.log2;
package body ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body ipif_pkg;
|
-----------------------------------------------------------------------------
-- Title :
-- Project :
-----------------------------------------------------------------------------
-- File : baudrate_gen.vhd
-- Author :
-- Company :
-- Created : Thu Aug 21 10:54:44 2014
-- Last update : Thu Aug 21 10:54:44 2014
-- Target Device : Cyclone V
-- Standard : VHDL'93
------------------------------------------------------------------------------
-- Description :
------------------------------------------------------------------------------
-- Generated with MyHDL Version 0.8
------------------------------------------------------------------------------
-- Copyright : (c) 2014
------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
------------------------------------------------------------------------------
-- Libraries and use clauses
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity baudrate_gen is
port (
sysclk: in std_logic;
reset_n: in std_logic;
half_baud_rate_tick_o: out std_logic;
baud_rate_tick_o: out std_logic
);
end entity baudrate_gen;
-- Serial
-- This module implements a baudrate generator
--
-- Ports:
-- -----
-- sysclk: sysclk input
-- reset_n: reset input
-- baud_rate_i: the baut rate to generate
-- baud_rate_tick_o: the baud rate enable
-- -----
architecture MyHDL of baudrate_gen is
constant half_baud_const: integer := 434;
constant baud_rate_i: integer := 868;
signal baud_gen_count_reg: unsigned(9 downto 0);
begin
BAUDRATE_GEN_SEQUENTIAL_PROCESS: process (sysclk, reset_n) is
begin
if (reset_n = '0') then
baud_gen_count_reg <= to_unsigned(0, 10);
baud_rate_tick_o <= '0';
half_baud_rate_tick_o <= '0';
elsif rising_edge(sysclk) then
baud_gen_count_reg <= (baud_gen_count_reg + 1);
baud_rate_tick_o <= '0';
half_baud_rate_tick_o <= '0';
if (baud_gen_count_reg = baud_rate_i) then
baud_gen_count_reg <= to_unsigned(0, 10);
baud_rate_tick_o <= '1';
half_baud_rate_tick_o <= '1';
end if;
if (baud_gen_count_reg = half_baud_const) then
half_baud_rate_tick_o <= '1';
end if;
end if;
end process BAUDRATE_GEN_SEQUENTIAL_PROCESS;
end architecture MyHDL;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tb_eth_add_ts IS
END tb_eth_add_ts;
ARCHITECTURE behavior OF tb_eth_add_ts IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bus_append
GENERIC ( N_BYTES : integer );
PORT( Clk : IN std_logic;
Rst : IN std_logic;
Value : in STD_LOGIC_VECTOR (N_BYTES*8 - 1 downto 0);
InPkt : IN std_logic;
InData : IN std_logic_vector(7 downto 0);
OutPkt : OUT std_logic;
OutData : OUT std_logic_vector(7 downto 0));
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal Cnt64 : std_logic_vector(63 downto 0) := (others => '0');
signal InPkt : std_logic := '0';
signal InData : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OutPkt : std_logic;
signal OutData : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bus_append
GENERIC MAP ( N_BYTES <= 8 )
PORT MAP (
Clk => Clk,
Rst => Rst,
Value => Cnt64,
InPkt => InPkt,
InData => InData,
OutPkt => OutPkt,
OutData => OutData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
Cnt64 <= Cnt64 + 1;
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
InPkt <= '1';
for i in 0 to 6 loop
InData <= X"55";
wait for Clk_period;
end loop;
InData <= X"d5";
wait for Clk_period;
for i in 0 to 63 loop
InData <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
-- InData <= x"00";
-- wait for Clk_period;
InPkt <= '0';
-- insert stimulus here
wait;
end process;
END;
|
library verilog;
use verilog.vl_types.all;
entity uc is
port(
clock : in vl_logic;
reset : in vl_logic;
z : in vl_logic;
id_out : in vl_logic_vector(1 downto 0);
opcode : in vl_logic_vector(5 downto 0);
s_inc : out vl_logic;
s_inm : out vl_logic;
we3 : out vl_logic;
rwe1 : out vl_logic;
rwe2 : out vl_logic;
rwe3 : out vl_logic;
rwe4 : out vl_logic;
sec : out vl_logic;
s_es : out vl_logic;
s_rel : out vl_logic;
swe : out vl_logic;
s_ret : out vl_logic;
op : out vl_logic_vector(2 downto 0)
);
end uc;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1540.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01540ent IS
END c08s09b00x00p10n01i01540ent;
ARCHITECTURE c08s09b00x00p10n01i01540arch OF c08s09b00x00p10n01i01540ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for j in 1 to 100 loop
for i in 1 to 5 loop
k := k + 1;
end loop;
end loop;
assert NOT( k=500 )
report "***PASSED TEST: c08s09b00x00p10n01i01540"
severity NOTE;
assert ( k=500 )
report "***FAILED TEST: c08s09b00x00p10n01i01540 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01540arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1540.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01540ent IS
END c08s09b00x00p10n01i01540ent;
ARCHITECTURE c08s09b00x00p10n01i01540arch OF c08s09b00x00p10n01i01540ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for j in 1 to 100 loop
for i in 1 to 5 loop
k := k + 1;
end loop;
end loop;
assert NOT( k=500 )
report "***PASSED TEST: c08s09b00x00p10n01i01540"
severity NOTE;
assert ( k=500 )
report "***FAILED TEST: c08s09b00x00p10n01i01540 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01540arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1540.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01540ent IS
END c08s09b00x00p10n01i01540ent;
ARCHITECTURE c08s09b00x00p10n01i01540arch OF c08s09b00x00p10n01i01540ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for j in 1 to 100 loop
for i in 1 to 5 loop
k := k + 1;
end loop;
end loop;
assert NOT( k=500 )
report "***PASSED TEST: c08s09b00x00p10n01i01540"
severity NOTE;
assert ( k=500 )
report "***FAILED TEST: c08s09b00x00p10n01i01540 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01540arch;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - Clock - Top level entity
--
-- project: ReconOS
-- author: Christoph R??thing, University of Paderborn
-- description: A clock manager which can be configures via the AXI
-- bus. Therefore it provides the following write only
-- registers:
-- Reg#i#: Clock 1 and 2 register of pll#i#
--
-- ======================================================================
<<reconos_preproc>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
entity reconos_clock is
--
-- Generic definitions
--
-- C_S_AXI_ - @see axi bus
--
-- C_BASE_ADDR - lower address of axi slave
-- C_HIGH_ADDR - higher address of axi slave
--
-- C_NUM_CLOCKS - number of clocks
--
-- C_CLKIN_PERIOD - input clock period
--
-- C_CLK#i# - pll generics
--
generic (
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_BASEADDR : std_logic_vector := x"FFFFFFFF";
C_HIGHADDR : std_logic_vector := x"00000000";
C_NUM_CLOCKS: integer := 1;
-- Silly Vivado does not yet (Version 2017.1) support real typed generics.
-- See AR# 58038 : https://www.xilinx.com/support/answers/58038.html
C_CLKIN_PERIOD : integer := 10;
<<generate for CLOCKS>>
C_CLK<<Id>>_CLKFBOUT_MULT : integer := 16;
C_CLK<<Id>>_DIVCLK_DIVIDE : integer := 1;
C_CLK<<Id>>_CLKOUT_DIVIDE : integer := 16<<c;>>
<<end generate>>
);
--
-- Port defintions
--
-- CLK_Ref - reference clock
--
-- CLK#i#_ - clock outputs
--
-- S_AXI_ - @see axi bus
--
port (
CLK_Ref : in std_logic;
<<generate for CLOCKS>>
CLK<<Id>>_Out : out std_logic;
CLK<<Id>>_Locked : out std_logic;
<<end generate>>
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH / 8 - 1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
end entity reconos_clock;
architecture imp of reconos_clock is
-- Declare port attributes for the Vivado IP Packager
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of CLK_Ref: SIGNAL is "xilinx.com:signal:clock:1.0 CLK_Ref CLK";
<<generate for CLOCKS>>
ATTRIBUTE X_INTERFACE_INFO of CLK<<Id>>_Out: SIGNAL is "xilinx.com:signal:clock:1.0 CLK<<Id>>_Out CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of CLK<<Id>>_Out: SIGNAL is "FREQ_HZ 100000000";
<<end generate>>
--
-- Internal ipif signals
--
-- @see axi_lite_ipif_v1_01_a
--
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_data : std_logic_vector(31 downto 0);
signal bus2ip_cs : std_logic_vector(C_NUM_CLOCKS - 1 downto 0);
signal bus2ip_rdce : std_logic_vector(C_NUM_CLOCKS - 1 downto 0);
signal bus2ip_wrce : std_logic_vector(C_NUM_CLOCKS - 1 downto 0);
signal ip2bus_data : std_logic_vector(31 downto 0);
signal ip2bus_rdack : std_logic;
signal ip2bus_wrack : std_logic;
signal ip2bus_error : std_logic;
--
-- Constants to configure ipif
--
-- @see axi_lite_ipif_v1_01_a
--
constant C_ADDR_PAD : std_logic_vector(31 downto 0) := (others => '0');
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := (
<<generate for CLOCKS>>
2 * <<_i>> + 0 => C_ADDR_PAD & std_logic_vector(unsigned(C_BASEADDR) + <<_i>> * 4),
2 * <<_i>> + 1 => C_ADDR_PAD & std_logic_vector(unsigned(C_BASEADDR) + <<_i>> * 4 + 3)<<c,>>
<<end generate>>
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (
<<generate for CLOCKS>>
<<_i>> => 1<<c,>>
<<end generate>>
);
begin
-- == Instantiation of components =====================================
--
-- Instantiation of axi_lite_ipif_v1_01_a
--
-- @see axi_lite_ipif_ds765.pdf
--
ipif : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_DPHASE_TIMEOUT => 64
)
port map (
s_axi_aclk => S_AXI_ACLK,
s_axi_aresetn => S_AXI_ARESETN,
s_axi_awaddr => S_AXI_AWADDR,
s_axi_awvalid => S_AXI_AWVALID,
s_axi_wdata => S_AXI_WDATA,
s_axi_wstrb => S_AXI_WSTRB,
s_axi_wvalid => S_AXI_WVALID,
s_axi_bready => S_AXI_BREADY,
s_axi_araddr => S_AXI_ARADDR,
s_axi_arvalid => S_AXI_ARVALID,
s_axi_rready => S_AXI_RREADY,
s_axi_arready => S_AXI_ARREADY,
s_axi_rdata => S_AXI_RDATA,
s_axi_rresp => S_AXI_RRESP,
s_axi_rvalid => S_AXI_RVALID,
s_axi_wready => S_AXI_WREADY,
s_axi_bresp => S_AXI_BRESP,
s_axi_bvalid => S_AXI_BVALID,
s_axi_awready => S_AXI_AWREADY,
bus2ip_clk => bus2ip_clk,
bus2ip_resetn => bus2ip_resetn,
bus2ip_data => bus2ip_data,
bus2ip_cs => bus2ip_cs,
bus2ip_rdce => bus2ip_rdce,
bus2ip_wrce => bus2ip_wrce,
ip2bus_data => ip2bus_data,
ip2bus_rdack => ip2bus_rdack,
ip2bus_wrack => ip2bus_wrack,
ip2bus_error => ip2bus_error
);
--
-- Instantiation of user logic
--
-- The user logic includes the actual implementation of the bus
-- attachment.
--
ul : entity work.reconos_clock_user_logic
generic map (
C_NUM_CLOCKS => C_NUM_CLOCKS,
C_CLKIN_PERIOD => REAL(C_CLKIN_PERIOD),
<<generate for CLOCKS>>
C_CLK<<Id>>_CLKFBOUT_MULT => C_CLK<<Id>>_CLKFBOUT_MULT,
C_CLK<<Id>>_DIVCLK_DIVIDE => C_CLK<<Id>>_DIVCLK_DIVIDE,
C_CLK<<Id>>_CLKOUT_DIVIDE => C_CLK<<Id>>_CLKOUT_DIVIDE<<c,>>
<<end generate>>
)
port map (
CLK_Ref => CLK_Ref,
<<generate for CLOCKS>>
CLK<<Id>>_Out => CLK<<Id>>_Out,
CLK<<Id>>_Locked => CLK<<Id>>_Locked,
<<end generate>>
BUS2IP_Clk => bus2ip_clk,
BUS2IP_Resetn => bus2ip_resetn,
BUS2IP_Data => bus2ip_data,
BUS2IP_CS => bus2ip_cs,
BUS2IP_RdCE => bus2ip_rdce,
BUS2IP_WrCE => bus2ip_wrce,
IP2BUS_Data => ip2bus_data,
IP2BUS_RdAck => ip2bus_rdack,
IP2BUS_WrAck => ip2bus_wrack,
IP2BUS_Error => ip2bus_error
);
end architecture imp; |
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library sys;
use sys.sys_pkg.all;
use work.cpu_mmu_inst_pass_pkg.all;
entity cpu_mmu_inst_pass is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_mmu_inst_pass_ctrl_in : in cpu_mmu_inst_pass_ctrl_in_type;
cpu_mmu_inst_pass_dp_in : in cpu_mmu_inst_pass_dp_in_type;
cpu_mmu_inst_pass_ctrl_out : out cpu_mmu_inst_pass_ctrl_out_type;
cpu_mmu_inst_pass_dp_out : out cpu_mmu_inst_pass_dp_out_type
);
end;
|
-- $Id: s3_sram_dummy.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: s3_sram_dummy - syn
-- Description: s3board: SRAM protection dummy
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-04-17 278 1.0.2 renamed from sram_dummy
-- 2007-12-09 101 1.0.1 use _N for active low
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity s3_sram_dummy is -- SRAM protection dummy
port (
O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv18; -- sram: address lines
IO_MEM_DATA : inout slv32 -- sram: data lines
);
end s3_sram_dummy;
architecture syn of s3_sram_dummy is
begin
O_MEM_CE_N <= "11"; -- disable sram chips
O_MEM_BE_N <= "1111";
O_MEM_WE_N <= '1';
O_MEM_OE_N <= '1';
O_MEM_ADDR <= (others=>'0');
IO_MEM_DATA <= (others=>'0');
end syn;
|
-------------------------------------------------------------------------------
-- Title : Decode dependencies
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : Control_Decode_Dependencies.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-28
-- Last update: 2016-12-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Dtall the decode (Read After Write)
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-28 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_defs.all;
-------------------------------------------------------------------------------
entity Control_Decode_Dependencies is
generic (
NB_REGISTERS : integer
);
port (
clk : in std_logic;
rst : in std_logic;
-- Decode source registers
signal rsi : in natural range 0 to NB_REGISTERS - 1;
signal rti : in natural range 0 to NB_REGISTERS - 1;
-- Decode to Execute
signal i_di2ex_reg1 : in register_port_type;
signal i_di2ex_reg2 : in register_port_type;
-- Execute to Memory
signal i_ex2mem_reg1 : in register_port_type;
signal i_ex2mem_reg2 : in register_port_type;
-- Memory internal pipe
signal i_mem2ctrl_stage1_reg1 : in register_port_type;
signal i_mem2ctrl_stage1_reg2 : in register_port_type;
signal i_mem2ctrl_stage2_reg1 : in register_port_type;
signal i_mem2ctrl_stage2_reg2 : in register_port_type;
-- Memory to WriteBack
signal i_mem2wb_reg1 : in register_port_type;
signal i_mem2wb_reg2 : in register_port_type;
-- Writeback to Decode
signal i_wb2di_reg1 : in register_port_type;
signal i_wb2di_reg2 : in register_port_type;
-- Dependencies
signal o_raw_detected : out std_logic
);
end entity Control_Decode_Dependencies;
-------------------------------------------------------------------------------
architecture rtl of Control_Decode_Dependencies is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
o_raw_detected <= '1' when
(i_di2ex_reg1.we = '1' and i_di2ex_reg1.idx = rsi) or
(i_di2ex_reg2.we = '1' and i_di2ex_reg2.idx = rsi) or
(i_ex2mem_reg1.we = '1' and i_ex2mem_reg1.idx = rsi) or
(i_ex2mem_reg2.we = '1' and i_ex2mem_reg2.idx = rsi) or
(i_mem2ctrl_stage1_reg1.we = '1' and i_mem2ctrl_stage1_reg1.idx = rsi) or
(i_mem2ctrl_stage1_reg2.we = '1' and i_mem2ctrl_stage1_reg2.idx = rsi) or
(i_mem2ctrl_stage2_reg1.we = '1' and i_mem2ctrl_stage2_reg1.idx = rsi) or
(i_mem2ctrl_stage2_reg2.we = '1' and i_mem2ctrl_stage2_reg2.idx = rsi) or
(i_mem2wb_reg1.we = '1' and i_mem2wb_reg1.idx = rsi) or
(i_mem2wb_reg2.we = '1' and i_mem2wb_reg2.idx = rsi) or
(i_wb2di_reg1.we = '1' and i_wb2di_reg1.idx = rsi) or
(i_wb2di_reg2.we = '1' and i_wb2di_reg2.idx = rsi) or
(i_ex2mem_reg1.we = '1' and i_ex2mem_reg1.idx = rti) or
(i_ex2mem_reg2.we = '1' and i_ex2mem_reg2.idx = rti) or
(i_mem2ctrl_stage1_reg1.we = '1' and i_mem2ctrl_stage1_reg1.idx = rti) or
(i_mem2ctrl_stage1_reg2.we = '1' and i_mem2ctrl_stage1_reg2.idx = rti) or
(i_mem2ctrl_stage2_reg1.we = '1' and i_mem2ctrl_stage2_reg1.idx = rti) or
(i_mem2ctrl_stage2_reg2.we = '1' and i_mem2ctrl_stage2_reg2.idx = rti) or
(i_mem2wb_reg1.we = '1' and i_mem2wb_reg1.idx = rti) or
(i_mem2wb_reg2.we = '1' and i_mem2wb_reg2.idx = rti) or
(i_wb2di_reg1.we = '1' and i_wb2di_reg1.idx = rti) or
(i_wb2di_reg2.we = '1' and i_wb2di_reg2.idx = rti)
else '0';
end architecture rtl;
-------------------------------------------------------------------------------
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 29 20:15:21 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_buffer_register_0_0 -prefix
-- system_buffer_register_0_0_ system_buffer_register_0_0_sim_netlist.vhdl
-- Design : system_buffer_register_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_0_0_buffer_register is
port (
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
clk : in STD_LOGIC
);
end system_buffer_register_0_0_buffer_register;
architecture STRUCTURE of system_buffer_register_0_0_buffer_register is
begin
\val_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(0),
Q => val_out(0),
R => '0'
);
\val_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(10),
Q => val_out(10),
R => '0'
);
\val_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(11),
Q => val_out(11),
R => '0'
);
\val_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(12),
Q => val_out(12),
R => '0'
);
\val_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(13),
Q => val_out(13),
R => '0'
);
\val_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(14),
Q => val_out(14),
R => '0'
);
\val_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(15),
Q => val_out(15),
R => '0'
);
\val_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(16),
Q => val_out(16),
R => '0'
);
\val_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(17),
Q => val_out(17),
R => '0'
);
\val_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(18),
Q => val_out(18),
R => '0'
);
\val_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(19),
Q => val_out(19),
R => '0'
);
\val_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(1),
Q => val_out(1),
R => '0'
);
\val_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(20),
Q => val_out(20),
R => '0'
);
\val_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(21),
Q => val_out(21),
R => '0'
);
\val_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(22),
Q => val_out(22),
R => '0'
);
\val_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(23),
Q => val_out(23),
R => '0'
);
\val_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(24),
Q => val_out(24),
R => '0'
);
\val_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(25),
Q => val_out(25),
R => '0'
);
\val_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(26),
Q => val_out(26),
R => '0'
);
\val_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(27),
Q => val_out(27),
R => '0'
);
\val_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(28),
Q => val_out(28),
R => '0'
);
\val_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(29),
Q => val_out(29),
R => '0'
);
\val_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(2),
Q => val_out(2),
R => '0'
);
\val_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(30),
Q => val_out(30),
R => '0'
);
\val_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(31),
Q => val_out(31),
R => '0'
);
\val_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(3),
Q => val_out(3),
R => '0'
);
\val_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(4),
Q => val_out(4),
R => '0'
);
\val_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(5),
Q => val_out(5),
R => '0'
);
\val_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(6),
Q => val_out(6),
R => '0'
);
\val_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(7),
Q => val_out(7),
R => '0'
);
\val_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(8),
Q => val_out(8),
R => '0'
);
\val_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(9),
Q => val_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_buffer_register_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_buffer_register_0_0 : entity is "system_buffer_register_0_0,buffer_register,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_buffer_register_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_buffer_register_0_0 : entity is "buffer_register,Vivado 2016.4";
end system_buffer_register_0_0;
architecture STRUCTURE of system_buffer_register_0_0 is
begin
U0: entity work.system_buffer_register_0_0_buffer_register
port map (
clk => clk,
val_in(31 downto 0) => val_in(31 downto 0),
val_out(31 downto 0) => val_out(31 downto 0)
);
end STRUCTURE;
|
--MAC > Multiplier - Adder - Accumulator
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--------------------------------------------
entity mac is
port (
clock : in std_logic;
ai : in std_logic_vector(7 downto 0);
xi : in std_logic_vector(7 downto 0);
mac_clean : in std_logic;
data_out : out std_logic_vector (18 downto 0)
);
end entity mac;
---------------------------------------------
architecture multiplier_accumulator_implentation of mac is
signal multiplier_result : std_logic_vector(15 downto 0);
signal mult_out : std_logic_vector(18 downto 0);
signal mult_out_reg : std_logic_vector(15 downto 0);
signal reg : std_logic_vector(18 downto 0);
signal adder_result : std_logic_vector(18 downto 0);
begin
multiplier_result <= ai * xi;
adder_result <= reg + mult_out;
data_out <= reg;
process (clock)
begin
if rising_edge(clock) then
mult_out_reg <= multiplier_result;
mult_out <= std_logic_vector(resize(signed(mult_out_reg), 19));
if (mac_clean = '1') then -- Multiplier result is ready
reg <= mult_out;
else
reg <= adder_result;
end if;
end if;
end process;
end architecture multiplier_accumulator_implentation;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:31:33 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arready\ : STD_LOGIC;
signal \^m_axi_awready\ : STD_LOGIC;
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rvalid\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arvalid\ : STD_LOGIC;
signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_awvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
signal \^s_axi_rready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC;
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_arready\ <= m_axi_arready;
\^m_axi_awready\ <= m_axi_awready;
\^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0);
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_buser\(0) <= m_axi_buser(0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0);
\^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0);
\^m_axi_rlast\ <= m_axi_rlast;
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^m_axi_rvalid\ <= m_axi_rvalid;
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0);
\^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0);
\^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0);
\^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0);
\^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0);
\^s_axi_arlock\(0) <= s_axi_arlock(0);
\^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0);
\^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0);
\^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0);
\^s_axi_aruser\(0) <= s_axi_aruser(0);
\^s_axi_arvalid\ <= s_axi_arvalid;
\^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0);
\^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0);
\^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0);
\^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0);
\^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0);
\^s_axi_awlock\(0) <= s_axi_awlock(0);
\^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0);
\^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0);
\^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0);
\^s_axi_awuser\(0) <= s_axi_awuser(0);
\^s_axi_awvalid\ <= s_axi_awvalid;
\^s_axi_bready\ <= s_axi_bready;
\^s_axi_rready\ <= s_axi_rready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\ <= s_axi_wlast;
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wuser\(0) <= s_axi_wuser(0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0);
m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0);
m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0);
m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0);
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0);
m_axi_arlock(0) <= \^s_axi_arlock\(0);
m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0);
m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0);
m_axi_aruser(0) <= \^s_axi_aruser\(0);
m_axi_arvalid <= \^s_axi_arvalid\;
m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0);
m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0);
m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0);
m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0);
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0);
m_axi_awlock(0) <= \^s_axi_awlock\(0);
m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0);
m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0);
m_axi_awuser(0) <= \^s_axi_awuser\(0);
m_axi_awvalid <= \^s_axi_awvalid\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \^s_axi_rready\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \^s_axi_wlast\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \^s_axi_wuser\(0);
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_arready <= \^m_axi_arready\;
s_axi_awready <= \^m_axi_awready\;
s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0);
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_buser(0) <= \^m_axi_buser\(0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0);
s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0);
s_axi_rlast <= \^m_axi_rlast\;
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
s_axi_rvalid <= \^m_axi_rvalid\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_auto_pc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_auto_pc_1 : entity is "zynq_design_1_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_auto_pc_1 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zynq_design_1_auto_pc_1;
architecture STRUCTURE of zynq_design_1_auto_pc_1 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
library verilog;
use verilog.vl_types.all;
entity bus_master_mux is
port(
m0_addr : in vl_logic_vector(29 downto 0);
m0_as_n : in vl_logic;
m0_rw : in vl_logic;
m0_wr_data : in vl_logic_vector(31 downto 0);
m0_grant_n : in vl_logic;
m1_addr : in vl_logic_vector(29 downto 0);
m1_as_n : in vl_logic;
m1_rw : in vl_logic;
m1_wr_data : in vl_logic_vector(31 downto 0);
m1_grant_n : in vl_logic;
m2_addr : in vl_logic_vector(29 downto 0);
m2_as_n : in vl_logic;
m2_rw : in vl_logic;
m2_wr_data : in vl_logic_vector(31 downto 0);
m2_grant_n : in vl_logic;
m3_addr : in vl_logic_vector(29 downto 0);
m3_as_n : in vl_logic;
m3_rw : in vl_logic;
m3_wr_data : in vl_logic_vector(31 downto 0);
m3_grant_n : in vl_logic;
s_addr : out vl_logic_vector(29 downto 0);
s_as_n : out vl_logic;
s_rw : out vl_logic;
s_wr_data : out vl_logic_vector(31 downto 0)
);
end bus_master_mux;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:47:00 10/29/2013
-- Design Name:
-- Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Proyecto Final/proyecto-final/test_i2s.vhd
-- Project Name: proyecto-final
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2s_output
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_i2s IS
END test_i2s;
ARCHITECTURE behavior OF test_i2s IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2s_output
PORT(
clk : IN std_logic;
data_l : IN std_logic_vector(15 downto 0);
data_r : IN std_logic_vector(15 downto 0);
accepted : OUT std_logic;
i2s_sd : OUT std_logic;
i2s_lrclk : OUT std_logic;
i2s_sclk : OUT std_logic;
i2s_mclk : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal data_l : std_logic_vector(15 downto 0) := (others => '0');
signal data_r : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal accepted : std_logic;
signal i2s_sd : std_logic;
signal i2s_lrclk : std_logic;
signal i2s_sclk : std_logic;
signal i2s_mclk : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant i2s_lrclk_period : time := 10 ns;
constant i2s_sclk_period : time := 10 ns;
constant i2s_mclk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2s_output PORT MAP (
clk => clk,
data_l => data_l,
data_r => data_r,
accepted => accepted,
i2s_sd => i2s_sd,
i2s_lrclk => i2s_lrclk,
i2s_sclk => i2s_sclk,
i2s_mclk => i2s_mclk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
i2s_lrclk_process :process
begin
i2s_lrclk <= '0';
wait for i2s_lrclk_period/2;
i2s_lrclk <= '1';
wait for i2s_lrclk_period/2;
end process;
i2s_sclk_process :process
begin
i2s_sclk <= '0';
wait for i2s_sclk_period/2;
i2s_sclk <= '1';
wait for i2s_sclk_period/2;
end process;
i2s_mclk_process :process
begin
i2s_mclk <= '0';
wait for i2s_mclk_period/2;
i2s_mclk <= '1';
wait for i2s_mclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_mc is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
ncores : integer range 1 to 8 := 1;
sepirq : integer range 0 to 1 := 0;
syncrst : integer range 0 to 2 := 0;
ft : integer range 0 to 1 := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(0 to 7);
can_txo : out std_logic_vector(0 to 7)
);
attribute sync_set_reset of resetn : signal is "true";
end;
architecture rtl of can_mc is
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal cs : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
--attribute sync_set_reset : string;
attribute sync_set_reset of reset : signal is "true";
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable lcs, dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1)) or not v.hsel;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
if ncores > 1 then
if r.hsel = '1' then lcs := decode(r.haddr(10 downto 8));
else lcs := (others => '0'); end if;
dataout := data_out(conv_integer(r.haddr(10 downto 8)));
else dataout := data_out(0); lcs := "0000000" & r.hsel; end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
cs <= lcs;
ahbso.hresp <= hresp; rin <= v;
end process;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cgen : for i in 0 to 7 generate
c0 : if i < ncores generate
cmod : can_mod generic map (memtech, syncrst, ft)
port map (reset, clk, cs(i), r.hwrite2, r.haddr(7 downto 0), r.hwdata,
data_out(i), irqo(i), can_rxi(i), can_txo(i), ahbsi.testen);
end generate;
c1 : if i >= ncores generate
can_txo(i) <= '0'; data_out(i) <= (others => '0');
end generate;
end generate;
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, #cores " & tost(REVISION+1) & ", irq " & tost(irq));
-- pragma translate_on
end;
|
package fifo_pkg is
end package fifo_pkg;
package fifo_pkg is
end package;
package fifo_pkg is
end;
|
-------------------------------------------------------------------------------
--
-- Title : rtl_lcd1602
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : [email protected]
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Controller for LCD Display LCD1602
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rtl_lcd1602 is
generic (
TD : in time; --! simulation time;
DIV_SCL : in integer --! clock division for SCL: clk50m/DIV_SCL
);
port(
-- global ports
clk50m : in std_logic; --! system frequency (50 MHz)
rstn : in std_logic; --! '0' - negative reset
-- main interface
start : in std_logic; --! start
data_ena : in std_logic; --! data enable (S)
data_int : in std_logic_vector(7 downto 0); --! data Tx
data_sel : in std_logic; --! select: '0' - data, '1' - command
data_rw : in std_logic; --! data write: write - '0', read - '1'
lcd_ready : out std_logic; --! ready for data
lcd_init : out std_logic; --! lcd initialization complete
-- lcd1602 interface
lcd_dt : out std_logic_vector(7 downto 0); --! lcd data
lcd_en : out std_logic; --! lcd clock enable
lcd_rw : out std_logic; --! lcd r/w: write - '0', read - '1'
lcd_rs : out std_logic --! lcd set: command - '0', data - '1'
);
end rtl_lcd1602;
architecture rtl_lcd1602 of rtl_lcd1602 is
signal clk_r : std_logic;
--signal clk_f : std_logic;
signal clk_z : std_logic;
signal clk_low : std_logic;
signal cnt_div : integer range 0 to DIV_SCL:=0;
type fsm_stage is (RDY_START, INIT, WAITING, DATA, DATA_WAIT, COM, COM_WAIT);
signal STM_OP : fsm_stage;
signal busy : std_logic;
signal en : std_logic;
signal rw : std_logic;
signal rs : std_logic;
signal dt : std_logic_vector(7 downto 0);
signal lcd_cnt : std_logic_vector(2 downto 0);
signal lcd_initr : std_logic;
--signal clk_rise : std_logic;
signal clk_en : std_logic;
begin
-- clk_div generator:
pr_cnt_div: process(clk50m, rstn) is
begin
if (rstn = '0') then
cnt_div <= 0;
clk_low <= '0';
elsif (rising_edge(clk50m)) then
if (cnt_div = DIV_SCL) then
cnt_div <= 0 after td;
clk_low <= not clk_low after td;
else
cnt_div <= cnt_div + 1 after td;
end if;
end if;
end process;
-- clk rising/falling
clk_z <= clk_low after td when rising_edge(clk50m);
clk_r <= (not clk_z) and clk_low after td when rising_edge(clk50m);
--clk_f <= (not clk_low) and clk_z after td when rising_edge(clk50m);
-- lcd_output data
--lcd_initr <= '0' when (rstn = '0') else lcd_cnt(2);
lcd_init <= lcd_initr after td when rising_edge(clk50m);
lcd_ready <= busy after td when rising_edge(clk50m);
lcd_dt <= dt after td when rising_edge(clk50m);
lcd_en <= en after td when rising_edge(clk50m);
lcd_rw <= rw after td when rising_edge(clk50m);
lcd_rs <= rs after td when rising_edge(clk50m);
pr_en_clk: process(clk50m, rstn) is
begin
if (rstn = '0') then
en <= '0';
elsif (rising_edge(clk50m)) then
if (clk_en = '1') then
if (clk_r = '1') then
en <= not en after td;
end if;
else
en <= '0' after td;
end if;
end if;
end process;
--clk_rise <= (clk_f and (not en)) after td when rising_edge(clk50m);
pr_fsm_operation: process(clk50m, rstn) is
variable cnt1: std_logic_vector(4 downto 0):="00000";
begin
if (rstn = '0') then
busy <= '0';
rs <= '0';
rw <= '0';
dt <= x"00";
clk_en <= '0';
lcd_initr <= '0';
lcd_cnt <= "000";
STM_OP <= RDY_START;
elsif (rising_edge(clk50m)) then
case STM_OP is
when RDY_START =>
cnt1 := "11111";
lcd_initr <= '0' after td;
rs <= '0' after td;
rw <= '0' after td;
lcd_cnt <= "001" after td;
if ((start = '1') and (clk_r = '1')) then
STM_OP <= INIT after td;
clk_en <= '1' after td;
end if;
when INIT =>
if (clk_r = '1') then
rs <= '0' after td;
rw <= '0' after td;
STM_OP <= WAITING after td;
if lcd_cnt = "001" then
if (lcd_initr = '0') then
dt <= x"01" after td;
else
dt <= x"00" after td;
end if;
elsif lcd_cnt = "010" then
dt <= x"38" after td;
elsif lcd_cnt = "011" then
dt <= x"0C" after td;
elsif lcd_cnt = "100" then
dt <= x"06" after td;
else
null;
end if;
end if;
when WAITING =>
if (clk_r = '1') then
if lcd_cnt(2) = '1' then
STM_OP <= DATA after td;
busy <= '1' after td;
lcd_initr <= '1' after td;
else
lcd_cnt <= lcd_cnt + '1' after td;
STM_OP <= INIT after td;
end if;
end if;
when DATA_WAIT =>
if (clk_r = '1') then
busy <= '0' after td;
STM_OP <= COM after td;
end if;
when DATA =>
if (clk_r = '1') then
if (data_ena = '1') then
busy <= '0' after td;
rs <= '1' after td;
rw <= data_rw after td;
dt <= data_int after td;
STM_OP <= DATA_WAIT after td;
end if;
end if;
when COM_WAIT =>
if (clk_r = '1') then
STM_OP <= INIT after td;
end if;
when COM =>
if (clk_r = '1') then
if (cnt1 < "11111") then
cnt1 := cnt1 + 1;
else
cnt1 := "00000";
end if;
if (cnt1(4) = '0') then
dt <= "10000000" + cnt1 after td;
else
dt <= "10110000" + cnt1 after td;--80H
end if;
rs <= '0' after td;
rw <= '0' after td;
lcd_cnt <= "001" after td;
STM_OP <= COM_WAIT after td;
end if;
end case;
end if;
end process;
end rtl_lcd1602; |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:18:10 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-conf-c.vhd,v 1.1 2007/03/03 17:24:06 wig Exp $
-- $Date: 2007/03/03 17:24:06 $
-- $Log: inst_t_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_A : inst_A_e
use configuration work.inst_A_e_rtl_conf;
end for;
for inst_a : inst_a_e
use configuration work.inst_a_e_rtl_conf;
end for;
for inst_b : inst_b_e
use configuration work.inst_b_e_rtl_conf;
end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DisplayDemo is
port( SW : in std_logic_vector(3 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector(3 downto 0);
KEY : in std_logic_vector(3 downto 3));
end DisplayDemo;
architecture Shell of DisplayDemo is
begin
system_core : entity work.Bin7SegDecoder(Behavioral)
port map(binInput => SW (3 downto 0),
decOut_n => HEX7(6 downto 0),
ledOut => LEDR(3 downto 0),
enable => KEY(3));
end Shell; |
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DisplayDemo is
port( SW : in std_logic_vector(3 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector(3 downto 0);
KEY : in std_logic_vector(3 downto 3));
end DisplayDemo;
architecture Shell of DisplayDemo is
begin
system_core : entity work.Bin7SegDecoder(Behavioral)
port map(binInput => SW (3 downto 0),
decOut_n => HEX7(6 downto 0),
ledOut => LEDR(3 downto 0),
enable => KEY(3));
end Shell; |
--!
--! \file third.vhd
--!
--! \author Ariane Keller
--! \date 23.03.2011
-- Demo file for the multibus. This file will be executed in slot 2.
-- It can also send and receive data to/from the Ethernet interface.
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library unisim;
use unisim.vcomponents.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity third is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32;
C_NR_SLOTS : integer := 3
);
port (
-- user defined signals: use the signal names defined in the system.ucf file!
-- user defined signals only work if they are before the reconos signals!
-- Signals for the Ethernet interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
-- SGMII-transceiver reference clock buffer input
MGTCLK_P : in std_logic;
MGTCLK_N : in std_logic;
-- Asynchronous reset
PRE_PHY_RESET : in std_logic;
PHY_RESET : out std_logic;
-- Signals for the Multibus
ready_2 : out std_logic;
req_2 : out std_logic_vector(0 to 3 - 1);
grant_2 : in std_logic_vector(0 to 3 - 1);
data_2 : out std_logic_vector(0 to 3 * 32 - 1);
sof_2 : out std_logic_vector(0 to C_NR_SLOTS - 1);
eof_2 : out std_logic_vector(0 to C_NR_SLOTS - 1);
src_rdy_2 : out std_logic_vector(0 to C_NR_SLOTS - 1);
dst_rdy_2 : in std_logic_vector(0 to C_NR_SLOTS - 1);
busdata_2 : in std_logic_vector(0 to 32 - 1);
bussof_2 : in std_logic;
buseof_2 : in std_logic;
bus_dst_rdy_2 : out std_logic;
bus_src_rdy_2 : in std_logic;
-- end user defined ports
-- normal reconOS signals
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- second ram
o_RAMAddr_x : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData_x : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData_x : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE_x : out std_logic;
o_RAMClk_x : out std_logic
);
end third;
architecture Behavioral of third is
-----------------start component declaration------------------------------
-- Component declaration for the LocalLink-level EMAC wrapper
component v6_emac_v1_4_locallink is
port(
-- 125MHz clock output from transceiver
CLK125_OUT : out std_logic;
-- 125MHz clock input from BUFG
CLK125 : in std_logic;
-- LocalLink receiver interface
RX_LL_CLOCK : in std_logic;
RX_LL_RESET : in std_logic;
RX_LL_DATA : out std_logic_vector(7 downto 0);
RX_LL_SOF_N : out std_logic;
RX_LL_EOF_N : out std_logic;
RX_LL_SRC_RDY_N : out std_logic;
RX_LL_DST_RDY_N : in std_logic;
RX_LL_FIFO_STATUS : out std_logic_vector(3 downto 0);
-- LocalLink transmitter interface
TX_LL_CLOCK : in std_logic;
TX_LL_RESET : in std_logic;
TX_LL_DATA : in std_logic_vector(7 downto 0);
TX_LL_SOF_N : in std_logic;
TX_LL_EOF_N : in std_logic;
TX_LL_SRC_RDY_N : in std_logic;
TX_LL_DST_RDY_N : out std_logic;
-- Client receiver interface
EMACCLIENTRXDVLD : out std_logic;
EMACCLIENTRXFRAMEDROP : out std_logic;
EMACCLIENTRXSTATS : out std_logic_vector(6 downto 0);
EMACCLIENTRXSTATSVLD : out std_logic;
EMACCLIENTRXSTATSBYTEVLD : out std_logic;
-- Client Transmitter Interface
CLIENTEMACTXIFGDELAY : in std_logic_vector(7 downto 0);
EMACCLIENTTXSTATS : out std_logic;
EMACCLIENTTXSTATSVLD : out std_logic;
EMACCLIENTTXSTATSBYTEVLD : out std_logic;
-- MAC control interface
CLIENTEMACPAUSEREQ : in std_logic;
CLIENTEMACPAUSEVAL : in std_logic_vector(15 downto 0);
-- EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS : out std_logic;
EMACANINTERRUPT : out std_logic;
-- SGMII interface
TXP : out std_logic;
TXN : out std_logic;
RXP : in std_logic;
RXN : in std_logic;
PHYAD : in std_logic_vector(4 downto 0);
RESETDONE : out std_logic;
-- SGMII transceiver clock buffer input
CLK_DS : in std_logic;
-- Asynchronous reset
RESET : in std_logic
);
end component;
-- Component declaration for the ll_fifo. This is used on the transmit
-- and on the receive side to convert from a data width of 8 bits to 32 bits.
component ll_fifo
generic (
MEM_TYPE : integer := 0; -- 0 choose BRAM,
-- 1 choose Distributed RAM
BRAM_MACRO_NUM : integer := 16; -- Memory Depth. For BRAM only
DRAM_DEPTH : integer := 16; -- Memory Depth. For DRAM only
WR_DWIDTH : integer := 32; -- FIFO write data width,
-- Acceptable values are
-- 8, 16, 32, 64, 128.
RD_DWIDTH : integer := 8; -- FIFO read data width,
-- Acceptable values are
-- 8, 16, 32, 64, 128.
RD_REM_WIDTH : integer := 1; -- Remainder width of read data
WR_REM_WIDTH : integer := 2; -- Remainder width of write data
USE_LENGTH : boolean := false; -- Length FIFO option
glbtm : time := 1 ns -- Global timing delay for simulation
);
port (
-- Reset
areset_in : in std_logic;
-- clocks
write_clock_in : in std_logic;
read_clock_in : in std_logic;
-- Interface to downstream user application
data_out : out std_logic_vector(0 to RD_DWIDTH-1);
rem_out : out std_logic_vector(0 to RD_REM_WIDTH-1);
sof_out_n : out std_logic;
eof_out_n : out std_logic;
src_rdy_out_n : out std_logic;
dst_rdy_in_n : in std_logic;
-- Interface to upstream user application
data_in : in std_logic_vector(0 to WR_DWIDTH-1);
rem_in : in std_logic_vector(0 to WR_REM_WIDTH-1);
sof_in_n : in std_logic;
eof_in_n : in std_logic;
src_rdy_in_n : in std_logic;
dst_rdy_out_n : out std_logic;
-- FIFO status signals
fifostatus_out : out std_logic_vector(0 to 3)
);
end component;
-----------------end component declaration------------------------------
-----------------signal declaration ------------------------------------
-- Constants for the message boxes. SW_HW: communication from SW to HW
-- HW_SW: communication from HW to SW
constant C_MBOX_HANDLE_SW_HW : std_logic_vector(0 to 31) := X"00000000";
constant C_MBOX_HANDLE_HW_SW : std_logic_vector(0 to 31) := X"00000001";
-- State machines
type os_state is ( STATE_INIT,
STATE_SEND_BUS_COUNTER,
STATE_SEND_ETH_COUNTER,
STATE_GET_COMMAND,
STATE_DECODE);
signal os_sync_state : os_state := STATE_INIT;
type s_state is ( S_STATE_INIT,
S_STATE_WAIT,
S_STATE_LOCK,
S_STATE_SEND_FIRST,
S_STATE_INTERM);
signal send_to_0_state : s_state;
signal send_to_0_state_next : s_state;
signal send_to_1_state : s_state;
signal send_to_1_state_next : s_state;
signal send_to_2_state : s_state;
signal send_to_2_state_next : s_state;
signal send_to_eth_state : s_state;
signal send_to_eth_state_next : s_state;
type r_state is ( R_STATE_INIT,
R_STATE_COUNT);
signal receive_state : r_state;
signal receive_state_next : r_state;
signal receive_eth_state : r_state;
signal receive_eth_state_next : r_state;
-- Ethernet Signals
-- Synchronous reset registers in the LocalLink clock domain
signal ll_pre_reset_i : std_logic_vector(5 downto 0);
signal ll_reset_i : std_logic;
attribute async_reg : string;
attribute async_reg of ll_pre_reset_i : signal is "true";
-- Reset signal from the transceiver
signal resetdone_i : std_logic;
signal resetdone_r : std_logic;
attribute async_reg of resetdone_r : signal is "true";
-- Transceiver output clock (REFCLKOUT at 125MHz)
signal clk125_o : std_logic;
-- 125MHz clock input to wrappers
signal clk125 : std_logic;
attribute keep : boolean;
attribute keep of clk125 : signal is true;
-- Input 125MHz differential clock for transceiver
signal clk_ds : std_logic;
-- Global asynchronous reset
signal reset_i : std_logic;
-- LocalLink interface clocking signal
signal ll_clk_i : std_logic;
-- Signals between sending process and ll tx fifo
signal tx_ll_data_i : std_logic_vector(31 downto 0);
signal tx_ll_sof_n_i : std_logic;
signal tx_ll_eof_n_i : std_logic;
signal tx_ll_src_rdy_n_i : std_logic;
signal tx_ll_dst_rdy_n_i : std_logic;
--Signals between ll_tx fifo and eth_ll_fifo
signal eth_tx_ll_data_i : std_logic_vector(7 downto 0);
signal eth_tx_ll_sof_n_i : std_logic;
signal eth_tx_ll_eof_n_i : std_logic;
signal eth_tx_ll_src_rdy_n_i : std_logic;
signal eth_tx_ll_dst_rdy_n_i : std_logic;
--Signals from eth ll fifo to rx_ll fifo
signal rx_ll_data_i : std_logic_vector(7 downto 0);
signal rx_ll_sof_n_i : std_logic;
signal rx_ll_eof_n_i : std_logic;
signal rx_ll_src_rdy_n_i : std_logic;
signal rx_ll_dst_rdy_n_i : std_logic;
--Signals from rx_ll fifo to process
signal rx_data : std_logic_vector(31 downto 0);
signal rx_sof_out_n : std_logic;
signal rx_eof_out_n : std_logic;
signal rx_src_rdy_out_n : std_logic;
signal rx_dst_rdy_in_n : std_logic;
signal rx_rem : std_logic_vector(1 downto 0);
-- bus signals (for communication between hw threats)
signal to_0_data : std_logic_vector(0 to 32 - 1);
signal to_1_data : std_logic_vector(0 to 32 - 1);
signal to_2_data : std_logic_vector(0 to 32 - 1);
signal to_0_sof : std_logic;
signal to_1_sof : std_logic;
signal to_2_sof : std_logic;
signal to_1_eof : std_logic;
signal to_2_eof : std_logic;
signal to_0_eof : std_logic;
signal received_counter : natural;
signal received_counter_next : natural;
signal received_eth_counter : natural;
signal received_eth_counter_next: natural;
signal start_to_0 : std_logic;
signal s_0_counter : natural;
signal s_0_counter_next : natural;
signal start_to_1 : std_logic;
signal s_1_counter : natural;
signal s_1_counter_next : natural;
signal start_to_2 : std_logic;
signal s_2_counter : natural;
signal s_2_counter_next : natural;
signal start_to_eth : std_logic;
signal s_eth_counter : natural;
signal s_eth_counter_next : natural;
--end signal declaration
begin
-- Ethernet setup
reset_i <= PRE_PHY_RESET;
PHY_RESET <= not reset_i;
-- Generate the clock input to the transceiver
-- (clk_ds can be shared between multiple EMAC instances, including
-- multiple instantiations of the EMAC wrappers)
clkingen : IBUFDS_GTXE1 port map (
I => MGTCLK_P,
IB => MGTCLK_N,
CEB => '0',
O => clk_ds,
ODIV2 => open
);
-- The 125MHz clock from the transceiver is routed through a BUFG and
-- input to the MAC wrappers
-- (clk125 can be shared between multiple EMAC instances, including
-- multiple instantiations of the EMAC wrappers)
bufg_clk125 : BUFG port map (
I => clk125_o,
O => clk125
);
-- Clock the LocalLink interface with the globally-buffered 125MHz
-- clock from the transceiver
ll_clk_i <= clk125;
-- Synchronize resetdone_i from the GT in the transmitter clock domain
gen_resetdone_r : process(ll_clk_i, reset_i)
begin
if (reset_i = '1') then
resetdone_r <= '0';
elsif ll_clk_i'event and ll_clk_i = '1' then
resetdone_r <= resetdone_i;
end if;
end process gen_resetdone_r;
-- Create synchronous reset in the transmitter clock domain
gen_ll_reset : process (ll_clk_i, reset_i)
begin
if reset_i = '1' then
ll_pre_reset_i <= (others => '1');
ll_reset_i <= '1';
elsif ll_clk_i'event and ll_clk_i = '1' then
if resetdone_r = '1' then
ll_pre_reset_i(0) <= '0';
ll_pre_reset_i(5 downto 1) <= ll_pre_reset_i(4 downto 0);
ll_reset_i <= ll_pre_reset_i(5);
end if;
end if;
end process gen_ll_reset;
-- End Ethernet setup
--Default assignements
-- we don't need the memories in this example
o_RAMAddr <= (others => '0');
o_RAMData <= (others => '0');
o_RAMWE <= '0';
o_RAMClk <= '0';
o_RAMAddr_x <= (others => '0');
o_RAMData_x <= (others => '0');
o_RAMWE_x <= '0';
o_RAMClk_x <= '0';
data_2 <= to_0_data & to_1_data & to_2_data;
ready_2 <= '0'; -- unused
-----------------start components------------------------------
v6_emac_v1_4_locallink_inst : v6_emac_v1_4_locallink port map (
-- 125MHz clock output from transceiver
CLK125_OUT => clk125_o,
-- 125MHz clock input from BUFG
CLK125 => clk125,
-- LocalLink receiver interface
RX_LL_CLOCK => ll_clk_i,
RX_LL_RESET => ll_reset_i,
RX_LL_DATA => rx_ll_data_i,
RX_LL_SOF_N => rx_ll_sof_n_i,
RX_LL_EOF_N => rx_ll_eof_n_i,
RX_LL_SRC_RDY_N => rx_ll_src_rdy_n_i,
RX_LL_DST_RDY_N => rx_ll_dst_rdy_n_i,
RX_LL_FIFO_STATUS => open,
-- Client receiver signals
EMACCLIENTRXDVLD => open, --EMACCLIENTRXDVLD,
EMACCLIENTRXFRAMEDROP => open, --EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS => open, --EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD => open, --EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD => open, --EMACCLIENTRXSTATSBYTEVLD,
-- LocalLink transmitter interface
TX_LL_CLOCK => ll_clk_i,
TX_LL_RESET => ll_reset_i,
TX_LL_DATA => eth_tx_ll_data_i,
TX_LL_SOF_N => eth_tx_ll_sof_n_i,
TX_LL_EOF_N => eth_tx_ll_eof_n_i,
TX_LL_SRC_RDY_N => eth_tx_ll_src_rdy_n_i,
TX_LL_DST_RDY_N => eth_tx_ll_dst_rdy_n_i,
-- Client transmitter signals
CLIENTEMACTXIFGDELAY => (others => '0'), --CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS => open, --EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD => open, --EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD => open, --EMACCLIENTTXSTATSBYTEVLD,
-- MAC control interface
CLIENTEMACPAUSEREQ => '0', --CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL => (others => '0'), --CLIENTEMACPAUSEVAL,
-- EMAC-transceiver link status
EMACCLIENTSYNCACQSTATUS => open, --EMACCLIENTSYNCACQSTATUS,
EMACANINTERRUPT => open, --EMACANINTERRUPT,
-- SGMII interface
TXP => TXP,
TXN => TXN,
RXP => RXP,
RXN => RXN,
PHYAD => (others => '0'), --PHYAD,
RESETDONE => resetdone_i,
-- SGMII transceiver reference clock buffer input
CLK_DS => clk_ds,
-- Asynchronous reset
RESET => reset_i
);
TX_FIFO : ll_fifo
port map (
areset_in => reset,
write_clock_in => clk,
read_clock_in => ll_clk_i,
-- Interface to downstream user application
data_out => eth_tx_ll_data_i,
rem_out => open,
sof_out_n => eth_tx_ll_sof_n_i,
eof_out_n => eth_tx_ll_eof_n_i,
src_rdy_out_n => eth_tx_ll_src_rdy_n_i,
dst_rdy_in_n => eth_tx_ll_dst_rdy_n_i,
-- Interface to upstream user application
data_in => tx_ll_data_i,
rem_in => (others => '0'),
sof_in_n => tx_ll_sof_n_i,
eof_in_n => tx_ll_eof_n_i,
src_rdy_in_n => tx_ll_src_rdy_n_i,
dst_rdy_out_n => tx_ll_dst_rdy_n_i,
-- FIFO status signals
fifostatus_out => open
);
RX_FIFO_1 : ll_fifo
generic map(
WR_DWIDTH => 8, -- FIFO write data width,
RD_DWIDTH => 32, -- FIFO read data width,
RD_REM_WIDTH => 2, -- Remainder width of read data
WR_REM_WIDTH => 1 -- Remainder width of write data
)
port map (
areset_in => reset,
write_clock_in => ll_clk_i,
read_clock_in => clk,
data_out => rx_data,
rem_out => rx_rem,
sof_out_n => rx_sof_out_n,
eof_out_n => rx_eof_out_n,
src_rdy_out_n => rx_src_rdy_out_n,
dst_rdy_in_n => rx_dst_rdy_in_n,
data_in => rx_ll_data_i,
rem_in => (others => '0'),
sof_in_n => rx_ll_sof_n_i,
eof_in_n => rx_ll_eof_n_i,
src_rdy_in_n => rx_ll_src_rdy_n_i,
dst_rdy_out_n => rx_ll_dst_rdy_n_i,
-- FIFO status signals
fifostatus_out => open
);
------------------------ State machines------------------------------------
-- Counts the number of packets received on the Bus interface
receiving : process(busdata_2, bussof_2, buseof_2, bus_src_rdy_2,
receive_state, received_counter)
begin
bus_dst_rdy_2 <= '1';
receive_state_next <= receive_state;
received_counter_next <= received_counter;
case receive_state is
when R_STATE_INIT =>
received_counter_next <= 0;
receive_state_next <= R_STATE_COUNT;
when R_STATE_COUNT =>
if bussof_2 = '1' then
received_counter_next <= received_counter + 1;
end if;
end case;
end process;
-- Counts the number of packets received on the Ethernet interface
receiving_eth : process(rx_data, rx_sof_out_n, rx_eof_out_n,
rx_src_rdy_out_n, receive_eth_state,
received_eth_counter)
begin
rx_dst_rdy_in_n <= '0';
receive_eth_state_next <= receive_eth_state;
received_eth_counter_next <= received_eth_counter;
case receive_state is
when R_STATE_INIT =>
received_eth_counter_next <= 0;
receive_eth_state_next <= R_STATE_COUNT;
when R_STATE_COUNT =>
if rx_src_rdy_out_n = '0' then
if rx_sof_out_n = '0' then
received_eth_counter_next <= received_eth_counter + 1;
end if;
end if;
end case;
end process;
-- Sends packets to the thread in slot 0 as long as the "start_to_eth" is high.
send_to_0 : process(start_to_0, send_to_0_state, s_0_counter, grant_2)
begin
src_rdy_2(0) <= '0';
to_0_data <= (others => '0');
sof_2(0) <= '0';
eof_2(0) <= '0';
req_2(0) <= '0';
send_to_0_state_next <= send_to_0_state;
s_0_counter_next <= s_0_counter;
case send_to_0_state is
when S_STATE_INIT =>
send_to_0_state_next <= S_STATE_WAIT;
s_0_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_0 = '1' then
send_to_0_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_2(0) <= '1';
if grant_2(0) = '0' then
send_to_0_state_next <= S_STATE_LOCK;
else
send_to_0_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_2(0) <= '1';
sof_2(0) <= '1';
to_0_data <= (others => '1');
s_0_counter_next <= s_0_counter + 1;
send_to_0_state_next <= S_STATE_INTERM;
req_2(0) <= '1';
when S_STATE_INTERM =>
req_2(0) <= '1';
src_rdy_2(0) <= '1';
to_0_data <= (others => '0');
if s_0_counter = 15 then
s_0_counter_next <= 0;
send_to_0_state_next <= S_STATE_WAIT;
eof_2(0) <= '1';
else
s_0_counter_next <= s_0_counter + 1;
end if;
end case;
end process;
-- Sends packets to the thread in slot 1 as long as the "start_to_eth" is high.
send_to_1 : process(start_to_1, send_to_1_state, s_1_counter, grant_2)
begin
src_rdy_2(1) <= '0';
to_1_data <= (others => '0');
sof_2(1) <= '0';
eof_2(1) <= '0';
req_2(1) <= '0';
send_to_1_state_next <= send_to_1_state;
s_1_counter_next <= s_1_counter;
case send_to_1_state is
when S_STATE_INIT =>
send_to_1_state_next <= S_STATE_WAIT;
s_1_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_1 = '1' then
send_to_1_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_2(1) <= '1';
if grant_2(1) = '0' then
send_to_1_state_next <= S_STATE_LOCK;
else
send_to_1_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_2(1) <= '1';
sof_2(1) <= '1';
to_1_data <= (others => '1');
s_1_counter_next <= s_1_counter + 1;
send_to_1_state_next <= S_STATE_INTERM;
req_2(1) <= '1';
when S_STATE_INTERM =>
req_2(1) <= '1';
src_rdy_2(1) <= '1';
to_1_data <= (others => '0');
if s_1_counter = 15 then
s_1_counter_next <= 0;
send_to_1_state_next <= S_STATE_WAIT;
eof_2(1) <= '1';
else
s_1_counter_next <= s_1_counter + 1;
end if;
end case;
end process;
-- Sends packets to the thread in slot 2 as long as the "start_to_eth" is high.
send_to_2 : process(start_to_2, send_to_2_state, s_2_counter, grant_2)
begin
src_rdy_2(2) <= '0';
to_2_data <= (others => '0');
sof_2(2) <= '0';
eof_2(2) <= '0';
req_2(2) <= '0';
send_to_2_state_next <= send_to_2_state;
s_2_counter_next <= s_2_counter;
case send_to_2_state is
when S_STATE_INIT =>
send_to_2_state_next <= S_STATE_WAIT;
s_2_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_2 = '1' then
send_to_2_state_next <= S_STATE_LOCK;
end if;
when S_STATE_LOCK =>
req_2(2) <= '1';
if grant_2(2) = '0' then
send_to_2_state_next <= S_STATE_LOCK;
else
send_to_2_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
src_rdy_2(2) <= '1';
sof_2(2) <= '1';
to_2_data <= (others => '1');
s_2_counter_next <= s_2_counter + 1;
send_to_2_state_next <= S_STATE_INTERM;
req_2(2) <= '1';
when S_STATE_INTERM =>
req_2(2) <= '1';
src_rdy_2(2) <= '1';
to_2_data <= (others => '0');
if s_2_counter = 15 then
s_2_counter_next <= 0;
send_to_2_state_next <= S_STATE_WAIT;
eof_2(2) <= '1';
else
s_2_counter_next <= s_2_counter + 1;
end if;
end case;
end process;
-- Sends packets to the Ethernet Interface as long as the "start_to_eth" is high.
send_to_eth : process(start_to_eth, send_to_eth_state, s_eth_counter, tx_ll_dst_rdy_n_i)
begin
tx_ll_src_rdy_n_i <= '1';
tx_ll_data_i <= (others => '0');
tx_ll_sof_n_i <= '1';
tx_ll_eof_n_i <= '1';
send_to_eth_state_next <= send_to_eth_state;
s_eth_counter_next <= s_eth_counter;
case send_to_eth_state is
when S_STATE_INIT =>
send_to_eth_state_next <= S_STATE_WAIT;
s_eth_counter_next <= 0;
when S_STATE_WAIT =>
if start_to_eth = '1' then
send_to_eth_state_next <= S_STATE_SEND_FIRST;
end if;
when S_STATE_SEND_FIRST =>
tx_ll_src_rdy_n_i <= '0';
tx_ll_sof_n_i <= '0';
tx_ll_data_i <= (others => '1');
if tx_ll_dst_rdy_n_i = '0' then
s_eth_counter_next <= s_eth_counter + 1;
send_to_eth_state_next <= S_STATE_INTERM;
end if;
when S_STATE_INTERM =>
tx_ll_src_rdy_n_i <= '0';
tx_ll_data_i <= (others => '1');
if tx_ll_dst_rdy_n_i = '0' then
if s_eth_counter = 15 then
s_eth_counter_next <= 0;
send_to_eth_state_next <= S_STATE_WAIT;
tx_ll_eof_n_i <= '0';
else
s_eth_counter_next <= s_eth_counter + 1;
end if;
end if;
when others =>
send_to_eth_state_next <= S_STATE_INIT;
end case;
end process;
-- memzing process
-- updates all the registers
proces_mem : process(clk, reset)
begin
if reset = '1' then
send_to_0_state <= S_STATE_INIT;
s_0_counter <= 0;
send_to_1_state <= S_STATE_INIT;
s_1_counter <= 0;
send_to_2_state <= S_STATE_INIT;
s_2_counter <= 0;
send_to_eth_state <= S_STATE_INIT;
s_eth_counter <= 0;
receive_state <= R_STATE_INIT;
received_counter <= 0;
receive_eth_state <= R_STATE_INIT;
received_eth_counter <= 0;
elsif rising_edge(clk) then
send_to_0_state <= send_to_0_state_next;
s_0_counter <= s_0_counter_next;
send_to_1_state <= send_to_1_state_next;
s_1_counter <= s_1_counter_next;
send_to_2_state <= send_to_2_state_next;
s_2_counter <= s_2_counter_next;
send_to_eth_state <= send_to_eth_state_next;
s_eth_counter <= s_eth_counter_next;
receive_state <= receive_state_next;
received_counter <= received_counter_next;
receive_eth_state <= receive_eth_state_next;
received_eth_counter <= received_eth_counter_next;
end if;
end process;
-- OS synchronization state machine (the reconOS state machine)
-- this has to have this special format!
state_proc : process(clk, reset)
variable success : boolean;
variable done : boolean;
variable sw_command : std_logic_vector(0 to C_OSIF_DATA_WIDTH - 1);
begin
if reset = '1' then
reconos_reset_with_signature(o_osif, i_osif, X"ABCDEF01");
os_sync_state <= STATE_INIT;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case os_sync_state is
when STATE_INIT =>
os_sync_state <= STATE_GET_COMMAND;
start_to_0 <= '0';
start_to_1 <= '0';
start_to_2 <= '0';
when STATE_SEND_BUS_COUNTER =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_HANDLE_HW_SW,
std_logic_vector(to_unsigned(received_counter,C_OSIF_DATA_WIDTH)));
if done then
os_sync_state <= STATE_GET_COMMAND;
end if;
when STATE_SEND_ETH_COUNTER =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MBOX_HANDLE_HW_SW,
std_logic_vector(to_unsigned(received_eth_counter,C_OSIF_DATA_WIDTH)));
if done then
os_sync_state <= STATE_GET_COMMAND;
end if;
when STATE_GET_COMMAND =>
reconos_mbox_get(done, success, o_osif, i_osif, C_MBOX_HANDLE_SW_HW, sw_command);
if done and success then
os_sync_state <= STATE_DECODE;
end if;
when STATE_DECODE =>
--default: command not known
os_sync_state <= STATE_GET_COMMAND;
-- element 0 indicates whether this thread should send to slot 0,
-- element 1 indicates whether this thread should send to slot 1,
-- element 6 indicates whether the receive counter from the bus interface
-- should be reported
-- element 7 indicates whether the receive counter from the eth interface
-- should be reported. Note, 6 and 7 can only be specified exclusivly. E.g.
-- only one counter value can be reported with one request.
if sw_command(6) = '1' then
os_sync_state <= STATE_SEND_BUS_COUNTER;
elsif sw_command(7) = '1' then
os_sync_state <= STATE_SEND_ETH_COUNTER;
else
if sw_command(0) = '1' then
start_to_0 <= '1';
else
start_to_0 <= '0';
end if;
if sw_command(1) = '1' then
start_to_1 <= '1';
else
start_to_1 <= '0';
end if;
if sw_command(2) = '1' then
start_to_2 <= '1';
else
start_to_2 <= '0';
end if;
if sw_command(3) = '1' then
start_to_eth <= '1';
else
start_to_eth <= '0';
end if;
end if;
when others =>
os_sync_state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:32:27 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_stub.vhdl
-- Design : vio_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0],probe_in3[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2016.3";
begin
end;
|
-- NEED RESULT: ARCH00418.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00418: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00418: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00418: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00418: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00418
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00418(ARCH00418)
-- ENT00418_Test_Bench(ARCH00418_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00418 is
end ENT00418 ;
--
--
architecture ARCH00418 of ENT00418 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns,
-- c_st_rec3_1.f2.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00418.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00418" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 4 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00418" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 5 ;
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_2.f2.f2 after 10 ns ,
-- c_st_rec3_1.f2.f2 after 20 ns ,
-- c_st_rec3_2.f2.f2 after 30 ns ,
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_2.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00418" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3.f2.f2 <=
-- c_st_rec3_1.f2.f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3.f2.f2 =
c_st_rec3_1.f2.f2 and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00418" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00418" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
wait until (not s_st_rec3.f2.f2'Quiet) and
(s_st_rec3_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec3.f2.f2 <=
c_st_rec3_2.f2.f2 after 10 ns,
c_st_rec3_1.f2.f2 after 20 ns
when st_rec3_select = 1 else
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when st_rec3_select = 2 else
--
c_st_rec3_1.f2.f2 after 5 ns
when st_rec3_select = 3 else
--
c_st_rec3_1.f2.f2 after 100 ns
when st_rec3_select = 4 else
--
c_st_rec3_2.f2.f2 after 10 ns ,
c_st_rec3_1.f2.f2 after 20 ns ,
c_st_rec3_2.f2.f2 after 30 ns ,
c_st_rec3_1.f2.f2 after 40 ns
when st_rec3_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_1.f2.f2 after 40 ns ;
--
end ARCH00418 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00418_Test_Bench is
end ENT00418_Test_Bench ;
--
--
architecture ARCH00418_Test_Bench of ENT00418_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00418 ( ARCH00418 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00418_Test_Bench ;
|
architecture RTL of ENT is
begin
-- These should pass the check
O_FOO <= (1 => q_foo(63 downto 32),
0 => q_foo(31 downto 0));
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
-- These should fail the check
O_FOO <= (1 => q_foo(63 downto 32),
0 => q_foo(31 downto 0));
n_foo <= resize(unsigned(I_FOO) +
unsigned(I_BAR), q_foo'length);
O_FOO <=
(
1 => func1(std_logic_vector(G_GEN1), G_GEN2),
2 => func2(func3(G_GEN3), G_GEN3),
3 => func4(G_GEN4)
);
end architecture RTL;
|
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