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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
-- Example of the GCModeller assembly script for
-- compile a virtual vell data model file
-- *.vhd GCModeller virtual assembly script
--
-- V virtual cell
-- H habiliment
-- D dialog
-- build a new virtual cell model from a base model
-- which the base model is named hsa and version label is
-- 20200929
--
-- if the version label is missing, then the latest model
-- of the specific name "hsa" in your repository will be
-- used
FROM hsa:20200929
-- add meta data for your new model
-- MAINTAINER is a kind of shortcut of the
-- LABEL maintainer="xxx"
MAINTAINER xieguigang "<[email protected]>"
-- keyword is a term list that used for registry indexing
-- of your generated virtual cell model
-- these keywords is used for local repository search and
-- online search.
--
-- the quot character can be omit if the keyword contains no
-- white space
-- and each keyword terms should be seperated by the comma
-- symbol
KEYWORDS hsa,"Human Diseases"
-- the label is apply for add meta data to your virtual
-- cell data model
-- label meta is written in key-string_value pair format
-- the meta data key is not limited on number, andalso
-- you can add any meta name as you wish
LABEL version="1.0",day="2020-10-01"
LABEL author="xieguigang <[email protected]>"
LABEL about="blabla"
LABEL url="https://gcmodeller.org"
-- set compiler environment variables
-- the environment variable could affect some compiler
-- behaviors
ENV name="value"
ENV name2="value2"
-- do virtual cell model modifications
-- example of add enzyme by a specific kegg ortholog id
-- this usually could reshape the metabolic network
-- structure
ADD K00087,K00106,K11177,K11178,K13479,K13480,K13482
-- example of add enzyme by specific a kegg orthology
-- category.
-- this command will add all enzymes in the specific
-- category
ADD KO:"Human Diseases\Neurodegenerative disease\*"
-- as the same as the ADD command, DELETE command also can
-- accept a list of KO id or category match for removes the
-- specific enzymes from the base model for create a new
-- model
-- example of delete enzyme by specific a kegg orthology
-- category.
-- this command will removes all enzymes under the
-- specific category.
DELETE KO:"Human Diseases\Substance dependence\*" |
-- Example of the GCModeller assembly script for
-- compile a virtual vell data model file
-- *.vhd GCModeller virtual assembly script
--
-- V virtual cell
-- H habiliment
-- D dialog
-- build a new virtual cell model from a base model
-- which the base model is named hsa and version label is
-- 20200929
--
-- if the version label is missing, then the latest model
-- of the specific name "hsa" in your repository will be
-- used
FROM hsa:20200929
-- add meta data for your new model
-- MAINTAINER is a kind of shortcut of the
-- LABEL maintainer="xxx"
MAINTAINER xieguigang "<[email protected]>"
-- keyword is a term list that used for registry indexing
-- of your generated virtual cell model
-- these keywords is used for local repository search and
-- online search.
--
-- the quot character can be omit if the keyword contains no
-- white space
-- and each keyword terms should be seperated by the comma
-- symbol
KEYWORDS hsa,"Human Diseases"
-- the label is apply for add meta data to your virtual
-- cell data model
-- label meta is written in key-string_value pair format
-- the meta data key is not limited on number, andalso
-- you can add any meta name as you wish
LABEL version="1.0",day="2020-10-01"
LABEL author="xieguigang <[email protected]>"
LABEL about="blabla"
LABEL url="https://gcmodeller.org"
-- set compiler environment variables
-- the environment variable could affect some compiler
-- behaviors
ENV name="value"
ENV name2="value2"
-- do virtual cell model modifications
-- example of add enzyme by a specific kegg ortholog id
-- this usually could reshape the metabolic network
-- structure
ADD K00087,K00106,K11177,K11178,K13479,K13480,K13482
-- example of add enzyme by specific a kegg orthology
-- category.
-- this command will add all enzymes in the specific
-- category
ADD KO:"Human Diseases\Neurodegenerative disease\*"
-- as the same as the ADD command, DELETE command also can
-- accept a list of KO id or category match for removes the
-- specific enzymes from the base model for create a new
-- model
-- example of delete enzyme by specific a kegg orthology
-- category.
-- this command will removes all enzymes under the
-- specific category.
DELETE KO:"Human Diseases\Substance dependence\*" |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when (rd_en = '1')else '1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when (rd_en = '1')else '1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1')else '1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when (rd_en = '1')else '1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when (rd_en = '1')else '1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1')else '1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
-- $Id: gray_cnt_5.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_5 - syn
-- Description: 5 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-07 840 1.1 disable fsm recognition in vivado
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 9 5 302MHz/ 3.31ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray_cnt_5 is -- 5 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv5 -- data out
);
end entity gray_cnt_5;
architecture syn of gray_cnt_5 is
signal R_DATA : slv5 := (others=>'0');
signal N_DATA : slv5 := (others=>'0');
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm
-- is inferred, using 'Johnson' encoding. DATA will be deduced
-- in a combinatorial logic, and will thus have very likely some
-- glitches at the clock transitions, rendering the whole Gray
-- coding useless.
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
-- Note: vivado started with -fsm_extraction one_hot didn't fsm recognize
-- this code up to 2016.2. With 2016.3 and later it is converted into a
-- 31 state one-hot fsm, unless explicitely suppressed
attribute fsm_encoding : string;
attribute fsm_encoding of R_DATA : signal is "none";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
N_DATA <= (others=>'0');
case R_DATA is
when "00000" => N_DATA <= "00001"; -- 0
when "00001" => N_DATA <= "00011"; -- 1
when "00011" => N_DATA <= "00010"; -- 2
when "00010" => N_DATA <= "00110"; -- 3
when "00110" => N_DATA <= "00111"; -- 4
when "00111" => N_DATA <= "00101"; -- 5
when "00101" => N_DATA <= "00100"; -- 6
when "00100" => N_DATA <= "01100"; -- 7
when "01100" => N_DATA <= "01101"; -- 8
when "01101" => N_DATA <= "01111"; -- 9
when "01111" => N_DATA <= "01110"; -- 10
when "01110" => N_DATA <= "01010"; -- 11
when "01010" => N_DATA <= "01011"; -- 12
when "01011" => N_DATA <= "01001"; -- 13
when "01001" => N_DATA <= "01000"; -- 14
when "01000" => N_DATA <= "11000"; -- 15
when "11000" => N_DATA <= "11001"; -- 16
when "11001" => N_DATA <= "11011"; -- 17
when "11011" => N_DATA <= "11010"; -- 18
when "11010" => N_DATA <= "11110"; -- 19
when "11110" => N_DATA <= "11111"; -- 20
when "11111" => N_DATA <= "11101"; -- 21
when "11101" => N_DATA <= "11100"; -- 22
when "11100" => N_DATA <= "10100"; -- 23
when "10100" => N_DATA <= "10101"; -- 24
when "10101" => N_DATA <= "10111"; -- 25
when "10111" => N_DATA <= "10110"; -- 26
when "10110" => N_DATA <= "10010"; -- 27
when "10010" => N_DATA <= "10011"; -- 28
when "10011" => N_DATA <= "10001"; -- 29
when "10001" => N_DATA <= "10000"; -- 30
when "10000" => N_DATA <= "00000"; -- 31
when others => null;
end case;
end process proc_next;
DATA <= R_DATA;
end syn;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:37:35 10/24/2015
-- Design Name:
-- Module Name: periodMap - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity periodMap is
Port ( clk : in STD_LOGIC;
key : in STD_LOGIC_VECTOR (31 downto 0);
sig : out STD_LOGIC_VECTOR (7 downto 0));
end periodMap;
architecture Behavioral of periodMap is
component voiceSynth
port ( clk : in STD_LOGIC;
enable : in STD_LOGIC;
period : in unsigned (15 downto 0);
sig : out STD_LOGIC_VECTOR (7 downto 0));
end component;
type vectorPeriod is array (natural range <>) of unsigned(15 downto 0);
constant keyPeriodMap : vectorPeriod(0 to 31) := (
to_unsigned(17896, 16),
to_unsigned(16892, 16),
to_unsigned(15944, 16),
to_unsigned(15049, 16),
to_unsigned(14204, 16),
to_unsigned(13407, 16),
to_unsigned(12654, 16),
to_unsigned(11944, 16),
to_unsigned(11274, 16),
to_unsigned(10641, 16),
to_unsigned(10044, 16),
to_unsigned(9480, 16),
to_unsigned(8948, 16),
to_unsigned(8446, 16),
to_unsigned(7972, 16),
to_unsigned(7524, 16),
to_unsigned(7102, 16),
to_unsigned(6703, 16),
to_unsigned(6327, 16),
to_unsigned(5972, 16),
to_unsigned(5637, 16),
to_unsigned(5320, 16),
to_unsigned(5022, 16),
to_unsigned(4740, 16),
to_unsigned(4474, 16),
to_unsigned(4223, 16),
to_unsigned(3986, 16),
to_unsigned(3762, 16),
to_unsigned(3551, 16),
to_unsigned(3351, 16),
to_unsigned(3163, 16),
to_unsigned(2986, 16)
);
type vectorSignal is array (natural range <>) of std_logic_vector(7 downto 0);
signal signalMap : vectorSignal(31 downto 0);
signal sigOut : std_logic_vector(12 downto 0);
begin
GEN_REG:
for I in 0 to 31 generate
voiceSynthInstance: voiceSynth port map (
clk => clk,
enable => key(I),
period => keyPeriodMap(I),
sig => signalMap(I)
);
end generate GEN_REG;
sigOut <= std_logic_vector(
resize(unsigned(signalMap(0)),13)+
resize(unsigned(signalMap(1)),13)+
resize(unsigned(signalMap(2)),13)+
resize(unsigned(signalMap(3)),13)+
resize(unsigned(signalMap(4)),13)+
resize(unsigned(signalMap(5)),13)+
resize(unsigned(signalMap(6)),13)+
resize(unsigned(signalMap(7)),13)+
resize(unsigned(signalMap(8)),13)+
resize(unsigned(signalMap(9)),13)+
resize(unsigned(signalMap(10)),13)+
resize(unsigned(signalMap(11)),13)+
resize(unsigned(signalMap(12)),13)+
resize(unsigned(signalMap(13)),13)+
resize(unsigned(signalMap(14)),13)+
resize(unsigned(signalMap(15)),13)+
resize(unsigned(signalMap(16)),13)+
resize(unsigned(signalMap(17)),13)+
resize(unsigned(signalMap(18)),13)+
resize(unsigned(signalMap(19)),13)+
resize(unsigned(signalMap(20)),13)+
resize(unsigned(signalMap(21)),13)+
resize(unsigned(signalMap(22)),13)+
resize(unsigned(signalMap(23)),13)+
resize(unsigned(signalMap(24)),13)+
resize(unsigned(signalMap(25)),13)+
resize(unsigned(signalMap(26)),13)+
resize(unsigned(signalMap(27)),13)+
resize(unsigned(signalMap(28)),13)+
resize(unsigned(signalMap(29)),13)+
resize(unsigned(signalMap(30)),13)+
resize(unsigned(signalMap(31)),13));
sig <= sigOut(12 downto 5);
end Behavioral;
|
architecture RTL of FIFO is
begin
-- These are passing
a <= b;
a <= when c = '0' else '1';
with z select
a <= b when z = "000",
c when z = "001";
-- Violation below
a<= b;
a <= when c = '0' else '1';
with z select
a<= b when z = "000",
c when z = "001";
end architecture RTL;
|
architecture RTL of FIFO is
attribute mark_debug of wr_en : signal is "true";
attribute mark_debug of almost_empty : signal is "true";
attribute mark_debug of full : signal is "true";
begin
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity datapath_vlg_sample_tst is
port(
clk : in vl_logic;
cost : in vl_logic_vector(7 downto 0);
enable_Change : in vl_logic;
enable_Total : in vl_logic;
reset : in vl_logic;
soda_Value : in vl_logic_vector(7 downto 0);
sampler_tx : out vl_logic
);
end datapath_vlg_sample_tst;
|
library ieee;
use ieee.std_logic_1164.all;
entity output01 is
port (i : std_logic;
o : out std_logic_vector (1 downto 0));
end output01;
architecture behav of output01 is
begin
o (0) <= i;
o (1) <= not i;
end behav;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5UKIMZVK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(17 downto 0);
output : out std_logic_vector(16 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5UKIMZVK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 18 + 1 ,
width_inr=> 0,
width_outl=> 17,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(17 downto 0) => input,
xin(18) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5UKIMZVK is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(17 downto 0);
output : out std_logic_vector(16 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5UKIMZVK is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 18 + 1 ,
width_inr=> 0,
width_outl=> 17,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(17 downto 0) => input,
xin(18) => '0', yout => output
);
end architecture; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:29:19 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_nmsuppression_0_0 -prefix
-- system_vga_nmsuppression_0_0_ system_vga_nmsuppression_1_0_sim_netlist.vhdl
-- Design : system_vga_nmsuppression_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_nmsuppression_0_0_vga_nmsuppression is
port (
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
active : in STD_LOGIC;
clk : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
enable : in STD_LOGIC
);
end system_vga_nmsuppression_0_0_vga_nmsuppression;
architecture STRUCTURE of system_vga_nmsuppression_0_0_vga_nmsuppression is
signal \hessian_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_3\ : STD_LOGIC;
signal hessian_out2_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out2_carry_n_0 : STD_LOGIC;
signal hessian_out2_carry_n_1 : STD_LOGIC;
signal hessian_out2_carry_n_2 : STD_LOGIC;
signal hessian_out2_carry_n_3 : STD_LOGIC;
signal \hessian_out3_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_3\ : STD_LOGIC;
signal hessian_out3_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out3_carry_n_0 : STD_LOGIC;
signal hessian_out3_carry_n_1 : STD_LOGIC;
signal hessian_out3_carry_n_2 : STD_LOGIC;
signal hessian_out3_carry_n_3 : STD_LOGIC;
signal \hessian_out4_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_3\ : STD_LOGIC;
signal hessian_out4_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out4_carry_n_0 : STD_LOGIC;
signal hessian_out4_carry_n_1 : STD_LOGIC;
signal hessian_out4_carry_n_2 : STD_LOGIC;
signal hessian_out4_carry_n_3 : STD_LOGIC;
signal \hessian_out5_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_3\ : STD_LOGIC;
signal hessian_out5_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out5_carry_n_0 : STD_LOGIC;
signal hessian_out5_carry_n_1 : STD_LOGIC;
signal hessian_out5_carry_n_2 : STD_LOGIC;
signal hessian_out5_carry_n_3 : STD_LOGIC;
signal \hessian_out6_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_3\ : STD_LOGIC;
signal hessian_out6_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out6_carry_n_0 : STD_LOGIC;
signal hessian_out6_carry_n_1 : STD_LOGIC;
signal hessian_out6_carry_n_2 : STD_LOGIC;
signal hessian_out6_carry_n_3 : STD_LOGIC;
signal \hessian_out7_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_3\ : STD_LOGIC;
signal hessian_out7_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out7_carry_n_0 : STD_LOGIC;
signal hessian_out7_carry_n_1 : STD_LOGIC;
signal hessian_out7_carry_n_2 : STD_LOGIC;
signal hessian_out7_carry_n_3 : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_3\ : STD_LOGIC;
signal hessian_out8_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out8_carry_n_0 : STD_LOGIC;
signal hessian_out8_carry_n_1 : STD_LOGIC;
signal hessian_out8_carry_n_2 : STD_LOGIC;
signal hessian_out8_carry_n_3 : STD_LOGIC;
signal \hessian_out[31]_i_1_n_0\ : STD_LOGIC;
signal \hessian_out[31]_i_2_n_0\ : STD_LOGIC;
signal \hessian_reg[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[10]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[11]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[1]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[4][0]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][10]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][11]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][12]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][13]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][14]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][15]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][16]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][17]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][18]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][19]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][1]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][20]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][21]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][22]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][23]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][24]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][25]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][26]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][27]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][28]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][29]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][2]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][30]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][31]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][3]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][4]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][5]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][6]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][7]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][8]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][9]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[5]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[6]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[7]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[8]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[9]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 0 to 0 );
signal \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\ : STD_LOGIC;
signal \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal NLW_hessian_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out3_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out4_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out5_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out6_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out7_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out8_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute srl_bus_name : string;
attribute srl_bus_name of \hessian_reg[4][0]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name : string;
attribute srl_name of \hessian_reg[4][0]_srl3\ : label is "\U0/hessian_reg[4][0]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][10]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][10]_srl3\ : label is "\U0/hessian_reg[4][10]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][11]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][11]_srl3\ : label is "\U0/hessian_reg[4][11]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][12]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][12]_srl3\ : label is "\U0/hessian_reg[4][12]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][13]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][13]_srl3\ : label is "\U0/hessian_reg[4][13]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][14]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][14]_srl3\ : label is "\U0/hessian_reg[4][14]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][15]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][15]_srl3\ : label is "\U0/hessian_reg[4][15]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][16]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][16]_srl3\ : label is "\U0/hessian_reg[4][16]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][17]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][17]_srl3\ : label is "\U0/hessian_reg[4][17]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][18]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][18]_srl3\ : label is "\U0/hessian_reg[4][18]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][19]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][19]_srl3\ : label is "\U0/hessian_reg[4][19]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][1]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][1]_srl3\ : label is "\U0/hessian_reg[4][1]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][20]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][20]_srl3\ : label is "\U0/hessian_reg[4][20]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][21]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][21]_srl3\ : label is "\U0/hessian_reg[4][21]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][22]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][22]_srl3\ : label is "\U0/hessian_reg[4][22]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][23]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][23]_srl3\ : label is "\U0/hessian_reg[4][23]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][24]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][24]_srl3\ : label is "\U0/hessian_reg[4][24]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][25]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][25]_srl3\ : label is "\U0/hessian_reg[4][25]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][26]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][26]_srl3\ : label is "\U0/hessian_reg[4][26]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][27]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][27]_srl3\ : label is "\U0/hessian_reg[4][27]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][28]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][28]_srl3\ : label is "\U0/hessian_reg[4][28]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][29]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][29]_srl3\ : label is "\U0/hessian_reg[4][29]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][2]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][2]_srl3\ : label is "\U0/hessian_reg[4][2]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][30]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][30]_srl3\ : label is "\U0/hessian_reg[4][30]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][31]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][31]_srl3\ : label is "\U0/hessian_reg[4][31]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][3]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][3]_srl3\ : label is "\U0/hessian_reg[4][3]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][4]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][4]_srl3\ : label is "\U0/hessian_reg[4][4]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][5]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][5]_srl3\ : label is "\U0/hessian_reg[4][5]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][6]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][6]_srl3\ : label is "\U0/hessian_reg[4][6]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][7]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][7]_srl3\ : label is "\U0/hessian_reg[4][7]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][8]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][8]_srl3\ : label is "\U0/hessian_reg[4][8]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][9]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][9]_srl3\ : label is "\U0/hessian_reg[4][9]_srl3 ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \x_addr_out[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x_addr_out[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x_addr_out[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x_addr_out[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x_addr_out[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[9]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y_addr_out[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y_addr_out[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y_addr_out[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y_addr_out[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y_addr_out[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y_addr_out[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y_addr_out[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y_addr_out[9]_i_1\ : label is "soft_lutpair3";
begin
hessian_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out2_carry_n_0,
CO(2) => hessian_out2_carry_n_1,
CO(1) => hessian_out2_carry_n_2,
CO(0) => hessian_out2_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out2_carry_i_1_n_0,
DI(2) => hessian_out2_carry_i_2_n_0,
DI(1) => hessian_out2_carry_i_3_n_0,
DI(0) => hessian_out2_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out2_carry_i_5_n_0,
S(2) => hessian_out2_carry_i_6_n_0,
S(1) => hessian_out2_carry_i_7_n_0,
S(0) => hessian_out2_carry_i_8_n_0
);
\hessian_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out2_carry_n_0,
CO(3) => \hessian_out2_carry__0_n_0\,
CO(2) => \hessian_out2_carry__0_n_1\,
CO(1) => \hessian_out2_carry__0_n_2\,
CO(0) => \hessian_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__0_i_1_n_0\,
DI(2) => \hessian_out2_carry__0_i_2_n_0\,
DI(1) => \hessian_out2_carry__0_i_3_n_0\,
DI(0) => \hessian_out2_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__0_i_5_n_0\,
S(2) => \hessian_out2_carry__0_i_6_n_0\,
S(1) => \hessian_out2_carry__0_i_7_n_0\,
S(0) => \hessian_out2_carry__0_i_8_n_0\
);
\hessian_out2_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[11]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out2_carry__0_i_1_n_0\
);
\hessian_out2_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[11]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out2_carry__0_i_2_n_0\
);
\hessian_out2_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[11]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out2_carry__0_i_3_n_0\
);
\hessian_out2_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[11]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out2_carry__0_i_4_n_0\
);
\hessian_out2_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[11]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out2_carry__0_i_5_n_0\
);
\hessian_out2_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[11]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out2_carry__0_i_6_n_0\
);
\hessian_out2_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[11]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out2_carry__0_i_7_n_0\
);
\hessian_out2_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[11]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out2_carry__0_i_8_n_0\
);
\hessian_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out2_carry__0_n_0\,
CO(3) => \hessian_out2_carry__1_n_0\,
CO(2) => \hessian_out2_carry__1_n_1\,
CO(1) => \hessian_out2_carry__1_n_2\,
CO(0) => \hessian_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__1_i_1_n_0\,
DI(2) => \hessian_out2_carry__1_i_2_n_0\,
DI(1) => \hessian_out2_carry__1_i_3_n_0\,
DI(0) => \hessian_out2_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__1_i_5_n_0\,
S(2) => \hessian_out2_carry__1_i_6_n_0\,
S(1) => \hessian_out2_carry__1_i_7_n_0\,
S(0) => \hessian_out2_carry__1_i_8_n_0\
);
\hessian_out2_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[11]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out2_carry__1_i_1_n_0\
);
\hessian_out2_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[11]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out2_carry__1_i_2_n_0\
);
\hessian_out2_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[11]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out2_carry__1_i_3_n_0\
);
\hessian_out2_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[11]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out2_carry__1_i_4_n_0\
);
\hessian_out2_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[11]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out2_carry__1_i_5_n_0\
);
\hessian_out2_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[11]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out2_carry__1_i_6_n_0\
);
\hessian_out2_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[11]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out2_carry__1_i_7_n_0\
);
\hessian_out2_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[11]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out2_carry__1_i_8_n_0\
);
\hessian_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out2_carry__1_n_0\,
CO(3) => \hessian_out2_carry__2_n_0\,
CO(2) => \hessian_out2_carry__2_n_1\,
CO(1) => \hessian_out2_carry__2_n_2\,
CO(0) => \hessian_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__2_i_1_n_0\,
DI(2) => \hessian_out2_carry__2_i_2_n_0\,
DI(1) => \hessian_out2_carry__2_i_3_n_0\,
DI(0) => \hessian_out2_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__2_i_5_n_0\,
S(2) => \hessian_out2_carry__2_i_6_n_0\,
S(1) => \hessian_out2_carry__2_i_7_n_0\,
S(0) => \hessian_out2_carry__2_i_8_n_0\
);
\hessian_out2_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[11]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out2_carry__2_i_1_n_0\
);
\hessian_out2_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[11]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out2_carry__2_i_2_n_0\
);
\hessian_out2_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[11]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out2_carry__2_i_3_n_0\
);
\hessian_out2_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[11]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out2_carry__2_i_4_n_0\
);
\hessian_out2_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[11]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out2_carry__2_i_5_n_0\
);
\hessian_out2_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[11]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out2_carry__2_i_6_n_0\
);
\hessian_out2_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[11]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out2_carry__2_i_7_n_0\
);
\hessian_out2_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[11]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out2_carry__2_i_8_n_0\
);
hessian_out2_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[11]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out2_carry_i_1_n_0
);
hessian_out2_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[11]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out2_carry_i_2_n_0
);
hessian_out2_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[11]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out2_carry_i_3_n_0
);
hessian_out2_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[11]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out2_carry_i_4_n_0
);
hessian_out2_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[11]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out2_carry_i_5_n_0
);
hessian_out2_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[11]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out2_carry_i_6_n_0
);
hessian_out2_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[11]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out2_carry_i_7_n_0
);
hessian_out2_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[11]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out2_carry_i_8_n_0
);
hessian_out3_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out3_carry_n_0,
CO(2) => hessian_out3_carry_n_1,
CO(1) => hessian_out3_carry_n_2,
CO(0) => hessian_out3_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out3_carry_i_1_n_0,
DI(2) => hessian_out3_carry_i_2_n_0,
DI(1) => hessian_out3_carry_i_3_n_0,
DI(0) => hessian_out3_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out3_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out3_carry_i_5_n_0,
S(2) => hessian_out3_carry_i_6_n_0,
S(1) => hessian_out3_carry_i_7_n_0,
S(0) => hessian_out3_carry_i_8_n_0
);
\hessian_out3_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out3_carry_n_0,
CO(3) => \hessian_out3_carry__0_n_0\,
CO(2) => \hessian_out3_carry__0_n_1\,
CO(1) => \hessian_out3_carry__0_n_2\,
CO(0) => \hessian_out3_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__0_i_1_n_0\,
DI(2) => \hessian_out3_carry__0_i_2_n_0\,
DI(1) => \hessian_out3_carry__0_i_3_n_0\,
DI(0) => \hessian_out3_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__0_i_5_n_0\,
S(2) => \hessian_out3_carry__0_i_6_n_0\,
S(1) => \hessian_out3_carry__0_i_7_n_0\,
S(0) => \hessian_out3_carry__0_i_8_n_0\
);
\hessian_out3_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[10]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out3_carry__0_i_1_n_0\
);
\hessian_out3_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[10]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out3_carry__0_i_2_n_0\
);
\hessian_out3_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[10]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out3_carry__0_i_3_n_0\
);
\hessian_out3_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[10]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out3_carry__0_i_4_n_0\
);
\hessian_out3_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[10]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out3_carry__0_i_5_n_0\
);
\hessian_out3_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[10]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out3_carry__0_i_6_n_0\
);
\hessian_out3_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[10]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out3_carry__0_i_7_n_0\
);
\hessian_out3_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[10]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out3_carry__0_i_8_n_0\
);
\hessian_out3_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out3_carry__0_n_0\,
CO(3) => \hessian_out3_carry__1_n_0\,
CO(2) => \hessian_out3_carry__1_n_1\,
CO(1) => \hessian_out3_carry__1_n_2\,
CO(0) => \hessian_out3_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__1_i_1_n_0\,
DI(2) => \hessian_out3_carry__1_i_2_n_0\,
DI(1) => \hessian_out3_carry__1_i_3_n_0\,
DI(0) => \hessian_out3_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__1_i_5_n_0\,
S(2) => \hessian_out3_carry__1_i_6_n_0\,
S(1) => \hessian_out3_carry__1_i_7_n_0\,
S(0) => \hessian_out3_carry__1_i_8_n_0\
);
\hessian_out3_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[10]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out3_carry__1_i_1_n_0\
);
\hessian_out3_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[10]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out3_carry__1_i_2_n_0\
);
\hessian_out3_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[10]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out3_carry__1_i_3_n_0\
);
\hessian_out3_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[10]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out3_carry__1_i_4_n_0\
);
\hessian_out3_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[10]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out3_carry__1_i_5_n_0\
);
\hessian_out3_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[10]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out3_carry__1_i_6_n_0\
);
\hessian_out3_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[10]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out3_carry__1_i_7_n_0\
);
\hessian_out3_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[10]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out3_carry__1_i_8_n_0\
);
\hessian_out3_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out3_carry__1_n_0\,
CO(3) => \hessian_out3_carry__2_n_0\,
CO(2) => \hessian_out3_carry__2_n_1\,
CO(1) => \hessian_out3_carry__2_n_2\,
CO(0) => \hessian_out3_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__2_i_1_n_0\,
DI(2) => \hessian_out3_carry__2_i_2_n_0\,
DI(1) => \hessian_out3_carry__2_i_3_n_0\,
DI(0) => \hessian_out3_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__2_i_5_n_0\,
S(2) => \hessian_out3_carry__2_i_6_n_0\,
S(1) => \hessian_out3_carry__2_i_7_n_0\,
S(0) => \hessian_out3_carry__2_i_8_n_0\
);
\hessian_out3_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[10]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out3_carry__2_i_1_n_0\
);
\hessian_out3_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[10]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out3_carry__2_i_2_n_0\
);
\hessian_out3_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[10]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out3_carry__2_i_3_n_0\
);
\hessian_out3_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[10]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out3_carry__2_i_4_n_0\
);
\hessian_out3_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[10]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out3_carry__2_i_5_n_0\
);
\hessian_out3_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[10]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out3_carry__2_i_6_n_0\
);
\hessian_out3_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[10]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out3_carry__2_i_7_n_0\
);
\hessian_out3_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[10]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out3_carry__2_i_8_n_0\
);
hessian_out3_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[10]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out3_carry_i_1_n_0
);
hessian_out3_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[10]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out3_carry_i_2_n_0
);
hessian_out3_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[10]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out3_carry_i_3_n_0
);
hessian_out3_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[10]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out3_carry_i_4_n_0
);
hessian_out3_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[10]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out3_carry_i_5_n_0
);
hessian_out3_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[10]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out3_carry_i_6_n_0
);
hessian_out3_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[10]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out3_carry_i_7_n_0
);
hessian_out3_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[10]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out3_carry_i_8_n_0
);
hessian_out4_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out4_carry_n_0,
CO(2) => hessian_out4_carry_n_1,
CO(1) => hessian_out4_carry_n_2,
CO(0) => hessian_out4_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out4_carry_i_1_n_0,
DI(2) => hessian_out4_carry_i_2_n_0,
DI(1) => hessian_out4_carry_i_3_n_0,
DI(0) => hessian_out4_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out4_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out4_carry_i_5_n_0,
S(2) => hessian_out4_carry_i_6_n_0,
S(1) => hessian_out4_carry_i_7_n_0,
S(0) => hessian_out4_carry_i_8_n_0
);
\hessian_out4_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out4_carry_n_0,
CO(3) => \hessian_out4_carry__0_n_0\,
CO(2) => \hessian_out4_carry__0_n_1\,
CO(1) => \hessian_out4_carry__0_n_2\,
CO(0) => \hessian_out4_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__0_i_1_n_0\,
DI(2) => \hessian_out4_carry__0_i_2_n_0\,
DI(1) => \hessian_out4_carry__0_i_3_n_0\,
DI(0) => \hessian_out4_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__0_i_5_n_0\,
S(2) => \hessian_out4_carry__0_i_6_n_0\,
S(1) => \hessian_out4_carry__0_i_7_n_0\,
S(0) => \hessian_out4_carry__0_i_8_n_0\
);
\hessian_out4_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[9]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out4_carry__0_i_1_n_0\
);
\hessian_out4_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[9]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out4_carry__0_i_2_n_0\
);
\hessian_out4_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[9]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out4_carry__0_i_3_n_0\
);
\hessian_out4_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[9]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out4_carry__0_i_4_n_0\
);
\hessian_out4_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[9]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out4_carry__0_i_5_n_0\
);
\hessian_out4_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[9]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out4_carry__0_i_6_n_0\
);
\hessian_out4_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[9]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out4_carry__0_i_7_n_0\
);
\hessian_out4_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[9]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out4_carry__0_i_8_n_0\
);
\hessian_out4_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out4_carry__0_n_0\,
CO(3) => \hessian_out4_carry__1_n_0\,
CO(2) => \hessian_out4_carry__1_n_1\,
CO(1) => \hessian_out4_carry__1_n_2\,
CO(0) => \hessian_out4_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__1_i_1_n_0\,
DI(2) => \hessian_out4_carry__1_i_2_n_0\,
DI(1) => \hessian_out4_carry__1_i_3_n_0\,
DI(0) => \hessian_out4_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__1_i_5_n_0\,
S(2) => \hessian_out4_carry__1_i_6_n_0\,
S(1) => \hessian_out4_carry__1_i_7_n_0\,
S(0) => \hessian_out4_carry__1_i_8_n_0\
);
\hessian_out4_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[9]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out4_carry__1_i_1_n_0\
);
\hessian_out4_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[9]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out4_carry__1_i_2_n_0\
);
\hessian_out4_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[9]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out4_carry__1_i_3_n_0\
);
\hessian_out4_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[9]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out4_carry__1_i_4_n_0\
);
\hessian_out4_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[9]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out4_carry__1_i_5_n_0\
);
\hessian_out4_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[9]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out4_carry__1_i_6_n_0\
);
\hessian_out4_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[9]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out4_carry__1_i_7_n_0\
);
\hessian_out4_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[9]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out4_carry__1_i_8_n_0\
);
\hessian_out4_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out4_carry__1_n_0\,
CO(3) => \hessian_out4_carry__2_n_0\,
CO(2) => \hessian_out4_carry__2_n_1\,
CO(1) => \hessian_out4_carry__2_n_2\,
CO(0) => \hessian_out4_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__2_i_1_n_0\,
DI(2) => \hessian_out4_carry__2_i_2_n_0\,
DI(1) => \hessian_out4_carry__2_i_3_n_0\,
DI(0) => \hessian_out4_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__2_i_5_n_0\,
S(2) => \hessian_out4_carry__2_i_6_n_0\,
S(1) => \hessian_out4_carry__2_i_7_n_0\,
S(0) => \hessian_out4_carry__2_i_8_n_0\
);
\hessian_out4_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[9]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out4_carry__2_i_1_n_0\
);
\hessian_out4_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[9]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out4_carry__2_i_2_n_0\
);
\hessian_out4_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[9]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out4_carry__2_i_3_n_0\
);
\hessian_out4_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[9]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out4_carry__2_i_4_n_0\
);
\hessian_out4_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[9]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out4_carry__2_i_5_n_0\
);
\hessian_out4_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[9]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out4_carry__2_i_6_n_0\
);
\hessian_out4_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[9]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out4_carry__2_i_7_n_0\
);
\hessian_out4_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[9]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out4_carry__2_i_8_n_0\
);
hessian_out4_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[9]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out4_carry_i_1_n_0
);
hessian_out4_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[9]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out4_carry_i_2_n_0
);
hessian_out4_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[9]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out4_carry_i_3_n_0
);
hessian_out4_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[9]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out4_carry_i_4_n_0
);
hessian_out4_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[9]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out4_carry_i_5_n_0
);
hessian_out4_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[9]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out4_carry_i_6_n_0
);
hessian_out4_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[9]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out4_carry_i_7_n_0
);
hessian_out4_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[9]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out4_carry_i_8_n_0
);
hessian_out5_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out5_carry_n_0,
CO(2) => hessian_out5_carry_n_1,
CO(1) => hessian_out5_carry_n_2,
CO(0) => hessian_out5_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out5_carry_i_1_n_0,
DI(2) => hessian_out5_carry_i_2_n_0,
DI(1) => hessian_out5_carry_i_3_n_0,
DI(0) => hessian_out5_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out5_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out5_carry_i_5_n_0,
S(2) => hessian_out5_carry_i_6_n_0,
S(1) => hessian_out5_carry_i_7_n_0,
S(0) => hessian_out5_carry_i_8_n_0
);
\hessian_out5_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out5_carry_n_0,
CO(3) => \hessian_out5_carry__0_n_0\,
CO(2) => \hessian_out5_carry__0_n_1\,
CO(1) => \hessian_out5_carry__0_n_2\,
CO(0) => \hessian_out5_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__0_i_1_n_0\,
DI(2) => \hessian_out5_carry__0_i_2_n_0\,
DI(1) => \hessian_out5_carry__0_i_3_n_0\,
DI(0) => \hessian_out5_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__0_i_5_n_0\,
S(2) => \hessian_out5_carry__0_i_6_n_0\,
S(1) => \hessian_out5_carry__0_i_7_n_0\,
S(0) => \hessian_out5_carry__0_i_8_n_0\
);
\hessian_out5_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[7]\(14),
I3 => \hessian_reg[7]\(15),
O => \hessian_out5_carry__0_i_1_n_0\
);
\hessian_out5_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[7]\(12),
I3 => \hessian_reg[7]\(13),
O => \hessian_out5_carry__0_i_2_n_0\
);
\hessian_out5_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[7]\(10),
I3 => \hessian_reg[7]\(11),
O => \hessian_out5_carry__0_i_3_n_0\
);
\hessian_out5_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[7]\(8),
I3 => \hessian_reg[7]\(9),
O => \hessian_out5_carry__0_i_4_n_0\
);
\hessian_out5_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[7]\(14),
I3 => \hessian_reg[7]\(15),
O => \hessian_out5_carry__0_i_5_n_0\
);
\hessian_out5_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[7]\(12),
I3 => \hessian_reg[7]\(13),
O => \hessian_out5_carry__0_i_6_n_0\
);
\hessian_out5_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[7]\(10),
I3 => \hessian_reg[7]\(11),
O => \hessian_out5_carry__0_i_7_n_0\
);
\hessian_out5_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[7]\(8),
I3 => \hessian_reg[7]\(9),
O => \hessian_out5_carry__0_i_8_n_0\
);
\hessian_out5_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out5_carry__0_n_0\,
CO(3) => \hessian_out5_carry__1_n_0\,
CO(2) => \hessian_out5_carry__1_n_1\,
CO(1) => \hessian_out5_carry__1_n_2\,
CO(0) => \hessian_out5_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__1_i_1_n_0\,
DI(2) => \hessian_out5_carry__1_i_2_n_0\,
DI(1) => \hessian_out5_carry__1_i_3_n_0\,
DI(0) => \hessian_out5_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__1_i_5_n_0\,
S(2) => \hessian_out5_carry__1_i_6_n_0\,
S(1) => \hessian_out5_carry__1_i_7_n_0\,
S(0) => \hessian_out5_carry__1_i_8_n_0\
);
\hessian_out5_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[7]\(22),
I3 => \hessian_reg[7]\(23),
O => \hessian_out5_carry__1_i_1_n_0\
);
\hessian_out5_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[7]\(20),
I3 => \hessian_reg[7]\(21),
O => \hessian_out5_carry__1_i_2_n_0\
);
\hessian_out5_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[7]\(18),
I3 => \hessian_reg[7]\(19),
O => \hessian_out5_carry__1_i_3_n_0\
);
\hessian_out5_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[7]\(16),
I3 => \hessian_reg[7]\(17),
O => \hessian_out5_carry__1_i_4_n_0\
);
\hessian_out5_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[7]\(22),
I3 => \hessian_reg[7]\(23),
O => \hessian_out5_carry__1_i_5_n_0\
);
\hessian_out5_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[7]\(20),
I3 => \hessian_reg[7]\(21),
O => \hessian_out5_carry__1_i_6_n_0\
);
\hessian_out5_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[7]\(18),
I3 => \hessian_reg[7]\(19),
O => \hessian_out5_carry__1_i_7_n_0\
);
\hessian_out5_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[7]\(16),
I3 => \hessian_reg[7]\(17),
O => \hessian_out5_carry__1_i_8_n_0\
);
\hessian_out5_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out5_carry__1_n_0\,
CO(3) => \hessian_out5_carry__2_n_0\,
CO(2) => \hessian_out5_carry__2_n_1\,
CO(1) => \hessian_out5_carry__2_n_2\,
CO(0) => \hessian_out5_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__2_i_1_n_0\,
DI(2) => \hessian_out5_carry__2_i_2_n_0\,
DI(1) => \hessian_out5_carry__2_i_3_n_0\,
DI(0) => \hessian_out5_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__2_i_5_n_0\,
S(2) => \hessian_out5_carry__2_i_6_n_0\,
S(1) => \hessian_out5_carry__2_i_7_n_0\,
S(0) => \hessian_out5_carry__2_i_8_n_0\
);
\hessian_out5_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[7]\(30),
I3 => \hessian_reg[7]\(31),
O => \hessian_out5_carry__2_i_1_n_0\
);
\hessian_out5_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[7]\(28),
I3 => \hessian_reg[7]\(29),
O => \hessian_out5_carry__2_i_2_n_0\
);
\hessian_out5_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[7]\(26),
I3 => \hessian_reg[7]\(27),
O => \hessian_out5_carry__2_i_3_n_0\
);
\hessian_out5_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[7]\(24),
I3 => \hessian_reg[7]\(25),
O => \hessian_out5_carry__2_i_4_n_0\
);
\hessian_out5_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[7]\(30),
I3 => \hessian_reg[7]\(31),
O => \hessian_out5_carry__2_i_5_n_0\
);
\hessian_out5_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[7]\(28),
I3 => \hessian_reg[7]\(29),
O => \hessian_out5_carry__2_i_6_n_0\
);
\hessian_out5_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[7]\(26),
I3 => \hessian_reg[7]\(27),
O => \hessian_out5_carry__2_i_7_n_0\
);
\hessian_out5_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[7]\(24),
I3 => \hessian_reg[7]\(25),
O => \hessian_out5_carry__2_i_8_n_0\
);
hessian_out5_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[7]\(6),
I3 => \hessian_reg[7]\(7),
O => hessian_out5_carry_i_1_n_0
);
hessian_out5_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[7]\(4),
I3 => \hessian_reg[7]\(5),
O => hessian_out5_carry_i_2_n_0
);
hessian_out5_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[7]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[7]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out5_carry_i_3_n_0
);
hessian_out5_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[7]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[7]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out5_carry_i_4_n_0
);
hessian_out5_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[7]\(6),
I3 => \hessian_reg[7]\(7),
O => hessian_out5_carry_i_5_n_0
);
hessian_out5_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[7]\(4),
I3 => \hessian_reg[7]\(5),
O => hessian_out5_carry_i_6_n_0
);
hessian_out5_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[7]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[7]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out5_carry_i_7_n_0
);
hessian_out5_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[7]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[7]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out5_carry_i_8_n_0
);
hessian_out6_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out6_carry_n_0,
CO(2) => hessian_out6_carry_n_1,
CO(1) => hessian_out6_carry_n_2,
CO(0) => hessian_out6_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out6_carry_i_1_n_0,
DI(2) => hessian_out6_carry_i_2_n_0,
DI(1) => hessian_out6_carry_i_3_n_0,
DI(0) => hessian_out6_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out6_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out6_carry_i_5_n_0,
S(2) => hessian_out6_carry_i_6_n_0,
S(1) => hessian_out6_carry_i_7_n_0,
S(0) => hessian_out6_carry_i_8_n_0
);
\hessian_out6_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out6_carry_n_0,
CO(3) => \hessian_out6_carry__0_n_0\,
CO(2) => \hessian_out6_carry__0_n_1\,
CO(1) => \hessian_out6_carry__0_n_2\,
CO(0) => \hessian_out6_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__0_i_1_n_0\,
DI(2) => \hessian_out6_carry__0_i_2_n_0\,
DI(1) => \hessian_out6_carry__0_i_3_n_0\,
DI(0) => \hessian_out6_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__0_i_5_n_0\,
S(2) => \hessian_out6_carry__0_i_6_n_0\,
S(1) => \hessian_out6_carry__0_i_7_n_0\,
S(0) => \hessian_out6_carry__0_i_8_n_0\
);
\hessian_out6_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[5]\(14),
I3 => \hessian_reg[5]\(15),
O => \hessian_out6_carry__0_i_1_n_0\
);
\hessian_out6_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[5]\(12),
I3 => \hessian_reg[5]\(13),
O => \hessian_out6_carry__0_i_2_n_0\
);
\hessian_out6_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[5]\(10),
I3 => \hessian_reg[5]\(11),
O => \hessian_out6_carry__0_i_3_n_0\
);
\hessian_out6_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[5]\(8),
I3 => \hessian_reg[5]\(9),
O => \hessian_out6_carry__0_i_4_n_0\
);
\hessian_out6_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[5]\(14),
I3 => \hessian_reg[5]\(15),
O => \hessian_out6_carry__0_i_5_n_0\
);
\hessian_out6_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[5]\(12),
I3 => \hessian_reg[5]\(13),
O => \hessian_out6_carry__0_i_6_n_0\
);
\hessian_out6_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[5]\(10),
I3 => \hessian_reg[5]\(11),
O => \hessian_out6_carry__0_i_7_n_0\
);
\hessian_out6_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[5]\(8),
I3 => \hessian_reg[5]\(9),
O => \hessian_out6_carry__0_i_8_n_0\
);
\hessian_out6_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out6_carry__0_n_0\,
CO(3) => \hessian_out6_carry__1_n_0\,
CO(2) => \hessian_out6_carry__1_n_1\,
CO(1) => \hessian_out6_carry__1_n_2\,
CO(0) => \hessian_out6_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__1_i_1_n_0\,
DI(2) => \hessian_out6_carry__1_i_2_n_0\,
DI(1) => \hessian_out6_carry__1_i_3_n_0\,
DI(0) => \hessian_out6_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__1_i_5_n_0\,
S(2) => \hessian_out6_carry__1_i_6_n_0\,
S(1) => \hessian_out6_carry__1_i_7_n_0\,
S(0) => \hessian_out6_carry__1_i_8_n_0\
);
\hessian_out6_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[5]\(22),
I3 => \hessian_reg[5]\(23),
O => \hessian_out6_carry__1_i_1_n_0\
);
\hessian_out6_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[5]\(20),
I3 => \hessian_reg[5]\(21),
O => \hessian_out6_carry__1_i_2_n_0\
);
\hessian_out6_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[5]\(18),
I3 => \hessian_reg[5]\(19),
O => \hessian_out6_carry__1_i_3_n_0\
);
\hessian_out6_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[5]\(16),
I3 => \hessian_reg[5]\(17),
O => \hessian_out6_carry__1_i_4_n_0\
);
\hessian_out6_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[5]\(22),
I3 => \hessian_reg[5]\(23),
O => \hessian_out6_carry__1_i_5_n_0\
);
\hessian_out6_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[5]\(20),
I3 => \hessian_reg[5]\(21),
O => \hessian_out6_carry__1_i_6_n_0\
);
\hessian_out6_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[5]\(18),
I3 => \hessian_reg[5]\(19),
O => \hessian_out6_carry__1_i_7_n_0\
);
\hessian_out6_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[5]\(16),
I3 => \hessian_reg[5]\(17),
O => \hessian_out6_carry__1_i_8_n_0\
);
\hessian_out6_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out6_carry__1_n_0\,
CO(3) => \hessian_out6_carry__2_n_0\,
CO(2) => \hessian_out6_carry__2_n_1\,
CO(1) => \hessian_out6_carry__2_n_2\,
CO(0) => \hessian_out6_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__2_i_1_n_0\,
DI(2) => \hessian_out6_carry__2_i_2_n_0\,
DI(1) => \hessian_out6_carry__2_i_3_n_0\,
DI(0) => \hessian_out6_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__2_i_5_n_0\,
S(2) => \hessian_out6_carry__2_i_6_n_0\,
S(1) => \hessian_out6_carry__2_i_7_n_0\,
S(0) => \hessian_out6_carry__2_i_8_n_0\
);
\hessian_out6_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[5]\(30),
I3 => \hessian_reg[5]\(31),
O => \hessian_out6_carry__2_i_1_n_0\
);
\hessian_out6_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[5]\(28),
I3 => \hessian_reg[5]\(29),
O => \hessian_out6_carry__2_i_2_n_0\
);
\hessian_out6_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[5]\(26),
I3 => \hessian_reg[5]\(27),
O => \hessian_out6_carry__2_i_3_n_0\
);
\hessian_out6_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[5]\(24),
I3 => \hessian_reg[5]\(25),
O => \hessian_out6_carry__2_i_4_n_0\
);
\hessian_out6_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[5]\(30),
I3 => \hessian_reg[5]\(31),
O => \hessian_out6_carry__2_i_5_n_0\
);
\hessian_out6_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[5]\(28),
I3 => \hessian_reg[5]\(29),
O => \hessian_out6_carry__2_i_6_n_0\
);
\hessian_out6_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[5]\(26),
I3 => \hessian_reg[5]\(27),
O => \hessian_out6_carry__2_i_7_n_0\
);
\hessian_out6_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[5]\(24),
I3 => \hessian_reg[5]\(25),
O => \hessian_out6_carry__2_i_8_n_0\
);
hessian_out6_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[5]\(6),
I3 => \hessian_reg[5]\(7),
O => hessian_out6_carry_i_1_n_0
);
hessian_out6_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[5]\(4),
I3 => \hessian_reg[5]\(5),
O => hessian_out6_carry_i_2_n_0
);
hessian_out6_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[5]\(2),
I3 => \hessian_reg[5]\(3),
O => hessian_out6_carry_i_3_n_0
);
hessian_out6_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[5]\(0),
I3 => \hessian_reg[5]\(1),
O => hessian_out6_carry_i_4_n_0
);
hessian_out6_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[5]\(6),
I3 => \hessian_reg[5]\(7),
O => hessian_out6_carry_i_5_n_0
);
hessian_out6_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[5]\(4),
I3 => \hessian_reg[5]\(5),
O => hessian_out6_carry_i_6_n_0
);
hessian_out6_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[5]\(2),
I3 => \hessian_reg[5]\(3),
O => hessian_out6_carry_i_7_n_0
);
hessian_out6_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[5]\(0),
I3 => \hessian_reg[5]\(1),
O => hessian_out6_carry_i_8_n_0
);
hessian_out7_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out7_carry_n_0,
CO(2) => hessian_out7_carry_n_1,
CO(1) => hessian_out7_carry_n_2,
CO(0) => hessian_out7_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out7_carry_i_1_n_0,
DI(2) => hessian_out7_carry_i_2_n_0,
DI(1) => hessian_out7_carry_i_3_n_0,
DI(0) => hessian_out7_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out7_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out7_carry_i_5_n_0,
S(2) => hessian_out7_carry_i_6_n_0,
S(1) => hessian_out7_carry_i_7_n_0,
S(0) => hessian_out7_carry_i_8_n_0
);
\hessian_out7_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out7_carry_n_0,
CO(3) => \hessian_out7_carry__0_n_0\,
CO(2) => \hessian_out7_carry__0_n_1\,
CO(1) => \hessian_out7_carry__0_n_2\,
CO(0) => \hessian_out7_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__0_i_1_n_0\,
DI(2) => \hessian_out7_carry__0_i_2_n_0\,
DI(1) => \hessian_out7_carry__0_i_3_n_0\,
DI(0) => \hessian_out7_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__0_i_5_n_0\,
S(2) => \hessian_out7_carry__0_i_6_n_0\,
S(1) => \hessian_out7_carry__0_i_7_n_0\,
S(0) => \hessian_out7_carry__0_i_8_n_0\
);
\hessian_out7_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[1]\(14),
I3 => \hessian_reg[1]\(15),
O => \hessian_out7_carry__0_i_1_n_0\
);
\hessian_out7_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[1]\(12),
I3 => \hessian_reg[1]\(13),
O => \hessian_out7_carry__0_i_2_n_0\
);
\hessian_out7_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[1]\(10),
I3 => \hessian_reg[1]\(11),
O => \hessian_out7_carry__0_i_3_n_0\
);
\hessian_out7_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[1]\(8),
I3 => \hessian_reg[1]\(9),
O => \hessian_out7_carry__0_i_4_n_0\
);
\hessian_out7_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[1]\(14),
I3 => \hessian_reg[1]\(15),
O => \hessian_out7_carry__0_i_5_n_0\
);
\hessian_out7_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[1]\(12),
I3 => \hessian_reg[1]\(13),
O => \hessian_out7_carry__0_i_6_n_0\
);
\hessian_out7_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[1]\(10),
I3 => \hessian_reg[1]\(11),
O => \hessian_out7_carry__0_i_7_n_0\
);
\hessian_out7_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[1]\(8),
I3 => \hessian_reg[1]\(9),
O => \hessian_out7_carry__0_i_8_n_0\
);
\hessian_out7_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out7_carry__0_n_0\,
CO(3) => \hessian_out7_carry__1_n_0\,
CO(2) => \hessian_out7_carry__1_n_1\,
CO(1) => \hessian_out7_carry__1_n_2\,
CO(0) => \hessian_out7_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__1_i_1_n_0\,
DI(2) => \hessian_out7_carry__1_i_2_n_0\,
DI(1) => \hessian_out7_carry__1_i_3_n_0\,
DI(0) => \hessian_out7_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__1_i_5_n_0\,
S(2) => \hessian_out7_carry__1_i_6_n_0\,
S(1) => \hessian_out7_carry__1_i_7_n_0\,
S(0) => \hessian_out7_carry__1_i_8_n_0\
);
\hessian_out7_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[1]\(22),
I3 => \hessian_reg[1]\(23),
O => \hessian_out7_carry__1_i_1_n_0\
);
\hessian_out7_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[1]\(20),
I3 => \hessian_reg[1]\(21),
O => \hessian_out7_carry__1_i_2_n_0\
);
\hessian_out7_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[1]\(18),
I3 => \hessian_reg[1]\(19),
O => \hessian_out7_carry__1_i_3_n_0\
);
\hessian_out7_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[1]\(16),
I3 => \hessian_reg[1]\(17),
O => \hessian_out7_carry__1_i_4_n_0\
);
\hessian_out7_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[1]\(22),
I3 => \hessian_reg[1]\(23),
O => \hessian_out7_carry__1_i_5_n_0\
);
\hessian_out7_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[1]\(20),
I3 => \hessian_reg[1]\(21),
O => \hessian_out7_carry__1_i_6_n_0\
);
\hessian_out7_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[1]\(18),
I3 => \hessian_reg[1]\(19),
O => \hessian_out7_carry__1_i_7_n_0\
);
\hessian_out7_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[1]\(16),
I3 => \hessian_reg[1]\(17),
O => \hessian_out7_carry__1_i_8_n_0\
);
\hessian_out7_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out7_carry__1_n_0\,
CO(3) => \hessian_out7_carry__2_n_0\,
CO(2) => \hessian_out7_carry__2_n_1\,
CO(1) => \hessian_out7_carry__2_n_2\,
CO(0) => \hessian_out7_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__2_i_1_n_0\,
DI(2) => \hessian_out7_carry__2_i_2_n_0\,
DI(1) => \hessian_out7_carry__2_i_3_n_0\,
DI(0) => \hessian_out7_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__2_i_5_n_0\,
S(2) => \hessian_out7_carry__2_i_6_n_0\,
S(1) => \hessian_out7_carry__2_i_7_n_0\,
S(0) => \hessian_out7_carry__2_i_8_n_0\
);
\hessian_out7_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[1]\(30),
I3 => \hessian_reg[1]\(31),
O => \hessian_out7_carry__2_i_1_n_0\
);
\hessian_out7_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[1]\(28),
I3 => \hessian_reg[1]\(29),
O => \hessian_out7_carry__2_i_2_n_0\
);
\hessian_out7_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[1]\(26),
I3 => \hessian_reg[1]\(27),
O => \hessian_out7_carry__2_i_3_n_0\
);
\hessian_out7_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[1]\(24),
I3 => \hessian_reg[1]\(25),
O => \hessian_out7_carry__2_i_4_n_0\
);
\hessian_out7_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[1]\(30),
I2 => \hessian_reg[6]\(30),
I3 => \hessian_reg[1]\(31),
O => \hessian_out7_carry__2_i_5_n_0\
);
\hessian_out7_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[1]\(28),
I3 => \hessian_reg[1]\(29),
O => \hessian_out7_carry__2_i_6_n_0\
);
\hessian_out7_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[1]\(26),
I3 => \hessian_reg[1]\(27),
O => \hessian_out7_carry__2_i_7_n_0\
);
\hessian_out7_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[1]\(24),
I3 => \hessian_reg[1]\(25),
O => \hessian_out7_carry__2_i_8_n_0\
);
hessian_out7_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[1]\(6),
I3 => \hessian_reg[1]\(7),
O => hessian_out7_carry_i_1_n_0
);
hessian_out7_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[1]\(4),
I3 => \hessian_reg[1]\(5),
O => hessian_out7_carry_i_2_n_0
);
hessian_out7_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[1]\(2),
I3 => \hessian_reg[1]\(3),
O => hessian_out7_carry_i_3_n_0
);
hessian_out7_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[1]\(0),
I3 => \hessian_reg[1]\(1),
O => hessian_out7_carry_i_4_n_0
);
hessian_out7_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[1]\(6),
I3 => \hessian_reg[1]\(7),
O => hessian_out7_carry_i_5_n_0
);
hessian_out7_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[1]\(4),
I3 => \hessian_reg[1]\(5),
O => hessian_out7_carry_i_6_n_0
);
hessian_out7_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[1]\(2),
I3 => \hessian_reg[1]\(3),
O => hessian_out7_carry_i_7_n_0
);
hessian_out7_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[1]\(0),
I3 => \hessian_reg[1]\(1),
O => hessian_out7_carry_i_8_n_0
);
\hessian_out8__15_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hessian_out8__15_carry_n_0\,
CO(2) => \hessian_out8__15_carry_n_1\,
CO(1) => \hessian_out8__15_carry_n_2\,
CO(0) => \hessian_out8__15_carry_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry_i_1_n_0\,
DI(2) => \hessian_out8__15_carry_i_2_n_0\,
DI(1) => \hessian_out8__15_carry_i_3_n_0\,
DI(0) => \hessian_out8__15_carry_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry_i_5_n_0\,
S(2) => \hessian_out8__15_carry_i_6_n_0\,
S(1) => \hessian_out8__15_carry_i_7_n_0\,
S(0) => \hessian_out8__15_carry_i_8_n_0\
);
\hessian_out8__15_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry_n_0\,
CO(3) => \hessian_out8__15_carry__0_n_0\,
CO(2) => \hessian_out8__15_carry__0_n_1\,
CO(1) => \hessian_out8__15_carry__0_n_2\,
CO(0) => \hessian_out8__15_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__0_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__0_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__0_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__0_i_5_n_0\,
S(2) => \hessian_out8__15_carry__0_i_6_n_0\,
S(1) => \hessian_out8__15_carry__0_i_7_n_0\,
S(0) => \hessian_out8__15_carry__0_i_8_n_0\
);
\hessian_out8__15_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(15),
I1 => \hessian_reg[6]\(14),
I2 => hessian_in(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out8__15_carry__0_i_1_n_0\
);
\hessian_out8__15_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(13),
I1 => \hessian_reg[6]\(12),
I2 => hessian_in(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out8__15_carry__0_i_2_n_0\
);
\hessian_out8__15_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(11),
I1 => \hessian_reg[6]\(10),
I2 => hessian_in(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out8__15_carry__0_i_3_n_0\
);
\hessian_out8__15_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(9),
I1 => \hessian_reg[6]\(8),
I2 => hessian_in(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out8__15_carry__0_i_4_n_0\
);
\hessian_out8__15_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(15),
I1 => \hessian_reg[6]\(14),
I2 => hessian_in(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out8__15_carry__0_i_5_n_0\
);
\hessian_out8__15_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(13),
I1 => \hessian_reg[6]\(12),
I2 => hessian_in(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out8__15_carry__0_i_6_n_0\
);
\hessian_out8__15_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(11),
I1 => \hessian_reg[6]\(10),
I2 => hessian_in(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out8__15_carry__0_i_7_n_0\
);
\hessian_out8__15_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(9),
I1 => \hessian_reg[6]\(8),
I2 => hessian_in(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out8__15_carry__0_i_8_n_0\
);
\hessian_out8__15_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry__0_n_0\,
CO(3) => \hessian_out8__15_carry__1_n_0\,
CO(2) => \hessian_out8__15_carry__1_n_1\,
CO(1) => \hessian_out8__15_carry__1_n_2\,
CO(0) => \hessian_out8__15_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__1_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__1_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__1_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__1_i_5_n_0\,
S(2) => \hessian_out8__15_carry__1_i_6_n_0\,
S(1) => \hessian_out8__15_carry__1_i_7_n_0\,
S(0) => \hessian_out8__15_carry__1_i_8_n_0\
);
\hessian_out8__15_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(23),
I1 => \hessian_reg[6]\(22),
I2 => hessian_in(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out8__15_carry__1_i_1_n_0\
);
\hessian_out8__15_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(21),
I1 => \hessian_reg[6]\(20),
I2 => hessian_in(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out8__15_carry__1_i_2_n_0\
);
\hessian_out8__15_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(19),
I1 => \hessian_reg[6]\(18),
I2 => hessian_in(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out8__15_carry__1_i_3_n_0\
);
\hessian_out8__15_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(17),
I1 => \hessian_reg[6]\(16),
I2 => hessian_in(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out8__15_carry__1_i_4_n_0\
);
\hessian_out8__15_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(23),
I1 => \hessian_reg[6]\(22),
I2 => hessian_in(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out8__15_carry__1_i_5_n_0\
);
\hessian_out8__15_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(21),
I1 => \hessian_reg[6]\(20),
I2 => hessian_in(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out8__15_carry__1_i_6_n_0\
);
\hessian_out8__15_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(19),
I1 => \hessian_reg[6]\(18),
I2 => hessian_in(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out8__15_carry__1_i_7_n_0\
);
\hessian_out8__15_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(17),
I1 => \hessian_reg[6]\(16),
I2 => hessian_in(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out8__15_carry__1_i_8_n_0\
);
\hessian_out8__15_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry__1_n_0\,
CO(3) => \hessian_out8__15_carry__2_n_0\,
CO(2) => \hessian_out8__15_carry__2_n_1\,
CO(1) => \hessian_out8__15_carry__2_n_2\,
CO(0) => \hessian_out8__15_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__2_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__2_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__2_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__2_i_5_n_0\,
S(2) => \hessian_out8__15_carry__2_i_6_n_0\,
S(1) => \hessian_out8__15_carry__2_i_7_n_0\,
S(0) => \hessian_out8__15_carry__2_i_8_n_0\
);
\hessian_out8__15_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(31),
I1 => \hessian_reg[6]\(30),
I2 => hessian_in(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out8__15_carry__2_i_1_n_0\
);
\hessian_out8__15_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(29),
I1 => \hessian_reg[6]\(28),
I2 => hessian_in(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out8__15_carry__2_i_2_n_0\
);
\hessian_out8__15_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(27),
I1 => \hessian_reg[6]\(26),
I2 => hessian_in(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out8__15_carry__2_i_3_n_0\
);
\hessian_out8__15_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(25),
I1 => \hessian_reg[6]\(24),
I2 => hessian_in(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out8__15_carry__2_i_4_n_0\
);
\hessian_out8__15_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(31),
I1 => \hessian_reg[6]\(30),
I2 => hessian_in(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out8__15_carry__2_i_5_n_0\
);
\hessian_out8__15_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(29),
I1 => \hessian_reg[6]\(28),
I2 => hessian_in(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out8__15_carry__2_i_6_n_0\
);
\hessian_out8__15_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(27),
I1 => \hessian_reg[6]\(26),
I2 => hessian_in(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out8__15_carry__2_i_7_n_0\
);
\hessian_out8__15_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(25),
I1 => \hessian_reg[6]\(24),
I2 => hessian_in(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out8__15_carry__2_i_8_n_0\
);
\hessian_out8__15_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(7),
I1 => \hessian_reg[6]\(6),
I2 => hessian_in(6),
I3 => \hessian_reg[6]\(7),
O => \hessian_out8__15_carry_i_1_n_0\
);
\hessian_out8__15_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(5),
I1 => \hessian_reg[6]\(4),
I2 => hessian_in(4),
I3 => \hessian_reg[6]\(5),
O => \hessian_out8__15_carry_i_2_n_0\
);
\hessian_out8__15_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(3),
I1 => \hessian_reg[6]\(2),
I2 => hessian_in(2),
I3 => \hessian_reg[6]\(3),
O => \hessian_out8__15_carry_i_3_n_0\
);
\hessian_out8__15_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(1),
I1 => \hessian_reg[6]\(0),
I2 => hessian_in(0),
I3 => \hessian_reg[6]\(1),
O => \hessian_out8__15_carry_i_4_n_0\
);
\hessian_out8__15_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(7),
I1 => \hessian_reg[6]\(6),
I2 => hessian_in(6),
I3 => \hessian_reg[6]\(7),
O => \hessian_out8__15_carry_i_5_n_0\
);
\hessian_out8__15_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(5),
I1 => \hessian_reg[6]\(4),
I2 => hessian_in(4),
I3 => \hessian_reg[6]\(5),
O => \hessian_out8__15_carry_i_6_n_0\
);
\hessian_out8__15_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(3),
I1 => \hessian_reg[6]\(2),
I2 => hessian_in(2),
I3 => \hessian_reg[6]\(3),
O => \hessian_out8__15_carry_i_7_n_0\
);
\hessian_out8__15_carry_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(1),
I1 => \hessian_reg[6]\(0),
I2 => hessian_in(0),
I3 => \hessian_reg[6]\(1),
O => \hessian_out8__15_carry_i_8_n_0\
);
hessian_out8_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out8_carry_n_0,
CO(2) => hessian_out8_carry_n_1,
CO(1) => hessian_out8_carry_n_2,
CO(0) => hessian_out8_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out8_carry_i_1_n_0,
DI(2) => hessian_out8_carry_i_2_n_0,
DI(1) => hessian_out8_carry_i_3_n_0,
DI(0) => hessian_out8_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out8_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out8_carry_i_5_n_0,
S(2) => hessian_out8_carry_i_6_n_0,
S(1) => hessian_out8_carry_i_7_n_0,
S(0) => hessian_out8_carry_i_8_n_0
);
\hessian_out8_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out8_carry_n_0,
CO(3) => \hessian_out8_carry__0_n_0\,
CO(2) => \hessian_out8_carry__0_n_1\,
CO(1) => \hessian_out8_carry__0_n_2\,
CO(0) => \hessian_out8_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__0_i_1_n_0\,
DI(2) => \hessian_out8_carry__0_i_2_n_0\,
DI(1) => \hessian_out8_carry__0_i_3_n_0\,
DI(0) => \hessian_out8_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__0_i_5_n_0\,
S(2) => \hessian_out8_carry__0_i_6_n_0\,
S(1) => \hessian_out8_carry__0_i_7_n_0\,
S(0) => \hessian_out8_carry__0_i_8_n_0\
);
\hessian_out8_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[0]\(14),
I3 => \hessian_reg[0]\(15),
O => \hessian_out8_carry__0_i_1_n_0\
);
\hessian_out8_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[0]\(12),
I3 => \hessian_reg[0]\(13),
O => \hessian_out8_carry__0_i_2_n_0\
);
\hessian_out8_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[0]\(10),
I3 => \hessian_reg[0]\(11),
O => \hessian_out8_carry__0_i_3_n_0\
);
\hessian_out8_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[0]\(8),
I3 => \hessian_reg[0]\(9),
O => \hessian_out8_carry__0_i_4_n_0\
);
\hessian_out8_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[0]\(14),
I2 => \hessian_reg[6]\(14),
I3 => \hessian_reg[0]\(15),
O => \hessian_out8_carry__0_i_5_n_0\
);
\hessian_out8_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[0]\(12),
I2 => \hessian_reg[6]\(12),
I3 => \hessian_reg[0]\(13),
O => \hessian_out8_carry__0_i_6_n_0\
);
\hessian_out8_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[0]\(10),
I2 => \hessian_reg[6]\(10),
I3 => \hessian_reg[0]\(11),
O => \hessian_out8_carry__0_i_7_n_0\
);
\hessian_out8_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[0]\(8),
I2 => \hessian_reg[6]\(8),
I3 => \hessian_reg[0]\(9),
O => \hessian_out8_carry__0_i_8_n_0\
);
\hessian_out8_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8_carry__0_n_0\,
CO(3) => \hessian_out8_carry__1_n_0\,
CO(2) => \hessian_out8_carry__1_n_1\,
CO(1) => \hessian_out8_carry__1_n_2\,
CO(0) => \hessian_out8_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__1_i_1_n_0\,
DI(2) => \hessian_out8_carry__1_i_2_n_0\,
DI(1) => \hessian_out8_carry__1_i_3_n_0\,
DI(0) => \hessian_out8_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__1_i_5_n_0\,
S(2) => \hessian_out8_carry__1_i_6_n_0\,
S(1) => \hessian_out8_carry__1_i_7_n_0\,
S(0) => \hessian_out8_carry__1_i_8_n_0\
);
\hessian_out8_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[0]\(22),
I3 => \hessian_reg[0]\(23),
O => \hessian_out8_carry__1_i_1_n_0\
);
\hessian_out8_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[0]\(20),
I3 => \hessian_reg[0]\(21),
O => \hessian_out8_carry__1_i_2_n_0\
);
\hessian_out8_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[0]\(18),
I3 => \hessian_reg[0]\(19),
O => \hessian_out8_carry__1_i_3_n_0\
);
\hessian_out8_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[0]\(16),
I3 => \hessian_reg[0]\(17),
O => \hessian_out8_carry__1_i_4_n_0\
);
\hessian_out8_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[0]\(22),
I2 => \hessian_reg[6]\(22),
I3 => \hessian_reg[0]\(23),
O => \hessian_out8_carry__1_i_5_n_0\
);
\hessian_out8_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[0]\(20),
I2 => \hessian_reg[6]\(20),
I3 => \hessian_reg[0]\(21),
O => \hessian_out8_carry__1_i_6_n_0\
);
\hessian_out8_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[0]\(18),
I2 => \hessian_reg[6]\(18),
I3 => \hessian_reg[0]\(19),
O => \hessian_out8_carry__1_i_7_n_0\
);
\hessian_out8_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[0]\(16),
I2 => \hessian_reg[6]\(16),
I3 => \hessian_reg[0]\(17),
O => \hessian_out8_carry__1_i_8_n_0\
);
\hessian_out8_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8_carry__1_n_0\,
CO(3) => \hessian_out8_carry__2_n_0\,
CO(2) => \hessian_out8_carry__2_n_1\,
CO(1) => \hessian_out8_carry__2_n_2\,
CO(0) => \hessian_out8_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__2_i_1_n_0\,
DI(2) => \hessian_out8_carry__2_i_2_n_0\,
DI(1) => \hessian_out8_carry__2_i_3_n_0\,
DI(0) => \hessian_out8_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__2_i_5_n_0\,
S(2) => \hessian_out8_carry__2_i_6_n_0\,
S(1) => \hessian_out8_carry__2_i_7_n_0\,
S(0) => \hessian_out8_carry__2_i_8_n_0\
);
\hessian_out8_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[0]\(30),
I3 => \hessian_reg[0]\(31),
O => \hessian_out8_carry__2_i_1_n_0\
);
\hessian_out8_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[0]\(28),
I3 => \hessian_reg[0]\(29),
O => \hessian_out8_carry__2_i_2_n_0\
);
\hessian_out8_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[0]\(26),
I3 => \hessian_reg[0]\(27),
O => \hessian_out8_carry__2_i_3_n_0\
);
\hessian_out8_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[0]\(24),
I3 => \hessian_reg[0]\(25),
O => \hessian_out8_carry__2_i_4_n_0\
);
\hessian_out8_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[0]\(30),
I2 => \hessian_reg[6]\(30),
I3 => \hessian_reg[0]\(31),
O => \hessian_out8_carry__2_i_5_n_0\
);
\hessian_out8_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[0]\(28),
I2 => \hessian_reg[6]\(28),
I3 => \hessian_reg[0]\(29),
O => \hessian_out8_carry__2_i_6_n_0\
);
\hessian_out8_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[0]\(26),
I2 => \hessian_reg[6]\(26),
I3 => \hessian_reg[0]\(27),
O => \hessian_out8_carry__2_i_7_n_0\
);
\hessian_out8_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[0]\(24),
I2 => \hessian_reg[6]\(24),
I3 => \hessian_reg[0]\(25),
O => \hessian_out8_carry__2_i_8_n_0\
);
hessian_out8_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[0]\(6),
I3 => \hessian_reg[0]\(7),
O => hessian_out8_carry_i_1_n_0
);
hessian_out8_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[0]\(4),
I3 => \hessian_reg[0]\(5),
O => hessian_out8_carry_i_2_n_0
);
hessian_out8_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[0]\(2),
I3 => \hessian_reg[0]\(3),
O => hessian_out8_carry_i_3_n_0
);
hessian_out8_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[0]\(0),
I3 => \hessian_reg[0]\(1),
O => hessian_out8_carry_i_4_n_0
);
hessian_out8_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[0]\(6),
I2 => \hessian_reg[6]\(6),
I3 => \hessian_reg[0]\(7),
O => hessian_out8_carry_i_5_n_0
);
hessian_out8_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[0]\(4),
I2 => \hessian_reg[6]\(4),
I3 => \hessian_reg[0]\(5),
O => hessian_out8_carry_i_6_n_0
);
hessian_out8_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[0]\(2),
I2 => \hessian_reg[6]\(2),
I3 => \hessian_reg[0]\(3),
O => hessian_out8_carry_i_7_n_0
);
hessian_out8_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[0]\(0),
I2 => \hessian_reg[6]\(0),
I3 => \hessian_reg[0]\(1),
O => hessian_out8_carry_i_8_n_0
);
\hessian_out[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80000"
)
port map (
I0 => active,
I1 => \hessian_out8__15_carry__2_n_0\,
I2 => \hessian_out[31]_i_2_n_0\,
I3 => \hessian_out2_carry__2_n_0\,
I4 => enable,
O => \hessian_out[31]_i_1_n_0\
);
\hessian_out[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \hessian_out3_carry__2_n_0\,
I1 => \hessian_out5_carry__2_n_0\,
I2 => \hessian_out8_carry__2_n_0\,
I3 => \hessian_out7_carry__2_n_0\,
I4 => \hessian_out6_carry__2_n_0\,
I5 => \hessian_out4_carry__2_n_0\,
O => \hessian_out[31]_i_2_n_0\
);
\hessian_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(0),
Q => hessian_out(0),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(10),
Q => hessian_out(10),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(11),
Q => hessian_out(11),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(12),
Q => hessian_out(12),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(13),
Q => hessian_out(13),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(14),
Q => hessian_out(14),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(15),
Q => hessian_out(15),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(16),
Q => hessian_out(16),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(17),
Q => hessian_out(17),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(18),
Q => hessian_out(18),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(19),
Q => hessian_out(19),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(1),
Q => hessian_out(1),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(20),
Q => hessian_out(20),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(21),
Q => hessian_out(21),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(22),
Q => hessian_out(22),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(23),
Q => hessian_out(23),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(24),
Q => hessian_out(24),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(25),
Q => hessian_out(25),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(26),
Q => hessian_out(26),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(27),
Q => hessian_out(27),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(28),
Q => hessian_out(28),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(29),
Q => hessian_out(29),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(2),
Q => hessian_out(2),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(30),
Q => hessian_out(30),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(31),
Q => hessian_out(31),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(3),
Q => hessian_out(3),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(4),
Q => hessian_out(4),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(5),
Q => hessian_out(5),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(6),
Q => hessian_out(6),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(7),
Q => hessian_out(7),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(8),
Q => hessian_out(8),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(9),
Q => hessian_out(9),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(0),
Q => \hessian_reg[0]\(0),
R => '0'
);
\hessian_reg[0][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(10),
Q => \hessian_reg[0]\(10),
R => '0'
);
\hessian_reg[0][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(11),
Q => \hessian_reg[0]\(11),
R => '0'
);
\hessian_reg[0][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(12),
Q => \hessian_reg[0]\(12),
R => '0'
);
\hessian_reg[0][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(13),
Q => \hessian_reg[0]\(13),
R => '0'
);
\hessian_reg[0][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(14),
Q => \hessian_reg[0]\(14),
R => '0'
);
\hessian_reg[0][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(15),
Q => \hessian_reg[0]\(15),
R => '0'
);
\hessian_reg[0][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(16),
Q => \hessian_reg[0]\(16),
R => '0'
);
\hessian_reg[0][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(17),
Q => \hessian_reg[0]\(17),
R => '0'
);
\hessian_reg[0][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(18),
Q => \hessian_reg[0]\(18),
R => '0'
);
\hessian_reg[0][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(19),
Q => \hessian_reg[0]\(19),
R => '0'
);
\hessian_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(1),
Q => \hessian_reg[0]\(1),
R => '0'
);
\hessian_reg[0][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(20),
Q => \hessian_reg[0]\(20),
R => '0'
);
\hessian_reg[0][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(21),
Q => \hessian_reg[0]\(21),
R => '0'
);
\hessian_reg[0][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(22),
Q => \hessian_reg[0]\(22),
R => '0'
);
\hessian_reg[0][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(23),
Q => \hessian_reg[0]\(23),
R => '0'
);
\hessian_reg[0][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(24),
Q => \hessian_reg[0]\(24),
R => '0'
);
\hessian_reg[0][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(25),
Q => \hessian_reg[0]\(25),
R => '0'
);
\hessian_reg[0][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(26),
Q => \hessian_reg[0]\(26),
R => '0'
);
\hessian_reg[0][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(27),
Q => \hessian_reg[0]\(27),
R => '0'
);
\hessian_reg[0][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(28),
Q => \hessian_reg[0]\(28),
R => '0'
);
\hessian_reg[0][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(29),
Q => \hessian_reg[0]\(29),
R => '0'
);
\hessian_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(2),
Q => \hessian_reg[0]\(2),
R => '0'
);
\hessian_reg[0][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(30),
Q => \hessian_reg[0]\(30),
R => '0'
);
\hessian_reg[0][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(31),
Q => \hessian_reg[0]\(31),
R => '0'
);
\hessian_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(3),
Q => \hessian_reg[0]\(3),
R => '0'
);
\hessian_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(4),
Q => \hessian_reg[0]\(4),
R => '0'
);
\hessian_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(5),
Q => \hessian_reg[0]\(5),
R => '0'
);
\hessian_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(6),
Q => \hessian_reg[0]\(6),
R => '0'
);
\hessian_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(7),
Q => \hessian_reg[0]\(7),
R => '0'
);
\hessian_reg[0][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(8),
Q => \hessian_reg[0]\(8),
R => '0'
);
\hessian_reg[0][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(9),
Q => \hessian_reg[0]\(9),
R => '0'
);
\hessian_reg[10][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(0),
Q => \hessian_reg[10]\(0),
R => '0'
);
\hessian_reg[10][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(10),
Q => \hessian_reg[10]\(10),
R => '0'
);
\hessian_reg[10][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(11),
Q => \hessian_reg[10]\(11),
R => '0'
);
\hessian_reg[10][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(12),
Q => \hessian_reg[10]\(12),
R => '0'
);
\hessian_reg[10][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(13),
Q => \hessian_reg[10]\(13),
R => '0'
);
\hessian_reg[10][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(14),
Q => \hessian_reg[10]\(14),
R => '0'
);
\hessian_reg[10][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(15),
Q => \hessian_reg[10]\(15),
R => '0'
);
\hessian_reg[10][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(16),
Q => \hessian_reg[10]\(16),
R => '0'
);
\hessian_reg[10][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(17),
Q => \hessian_reg[10]\(17),
R => '0'
);
\hessian_reg[10][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(18),
Q => \hessian_reg[10]\(18),
R => '0'
);
\hessian_reg[10][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(19),
Q => \hessian_reg[10]\(19),
R => '0'
);
\hessian_reg[10][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(1),
Q => \hessian_reg[10]\(1),
R => '0'
);
\hessian_reg[10][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(20),
Q => \hessian_reg[10]\(20),
R => '0'
);
\hessian_reg[10][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(21),
Q => \hessian_reg[10]\(21),
R => '0'
);
\hessian_reg[10][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(22),
Q => \hessian_reg[10]\(22),
R => '0'
);
\hessian_reg[10][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(23),
Q => \hessian_reg[10]\(23),
R => '0'
);
\hessian_reg[10][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(24),
Q => \hessian_reg[10]\(24),
R => '0'
);
\hessian_reg[10][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(25),
Q => \hessian_reg[10]\(25),
R => '0'
);
\hessian_reg[10][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(26),
Q => \hessian_reg[10]\(26),
R => '0'
);
\hessian_reg[10][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(27),
Q => \hessian_reg[10]\(27),
R => '0'
);
\hessian_reg[10][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(28),
Q => \hessian_reg[10]\(28),
R => '0'
);
\hessian_reg[10][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(29),
Q => \hessian_reg[10]\(29),
R => '0'
);
\hessian_reg[10][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(2),
Q => \hessian_reg[10]\(2),
R => '0'
);
\hessian_reg[10][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(30),
Q => \hessian_reg[10]\(30),
R => '0'
);
\hessian_reg[10][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(31),
Q => \hessian_reg[10]\(31),
R => '0'
);
\hessian_reg[10][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(3),
Q => \hessian_reg[10]\(3),
R => '0'
);
\hessian_reg[10][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(4),
Q => \hessian_reg[10]\(4),
R => '0'
);
\hessian_reg[10][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(5),
Q => \hessian_reg[10]\(5),
R => '0'
);
\hessian_reg[10][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(6),
Q => \hessian_reg[10]\(6),
R => '0'
);
\hessian_reg[10][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(7),
Q => \hessian_reg[10]\(7),
R => '0'
);
\hessian_reg[10][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(8),
Q => \hessian_reg[10]\(8),
R => '0'
);
\hessian_reg[10][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(9),
Q => \hessian_reg[10]\(9),
R => '0'
);
\hessian_reg[11][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(0),
Q => \hessian_reg[11]\(0),
R => '0'
);
\hessian_reg[11][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(10),
Q => \hessian_reg[11]\(10),
R => '0'
);
\hessian_reg[11][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(11),
Q => \hessian_reg[11]\(11),
R => '0'
);
\hessian_reg[11][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(12),
Q => \hessian_reg[11]\(12),
R => '0'
);
\hessian_reg[11][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(13),
Q => \hessian_reg[11]\(13),
R => '0'
);
\hessian_reg[11][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(14),
Q => \hessian_reg[11]\(14),
R => '0'
);
\hessian_reg[11][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(15),
Q => \hessian_reg[11]\(15),
R => '0'
);
\hessian_reg[11][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(16),
Q => \hessian_reg[11]\(16),
R => '0'
);
\hessian_reg[11][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(17),
Q => \hessian_reg[11]\(17),
R => '0'
);
\hessian_reg[11][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(18),
Q => \hessian_reg[11]\(18),
R => '0'
);
\hessian_reg[11][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(19),
Q => \hessian_reg[11]\(19),
R => '0'
);
\hessian_reg[11][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(1),
Q => \hessian_reg[11]\(1),
R => '0'
);
\hessian_reg[11][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(20),
Q => \hessian_reg[11]\(20),
R => '0'
);
\hessian_reg[11][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(21),
Q => \hessian_reg[11]\(21),
R => '0'
);
\hessian_reg[11][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(22),
Q => \hessian_reg[11]\(22),
R => '0'
);
\hessian_reg[11][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(23),
Q => \hessian_reg[11]\(23),
R => '0'
);
\hessian_reg[11][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(24),
Q => \hessian_reg[11]\(24),
R => '0'
);
\hessian_reg[11][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(25),
Q => \hessian_reg[11]\(25),
R => '0'
);
\hessian_reg[11][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(26),
Q => \hessian_reg[11]\(26),
R => '0'
);
\hessian_reg[11][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(27),
Q => \hessian_reg[11]\(27),
R => '0'
);
\hessian_reg[11][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(28),
Q => \hessian_reg[11]\(28),
R => '0'
);
\hessian_reg[11][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(29),
Q => \hessian_reg[11]\(29),
R => '0'
);
\hessian_reg[11][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(2),
Q => \hessian_reg[11]\(2),
R => '0'
);
\hessian_reg[11][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(30),
Q => \hessian_reg[11]\(30),
R => '0'
);
\hessian_reg[11][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(31),
Q => \hessian_reg[11]\(31),
R => '0'
);
\hessian_reg[11][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(3),
Q => \hessian_reg[11]\(3),
R => '0'
);
\hessian_reg[11][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(4),
Q => \hessian_reg[11]\(4),
R => '0'
);
\hessian_reg[11][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(5),
Q => \hessian_reg[11]\(5),
R => '0'
);
\hessian_reg[11][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(6),
Q => \hessian_reg[11]\(6),
R => '0'
);
\hessian_reg[11][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(7),
Q => \hessian_reg[11]\(7),
R => '0'
);
\hessian_reg[11][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(8),
Q => \hessian_reg[11]\(8),
R => '0'
);
\hessian_reg[11][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(9),
Q => \hessian_reg[11]\(9),
R => '0'
);
\hessian_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(0),
Q => \hessian_reg[1]\(0),
R => '0'
);
\hessian_reg[1][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(10),
Q => \hessian_reg[1]\(10),
R => '0'
);
\hessian_reg[1][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(11),
Q => \hessian_reg[1]\(11),
R => '0'
);
\hessian_reg[1][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(12),
Q => \hessian_reg[1]\(12),
R => '0'
);
\hessian_reg[1][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(13),
Q => \hessian_reg[1]\(13),
R => '0'
);
\hessian_reg[1][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(14),
Q => \hessian_reg[1]\(14),
R => '0'
);
\hessian_reg[1][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(15),
Q => \hessian_reg[1]\(15),
R => '0'
);
\hessian_reg[1][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(16),
Q => \hessian_reg[1]\(16),
R => '0'
);
\hessian_reg[1][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(17),
Q => \hessian_reg[1]\(17),
R => '0'
);
\hessian_reg[1][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(18),
Q => \hessian_reg[1]\(18),
R => '0'
);
\hessian_reg[1][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(19),
Q => \hessian_reg[1]\(19),
R => '0'
);
\hessian_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(1),
Q => \hessian_reg[1]\(1),
R => '0'
);
\hessian_reg[1][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(20),
Q => \hessian_reg[1]\(20),
R => '0'
);
\hessian_reg[1][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(21),
Q => \hessian_reg[1]\(21),
R => '0'
);
\hessian_reg[1][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(22),
Q => \hessian_reg[1]\(22),
R => '0'
);
\hessian_reg[1][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(23),
Q => \hessian_reg[1]\(23),
R => '0'
);
\hessian_reg[1][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(24),
Q => \hessian_reg[1]\(24),
R => '0'
);
\hessian_reg[1][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(25),
Q => \hessian_reg[1]\(25),
R => '0'
);
\hessian_reg[1][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(26),
Q => \hessian_reg[1]\(26),
R => '0'
);
\hessian_reg[1][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(27),
Q => \hessian_reg[1]\(27),
R => '0'
);
\hessian_reg[1][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(28),
Q => \hessian_reg[1]\(28),
R => '0'
);
\hessian_reg[1][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(29),
Q => \hessian_reg[1]\(29),
R => '0'
);
\hessian_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(2),
Q => \hessian_reg[1]\(2),
R => '0'
);
\hessian_reg[1][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(30),
Q => \hessian_reg[1]\(30),
R => '0'
);
\hessian_reg[1][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(31),
Q => \hessian_reg[1]\(31),
R => '0'
);
\hessian_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(3),
Q => \hessian_reg[1]\(3),
R => '0'
);
\hessian_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(4),
Q => \hessian_reg[1]\(4),
R => '0'
);
\hessian_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(5),
Q => \hessian_reg[1]\(5),
R => '0'
);
\hessian_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(6),
Q => \hessian_reg[1]\(6),
R => '0'
);
\hessian_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(7),
Q => \hessian_reg[1]\(7),
R => '0'
);
\hessian_reg[1][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(8),
Q => \hessian_reg[1]\(8),
R => '0'
);
\hessian_reg[1][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(9),
Q => \hessian_reg[1]\(9),
R => '0'
);
\hessian_reg[4][0]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(0),
Q => \hessian_reg[4][0]_srl3_n_0\
);
\hessian_reg[4][10]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(10),
Q => \hessian_reg[4][10]_srl3_n_0\
);
\hessian_reg[4][11]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(11),
Q => \hessian_reg[4][11]_srl3_n_0\
);
\hessian_reg[4][12]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(12),
Q => \hessian_reg[4][12]_srl3_n_0\
);
\hessian_reg[4][13]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(13),
Q => \hessian_reg[4][13]_srl3_n_0\
);
\hessian_reg[4][14]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(14),
Q => \hessian_reg[4][14]_srl3_n_0\
);
\hessian_reg[4][15]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(15),
Q => \hessian_reg[4][15]_srl3_n_0\
);
\hessian_reg[4][16]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(16),
Q => \hessian_reg[4][16]_srl3_n_0\
);
\hessian_reg[4][17]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(17),
Q => \hessian_reg[4][17]_srl3_n_0\
);
\hessian_reg[4][18]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(18),
Q => \hessian_reg[4][18]_srl3_n_0\
);
\hessian_reg[4][19]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(19),
Q => \hessian_reg[4][19]_srl3_n_0\
);
\hessian_reg[4][1]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(1),
Q => \hessian_reg[4][1]_srl3_n_0\
);
\hessian_reg[4][20]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(20),
Q => \hessian_reg[4][20]_srl3_n_0\
);
\hessian_reg[4][21]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(21),
Q => \hessian_reg[4][21]_srl3_n_0\
);
\hessian_reg[4][22]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(22),
Q => \hessian_reg[4][22]_srl3_n_0\
);
\hessian_reg[4][23]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(23),
Q => \hessian_reg[4][23]_srl3_n_0\
);
\hessian_reg[4][24]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(24),
Q => \hessian_reg[4][24]_srl3_n_0\
);
\hessian_reg[4][25]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(25),
Q => \hessian_reg[4][25]_srl3_n_0\
);
\hessian_reg[4][26]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(26),
Q => \hessian_reg[4][26]_srl3_n_0\
);
\hessian_reg[4][27]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(27),
Q => \hessian_reg[4][27]_srl3_n_0\
);
\hessian_reg[4][28]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(28),
Q => \hessian_reg[4][28]_srl3_n_0\
);
\hessian_reg[4][29]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(29),
Q => \hessian_reg[4][29]_srl3_n_0\
);
\hessian_reg[4][2]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(2),
Q => \hessian_reg[4][2]_srl3_n_0\
);
\hessian_reg[4][30]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(30),
Q => \hessian_reg[4][30]_srl3_n_0\
);
\hessian_reg[4][31]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(31),
Q => \hessian_reg[4][31]_srl3_n_0\
);
\hessian_reg[4][3]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(3),
Q => \hessian_reg[4][3]_srl3_n_0\
);
\hessian_reg[4][4]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(4),
Q => \hessian_reg[4][4]_srl3_n_0\
);
\hessian_reg[4][5]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(5),
Q => \hessian_reg[4][5]_srl3_n_0\
);
\hessian_reg[4][6]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(6),
Q => \hessian_reg[4][6]_srl3_n_0\
);
\hessian_reg[4][7]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(7),
Q => \hessian_reg[4][7]_srl3_n_0\
);
\hessian_reg[4][8]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(8),
Q => \hessian_reg[4][8]_srl3_n_0\
);
\hessian_reg[4][9]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(9),
Q => \hessian_reg[4][9]_srl3_n_0\
);
\hessian_reg[5][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][0]_srl3_n_0\,
Q => \hessian_reg[5]\(0),
R => '0'
);
\hessian_reg[5][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][10]_srl3_n_0\,
Q => \hessian_reg[5]\(10),
R => '0'
);
\hessian_reg[5][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][11]_srl3_n_0\,
Q => \hessian_reg[5]\(11),
R => '0'
);
\hessian_reg[5][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][12]_srl3_n_0\,
Q => \hessian_reg[5]\(12),
R => '0'
);
\hessian_reg[5][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][13]_srl3_n_0\,
Q => \hessian_reg[5]\(13),
R => '0'
);
\hessian_reg[5][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][14]_srl3_n_0\,
Q => \hessian_reg[5]\(14),
R => '0'
);
\hessian_reg[5][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][15]_srl3_n_0\,
Q => \hessian_reg[5]\(15),
R => '0'
);
\hessian_reg[5][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][16]_srl3_n_0\,
Q => \hessian_reg[5]\(16),
R => '0'
);
\hessian_reg[5][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][17]_srl3_n_0\,
Q => \hessian_reg[5]\(17),
R => '0'
);
\hessian_reg[5][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][18]_srl3_n_0\,
Q => \hessian_reg[5]\(18),
R => '0'
);
\hessian_reg[5][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][19]_srl3_n_0\,
Q => \hessian_reg[5]\(19),
R => '0'
);
\hessian_reg[5][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][1]_srl3_n_0\,
Q => \hessian_reg[5]\(1),
R => '0'
);
\hessian_reg[5][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][20]_srl3_n_0\,
Q => \hessian_reg[5]\(20),
R => '0'
);
\hessian_reg[5][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][21]_srl3_n_0\,
Q => \hessian_reg[5]\(21),
R => '0'
);
\hessian_reg[5][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][22]_srl3_n_0\,
Q => \hessian_reg[5]\(22),
R => '0'
);
\hessian_reg[5][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][23]_srl3_n_0\,
Q => \hessian_reg[5]\(23),
R => '0'
);
\hessian_reg[5][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][24]_srl3_n_0\,
Q => \hessian_reg[5]\(24),
R => '0'
);
\hessian_reg[5][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][25]_srl3_n_0\,
Q => \hessian_reg[5]\(25),
R => '0'
);
\hessian_reg[5][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][26]_srl3_n_0\,
Q => \hessian_reg[5]\(26),
R => '0'
);
\hessian_reg[5][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][27]_srl3_n_0\,
Q => \hessian_reg[5]\(27),
R => '0'
);
\hessian_reg[5][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][28]_srl3_n_0\,
Q => \hessian_reg[5]\(28),
R => '0'
);
\hessian_reg[5][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][29]_srl3_n_0\,
Q => \hessian_reg[5]\(29),
R => '0'
);
\hessian_reg[5][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][2]_srl3_n_0\,
Q => \hessian_reg[5]\(2),
R => '0'
);
\hessian_reg[5][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][30]_srl3_n_0\,
Q => \hessian_reg[5]\(30),
R => '0'
);
\hessian_reg[5][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][31]_srl3_n_0\,
Q => \hessian_reg[5]\(31),
R => '0'
);
\hessian_reg[5][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][3]_srl3_n_0\,
Q => \hessian_reg[5]\(3),
R => '0'
);
\hessian_reg[5][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][4]_srl3_n_0\,
Q => \hessian_reg[5]\(4),
R => '0'
);
\hessian_reg[5][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][5]_srl3_n_0\,
Q => \hessian_reg[5]\(5),
R => '0'
);
\hessian_reg[5][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][6]_srl3_n_0\,
Q => \hessian_reg[5]\(6),
R => '0'
);
\hessian_reg[5][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][7]_srl3_n_0\,
Q => \hessian_reg[5]\(7),
R => '0'
);
\hessian_reg[5][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][8]_srl3_n_0\,
Q => \hessian_reg[5]\(8),
R => '0'
);
\hessian_reg[5][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][9]_srl3_n_0\,
Q => \hessian_reg[5]\(9),
R => '0'
);
\hessian_reg[6][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(0),
Q => \hessian_reg[6]\(0),
R => '0'
);
\hessian_reg[6][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(10),
Q => \hessian_reg[6]\(10),
R => '0'
);
\hessian_reg[6][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(11),
Q => \hessian_reg[6]\(11),
R => '0'
);
\hessian_reg[6][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(12),
Q => \hessian_reg[6]\(12),
R => '0'
);
\hessian_reg[6][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(13),
Q => \hessian_reg[6]\(13),
R => '0'
);
\hessian_reg[6][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(14),
Q => \hessian_reg[6]\(14),
R => '0'
);
\hessian_reg[6][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(15),
Q => \hessian_reg[6]\(15),
R => '0'
);
\hessian_reg[6][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(16),
Q => \hessian_reg[6]\(16),
R => '0'
);
\hessian_reg[6][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(17),
Q => \hessian_reg[6]\(17),
R => '0'
);
\hessian_reg[6][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(18),
Q => \hessian_reg[6]\(18),
R => '0'
);
\hessian_reg[6][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(19),
Q => \hessian_reg[6]\(19),
R => '0'
);
\hessian_reg[6][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(1),
Q => \hessian_reg[6]\(1),
R => '0'
);
\hessian_reg[6][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(20),
Q => \hessian_reg[6]\(20),
R => '0'
);
\hessian_reg[6][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(21),
Q => \hessian_reg[6]\(21),
R => '0'
);
\hessian_reg[6][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(22),
Q => \hessian_reg[6]\(22),
R => '0'
);
\hessian_reg[6][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(23),
Q => \hessian_reg[6]\(23),
R => '0'
);
\hessian_reg[6][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(24),
Q => \hessian_reg[6]\(24),
R => '0'
);
\hessian_reg[6][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(25),
Q => \hessian_reg[6]\(25),
R => '0'
);
\hessian_reg[6][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(26),
Q => \hessian_reg[6]\(26),
R => '0'
);
\hessian_reg[6][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(27),
Q => \hessian_reg[6]\(27),
R => '0'
);
\hessian_reg[6][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(28),
Q => \hessian_reg[6]\(28),
R => '0'
);
\hessian_reg[6][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(29),
Q => \hessian_reg[6]\(29),
R => '0'
);
\hessian_reg[6][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(2),
Q => \hessian_reg[6]\(2),
R => '0'
);
\hessian_reg[6][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(30),
Q => \hessian_reg[6]\(30),
R => '0'
);
\hessian_reg[6][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(31),
Q => \hessian_reg[6]\(31),
R => '0'
);
\hessian_reg[6][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(3),
Q => \hessian_reg[6]\(3),
R => '0'
);
\hessian_reg[6][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(4),
Q => \hessian_reg[6]\(4),
R => '0'
);
\hessian_reg[6][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(5),
Q => \hessian_reg[6]\(5),
R => '0'
);
\hessian_reg[6][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(6),
Q => \hessian_reg[6]\(6),
R => '0'
);
\hessian_reg[6][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(7),
Q => \hessian_reg[6]\(7),
R => '0'
);
\hessian_reg[6][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(8),
Q => \hessian_reg[6]\(8),
R => '0'
);
\hessian_reg[6][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(9),
Q => \hessian_reg[6]\(9),
R => '0'
);
\hessian_reg[7][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(0),
Q => \hessian_reg[7]\(0),
R => '0'
);
\hessian_reg[7][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(10),
Q => \hessian_reg[7]\(10),
R => '0'
);
\hessian_reg[7][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(11),
Q => \hessian_reg[7]\(11),
R => '0'
);
\hessian_reg[7][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(12),
Q => \hessian_reg[7]\(12),
R => '0'
);
\hessian_reg[7][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(13),
Q => \hessian_reg[7]\(13),
R => '0'
);
\hessian_reg[7][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(14),
Q => \hessian_reg[7]\(14),
R => '0'
);
\hessian_reg[7][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(15),
Q => \hessian_reg[7]\(15),
R => '0'
);
\hessian_reg[7][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(16),
Q => \hessian_reg[7]\(16),
R => '0'
);
\hessian_reg[7][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(17),
Q => \hessian_reg[7]\(17),
R => '0'
);
\hessian_reg[7][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(18),
Q => \hessian_reg[7]\(18),
R => '0'
);
\hessian_reg[7][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(19),
Q => \hessian_reg[7]\(19),
R => '0'
);
\hessian_reg[7][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(1),
Q => \hessian_reg[7]\(1),
R => '0'
);
\hessian_reg[7][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(20),
Q => \hessian_reg[7]\(20),
R => '0'
);
\hessian_reg[7][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(21),
Q => \hessian_reg[7]\(21),
R => '0'
);
\hessian_reg[7][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(22),
Q => \hessian_reg[7]\(22),
R => '0'
);
\hessian_reg[7][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(23),
Q => \hessian_reg[7]\(23),
R => '0'
);
\hessian_reg[7][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(24),
Q => \hessian_reg[7]\(24),
R => '0'
);
\hessian_reg[7][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(25),
Q => \hessian_reg[7]\(25),
R => '0'
);
\hessian_reg[7][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(26),
Q => \hessian_reg[7]\(26),
R => '0'
);
\hessian_reg[7][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(27),
Q => \hessian_reg[7]\(27),
R => '0'
);
\hessian_reg[7][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(28),
Q => \hessian_reg[7]\(28),
R => '0'
);
\hessian_reg[7][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(29),
Q => \hessian_reg[7]\(29),
R => '0'
);
\hessian_reg[7][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(2),
Q => \hessian_reg[7]\(2),
R => '0'
);
\hessian_reg[7][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(30),
Q => \hessian_reg[7]\(30),
R => '0'
);
\hessian_reg[7][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(31),
Q => \hessian_reg[7]\(31),
R => '0'
);
\hessian_reg[7][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(3),
Q => \hessian_reg[7]\(3),
R => '0'
);
\hessian_reg[7][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(4),
Q => \hessian_reg[7]\(4),
R => '0'
);
\hessian_reg[7][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(5),
Q => \hessian_reg[7]\(5),
R => '0'
);
\hessian_reg[7][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(6),
Q => \hessian_reg[7]\(6),
R => '0'
);
\hessian_reg[7][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(7),
Q => \hessian_reg[7]\(7),
R => '0'
);
\hessian_reg[7][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(8),
Q => \hessian_reg[7]\(8),
R => '0'
);
\hessian_reg[7][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(9),
Q => \hessian_reg[7]\(9),
R => '0'
);
\hessian_reg[8][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(0),
Q => \hessian_reg[8]\(0),
R => '0'
);
\hessian_reg[8][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(10),
Q => \hessian_reg[8]\(10),
R => '0'
);
\hessian_reg[8][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(11),
Q => \hessian_reg[8]\(11),
R => '0'
);
\hessian_reg[8][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(12),
Q => \hessian_reg[8]\(12),
R => '0'
);
\hessian_reg[8][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(13),
Q => \hessian_reg[8]\(13),
R => '0'
);
\hessian_reg[8][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(14),
Q => \hessian_reg[8]\(14),
R => '0'
);
\hessian_reg[8][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(15),
Q => \hessian_reg[8]\(15),
R => '0'
);
\hessian_reg[8][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(16),
Q => \hessian_reg[8]\(16),
R => '0'
);
\hessian_reg[8][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(17),
Q => \hessian_reg[8]\(17),
R => '0'
);
\hessian_reg[8][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(18),
Q => \hessian_reg[8]\(18),
R => '0'
);
\hessian_reg[8][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(19),
Q => \hessian_reg[8]\(19),
R => '0'
);
\hessian_reg[8][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(1),
Q => \hessian_reg[8]\(1),
R => '0'
);
\hessian_reg[8][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(20),
Q => \hessian_reg[8]\(20),
R => '0'
);
\hessian_reg[8][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(21),
Q => \hessian_reg[8]\(21),
R => '0'
);
\hessian_reg[8][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(22),
Q => \hessian_reg[8]\(22),
R => '0'
);
\hessian_reg[8][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(23),
Q => \hessian_reg[8]\(23),
R => '0'
);
\hessian_reg[8][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(24),
Q => \hessian_reg[8]\(24),
R => '0'
);
\hessian_reg[8][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(25),
Q => \hessian_reg[8]\(25),
R => '0'
);
\hessian_reg[8][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(26),
Q => \hessian_reg[8]\(26),
R => '0'
);
\hessian_reg[8][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(27),
Q => \hessian_reg[8]\(27),
R => '0'
);
\hessian_reg[8][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(28),
Q => \hessian_reg[8]\(28),
R => '0'
);
\hessian_reg[8][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(29),
Q => \hessian_reg[8]\(29),
R => '0'
);
\hessian_reg[8][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(2),
Q => \hessian_reg[8]\(2),
R => '0'
);
\hessian_reg[8][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(30),
Q => \hessian_reg[8]\(30),
R => '0'
);
\hessian_reg[8][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(31),
Q => \hessian_reg[8]\(31),
R => '0'
);
\hessian_reg[8][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(3),
Q => \hessian_reg[8]\(3),
R => '0'
);
\hessian_reg[8][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(4),
Q => \hessian_reg[8]\(4),
R => '0'
);
\hessian_reg[8][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(5),
Q => \hessian_reg[8]\(5),
R => '0'
);
\hessian_reg[8][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(6),
Q => \hessian_reg[8]\(6),
R => '0'
);
\hessian_reg[8][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(7),
Q => \hessian_reg[8]\(7),
R => '0'
);
\hessian_reg[8][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(8),
Q => \hessian_reg[8]\(8),
R => '0'
);
\hessian_reg[8][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(9),
Q => \hessian_reg[8]\(9),
R => '0'
);
\hessian_reg[9][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(0),
Q => \hessian_reg[9]\(0),
R => '0'
);
\hessian_reg[9][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(10),
Q => \hessian_reg[9]\(10),
R => '0'
);
\hessian_reg[9][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(11),
Q => \hessian_reg[9]\(11),
R => '0'
);
\hessian_reg[9][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(12),
Q => \hessian_reg[9]\(12),
R => '0'
);
\hessian_reg[9][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(13),
Q => \hessian_reg[9]\(13),
R => '0'
);
\hessian_reg[9][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(14),
Q => \hessian_reg[9]\(14),
R => '0'
);
\hessian_reg[9][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(15),
Q => \hessian_reg[9]\(15),
R => '0'
);
\hessian_reg[9][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(16),
Q => \hessian_reg[9]\(16),
R => '0'
);
\hessian_reg[9][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(17),
Q => \hessian_reg[9]\(17),
R => '0'
);
\hessian_reg[9][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(18),
Q => \hessian_reg[9]\(18),
R => '0'
);
\hessian_reg[9][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(19),
Q => \hessian_reg[9]\(19),
R => '0'
);
\hessian_reg[9][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(1),
Q => \hessian_reg[9]\(1),
R => '0'
);
\hessian_reg[9][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(20),
Q => \hessian_reg[9]\(20),
R => '0'
);
\hessian_reg[9][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(21),
Q => \hessian_reg[9]\(21),
R => '0'
);
\hessian_reg[9][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(22),
Q => \hessian_reg[9]\(22),
R => '0'
);
\hessian_reg[9][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(23),
Q => \hessian_reg[9]\(23),
R => '0'
);
\hessian_reg[9][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(24),
Q => \hessian_reg[9]\(24),
R => '0'
);
\hessian_reg[9][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(25),
Q => \hessian_reg[9]\(25),
R => '0'
);
\hessian_reg[9][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(26),
Q => \hessian_reg[9]\(26),
R => '0'
);
\hessian_reg[9][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(27),
Q => \hessian_reg[9]\(27),
R => '0'
);
\hessian_reg[9][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(28),
Q => \hessian_reg[9]\(28),
R => '0'
);
\hessian_reg[9][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(29),
Q => \hessian_reg[9]\(29),
R => '0'
);
\hessian_reg[9][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(2),
Q => \hessian_reg[9]\(2),
R => '0'
);
\hessian_reg[9][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(30),
Q => \hessian_reg[9]\(30),
R => '0'
);
\hessian_reg[9][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(31),
Q => \hessian_reg[9]\(31),
R => '0'
);
\hessian_reg[9][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(3),
Q => \hessian_reg[9]\(3),
R => '0'
);
\hessian_reg[9][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(4),
Q => \hessian_reg[9]\(4),
R => '0'
);
\hessian_reg[9][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(5),
Q => \hessian_reg[9]\(5),
R => '0'
);
\hessian_reg[9][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(6),
Q => \hessian_reg[9]\(6),
R => '0'
);
\hessian_reg[9][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(7),
Q => \hessian_reg[9]\(7),
R => '0'
);
\hessian_reg[9][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(8),
Q => \hessian_reg[9]\(8),
R => '0'
);
\hessian_reg[9][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(9),
Q => \hessian_reg[9]\(9),
R => '0'
);
\minusOp_inferred__0/y_addr_out[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => y_addr_in(0),
O => \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\
);
\minusOp_inferred__0/y_addr_out[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => y_addr_in(4),
I1 => y_addr_in(2),
I2 => y_addr_in(0),
I3 => y_addr_in(1),
I4 => y_addr_in(3),
I5 => y_addr_in(5),
O => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\
);
\x_addr_out[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x_addr_in(0),
O => minusOp(0)
);
\x_addr_out[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x_addr_in(0),
I1 => x_addr_in(1),
O => \x_addr_out[1]_i_1_n_0\
);
\x_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => x_addr_in(1),
I1 => x_addr_in(0),
I2 => x_addr_in(2),
O => \x_addr_out[2]_i_1_n_0\
);
\x_addr_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => x_addr_in(2),
I1 => x_addr_in(0),
I2 => x_addr_in(1),
I3 => x_addr_in(3),
O => \x_addr_out[3]_i_1_n_0\
);
\x_addr_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => x_addr_in(3),
I1 => x_addr_in(1),
I2 => x_addr_in(0),
I3 => x_addr_in(2),
I4 => x_addr_in(4),
O => \x_addr_out[4]_i_1_n_0\
);
\x_addr_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => x_addr_in(4),
I1 => x_addr_in(2),
I2 => x_addr_in(0),
I3 => x_addr_in(1),
I4 => x_addr_in(3),
I5 => x_addr_in(5),
O => \x_addr_out[5]_i_1_n_0\
);
\x_addr_out[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_addr_out[9]_i_2_n_0\,
I1 => x_addr_in(6),
O => \x_addr_out[6]_i_1_n_0\
);
\x_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => x_addr_in(6),
I1 => \x_addr_out[9]_i_2_n_0\,
I2 => x_addr_in(7),
O => \x_addr_out[7]_i_1_n_0\
);
\x_addr_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => x_addr_in(7),
I1 => \x_addr_out[9]_i_2_n_0\,
I2 => x_addr_in(6),
I3 => x_addr_in(8),
O => \x_addr_out[8]_i_1_n_0\
);
\x_addr_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => x_addr_in(8),
I1 => x_addr_in(6),
I2 => \x_addr_out[9]_i_2_n_0\,
I3 => x_addr_in(7),
I4 => x_addr_in(9),
O => \x_addr_out[9]_i_1_n_0\
);
\x_addr_out[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => x_addr_in(4),
I1 => x_addr_in(2),
I2 => x_addr_in(0),
I3 => x_addr_in(1),
I4 => x_addr_in(3),
I5 => x_addr_in(5),
O => \x_addr_out[9]_i_2_n_0\
);
\x_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => minusOp(0),
Q => x_addr_out(0),
R => '0'
);
\x_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[1]_i_1_n_0\,
Q => x_addr_out(1),
R => '0'
);
\x_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[2]_i_1_n_0\,
Q => x_addr_out(2),
R => '0'
);
\x_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[3]_i_1_n_0\,
Q => x_addr_out(3),
R => '0'
);
\x_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[4]_i_1_n_0\,
Q => x_addr_out(4),
R => '0'
);
\x_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[5]_i_1_n_0\,
Q => x_addr_out(5),
R => '0'
);
\x_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[6]_i_1_n_0\,
Q => x_addr_out(6),
R => '0'
);
\x_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[7]_i_1_n_0\,
Q => x_addr_out(7),
R => '0'
);
\x_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[8]_i_1_n_0\,
Q => x_addr_out(8),
R => '0'
);
\x_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[9]_i_1_n_0\,
Q => x_addr_out(9),
R => '0'
);
\y_addr_out[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => y_addr_in(0),
I1 => y_addr_in(1),
O => \y_addr_out[1]_i_1_n_0\
);
\y_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => y_addr_in(1),
I1 => y_addr_in(0),
I2 => y_addr_in(2),
O => \y_addr_out[2]_i_1_n_0\
);
\y_addr_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => y_addr_in(2),
I1 => y_addr_in(0),
I2 => y_addr_in(1),
I3 => y_addr_in(3),
O => \y_addr_out[3]_i_1_n_0\
);
\y_addr_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => y_addr_in(3),
I1 => y_addr_in(1),
I2 => y_addr_in(0),
I3 => y_addr_in(2),
I4 => y_addr_in(4),
O => \y_addr_out[4]_i_1_n_0\
);
\y_addr_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => y_addr_in(4),
I1 => y_addr_in(2),
I2 => y_addr_in(0),
I3 => y_addr_in(1),
I4 => y_addr_in(3),
I5 => y_addr_in(5),
O => \y_addr_out[5]_i_1_n_0\
);
\y_addr_out[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I1 => y_addr_in(6),
O => \y_addr_out[6]_i_1_n_0\
);
\y_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => y_addr_in(6),
I1 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I2 => y_addr_in(7),
O => \y_addr_out[7]_i_1_n_0\
);
\y_addr_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => y_addr_in(7),
I1 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I2 => y_addr_in(6),
I3 => y_addr_in(8),
O => \y_addr_out[8]_i_1_n_0\
);
\y_addr_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => y_addr_in(8),
I1 => y_addr_in(6),
I2 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I3 => y_addr_in(7),
I4 => y_addr_in(9),
O => \y_addr_out[9]_i_1_n_0\
);
\y_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\,
Q => y_addr_out(0),
R => '0'
);
\y_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[1]_i_1_n_0\,
Q => y_addr_out(1),
R => '0'
);
\y_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[2]_i_1_n_0\,
Q => y_addr_out(2),
R => '0'
);
\y_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[3]_i_1_n_0\,
Q => y_addr_out(3),
R => '0'
);
\y_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[4]_i_1_n_0\,
Q => y_addr_out(4),
R => '0'
);
\y_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[5]_i_1_n_0\,
Q => y_addr_out(5),
R => '0'
);
\y_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[6]_i_1_n_0\,
Q => y_addr_out(6),
R => '0'
);
\y_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[7]_i_1_n_0\,
Q => y_addr_out(7),
R => '0'
);
\y_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[8]_i_1_n_0\,
Q => y_addr_out(8),
R => '0'
);
\y_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[9]_i_1_n_0\,
Q => y_addr_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_nmsuppression_0_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
active : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_nmsuppression_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_nmsuppression_0_0 : entity is "system_vga_nmsuppression_1_0,vga_nmsuppression,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_nmsuppression_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_nmsuppression_0_0 : entity is "vga_nmsuppression,Vivado 2016.4";
end system_vga_nmsuppression_0_0;
architecture STRUCTURE of system_vga_nmsuppression_0_0 is
begin
U0: entity work.system_vga_nmsuppression_0_0_vga_nmsuppression
port map (
active => active,
clk => clk,
enable => enable,
hessian_in(31 downto 0) => hessian_in(31 downto 0),
hessian_out(31 downto 0) => hessian_out(31 downto 0),
x_addr_in(9 downto 0) => x_addr_in(9 downto 0),
x_addr_out(9 downto 0) => x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => y_addr_in(9 downto 0),
y_addr_out(9 downto 0) => y_addr_out(9 downto 0)
);
end STRUCTURE;
|
entity computation is
end entity;
package my_logic is
type std_logic is ('0', '1');
type std_logic_vector is array (natural range <>) of std_logic;
type unsigned is array (natural range <>) of std_logic;
type signed is array (natural range <>) of std_logic;
function to_integer(x : unsigned) return integer;
end package;
use work.my_logic.all;
architecture foo of computation is
signal size :std_logic_vector (7 downto 0) := "00001001";
-- architecture declarative part
begin
UNLABELLED:
process
variable N: integer := to_integer(unsigned'("00000111")) ; ---WORKING
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "UNLABELLED memory left bound = " &integer'image(N);
wait;
end process;
OTHER:
process
variable N: integer:= to_integer (unsigned(size)) ; -- Not working
type memory is array (N downto 0 ) of std_logic_vector (31 downto 0 );
variable ram: memory;
begin
report "OTHER memory left bound = " &integer'image(N);
wait;
end process;
size <= "01000010" after 1 ns;
block1: block is
constant N: integer:= to_integer (unsigned(size)) ; -- Error
constant M: integer := size'length; -- OK
constant P: boolean := size'event; -- Error
begin
end block;
end architecture;
architecture bar of computation is
signal N : integer := 5;
signal bad : bit_vector(1 to N); -- Error
signal x : integer range 1 to N; -- Error
signal y : bit_vector(1 to bad'length); -- OK
begin
end architecture;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: rgmii1000_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY rgmii1000_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END rgmii1000_pll;
ARCHITECTURE SYN OF rgmii1000_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 8000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=rgmii1000_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "250.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "250.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "rgmii1000_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rgmii1000_pll_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-------------------------------------------------------------------------------
-- Title : Pulse synchronizer
-- Project : General Cores Library
-------------------------------------------------------------------------------
-- File : gc_pulse_synchronizer.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2012-08-29
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Full feedback pulse synchronizer (works independently of the
-- input/output clock domain frequency ratio)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-01-12 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencores_pkg.all;
entity gc_pulse_synchronizer is
port (
-- pulse input clock
clk_in_i : in std_logic;
-- pulse output clock
clk_out_i : in std_logic;
-- system reset (clk_in_i domain)
rst_n_i : in std_logic;
-- pulse input ready (clk_in_i domain). When HI, a pulse coming to d_p_i will be
-- correctly transferred to q_p_o.
d_ready_o : out std_logic;
-- pulse input (clk_in_i domain)
d_p_i : in std_logic;
-- pulse output (clk_out_i domain)
q_p_o : out std_logic);
end gc_pulse_synchronizer;
architecture rtl of gc_pulse_synchronizer is
constant c_sync_stages : integer := 3;
signal ready, d_p_d0 : std_logic;
signal in_ext, out_ext : std_logic;
signal out_feedback : std_logic;
signal d_in2out : std_logic_vector(c_sync_stages-1 downto 0);
signal d_out2in : std_logic_vector(c_sync_stages-1 downto 0);
begin -- rtl
process(clk_out_i, rst_n_i)
begin
if rst_n_i = '0' then
d_in2out <= (others => '0');
out_ext <= '0';
elsif rising_edge(clk_out_i) then
d_in2out <= d_in2out(c_sync_stages-2 downto 0) & in_ext;
out_ext <= d_in2out(c_sync_stages-1);
end if;
end process;
process(clk_in_i, rst_n_i)
begin
if rst_n_i = '0' then
d_out2in <= (others => '0');
elsif rising_edge(clk_in_i) then
d_out2in <= d_out2in(c_sync_stages-2 downto 0) & out_ext;
end if;
end process;
out_feedback <= d_out2in(c_sync_stages-1);
p_input_ack : process(clk_in_i, rst_n_i)
begin
if rst_n_i = '0' then
ready <= '1';
in_ext <= '0';
d_p_d0 <= '0';
elsif rising_edge(clk_in_i) then
d_p_d0 <= d_p_i;
if(ready = '1' and d_p_i = '1' and d_p_d0 = '0') then
in_ext <= '1';
ready <= '0';
elsif(in_ext = '1' and out_feedback = '1') then
in_ext <= '0';
elsif(in_ext = '0' and out_feedback = '0') then
ready <= '1';
end if;
end if;
end process;
p_drive_output : process(clk_out_i, rst_n_i)
begin
if rst_n_i = '0' then
q_p_o <= '0';
elsif rising_edge(clk_out_i) then
q_p_o <= not out_ext and d_in2out(c_sync_stages-1);
end if;
end process;
d_ready_o <= ready;
end rtl;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(13 DOWNTO 0) <= WRITE_ADDR(13 DOWNTO 0);
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16384
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity assert_uut is
port(
clock : in std_logic;
reset : in std_logic;
context_uut : in context_t;
en_feed : in std_logic;
stdin_rdy : in std_logic;
stdin_ack : out std_logic;
stdin_data : out stdin_vector;
en_check : in std_logic;
stdout_rdy : in std_logic;
stdout_ack : out std_logic;
stdout_data : in stdout_vector;
vecs_found : out std_logic;
vec_read : out std_logic;
n_error : out std_logic
);
end assert_uut;
architecture rtl of assert_uut is
type vin_table is array(0 to 2**VEC_NO_SIZE - 1) of stdin_vector;
type vout_table is array(0 to 2**VEC_NO_SIZE - 1) of stdout_vector;
constant input_vectors_1 : vin_table := (
--##INPUT_VECTORS_1_GO_DOWN_HERE##--
0 => x"00_00_00_a3",
1 => x"00_00_00_ea",
2 => x"00_00_00_cc",
3 => x"00_00_00_28",
4 => x"00_00_00_30",
5 => x"00_00_00_a0",
6 => x"00_00_00_c0",
7 => x"00_00_00_80",
8 => x"00_00_00_00",
9 => x"00_00_00_00",
10 => x"00_00_00_00",
11 => x"00_00_00_00",
12 => x"00_00_00_00",
13 => x"00_00_00_00",
14 => x"00_00_00_00",
15 => x"00_00_00_00",
16 => x"00_00_00_00",
17 => x"00_00_00_00",
18 => x"00_00_00_00",
19 => x"00_00_00_00",
20 => x"00_00_00_00",
21 => x"00_00_00_00",
22 => x"00_00_00_00",
23 => x"00_00_00_00",
24 => x"00_00_00_00",
25 => x"00_00_00_00",
26 => x"00_00_00_00",
27 => x"00_00_00_00",
28 => x"00_00_00_00",
29 => x"00_00_00_00",
30 => x"00_00_00_00",
31 => x"00_00_00_00",
32 => x"00_00_00_00",
33 => x"00_00_00_00",
34 => x"00_00_00_00",
35 => x"00_00_00_00",
36 => x"00_00_00_00",
37 => x"00_00_00_00",
38 => x"00_00_00_00",
39 => x"00_00_00_00",
40 => x"00_00_00_00",
41 => x"00_00_00_00",
42 => x"00_00_00_00",
43 => x"00_00_00_00",
44 => x"00_00_00_00",
45 => x"00_00_00_00",
46 => x"00_00_00_00",
47 => x"00_00_00_00",
48 => x"00_00_00_00",
49 => x"00_00_00_00",
50 => x"00_00_00_00",
51 => x"00_00_00_00",
52 => x"00_00_00_00",
53 => x"00_00_00_00",
54 => x"00_00_00_00",
55 => x"00_00_00_00",
56 => x"00_00_00_00",
57 => x"00_00_00_00",
58 => x"00_00_00_00",
59 => x"00_00_00_00",
60 => x"00_00_00_00",
61 => x"00_00_00_00",
62 => x"00_00_00_00",
63 => x"00_00_00_00",
--##INPUT_VECTORS_1_GO_OVER_HERE##--
others => (others => '0'));
constant output_vectors_1 : vout_table := (
--##OUTPUT_VECTORS_1_GO_DOWN_HERE##--
0 => x"ff",
1 => x"00",
2 => x"ff",
3 => x"ff",
4 => x"00",
5 => x"00",
6 => x"ff",
7 => x"00",
8 => x"ff",
9 => x"00",
10 => x"ff",
11 => x"ff",
12 => x"00",
13 => x"00",
14 => x"ff",
15 => x"00",
16 => x"ff",
17 => x"00",
18 => x"ff",
19 => x"ff",
20 => x"00",
21 => x"00",
22 => x"ff",
23 => x"00",
24 => x"ff",
25 => x"00",
26 => x"ff",
27 => x"ff",
28 => x"00",
29 => x"00",
30 => x"ff",
31 => x"00",
32 => x"ff",
33 => x"00",
34 => x"ff",
35 => x"ff",
36 => x"00",
37 => x"00",
38 => x"ff",
39 => x"00",
40 => x"ff",
41 => x"00",
42 => x"ff",
43 => x"ff",
44 => x"00",
45 => x"00",
46 => x"ff",
47 => x"00",
48 => x"ff",
49 => x"00",
50 => x"ff",
51 => x"ff",
52 => x"00",
53 => x"00",
54 => x"ff",
55 => x"00",
56 => x"ff",
57 => x"00",
58 => x"ff",
59 => x"ff",
60 => x"00",
61 => x"00",
62 => x"ff",
63 => x"00",
--##OUTPUT_VECTORS_1_GO_OVER_HERE##--
others => (others => '0'));
constant input_vectors_2 : vin_table := (
--##INPUT_VECTORS_2_GO_DOWN_HERE##--
0 => x"00_00_00_a3",
1 => x"00_00_00_ea",
2 => x"00_00_00_cc",
3 => x"00_00_00_28",
4 => x"00_00_00_30",
5 => x"00_00_00_a0",
6 => x"00_00_00_c0",
7 => x"00_00_00_80",
8 => x"00_00_00_00",
9 => x"00_00_00_00",
10 => x"00_00_00_00",
11 => x"00_00_00_00",
12 => x"00_00_00_00",
13 => x"00_00_00_00",
14 => x"00_00_00_00",
15 => x"00_00_00_00",
16 => x"00_00_00_00",
17 => x"00_00_00_00",
18 => x"00_00_00_00",
19 => x"00_00_00_00",
20 => x"00_00_00_00",
21 => x"00_00_00_00",
22 => x"00_00_00_00",
23 => x"00_00_00_00",
24 => x"00_00_00_00",
25 => x"00_00_00_00",
26 => x"00_00_00_00",
27 => x"00_00_00_00",
28 => x"00_00_00_00",
29 => x"00_00_00_00",
30 => x"00_00_00_00",
31 => x"00_00_00_00",
32 => x"00_00_00_00",
33 => x"00_00_00_00",
34 => x"00_00_00_00",
35 => x"00_00_00_00",
36 => x"00_00_00_00",
37 => x"00_00_00_00",
38 => x"00_00_00_00",
39 => x"00_00_00_00",
40 => x"00_00_00_00",
41 => x"00_00_00_00",
42 => x"00_00_00_00",
43 => x"00_00_00_00",
44 => x"00_00_00_00",
45 => x"00_00_00_00",
46 => x"00_00_00_00",
47 => x"00_00_00_00",
48 => x"00_00_00_00",
49 => x"00_00_00_00",
50 => x"00_00_00_00",
51 => x"00_00_00_00",
52 => x"00_00_00_00",
53 => x"00_00_00_00",
54 => x"00_00_00_00",
55 => x"00_00_00_00",
56 => x"00_00_00_00",
57 => x"00_00_00_00",
58 => x"00_00_00_00",
59 => x"00_00_00_00",
60 => x"00_00_00_00",
61 => x"00_00_00_00",
62 => x"00_00_00_00",
63 => x"00_00_00_00",
--##INPUT_VECTORS_2_GO_OVER_HERE##--
others => (others => '0'));
constant output_vectors_2 : vout_table := (
--##OUTPUT_VECTORS_2_GO_DOWN_HERE##--
0 => x"ff",
1 => x"00",
2 => x"ff",
3 => x"ff",
4 => x"00",
5 => x"00",
6 => x"ff",
7 => x"00",
8 => x"ff",
9 => x"00",
10 => x"ff",
11 => x"ff",
12 => x"00",
13 => x"00",
14 => x"ff",
15 => x"00",
16 => x"ff",
17 => x"00",
18 => x"ff",
19 => x"ff",
20 => x"00",
21 => x"00",
22 => x"ff",
23 => x"00",
24 => x"ff",
25 => x"00",
26 => x"ff",
27 => x"ff",
28 => x"00",
29 => x"00",
30 => x"ff",
31 => x"00",
32 => x"ff",
33 => x"00",
34 => x"ff",
35 => x"ff",
36 => x"00",
37 => x"00",
38 => x"ff",
39 => x"00",
40 => x"ff",
41 => x"00",
42 => x"ff",
43 => x"ff",
44 => x"00",
45 => x"00",
46 => x"ff",
47 => x"00",
48 => x"ff",
49 => x"00",
50 => x"ff",
51 => x"ff",
52 => x"00",
53 => x"00",
54 => x"ff",
55 => x"00",
56 => x"ff",
57 => x"00",
58 => x"ff",
59 => x"ff",
60 => x"00",
61 => x"00",
62 => x"ff",
63 => x"00",
--##OUTPUT_VECTORS_2_GO_OVER_HERE##--
others => (others => '0'));
signal in_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal in_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal out_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal out_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal stdin_ack_sig : std_logic;
signal vector_read : std_logic;
begin
feed : process(reset, clock) is
begin
if (reset = '1') then
in_vec_counter_1 <= (others => '0');
in_vec_counter_2 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
elsif rising_edge(clock) then
case context_uut is
when "01" =>
if (en_feed = '1') then
stdin_data <= input_vectors_1(to_integer(in_vec_counter_1));
stdin_ack_sig <= '1';
if (stdin_rdy = '1' and stdin_ack_sig = '1') then
in_vec_counter_1 <= in_vec_counter_1 + 1;
stdin_ack_sig <= '0';
end if;
else
--in_vec_counter_1 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
end if;
when "10" =>
if (en_feed = '1') then
stdin_data <= input_vectors_2(to_integer(in_vec_counter_2));
stdin_ack_sig <= '1';
if (stdin_rdy = '1' and stdin_ack_sig = '1') then
in_vec_counter_2 <= in_vec_counter_2 + 1;
stdin_ack_sig <= '0';
end if;
else
--in_vec_counter_2 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
end if;
when others =>
end case;
end if;
end process feed;
check : process(reset, clock) is
begin
if (reset = '1') then
n_error <= '1';
vec_read <= '0';
elsif rising_edge(clock) then
vec_read <= '0';
if (en_check = '1') then
if (stdout_rdy = '1') then
vec_read <= '1';
case context_uut is
when "01" =>
assert (stdout_data = output_vectors_1(to_integer(out_vec_counter_1)))
report "ERROR ---> Bad output vector found";
--synthesizable check
if (stdout_data /= output_vectors_1(to_integer(out_vec_counter_1))) then
n_error <= '0';
end if;
when "10" =>
assert (stdout_data = output_vectors_2(to_integer(out_vec_counter_2)))
report "ERROR ---> Bad output vector found";
--synthesizable check
if (stdout_data /= output_vectors_2(to_integer(out_vec_counter_2))) then
n_error <= '0';
end if;
when others =>
end case;
end if;
end if;
end if;
end process check;
read_counter : process(reset, clock) is
begin
if (reset = '1') then
out_vec_counter_1 <= (others => '0');
out_vec_counter_2 <= (others => '0');
elsif rising_edge(clock) then
if (en_check = '1') then
if (stdout_rdy = '1') then
case context_uut is
when "01" =>
out_vec_counter_1 <= out_vec_counter_1 + 1;
when "10" =>
out_vec_counter_2 <= out_vec_counter_2 + 1;
when others =>
end case;
end if;
--else
-- case context_uut is
-- when "01" =>
-- out_vec_counter_1 <= (others => '0');
-- when "10" =>
-- out_vec_counter_2 <= (others => '0');
-- when others =>
-- end case;
end if;
end if;
end process read_counter;
--asynchronous declarations
stdout_ack <= en_check;
stdin_ack <= stdin_ack_sig;
vecs_found <= '1' when (out_vec_counter_1 /= 0 or out_vec_counter_2 /= 0) else '0';
end rtl;
|
--test bench written by Alban Bourge @ TIMA
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.pkg_tb.all;
entity assert_uut is
port(
clock : in std_logic;
reset : in std_logic;
context_uut : in context_t;
en_feed : in std_logic;
stdin_rdy : in std_logic;
stdin_ack : out std_logic;
stdin_data : out stdin_vector;
en_check : in std_logic;
stdout_rdy : in std_logic;
stdout_ack : out std_logic;
stdout_data : in stdout_vector;
vecs_found : out std_logic;
vec_read : out std_logic;
n_error : out std_logic
);
end assert_uut;
architecture rtl of assert_uut is
type vin_table is array(0 to 2**VEC_NO_SIZE - 1) of stdin_vector;
type vout_table is array(0 to 2**VEC_NO_SIZE - 1) of stdout_vector;
constant input_vectors_1 : vin_table := (
--##INPUT_VECTORS_1_GO_DOWN_HERE##--
0 => x"00_00_00_a3",
1 => x"00_00_00_ea",
2 => x"00_00_00_cc",
3 => x"00_00_00_28",
4 => x"00_00_00_30",
5 => x"00_00_00_a0",
6 => x"00_00_00_c0",
7 => x"00_00_00_80",
8 => x"00_00_00_00",
9 => x"00_00_00_00",
10 => x"00_00_00_00",
11 => x"00_00_00_00",
12 => x"00_00_00_00",
13 => x"00_00_00_00",
14 => x"00_00_00_00",
15 => x"00_00_00_00",
16 => x"00_00_00_00",
17 => x"00_00_00_00",
18 => x"00_00_00_00",
19 => x"00_00_00_00",
20 => x"00_00_00_00",
21 => x"00_00_00_00",
22 => x"00_00_00_00",
23 => x"00_00_00_00",
24 => x"00_00_00_00",
25 => x"00_00_00_00",
26 => x"00_00_00_00",
27 => x"00_00_00_00",
28 => x"00_00_00_00",
29 => x"00_00_00_00",
30 => x"00_00_00_00",
31 => x"00_00_00_00",
32 => x"00_00_00_00",
33 => x"00_00_00_00",
34 => x"00_00_00_00",
35 => x"00_00_00_00",
36 => x"00_00_00_00",
37 => x"00_00_00_00",
38 => x"00_00_00_00",
39 => x"00_00_00_00",
40 => x"00_00_00_00",
41 => x"00_00_00_00",
42 => x"00_00_00_00",
43 => x"00_00_00_00",
44 => x"00_00_00_00",
45 => x"00_00_00_00",
46 => x"00_00_00_00",
47 => x"00_00_00_00",
48 => x"00_00_00_00",
49 => x"00_00_00_00",
50 => x"00_00_00_00",
51 => x"00_00_00_00",
52 => x"00_00_00_00",
53 => x"00_00_00_00",
54 => x"00_00_00_00",
55 => x"00_00_00_00",
56 => x"00_00_00_00",
57 => x"00_00_00_00",
58 => x"00_00_00_00",
59 => x"00_00_00_00",
60 => x"00_00_00_00",
61 => x"00_00_00_00",
62 => x"00_00_00_00",
63 => x"00_00_00_00",
--##INPUT_VECTORS_1_GO_OVER_HERE##--
others => (others => '0'));
constant output_vectors_1 : vout_table := (
--##OUTPUT_VECTORS_1_GO_DOWN_HERE##--
0 => x"ff",
1 => x"00",
2 => x"ff",
3 => x"ff",
4 => x"00",
5 => x"00",
6 => x"ff",
7 => x"00",
8 => x"ff",
9 => x"00",
10 => x"ff",
11 => x"ff",
12 => x"00",
13 => x"00",
14 => x"ff",
15 => x"00",
16 => x"ff",
17 => x"00",
18 => x"ff",
19 => x"ff",
20 => x"00",
21 => x"00",
22 => x"ff",
23 => x"00",
24 => x"ff",
25 => x"00",
26 => x"ff",
27 => x"ff",
28 => x"00",
29 => x"00",
30 => x"ff",
31 => x"00",
32 => x"ff",
33 => x"00",
34 => x"ff",
35 => x"ff",
36 => x"00",
37 => x"00",
38 => x"ff",
39 => x"00",
40 => x"ff",
41 => x"00",
42 => x"ff",
43 => x"ff",
44 => x"00",
45 => x"00",
46 => x"ff",
47 => x"00",
48 => x"ff",
49 => x"00",
50 => x"ff",
51 => x"ff",
52 => x"00",
53 => x"00",
54 => x"ff",
55 => x"00",
56 => x"ff",
57 => x"00",
58 => x"ff",
59 => x"ff",
60 => x"00",
61 => x"00",
62 => x"ff",
63 => x"00",
--##OUTPUT_VECTORS_1_GO_OVER_HERE##--
others => (others => '0'));
constant input_vectors_2 : vin_table := (
--##INPUT_VECTORS_2_GO_DOWN_HERE##--
0 => x"00_00_00_a3",
1 => x"00_00_00_ea",
2 => x"00_00_00_cc",
3 => x"00_00_00_28",
4 => x"00_00_00_30",
5 => x"00_00_00_a0",
6 => x"00_00_00_c0",
7 => x"00_00_00_80",
8 => x"00_00_00_00",
9 => x"00_00_00_00",
10 => x"00_00_00_00",
11 => x"00_00_00_00",
12 => x"00_00_00_00",
13 => x"00_00_00_00",
14 => x"00_00_00_00",
15 => x"00_00_00_00",
16 => x"00_00_00_00",
17 => x"00_00_00_00",
18 => x"00_00_00_00",
19 => x"00_00_00_00",
20 => x"00_00_00_00",
21 => x"00_00_00_00",
22 => x"00_00_00_00",
23 => x"00_00_00_00",
24 => x"00_00_00_00",
25 => x"00_00_00_00",
26 => x"00_00_00_00",
27 => x"00_00_00_00",
28 => x"00_00_00_00",
29 => x"00_00_00_00",
30 => x"00_00_00_00",
31 => x"00_00_00_00",
32 => x"00_00_00_00",
33 => x"00_00_00_00",
34 => x"00_00_00_00",
35 => x"00_00_00_00",
36 => x"00_00_00_00",
37 => x"00_00_00_00",
38 => x"00_00_00_00",
39 => x"00_00_00_00",
40 => x"00_00_00_00",
41 => x"00_00_00_00",
42 => x"00_00_00_00",
43 => x"00_00_00_00",
44 => x"00_00_00_00",
45 => x"00_00_00_00",
46 => x"00_00_00_00",
47 => x"00_00_00_00",
48 => x"00_00_00_00",
49 => x"00_00_00_00",
50 => x"00_00_00_00",
51 => x"00_00_00_00",
52 => x"00_00_00_00",
53 => x"00_00_00_00",
54 => x"00_00_00_00",
55 => x"00_00_00_00",
56 => x"00_00_00_00",
57 => x"00_00_00_00",
58 => x"00_00_00_00",
59 => x"00_00_00_00",
60 => x"00_00_00_00",
61 => x"00_00_00_00",
62 => x"00_00_00_00",
63 => x"00_00_00_00",
--##INPUT_VECTORS_2_GO_OVER_HERE##--
others => (others => '0'));
constant output_vectors_2 : vout_table := (
--##OUTPUT_VECTORS_2_GO_DOWN_HERE##--
0 => x"ff",
1 => x"00",
2 => x"ff",
3 => x"ff",
4 => x"00",
5 => x"00",
6 => x"ff",
7 => x"00",
8 => x"ff",
9 => x"00",
10 => x"ff",
11 => x"ff",
12 => x"00",
13 => x"00",
14 => x"ff",
15 => x"00",
16 => x"ff",
17 => x"00",
18 => x"ff",
19 => x"ff",
20 => x"00",
21 => x"00",
22 => x"ff",
23 => x"00",
24 => x"ff",
25 => x"00",
26 => x"ff",
27 => x"ff",
28 => x"00",
29 => x"00",
30 => x"ff",
31 => x"00",
32 => x"ff",
33 => x"00",
34 => x"ff",
35 => x"ff",
36 => x"00",
37 => x"00",
38 => x"ff",
39 => x"00",
40 => x"ff",
41 => x"00",
42 => x"ff",
43 => x"ff",
44 => x"00",
45 => x"00",
46 => x"ff",
47 => x"00",
48 => x"ff",
49 => x"00",
50 => x"ff",
51 => x"ff",
52 => x"00",
53 => x"00",
54 => x"ff",
55 => x"00",
56 => x"ff",
57 => x"00",
58 => x"ff",
59 => x"ff",
60 => x"00",
61 => x"00",
62 => x"ff",
63 => x"00",
--##OUTPUT_VECTORS_2_GO_OVER_HERE##--
others => (others => '0'));
signal in_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal in_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal out_vec_counter_1 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal out_vec_counter_2 : unsigned(VEC_NO_SIZE - 1 downto 0);
signal stdin_ack_sig : std_logic;
signal vector_read : std_logic;
begin
feed : process(reset, clock) is
begin
if (reset = '1') then
in_vec_counter_1 <= (others => '0');
in_vec_counter_2 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
elsif rising_edge(clock) then
case context_uut is
when "01" =>
if (en_feed = '1') then
stdin_data <= input_vectors_1(to_integer(in_vec_counter_1));
stdin_ack_sig <= '1';
if (stdin_rdy = '1' and stdin_ack_sig = '1') then
in_vec_counter_1 <= in_vec_counter_1 + 1;
stdin_ack_sig <= '0';
end if;
else
--in_vec_counter_1 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
end if;
when "10" =>
if (en_feed = '1') then
stdin_data <= input_vectors_2(to_integer(in_vec_counter_2));
stdin_ack_sig <= '1';
if (stdin_rdy = '1' and stdin_ack_sig = '1') then
in_vec_counter_2 <= in_vec_counter_2 + 1;
stdin_ack_sig <= '0';
end if;
else
--in_vec_counter_2 <= (others => '0');
stdin_data <= (others => '0');
stdin_ack_sig <= '0';
end if;
when others =>
end case;
end if;
end process feed;
check : process(reset, clock) is
begin
if (reset = '1') then
n_error <= '1';
vec_read <= '0';
elsif rising_edge(clock) then
vec_read <= '0';
if (en_check = '1') then
if (stdout_rdy = '1') then
vec_read <= '1';
case context_uut is
when "01" =>
assert (stdout_data = output_vectors_1(to_integer(out_vec_counter_1)))
report "ERROR ---> Bad output vector found";
--synthesizable check
if (stdout_data /= output_vectors_1(to_integer(out_vec_counter_1))) then
n_error <= '0';
end if;
when "10" =>
assert (stdout_data = output_vectors_2(to_integer(out_vec_counter_2)))
report "ERROR ---> Bad output vector found";
--synthesizable check
if (stdout_data /= output_vectors_2(to_integer(out_vec_counter_2))) then
n_error <= '0';
end if;
when others =>
end case;
end if;
end if;
end if;
end process check;
read_counter : process(reset, clock) is
begin
if (reset = '1') then
out_vec_counter_1 <= (others => '0');
out_vec_counter_2 <= (others => '0');
elsif rising_edge(clock) then
if (en_check = '1') then
if (stdout_rdy = '1') then
case context_uut is
when "01" =>
out_vec_counter_1 <= out_vec_counter_1 + 1;
when "10" =>
out_vec_counter_2 <= out_vec_counter_2 + 1;
when others =>
end case;
end if;
--else
-- case context_uut is
-- when "01" =>
-- out_vec_counter_1 <= (others => '0');
-- when "10" =>
-- out_vec_counter_2 <= (others => '0');
-- when others =>
-- end case;
end if;
end if;
end process read_counter;
--asynchronous declarations
stdout_ack <= en_check;
stdin_ack <= stdin_ack_sig;
vecs_found <= '1' when (out_vec_counter_1 /= 0 or out_vec_counter_2 /= 0) else '0';
end rtl;
|
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity Tester is
port( CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
HEX0, HEX1,
HEX2, HEX3,
HEX4, HEX5,
HEX6, HEX7 : out std_logic_vector(6 downto 0);
SW : in std_logic_vector(15 downto 0);
LEDR : out std_logic_vector(0 downto 0)
);
end Tester;
-----Architecture-----
architecture watch_tester of Tester is
signal time_watch, time_alarm : std_logic_vector(15 downto 0) := "0000000000000000";--(others => '0');
signal watch : std_logic_vector(41 downto 0) := (others => '0');
signal alarm : std_logic_vector(27 downto 0) := (others => '0');
begin
HEX0 <= "1111111";
HEX1 <= "1111111";
w : entity work.watch port map ( clk => CLOCK_50, speed => KEY(0), reset => KEY(3), sec_1 => watch(6 downto 0),
sec_10 => watch(13 downto 7), min_1 => watch(20 downto 14), min_10 => watch(27 downto 21),
hrs_1 => watch(34 downto 28), hrs_10 => watch(41 downto 35), time => time_watch);
a : entity work.Alarm port map ( bin_min1 => SW(3 downto 0), bin_min10 => SW(7 downto 4), bin_hrs1 => SW(11 downto 8), bin_hrs10 => SW(15 downto 12),
time_alarm => time_alarm);
c : entity work.Compare port map (alarm => LEDR(0), time_watch => time_watch, time_alarm => time_alarm);
b1 : entity work.Binary_7_Segment port map (bin => time_alarm(3 downto 0), seg => alarm(6 downto 0));
b2 : entity work.Binary_7_Segment port map (bin => time_alarm(7 downto 4), seg => alarm(13 downto 7));
b3 : entity work.Binary_7_Segment port map (bin => time_alarm(11 downto 8), seg => alarm(20 downto 14));
b4 : entity work.Binary_7_Segment port map (bin => time_alarm(15 downto 12), seg => alarm(27 downto 21));
v : entity work.view port map ( sec_1 => watch(6 downto 0) , sec_10 => watch(13 downto 7), min_1 => watch(20 downto 14), min_10 => watch(27 downto 21),
hrs_1 => watch(34 downto 28), hrs_10 => watch(41 downto 35),
min_1a => alarm(6 downto 0) , min_10a => alarm(13 downto 7),
hrs_1a => alarm(20 downto 14), hrs_10a => alarm(27 downto 21), check => KEY(2),
show(6 downto 0) => HEX2, show(13 downto 7) => HEX3, show(20 downto 14) => HEX4, show(27 downto 21) => HEX5,
show(34 downto 28) => HEX6, show(41 downto 35) => HEX7);
end watch_tester; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
generic (
skip : integer := 10
);
port (
nreset : in std_logic;
clk : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic
);
end mwe;
architecture behav of mwe is
type shared_counter is protected
procedure reset;
procedure increment;
impure function value return integer;
impure function pulsed return boolean;
end protected shared_counter;
type shared_counter is protected body
variable cnt : integer range 0 to skip-1 := 0;
variable flag_pulse : boolean := false;
procedure reset is
begin
cnt := 0;
flag_pulse := false;
end reset;
procedure increment is
begin
if cnt < skip-1 then
cnt := cnt + 1;
else
cnt := 0;
flag_pulse := true;
report "Pulse detected";
end if;
end increment;
impure function value return integer is
begin
return cnt;
end function value;
impure function pulsed return boolean is
variable pulsed_state : boolean;
begin
pulsed_state := flag_pulse;
flag_pulse := false;
return pulsed_state;
end function pulsed;
end protected body shared_counter;
shared variable shrd_cnt : shared_counter;
begin
output:process(clk,nreset)
begin
if nreset /= '1' then
shrd_cnt.reset;
pulse_out <= '0';
elsif rising_edge(clk) then
pulse_out <= '0';
if shrd_cnt.pulsed then
pulse_out <= '1';
end if;
end if;
end process;
pulse_cnt_update:process(nreset,pulse_in)
begin
if nreset = '1' then
if pulse_in = '1' then
shrd_cnt.increment;
end if;
end if ;
end process;
end behav;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library mem;
library tech;
use work.cpu_btb_cache_config_pkg.all;
use work.cpu_btb_cache_replace_lfsr_config_pkg.all;
architecture rtl of cpu_btb_cache_replace_lfsr is
type comb_type is record
rway_enc : std_ulogic_vector(cpu_btb_cache_log2_assoc-1 downto 0);
end record;
signal c : comb_type;
begin
lfsr_assoc_loop : for n in cpu_btb_cache_log2_assoc-1 downto 0 generate
-- use different sizes for LFSRs for each bit so each sequence is different
lfsr : entity tech.lfsr(rtl)
generic map (
state_bits => cpu_btb_cache_replace_lfsr_state_bits + n
)
port map (
clk => clk,
rstn => rstn,
en => cpu_btb_cache_replace_lfsr_ctrl_in.re,
output => c.rway_enc(n)
);
end generate;
rway_dec : entity tech.decoder(rtl)
generic map (
output_bits => 2**cpu_btb_cache_log2_assoc
)
port map (
datain => c.rway_enc,
dataout => cpu_btb_cache_replace_lfsr_dp_out.rway
);
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_ab_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:33:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_ab_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_ab_e
--
architecture rtl of inst_ab_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
udc: DECLARATION SELECTED inst_ab_i
begin
udc: AUTOBODY SELECTED inst_ab_i
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3122.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p07n01i03122ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p07n01i03122ent_a;
ARCHITECTURE c05s02b01x01p07n01i03122arch_a OF c05s02b01x01p07n01i03122ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p07n01i03122arch_a;
configuration c05s02b01x01p07n01i03122cfg_a of c05s02b01x01p07n01i03122ent_a is
for c05s02b01x01p07n01i03122arch_a
end for;
end c05s02b01x01p07n01i03122cfg_a;
--
ENTITY c05s02b01x01p07n01i03122ent IS
END c05s02b01x01p07n01i03122ent;
ARCHITECTURE c05s02b01x01p07n01i03122arch OF c05s02b01x01p07n01i03122ent IS
component ic_socket
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : ic_socket
generic map ( true )
port map (s1, s2);
u2 : ic_socket
generic map ( true )
port map (s2, s3);
u3 : ic_socket
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p07n01i03122"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p07n01i03122 - Explicitly OPEN entity aspects in configuration blocks test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p07n01i03122arch;
configuration c05s02b01x01p07n01i03122cfg of c05s02b01x01p07n01i03122ent is
for c05s02b01x01p07n01i03122arch
for all : ic_socket use OPEN;
end for;
end for;
end c05s02b01x01p07n01i03122cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3122.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p07n01i03122ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p07n01i03122ent_a;
ARCHITECTURE c05s02b01x01p07n01i03122arch_a OF c05s02b01x01p07n01i03122ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p07n01i03122arch_a;
configuration c05s02b01x01p07n01i03122cfg_a of c05s02b01x01p07n01i03122ent_a is
for c05s02b01x01p07n01i03122arch_a
end for;
end c05s02b01x01p07n01i03122cfg_a;
--
ENTITY c05s02b01x01p07n01i03122ent IS
END c05s02b01x01p07n01i03122ent;
ARCHITECTURE c05s02b01x01p07n01i03122arch OF c05s02b01x01p07n01i03122ent IS
component ic_socket
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : ic_socket
generic map ( true )
port map (s1, s2);
u2 : ic_socket
generic map ( true )
port map (s2, s3);
u3 : ic_socket
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p07n01i03122"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p07n01i03122 - Explicitly OPEN entity aspects in configuration blocks test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p07n01i03122arch;
configuration c05s02b01x01p07n01i03122cfg of c05s02b01x01p07n01i03122ent is
for c05s02b01x01p07n01i03122arch
for all : ic_socket use OPEN;
end for;
end for;
end c05s02b01x01p07n01i03122cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3122.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b01x01p07n01i03122ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b01x01p07n01i03122ent_a;
ARCHITECTURE c05s02b01x01p07n01i03122arch_a OF c05s02b01x01p07n01i03122ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b01x01p07n01i03122arch_a;
configuration c05s02b01x01p07n01i03122cfg_a of c05s02b01x01p07n01i03122ent_a is
for c05s02b01x01p07n01i03122arch_a
end for;
end c05s02b01x01p07n01i03122cfg_a;
--
ENTITY c05s02b01x01p07n01i03122ent IS
END c05s02b01x01p07n01i03122ent;
ARCHITECTURE c05s02b01x01p07n01i03122arch OF c05s02b01x01p07n01i03122ent IS
component ic_socket
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : ic_socket
generic map ( true )
port map (s1, s2);
u2 : ic_socket
generic map ( true )
port map (s2, s3);
u3 : ic_socket
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b01x01p07n01i03122"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b01x01p07n01i03122 - Explicitly OPEN entity aspects in configuration blocks test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b01x01p07n01i03122arch;
configuration c05s02b01x01p07n01i03122cfg of c05s02b01x01p07n01i03122ent is
for c05s02b01x01p07n01i03122arch
for all : ic_socket use OPEN;
end for;
end for;
end c05s02b01x01p07n01i03122cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2817.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity NULL is
end NULL;
ENTITY c13s09b00x00p99n01i02817ent IS
END c13s09b00x00p99n01i02817ent;
ARCHITECTURE c13s09b00x00p99n01i02817arch OF c13s09b00x00p99n01i02817ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02817 - Reserved word NULL can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02817arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2817.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity NULL is
end NULL;
ENTITY c13s09b00x00p99n01i02817ent IS
END c13s09b00x00p99n01i02817ent;
ARCHITECTURE c13s09b00x00p99n01i02817arch OF c13s09b00x00p99n01i02817ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02817 - Reserved word NULL can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02817arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2817.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity NULL is
end NULL;
ENTITY c13s09b00x00p99n01i02817ent IS
END c13s09b00x00p99n01i02817ent;
ARCHITECTURE c13s09b00x00p99n01i02817arch OF c13s09b00x00p99n01i02817ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02817 - Reserved word NULL can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02817arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc792.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b02x00p03n01i00792pkg is
constant k : integer := 5;
function wired_and (sig : bit_vector) return bit;
end c01s01b02x00p03n01i00792pkg;
package body c01s01b02x00p03n01i00792pkg is
function wired_and (sig : bit_vector) return bit is
begin
return '0';
end wired_and;
end c01s01b02x00p03n01i00792pkg;
ENTITY c01s01b02x00p03n01i00792ent_1 IS
GENERIC (CONSTANT a : bit);
ALIAS alias_identifier : bit IS a ;
END c01s01b02x00p03n01i00792ent_1 ;
ENTITY c01s01b02x00p03n01i00792ent_2 IS
GENERIC (CONSTANT a : bit);
ATTRIBUTE my_name : integer;
END c01s01b02x00p03n01i00792ent_2 ;
ENTITY c01s01b02x00p03n01i00792ent_4 IS
GENERIC (CONSTANT a : bit);
USE work.c01s01b02x00p03n01i00792pkg.ALL;
END c01s01b02x00p03n01i00792ent_4 ;
use work.c01s01b02x00p03n01i00792pkg.all;
ENTITY c01s01b02x00p03n01i00792ent_5 IS
port (signal a : in wired_and bit bus);
DISCONNECT a:bit AFTER 100 ns;
END c01s01b02x00p03n01i00792ent_5 ;
--------------------------------
ENTITY c01s01b02x00p03n01i00792ent IS
END c01s01b02x00p03n01i00792ent;
ARCHITECTURE c01s01b02x00p03n01i00792arch OF c01s01b02x00p03n01i00792ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b02x00p03n01i00792"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00792arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc792.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b02x00p03n01i00792pkg is
constant k : integer := 5;
function wired_and (sig : bit_vector) return bit;
end c01s01b02x00p03n01i00792pkg;
package body c01s01b02x00p03n01i00792pkg is
function wired_and (sig : bit_vector) return bit is
begin
return '0';
end wired_and;
end c01s01b02x00p03n01i00792pkg;
ENTITY c01s01b02x00p03n01i00792ent_1 IS
GENERIC (CONSTANT a : bit);
ALIAS alias_identifier : bit IS a ;
END c01s01b02x00p03n01i00792ent_1 ;
ENTITY c01s01b02x00p03n01i00792ent_2 IS
GENERIC (CONSTANT a : bit);
ATTRIBUTE my_name : integer;
END c01s01b02x00p03n01i00792ent_2 ;
ENTITY c01s01b02x00p03n01i00792ent_4 IS
GENERIC (CONSTANT a : bit);
USE work.c01s01b02x00p03n01i00792pkg.ALL;
END c01s01b02x00p03n01i00792ent_4 ;
use work.c01s01b02x00p03n01i00792pkg.all;
ENTITY c01s01b02x00p03n01i00792ent_5 IS
port (signal a : in wired_and bit bus);
DISCONNECT a:bit AFTER 100 ns;
END c01s01b02x00p03n01i00792ent_5 ;
--------------------------------
ENTITY c01s01b02x00p03n01i00792ent IS
END c01s01b02x00p03n01i00792ent;
ARCHITECTURE c01s01b02x00p03n01i00792arch OF c01s01b02x00p03n01i00792ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b02x00p03n01i00792"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00792arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc792.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b02x00p03n01i00792pkg is
constant k : integer := 5;
function wired_and (sig : bit_vector) return bit;
end c01s01b02x00p03n01i00792pkg;
package body c01s01b02x00p03n01i00792pkg is
function wired_and (sig : bit_vector) return bit is
begin
return '0';
end wired_and;
end c01s01b02x00p03n01i00792pkg;
ENTITY c01s01b02x00p03n01i00792ent_1 IS
GENERIC (CONSTANT a : bit);
ALIAS alias_identifier : bit IS a ;
END c01s01b02x00p03n01i00792ent_1 ;
ENTITY c01s01b02x00p03n01i00792ent_2 IS
GENERIC (CONSTANT a : bit);
ATTRIBUTE my_name : integer;
END c01s01b02x00p03n01i00792ent_2 ;
ENTITY c01s01b02x00p03n01i00792ent_4 IS
GENERIC (CONSTANT a : bit);
USE work.c01s01b02x00p03n01i00792pkg.ALL;
END c01s01b02x00p03n01i00792ent_4 ;
use work.c01s01b02x00p03n01i00792pkg.all;
ENTITY c01s01b02x00p03n01i00792ent_5 IS
port (signal a : in wired_and bit bus);
DISCONNECT a:bit AFTER 100 ns;
END c01s01b02x00p03n01i00792ent_5 ;
--------------------------------
ENTITY c01s01b02x00p03n01i00792ent IS
END c01s01b02x00p03n01i00792ent;
ARCHITECTURE c01s01b02x00p03n01i00792arch OF c01s01b02x00p03n01i00792ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b02x00p03n01i00792"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b02x00p03n01i00792arch;
|
-- File: ./ex-target/WordContextUpdated.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon Oct 5 14:15:05 2015
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity WordContextUpdated is
port (
y: inout signed (15 downto 0);
error: out signed (15 downto 0);
new_word_embv: out unsigned(47 downto 0);
new_context_embv: out unsigned(47 downto 0);
y_actual: in signed (15 downto 0);
word_embv: inout unsigned(47 downto 0);
context_embv: inout unsigned(47 downto 0)
);
end entity WordContextUpdated;
-- Word-context embeddings updated model.
--
-- :param y: return relu(dot(word_emb, context_emb)) as fixbv
-- :param error: return MSE prediction error as fixbv
-- :param new_word_embv: return updated word embedding vector of fixbv
-- :param new_context_embv: return updated context embedding vector of fixbv
-- :param y_actual: actual training value as fixbv
-- :param word_embv: word embedding vector of fixbv
-- :param context_embv: context embedding vector of fixbv
-- :param embedding_dim: embedding dimensionality
-- :param leaky_val: factor for leaky ReLU, 0.0 without
-- :param rate_val: learning rate factor
-- :param fix_min: fixbv min value
-- :param fix_max: fixbv max value
-- :param fix_res: fixbv resolution
architecture MyHDL of WordContextUpdated is
signal y_dcontext_vec: unsigned(47 downto 0);
signal y_dword_vec: unsigned(47 downto 0);
signal wcprod_y_dot_dword_vec: unsigned(47 downto 0);
signal wcprod_y_dot: signed (15 downto 0);
signal wcprod_y_relu_dx: signed (15 downto 0);
signal wcprod_y_dot_dcontext_vec: unsigned(47 downto 0);
type t_array_y_dcontext_list is array(0 to 3-1) of signed (15 downto 0);
signal y_dcontext_list: t_array_y_dcontext_list;
type t_array_context_emb is array(0 to 3-1) of signed (15 downto 0);
signal context_emb: t_array_context_emb;
type t_array_word_emb is array(0 to 3-1) of signed (15 downto 0);
signal word_emb: t_array_word_emb;
type t_array_y_dword_list is array(0 to 3-1) of signed (15 downto 0);
signal y_dword_list: t_array_y_dword_list;
type t_array_wcprod_y_dot_dword_list is array(0 to 3-1) of signed (15 downto 0);
signal wcprod_y_dot_dword_list: t_array_wcprod_y_dot_dword_list;
type t_array_wcprod_y_dot_dcontext_list is array(0 to 3-1) of signed (15 downto 0);
signal wcprod_y_dot_dcontext_list: t_array_wcprod_y_dot_dcontext_list;
type t_array_wcprod_dot_a_list is array(0 to 3-1) of signed (15 downto 0);
signal wcprod_dot_a_list: t_array_wcprod_dot_a_list;
type t_array_wcprod_dot_b_list is array(0 to 3-1) of signed (15 downto 0);
signal wcprod_dot_b_list: t_array_wcprod_dot_b_list;
begin
context_embv(48-1 downto 32) <= None;
context_embv(32-1 downto 16) <= None;
context_embv(16-1 downto 0) <= None;
word_embv(48-1 downto 32) <= None;
word_embv(32-1 downto 16) <= None;
word_embv(16-1 downto 0) <= None;
y_dcontext_list(0) <= y_dcontext_vec(16-1 downto 0);
y_dcontext_list(1) <= y_dcontext_vec(32-1 downto 16);
y_dcontext_list(2) <= y_dcontext_vec(48-1 downto 32);
context_emb(0) <= context_embv(16-1 downto 0);
context_emb(1) <= context_embv(32-1 downto 16);
context_emb(2) <= context_embv(48-1 downto 32);
word_emb(0) <= word_embv(16-1 downto 0);
word_emb(1) <= word_embv(32-1 downto 16);
word_emb(2) <= word_embv(48-1 downto 32);
y_dword_list(0) <= y_dword_vec(16-1 downto 0);
y_dword_list(1) <= y_dword_vec(32-1 downto 16);
y_dword_list(2) <= y_dword_vec(48-1 downto 32);
wcprod_y_dot_dword_list(0) <= wcprod_y_dot_dword_vec(16-1 downto 0);
wcprod_y_dot_dword_list(1) <= wcprod_y_dot_dword_vec(32-1 downto 16);
wcprod_y_dot_dword_list(2) <= wcprod_y_dot_dword_vec(48-1 downto 32);
wcprod_y_dot_dcontext_list(0) <= wcprod_y_dot_dcontext_vec(16-1 downto 0);
wcprod_y_dot_dcontext_list(1) <= wcprod_y_dot_dcontext_vec(32-1 downto 16);
wcprod_y_dot_dcontext_list(2) <= wcprod_y_dot_dcontext_vec(48-1 downto 32);
wcprod_dot_a_list(0) <= word_embv(16-1 downto 0);
wcprod_dot_a_list(1) <= word_embv(32-1 downto 16);
wcprod_dot_a_list(2) <= word_embv(48-1 downto 32);
wcprod_dot_b_list(0) <= context_embv(16-1 downto 0);
wcprod_dot_b_list(1) <= context_embv(32-1 downto 16);
wcprod_dot_b_list(2) <= context_embv(48-1 downto 32);
WORDCONTEXTUPDATED_WCPROD_DOT_DOT: process (wcprod_dot_a_list, wcprod_dot_b_list) is
variable y_sum: signed(31 downto 0);
begin
y_sum := to_signed(0.0, 32);
for j in 0 to 3-1 loop
y_sum := (y_sum + (wcprod_dot_a_list(j) * wcprod_dot_b_list(j)));
end loop;
wcprod_y_dot <= to_signed(y_sum, 16);
end process WORDCONTEXTUPDATED_WCPROD_DOT_DOT;
wcprod_y_dot_dword_vec <= context_embv;
wcprod_y_dot_dcontext_vec <= word_embv;
WORDCONTEXTUPDATED_WCPROD_RELU_RELU: process (wcprod_y_dot) is
variable zero: signed(15 downto 0);
variable leaky: signed(15 downto 0);
begin
if (wcprod_y_dot > zero) then
y <= wcprod_y_dot;
else
y <= to_signed((leaky * wcprod_y_dot), 16);
end if;
end process WORDCONTEXTUPDATED_WCPROD_RELU_RELU;
WORDCONTEXTUPDATED_WCPROD_RELU_RELU_DX: process (wcprod_y_dot) is
variable zero: signed(15 downto 0);
variable leaky: signed(15 downto 0);
variable one: signed(15 downto 0);
begin
if (wcprod_y_dot > zero) then
wcprod_y_relu_dx <= one;
else
wcprod_y_relu_dx <= leaky;
end if;
end process WORDCONTEXTUPDATED_WCPROD_RELU_RELU_DX;
WORDCONTEXTUPDATED_WCPROD_WCPROD_DWORD: process (wcprod_y_relu_dx, wcprod_y_dot_dword_list) is
variable prod: signed(15 downto 0);
begin
for j in 0 to 3-1 loop
prod := to_signed((wcprod_y_relu_dx * wcprod_y_dot_dword_list(j)), 16);
y_dword_vec(((j + 1) * 16)-1 downto (j * 16)) <= unsigned(prod);
end loop;
end process WORDCONTEXTUPDATED_WCPROD_WCPROD_DWORD;
WORDCONTEXTUPDATED_WCPROD_WCPROD_DCONTEXT: process (wcprod_y_relu_dx, wcprod_y_dot_dcontext_list) is
variable prod: signed(15 downto 0);
begin
for j in 0 to 3-1 loop
prod := to_signed((wcprod_y_relu_dx * wcprod_y_dot_dcontext_list(j)), 16);
y_dcontext_vec(((j + 1) * 16)-1 downto (j * 16)) <= unsigned(prod);
end loop;
end process WORDCONTEXTUPDATED_WCPROD_WCPROD_DCONTEXT;
WORDCONTEXTUPDATED_MSE: process (y, y_actual) is
variable diff: signed(15 downto 0);
begin
diff := to_signed((y - y_actual), 16);
error <= to_signed((diff * diff), 16);
end process WORDCONTEXTUPDATED_MSE;
WORDCONTEXTUPDATED_UPDATED_WORD: process (y, word_emb, y_actual, y_dword_list) is
variable new: signed(15 downto 0);
variable y_dword: signed(15 downto 0);
variable rate: signed(15 downto 0);
variable delta: signed(15 downto 0);
variable diff: signed(15 downto 0);
begin
diff := to_signed((y - y_actual), 16);
for j in 0 to 3-1 loop
y_dword := to_signed(y_dword_list(j), 16);
delta := to_signed(((rate * diff) * y_dword), 16);
new := to_signed((word_emb(j) - delta), 16);
new_word_embv(((j + 1) * 16)-1 downto (j * 16)) <= unsigned(new);
end loop;
end process WORDCONTEXTUPDATED_UPDATED_WORD;
WORDCONTEXTUPDATED_UPDATED_CONTEXT: process (y, y_dcontext_list, y_actual, context_emb) is
variable y_dcontext: signed(15 downto 0);
variable rate: signed(15 downto 0);
variable new: signed(15 downto 0);
variable delta: signed(15 downto 0);
variable diff: signed(15 downto 0);
begin
diff := to_signed((y - y_actual), 16);
for j in 0 to 3-1 loop
y_dcontext := to_signed(y_dcontext_list(j), 16);
delta := to_signed(((rate * diff) * y_dcontext), 16);
new := to_signed((context_emb(j) - delta), 16);
new_context_embv(((j + 1) * 16)-1 downto (j * 16)) <= unsigned(new);
end loop;
end process WORDCONTEXTUPDATED_UPDATED_CONTEXT;
end architecture MyHDL;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_9;
USE proc_sys_reset_v5_0_9.proc_sys_reset;
ENTITY design_1_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_processing_system7_0_100M_0;
ARCHITECTURE design_1_rst_processing_system7_0_100M_0_arch OF design_1_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_processing_system7_0_100M_0_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cycloneiii_ddr_phy
-- File: cycloneiii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_cyciii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT cycloneiii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "cycloneiii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "cycloneiii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_cyciii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_cyciii_io2a_dqsbusout;
dqs_update <= wire_cyciii_dll1_dqsupdate;
dqsundelayedout <= wire_cyciii_io2a_combout;
offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
cyciii_dll1 : cycloneiii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_cyciii_dll1_delayctrlout,
dqsupdate => wire_cyciii_dll1_dqsupdate,
offsetctrlout => wire_cyciii_dll1_offsetctrlout
);
wire_cyciii_io2a_datain <= dqs_datain_h;
wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
wire_cyciii_io2a_oe <= oe;
wire_cyciii_io2a_outclk <= outclk;
wire_cyciii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
cyciii_io2a : cycloneiii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_cyciii_io2a_combout(i),
datain => wire_cyciii_io2a_datain(i),
ddiodatain => wire_cyciii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_cyciii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_cyciii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_cyciii_io2a_outclk(i),
outclkena => wire_cyciii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_cyciii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_cyciii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_cyciii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_cyciii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "CycloneIII",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst, lockl)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => casn, datain_l(0) => casn,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => wen, datain_l(0) => wen,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0),
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
|
--==============================================================================
-- CERN (BE-CO-HT)
-- Glitch filter with selectable length
--==============================================================================
--
-- author: Theodor Stana ([email protected])
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
-- Glitch filter consisting of a set of chained flip-flops followed by a
-- comparator. The comparator toggles to '1' when all FFs in the chain are
-- '1' and respectively to '0' when all the FFS in the chain are '0'.
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana [email protected] File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity gc_glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input, synchronous to clk_i
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end entity gc_glitch_filt;
architecture behav of gc_glitch_filt is
--============================================================================
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Glitch filtration logic
--============================================================================
glitch_filt(0) <= dat_i;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
p_glitch_filt: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
glitch_filt(g_len downto 1) <= (others => '0');
else
glitch_filt(g_len downto 1) <= glitch_filt(g_len-1 downto 0);
end if;
end if;
end process p_glitch_filt;
end generate gen_glitch_filt;
-- and set the data output based on the state of the glitch filter
p_output: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
dat_o <= '0';
elsif (unsigned(glitch_filt) = (glitch_filt'range => '1')) then
dat_o <= '1';
elsif (unsigned(glitch_filt) = (glitch_filt'range => '0')) then
dat_o <= '0';
end if;
end if;
end process p_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
|
--------------------------------------------------------------------------------
-- FILE: FwdMux2
-- DESC: Forward Multiplexer with 2 stage forward.
--
-- Author:
-- Create: 2015-06-01
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity FwdMux2 is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_ADDR_SIZE : integer := MyLog2Ceil(C_REG_NUM)
);
port(
reg_c : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_f : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_ff : in std_logic_vector(DATA_SIZE-1 downto 0);
addr_c : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_f : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_ff : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
valid_f : in std_logic;
valid_ff: in std_logic;
dirty_f : in std_logic;
dirty_ff: in std_logic;
en : in std_logic:='1';
output : out std_logic_vector(DATA_SIZE-1 downto 0);
match_dirty_f : out std_logic;
match_dirty_ff : out std_logic
);
end FwdMux2;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture fwd_mux_2_arch of FwdMux2 is
begin
P0: process(en, reg_c, reg_f, reg_ff, addr_c, addr_f, addr_ff, valid_f, valid_ff, dirty_f, dirty_ff)
variable dmatchf: std_logic:='0';
variable dmatchff: std_logic:='0';
begin
dmatchf:='0';
dmatchff:='0';
if en='1' then
if addr_c=(addr_c'range=>'0') then
output <= reg_c;
else
if (addr_c=addr_f) and (valid_f='1') then
if dirty_f='1' then
dmatchf := '1';
end if;
output <= reg_f;
elsif (addr_c=addr_ff) and (valid_ff='1') then
if dirty_ff='1' then
dmatchff := '1';
end if;
output <= reg_ff;
else
output <= reg_c;
end if;
end if;
match_dirty_f <= dmatchf;
match_dirty_ff <= dmatchff;
end if;
end process;
end fwd_mux_2_arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF2_4.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF2_4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_1 : IN std_logic; -- ufix1
dout_1_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_1_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_9_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_9_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_1_im_1 : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_2_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_2_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4 IS
-- Signals
SIGNAL dout_1_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_1_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_9_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_9_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21_En13
SIGNAL dout_1_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_1_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_2_re_tmp : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL dout_2_im_tmp : signed(19 DOWNTO 0); -- sfix20_En13
BEGIN
dout_1_re_signed <= signed(dout_1_re);
din1_re <= resize(dout_1_re_signed, 20);
dout_1_im_signed <= signed(dout_1_im);
din1_im <= resize(dout_1_im_signed, 20);
dout_9_re_signed <= signed(dout_9_re);
din2_re <= resize(dout_9_re_signed, 20);
dout_9_im_signed <= signed(dout_9_im);
din2_im <= resize(dout_9_im_signed, 20);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 21);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 21);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_1)
VARIABLE add_cast : signed(20 DOWNTO 0);
VARIABLE add_cast_0 : signed(20 DOWNTO 0);
VARIABLE add_cast_1 : signed(20 DOWNTO 0);
VARIABLE add_cast_2 : signed(20 DOWNTO 0);
VARIABLE sub_cast : signed(20 DOWNTO 0);
VARIABLE sub_cast_0 : signed(20 DOWNTO 0);
VARIABLE sub_cast_1 : signed(20 DOWNTO 0);
VARIABLE sub_cast_2 : signed(20 DOWNTO 0);
VARIABLE add_cast_3 : signed(20 DOWNTO 0);
VARIABLE add_cast_4 : signed(20 DOWNTO 0);
VARIABLE add_cast_5 : signed(20 DOWNTO 0);
VARIABLE add_cast_6 : signed(20 DOWNTO 0);
VARIABLE sub_cast_3 : signed(20 DOWNTO 0);
VARIABLE sub_cast_4 : signed(20 DOWNTO 0);
VARIABLE sub_cast_5 : signed(20 DOWNTO 0);
VARIABLE sub_cast_6 : signed(20 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_1 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(din1_re, 21);
add_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(din1_re, 21);
sub_cast_2 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(din1_im, 21);
add_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(din1_im, 21);
sub_cast_6 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(din1_re, 21);
add_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(din1_re, 21);
sub_cast_0 := resize(din2_re, 21);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(din1_im, 21);
add_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(din1_im, 21);
sub_cast_4 := resize(din2_im, 21);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
dout_1_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(19 DOWNTO 0);
dout_1_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(19 DOWNTO 0);
dout_2_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(19 DOWNTO 0);
dout_2_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(19 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_2_re <= std_logic_vector(dout_2_re_tmp);
dout_2_im <= std_logic_vector(dout_2_im_tmp);
dout_1_re_1 <= std_logic_vector(dout_1_re_tmp);
dout_1_im_1 <= std_logic_vector(dout_1_im_tmp);
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
generic (NUM_CHANNELS : natural := 4);
port (
iar : in unsigned(15 downto 0);
ipend : in unsigned(NUM_CHANNELS-1 downto 0);
irq : out unsigned(3 downto 0);
clk : in std_logic
);
end;
architecture a of ent is
type irq_t is
array (integer range 0 to 4-1) of unsigned(NUM_CHANNELS-1 downto 0);
signal imap : irq_t;
function or_reduce (v: in unsigned) return std_logic is
variable rv : std_logic := '0';
begin
for i in v'range loop
rv := rv or v(i);
end loop;
return rv;
end function;
begin
gen_irqmap:
for i in 0 to 4-1 generate
irq(i) <= or_reduce(imap(i));
end generate;
irq_map:
process (clk)
variable itmp : irq_t := (others => (others => '0'));
begin
-- IRQ channel assignment:
if rising_edge(clk) then
for i in 0 to NUM_CHANNELS-1 loop
itmp(to_integer(iar(i*2+1 downto i*2)))(i) := ipend(i);
end loop;
imap <= itmp;
end if;
end process;
end;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_qspi_enhanced_mode.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- enhanced mode with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of xps_spi.
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- SK 12/12/11
-- 1. First introduction of AXI4 full in v3_1 version of axi_quad_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.srl_fifo_f;
library interrupt_control_v3_0;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
entity axi_qspi_enhanced_mode is
generic (
-- General Parameters
C_FAMILY : string := "virtex7";
C_SUB_FAMILY : string := "virtex7";
-------------------------
C_AXI4_CLK_PS : integer := 10000;--AXI clock period
C_EXT_SPI_CLK_PS : integer := 10000;--ext clock period
C_FIFO_DEPTH : integer := 16;-- allowed 0,16,256.
C_SCK_RATIO : integer := 16;--default in legacy mode
C_NUM_SS_BITS : integer range 1 to 32:= 1;
C_NUM_TRANSFER_BITS : integer := 8; -- allowed 8, 16, 32
-------------------------
C_SPI_MODE : integer range 0 to 2 := 0; -- used for differentiating
C_USE_STARTUP : integer range 0 to 1 := 1; --
C_SPI_MEMORY : integer range 0 to 2 := 1; -- 0 - mixed mode,
-------------------------
-- AXI4 Full Interface Parameters
--*C_S_AXI4_ADDR_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ADDR_WIDTH : integer range 24 to 24 := 24;
C_S_AXI4_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI4_ID_WIDTH : integer range 1 to 16 := 4;
-------------------------
--C_AXI4_BASEADDR : std_logic_vector := x"FFFFFFFF";
--C_AXI4_HIGHADDR : std_logic_vector := x"00000000";
-------------------------
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_S_AXI_SPI_MIN_SIZE : std_logic_vector(31 downto 0):= X"0000007c";
C_SPI_MEM_ADDR_BITS : integer -- newly added
);
port (
-- external async clock for SPI interface logic
EXT_SPI_CLK : in std_logic;
S_AXI4_ACLK : in std_logic;
S_AXI4_ARESETN : in std_logic;
-------------------------------
-------------------------------
--*AXI4 Full port interface* --
-------------------------------
------------------------------------
-- AXI Write Address Channel Signals
------------------------------------
S_AXI4_AWID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_AWADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_AWLEN : in std_logic_vector(7 downto 0);
S_AXI4_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI4_AWBURST : in std_logic_vector(1 downto 0);
S_AXI4_AWLOCK : in std_logic; -- not supported in design
S_AXI4_AWCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_AWPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_AWVALID : in std_logic;
S_AXI4_AWREADY : out std_logic;
---------------------------------------
-- AXI4 Full Write Data Channel Signals
---------------------------------------
S_AXI4_WDATA : in std_logic_vector((C_S_AXI4_DATA_WIDTH-1)downto 0);
S_AXI4_WSTRB : in std_logic_vector(((C_S_AXI4_DATA_WIDTH/8)-1) downto 0);
S_AXI4_WLAST : in std_logic;
S_AXI4_WVALID : in std_logic;
S_AXI4_WREADY : out std_logic;
-------------------------------------------
-- AXI4 Full Write Response Channel Signals
-------------------------------------------
S_AXI4_BID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_BRESP : out std_logic_vector(1 downto 0);
S_AXI4_BVALID : out std_logic;
S_AXI4_BREADY : in std_logic;
-----------------------------------
-- AXI Read Address Channel Signals
-----------------------------------
S_AXI4_ARID : in std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_ARADDR : in std_logic_vector((C_SPI_MEM_ADDR_BITS-1) downto 0);--((C_S_AXI4_ADDR_WIDTH-1) downto 0);
S_AXI4_ARLEN : in std_logic_vector(7 downto 0);
S_AXI4_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI4_ARBURST : in std_logic_vector(1 downto 0);
S_AXI4_ARLOCK : in std_logic; -- not supported in design
S_AXI4_ARCACHE : in std_logic_vector(3 downto 0);-- not supported in design
S_AXI4_ARPROT : in std_logic_vector(2 downto 0);-- not supported in design
S_AXI4_ARVALID : in std_logic;
S_AXI4_ARREADY : out std_logic;
--------------------------------
-- AXI Read Data Channel Signals
--------------------------------
S_AXI4_RID : out std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
S_AXI4_RDATA : out std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
S_AXI4_RRESP : out std_logic_vector(1 downto 0);
S_AXI4_RLAST : out std_logic;
S_AXI4_RVALID : out std_logic;
S_AXI4_RREADY : in std_logic;
--------------------------------
Bus2IP_Clk : out std_logic;
Bus2IP_Reset : out std_logic;
--Bus2IP_Addr : out std_logic_vector
-- (C_S_AXI4_ADDR_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI4_DATA_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI4_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI4_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic;
---------------------------------
burst_tr : out std_logic;
rready : out std_logic
);
end entity axi_qspi_enhanced_mode;
architecture imp of axi_qspi_enhanced_mode is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- constant declaration
constant ACTIVE_LOW_RESET : std_logic := '0';
-- local type declarations
type STATE_TYPE is (
IDLE,
AXI_SINGLE_RD,
AXI_RD,
AXI_SINGLE_WR,
AXI_WR,
CHECK_AXI_LENGTH_ERROR,
AX_WRONG_BURST_TYPE,
WR_RESP_1,
WR_RESP_2,
RD_RESP_1,RD_LAST,
RD_RESP_2,
ERROR_RESP,
RD_ERROR_RESP
);
-- Signal Declaration
-----------------------------
signal axi_full_sm_ps : STATE_TYPE;
signal axi_full_sm_ns : STATE_TYPE;
-- function declaration
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
-- code coverage -- function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
-- code coverage -- variable i : integer := 0;
-- code coverage -- begin
-- code coverage -- for i in 31 downto 0 loop
-- code coverage -- if y(i)='1' then
-- code coverage -- return (i);
-- code coverage -- end if;
-- code coverage -- end loop;
-- code coverage -- return -1;
-- code coverage -- end function Get_Addr_Bits;
-- constant declaration
constant C_ADDR_DECODE_BITS : integer := 6; -- Get_Addr_Bits(C_S_AXI_SPI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector(31 downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-- type decode_bit_array_type is Array(natural range 0 to (
-- (C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
-- integer;
-- type short_addr_array_type is Array(natural range 0 to
-- C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
-- std_logic_vector(0 to(C_ADDR_DECODE_BITS-1));
-- signal declaration
signal axi_size_reg : std_logic_vector(2 downto 0);
signal axi_size_cmb : std_logic_vector(2 downto 0);
signal bus2ip_rnw_i : std_logic;
signal bus2ip_addr_i : std_logic_vector(31 downto 0); -- (31 downto 0); -- 8/18/2013
signal wr_transaction : std_logic;
signal wr_addr_transaction : std_logic;
signal arready_i : std_logic;
signal awready_i, s_axi_wready_i : std_logic;
signal S_AXI4_RID_reg : std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
signal S_AXI4_BID_reg : std_logic_vector((C_S_AXI4_ID_WIDTH-1) downto 0);
signal s_axi_mem_bresp_reg : std_logic_vector(2 downto 0);
signal axi_full_sm_ps_IDLE_cmb : std_logic;
signal s_axi_mem_bvalid_reg : std_logic;
signal bus2ip_BE_reg : std_logic_vector(((C_S_AXI4_DATA_WIDTH/8) - 1) downto 0);
signal axi_length_cmb : std_logic_vector(7 downto 0);
signal axi_length_reg : std_logic_vector(7 downto 0);
signal burst_transfer_cmb : std_logic;
signal burst_transfer_reg : std_logic;
signal axi_burst_cmb : std_logic_vector(1 downto 0);
signal axi_burst_reg : std_logic_vector(1 downto 0);
signal length_cntr : std_logic_vector(7 downto 0);
signal last_data_cmb : std_logic;
signal last_bt_one_data_cmb : std_logic;
signal last_data_acked : std_logic;
signal pr_state_idle : std_logic;
signal length_error : std_logic;
signal rnw_reg, rnw_cmb : std_logic;
signal arready_cmb : std_logic;
signal awready_cmb : std_logic;
signal wready_cmb : std_logic;
signal store_axi_signal_cmb : std_logic;
signal combine_ack, start, temp_i, response : std_logic;
signal s_axi4_rdata_i : std_logic_vector((C_S_AXI4_DATA_WIDTH-1) downto 0);
signal s_axi4_rresp_i : std_logic_vector(1 downto 0);
signal s_axi_rvalid_i : std_logic;
signal S_AXI4_BRESP_i : std_logic_vector(1 downto 0);
signal s_axi_bvalid_i : std_logic;
signal pr_state_length_chk : std_logic;
signal axi_full_sm_ns_IDLE_cmb : std_logic;
signal last_data_reg: std_logic;
signal rst_en : std_logic;
signal s_axi_rvalid_cmb, last_data, burst_tr_i,rready_i, store_data : std_logic;
signal Bus2IP_Reset_i : std_logic;
-----
begin
-----
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
-- REGISTERING_RESET_P: Invert the reset coming from AXI4
-----------------------
REGISTERING_RESET_P : process (S_AXI4_ACLK) is
-----
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
Bus2IP_Reset_i <= not S_AXI4_ARESETN;
end if;
end process REGISTERING_RESET_P;
Bus2IP_Reset <= Bus2IP_Reset_i;
Bus2IP_Clk <= S_AXI4_ACLK;
--Bus2IP_Resetn <= S_AXI4_ARESETN;
--bus2ip_rnw_i <= rnw_reg;-- '1' when S_AXI4_ARVALID='1' else '0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_Data <= S_AXI4_WDATA;
--Bus2IP_Addr <= bus2ip_addr_i;
wr_transaction <= S_AXI4_AWVALID and (S_AXI4_WVALID);
bus2ip_addr_i <= ZEROS & S_AXI4_ARADDR(C_ADDR_DECODE_BITS downto 0) when (S_AXI4_ARVALID='1')
else
ZEROS & S_AXI4_AWADDR(C_ADDR_DECODE_BITS downto 0);
--S_AXI4_ARADDR(C_ADDR_DECODE_BITS+1 downto 0) when (S_AXI4_ARVALID='1')
--else
--S_AXI4_AWADDR(C_ADDR_DECODE_BITS+1 downto 0);
-- read and write transactions should be separate
-- preferencec of read over write
-- only narrow transfer of 8-bit are supported
-- for 16-bit and 32-bit transactions error should be generated - dont provide these signals to internal logic
--wr_transaction <= S_AXI4_AWVALID and (S_AXI4_WVALID);
--wr_addr_transaction <= S_AXI4_AWVALID and (not S_AXI4_WVALID);
-------------------------------------------------------------------------------
AXI_ARREADY_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
arready_i <='0';
else
arready_i <= arready_cmb;
end if;
end if;
end process AXI_ARREADY_P;
--------------------------
S_AXI4_ARREADY <= arready_i; -- arready_i;--IP2Bus_RdAck; --arready_i;
--------------------------
AXI_AWREADY_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK = '1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
awready_i <='0';
else
awready_i <= awready_cmb;
end if;
end if;
end process AXI_AWREADY_P;
--------------------------
S_AXI4_AWREADY <= awready_i;
--------------------------
S_AXI4_BRESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (axi_full_sm_ps = IDLE) then
S_AXI4_BRESP_i <= (others => '0');
elsif (axi_full_sm_ps = AXI_WR) or (axi_full_sm_ps = AXI_SINGLE_WR) then
S_AXI4_BRESP_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI4_BRESP_P;
---------------------------
S_AXI4_BRESP <= S_AXI4_BRESP_i;
-------------------------------
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if S_AXI4_ARESETN = '0' then
s_axi_bvalid_i <= '0';
elsif(axi_full_sm_ps = WR_RESP_1)then
s_axi_bvalid_i <= '1';
elsif(S_AXI4_BREADY = '1')then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------
S_AXI4_BVALID <= s_axi_bvalid_i;
--------------------------------
----S_AXI_WREADY_I_P: below process provides logic for valid write response signal
---------------------
S_AXI_WREADY_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if S_AXI4_ARESETN = '0' then
s_axi_wready_i <= '0';
else
s_axi_wready_i <= wready_cmb;
end if;
end if;
end process S_AXI_WREADY_I_P;
-------------------------------
S_AXI4_WREADY <= s_axi_wready_i;
--------------------------------
-------------------------------------------------------------------------------
-- REG_BID_P,REG_RID_P: Below process makes the RID and BID '0' at POR and
-- : generate proper values based upon read/write
-- transaction
-----------------------
REG_RID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESETN = '0') then
S_AXI4_RID_reg <= (others=> '0');
elsif(store_axi_signal_cmb = '1')then
S_AXI4_RID_reg <= S_AXI4_ARID ;
end if;
end if;
end process REG_RID_P;
----------------------
S_AXI4_RID <= S_AXI4_RID_reg;
-----------------------------
REG_BID_P: process (S_AXI4_ACLK) is
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
S_AXI4_BID_reg <= (others=> '0');
elsif(store_axi_signal_cmb = '1')then
S_AXI4_BID_reg <= S_AXI4_AWID;-- and pr_state_length_chk;
end if;
end if;
end process REG_BID_P;
-----------------------
S_AXI4_BID <= S_AXI4_BID_reg;
------------------------------
------------------------
-- BUS2IP_BE_P:Register Bus2IP_BE for write strobe during write mode else '1'.
------------------------
BUS2IP_BE_P: process (S_AXI4_ACLK) is
------------
begin
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if ((Bus2IP_Reset_i = RESET_ACTIVE)) then
bus2ip_BE_reg <= (others => '0');
else
if (rnw_cmb = '0'-- and
--(wready_cmb = '1')
) then
bus2ip_BE_reg <= S_AXI4_WSTRB;
else -- if(rnw_cmb = '1') then
bus2ip_BE_reg <= (others => '1');
end if;
end if;
end if;
end process BUS2IP_BE_P;
------------------------
Bus2IP_BE <= bus2ip_BE_reg;
axi_length_cmb <= S_AXI4_ARLEN when (rnw_cmb = '1')
else
S_AXI4_AWLEN;
burst_transfer_cmb <= (or_reduce(axi_length_cmb));
BURST_LENGTH_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
axi_length_reg <= (others => '0');
burst_transfer_reg <= '0';
elsif((store_axi_signal_cmb = '1'))then
axi_length_reg <= axi_length_cmb;
burst_transfer_reg <= burst_transfer_cmb;
end if;
end if;
end process BURST_LENGTH_REG_P;
-----------------------
burst_tr_i <= burst_transfer_reg;
burst_tr <= burst_tr_i;
-------------------------------------------------------------------------------
axi_size_cmb <= S_AXI4_ARSIZE(2 downto 0) when (rnw_cmb = '1')
else
S_AXI4_AWSIZE(2 downto 0);
SIZE_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN=ACTIVE_LOW_RESET) then
axi_size_reg <= (others => '0');
elsif((store_axi_signal_cmb = '1'))then
axi_size_reg <= axi_size_cmb;
end if;
end if;
end process SIZE_REG_P;
-----------------------
axi_burst_cmb <= S_AXI4_ARBURST when (rnw_cmb = '1')
else
S_AXI4_AWBURST;
BURST_REG_P:process(S_AXI4_ACLK)is
-----
begin
-----
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN = ACTIVE_LOW_RESET) then
axi_burst_reg <= (others => '0');
elsif(store_axi_signal_cmb = '1')then
axi_burst_reg <= axi_burst_cmb;
end if;
end if;
end process BURST_REG_P;
-----------------------
combine_ack <= IP2Bus_WrAck or IP2Bus_RdAck;
--------------------------------------------
LENGTH_CNTR_P:process(S_AXI4_ACLK)is
begin
if(S_AXI4_ACLK'event and S_AXI4_ACLK='1')then
if (S_AXI4_ARESETN = ACTIVE_LOW_RESET) then
length_cntr <= (others => '0');
elsif((store_axi_signal_cmb = '1'))then
length_cntr <= axi_length_cmb;
elsif (wready_cmb = '1' and S_AXI4_WVALID = '1') or
(S_AXI4_RREADY = '1' and s_axi_rvalid_i = '1') then -- burst length error
length_cntr <= length_cntr - '1';
end if;
end if;
end process LENGTH_CNTR_P;
--------------------------
--last_data_cmb <= or_reduce(length_cntr(7 downto 1)) and length_cntr(1);
rready <= rready_i;
last_bt_one_data_cmb <= not(or_reduce(length_cntr(7 downto 1))) and length_cntr(0) and S_AXI4_RREADY;
last_data_cmb <= not(or_reduce(length_cntr(7 downto 0)));
--temp_i <= (combine_ack and last_data_reg)or rst_en;
LAST_DATA_ACKED_P: process (S_AXI4_ACLK) is
-----------------
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if(axi_full_sm_ps_IDLE_cmb = '1') then
last_data_acked <= '0';
elsif(burst_tr_i = '0')then
if(S_AXI4_RREADY = '1' and last_data_acked = '1')then
last_data_acked <= '0';
else
last_data_acked <= last_data_cmb and s_axi_rvalid_cmb;
end if;
else
if(S_AXI4_RREADY = '1' and last_data_acked = '1') then
last_data_acked <= '0';
elsif(S_AXI4_RREADY = '0' and last_data_acked = '1')then
last_data_acked <= '1';
else
last_data_acked <= last_data and s_axi_rvalid_i and S_AXI4_RREADY;
end if;
end if;
end if;
end process LAST_DATA_ACKED_P;
------------------------------
S_AXI4_RLAST <= last_data_acked;
--------------------------------
-- S_AXI4_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI4_RDATA_RESP_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (S_AXI4_ARESETN = '0') then
S_AXI4_RRESP_i <= (others => '0');
S_AXI4_RDATA_i <= (others => '0');
elsif(S_AXI4_RREADY = '1' )or(store_data = '1') then --if --((axi_full_sm_ps = AXI_SINGLE_RD) or (axi_full_sm_ps = AXI_BURST_RD)) then
S_AXI4_RRESP_i <= (IP2Bus_Error) & '0';
S_AXI4_RDATA_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI4_RDATA_RESP_P;
S_AXI4_RRESP <= S_AXI4_RRESP_i;
S_AXI4_RDATA <= S_AXI4_RDATA_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI4_ACLK) is
begin
if S_AXI4_ACLK'event and S_AXI4_ACLK = '1' then
if (axi_full_sm_ps = IDLE) then
s_axi_rvalid_i <= '0';
elsif(S_AXI4_RREADY = '0') and (s_axi_rvalid_i = '1') then
s_axi_rvalid_i <= s_axi_rvalid_i;
else
s_axi_rvalid_i <= s_axi_rvalid_cmb;
end if;
end if;
end process S_AXI_RVALID_I_P;
-----------------------------
S_AXI4_RVALID <= s_axi_rvalid_i;
-- -----------------------------
-- Addr_int <= S_AXI_ARADDR when(rnw_cmb_dup = '1')
-- else
-- S_AXI_AWADDR;
axi_full_sm_ns_IDLE_cmb <= '1' when (axi_full_sm_ns = IDLE) else '0';
axi_full_sm_ps_IDLE_cmb <= '1' when (axi_full_sm_ps = IDLE) else '0';
pr_state_idle <= '1' when axi_full_sm_ps = IDLE else '0';
pr_state_length_chk <= '1' when axi_full_sm_ps = CHECK_AXI_LENGTH_ERROR
else
'0';
REGISTER_LOWER_ADDR_BITS_P:process(S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (axi_full_sm_ps_IDLE_cmb = '1') then
length_error <= '0';
elsif(burst_transfer_cmb = '1')then -- means its a burst
--if (bus2ip_addr_i (7 downto 3) = "01101")then
if (bus2ip_addr_i (6 downto 3) = "1101")then
length_error <= '0';
else
length_error <= '1';
end if;
end if;
end if;
end process REGISTER_LOWER_ADDR_BITS_P;
---------------------------------------
-- length_error <= '0';
---------------------------
REG_P: process (S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
axi_full_sm_ps <= IDLE;
last_data_reg <= '0';
else
axi_full_sm_ps <= axi_full_sm_ns;
last_data_reg <= last_data_cmb;
end if;
end if;
end process REG_P;
-------------------------------------------------------
STORE_SIGNALS_P: process (S_AXI4_ACLK) is
begin
-----
if (S_AXI4_ACLK'event and S_AXI4_ACLK='1') then
if (Bus2IP_Reset_i = RESET_ACTIVE) then
rnw_reg <= '0';
else-- if(store_axi_signal_cmb = '1')then
rnw_reg <= rnw_cmb;
end if;
end if;
end process STORE_SIGNALS_P;
-------------------------------------------------------
AXI_FULL_STATE_MACHINE_P:process(
axi_full_sm_ps ,
S_AXI4_ARVALID ,
S_AXI4_AWVALID ,
S_AXI4_WVALID ,
S_AXI4_BREADY ,
S_AXI4_RREADY ,
wr_transaction ,
wr_addr_transaction ,
length_error ,
IP2Bus_WrAck ,
last_data_cmb ,
IP2Bus_RdAck ,
IP2Bus_Error ,
burst_transfer_cmb ,
last_bt_one_data_cmb ,
rnw_reg ,
length_cntr
)is
-----
begin
-----
arready_cmb <= '0';
awready_cmb <= '0';
wready_cmb <= '0';
start <= '0';
rst_en <= '0';
temp_i <= '0';
store_axi_signal_cmb <= '0';
s_axi_rvalid_cmb <= '0';
rready_i <= '0';
rnw_cmb <= '0';
last_data <= '0';
store_data <= '0';
case axi_full_sm_ps is
when IDLE => if(S_AXI4_ARVALID = '1') then
start <= '1';
store_axi_signal_cmb <= '1';
arready_cmb <= '1';
if(burst_transfer_cmb = '1') then
axi_full_sm_ns <= AXI_RD;
else
axi_full_sm_ns <= AXI_SINGLE_RD;
end if;
elsif(wr_transaction = '1')then
start <= '1';
store_axi_signal_cmb <= '1';
if(burst_transfer_cmb = '1') then
awready_cmb <= '1';
wready_cmb <= '1';
axi_full_sm_ns <= AXI_WR;
else
axi_full_sm_ns <= AXI_SINGLE_WR;
end if;
else
axi_full_sm_ns <= IDLE;
end if;
rnw_cmb <= S_AXI4_ARVALID and (not S_AXI4_AWVALID);
------------------------------
when CHECK_AXI_LENGTH_ERROR => if (length_error = '0') then
if(rnw_reg = '1')then
arready_cmb <= '1';
axi_full_sm_ns <= AXI_RD;
else
awready_cmb <= '1';
axi_full_sm_ns <= AXI_WR;
end if;
start <= '1';
else
axi_full_sm_ns <= ERROR_RESP;
end if;
---------------------------------------------------------
when AXI_SINGLE_RD => --arready_cmb <= IP2Bus_RdAck;
s_axi_rvalid_cmb <= IP2Bus_RdAck or IP2Bus_Error;
temp_i <= IP2Bus_RdAck or IP2Bus_Error;
rready_i <= '1';
if(IP2Bus_RdAck = '1')or (IP2Bus_Error = '1') then
store_data <= not S_AXI4_RREADY;
axi_full_sm_ns <= RD_LAST;
else
axi_full_sm_ns <= AXI_SINGLE_RD;
end if;
rnw_cmb <= rnw_reg;
when AXI_RD =>
rready_i <= S_AXI4_RREADY and not last_data_cmb;
last_data <= last_bt_one_data_cmb;
if(last_data_cmb = '1') then
if(S_AXI4_RREADY = '1')then
temp_i <= '1';--IP2Bus_RdAck;--IP2Bus_WrAck;
rst_en <= '1';--IP2Bus_RdAck;--IP2Bus_WrAck;
axi_full_sm_ns <= IDLE;
else
s_axi_rvalid_cmb <= not S_AXI4_RREADY;
last_data <= not S_AXI4_RREADY;
temp_i <= '1';
axi_full_sm_ns <= RD_LAST;
end if;
else
s_axi_rvalid_cmb <= IP2Bus_RdAck or IP2Bus_Error; -- not last_data_cmb;
axi_full_sm_ns <= AXI_RD;
end if;
rnw_cmb <= rnw_reg;
----------------------------------------------------------
when AXI_SINGLE_WR => awready_cmb <= IP2Bus_WrAck or IP2Bus_Error;
wready_cmb <= IP2Bus_WrAck or IP2Bus_Error;
temp_i <= IP2Bus_WrAck or IP2Bus_Error;
if(IP2Bus_WrAck = '1')or (IP2Bus_Error = '1')then
axi_full_sm_ns <= WR_RESP_1;
else
axi_full_sm_ns <= AXI_SINGLE_WR;
end if;
rnw_cmb <= rnw_reg;
when AXI_WR => --if(IP2Bus_WrAck = '1')then
wready_cmb <= '1';--IP2Bus_WrAck;
if(last_data_cmb = '1') then
wready_cmb <= '0';
temp_i <= '1';--IP2Bus_WrAck;
rst_en <= '1';--IP2Bus_WrAck;
axi_full_sm_ns <= WR_RESP_1;
else
axi_full_sm_ns <= AXI_WR;
end if;
rnw_cmb <= rnw_reg;
-----------------------------------------------------------
when WR_RESP_1 => --if(S_AXI4_BREADY = '1') then
-- axi_full_sm_ns <= IDLE;
--else
axi_full_sm_ns <= WR_RESP_2;
-- end if;
-----------------------------------------------------------
when WR_RESP_2 => if(S_AXI4_BREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= WR_RESP_2;
end if;
-----------------------------------------------------------
when RD_LAST => if(S_AXI4_RREADY = '1') then -- and (TX_FIFO_Empty = '1') then
last_data <= not S_AXI4_RREADY;
axi_full_sm_ns <= IDLE;
else
last_data <= not S_AXI4_RREADY;
s_axi_rvalid_cmb <= not S_AXI4_RREADY;
axi_full_sm_ns <= RD_LAST;
temp_i <= '1';
end if;
-----------------------------------------------------------
when RD_RESP_2 => if(S_AXI4_RREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= RD_RESP_2;
end if;
-----------------------------------------------------------
when ERROR_RESP => if(length_cntr = "00000000") and
(S_AXI4_BREADY = '1') then
axi_full_sm_ns <= IDLE;
else
axi_full_sm_ns <= ERROR_RESP;
end if;
response <= '1';
when others => axi_full_sm_ns <= IDLE;
end case;
end process AXI_FULL_STATE_MACHINE_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
I_DECODER : entity axi_quad_spi_v3_1.qspi_address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS, -- C_S_AXI4_ADDR_WIDTH,
C_S_AXI4_MIN_SIZE => C_S_AXI_SPI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI4_ACLK,
Bus_rst => S_AXI4_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0), -- (C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI4_ARVALID,
Bus_RNW_Erly => S_AXI4_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
end architecture imp;
------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Provides a test application that simply writes to and reads from the SRAM.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library SPI_Interface;
use SPI_Interface.globals.all;
entity Main is
generic
(
-- The width of the SRAM address and data.
ram_address_width: natural := 19;
ram_data_width: natural := 8
);
port
(
-- The system clock.
sysclk: in std_logic;
-- The internal SPI interface.
f_sck: in std_logic; --
f_rs: in std_logic; -- low during transmission
f_ds: in std_logic; -- low during transmission
f_mosi: in std_logic;
f_miso: out std_logic;
-- The external SPI interface.
ext_sck: in std_logic; --
ext_rs: in std_logic; -- low during transmission
ext_ds: in std_logic; -- low during transmission
ext_mosi: in std_logic;
ext_miso: out std_logic;
-- The test LED output.
test_led: out std_logic;
-- The SRAM data and control signals.
ram_we_n: out std_logic;
ram_oe_n: out std_logic;
ram_address: out unsigned(ram_address_width-1 downto 0);
ram_data: inout std_logic_vector(ram_data_width-1 downto 0);
-- The DAC control signals.
dac_clk: out std_logic;
dac_channel_select: out std_logic;
dac_write_n: out std_logic
);
end entity;
architecture stdarch of Main is
-- Configuration constants
-----------------------------------------------------------------------------
-- SPI interface.
constant use_internal_spi: boolean := true;
constant use_external_spi: boolean := false;
constant address_width: positive := 5; -- max. 8 (for addresses 0..255)
constant number_of_data_buffers: positive := 2**address_width;
-- SRAM controller.
constant num_of_total_wait_states: natural := 9; -- 90ns @ 100MHz (min 70ns)
constant num_of_write_pulse_wait_states: natural := 6; -- 60ns @ 100MHz (min 50ns)
constant num_of_wait_states_before_write_after_read: natural := 4; -- 40ns @ 100MHz (min 30ns)
-- SPI sub-address constants
-----------------------------------------------------------------------------
constant sram_subaddr: integer := 24;
-- Signals
-----------------------------------------------------------------------------
-- Clocks
signal clk_50mhz: std_logic;
signal clk_100mhz: std_logic;
-- SPI interfaces
type spi_in_type is record
mosi: std_logic;
sclk: std_logic;
ss_address: std_logic;
ss_data: std_logic;
end record;
signal selected_spi_in, internal_spi_in, external_spi_in, inactive_spi_in: spi_in_type :=
(
-- Initialize to proper idle values.
mosi => '0',
sclk => '1',
ss_address => '1',
ss_data => '1'
);
signal miso: std_logic;
-- Memory controller
signal memory_read: std_logic;
signal memory_write: std_logic;
signal memory_ready: std_logic;
signal memory_auto_increment_address: std_logic;
signal memory_auto_increment_end_address_reached: std_logic;
signal memory_address: unsigned(ram_address_width-1 downto 0);
signal memory_data_in: std_logic_vector(ram_data_width-1 downto 0);
signal memory_data_out: std_logic_vector(ram_data_width-1 downto 0);
-- Interconnection
signal transmit_data_x: data_buffer_vector(number_of_data_buffers-1 downto 0)
:= (others => (others => '0'));
signal received_data_x: data_buffer_vector(number_of_data_buffers-1 downto 0);
signal ready_x: std_logic_vector(number_of_data_buffers-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Connections to and from internal signals.
--------------------------------------------------------------------------------
-- NOTE: Reading to and writing from an SPI address always happen together. Each time
-- the SPI master reads a value from the slave's transmit register, it also writes a value
-- to the slave's receive register of the same address, overwriting any previous value.
--
-- If the internal SPI connection is used, the microcontroller of the c'Lab FPGA board
-- acts as the SPI master. It accesses a particular SPI adress as follows:
-- 1) If one of the Param or Value screens is selected on the panel, the microcontroller
-- accesses the SPI bus periodically to read the value from and write the parameter to
-- the according SPI address.
-- 2) When processing a c't Lab protocol set command, the microcontroller writes the
-- according parameter to the SPI slave and ignores the value read from the SPI slave.
-- 3) When processing a c't Lab protocol query command, the microcontroller writes an
-- arbitrary parameter to the SPI slave and returns the value read from the SPI slave.
-- It happens to be that the parameter sent most recently to the same or any other SPI
-- address is reused as this arbitrary parameter.
--
-- If the external SPI connection is used, it's up to the external SPI master how to handle
-- values read from the SPI slave and how to generate parameters written to the SPI slave.
-- SPI receiver data (index 0 to 3 are also available via the FPGA panel).
-----------------------------------------------------------------------------
-- Combination of mode (5 bits), address (19 bits) and write data (8 bits).
-- Mode is sum of
-- automatic address increment: 0 = off, 8 = on
-- memory access: 0 = off, 1 = read, 2 = write
-- Here is 1 unused bit (data_buffer'high).
memory_auto_increment_address <= received_data_x(sram_subaddr)(data_buffer'high-1);
-- Here is 1 unused bit (data_buffer'high-2).
memory_write <= received_data_x(sram_subaddr)(data_buffer'high-3);
memory_read <= received_data_x(sram_subaddr)(data_buffer'high-4);
memory_address <= unsigned(received_data_x(sram_subaddr)(ram_address_width-1+ram_data_width downto ram_data_width));
memory_data_in <= received_data_x(sram_subaddr)(ram_data_width-1 downto 0);
-- SPI transmitter data (index 0 to 3 are also available via the FPGA panel).
-----------------------------------------------------------------------------
-- Combination of memory state (1 bit), memory auto-increment state (1 bit), '0' (1 bit),
-- partial mode loopback (2 bits), address loopback (19 bits) and read data (8 bits).
-- State is sum of
-- memory state: 0 = working, 16 = ready
-- memory auto-increment state: 0 = end address not reached, 8 = end address reached
-- mode loopback: 0 = off, 1 = reading, 2 = writing
transmit_data_x(sram_subaddr) <= memory_ready
& memory_auto_increment_end_address_reached
& '0'
& received_data_x(sram_subaddr)(data_buffer'high-3 downto ram_data_width)
& memory_data_out;
--------------------------------------------------------------------------------
-- SPI input selection logic.
--------------------------------------------------------------------------------
-- The internal SPI bus (i.e. the one connected to the microcontroller of the
-- c'Lab FPGA board).
internal_spi_in.mosi <= f_mosi;
internal_spi_in.sclk <= f_sck;
internal_spi_in.ss_address <= f_rs;
internal_spi_in.ss_data <= f_ds;
-- The external SPI bus (i.e. the one connected to the expansion ports of the
-- c'Lab FPGA board).
external_spi_in.mosi <= ext_mosi;
external_spi_in.sclk <= ext_sck;
external_spi_in.ss_address <= ext_rs;
external_spi_in.ss_data <= ext_ds;
-- Select the SPI connection to use.
-- NOTE: If one of the Param or Value screens is selected on the panel, the microcontroller
-- of the c'Lab FPGA board accesses the SPI bus periodically to read the value from and write
-- the parameter to the according SPI address (SPI reading and writing always happen together).
-- Thus, when both connections are activated, while using the *external* connection, set the
-- panel to the file selection screen to avoid this interference.
-- Also, when both connections are activated, while using the *internal* connection, ensure
-- that the selection pins of the external connection (ext_rs and ext_ds) are pulled up properly.
-- If they are e.g. connected to the SPI interface of a Raspberry Pi, ensure that the latter is
-- switched on. Don't leave the pins unconnected, pull them up instead.
selected_spi_in <=
internal_spi_in when use_internal_spi and
(internal_spi_in.ss_address = '0' or internal_spi_in.ss_data = '0') else
external_spi_in when use_external_spi and
(external_spi_in.ss_address = '0' or external_spi_in.ss_data = '0') else
inactive_spi_in;
--------------------------------------------------------------------------------
-- Component instantiation.
--------------------------------------------------------------------------------
-- The clock manager generating the clocks used throughout the system.
clock_manager: entity work.ClockManager
port map
(
clk => sysclk,
clk_50mhz => clk_50mhz,
clk_100mhz => clk_100mhz
);
-- The slave of the SPI interface.
slave: entity SPI_Interface.SPI_Slave
generic map
(
address_width => address_width,
synchronize_data_to_clk => true
)
port map
(
clk => clk_50mhz,
sclk => selected_spi_in.sclk,
ss_address => selected_spi_in.ss_address,
ss_data => selected_spi_in.ss_data,
transmit_data_x => transmit_data_x,
mosi => selected_spi_in.mosi,
miso => miso,
received_data_x => received_data_x,
ready_x => ready_x
);
-- The SRAM controller.
sram: entity work.SRAM_Controller
generic map
(
num_of_total_wait_states => num_of_total_wait_states,
num_of_write_pulse_wait_states => num_of_write_pulse_wait_states,
num_of_wait_states_before_write_after_read => num_of_wait_states_before_write_after_read,
data_width => ram_data_width,
address_width => ram_address_width
)
port map
(
clk => clk_100mhz,
read => memory_read,
write => memory_write,
ready => memory_ready,
auto_increment_address => memory_auto_increment_address,
auto_increment_end_address_reached => memory_auto_increment_end_address_reached,
address => memory_address,
data_in => memory_data_in,
data_out => memory_data_out,
ram_we_n => ram_we_n,
ram_oe_n => ram_oe_n,
ram_address => ram_address,
ram_data => ram_data
);
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
-- SPI & test LED.
f_miso <= miso when f_ds = '0' else 'Z';
ext_miso <= miso when ext_ds = '0' else 'Z';
test_led <= not memory_ready; -- LED is active low
-- Single and dual DAC.
dac_clk <= '1';
dac_channel_select <= '1';
dac_write_n <= '1';
end architecture;
|
-------------------------------------------------------------------------------
--! @file fifoRead-rtl-ea.vhd
--
--! @brief FIFO read controller
--
--! @details This is a FIFO read controller.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity fifoRead is
generic (
gAddrWidth : natural := 4
);
port (
iClk : in std_logic;
iRst : in std_logic;
iRead : in std_logic;
iWrPointer : in std_logic_vector(gAddrWidth downto 0);
oEmpty : out std_logic;
oFull : out std_logic;
oPointer : out std_logic_vector(gAddrWidth downto 0);
oAddress : out std_logic_vector(gAddrWidth-1 downto 0);
oUsedWord : out std_logic_vector(gAddrWidth-1 downto 0)
);
end fifoRead;
architecture rtl of fifoRead is
signal r_ptr_reg : std_logic_vector(gAddrWidth downto 0);
signal r_ptr_next : std_logic_vector(gAddrWidth downto 0);
signal gray1 : std_logic_vector(gAddrWidth downto 0);
signal bin : std_logic_vector(gAddrWidth downto 0);
signal bin1 : std_logic_vector(gAddrWidth downto 0);
signal raddr_all : std_logic_vector(gAddrWidth-1 downto 0);
signal raddr_msb : std_logic;
signal waddr_msb : std_logic;
signal empty_flag : std_logic;
signal full_flag : std_logic;
signal r_elements_wr : std_logic_vector(gAddrWidth downto 0);
signal r_elements_rd : std_logic_vector(gAddrWidth downto 0);
signal r_elements_diff : std_logic_vector(gAddrWidth downto 0);
signal r_elements_reg : std_logic_vector(gAddrWidth-1 downto 0);
signal r_elements_next : std_logic_vector(gAddrWidth-1 downto 0);
begin
--! Clock process for registers.
regProc : process(iRst, iClk)
begin
if iRst = cActivated then
r_ptr_reg <= (others => cInactivated);
r_elements_reg <= (others => cInactivated);
elsif rising_edge(iClk) then
r_ptr_reg <= r_ptr_next;
r_elements_reg <= r_elements_next;
end if;
end process;
-- (gAddrWidth+1)-bit Gray counter
bin <= r_ptr_reg xor (cInactivated & bin(gAddrWidth downto 1));
bin1 <= std_logic_vector(unsigned(bin) + 1);
gray1 <= bin1 xor (cInactivated & bin1(gAddrWidth downto 1));
-- update read pointer
r_ptr_next <= gray1 when iRead = cActivated and empty_flag = cInactivated else
r_ptr_reg;
-- gAddrWidth-bit Gray counter
raddr_msb <= r_ptr_reg(gAddrWidth) xor r_ptr_reg(gAddrWidth-1);
raddr_all <= raddr_msb & r_ptr_reg(gAddrWidth-2 downto 0);
waddr_msb <= iWrPointer(gAddrWidth) xor iWrPointer(gAddrWidth-1);
-- check for FIFO read empty
empty_flag <= cActivated when iWrPointer(gAddrWidth) = r_ptr_reg(gAddrWidth) and
iWrPointer(gAddrWidth-2 downto 0) = r_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- check for FIFO read full
full_flag <= cActivated when iWrPointer(gAddrWidth) /= r_ptr_reg(gAddrWidth) and
iWrPointer(gAddrWidth-2 downto 0) = r_ptr_reg(gAddrWidth-2 downto 0) and
raddr_msb = waddr_msb else
cInactivated;
-- convert gray value to bin and obtain difference
r_elements_wr <= bin;
r_elements_rd <= iWrPointer xor (cInactivated & r_elements_rd(gAddrWidth downto 1));
r_elements_diff <= std_logic_vector(unsigned(r_elements_rd) - unsigned(r_elements_wr));
r_elements_next <= r_elements_diff(r_elements_next'range);
-- output
oAddress <= raddr_all;
oPointer <= r_ptr_reg;
oUsedWord <= r_elements_reg;
oEmpty <= empty_flag;
oFull <= full_flag;
end rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:51:11 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top RAT_xlslice_0_0 -prefix
-- RAT_xlslice_0_0_ RAT_slice_1_0_0_sim_netlist.vhdl
-- Design : RAT_slice_1_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_xlslice_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_xlslice_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_xlslice_0_0 : entity is "RAT_slice_1_0_0,xlslice,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_xlslice_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_xlslice_0_0 : entity is "xlslice,Vivado 2016.4";
end RAT_xlslice_0_0;
architecture STRUCTURE of RAT_xlslice_0_0 is
signal \^din\ : STD_LOGIC_VECTOR ( 17 downto 0 );
begin
Dout(9 downto 0) <= \^din\(12 downto 3);
\^din\(12 downto 3) <= Din(12 downto 3);
end STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Oct 17 02:51:11 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top RAT_xlslice_0_0 -prefix
-- RAT_xlslice_0_0_ RAT_slice_1_0_0_sim_netlist.vhdl
-- Design : RAT_slice_1_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RAT_xlslice_0_0 is
port (
Din : in STD_LOGIC_VECTOR ( 17 downto 0 );
Dout : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of RAT_xlslice_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of RAT_xlslice_0_0 : entity is "RAT_slice_1_0_0,xlslice,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of RAT_xlslice_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of RAT_xlslice_0_0 : entity is "xlslice,Vivado 2016.4";
end RAT_xlslice_0_0;
architecture STRUCTURE of RAT_xlslice_0_0 is
signal \^din\ : STD_LOGIC_VECTOR ( 17 downto 0 );
begin
Dout(9 downto 0) <= \^din\(12 downto 3);
\^din\(12 downto 3) <= Din(12 downto 3);
end STRUCTURE;
|
-- file: input/input_parser.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Parses input signals from switches and keys and attributes the adequate
-- values to the internal signals.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.numeric_std.all ;
entity input_parser is
generic (
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
key : in std_logic_vector(3 downto 0) ;
sw : in std_logic_vector(9 downto 0) ;
clock : in std_logic ;
jump : out std_logic ;
reset : out std_logic ;
pause : out std_logic ;
gravity : out integer range 0 to V_RES - 1
) ;
end input_parser ;
architecture behavior of input_parser is
begin
-- Syncronize input with circuit clock changes to minimize hazards.
process(clock)
variable tmp_key : std_logic_vector(3 downto 0) ;
variable tmp_sw : std_logic_vector(9 downto 0) ;
begin
if rising_edge(clock) then
-- Update output.
jump <= not tmp_key(3) ;
reset <= not tmp_key(2) ;
pause <= tmp_sw(9) ;
gravity <= to_integer(signed(tmp_sw(7 downto 0))) ;
-- Update local buffer.
tmp_key := key ;
tmp_sw := sw ;
end if ;
end process ;
end behavior ;
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_constant is
end entity alt_dspbuilder_constant;
architecture rtl of alt_dspbuilder_constant is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IPv4_destination is
port( data_in : in std_logic_vector(7 downto 0);
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
destination : out std_logic_vector(31 downto 0)
);
end IPv4_destination;
architecture Behavioral of IPv4_destination is
signal address_counter : std_logic_vector(10 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
address_counter <= (others=>'0');
elsif enable = '1' then
address_counter <= address_counter+1;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
destination <= (others=>'0');
elsif address_counter = 31 then
destination(31 downto 24) <= data_in;
elsif address_counter = 32 then
destination(23 downto 16) <= data_in;
elsif address_counter = 33 then
destination(15 downto 8) <= data_in;
elsif address_counter = 34 then
destination(7 downto 0) <= data_in;
end if;
end if;
end process;
end Behavioral; |
-- real_alu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity real_alu is
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
-- OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end real_alu;
architecture Bhe of real_alu is
component simple_booth_add_ext
generic (N : integer);
port(
Clock : in std_logic;
Reset : in std_logic;
sign : in std_logic;
enable : in std_logic;
valid : out std_logic;
A : in std_logic_vector (N-1 downto 0);
B : in std_logic_vector (N-1 downto 0);
A_to_add : out std_logic_vector (2*N-1 downto 0);
B_to_add : out std_logic_vector (2*N-1 downto 0);
final_out : out std_logic_vector (2*N-1 downto 0);
sign_to_add : out std_logic;
ACC_from_add : in std_logic_vector (2*N-1 downto 0)
);
end component;
component p4add
generic (
N : integer := 32;
logN : integer := 5);
Port (
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_vector(N-1 downto 0);
Cin : in std_logic;
sign : In std_logic;
S : out std_logic_vector(N-1 downto 0);
Cout : out std_logic);
end component;
component comparator
generic (M : integer := 32);
port (
C : in std_logic; -- carry out
V : in std_logic; -- overflow
SUM : in std_logic_vector(M-1 downto 0);
sel : in std_logic_vector(2 downto 0); -- selection
sign : in std_logic; -- 0 unsigned / signed 1
S : out std_logic
);
end component;
component bhe_comparator is
generic (M : integer := 32);
port (
A : in std_logic_vector(M-1 downto 0); -- carry out
B : in std_logic_vector(M-1 downto 0);
sign : in std_logic;
sel : in std_logic_vector(2 downto 0); -- selection
S : out std_logic
);
end component;
component shifter
port(
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(4 downto 0);
LOGIC_ARITH : in std_logic; -- 1 = logic, 0 = arith
LEFT_RIGHT : in std_logic; -- 1 = left, 0 = right
OUTPUT : out std_logic_vector(31 downto 0)
);
end component;
component logic_unit
generic ( SIZE : integer := 32 );
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
IN2 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0); -- need to do only and, or and xor
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
signal sign_to_booth : std_logic;
signal enable_to_booth : std_logic;
signal valid_from_booth : std_logic;
signal A_booth_to_add : std_logic_vector(DATA_SIZE-1 downto 0);
signal B_booth_to_add : std_logic_vector(DATA_SIZE-1 downto 0);
signal sign_booth_to_add : std_logic;
signal sum_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal comp_out : std_logic;
signal shift_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal mult_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal mux_A : std_logic_vector(DATA_SIZE-1 downto 0);
signal mux_B : std_logic_vector(DATA_SIZE-1 downto 0);
signal mux_sign : std_logic;
signal carry_from_adder : std_logic;
signal overflow : std_logic;
signal sign_bit_to_comp : std_logic;
signal out_mux_sel : std_logic_vector(2 downto 0);
signal comp_sel : std_logic_vector(2 downto 0);
signal sign_to_adder : std_logic;
signal left_right : std_logic; -- 1 = logic, 0 = arith
signal logic_arith : std_logic; -- 1 = left, 0 = right
signal lu_ctrl : std_logic_vector(1 downto 0);
signal lu_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal ALU_WORD_TEST :std_logic_vector(12 downto 0);
begin
-- debug signal
ALU_WORD_TEST <= out_mux_sel&left_right&logic_arith&sign_to_adder&lu_ctrl&comp_sel&enable_to_booth&sign_to_booth;
-- signals from decode aluOP
out_mux_sel <= ALUW_i(12 downto 10);
left_right <= ALUW_i(9);
logic_arith <= ALUW_i(8);
sign_to_adder <= ALUW_i(7);
lu_ctrl <= ALUW_i(6 downto 5);
comp_sel <= ALUW_i(4 downto 2);
enable_to_booth <= ALUW_i(1);
sign_to_booth <= ALUW_i(0);
--muxes to adder
mux_A <= IN1 when enable_to_booth = '0' else
A_booth_to_add when enable_to_booth = '1' else
(others => 'X');
mux_B <= IN2 when enable_to_booth = '0' else
B_booth_to_add when enable_to_booth = '1' else
(others => 'X');
mux_sign <= sign_to_adder when enable_to_booth = '0' else
sign_booth_to_add when enable_to_booth = '1' else
'X';
--sign bit calculation
sign_bit_to_comp <= IN1(DATA_SIZE-1) xor IN2(DATA_SIZE-1);
MULT: simple_booth_add_ext
generic map ( N => DATA_SIZE/2)
port Map(
Clock => Clock,
Reset => Reset,
sign => sign_to_booth,
enable => enable_to_booth,
valid => valid_from_booth,
A => IN1(DATA_SIZE/2-1 downto 0),
B => IN2(DATA_SIZE/2-1 downto 0),
A_to_add => A_booth_to_add,
B_to_add => B_booth_to_add,
final_out => mult_out,
sign_to_add => sign_booth_to_add,
ACC_from_add => sum_out
);
ADDER: p4add
generic map (
N => DATA_SIZE,
logN => 5
)
port map (
A => mux_A,
B => mux_B,
Cin => '0',
sign => mux_sign,
S => sum_out,
Cout => carry_from_adder
);
COMP: comparator
generic map ( M => DATA_SIZE)
port map (
C => carry_from_adder,
V => overflow,
SUM => sum_out,
sel => comp_sel,
sign => sign_to_booth,
S => comp_out
);
-- NO MORE USED, IMPROVES SPEED, INCREASES AREA
-- BHE_COMP: bhe_comparator
-- generic map ( M => DATA_SIZE)
-- port map (
-- A => IN1,
-- B => IN2,
-- sel => comp_sel,
-- sign => sign_to_booth,
-- S => comp_out
-- );
SHIFT: shifter
port map(
A => IN1,
B => IN2(4 downto 0),
LOGIC_ARITH => logic_arith,
LEFT_RIGHT => left_right,
OUTPUT => shift_out
);
LU: logic_unit
generic map( SIZE => DATA_SIZE)
port map(
IN1 => IN1,
IN2 => IN2,
CTRL => lu_ctrl,
OUT1 => lu_out
);
-- overflow bit calculation
overflow <= (IN2(DATA_SIZE-1) xnor sum_out(DATA_SIZE-1)) and (IN1(DATA_SIZE-1) xor IN2(DATA_SIZE-1));
-- stalling while booth is in process
stall_o <= enable_to_booth and not(valid_from_booth);
--output mux
DOUT <= sum_out when out_mux_sel = "000" else
lu_out when out_mux_sel = "001" else
shift_out when out_mux_sel = "010" else
"000"&X"0000000"&comp_out when out_mux_sel = "011" else
IN2 when out_mux_sel = "100" else
mult_out when out_mux_sel = "101" else
(others => 'X');
end bhe;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixiii_pllpack;
package body stratixiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1600; -- max vco frequency. (in mHz)
constant MIN_VCO : integer := 300; -- min vco frequency. (in mHz)
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if ((closest_vco_step_value = 0) or (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step)))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_dffe : entity is TRUE;
end stratixiii_dffe;
-- architecture body --
architecture behave of stratixiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixiii_mux21 : entity is TRUE;
end stratixiii_mux21;
architecture AltVITAL of stratixiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_mux41 : entity is TRUE;
end stratixiii_mux41;
architecture AltVITAL of stratixiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
-- entity declaration --
entity stratixiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_and1 : entity is TRUE;
end stratixiii_and1;
-- architecture body --
architecture AltVITAL of stratixiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_jtag
--
-- Description : Stratix JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_jtag is
generic (
lpm_type : string := "stratixiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratixiii_jtag;
architecture architecture_jtag of stratixiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_crcblock
--
-- Description : Stratix CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_crcblock is
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "stratixiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end stratixiii_crcblock;
architecture architecture_crcblock of stratixiii_crcblock is
begin
crcerror <= '0';
regout <= '0';
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_lcell_comb
--
-- Description : Stratix III LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_lcell_comb : entity is TRUE;
end stratixiii_lcell_comb;
architecture vital_lcell_comb of stratixiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_routing_wire
--
-- Description : Stratix III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_routing_wire : entity is TRUE;
end stratixiii_routing_wire;
ARCHITECTURE behave of stratixiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of stratixiii_lvds_tx_reg : ENTITY is TRUE;
END stratixiii_lvds_tx_reg;
ARCHITECTURE vital_stratixiii_lvds_tx_reg of stratixiii_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_stratixiii_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiii_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the Stratix III
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
ENTITY stratixiii_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END stratixiii_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixiii_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
ENTITY stratixiii_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END stratixiii_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixiii_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_transmitter
--
-- Description : Timing simulation model for the Stratix III LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) Stratix III_lvds_tx_parallel_register and
-- 3) Stratix III_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
USE work.stratixiii_lvds_tx_parallel_register;
USE work.stratixiii_lvds_tx_out_block;
USE work.stratixiii_lvds_tx_reg;
ENTITY stratixiii_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end stratixiii_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixiii_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal dpaclkin_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT stratixiii_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT stratixiii_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: stratixiii_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: stratixiii_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: stratixiii_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
dpaclkin_ipd,
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then
dataout_tmp := dpaclkin_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (enable_dpaclk_to_lvdsout = "on") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--
--
-- STRATIXIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end stratixiii_rublock;
architecture architecture_rublock of stratixiii_rublock is
begin
end architecture_rublock;
----------------------------------------------------------------------------
-- Module Name : stratixiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixiii_ram_register;
ARCHITECTURE reg_arch OF stratixiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiii_ram_pulse_generator:ENTITY IS TRUE;
END stratixiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_ram_register;
USE work.stratixiii_ram_pulse_generator;
ENTITY stratixiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
width_eccstatus : INTEGER := 3;
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "Auto";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0');
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixiii_ram_block;
ARCHITECTURE block_arch OF stratixiii_ram_block IS
COMPONENT stratixiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : stratixiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : stratixiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
rpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
rwpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
rwpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length +
mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length +
mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length +
mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length +
mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length +
mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length +
mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length +
mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length +
mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length +
mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length +
mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length +
mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length +
mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length +
mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length +
mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
ftpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
ftpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_in(0) <= dataout_a_clr;
aclr_a_mux_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_out
);
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
-- Port B output register clear
dataout_b_clr_reg_in(0) <= dataout_b_clr;
aclr_b_mux_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_out
);
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
dataout_a;
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
dataout_b;
eccstatus <= (OTHERS => '0');
dftout <= (OTHERS => '0');
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ff
--
-- Description : Stratix III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_and1;
entity stratixiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ff : entity is TRUE;
end stratixiii_ff;
architecture vital_lcell_ff of stratixiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component stratixiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: stratixiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: stratixiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: stratixiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Stratix III CLKSELECT Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIXIII_CLKSELECT Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_clkselect is
generic (
lpm_type : STRING := "stratixiii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_clkselect : entity is TRUE;
end stratixiii_clkselect;
architecture vital_clkselect of stratixiii_clkselect is
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal clkmux_out : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable outclk_VitalGlitchData : VitalGlitchDataType;
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLOCK",
OutTemp => tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkselect;
--/////////////////////////////////////////////////////////////////////////////
--
-- stratixiii_and2 Model
-- Description : Simulation model for a simple two input AND gate.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
-- entity declaration --
entity stratixiii_and2 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_and2 : entity is TRUE;
end stratixiii_and2;
-- architecture body --
architecture AltVITAL of stratixiii_and2 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ena_reg : entity is TRUE;
end stratixiii_ena_reg;
ARCHITECTURE behave of stratixiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Stratix III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- Stratix III_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ena_reg;
use work.stratixiii_and2;
entity stratixiii_clkena is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_clkena : entity is TRUE;
end stratixiii_clkena;
architecture vital_clkena of stratixiii_clkena is
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
component stratixiii_and2
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
end component;
component stratixiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic;
signal inclk_inv : std_logic;
signal ena_ipd : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
end block;
inclk_inv <= NOT inclk_ipd;
extena_reg1 : stratixiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena_reg2 : stratixiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_and : stratixiii_and2
port map (
IN1 => inclk_ipd,
IN2 => ena_out,
Y => outclk
);
enaout_and : stratixiii_and2
port map (
IN1 => vcc,
IN2 => ena_out,
Y => enaout
);
end vital_clkena;
----------------------------------------------------------------------------
-- Module Name : stratixiii_mlab_cell_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_mlab_cell_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (1 ps,1 ps);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiii_mlab_cell_pulse_generator:ENTITY IS TRUE;
END stratixiii_mlab_cell_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiii_mlab_cell_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_mlab_cell_pulse_generator;
ENTITY stratixiii_mlab_cell IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "stratixiii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
-- --------- VITAL PARAMETERS --------
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END stratixiii_mlab_cell;
ARCHITECTURE block_arch OF stratixiii_mlab_cell IS
COMPONENT stratixiii_mlab_cell_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT port_byte_size : INTEGER := data_width / byte_enable_mask_width;
-- -------- internal signals ---------
-- Write address
SIGNAL write_address : INTEGER := 0;
SIGNAL read_address : INTEGER := 0;
-- pulses
SIGNAL write_pulse, write_cycle, write_clock : STD_LOGIC;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
TYPE mem_type IS ARRAY ((2 ** address_width) - 1 DOWNTO 0) OF mem_word_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_write IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
SIGNAL mask_vector : mask_write := (
normal => (OTHERS => '0'),
inverse => (OTHERS => 'X')
);
-- output
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_write IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_write := (normal => (OTHERS => '0'),inverse => (OTHERS => 'X'));
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END LOOP;
RETURN mask;
END get_mask;
SIGNAL clk0_ipd : STD_LOGIC;
SIGNAL ena0_ipd : STD_LOGIC;
SIGNAL portaaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portbaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portabyteenamasks_ipd : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
SIGNAL ena0_reg : STD_LOGIC := '0';
BEGIN
-- interconnect delays
WireDelay : BLOCK
BEGIN
loopbits_ad : FOR i in portaaddr'RANGE GENERATE
VitalWireDelay (portaaddr_ipd(i), portaaddr(i), tipd_portaaddr(i));
VitalWireDelay (portbaddr_ipd(i), portbaddr(i), tipd_portbaddr(i));
END GENERATE;
loopbits_be : FOR j in portabyteenamasks'RANGE GENERATE
VitalWireDelay (portabyteenamasks_ipd(j), portabyteenamasks(j), tipd_portabyteenamasks(j));
END GENERATE;
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (ena0_ipd, ena0, tipd_ena0);
END BLOCK;
-- setup/hold checks
setup_hold_checks: PROCESS (ena0_reg,portaaddr_ipd,portabyteenamasks_ipd,clk0_ipd,ena0_ipd)
VARIABLE Tviol_clk_enable : STD_ULOGIC := '0';
VARIABLE Tviol_clk_address : STD_ULOGIC := '0';
VARIABLE Tviol_clk_bemasks : STD_ULOGIC := '0';
VARIABLE TimingData_clk_enable : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_address : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_bemasks : VitalTimingDataType := VitalTimingDataInit;
BEGIN
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_enable,
TimingData => TimingData_clk_enable,
TestSignal => ena0_ipd,
TestSignalName => "ena0",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_ena0_clk0_noedge_posedge,
SetupLow => tsetup_ena0_clk0_noedge_posedge,
HoldHigh => thold_ena0_clk0_noedge_posedge,
HoldLow => thold_ena0_clk0_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_address,
TimingData => TimingData_clk_address,
TestSignal => portaaddr_ipd,
TestSignalName => "portaaddr",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portaaddr_clk0_noedge_negedge,
SetupLow => tsetup_portaaddr_clk0_noedge_negedge,
HoldHigh => thold_portaaddr_clk0_noedge_negedge,
HoldLow => thold_portaaddr_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_bemasks,
TimingData => TimingData_clk_bemasks,
TestSignal => portabyteenamasks_ipd,
TestSignalName => "portabyteenamasks",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portabyteenamasks_clk0_noedge_negedge,
SetupLow => tsetup_portabyteenamasks_clk0_noedge_negedge,
HoldHigh => thold_portabyteenamasks_clk0_noedge_negedge,
HoldLow => thold_portabyteenamasks_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
END PROCESS setup_hold_checks;
-- latch CE signal
PROCESS (clk0_ipd)
BEGIN
IF (clk0_ipd'EVENT AND clk0_ipd = '1') THEN
ena0_reg <= ena0_ipd;
END IF;
END PROCESS;
-- output path delay
PROCESS (portbaddr_ipd)
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
CQDelay := SelectDelay(
( 1 => ( portbaddr_ipd'LAST_EVENT, tpd_portbaddr_portbdataout, TRUE ) )
);
read_address <= TRANSPORT alt_conv_integer(portbaddr_ipd) AFTER CQDelay;
END PROCESS;
-- memory initialization
init_mem <= TRUE;
write_clock <= NOT clk0_ipd;
write_address <= alt_conv_integer(portaaddr_ipd);
-- Write pulse generation (neg edge)
wpgen_a : stratixiii_mlab_cell_pulse_generator
PORT MAP (
clk => write_clock,
ena => ena0_reg,
pulse => write_pulse,
cycle => write_cycle
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (portabyteenamasks_ipd)
VARIABLE mask : mask_write;
BEGIN
IF (portabyteenamasks_ipd'EVENT) THEN
mask := get_mask(portabyteenamasks_ipd,byte_enable_mask_width,port_byte_size);
mask_vector <= mask;
END IF;
END PROCESS mask_create;
mem_rw : PROCESS (init_mem, write_pulse)
-- mem init
VARIABLE addr_range_init,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_word_type;
BEGIN
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output to 0
mem_val := (OTHERS => (OTHERS => '0'));
IF (init_file /= "UNUSED" AND init_file /= "unused") THEN
addr_range_init := last_address - first_address + 1;
mem_init := mem_init0;
mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
index := row * data_width;
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
END LOOP;
END IF;
mem <= mem_val;
END IF;
-- Write stage 1 : X to memory
-- Write stage 2 : actual data to memory
IF (write_pulse'EVENT) THEN
IF (write_pulse = '1') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR mask_vector(inverse)(i);
END LOOP;
mem(write_address) <= mem_data_p;
ELSIF (write_pulse = '0') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector(normal)(i) = '0') THEN
mem(write_address)(i) <= portadatain(i);
mem_data_p(i) := portadatain(i);
ELSIF (mask_vector(inverse)(i) = 'X') THEN
mem(write_address)(i) <= 'X';
mem_data_p(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END PROCESS mem_rw;
-- Continuous read
portbdataout <= mem(read_address);
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_ibuf
--
-- Description : Stratix III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END stratixiii_io_ibuf;
ARCHITECTURE arch OF stratixiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_obuf
--
-- Description : Stratix III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01);
tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 );
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiii_io_obuf;
ARCHITECTURE arch OF stratixiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL dynamicterminationcontrol_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
SIGNAL seriesterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
SIGNAL parallelterminationcontrol_ipd : std_logic_vector(13 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol);
g1 :for i in seriesterminationcontrol'range generate
VitalWireDelay (seriesterminationcontrol_ipd(i), seriesterminationcontrol(i), tipd_seriesterminationcontrol(i));
end generate;
g2 :for i in parallelterminationcontrol'range generate
VitalWireDelay (parallelterminationcontrol_ipd(i), parallelterminationcontrol(i), tipd_parallelterminationcontrol(i));
end generate;
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_in
--
-- Description : Stratix III DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixiii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_in;
ARCHITECTURE arch OF stratixiii_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_oe
--
-- Description : Stratix III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_oe;
ARCHITECTURE arch OF stratixiii_ddio_oe IS
component stratixiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : stratixiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_out
--
-- Description : Stratix III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_out;
ARCHITECTURE arch OF stratixiii_ddio_out IS
component stratixiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
sel_mux : stratixiii_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
-- --------------------------------------------------------------------
-- Module Name: stratixiii_rt_sm
-- Description: Parallel Termination State Machine
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY stratixiii_rt_sm IS
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0));
END stratixiii_rt_sm;
ARCHITECTURE stratixiii_rt_sm_rtl OF stratixiii_rt_sm IS
CONSTANT STRATIXIII_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000";
CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001";
CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010";
CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011";
CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100";
CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101";
CONSTANT STRATIXIII_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000";
CONSTANT STRATIXIII_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001";
CONSTANT STRATIXIII_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010";
CONSTANT STRATIXIII_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011";
CONSTANT STRATIXIII_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100";
CONSTANT STRATIXIII_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101";
CONSTANT STRATIXIII_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001";
CONSTANT STRATIXIII_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111";
-- interface
SIGNAL nclr : std_logic := '1'; -- for synthesis
SIGNAL rtcalclk : std_logic;
SIGNAL caldone_sig : std_logic := '0';
-- sm
SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL sel_rup_vref_h_d : std_logic := '0';
SIGNAL sel_rup_vref_h : std_logic := '0';
SIGNAL sel_rup_vref_m_d : std_logic := '1';
SIGNAL sel_rup_vref_m : std_logic := '1';
SIGNAL sel_rup_vref_l_d : std_logic := '0';
SIGNAL sel_rup_vref_l : std_logic := '0';
SIGNAL sel_rdn_vref_h_d : std_logic := '0';
SIGNAL sel_rdn_vref_h : std_logic := '0';
SIGNAL sel_rdn_vref_m_d : std_logic := '1';
SIGNAL sel_rdn_vref_m : std_logic := '1';
SIGNAL sel_rdn_vref_l_d : std_logic := '0';
SIGNAL sel_rdn_vref_l : std_logic := '0';
SIGNAL switch_region_d : std_logic := '0';
SIGNAL switch_region : std_logic := '0';
SIGNAL cmpup : std_logic := '0';
SIGNAL cmpdn : std_logic := '0';
SIGNAL rt_sm_done_d : std_logic := '0';
SIGNAL rt_sm_done : std_logic := '0';
-- cnt
SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt_sub_d : std_logic := '0';
SIGNAL p_cnt_sub : std_logic := '0';
SIGNAL n_cnt_sub_d : std_logic := '0';
SIGNAL n_cnt_sub : std_logic := '0';
BEGIN
-- primary output - MSB is sign bit
rtoffsetp <= p_cnt_sub & p_cnt ;
rtoffsetn <= n_cnt_sub & n_cnt ;
caldone <= caldone_sig;
caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1';
sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ;
sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ;
-- input interface
nclr <= NOT clr ;
rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ;
-- latch registers - rising on everything except cmpup and cmpdn
-- cmpup/dn
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0');
IF (nclr = '0') THEN
cmpup <= '0';
cmpdn <= '0';
ELSE
cmpup <= rup;
cmpdn <= rdn;
END IF;
END PROCESS;
-- other regisers
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1');
IF (clr = '1') THEN
current_state <= STRATIXIII_RTOCT_WAIT;
switch_region <= '0';
rt_sm_done <= '0';
p_cnt <= "000";
p_cnt_sub <= '0';
n_cnt <= "000";
n_cnt_sub <= '0';
sel_rup_vref_h <= '0';
sel_rup_vref_m <= '1';
sel_rup_vref_l <= '0';
sel_rdn_vref_h <= '0';
sel_rdn_vref_m <= '1';
sel_rdn_vref_l <= '0';
ELSE
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
END IF;
END PROCESS;
-- state machine
PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region)
variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0);
variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic;
BEGIN
p_cnt_d_var := p_cnt;
n_cnt_d_var := n_cnt;
p_cnt_sub_d_var := '0';
n_cnt_sub_d_var := '0';
CASE current_state IS
WHEN STRATIXIII_RTOCT_WAIT =>
IF (rtena = '0') THEN
next_state <= STRATIXIII_RTOCT_WAIT;
ELSE
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
WHEN RUP_VREF_M_RDN_VER_M =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_L =>
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '0') THEN
next_state <= STRATIXIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_H =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_H =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_L =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
ELSE
IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIII_RTOCT_INC_PN =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_PN =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
END IF;
END IF;
END IF;
END IF;
----------------- same action begin
WHEN STRATIXIII_RTOCT_INC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_INC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
----------------- same action end
WHEN STRATIXIII_RTOCT_SWITCH_REG =>
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
WHEN STRATIXIII_RTOCT_DONE =>
next_state <= STRATIXIII_RTOCT_DONE;
rt_sm_done_d <= '1';
WHEN OTHERS =>
next_state <= STRATIXIII_RTOCT_WAIT;
END CASE;
-- case(current_state)
-- schedule the outputs
p_cnt_d <= p_cnt_d_var;
n_cnt_d <= n_cnt_d_var;
p_cnt_sub_d <= p_cnt_sub_d_var;
n_cnt_sub_d <= n_cnt_sub_d_var;
END PROCESS;
END stratixiii_rt_sm_rtl;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_termination_aux_clock_div
-- Description: auxilary clock divider module
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY stratixiii_termination_aux_clock_div IS
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END stratixiii_termination_aux_clock_div;
ARCHITECTURE oct_clock_div_arch OF stratixiii_termination_aux_clock_div IS
SIGNAL clk_edges : INTEGER := -1;
SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0)
:= (OTHERS => '0');
BEGIN
PROCESS(clk,reset)
VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0');
VARIABLE m : INTEGER := 0;
VARIABLE running_clk_edge : INTEGER := -1;
BEGIN
running_clk_edge := clk_edges;
IF (reset = '1') THEN
clk_edges <= -1;
m := 0;
div_n := (OTHERS => '0');
ELSE
IF (clk'EVENT) THEN
IF (running_clk_edge = -1) THEN
m := 0;
div_n(0) := clk;
IF (clk = '1') THEN running_clk_edge := 0; END IF;
ELSIF (running_clk_edge mod clk_divide_by = 0) THEN
div_n(0) := NOT div_n(0);
END IF;
IF (running_clk_edge >= 0 OR clk = '1') THEN
clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by);
END IF;
END IF;
END IF;
m := 0;
div_n_register(m) <= div_n(m);
WHILE (m < 2 * extra_latency) LOOP
div_n_register(m+1) <= div_n_register(m);
m := m + 1;
END LOOP;
END PROCESS;
clkout <= div_n_register(2 * extra_latency);
END oct_clock_div_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_termination
--
-- Description : Stratix III Termination Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiii_atom_pack.all;
USE WORK.stratixiii_termination_aux_clock_div;
USE WORK.stratixiii_rt_sm;
ENTITY stratixiii_termination IS
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END stratixiii_termination;
ARCHITECTURE stratixiii_oct_arch OF stratixiii_termination IS
COMPONENT stratixiii_termination_aux_clock_div
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_rt_sm
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)
);
END COMPONENT;
-- HW outputs
SIGNAL compout_rup_core : std_logic;
SIGNAL compout_rdn_core : std_logic;
SIGNAL ser_data_io : std_logic;
SIGNAL ser_data_core : std_logic;
-- HW inputs
SIGNAL usr_clk : std_logic;
SIGNAL cal_clk : std_logic;
SIGNAL rscal_clk : std_logic;
SIGNAL cal_clken : std_logic;
SIGNAL cal_nclr : std_logic;
-- legality check on enser
SIGNAL enser_checked : std_logic := '0';
-- Shift Register
SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL sreg_bit_out_tmp0 : std_logic := '0';
SIGNAL sreg_vshift_bit_tmp : std_logic := '0';
SIGNAL sreg_vshift_bit_out : std_logic := '0';
SIGNAL sreg_rscaldone_prev : std_logic := '0';
SIGNAL sreg_rscaldone_prev1 : std_logic := '0';
SIGNAL sregn_rscaldone_out : std_logic := '0';
SIGNAL sreg_bit6_prev : std_logic := '1';
-- nreg before SA-ADC
SIGNAL regn_rup_in : std_logic;
SIGNAL regn_rdn_in : std_logic;
SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- SA-ADC
SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS
SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS
SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0);
SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0);
-- ENSER
SIGNAL enser_out : std_logic;
SIGNAL enser_gen_out : std_logic;
SIGNAL enser_cnt : INTEGER := 0;
-- RT State Machine
SIGNAL rtsm_rup_in : std_logic;
SIGNAL rtsm_rdn_in : std_logic;
SIGNAL rtsm_rtena_in : std_logic;
SIGNAL rtsm_rscaldone_in : std_logic;
SIGNAL rtsm_caldone_out : std_logic;
SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
-- RT Adder/Sub
SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- P2S
SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_enser_in : std_logic;
SIGNAL p2s_clk_in : std_logic;
SIGNAL p2s_ser_data_out : std_logic;
SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL p2s_serial_reg : std_logic := '0';
SIGNAL p2s_index : integer := 27;
-- used to set SA outputs
SIGNAL temp_xhdl10 : std_logic;
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl14 : std_logic;
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl18 : std_logic;
SIGNAL temp_xhdl20 : std_logic;
SIGNAL temp_xhdl22 : std_logic;
SIGNAL temp_xhdl24 : std_logic;
SIGNAL temp_xhdl26 : std_logic;
SIGNAL temp_xhdl28 : std_logic;
SIGNAL temp_xhdl30 : std_logic;
SIGNAL temp_xhdl32 : std_logic;
SIGNAL temp_xhdl34 : std_logic;
SIGNAL temp_xhdl36 : std_logic;
SIGNAL MY_GND : std_logic := '0';
-- timing
SIGNAL rup_ipd : std_logic;
SIGNAL rdn_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL terminationclear_ipd : std_logic;
SIGNAL terminationenable_ipd : std_logic;
SIGNAL serializerenable_ipd : std_logic;
SIGNAL terminationcontrolin_ipd : std_logic;
SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0);
BEGIN
-- primary outputs
incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core;
incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core;
terminationcontrol <= ser_data_io;
terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core;
shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out;
serializerenableout <= serializerenable;
compout_rup_core <= rup ;
compout_rdn_core <= rdn ;
ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out;
ser_data_core <= p2s_ser_data_out ;
-- primary inputs
usr_clk <= terminationclock ;
cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0';
cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0';
-- divide by 100 clock
m_gen_calclk : stratixiii_termination_aux_clock_div
GENERIC MAP (
clk_divide_by => 100,
extra_latency => 0)
PORT MAP (
clk => usr_clk,
reset => MY_GND,
clkout => cal_clk);
rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ;
-- legality check on enser
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serializerenable = '1' AND cal_clken = '0') THEN
IF (otherserializerenable(0) = '1' OR
otherserializerenable(1) = '1' OR
otherserializerenable(2) = '1' OR
otherserializerenable(3) = '1' OR
otherserializerenable(4) = '1' OR
otherserializerenable(5) = '1' OR
otherserializerenable(6) = '1' OR
otherserializerenable(7) = '1' OR
otherserializerenable(8) = '1') THEN
IF (enser_checked = '0') THEN
assert false
report "serializizerable and some bits of otherserializerenable are asserted at data transfer time"
severity warning;
enser_checked <= '1';
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
END PROCESS;
-- SHIFT regiter
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sreg_bit6_prev <= '1';
sreg_bit_out <= "0000000";
sreg_vshift_bit_out <= '0';
sreg_vshift_bit_tmp <= '0';
sreg_bit_out_tmp0 <= '0';
sreg_rscaldone_prev <= '0';
sreg_rscaldone_prev1 <= '0';
ELSE
IF (cal_clken = '1') THEN
sreg_bit_out(6) <= sreg_bit6_prev;
sreg_bit_out(5) <= sreg_bit_out(6);
sreg_bit_out(4) <= sreg_bit_out(5);
sreg_bit_out(3) <= sreg_bit_out(4);
sreg_bit_out(2) <= sreg_bit_out(3);
sreg_bit_out(1) <= sreg_bit_out(2);
sreg_bit_out_tmp0 <= sreg_bit_out(1);
sreg_vshift_bit_tmp <= sreg_bit_out_tmp0;
sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp;
sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp;
sreg_bit6_prev <= '0';
END IF;
END IF;
-- might falling outside of 10 cycles
IF (sreg_vshift_bit_tmp = '1') THEN
sreg_rscaldone_prev <= '1';
END IF;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sregn_rscaldone_out <= '0';
ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles
IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN
sregn_rscaldone_out <= '1';
END IF;
END IF;
END PROCESS;
-- nreg and SA-ADC:
--
-- RDN_vol < ref_voltage < RUP_voltage
-- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
-- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
-- RDN=GND so voltage compare out for RDN = 0
regn_rup_in <= rup ;
regn_rdn_in <= rdn ;
PROCESS
BEGIN
WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0');
IF (cal_nclr = '1') THEN
regn_compout_rup <= "0000000";
regn_compout_rdn <= "0000000";
ELSE
-- rup
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rup(0) <= regn_rup_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rup(1) <= regn_rup_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rup(2) <= regn_rup_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rup(3) <= regn_rup_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rup(4) <= regn_rup_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rup(5) <= regn_rup_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rup(6) <= regn_rup_in;
END IF;
-- rdn
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rdn(0) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rdn(1) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rdn(2) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rdn(3) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rdn(4) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rdn(5) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rdn(6) <= regn_rdn_in;
END IF;
END IF;
END PROCESS;
sa_octcaln_in <= sreg_bit_out ;
sa_octcalp_in <= sreg_bit_out ;
-- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0);
sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10;
temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1);
sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12;
temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2);
sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14;
temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3);
sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16;
temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4);
sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18;
temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5);
sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20;
temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6);
sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22;
temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0);
sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24;
temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1);
sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26;
temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2);
sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28;
temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3);
sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30;
temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4);
sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32;
temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5);
sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34;
temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6);
sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36;
-- ENSER
enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out;
enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0';
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1');
IF (sregn_rscaldone_out = '0') THEN
enser_cnt <= 0;
ELSE
IF (enser_cnt < 63) THEN
enser_cnt <= enser_cnt + 1;
END IF;
END IF;
END PROCESS;
-- RT SM
rtsm_rup_in <= rup ;
rtsm_rdn_in <= rdn ;
rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0';
rtsm_rscaldone_in <= sregn_rscaldone_out ;
m_rt_sm : stratixiii_rt_sm
PORT MAP (
rup => rtsm_rup_in,
rdn => rtsm_rdn_in,
clk => cal_clk,
clken => cal_clken,
clr => cal_nclr,
rtena => rtsm_rtena_in,
rscaldone => rtsm_rscaldone_in,
rtoffsetp => rtsm_rtoffsetp_out,
rtoffsetn => rtsm_rtoffsetn_out,
caldone => rtsm_caldone_out,
sel_rup_vref => rtsm_sel_rup_vref_out,
sel_rdn_vref => rtsm_sel_rdn_vref_out
);
-- RT Adder/Sub
rtas_rs_rpcdp_in <= sa_octcalp_out ;
rtas_rs_rpcdn_in <= sa_octcaln_out ;
rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0);
rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0);
rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ;
rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ;
rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
-- P2S
p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ;
p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ;
p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out;
p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out;
p2s_enser_in <= enser_out ;
p2s_clk_in <= usr_clk ;
p2s_ser_data_out <= p2s_serial_reg ;
-- load - clken
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_parallel_reg <= "0000000000000000000000000000";
ELSE
IF (cal_clken = '1') THEN
p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in;
END IF;
END IF;
END PROCESS;
-- shift - enser
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_serial_reg <= '0';
p2s_index <= 27;
ELSE
IF (p2s_enser_in = '1' AND cal_clken = '0') THEN
p2s_serial_reg <= p2s_parallel_reg(p2s_index);
IF (p2s_index > 0) THEN
p2s_index <= p2s_index - 1;
END IF;
END IF;
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (rup_ipd, rup, tipd_rup);
VitalWireDelay (rdn_ipd, rdn, tipd_rdn);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear);
VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable);
VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable);
VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin);
VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0));
VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1));
VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2));
VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3));
VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4));
VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5));
VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6));
VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7));
VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8));
end block;
END stratixiii_oct_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_termination_logic
--
-- Description : Stratix III Termination Logic Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_termination_logic IS
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "stratixiii_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END stratixiii_termination_logic;
ARCHITECTURE stratixiii_oct_logic_arch OF stratixiii_termination_logic IS
CONSTANT xhdl_timescale : time := 1 ps;
SIGNAL usr_clk : std_logic;
SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL shift_index : integer := 27;
-- timing
SIGNAL serialloadenable_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL parallelloadenable_ipd : std_logic;
SIGNAL terminationdata_ipd : std_logic;
BEGIN
seriesterminationcontrol <= rs_reg;
parallelterminationcontrol <= rt_reg;
usr_clk <= terminationclock AFTER 11 * xhdl_timescale;
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serialloadenable = '0') THEN
shift_index <= 27;
ELSE
hold_reg(shift_index) <= terminationdata;
IF (shift_index > 0) THEN
shift_index <= shift_index - 1;
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1');
IF (parallelloadenable = '1') THEN
rs_reg <= hold_reg(27 DOWNTO 14);
rt_reg <= hold_reg(13 DOWNTO 0);
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable);
VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata);
end block;
END stratixiii_oct_logic_arch;
-------------------------------------------------------------------------------
-- utilities common for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package stratixiii_atom_ddr_pack is
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
end stratixiii_atom_ddr_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiii_atom_ddr_pack is
-- truncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
end stratixiii_atom_ddr_pack;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiii_dll_gray_encoder IS
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiii_dll_gray_encoder;
ARCHITECTURE stratixiii_dll_gray_encoder_arch OF stratixiii_dll_gray_encoder IS
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
gout <= greg;
PROCESS(mbin)
VARIABLE i : INTEGER := 0;
BEGIN
greg(width-1) <= mbin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
greg(i) <= mbin(i+1) XOR mbin(i);
i := i - 1;
END LOOP;
END IF;
END PROCESS;
END stratixiii_dll_gray_encoder_arch;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiii_dll_gray_decoder IS
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiii_dll_gray_decoder;
ARCHITECTURE stratixiii_dll_gray_decoder_arch OF stratixiii_dll_gray_decoder IS
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bout <= breg;
PROCESS(gin)
VARIABLE i : INTEGER := 0;
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bvar(width-1) := gin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
bvar(i) := bvar(i+1) XOR gin(i);
i := i - 1;
END LOOP;
END IF;
breg <= bvar;
END PROCESS;
END stratixiii_dll_gray_decoder_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_ddr_delay_chain_s
-- Description: auxilary module - delay chain-setting
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_ddr_delay_chain_s IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END stratixiii_ddr_delay_chain_s;
ARCHITECTURE stratixiii_ddr_delay_chain_s_arch OF stratixiii_ddr_delay_chain_s IS
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_delay : INTEGER := 0;
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
-- decoder
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
PROCESS(delayctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in);
END IF;
-- total delay - added extra 1 ps for resolving racing
clk_delay <= delay_chain_len * acell_delay + 1;
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
END IF;
END PROCESS; -- generating delays
delayed_clk <= transport clk after (clk_delay * 1 ps);
delayed_clkout <= delayed_clk;
END stratixiii_ddr_delay_chain_s_arch;
-------------------------------------------------------------------------------
-- based on dffeas
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_ddr_io_reg is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ddr_io_reg : entity is TRUE;
end stratixiii_ddr_io_reg;
architecture vital_stratixiii_ddr_io_reg of stratixiii_ddr_io_reg is
attribute VITAL_LEVEL0 of vital_stratixiii_ddr_io_reg : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiii_ddr_io_reg;
-------------------------------------------------------------------------------
--
-- Entity Name : Stratix III_dll
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_pllpack.all;
use work.stratixiii_atom_ddr_pack.all;
use work.stratixiii_dll_gray_encoder;
ENTITY stratixiii_dll is
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixiii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END stratixiii_dll;
ARCHITECTURE vital_titandll of stratixiii_dll is
COMPONENT stratixiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in_buf : std_logic := '0';
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_out : std_logic := '0';
signal dqsupdate_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
signal sim_buffer_intrinsic_delay : INTEGER := 0;
-- two reg on the de-assertion of dll
SIGNAL aload_in : std_logic := '0';
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
-- delay chain setting counter
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_clkena_in : std_logic := '1'; -- new in stratixiii
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_lock : std_logic := '0'; -- new in stratixiii
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
signal pc_lock_reg : std_logic := '0'; -- new in stratixiii
signal pc_comp_range : integer := 0; -- new in stratixiii
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
sim_high_buffer_intrinsic_delay;
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetdelayctrl_out <= dr_offsetctrl_out;
offsetdelayctrlclkout <= dr_clk8_in;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- two registers on aload path --------------------------------------------
aload_in <= (aload_in_buf OR aload_reg2);
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in_buf;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_dllcount_in <= dc_dllcount_out_gray;
dr_aload_in <= aload_in;
mdll_count_enc : stratixiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
-- outputs
dr_delayctrl_out <= dr_reg_dllcount;
dr_offsetctrl_out <= dr_delayctrl_int;
-- assumed para_static_delay_ctrl is gray-coded
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= "000000";
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- new in stratixiii
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_clkena_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
else -- not clkena
jc_reg_upndnclkena <= '0';
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
pc_lock <= pc_lock_reg;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
pc_delay <= pc_var_delay;
if (dual_phase_comparators = "false") then
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
else -- use dual phase
if (pc_var_delay < (input_period - pc_comp_range/2)) then
pc_reg_upndn <= '1';
pc_lock_reg <= '0';
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
pc_reg_upndn <= '0';
pc_lock_reg <= '1';
else
pc_reg_upndn <= '0';
pc_lock_reg <= '0';
end if;
end if;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in_buf, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetdelayctrlout <= offsetdelayctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_titandll;
-------------------------------------------------------------------------------
--
-- Entity Name : Stratix III_dll_offset_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
USE work.stratixiii_pllpack.all;
use work.stratixiii_atom_ddr_pack.all;
use work.stratixiii_dll_gray_encoder;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_dll_offset_ctrl is
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "stratixiii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END stratixiii_dll_offset_ctrl;
ARCHITECTURE vital_titanoffset of stratixiii_dll_offset_ctrl is
COMPONENT stratixiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal addnsub_in : std_logic := '0';
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_use_offset : std_logic := '0';
signal para_static_offset : integer := 0;
signal para_static_offset_pos : integer := 0;
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- two reg on the de-assertion of aload
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
-- docoder
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
begin
-- paramters
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
para_static_offset <= dqs_str2int(static_offset); -- signed int
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
-- outputs
offsetctrl_out <= dr_offsetctrl_out_gray;
offsettestout <= dr_offsettest_out;
-- two registers on aload path --------------------------------------------
-- it should be user clock to DLL, not the /8 clock of offsetctrl
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-- inputs
dr_clk8_in <= clk_in;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
dr_offset_in_gray <= offset_in;
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
-- outputs
dr_offsetctrl_out <= dr_reg_offset;
moffsetctrl_out_enc : stratixiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
-- model
-- decoders
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
mdr_offset_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
mpara_static_offset_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
-- get postive value of decoded offset for over/underflow check
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= "000000";
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (use_offset = "true") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= "111111";
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
else
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= "111111";
end if;
else
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
end if;
end if; -- rising clock
end process ; -- generating dr_reg_offset
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, addnsub_in,
offsetctrl_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => offsetctrlout(0),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(1),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(2),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(3),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(4),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(5),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_titanoffset;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_dqs_delay_chain IS
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
-- DFT added in WYS 1.33
test_enable : string := "false";
test_select : integer := 0;
-- SIM only
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_delay_chain_arch OF stratixiii_dqs_delay_chain IS
-- component section
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
-- signal section
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- offsetctrl after "dqs_offsetctrl_enable" mux
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- reged outputs of delay count
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
-- delay count after latch enable mux
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
SIGNAL dqs_delay : INTEGER := 0;
-- timing inputs
SIGNAL dqsin_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL dqsupdateen_in : std_logic := '1';
SIGNAL phasectrlin_in : std_logic_vector(2 downto 0) := (OTHERS => '0');
SIGNAL test_bus : std_logic_vector(12 downto 0);
SIGNAL test_lpbk : std_logic;
SIGNAL tmp_dqsin : std_logic;
BEGIN
PROCESS(dqsupdateen_in)
BEGIN
IF (dqsupdateen_in = '1') THEN
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
END IF;
END PROCESS;
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
-- mux after reg
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
mdelayctrlin_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin);
moffsetctrlin_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin);
PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable tmp_delayctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable tmp_offsetctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable acell_delay : INTEGER := 0;
variable aoffsetcell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
tmp_delayctrl := "011111";
ELSE
tmp_delayctrl := delayctrl_bin;
END IF;
IF (delay_buffer_mode = "high" AND offsetctrl_bin(5) = '1') THEN
tmp_offsetctrl := "011111";
ELSE
tmp_offsetctrl := offsetctrl_bin;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_delayctrl) * sim_buffer_delay_increment;
IF (dqs_offsetctrl_enable = "true") THEN
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_offsetctrl)*sim_buffer_delay_increment;
ELSE
aoffsetcell_delay := acell_delay;
END IF;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (phasectrlin_in(2) = '1') THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in) + 1;
END IF;
-- total delay
IF (delay_chain_len = 0) THEN
dqs_delay <= 0;
ELSE
dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
END IF;
END PROCESS; -- generating delays
-- test bus loopback
test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux;
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z';
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in;
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
END GENERATE;
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_offsetctrlin,
TimingData => TimingData_dqsupdateen_offsetctrlin,
TestSignal => offsetctrlin_in,
TestSignalName => "offsetctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_delayctrlin,
TimingData => TimingData_dqsupdateen_delayctrlin,
TestSignal => delayctrlin_in,
TestSignalName => "delayctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_enable
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_dqs_enable IS
GENERIC (
lpm_type : string := "stratixiii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_enable_arch OF stratixiii_dqs_enable IS
-- component section
-- signal section
SIGNAL ena_reg : STD_LOGIC := '1';
-- timing output
SIGNAL tmp_dqsbusout : std_logic := '0';
-- timing input
SIGNAL dqsin_in : std_logic := '0';
SIGNAL dqsenable_in : std_logic := '1';
BEGIN
tmp_dqsbusout <= ena_reg AND dqsin_in;
PROCESS(tmp_dqsbusout, dqsenable_in)
BEGIN
IF (dqsenable_in = '1') THEN
ena_reg <= '1';
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
ena_reg <= '0';
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
end block;
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_enable_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_enable_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_dqs_enable_ctrl IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_enable_ctrl_arch OF stratixiii_dqs_enable_ctrl IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : std_logic := '0';
SIGNAL delayed_clk : std_logic := '0';
SIGNAL dqsenablein_reg_q : std_logic := '0';
SIGNAL dqsenablein_level_ena : std_logic := '0';
-- transfer delay
SIGNAL dqsenablein_reg_dly : std_logic := '0';
SIGNAL phasetransferdelay_mux_out : std_logic := '0';
SIGNAL dqsenable_delayed_regp : std_logic := '0';
SIGNAL dqsenable_delayed_regn : std_logic := '0';
SIGNAL m_vcc : std_logic := '1';
SIGNAL m_gnd : std_logic := '0';
SIGNAL not_clk_in : std_logic := '1';
SIGNAL not_delayed_clk : std_logic := '1';
-- timing output
SIGNAL tmp_dqsenableout : std_logic := '1';
-- timing input
SIGNAL dqsenablein_in : std_logic := '1';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
not_clk_in <= not clk_in;
not_delayed_clk <= not delayed_clk;
dqsenablein_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenablein_in,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_q
);
dqsenable_transfer_reg : stratixiii_ddr_io_reg
PORT MAP (
d => dqsenablein_reg_q,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_dly
);
-- add phase transfer mux
phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE
dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE
dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE
dqsenablein_reg_q;
dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in;
dqsenableout_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenablein_level_ena,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regp
);
dqsenableout_extend_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenable_delayed_regp,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regn
);
tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE
(dqsenable_delayed_regp AND dqsenable_delayed_regn);
dqsenableout <= tmp_dqsenableout;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_dqs_enable_ctrl_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_delay_chain IS
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
-- new in STRATIXIV ww30.2008
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "stratixiii_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_delay_chain_arch OF stratixiii_delay_chain IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
-- signal section
SIGNAL rising_dly : INTEGER := 0;
SIGNAL falling_dly : INTEGER := 0;
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL finedelayctrlin_in : STD_LOGIC := '0';
-- timing inputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
BEGIN
-- filtering X/U etc.
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
finedelayctrlin_in <= '1' WHEN (finedelayctrlin = '1') ELSE '0';
-- generate dynamic delay table and dynamic delay
process(delayctrlin_in, finedelayctrlin_in)
variable init : boolean := true;
variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable finedly_table_rising : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable finedly_table_falling : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable dly_setting : integer := 0;
variable finedly_setting : integer := 0;
begin
if (init) then
dly_table_rising(0) := sim_delayctrlin_rising_delay_0;
dly_table_rising(1) := sim_delayctrlin_rising_delay_1;
dly_table_rising(2) := sim_delayctrlin_rising_delay_2;
dly_table_rising(3) := sim_delayctrlin_rising_delay_3;
dly_table_rising(4) := sim_delayctrlin_rising_delay_4;
dly_table_rising(5) := sim_delayctrlin_rising_delay_5;
dly_table_rising(6) := sim_delayctrlin_rising_delay_6;
dly_table_rising(7) := sim_delayctrlin_rising_delay_7;
dly_table_rising(8) := sim_delayctrlin_rising_delay_8;
dly_table_rising(9) := sim_delayctrlin_rising_delay_9;
dly_table_rising(10) := sim_delayctrlin_rising_delay_10;
dly_table_rising(11) := sim_delayctrlin_rising_delay_11;
dly_table_rising(12) := sim_delayctrlin_rising_delay_12;
dly_table_rising(13) := sim_delayctrlin_rising_delay_13;
dly_table_rising(14) := sim_delayctrlin_rising_delay_14;
dly_table_rising(15) := sim_delayctrlin_rising_delay_15;
dly_table_falling(0) := sim_delayctrlin_falling_delay_0;
dly_table_falling(1) := sim_delayctrlin_falling_delay_1;
dly_table_falling(2) := sim_delayctrlin_falling_delay_2;
dly_table_falling(3) := sim_delayctrlin_falling_delay_3;
dly_table_falling(4) := sim_delayctrlin_falling_delay_4;
dly_table_falling(5) := sim_delayctrlin_falling_delay_5;
dly_table_falling(6) := sim_delayctrlin_falling_delay_6;
dly_table_falling(7) := sim_delayctrlin_falling_delay_7;
dly_table_falling(8) := sim_delayctrlin_falling_delay_8;
dly_table_falling(9) := sim_delayctrlin_falling_delay_9;
dly_table_falling(10) := sim_delayctrlin_falling_delay_10;
dly_table_falling(11) := sim_delayctrlin_falling_delay_11;
dly_table_falling(12) := sim_delayctrlin_falling_delay_12;
dly_table_falling(13) := sim_delayctrlin_falling_delay_13;
dly_table_falling(14) := sim_delayctrlin_falling_delay_14;
dly_table_falling(15) := sim_delayctrlin_falling_delay_15;
finedly_table_rising(0) := sim_finedelayctrlin_rising_delay_0;
finedly_table_rising(1) := sim_finedelayctrlin_rising_delay_1;
finedly_table_falling(0) := sim_finedelayctrlin_falling_delay_0;
finedly_table_falling(1) := sim_finedelayctrlin_falling_delay_1;
init := false;
end if;
IF (use_delayctrlin = "false") THEN
dly_setting := delay_setting;
ELSE
dly_setting := alt_conv_integer(delayctrlin_in);
END IF;
IF (finedelayctrlin_in = '1') THEN
finedly_setting := 1;
ELSE
finedly_setting := 0;
END IF;
IF (use_finedelayctrlin = "true") THEN
rising_dly <= dly_table_rising(dly_setting) + finedly_table_rising(finedly_setting);
falling_dly <= dly_table_falling(dly_setting) + finedly_table_falling(finedly_setting);
ELSE
rising_dly <= dly_table_rising(dly_setting);
falling_dly <= dly_table_falling(dly_setting);
END IF;
end process; -- generating dynamic delays
PROCESS(datain_in)
BEGIN
if (datain_in = '0') then
tmp_dataout <= transport datain_in after (falling_dly * 1 ps);
else
tmp_dataout <= transport datain_in after (rising_dly * 1 ps);
end if;
END PROCESS;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
END stratixiii_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_clock_divider
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_io_clock_divider IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_io_clock_divider_arch OF stratixiii_io_clock_divider IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL divided_clk_in : STD_LOGIC := '0';
SIGNAL divided_clk : STD_LOGIC := '0';
-- timing outputs
SIGNAL tmp_clkout : STD_LOGIC := '0';
-- timing inputs
SIGNAL clk_in : std_logic := '0';
SIGNAL phaseselect_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL masterin_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk;
PROCESS (delayed_clk)
BEGIN
if (delayed_clk = '1') then
divided_clk <= not divided_clk_in;
end if;
END PROCESS;
tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk;
slaveout <= divided_clk;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_clkout)
variable clkout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "clkout",
OutTemp => tmp_clkout,
Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)),
GlitchData => clkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
VitalWireDelay (masterin_in, masterin, tipd_masterin);
end block;
END stratixiii_io_clock_divider_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_output_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_output_phase_alignment IS
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
-- new in STRATIXIV: ww30.2008
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "stratixiii_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_output_phase_alignment_arch OF stratixiii_output_phase_alignment IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals on clock paths
SIGNAL clk_in_delayed: STD_LOGIC := '0';
SIGNAL clk_in_mux: STD_LOGIC := '0';
SIGNAL phasectrl_clkout: STD_LOGIC := '0';
SIGNAL phaseinvertctrl_out: STD_LOGIC := '0';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg
SIGNAL sclr_in_r : STD_LOGIC := '0';
SIGNAL sload_in_r : STD_LOGIC := '0';
SIGNAL sclr_in : STD_LOGIC := '0';
SIGNAL sload_in : STD_LOGIC := '0';
SIGNAL adatasdata_in : STD_LOGIC := '0';
SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers
SIGNAL prn_in_r : STD_LOGIC := '1';
SIGNAL datain_q: STD_LOGIC := '0';
SIGNAL ddio_datain_q: STD_LOGIC := '0';
SIGNAL cycledelay_q: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_q: STD_LOGIC := '0';
SIGNAL cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL not_clk_in_mux: STD_LOGIC := '0';
SIGNAL ddio_out_clk_mux: STD_LOGIC := '0';
SIGNAL ddio_out_lo_q: STD_LOGIC := '0';
SIGNAL ddio_out_hi_q: STD_LOGIC := '0';
-- transfer delay now by negative clk
SIGNAL transfer_q: STD_LOGIC := '0';
SIGNAL ddio_transfer_q: STD_LOGIC := '0';
-- Duty Cycle Delay
SIGNAL dcd_in : STD_LOGIC := '0';
SIGNAL dcd_out : STD_LOGIC := '0';
SIGNAL dcd_both : STD_LOGIC := '0';
SIGNAL dcd_both_gnd : STD_LOGIC := '0';
SIGNAL dcd_both_vcc : STD_LOGIC := '0';
SIGNAL dcd_fallnrise : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_gnd : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_vcc : STD_LOGIC := '0';
SIGNAL dcd_rising_dly : INTEGER := 0;
SIGNAL dcd_falling_dly : INTEGER := 0;
SIGNAL dlyclk_clk: STD_LOGIC := '0';
SIGNAL dlyclk_d: STD_LOGIC := '0';
SIGNAL dlyclk_q: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_d: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_q: STD_LOGIC := '0';
SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared
SIGNAL dlyclk_extended_q: STD_LOGIC := '0';
SIGNAL dlyclk_extended_clk: STD_LOGIC := '0';
SIGNAL normal_dataout: STD_LOGIC := '0';
SIGNAL extended_dataout: STD_LOGIC := '0';
SIGNAL ddio_dataout: STD_LOGIC := '0';
SIGNAL tmp_dataout: STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL sreset_in : std_logic := '0';
SIGNAL clkena_in : std_logic := '1';
SIGNAL enaoutputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL delaymode_in: std_logic := '0';
SIGNAL dutycycledelayctrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
BEGIN
-- filtering X/U etc.
delaymode_in <= '1' WHEN (delaymode = '1') ELSE '0';
dutycycledelayctrlin_in(0) <= '1' WHEN (dutycycledelayctrlin(0) = '1') ELSE '0';
dutycycledelayctrlin_in(1) <= '1' WHEN (dutycycledelayctrlin(1) = '1') ELSE '0';
dutycycledelayctrlin_in(2) <= '1' WHEN (dutycycledelayctrlin(2) = '1') ELSE '0';
dutycycledelayctrlin_in(3) <= '1' WHEN (dutycycledelayctrlin(3) = '1') ELSE '0';
-- delay chain for clk_in delay
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting_for_delayed_clock,
use_phasectrlin => "false",
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => clk_in_delayed
);
-- clock source for datain and cycle delay registers
clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in;
-- delay chain for phase control
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
phasectrlin_limit => 10,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
-- primary outputs
normal_dataout <= dlyclk_q;
extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low
ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q;
tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE
extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE
normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE
'Z';
dataout <= tmp_dataout;
ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h
ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l
ddio_out_hi_q <= ddio_dlyclk_q;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
IF (async_mode = "clear") THEN
clrn_in_r <= not areset_in;
prn_in_r <= '1';
ELSIF (async_mode = "preset") THEN
prn_in_r <= not areset_in;
clrn_in_r <= '1';
END IF;
END PROCESS;
PROCESS(sreset_in)
BEGIN
IF (sync_mode = "clear") THEN
sclr_in_r <= sreset_in;
adatasdata_in_r <= '0';
sload_in_r <= '0';
ELSIF (sync_mode = "preset") THEN
sload_in_r <= sreset_in;
adatasdata_in_r <= '1';
sclr_in_r <= '0';
END IF;
END PROCESS;
sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r;
sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r;
adatasdata_in <= adatasdata_in_r;
dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in;
-- Datain Register
datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- DDIO Datain Register
ddio_datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- DDIO Cycle Delay Register
ddio_cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_cycledelay_q
);
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
datain_q WHEN (add_output_cycle_delay = "false") ELSE
cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
datain_q;
-- input register bypass mux
bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out;
--assign #300 transfer_q = cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
transferdelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => transfer_q
);
-- add phase transfer data path mux
dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
bypass_input_reg_mux_out;
-- clock mux for the output register
phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE
phasectrl_clkout;
-- Duty Cycle Delay
dcd_in <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux;
PROCESS(dutycycledelayctrlin_in)
variable init : boolean := true;
variable dcd_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_dly_setting : integer := 0;
begin
if (init) then
dcd_table_rising(0) := sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising(1) := sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising(2) := sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising(3) := sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising(4) := sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising(5) := sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising(6) := sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising(7) := sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising(8) := sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising(9) := sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising(10) := sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising(11) := sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising(12) := sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising(13) := sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising(14) := sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising(15) := sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling(0) := sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling(1) := sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling(2) := sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling(3) := sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling(4) := sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling(5) := sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling(6) := sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling(7) := sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling(8) := sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling(9) := sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling(10) := sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling(11) := sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling(12) := sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling(13) := sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling(14) := sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling(15) := sim_dutycycledelayctrlin_falling_delay_15;
init := false;
end if;
dcd_dly_setting := alt_conv_integer(dutycycledelayctrlin_in);
dcd_rising_dly <= dcd_table_rising(dcd_dly_setting);
dcd_falling_dly <= dcd_table_falling(dcd_dly_setting);
end process; -- generating dynamic delays
PROCESS(dcd_in)
BEGIN
dcd_both_gnd <= dcd_in;
if (dcd_in = '0') then
dcd_both_vcc <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_both_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
PROCESS(dcd_in)
BEGIN
if (dcd_in = '0') then
dcd_fallnrise_gnd <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_fallnrise_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
dcd_both <= dcd_both_vcc WHEN (delaymode_in = '1') ELSE dcd_both_gnd;
dcd_fallnrise <= dcd_fallnrise_vcc WHEN (delaymode_in = '1') ELSE dcd_fallnrise_gnd;
dlyclk_clk <= dcd_both WHEN (duty_cycle_delay_mode = "both") ELSE
dcd_fallnrise WHEN (duty_cycle_delay_mode = "fallnrise") ELSE dcd_in;
-- Output Register clocked by phasectrl_clk
dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
-- enaoutputcycledelay data path mux
ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE
ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
ddio_datain_q;
-- input register bypass mux
ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out;
--assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
not_clk_in_mux <= not clk_in_mux;
ddio_transferdelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_transfer_q
);
-- add phase transfer data path mux
ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
ddio_bypass_input_reg_mux_out;
-- Output Register clocked by phasectrl_clk
ddio_dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_dlyclk_q
);
-- Extension Register
dlyclk_extended_clk <= not dlyclk_clk;
dlyclk_extended_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_q,
clk => dlyclk_extended_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_extended_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (sreset_in, sreset, tipd_sreset);
VitalWireDelay (clkena_in, clkena, tipd_clkena);
VitalWireDelay (enaoutputcycledelay_in, enaoutputcycledelay, tipd_enaoutputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_output_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_input_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_input_phase_alignment IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END;
ARCHITECTURE stratixiii_input_phase_alignment_arch OF stratixiii_input_phase_alignment IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL not_delayed_clk : STD_LOGIC := '1';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
SIGNAL datain_q : STD_LOGIC := '0';
SIGNAL cycledelay_q : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0';
SIGNAL dlyclk_d : STD_LOGIC := '0';
SIGNAL dlyclk_q : STD_LOGIC := '0';
SIGNAL tmp_dataout : STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL enainputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
-- primary output
dataout <= tmp_dataout;
tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q;
-- add phase transfer data path mux
dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE
cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE
cycledelay_mux_out;
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE
datain_q WHEN (add_input_cycle_delay = "false") ELSE
cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE
datain_q;
-- resolve reset modes
PROCESS (areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
-- Datain Register
datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
-- Transfer Register - clocked by negative edge
not_delayed_clk <= not delayed_clk;
transfer_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => cycledelay_mux_out,
clk => not_delayed_clk, -- ~delayed_clk
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_mux_out_dly
);
-- Register clocked by actually by clk_in
dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_input_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_half_rate_input
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
ENTITY stratixiii_half_rate_input IS
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "stratixiii_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiii_half_rate_input_arch OF stratixiii_half_rate_input IS
-- component section
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO SIGNAListers
-- common
SIGNAL neg_clk_in : STD_LOGIC := '0';
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
-- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
-- high_bank = {3, 2} - output of SIGNALister datain at rising
SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank_low : STD_LOGIC := '0';
SIGNAL low_bank_high : STD_LOGIC := '0';
SIGNAL high_bank_low : STD_LOGIC := '0';
SIGNAL high_bank_high: STD_LOGIC := '0';
SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
-- delayed version to ensure 1 latency as expected in functional sim
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
-- timing inputs
SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL directin_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL areset_in : std_logic := '0';
SIGNAL dataoutbypass_in: std_logic := '0';
BEGIN
-- primary input
datain_in <= transport datain_ipd after 2 ps;
-- primary output
dataout <= tmp_dataout;
tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high;
tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low;
tmp_dataout(1) <= low_bank(1);
tmp_dataout(0) <= low_bank(0);
low_bank <= low_bank_high & low_bank_low;
high_bank <= high_bank_high & high_bank_low;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
neg_clk_in <= not clk_in;
-- datain_1 - H
reg1_h : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_high
);
-- datain_0 - H
reg0_h : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_low
);
-- datain_1 - L (n)
reg1_l_n : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(1)
);
-- datain_1 - L
reg1_l : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_high
);
-- datain_0 - L (n)
reg0_l_n : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(0)
);
-- datain_0 - L
reg0_l : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_low
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (directin_in, directin, tipd_directin);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass);
end block;
END stratixiii_half_rate_input_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
-- new STRATIXIV: ww30.2008
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_io_config_arch OF stratixiii_io_config IS
-- component section
SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL enhance_shift_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_output_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_tmp_output : std_logic_vector(22 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= enhance_shift_reg(22) WHEN (enhanced_mode = "true") ELSE shift_reg(10);
-- bit order changed in wys revision 1.32
outputdelaysetting1 <= tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7);
-- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0);
-- outputdelaysetting1 <= tmp_output(7 DOWNTO 4);
-- outputdelaysetting2 <= tmp_output(10 DOWNTO 8);
tmp_output <= output_reg;
outputdelaysetting1 <= enhance_tmp_output(3 DOWNTO 0) WHEN (enhanced_mode = "true") ELSE tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= enhance_tmp_output(6 DOWNTO 4) WHEN (enhanced_mode = "true") ELSE tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= enhance_tmp_output(10 DOWNTO 7) WHEN (enhanced_mode = "true") ELSE tmp_output(10 DOWNTO 7);
outputfinedelaysetting1 <= enhance_tmp_output(11) WHEN (enhanced_mode = "true") ELSE '0';
outputfinedelaysetting2 <= enhance_tmp_output(12) WHEN (enhanced_mode = "true") ELSE '0';
padtoinputregisterfinedelaysetting <= enhance_tmp_output(13) WHEN (enhanced_mode = "true") ELSE '0';
outputonlyfinedelaysetting2 <= enhance_tmp_output(14) WHEN (enhanced_mode = "true") ELSE '0';
outputonlydelaysetting2 <= enhance_tmp_output(17 DOWNTO 15) WHEN (enhanced_mode = "true") ELSE "000";
dutycycledelaymode <= enhance_tmp_output(18) WHEN (enhanced_mode = "true") ELSE '0';
dutycycledelaysettings <= enhance_tmp_output(22 DOWNTO 19) WHEN (enhanced_mode = "true") ELSE "0000";
tmp_output <= output_reg;
enhance_tmp_output <= enhance_output_reg;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0);
enhance_shift_reg(0) <= datain_in;
enhance_shift_reg(22 DOWNTO 1) <= enhance_shift_reg(21 DOWNTO 0);
end if;
END PROCESS;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end if;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_io_config_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_dqs_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_config_arch OF stratixiii_dqs_config IS
-- component section
SIGNAL shift_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL output_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_output : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= shift_reg(47) WHEN (enhanced_mode = "true")ELSE shift_reg(45);
dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0);
dqsinputphasesetting <= tmp_output(6 DOWNTO 4);
dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7);
dqsoutputphasesetting <= tmp_output(14 DOWNTO 11);
dqoutputphasesetting <= tmp_output(18 DOWNTO 15);
resyncinputphasesetting <= tmp_output(22 DOWNTO 19);
dividerphasesetting <= tmp_output(23);
enaoctcycledelaysetting <= tmp_output(24);
enainputcycledelaysetting <= tmp_output(25);
enaoutputcycledelaysetting<= tmp_output(26);
dqsenabledelaysetting <= tmp_output(29 DOWNTO 27);
octdelaysetting1 <= tmp_output(33 DOWNTO 30);
octdelaysetting2 <= tmp_output(36 DOWNTO 34);
enadataoutbypass <= tmp_output(37);
enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23
enaoctphasetransferreg <= tmp_output(39); -- new in 1.23
enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23
enainputphasetransferreg <= tmp_output(41); -- new in 1.23
resyncinputphaseinvert <= tmp_output(42); -- new in 1.26
dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26
dqoutputphaseinvert <= tmp_output(44); -- new in 1.26
dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26
-- new in STRATIXIV: ww30.2008
dqsbusoutfinedelaysetting <= tmp_output(46) WHEN (enhanced_mode = "true") ELSE '0';
dqsenablefinedelaysetting <= tmp_output(47) WHEN (enhanced_mode = "true") ELSE '0';
tmp_output <= output_reg;
PROCESS(clk_in)
begin
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(47 DOWNTO 1) <= shift_reg(46 DOWNTO 0);
end if;
end process;
PROCESS(clk_in)
begin
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_config_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_bit_register --
-- Description: Stratix III MAC single bit register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_bit_register IS
GENERIC (
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_mac_bit_register;
ARCHITECTURE arch OF stratixiii_mac_bit_register IS
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic := '0';
SIGNAL dataout_reg : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_register --
-- Description: Stratix III MAC variable width register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_register IS
GENERIC (
data_width : integer := 18;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END stratixiii_mac_register;
ARCHITECTURE arch OF stratixiii_mac_register IS
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= (OTHERS => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
END process;
sh: block
begin
g0 : for i in datain'range generate
process(datain_ipd(i),clk_ipd,sload_ipd)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
begin
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd(i),
TestSignalName => "DATAIN(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge(i),
SetupLow => tsetup_datain_clk_noedge_posedge(i),
HoldHigh => thold_datain_clk_noedge_posedge(i),
HoldLow => thold_datain_clk_noedge_posedge(i),
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
end generate g0;
end block;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_multiplier --
-- Description: Stratix III MAC signed multiplier --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_multiplier IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END stratixiii_mac_multiplier;
ARCHITECTURE arch OF stratixiii_mac_multiplier IS
constant dataout_width : integer := dataa_width + datab_width;
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL product_sign : std_logic := '0';
SIGNAL dataa_sign : std_logic := '0';
SIGNAL datab_sign : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
product_sign <= dataa_sign XOR datab_sign ;
abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd;
abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd;
abs_product <= abs_a * abs_b ;
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
PathDelay : block
begin
do : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_mult_atom --
-- Description: Simulation model for stratixiii mac mult atom. --
-- This model instantiates the following components. --
-- 1.stratixiii_mac_bit_register. --
-- 2.stratixiii_mac_register. --
-- 3.stratixiii_mac_multiplier. --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_mac_mult;
ARCHITECTURE arch OF stratixiii_mac_mult IS
constant dataout_width : integer := dataa_width + datab_width;
COMPONENT stratixiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_mac_multiplier
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END COMPONENT;
--Internal signals to instantiate the dataa input register unit
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic := '0';
SIGNAL dataa_aclr : std_logic := '0';
SIGNAL dataa_sload : std_logic := '0';
SIGNAL dataa_bypass_register : std_logic := '0';
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the datab input register unit
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic := '0';
SIGNAL datab_aclr : std_logic := '0';
SIGNAL datab_sload : std_logic := '0';
SIGNAL datab_bypass_register : std_logic := '0';
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the signa input register unit
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic := '0';
SIGNAL signa_aclr : std_logic := '0';
SIGNAL signa_sload : std_logic := '0';
SIGNAL signa_bypass_register : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--Internal signbls to instantiate the signb input register unit
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic := '0';
SIGNAL signb_aclr : std_logic := '0';
SIGNAL signb_sload : std_logic := '0';
SIGNAL signb_bypass_register : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--Internal scanoutals to instantiate the scanouta input register unit
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_clk : std_logic := '0';
SIGNAL scanouta_aclr : std_logic := '0';
SIGNAL scanouta_sload : std_logic := '0';
SIGNAL scanouta_bypass_register : std_logic := '0';
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal Signals to instantiate the mac multiplier
SIGNAL signa_mult : std_logic := '0';
SIGNAL signb_mult : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
BEGIN
--Instantiate the dataa input Register
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
ELSE "0001" WHEN (dataa_clock = "1")
ELSE "0010" WHEN (dataa_clock = "2")
ELSE "0011" WHEN (dataa_clock = "3")
ELSE "0000" ;
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
ELSE "0001" WHEN (dataa_clear = "1")
ELSE "0010" WHEN (dataa_clear = "2")
ELSE "0011" WHEN (dataa_clear = "3")
ELSE "0000" ;
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
dataa_in <= dataa;
dataa_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in,
clk => dataa_clk,
aclr => dataa_aclr,
sload => dataa_sload,
bypass_register => dataa_bypass_register,
dataout => dataa_in_reg
);
--Instantiate the datab input Register
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
ELSE "0001" WHEN (datab_clock = "1")
ELSE "0010" WHEN (datab_clock = "2")
ELSE "0011" WHEN (datab_clock = "3")
ELSE "0000" ;
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
ELSE "0001" WHEN (datab_clear = "1")
ELSE "0010" WHEN (datab_clear = "2")
ELSE "0011" WHEN (datab_clear = "3")
ELSE "0000" ;
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
datab_in <= datab;
datab_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => datab_width
)
PORT MAP (
datain => datab_in,
clk => datab_clk,
aclr => datab_aclr,
sload => datab_sload,
bypass_register => datab_bypass_register,
dataout => datab_in_reg
);
--Instantiate the signa input Register
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk,
aclr => signa_aclr,
sload => signa_sload,
bypass_register => signa_bypass_register,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk,
aclr => signb_aclr,
sload => signb_sload,
bypass_register => signb_bypass_register,
dataout => signb_in_reg
);
--Instantiate the scanouta input Register
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
ELSE "0001" WHEN (scanouta_clock = "1")
ELSE "0010" WHEN (scanouta_clock = "2")
ELSE "0011" WHEN (scanouta_clock = "3")
ELSE "0000" ;
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
ELSE "0001" WHEN (scanouta_clear = "1")
ELSE "0010" WHEN (scanouta_clear = "2")
ELSE "0011" WHEN (scanouta_clear = "3")
ELSE "0000" ;
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
scanouta_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in_reg,
clk => scanouta_clk,
aclr => scanouta_aclr,
sload => scanouta_sload,
bypass_register => scanouta_bypass_register,
dataout => scanouta
);
--Instantiate mac_multiplier block
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
mac_multiplier : stratixiii_mac_multiplier
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => dataa_in_reg,
datab => datab_in_reg,
signa => signa_mult,
signb => signb_mult,
dataout => dataout
);
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_fsa_isse --
-- Description: Stratix III first stage adder input selection and sign extension block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_fsa_isse IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
chainin_width : integer := 44;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
operation_mode : string := "output_only"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
datab_out : OUT std_logic_vector(71 DOWNTO 0);
datac_out : OUT std_logic_vector(71 DOWNTO 0);
datad_out : OUT std_logic_vector(71 DOWNTO 0);
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END stratixiii_fsa_isse;
ARCHITECTURE arch OF stratixiii_fsa_isse IS
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
signal sign :std_logic := '0';
BEGIN
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
"0001" WHEN (operation_mode = "one_level_adder") ELSE
"0010" WHEN (operation_mode = "loopback") ELSE
"0011" WHEN (operation_mode = "accumulator") ELSE
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
"0101" WHEN (operation_mode = "two_level_adder") ELSE
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
"1000" WHEN (operation_mode = "shift") ELSE
"1001" WHEN (operation_mode = "double") ELSE "0000";
sign <= signa or signb;
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
variable active_signb : std_logic := '0';
variable active_signc : std_logic := '0';
variable active_signd : std_logic := '0';
variable read_new_param : std_logic := '0';
variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false"
AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false"
AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false"
AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN
read_new_param := '0' ;
ELSE
read_new_param := '1' ;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then
active_signb := signb;
elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then
active_signb := signa;
elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then
active_signb := sign;
else
active_signb := '0';
end if;
ELSE
active_signb := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then
active_signc := signb;
elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then
active_signc := signa;
elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then
active_signc := sign;
else
active_signc := '0';
end if;
ELSE
active_signc := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then
active_signd := signb;
elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then
active_signd := signa;
elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then
active_signd := sign;
else
active_signd := '0';
end if;
ELSE
active_signd := sign;
END IF;
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
ELSE
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN
datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN
datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN
datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSIF(operation_mode = "double") THEN
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
ELSIF(operation_mode = "double")THEN
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF (chainin(chainin_width - 1) = '1') THEN
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
ELSE
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
END IF;
IF(read_new_param = '1') THEN
datab_out_tmp <= datab_out_tim_tmp;
datac_out_tmp <= datac_out_tim_tmp;
datad_out_tmp <= datad_out_tim_tmp;
ELSE
datab_out_tmp <= datab_out_fun_tmp;
datac_out_tmp <= datac_out_fun_tmp;
datad_out_tmp <= datad_out_fun_tmp;
END IF;
END process;
dataa_out <= dataa_out_tmp;
datab_out <= datab_out_tmp;
datac_out <= datac_out_tmp;
datad_out <= datad_out_tmp;
chainin_out <= chainin_out_tmp;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_first_stage_add_sub --
-- Description: Stratix III First Stage Adder Subtractor Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_first_stage_add_sub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_first_stage_add_sub;
ARCHITECTURE arch OF stratixiii_first_stage_add_sub IS
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_a : std_logic := '0';
SIGNAL sign_b : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
ELSE
IF(fsa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
END IF;
END IF;
END IF;
END process ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_second_stage_add_accum --
-- Description: Stratix III Second stage Adder and Accumulator/Decimator Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_second_stage_add_accum IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END stratixiii_second_stage_add_accum;
ARCHITECTURE arch OF stratixiii_second_stage_add_accum IS
constant accum_width : integer := dataa_width + 7;
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 :for i in accumin'range generate
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
IF(ssa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
ELSE
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
ELSE
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
END IF;
END IF;
IF(sign_ipd = '1')THEN
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
ELSE
IF(ssa_mode = "add")THEN
overflow_tmp <= dataout_tmp(accum_width);
ELSE
overflow_tmp <= 'X';
END IF;
END IF;
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
overflow_tmp <= '0';
IF (sign_ipd = '1') THEN
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
overflow_tmp <= '0';
ELSIF ((operation = "1001")) THEN --double mode
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
overflow_tmp <= '0';
END IF;
dataout_temp <= dataout_tmp;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_temp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_temp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(overflow_tmp)
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => overflow,
OutSignalName => "overflow",
OutTemp => overflow_tmp,
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
GlitchData => overflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_round_block --
-- Description: Stratix III round block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_round_block IS
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_round_block;
ARCHITECTURE arch OF stratixiii_round_block IS
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
dataout <= out_tmp ;
PROCESS(datain,round,datain_width)
variable i : integer ;
variable j : integer ;
variable sign : std_logic ;
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
if(round = '0')then
dataout_value := datain;
else
dataout_value := datain;
j := 0;
sign := '0';
IF( conv_integer(datain_width) > round_width) THEN
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
result_tmp(j) := datain(i);
j := j + 1;
END LOOP;
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
sign := sign or datain(i);
dataout_value(i) := 'X';
END LOOP;
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
dataout_tmp := result_tmp;
ELSE
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
dataout_tmp := result_tmp + '1';
ELSE
IF (round_mode = "nearest_even") THEN --unbiased rounding
IF(result_tmp(0) = '1') THEN --check for odd integer
dataout_tmp := result_tmp + '1' ;
ELSE
dataout_tmp := result_tmp;
END IF;
ELSE --biased rounding
dataout_tmp := result_tmp + '1';
END IF;
END IF;
END IF;
j := conv_integer(datain_width) - round_width;
FOR i IN 0 to (round_width -1)LOOP
dataout_value(j) := dataout_tmp(i);
j := j + 1;
END LOOP;
ELSE
dataout_value := datain;
END IF;
end if;
out_tmp <= dataout_value;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_saturate_block --
-- Description: Stratix III saturation block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
saturation_overflow : OUT std_logic
);
END stratixiii_saturate_block;
ARCHITECTURE arch OF stratixiii_saturate_block IS
constant accum_width : integer := dataa_width + 8;
SIGNAL saturation_overflow_tmp : std_logic := '0';
signal msb : std_logic := '0';
signal sign : std_logic := '0';
signal min : std_logic_vector(71 downto 0):=(others => '1');
signal max : std_logic_vector(71 downto 0):=(others => '0');
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL i : integer;
BEGIN
sign <= signa OR signb ;
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
ELSE datain(dataa_width -1);
dataout <= dataout_tmp ;
saturation_overflow <= saturation_overflow_tmp ;
PROCESS(datain,datain_width,round,saturate,sign,msb)
variable saturation_temp : std_logic := '0';
variable sign_tmp : std_logic := '1';
variable data_tmp : std_logic := '0';
BEGIN
IF (saturate = '0') THEN
dataout_tmp <= datain;
saturation_overflow_tmp <= '0';
ELSE
saturation_temp := '0';
data_tmp := '0';
sign_tmp := '1';
IF (round = '1') THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
max(i) <= 'X';
END LOOP;
END IF;
IF (saturate_mode = "symmetric") THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
IF (round = '1') THEN
max(i) <= 'X';
min(i) <= 'X';
ELSE
max(i) <= '1';
min(i) <= '0';
END IF;
END LOOP;
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
data_tmp := data_tmp or datain(i);
max(i) <= '1';
min(i) <= '0';
END LOOP;
IF (round = '1') THEN
min(conv_integer(datain_width) - round_width) <= '1';
ELSE
min(0) <= '1';
END IF;
END IF;
IF (saturate_mode = "asymmetric") THEN
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
max(i) <= '1';
min(i) <= '0';
END LOOP;
END IF;
if((saturate_width = 1))then
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
saturation_temp := '1';
ELSE
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
END IF;
else
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
sign_tmp := sign_tmp and datain(i);
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
saturation_temp := '1';
end if;
END LOOP;
end if;
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
saturation_temp := '1';
end if;
saturation_overflow_tmp <= saturation_temp;
IF (saturation_temp = '1') THEN
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
IF (sign = '1') THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
dataout_tmp <= (others => 'X');
END IF;
END IF;
ELSE
dataout_tmp <= datain;
END IF;
END IF;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_round_saturate_block --
-- Description: Stratix III round and saturation Unit. --
-- This unit instantiated the following components. --
-- 1.stratixiii_round_block. --
-- 2.stratixiii_saturate_block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_round_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
round_mode : string := "nearest_integer";
operation_mode : string := "output_only" ;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_round : VitalDelayType01 :=DefPropDelay01;
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0);
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END stratixiii_round_saturate_block;
ARCHITECTURE arch OF stratixiii_round_saturate_block IS
COMPONENT stratixiii_round_block
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_saturate_block
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturation_overflow : OUT std_logic
);
END COMPONENT;
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL saturationoverflow_tmp : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
VitalWireDelay (round_ipd, round, tipd_round);
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
end block;
round_unit : stratixiii_round_block
GENERIC MAP (
operation_mode => operation_mode,
round_width => round_width,
round_mode => round_mode
)
PORT MAP (
datain => datain_ipd,
round => round_ipd,
datain_width => datain_width,
dataout => dataout_round
);
saturate_unit : stratixiii_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
saturate_mode => saturate_mode,
saturate_width =>saturate_width,
round_width =>round_width
)
PORT MAP (
datain => dataout_round,
saturate => saturate_ipd,
round => round_ipd,
signa => signa_ipd,
signb => signb_ipd,
datain_width => datain_width,
dataout => dataout_saturate,
saturation_overflow => saturationoverflow_tmp
);
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_saturate(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_saturate(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(saturationoverflow_tmp)
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => saturationoverflow,
OutSignalName => "saturationoverflow",
OutTemp => saturationoverflow_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
GlitchData => saturationoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_rotate_shift_block --
-- Description: Stratix III roate and shift Unit. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_rotate_shift_block IS
GENERIC (
dataa_width : integer := 32;
datab_width : integer := 32;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_rotate_shift_block;
ARCHITECTURE arch OF stratixiii_rotate_shift_block IS
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL rotate_ipd : std_logic := '0';
SIGNAL shiftright_ipd : std_logic := '0';
SIGNAL sign : std_logic;
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signa, tipd_signa);
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
end block;
PROCESS
BEGIN
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT;
sign <= signa_ipd xor signb_ipd;
dataout_tmp <= datain;
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
ELSE
dataout_tmp <= datain_ipd;
END IF;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_carry_chain_adder --
-- Description: Stratix III carry Chain Adder --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_carry_chain_adder IS
GENERIC(
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
);
END stratixiii_carry_chain_adder;
ARCHITECTURE arch OF stratixiii_carry_chain_adder IS
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_out_atom --
-- Description: Simulation model for stratixiii mac out atom --
-- This model instantiates the following components --
-- 1.stratixiii_mac_bit_register --
-- 2.stratixiii_mac_register --
-- 3.stratixiii_fsa_isse --
-- 4.stratixiii_first_stage_add_sub --
-- 5.stratixiii_second_stage_add_accum --
-- 6.stratixiii_round_saturate_block --
-- 7.stratixiii_rotate_shift_block --
-- 8.stratixiii_carry_chain_adder --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiii_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END stratixiii_mac_out;
ARCHITECTURE arch OF stratixiii_mac_out IS
COMPONENT stratixiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_fsa_isse
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
chainin_width : integer := 44;
operation_mode : string := "output_only";
datad_width : integer := 36;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
datac_width : integer := 36
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_first_stage_add_sub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_second_stage_add_accum
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_round_saturate_block
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only";
round_mode : string := "nearest_integer"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_rotate_shift_block
GENERIC (
datab_width : integer := 32;
dataa_width : integer := 32
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_carry_chain_adder
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
--signals for zeroloopback input register
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_ir : std_logic := '0';
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
SIGNAL zeroloopback_sload_ir : std_logic := '0';
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
SIGNAL zeroloopback_in_reg : std_logic := '0';
SIGNAL zeroloopback_in : std_logic := '0';
--signals for zeroacc input register
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_ir : std_logic := '0';
SIGNAL zeroacc_aclr_ir : std_logic := '0';
SIGNAL zeroacc_sload_ir : std_logic := '0';
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
SIGNAL zeroacc_in_reg : std_logic := '0';
SIGNAL zeroacc_in : std_logic := '0';
--Signals for signa input register
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_ir : std_logic := '0';
SIGNAL signa_aclr_ir : std_logic := '0';
SIGNAL signa_sload_ir : std_logic := '0';
SIGNAL signa_bypass_register_ir : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--signals for signb input register
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_ir : std_logic := '0';
SIGNAL signb_aclr_ir : std_logic := '0';
SIGNAL signb_sload_ir : std_logic := '0';
SIGNAL signb_bypass_register_ir : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--signals for rotate input register
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_ir : std_logic := '0';
SIGNAL rotate_aclr_ir : std_logic := '0';
SIGNAL rotate_sload_ir : std_logic := '0';
SIGNAL rotate_bypass_register_ir: std_logic := '0';
SIGNAL rotate_in_reg : std_logic := '0';
SIGNAL rotate_in : std_logic := '0';
--signals for shiftright input register
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_ir : std_logic := '0';
SIGNAL shiftright_aclr_ir : std_logic := '0';
SIGNAL shiftright_sload_ir : std_logic := '0';
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
SIGNAL shiftright_in_reg : std_logic := '0';
SIGNAL shiftright_in : std_logic := '0';
--signals for round input register
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_ir : std_logic := '0';
SIGNAL round_aclr_ir : std_logic := '0';
SIGNAL round_sload_ir : std_logic := '0';
SIGNAL round_bypass_register_ir : std_logic := '0';
SIGNAL round_in_reg : std_logic := '0';
SIGNAL round_in : std_logic := '0';
--signals for saturate input register
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_ir : std_logic := '0';
SIGNAL saturate_aclr_ir : std_logic := '0';
SIGNAL saturate_sload_ir : std_logic := '0';
SIGNAL saturate_bypass_register_ir : std_logic := '0';
SIGNAL saturate_in_reg : std_logic := '0';
SIGNAL saturate_in : std_logic := '0';
--signals for roundchainout input register
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_ir : std_logic := '0';
SIGNAL roundchainout_aclr_ir : std_logic := '0';
SIGNAL roundchainout_sload_ir : std_logic := '0';
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
SIGNAL roundchainout_in_reg : std_logic := '0';
SIGNAL roundchainout_in : std_logic := '0';
--signals for saturatechainout input register
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_ir : std_logic := '0';
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
SIGNAL saturatechainout_sload_ir: std_logic := '0';
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
SIGNAL saturatechainout_in_reg : std_logic := '0';
SIGNAL saturatechainout_in : std_logic := '0';
--signals for fsa_input_interface
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
--Signals for First Stage Adder units
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_fsa0 : std_logic := '0';
SIGNAL overflow_fsa1 : std_logic := '0';
--signals for zeroloopback pipeline register
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_pip : std_logic := '0';
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
SIGNAL zeroloopback_sload_pip : std_logic := '0';
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
SIGNAL zeroloopback_pip_reg : std_logic := '0';
--signals for zeroacc pipeline register
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_pip : std_logic := '0';
SIGNAL zeroacc_aclr_pip : std_logic := '0';
SIGNAL zeroacc_sload_pip : std_logic := '0';
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
SIGNAL zeroacc_pip_reg : std_logic := '0';
--Signals for signa pipeline register
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_pip : std_logic := '0';
SIGNAL signa_aclr_pip : std_logic := '0';
SIGNAL signa_sload_pip : std_logic := '0';
SIGNAL signa_bypass_register_pip: std_logic := '0';
SIGNAL signa_pip_reg : std_logic := '0';
--signals for signb pipeline register
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_pip : std_logic := '0';
SIGNAL signb_aclr_pip : std_logic := '0';
SIGNAL signb_sload_pip : std_logic := '0';
SIGNAL signb_bypass_register_pip: std_logic := '0';
SIGNAL signb_pip_reg : std_logic := '0';
--signals for rotate pipeline register
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_pip : std_logic := '0';
SIGNAL rotate_aclr_pip : std_logic := '0';
SIGNAL rotate_sload_pip : std_logic := '0';
SIGNAL rotate_bypass_register_pip : std_logic := '0';
SIGNAL rotate_pip_reg : std_logic := '0';
--signals for shiftright pipeline register
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_pip : std_logic := '0';
SIGNAL shiftright_aclr_pip : std_logic := '0';
SIGNAL shiftright_sload_pip : std_logic := '0';
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
SIGNAL shiftright_pip_reg : std_logic := '0';
--signals for round pipeline register
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_pip : std_logic := '0';
SIGNAL round_aclr_pip : std_logic := '0';
SIGNAL round_sload_pip : std_logic := '0';
SIGNAL round_bypass_register_pip: std_logic := '0';
SIGNAL round_pip_reg : std_logic := '0';
--signals for saturate pipeline register
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_pip : std_logic := '0';
SIGNAL saturate_aclr_pip : std_logic := '0';
SIGNAL saturate_sload_pip : std_logic := '0';
SIGNAL saturate_bypass_register_pip : std_logic := '0';
SIGNAL saturate_pip_reg : std_logic := '0';
--signals for roundchainout pipeline register
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_pip : std_logic := '0';
SIGNAL roundchainout_aclr_pip : std_logic := '0';
SIGNAL roundchainout_sload_pip : std_logic := '0';
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
SIGNAL roundchainout_pip_reg : std_logic := '0';
--signals for saturatechainout pipeline register
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_pip : std_logic := '0';
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
SIGNAL saturatechainout_sload_pip : std_logic := '0';
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
SIGNAL saturatechainout_pip_reg : std_logic := '0';
--signals for fsa0 pipeline register
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_clk_pip : std_logic := '0';
SIGNAL fsa0_aclr_pip : std_logic := '0';
SIGNAL fsa0_sload_pip : std_logic := '0';
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--signals for fsa1 pipeline register
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_clk_pip : std_logic := '0';
SIGNAL fsa1_aclr_pip : std_logic := '0';
SIGNAL fsa1_sload_pip : std_logic := '0';
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--Signals for second stage adder
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_sign : std_logic := '0';
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_overflow : std_logic := '0';
--Signals for RS block
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow : std_logic := '0';
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
--signals for zeroloopback output register
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_or : std_logic := '0';
SIGNAL zeroloopback_aclr_or : std_logic := '0';
SIGNAL zeroloopback_sload_or : std_logic := '0';
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
SIGNAL zeroloopback_out_reg : std_logic := '0';
--signals for zerochainout output register
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_clk_or : std_logic := '0';
SIGNAL zerochainout_aclr_or : std_logic := '0';
SIGNAL zerochainout_sload_or : std_logic := '0';
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
SIGNAL zerochainout_out_reg : std_logic := '0';
--Signals for saturation_overflow output register
SIGNAL rs_saturation_overflow_in : std_logic := '0';
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_clk_or : std_logic := '0';
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
SIGNAL saturation_overflow_sload_or : std_logic := '0';
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
SIGNAL saturation_overflow_out_reg : std_logic := '0';
--signals for rs_dataout output register
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clk_or : std_logic := '0';
SIGNAL rs_dataout_aclr_or : std_logic := '0';
SIGNAL rs_dataout_sload_or : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
--signals for rotate output register
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_or : std_logic := '0';
SIGNAL rotate_aclr_or : std_logic := '0';
SIGNAL rotate_sload_or : std_logic := '0';
SIGNAL rotate_bypass_register_or: std_logic := '0';
SIGNAL rotate_out_reg : std_logic := '0';
--signals for shiftright output register
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_or : std_logic := '0';
SIGNAL shiftright_aclr_or : std_logic := '0';
SIGNAL shiftright_sload_or : std_logic := '0';
SIGNAL shiftright_bypass_register_or : std_logic := '0';
SIGNAL shiftright_out_reg : std_logic := '0';
--signals for roundchainout output register
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_or : std_logic := '0';
SIGNAL roundchainout_aclr_or : std_logic := '0';
SIGNAL roundchainout_sload_or : std_logic := '0';
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
SIGNAL roundchainout_out_reg : std_logic := '0';
--signals for saturatechainout output register
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_or : std_logic := '0';
SIGNAL saturatechainout_aclr_or : std_logic := '0';
SIGNAL saturatechainout_sload_or: std_logic := '0';
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
SIGNAL saturatechainout_out_reg : std_logic := '0';
--Signals for chainout Adder RS Block
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
--signals for control signals for COA output register
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_clk_or : std_logic := '0';
SIGNAL coa_reg_aclr_or : std_logic := '0';
SIGNAL coa_reg_sload_or : std_logic := '0';
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
SIGNAL coa_reg_out_reg : std_logic := '0';
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_tmp : std_logic := '0';
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign : std_logic := '0';
BEGIN
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
begin
rs_tmp := rs_dataout;
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
end if;
rs_dataout_of <= rs_tmp;
end process;
--Instantiate the zeroloopback input Register
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
ELSE "0001" WHEN (zeroloopback_clock = "1")
ELSE "0010" WHEN (zeroloopback_clock = "2")
ELSE "0011" WHEN (zeroloopback_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
ELSE "0001" WHEN (zeroloopback_clear = "1")
ELSE "0010" WHEN (zeroloopback_clear = "2")
ELSE "0011" WHEN (zeroloopback_clear = "3")
ELSE "0000" ;
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
zeroloopback_in <= zeroloopback;
zeroloopback_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in,
clk => zeroloopback_clk_ir,
aclr => zeroloopback_aclr_ir,
sload => zeroloopback_sload_ir,
bypass_register => zeroloopback_bypass_register_ir,
dataout => zeroloopback_in_reg
);
--Instantiate the zeroacc input Register
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
ELSE "0001" WHEN (zeroacc_clock = "1")
ELSE "0010" WHEN (zeroacc_clock = "2")
ELSE "0011" WHEN (zeroacc_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
ELSE "0001" WHEN (zeroacc_clear = "1")
ELSE "0010" WHEN (zeroacc_clear = "2")
ELSE "0011" WHEN (zeroacc_clear = "3")
ELSE "0000" ;
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
zeroacc_in <= zeroacc;
zeroacc_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroacc_in,
clk => zeroacc_clk_ir,
aclr => zeroacc_aclr_ir,
sload => zeroacc_sload_ir,
bypass_register => zeroacc_bypass_register_ir,
dataout => zeroacc_in_reg
);
--Instantiate the signa input Register
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk_ir,
aclr => signa_aclr_ir,
sload => signa_sload_ir,
bypass_register => signa_bypass_register_ir,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk_ir,
aclr => signb_aclr_ir,
sload => signb_sload_ir,
bypass_register => signb_bypass_register_ir,
dataout => signb_in_reg
);
--Instantiate the rotate input Register
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
ELSE "0001" WHEN (rotate_clock = "1")
ELSE "0010" WHEN (rotate_clock = "2")
ELSE "0011" WHEN (rotate_clock = "3")
ELSE "0000" ;
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
ELSE "0001" WHEN (rotate_clear = "1")
ELSE "0010" WHEN (rotate_clear = "2")
ELSE "0011" WHEN (rotate_clear = "3")
ELSE "0000" ;
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
rotate_in <= rotate;
rotate_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_in,
clk => rotate_clk_ir,
aclr => rotate_aclr_ir,
sload => rotate_sload_ir,
bypass_register => rotate_bypass_register_ir,
dataout => rotate_in_reg
);
--Instantiate the shiftright input Register
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
ELSE "0001" WHEN (shiftright_clock = "1")
ELSE "0010" WHEN (shiftright_clock = "2")
ELSE "0011" WHEN (shiftright_clock = "3")
ELSE "0000" ;
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
ELSE "0001" WHEN (shiftright_clear = "1")
ELSE "0010" WHEN (shiftright_clear = "2")
ELSE "0011" WHEN (shiftright_clear = "3")
ELSE "0000" ;
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
shiftright_in <= shiftright;
shiftright_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_in,
clk => shiftright_clk_ir,
aclr => shiftright_aclr_ir,
sload => shiftright_sload_ir,
bypass_register => shiftright_bypass_register_ir,
dataout => shiftright_in_reg
);
--Instantiate the round input Register
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
ELSE "0001" WHEN (round_clock = "1")
ELSE "0010" WHEN (round_clock = "2")
ELSE "0011" WHEN (round_clock = "3")
ELSE "0000" ;
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
ELSE "0001" WHEN (round_clear = "1")
ELSE "0010" WHEN (round_clear = "2")
ELSE "0011" WHEN (round_clear = "3")
ELSE "0000" ;
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
round_in <= round;
round_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => round_in,
clk => round_clk_ir,
aclr => round_aclr_ir,
sload => round_sload_ir,
bypass_register => round_bypass_register_ir,
dataout => round_in_reg
);
--Instantiate the saturate input Register
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
ELSE "0001" WHEN (saturate_clock = "1")
ELSE "0010" WHEN (saturate_clock = "2")
ELSE "0011" WHEN (saturate_clock = "3")
ELSE "0000" ;
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
ELSE "0001" WHEN (saturate_clear = "1")
ELSE "0010" WHEN (saturate_clear = "2")
ELSE "0011" WHEN (saturate_clear = "3")
ELSE "0000" ;
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
saturate_in <= saturate;
saturate_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturate_in,
clk => saturate_clk_ir,
aclr => saturate_aclr_ir,
sload => saturate_sload_ir,
bypass_register => saturate_bypass_register_ir,
dataout => saturate_in_reg
);
--Instantiate the roundchainout input Register
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
ELSE "0001" WHEN (roundchainout_clock = "1")
ELSE "0010" WHEN (roundchainout_clock = "2")
ELSE "0011" WHEN (roundchainout_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
ELSE "0001" WHEN (roundchainout_clear = "1")
ELSE "0010" WHEN (roundchainout_clear = "2")
ELSE "0011" WHEN (roundchainout_clear = "3")
ELSE "0000" ;
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
roundchainout_in <= roundchainout;
roundchainout_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_in,
clk => roundchainout_clk_ir,
aclr => roundchainout_aclr_ir,
sload => roundchainout_sload_ir,
bypass_register => roundchainout_bypass_register_ir,
dataout => roundchainout_in_reg
);
--Instantiate the saturatechainout input Register
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
ELSE "0001" WHEN (saturatechainout_clock = "1")
ELSE "0010" WHEN (saturatechainout_clock = "2")
ELSE "0011" WHEN (saturatechainout_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
ELSE "0001" WHEN (saturatechainout_clear = "1")
ELSE "0010" WHEN (saturatechainout_clear = "2")
ELSE "0011" WHEN (saturatechainout_clear = "3")
ELSE "0000" ;
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
saturatechainout_in <= saturatechainout;
saturatechainout_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in,
clk => saturatechainout_clk_ir,
aclr => saturatechainout_aclr_ir,
sload => saturatechainout_sload_ir,
bypass_register => saturatechainout_bypass_register_ir,
dataout => saturatechainout_in_reg
);
--Instantiate the First level adder interface and sign extension block
sign <= signa_in_reg OR signb_in_reg ;
fsa_interface : stratixiii_fsa_isse
GENERIC MAP (
chainin_width => chainin_width,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
operation_mode => operation_mode,
multa_signa_internally_grounded => multa_signa_internally_grounded,
multa_signb_internally_grounded => multa_signb_internally_grounded,
multb_signa_internally_grounded => multb_signa_internally_grounded,
multb_signb_internally_grounded => multb_signb_internally_grounded,
multc_signa_internally_grounded => multc_signa_internally_grounded,
multc_signb_internally_grounded => multc_signb_internally_grounded,
multd_signa_internally_grounded => multd_signa_internally_grounded,
multd_signb_internally_grounded => multd_signb_internally_grounded
)
PORT MAP (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
chainin => chainin,
signa => signa_in_reg,
signb => signb_in_reg,
dataa_out => dataa_fsa_in,
datab_out => datab_fsa_in,
datac_out => datac_fsa_in,
datad_out => datad_fsa_in,
chainin_out => chainin_coa_in,
operation => operation
);
--Instantiate First Stage Adder/Subtractor Unit0
fsaunit0 : stratixiii_first_stage_add_sub
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
fsa_mode => first_adder0_mode
)
PORT MAP (
dataa => dataa_fsa_in,
datab => datab_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa0
);
--Instantiate First Stage Adder/Subtractor Unit1
fsaunit1 : stratixiii_first_stage_add_sub
GENERIC MAP (
dataa_width => datac_width,
datab_width => datad_width,
fsa_mode => first_adder1_mode
)
PORT MAP (
dataa => datac_fsa_in,
datab => datad_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa1
);
--Instantiate the zeroloopback pipeline Register
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
ELSE "0000" ;
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
zeroloopback_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in_reg,
clk => zeroloopback_clk_pip,
aclr => zeroloopback_aclr_pip,
sload => zeroloopback_sload_pip,
bypass_register => zeroloopback_bypass_register_pip,
dataout => zeroloopback_pip_reg
);
--Instantiate the zeroacc pipeline Register
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
ELSE "0000" ;
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
zeroacc_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroacc_in_reg,
clk => zeroacc_clk_pip,
aclr => zeroacc_aclr_pip,
sload => zeroacc_sload_pip,
bypass_register => zeroacc_bypass_register_pip,
dataout => zeroacc_pip_reg
);
--Instantiate the signa pipeline Register
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
ELSE "0001" WHEN (signa_pipeline_clock = "1")
ELSE "0010" WHEN (signa_pipeline_clock = "2")
ELSE "0011" WHEN (signa_pipeline_clock = "3")
ELSE "0000" ;
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
ELSE "0001" WHEN (signa_pipeline_clear = "1")
ELSE "0010" WHEN (signa_pipeline_clear = "2")
ELSE "0011" WHEN (signa_pipeline_clear = "3")
ELSE "0000" ;
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
signa_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in_reg,
clk => signa_clk_pip,
aclr => signa_aclr_pip,
sload => signa_sload_pip,
bypass_register => signa_bypass_register_pip,
dataout => signa_pip_reg
);
--Instantiate the signb pipeline Register
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
ELSE "0001" WHEN (signb_pipeline_clock = "1")
ELSE "0010" WHEN (signb_pipeline_clock = "2")
ELSE "0011" WHEN (signb_pipeline_clock = "3")
ELSE "0000" ;
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
ELSE "0001" WHEN (signb_pipeline_clear = "1")
ELSE "0010" WHEN (signb_pipeline_clear = "2")
ELSE "0011" WHEN (signb_pipeline_clear = "3")
ELSE "0000" ;
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
signb_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in_reg,
clk => signb_clk_pip,
aclr => signb_aclr_pip,
sload => signb_sload_pip,
bypass_register => signb_bypass_register_pip,
dataout => signb_pip_reg
);
--Instantiate the rotate pipeline Register
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
ELSE "0000" ;
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
ELSE "0000" ;
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
rotate_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_in_reg,
clk => rotate_clk_pip,
aclr => rotate_aclr_pip,
sload => rotate_sload_pip,
bypass_register => rotate_bypass_register_pip,
dataout => rotate_pip_reg
);
--Instantiate the shiftright pipeline Register
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
ELSE "0000" ;
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
ELSE "0000" ;
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
shiftright_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_in_reg,
clk => shiftright_clk_pip,
aclr => shiftright_aclr_pip,
sload => shiftright_sload_pip,
bypass_register => shiftright_bypass_register_pip,
dataout => shiftright_pip_reg
);
--Instantiate the round pipeline Register
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
ELSE "0001" WHEN (round_pipeline_clock = "1")
ELSE "0010" WHEN (round_pipeline_clock = "2")
ELSE "0011" WHEN (round_pipeline_clock = "3")
ELSE "0000" ;
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
ELSE "0001" WHEN (round_pipeline_clear = "1")
ELSE "0010" WHEN (round_pipeline_clear = "2")
ELSE "0011" WHEN (round_pipeline_clear = "3")
ELSE "0000" ;
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
round_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => round_in_reg,
clk => round_clk_pip,
aclr => round_aclr_pip,
sload => round_sload_pip,
bypass_register => round_bypass_register_pip,
dataout => round_pip_reg
);
--Instantiate the saturate pipeline Register
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
ELSE "0000" ;
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
ELSE "0000" ;
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
saturate_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturate_in_reg,
clk => saturate_clk_pip,
aclr => saturate_aclr_pip,
sload => saturate_sload_pip,
bypass_register => saturate_bypass_register_pip,
dataout => saturate_pip_reg
);
--Instantiate the roundchainout pipeline Register
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
ELSE "0000" ;
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
roundchainout_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_in_reg,
clk => roundchainout_clk_pip,
aclr => roundchainout_aclr_pip,
sload => roundchainout_sload_pip,
bypass_register => roundchainout_bypass_register_pip,
dataout => roundchainout_pip_reg
);
--Instantiate the saturatechainout pipeline Register
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
ELSE "0000" ;
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
saturatechainout_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in_reg,
clk => saturatechainout_clk_pip,
aclr => saturatechainout_aclr_pip,
sload => saturatechainout_sload_pip,
bypass_register => saturatechainout_bypass_register_pip,
dataout => saturatechainout_pip_reg
);
-- Instantiate fsa0 dataout pipline register
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
ELSE "0001" WHEN (first_adder0_clock = "1")
ELSE "0010" WHEN (first_adder0_clock = "2")
ELSE "0011" WHEN (first_adder0_clock = "3")
ELSE "0000" ;
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
ELSE "0001" WHEN (first_adder0_clear = "1")
ELSE "0010" WHEN (first_adder0_clear = "2")
ELSE "0011" WHEN (first_adder0_clear = "3")
ELSE "0000" ;
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
fsa0_pipeline_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => fsa_pip_datain1,
clk => fsa0_clk_pip,
aclr => fsa0_aclr_pip,
sload => fsa0_sload_pip,
bypass_register => fsa0_bypass_register_pip,
dataout => fsa0_pip_reg
);
-- Instantiate fsa1 dataout pipline register
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
ELSE "0001" WHEN (first_adder1_clock = "1")
ELSE "0010" WHEN (first_adder1_clock = "2")
ELSE "0011" WHEN (first_adder1_clock = "3")
ELSE "0000" ;
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
ELSE "0001" WHEN (first_adder1_clear = "1")
ELSE "0010" WHEN (first_adder1_clear = "2")
ELSE "0011" WHEN (first_adder1_clear = "3")
ELSE "0000" ;
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
fsa1_pipeline_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => dataout_fsa1,
clk => fsa1_clk_pip,
aclr => fsa1_aclr_pip,
sload => fsa1_sload_pip,
bypass_register => fsa1_bypass_register_pip,
dataout => fsa1_pip_reg
);
--Instantiate the second level adder/accumulator block
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
ssa_unit : stratixiii_second_stage_add_accum
GENERIC MAP (
dataa_width => dataa_width + 1,
datab_width => datac_width + 1,
ssa_mode => acc_adder_operation
)
PORT MAP (
dataa => fsa0_pip_reg,
datab => fsa1_pip_reg,
accumin => ssa_accum_in,
sign => ssa_sign,
operation => operation,
dataout => ssa_dataout,
overflow => ssa_overflow
);
-- Instantiate round and saturation block
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
ELSE ssa_dataout ;
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
rs_block : stratixiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_mode,
saturate_mode => saturate_mode,
saturate_width => saturate_width,
round_width => round_width
)
PORT MAP (
datain => rs_datain,
round => round_pip_reg,
saturate => saturate_pip_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => rs_dataout,
saturationoverflow => rs_saturation_overflow
);
--Instantiate the zeroloopback output Register
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
ELSE "0000" ;
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
zeroloopback_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_pip_reg,
clk => zeroloopback_clk_or,
aclr => zeroloopback_aclr_or,
sload => zeroloopback_sload_or,
bypass_register => zeroloopback_bypass_register_or,
dataout => zeroloopback_out_reg
);
--Instantiate the zerochainout output Register
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
ELSE "0001" WHEN (zerochainout_output_clock = "1")
ELSE "0010" WHEN (zerochainout_output_clock = "2")
ELSE "0011" WHEN (zerochainout_output_clock = "3")
ELSE "0000" ;
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
ELSE "0001" WHEN (zerochainout_output_clear = "1")
ELSE "0010" WHEN (zerochainout_output_clear = "2")
ELSE "0011" WHEN (zerochainout_output_clear = "3")
ELSE "0000" ;
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
zerochainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => zerochainout,
clk => zerochainout_clk_or,
aclr => zerochainout_aclr_or,
sload => zerochainout_sload_or,
bypass_register => zerochainout_bypass_register_or,
dataout => zerochainout_out_reg
);
-- Instantiate Round_Saturate dataout output register
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
ELSE "0001" WHEN (second_adder_clock = "1")
ELSE "0010" WHEN (second_adder_clock = "2")
ELSE "0011" WHEN (second_adder_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
ELSE "0001" WHEN (second_adder_clear = "1")
ELSE "0010" WHEN (second_adder_clear = "2")
ELSE "0011" WHEN (second_adder_clear = "3")
ELSE "0000" ;
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_aclrval_or_o;
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_clkval_or_o;
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_bypass_register_or_o;
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
rs_dataout_output_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => rs_dataout_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_dataout_out_reg
);
-- Instantiate Round_Saturate saturation_overflow output register
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
rs_saturation_overflow_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_saturation_overflow_out_reg
);
--Instantiate the rotate output Register
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
ELSE "0001" WHEN (rotate_output_clock = "1")
ELSE "0010" WHEN (rotate_output_clock = "2")
ELSE "0011" WHEN (rotate_output_clock = "3")
ELSE "0000" ;
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
ELSE "0001" WHEN (rotate_output_clear = "1")
ELSE "0010" WHEN (rotate_output_clear = "2")
ELSE "0011" WHEN (rotate_output_clear = "3")
ELSE "0000" ;
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
rotate_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_pip_reg,
clk => rotate_clk_or,
aclr => rotate_aclr_or,
sload => rotate_sload_or,
bypass_register => rotate_bypass_register_or,
dataout => rotate_out_reg
);
--Instantiate the shiftright output Register
shiftright_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_pip_reg,
clk => shiftright_clk_or,
aclr => shiftright_aclr_or,
sload => shiftright_sload_or,
bypass_register => shiftright_bypass_register_or,
dataout => shiftright_out_reg
);
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
ELSE "0001" WHEN (shiftright_output_clock = "1")
ELSE "0010" WHEN (shiftright_output_clock = "2")
ELSE "0011" WHEN (shiftright_output_clock = "3")
ELSE "0000" ;
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
ELSE "0001" WHEN (shiftright_output_clear = "1")
ELSE "0010" WHEN (shiftright_output_clear = "2")
ELSE "0011" WHEN (shiftright_output_clear = "3")
ELSE "0000" ;
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
--Instantiate the roundchainout output Register
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
ELSE "0001" WHEN (roundchainout_output_clock = "1")
ELSE "0010" WHEN (roundchainout_output_clock = "2")
ELSE "0011" WHEN (roundchainout_output_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
ELSE "0001" WHEN (roundchainout_output_clear = "1")
ELSE "0010" WHEN (roundchainout_output_clear = "2")
ELSE "0011" WHEN (roundchainout_output_clear = "3")
ELSE "0000" ;
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
roundchainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_pip_reg,
clk => roundchainout_clk_or,
aclr => roundchainout_aclr_or,
sload => roundchainout_sload_or,
bypass_register => roundchainout_bypass_register_or,
dataout => roundchainout_out_reg
);
--Instantiate the saturatechainout output Register
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
ELSE "0000" ;
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
saturatechainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_pip_reg,
clk => saturatechainout_clk_or,
aclr => saturatechainout_aclr_or,
sload => saturatechainout_sload_or,
bypass_register => saturatechainout_bypass_register_or,
dataout => saturatechainout_out_reg
);
--Instantiate the Carry chainout Adder
chainout_adder : stratixiii_carry_chain_adder
PORT MAP (
dataa => rs_dataout_out_reg,
datab => chainin_coa_in,
dataout => coa_dataout
);
--Instantiate the carry chainout adder RS Block
coa_rs_block : stratixiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_chain_out_mode,
saturate_mode => saturate_chain_out_mode,
saturate_width => saturate_chain_out_width,
round_width => round_chain_out_width
)
PORT MAP (
datain => coa_dataout,
round => roundchainout_out_reg,
saturate => saturatechainout_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => coa_rs_dataout,
saturationoverflow => coa_rs_saturation_overflow
);
--Instantiate the rs_saturation_overflow output register (after COA)
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
coa_rs_saturation_overflow_register : stratixiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_out_reg,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => '1',
dataout => coa_rs_saturation_overflow_out_reg
);
--Instantiate the rs_saturationchainout_overflow output register
coa_rs_saturationchainout_overflow_register : stratixiii_mac_bit_register
PORT MAP (
datain => coa_rs_saturation_overflow,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_saturationchainout_overflow_out_reg
);
-- Instantiate the coa_rs_dataout output register
coa_rs_dataout_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => coa_rs_dataout,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_dataout_out_reg
);
--Instantiate the shift/Rotate Unit
shift_rot_unit : stratixiii_rotate_shift_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
datain => rs_dataout_out_reg,
rotate => rotate_out_reg,
shiftright => shiftright_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
dataout => dataout_shift_rot
);
--Assign the dataout depENDing on the mode of operation
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE dataout_shift_rot when (operation_mode = "shift")
ELSE rs_dataout_out_reg;
--Assign the loopbackout for loopback mode
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
ELSE (others => '0');
--Assign the saturation overflow output
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
--Assign the saturationchainout overflow output
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
ELSE dataout_tmp;
loopbackout <= loopbackout_tmp(35 downto 18);
overflow <= saturation_overflow_tmp;
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : stratixiii_io_pad
-- Description : Simulation model for stratixiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiii_io_pad IS
GENERIC (
lpm_type : string := "stratixiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END stratixiii_io_pad;
ARCHITECTURE arch OF stratixiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the StratixII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixiii_mn_cntr;
ARCHITECTURE behave of stratixiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the StratixII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END stratixiii_scale_cntr;
ARCHITECTURE behave of stratixiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--BEGIN MF PORTING DELETE
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end stratixiii_pll_reg;
ARCHITECTURE behave of stratixiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--END MF PORTING DELETE
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_pll
--
-- Description : Timing simulation model for the StratixII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_pllpack.all;
USE work.stratixiii_mn_cntr;
USE work.stratixiii_scale_cntr;
USE work.stratixiii_dffe;
USE work.stratixiii_pll_reg;
-- New Features : The list below outlines key new features in STRATIXIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY stratixiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "StratixIII";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END stratixiii_pll;
ARCHITECTURE vital_pll of stratixiii_pll is
function get_vco_min_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_min * 2;
else
return vco_min;
end if;
end;
function get_vco_max_no_division(i_vco_post_scale : INTEGER) return INTEGER is
begin
if (i_vco_post_scale = 1) then
return vco_max * 2;
else
return vco_max;
end if;
end;
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
constant VCO_MIN_NO_DIVISION : integer := get_vco_min_no_division(vco_post_scale);
constant VCO_MAX_NO_DIVISION : integer := get_vco_max_no_division(vco_post_scale);
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min;
signal i_vco_max : integer := vco_max;
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 9);
signal clk_num : str_array(0 to 9);
-- old values
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 9);
-- hold registers
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 9);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
signal i_clk9_counter : integer := 9;
signal i_clk8_counter : integer := 8;
signal i_clk7_counter : integer := 7;
signal i_clk6_counter : integer := 6;
signal i_clk5_counter : integer := 5;
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 9);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 10;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 9);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal clk6_tmp : std_logic;
signal clk7_tmp : std_logic;
signal clk8_tmp : std_logic;
signal clk9_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_c6 : std_logic;
signal inclk_c7 : std_logic;
signal inclk_c8 : std_logic;
signal inclk_c9 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 9);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT stratixiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1 or
c5_test_source /= -1 or c6_test_source /= -1 or
c7_test_source /= -1 or c8_test_source /= -1 or
c9_test_source /= -1)
else
false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : stratixiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if (areset_ipd = '0') then
if ((inclk0_period > inclk1_period) and (inclk1_period /= 0 ps)) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
elsif (inclk0_period /= 0 ps) then
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : stratixiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : stratixiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : stratixiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : stratixiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : stratixiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : stratixiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= refclk when c5_test_source = 1 else
fbclk when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : stratixiii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c6 <= refclk when c6_test_source = 1 else
fbclk when c6_test_source = 0 else
c_clk(5) when c6_use_casc_in = "on" else
inclk_c_from_vco(6);
c6 : stratixiii_scale_cntr
port map (
clk => inclk_c6,
reset => areset_ena_sig,
cout => c_clk(6),
initial => c_initial_val(6),
high => c_high_val(6),
low => c_low_val(6),
mode => c_mode_val(6),
ph_tap => c_ph_val(6));
inclk_c7 <= refclk when c7_test_source = 1 else
fbclk when c7_test_source = 0 else
c_clk(6) when c7_use_casc_in = "on" else
inclk_c_from_vco(7);
c7 : stratixiii_scale_cntr
port map (
clk => inclk_c7,
reset => areset_ena_sig,
cout => c_clk(7),
initial => c_initial_val(7),
high => c_high_val(7),
low => c_low_val(7),
mode => c_mode_val(7),
ph_tap => c_ph_val(7));
inclk_c8 <= refclk when c8_test_source = 1 else
fbclk when c8_test_source = 0 else
c_clk(7) when c8_use_casc_in = "on" else
inclk_c_from_vco(8);
c8 : stratixiii_scale_cntr
port map (
clk => inclk_c8,
reset => areset_ena_sig,
cout => c_clk(8),
initial => c_initial_val(8),
high => c_high_val(8),
low => c_low_val(8),
mode => c_mode_val(8),
ph_tap => c_ph_val(8));
inclk_c9 <= refclk when c9_test_source = 1 else
fbclk when c9_test_source = 0 else
c_clk(8) when c9_use_casc_in = "on" else
inclk_c_from_vco(9);
c9 : stratixiii_scale_cntr
port map (
clk => inclk_c9,
reset => areset_ena_sig,
cout => c_clk(9),
initial => c_initial_val(9),
high => c_high_val(9),
low => c_low_val(9),
mode => c_mode_val(9),
ph_tap => c_ph_val(9));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 9);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
variable c6_rising_edge_transfer_done : boolean := false;
variable c7_rising_edge_transfer_done : boolean := false;
variable c8_rising_edge_transfer_done : boolean := false;
variable c9_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_clk6_mult_by : integer := 1;
variable i_clk6_div_by : integer := 1;
variable i_clk7_mult_by : integer := 1;
variable i_clk7_div_by : integer := 1;
variable i_clk8_mult_by : integer := 1;
variable i_clk8_div_by : integer := 1;
variable i_clk9_mult_by : integer := 1;
variable i_clk9_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 9);
variable i_c_low : int_array(0 to 9);
variable i_c_initial : int_array(0 to 9);
variable i_c_ph : int_array(0 to 9);
variable i_c_mode : str_array(0 to 9);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable clk5_cntr : string(1 to 6) := " c5";
variable clk6_cntr : string(1 to 6) := " c6";
variable clk7_cntr : string(1 to 6) := " c7";
variable clk8_cntr : string(1 to 6) := " c8";
variable clk9_cntr : string(1 to 6) := " c9";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk9_cntr := " c9";
clk8_cntr := " c8";
clk7_cntr := " c7";
clk6_cntr := " c6";
clk5_cntr := " c5";
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk9_cntr := extract_cntr_string(clk9_counter);
clk8_cntr := extract_cntr_string(clk8_counter);
clk7_cntr := extract_cntr_string(clk7_counter);
clk6_cntr := extract_cntr_string(clk6_counter);
clk5_cntr := extract_cntr_string(clk5_counter);
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(9) <= output_cntr_num(clk9_counter);
clk_num(8) <= output_cntr_num(clk8_counter);
clk_num(7) <= output_cntr_num(clk7_counter);
clk_num(6) <= output_cntr_num(clk6_counter);
clk_num(5) <= output_cntr_num(clk5_counter);
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
i_clk6_counter <= extract_cntr_index(clk6_cntr);
i_clk7_counter <= extract_cntr_index(clk7_cntr);
i_clk8_counter <= extract_cntr_index(clk8_cntr);
i_clk9_counter <= extract_cntr_index(clk9_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
i_clk5_div_by,i_clk6_div_by,
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
clk5_counter,clk6_counter,
clk7_counter,clk8_counter,clk9_counter,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_ph(6) := c6_ph;
i_c_ph(7) := c7_ph;
i_c_ph(8) := c8_ph;
i_c_ph(9) := c9_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_high(6) := c6_high;
i_c_high(7) := c7_high;
i_c_high(8) := c8_high;
i_c_high(9) := c9_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_low(6) := c6_low;
i_c_low(7) := c7_low;
i_c_low(8) := c8_low;
i_c_low(9) := c9_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_initial(6) := c6_initial;
i_c_initial(7) := c7_initial;
i_c_initial(8) := c8_initial;
i_c_initial(9) := c9_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
i_c_mode(6) := translate_string(c6_mode);
i_c_mode(7) := translate_string(c7_mode);
i_c_mode(8) := translate_string(c8_mode);
i_c_mode(9) := translate_string(c9_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 9 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
if (pll_type = "fast" OR (pll_type = "left_right")) then
scan_chain_length := FAST_SCAN_CHAIN;
else
scan_chain_length := GPP_SCAN_CHAIN;
end if;
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
num_output_cntrs <= 7;
else
num_output_cntrs <= 10;
end if;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
c6_rising_edge_transfer_done := false;
c7_rising_edge_transfer_done := false;
c8_rising_edge_transfer_done := false;
c9_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= VCO_MAX_NO_DIVISION/2;
i_vco_min <= VCO_MIN_NO_DIVISION/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(18) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(36) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(6) <= c_high_val_tmp(6);
c_mode_val(6) <= c_mode_val_tmp(6);
c6_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(7) <= c_high_val_tmp(7);
c_mode_val(7) <= c_mode_val_tmp(7);
c7_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(8) <= c_high_val_tmp(8);
c_mode_val(8) <= c_mode_val_tmp(8);
c8_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(9) <= c_high_val_tmp(9);
c_mode_val(9) <= c_mode_val_tmp(9);
c9_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
c_low_val(6) <= c_low_val_tmp(6);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
c_low_val(7) <= c_low_val_tmp(7);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
c_low_val(8) <= c_low_val_tmp(8);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
c_low_val(9) <= c_low_val_tmp(9);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
IF (phasecounterselect_ipd = "0000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "0001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after 1 ps;
end loop;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
locked_tmp := '0';
end if;
pll_is_in_reset := false;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk6_tmp <= c_clk(i_clk6_counter);
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk7_tmp <= c_clk(i_clk7_counter);
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk8_tmp <= c_clk(i_clk8_counter);
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk9_tmp <= c_clk(i_clk9_counter);
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_asmiblock
--
-- Description : Stratix III ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_asmiblock is
generic (
lpm_type : string := "stratixiii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end stratixiii_asmiblock;
architecture architecture_asmiblock of stratixiii_asmiblock is
begin
end architecture_asmiblock; -- end of stratixiii_asmiblock
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END stratixiii_lvds_reg;
ARCHITECTURE vital_stratixiii_lvds_reg of stratixiii_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_stratixiii_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF stratixiii_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_rx_fifo_sync_ram;
ENTITY stratixiii_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of stratixiii_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT stratixiii_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixiii_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_reg;
ENTITY stratixiii_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END stratixiii_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF stratixiii_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT stratixiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : stratixiii_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : stratixiii_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_deser
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF stratixiii_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF stratixiii_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_pclk_divider
--
-- Description : Simulation model for a clock divider
-- output clock is divided by value specified
-- in the parameter clk_divide_by
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY stratixiii_pclk_divider IS
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END stratixiii_pclk_divider;
ARCHITECTURE arch OF stratixiii_pclk_divider IS
SIGNAL lloaden_tmp : std_logic := '0';
SIGNAL clkout_tmp : std_logic := '0';
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
BEGIN
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
lloaden <= lloaden_tmp;
PROCESS(clkin)
variable count : std_logic := '0';
variable start : std_logic := '0';
variable prev_load : std_logic := '0';
BEGIN
IF(clkin = '1') THEN
count := '1';
END IF;
if( count = '1') then
IF (cnt < clk_divide_by) THEN
clkout_tmp <= '0';
cnt <= cnt + "00001";
ELSE
IF (cnt = (2 * clk_divide_by - 1)) THEN
cnt <= "00000";
ELSE
clkout_tmp <= '1';
cnt <= cnt + "00001";
END IF;
END IF;
end if;
END PROCESS;
process( clkin, cnt )
begin
if( cnt =( 2*clk_divide_by -2) )then
lloaden_tmp <= '1';
else
if(cnt = 0)then
lloaden_tmp <= '0';
end if;
end if;
end process;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_select_ini_phase_dpaclk
--
-- Description : Simulation model for selecting the initial phase of the dpa clock
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiii_select_ini_phase_dpaclk IS
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
loadenout : OUT STD_LOGIC
);
END stratixiii_select_ini_phase_dpaclk;
ARCHITECTURE trans OF stratixiii_select_ini_phase_dpaclk IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL loaden0_tmp : STD_LOGIC;
SIGNAL loaden1_tmp : STD_LOGIC;
SIGNAL loaden2_tmp : STD_LOGIC;
SIGNAL loaden3_tmp : STD_LOGIC;
SIGNAL loaden4_tmp : STD_LOGIC;
SIGNAL loaden5_tmp : STD_LOGIC;
SIGNAL loaden6_tmp : STD_LOGIC;
SIGNAL loaden7_tmp : STD_LOGIC;
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL loadenout_tmp : STD_LOGIC;
BEGIN
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
clk2_tmp when (initial_phase_select = 2) else
clk3_tmp when (initial_phase_select = 3) else
clk4_tmp when (initial_phase_select = 4) else
clk5_tmp when (initial_phase_select = 5) else
clk6_tmp when (initial_phase_select = 6) else
clk7_tmp when (initial_phase_select = 7) else
clk0_tmp;
clkout <= clkout_tmp when enable = '1' else clkin;
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
loaden2_tmp when (initial_phase_select = 2) else
loaden3_tmp when (initial_phase_select = 3) else
loaden4_tmp when (initial_phase_select = 4) else
loaden5_tmp when (initial_phase_select = 5) else
loaden6_tmp when (initial_phase_select = 6) else
loaden7_tmp when (initial_phase_select = 7) else
loaden0_tmp;
loadenout <= loadenout_tmp when enable = '1' else loaden;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (loaden)
BEGIN
loaden0_tmp <= clkin;
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_dpa_retime_block
--
-- Description : Simulation model for generating the retimed clock,data and loaden.
-- Each of the signals has 8 different phase shifted versions.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiii_dpa_retime_block IS
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END stratixiii_dpa_retime_block;
ARCHITECTURE trans OF stratixiii_dpa_retime_block IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL lock_tmp : STD_LOGIC := '0';
BEGIN
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
lock_tmp <= '1';
ELSE
lock_tmp <= '0';
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (datain)
BEGIN
data0_tmp <= datain;
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_dpa_block
--
-- Description : Simulation model for selecting the retimed data, clock and loaden
-- depending on the PPM varaiation and direction of shift.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.stratixiii_dpa_retime_block;
ENTITY stratixiii_dpa_block IS
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END stratixiii_dpa_block;
ARCHITECTURE trans OF stratixiii_dpa_block IS
COMPONENT stratixiii_dpa_retime_block
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL dataout_tmp : STD_LOGIC;
SIGNAL counter_reset_value : INTEGER ;
SIGNAL count_value : INTEGER ;
SIGNAL i : INTEGER := 0;
SIGNAL dpalock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
dpalock <= dpalock_xhdl0;
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
data_clock_retime : stratixiii_dpa_retime_block
PORT MAP (
clkin => clkin,
datain => datain,
reset => dpareset,
clk0 => clk0_tmp,
clk1 => clk1_tmp,
clk2 => clk2_tmp,
clk3 => clk3_tmp,
clk4 => clk4_tmp,
clk5 => clk5_tmp,
clk6 => clk6_tmp,
clk7 => clk7_tmp,
data0 => data0_tmp,
data1 => data1_tmp,
data2 => data2_tmp,
data3 => data3_tmp,
data4 => data4_tmp,
data5 => data5_tmp,
data6 => data6_tmp,
data7 => data7_tmp,
lock => dpalock_xhdl0
);
PROCESS (clkin, dpareset, dpahold)
variable initial : boolean := true;
variable ppm_tmp : integer;
BEGIN
if(initial) then
if(net_ppm_variation = 0) then
ppm_tmp := 1;
else
ppm_tmp := net_ppm_variation;
end if;
if(net_ppm_variation = 0) then
counter_reset_value <= 1;
count_value <= 1;
initial := false;
else
counter_reset_value <= 1000000 / (ppm_tmp * 8);
count_value <= 1000000 / (ppm_tmp * 8);
initial := false;
end if;
end if;
IF (clkin'EVENT AND clkin = '1') THEN
IF(net_ppm_variation = 0) THEN
select_xhdl1 <= "000";
ELSE
IF (dpareset = '1') THEN
i <= 0;
select_xhdl1 <= "000";
ELSE
IF (dpahold = '0') THEN
IF (i < count_value) THEN
i <= i + 1;
ELSE
select_xhdl1 <= select_xhdl1 + "001";
i <= 0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
BEGIN
if (select_xhdl1 = "000") then
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
elsif (select_xhdl1 = "001") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
else
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
end if;
elsif (select_xhdl1 = "010") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
else
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
end if;
elsif (select_xhdl1 = "011")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
else
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
end if;
elsif (select_xhdl1 = "100")then
clkout_tmp <= clk4_tmp;
dataout_tmp <= data4_tmp;
elsif (select_xhdl1 = "101")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
else
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
end if;
elsif (select_xhdl1 = "110") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
else
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
end if;
elsif (select_xhdl1 = "111")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
else
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
end if;
else
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
end if;
END PROCESS;
END trans;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_LVDS_RECEIVER
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) stratixiii_lvds_rx_fifo
-- 2) stratixiii_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) stratixiii_lvds_rx_parallel_reg
-- 5) stratixiii_pclk_divider
-- 6) stratixiii_select_ini_phase_dpaclk
-- 7) stratixiii_dpa_block
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_rx_bitslip;
USE work.stratixiii_lvds_rx_fifo;
USE work.stratixiii_lvds_rx_deser;
USE work.stratixiii_lvds_rx_parallel_reg;
USE work.stratixiii_lvds_reg;
USE work.stratixiii_pclk_divider;
USE work.stratixiii_select_ini_phase_dpaclk;
USE work.stratixiii_dpa_block;
ENTITY stratixiii_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := -1;
x_on_bitslip : string := "on";
lpm_type : string := "stratixiii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF stratixiii_lvds_receiver IS
COMPONENT stratixiii_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_pclk_divider
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END COMPONENT;
COMPONENT stratixiii_select_ini_phase_dpaclk
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
loadenout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_dpa_block
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
signal ini_dpa_clk : std_logic;
signal ini_dpa_load : std_logic;
signal ini_phase_select_enable : std_logic;
signal dpa_clk_shift : std_logic;
signal dpa_data_shift : std_logic;
signal lloaden : std_logic;
signal lock_tmp : std_logic;
signal divfwdclk_tmp : std_logic;
signal dpa_is_locked : std_logic;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
signal clk0_tmp : std_logic;
signal clk0_tmp_neg : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
process (clk0_ipd, dpareset_ipd,lock_tmp )
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
if(lock_tmp = '1') then
reset_fifo <= '0';
else
reset_fifo <= '1';
end if;
end process;
xhdl_12 <= devclrn OR devpor;
-- input register in non-DPA mode for sampling incoming data
in_reg : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_tmp <= clk0_ipd;
clk0_tmp_neg <= not clk0_ipd;
neg_reg : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp_neg,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg_neg
);
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
-- dpa initial phase select
ini_clk_phase_select: stratixiii_select_ini_phase_dpaclk
GENERIC MAP(
initial_phase_select => dpa_initial_phase_value
)
PORT MAP(
clkin => clk0_ipd,
loaden => enable0_ipd,
enable => ini_phase_select_enable,
loadenout=>ini_dpa_load,
clkout => ini_dpa_clk
);
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
-- DPA circuitary
dpareg0 : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : stratixiii_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
dpa_circuit: stratixiii_dpa_block
GENERIC MAP(
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
enable_soft_cdr_mode => enable_soft_cdr
)
PORT MAP(
clkin => ini_dpa_clk,
dpareset => dpareset_ipd,
dpahold => dpahold_ipd,
datain => dpareg1_out,
clkout => dpa_clk_shift,
dataout => dpa_data_shift,
dpalock => lock_tmp
);
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
-- PCLK and lloaden generation
clk_forward: stratixiii_pclk_divider
GENERIC MAP (
clk_divide_by => channel_width )
PORT MAP(
clkin => dpa_clk,
lloaden => lloaden,
clkout => divfwdclk_tmp
);
-- FIFO
s_fifo : stratixiii_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => dpa_clk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
-- Bit Slip
s_bslip : stratixiii_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
-- DESERIALISER
rxload_reg : stratixiii_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
s_deser : stratixiii_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : stratixiii_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
dpa_is_locked <= gnd;
dpaclkout <= dpa_clk_shift;
postdpaserialdataout <= dpa_data_shift ;
serialdataout <= datain_ipd;
divfwdclk <= divfwdclk_tmp ;
END vital_arm_lvds_receiver;
----------------------------------------------------------------------------------
--Module Name: stratixiii_pseudo_diff_out --
--Description: Simulation model for Stratix III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratixiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiii_pseudo_diff_out;
ARCHITECTURE arch OF stratixiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_logic
--
-- Description : STRATIXIII Bias Block's Logic Block
-- VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_logic IS
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_logic : ENTITY IS TRUE;
end stratixiii_bias_logic;
ARCHITECTURE vital_bias_logic of stratixiii_bias_logic IS
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
signal clk_ipd : std_logic := '0';
signal shiftnld_ipd : std_logic := '0';
signal captnupdt_ipd : std_logic := '0';
begin
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
end block;
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
begin
select_tmp := captnupdt_ipd & shiftnld_ipd;
case select_tmp IS
when "10"|"11" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '1';
update <= '0';
when "01" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '0';
update <= '0';
when "00" =>
mainclk <= clk_ipd;
updateclk <= '0';
capture <= '0';
update <= '1';
when others =>
mainclk <= '0';
updateclk <= '0';
capture <= '0';
update <= '0';
end case;
end process;
end vital_bias_logic;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_generator
--
-- Description : STRATIXIII Bias Generator VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_generator IS
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_generator : ENTITY IS TRUE;
end stratixiii_bias_generator;
ARCHITECTURE vital_bias_generator of stratixiii_bias_generator IS
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
CONSTANT TOTAL_REG : integer := 252;
signal din_ipd : std_logic := '0';
signal mainclk_ipd : std_logic := '0';
signal updateclk_ipd : std_logic := '0';
signal update_ipd : std_logic := '0';
signal capture_ipd : std_logic := '0';
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal dout_tmp : std_logic := '0';
signal i : integer := 0;
begin
WireDelay : block
begin
VitalWireDelay (din_ipd, din, tipd_din);
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
VitalWireDelay (update_ipd, update, tipd_update);
VitalWireDelay (capture_ipd, capture, tipd_capture);
end block;
process (mainclk_ipd)
begin
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
if ((capture_ipd = '0') AND (update_ipd = '1')) then
for i in 0 to (TOTAL_REG - 1)
loop
generator_reg(i) <= update_reg(i);
end loop;
end if;
end if;
end process;
process (updateclk_ipd)
begin
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
dout_tmp <= update_reg(TOTAL_REG - 1);
if ((capture_ipd = '0') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= update_reg(i - 1);
end loop;
update_reg(0) <= din_ipd;
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= generator_reg(i);
end loop;
end if;
end if;
end process;
dout <= dout_tmp;
end vital_bias_generator;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_block
--
-- Description : STRATIXIII Bias Block VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_block IS
GENERIC (
lpm_type : string := "stratixiii_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_block : ENTITY IS TRUE;
end stratixiii_bias_block;
ARCHITECTURE vital_bias_block of stratixiii_bias_block IS
COMPONENT stratixiii_bias_logic
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
end COMPONENT;
COMPONENT stratixiii_bias_generator
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
end COMPONENT;
signal mainclk_wire : std_logic := '0';
signal updateclk_wire : std_logic := '0';
signal capture_wire : std_logic := '0';
signal update_wire : std_logic := '0';
begin
logic_block : stratixiii_bias_logic
PORT MAP (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire
);
bias_generator : stratixiii_bias_generator
PORT MAP (
din => din,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire,
dout => dout
);
end vital_bias_block;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_tsdblock
--
-- Description : Stratix III TSDBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_tsdblock is
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "stratixiii_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
end stratixiii_tsdblock;
architecture architecture_tsdblock of stratixiii_tsdblock is
begin
end architecture_tsdblock; -- end of stratixiii_tsdblock
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF cmdfifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF cmdfifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: cmdfifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.cmdfifo_pkg.ALL;
ENTITY cmdfifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF cmdfifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:cmdfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_2048_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_2048_1;
ARCHITECTURE bram_2048_1_arch OF bram_2048_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_2048_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_2048_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_2048_1_arch : ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_2048_1_arch: ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_2048_1.mi" &
"f,C_INIT_FILE=bram_2048_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.9373 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_2048_1.mif",
C_INIT_FILE => "bram_2048_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.9373 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_2048_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_2048_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_2048_1;
ARCHITECTURE bram_2048_1_arch OF bram_2048_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_2048_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_2048_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_2048_1_arch : ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_2048_1_arch: ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_2048_1.mi" &
"f,C_INIT_FILE=bram_2048_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.9373 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_2048_1.mif",
C_INIT_FILE => "bram_2048_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.9373 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_2048_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_2048_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_2048_1;
ARCHITECTURE bram_2048_1_arch OF bram_2048_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_2048_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_2048_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_2048_1_arch : ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_2048_1_arch: ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_2048_1.mi" &
"f,C_INIT_FILE=bram_2048_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.9373 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_2048_1.mif",
C_INIT_FILE => "bram_2048_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.9373 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_2048_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_5;
USE blk_mem_gen_v8_3_5.blk_mem_gen_v8_3_5;
ENTITY bram_2048_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0)
);
END bram_2048_1;
ARCHITECTURE bram_2048_1_arch OF bram_2048_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF bram_2048_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_5 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_5;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF bram_2048_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_5,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF bram_2048_1_arch : ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF bram_2048_1_arch: ARCHITECTURE IS "bram_2048_1,blk_mem_gen_v8_3_5,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=bram_2048_1.mi" &
"f,C_INIT_FILE=bram_2048_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=20,C_READ_WIDTH_A=20,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=20,C_READ_WIDTH_B=20,C_WRITE_DE" &
"PTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE" &
"_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.9373 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_5
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "bram_2048_1.mif",
C_INIT_FILE => "bram_2048_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 20,
C_READ_WIDTH_A => 20,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 20,
C_READ_WIDTH_B => 20,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 1,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "1",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.9373 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 20)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END bram_2048_1_arch;
|
entity tb_issue3 is
end tb_issue3;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_issue3 is
signal i : integer := 0;
signal o : signed (3 downto 0);
begin
dut: entity work.issue3
port map (i, o);
process
begin
i <= 0;
wait for 1 ns;
assert o = "0010" severity failure;
i <= 1;
wait for 1 ns;
assert o = "0011" severity failure;
i <= -1;
wait for 1 ns;
assert o = "0001" severity failure;
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
-- FILE: DataPath
-- DESC: Datapath of DLX
--
-- Author:
-- Create: 2015-05-24
-- Update: 2015-10-03
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DataPath is
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
IMME_SIZE : integer := C_SYS_IMME_SIZE;
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Datapath Contrl Word
CALU_SIZE : integer := C_CTR_CALU_SIZE;
DRCW_SIZE : integer := C_CTR_DRCW_SIZE
);
port (
clk : in std_logic;
rst : in std_logic;
istr_addr : out std_logic_vector(ADDR_SIZE-1 downto 0);
istr_val : in std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
ir_out : out std_logic_vector(ISTR_SIZE-1 downto 0):=(others=>'0');
pc_out : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
reg_a_out : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
ld_a_out : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
data_addr : out std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
data_i_val : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
data_o_val : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
cw : in std_logic_vector(CWRD_SIZE-1 downto 0):=(others=>'0');
dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0):=(others=>'0');
calu : in std_logic_vector(CALU_SIZE-1 downto 0):=(others=>'0');
sig_bal : out std_logic:='0';
sig_bpw : in std_logic:='0';
sig_jral : out std_logic:='0';
sig_ral : out std_logic:='0';
sig_mul : out std_logic:='0';
sig_div : out std_logic:='0';
sig_sqrt : out std_logic:='0'
);
end DataPath;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture data_path_arch of DataPath is
component Mux is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
sel: in std_logic;
din0: in std_logic_vector(DATA_SIZE-1 downto 0);
din1: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Mux4 is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
sel: in std_logic_vector(1 downto 0);
din0: in std_logic_vector(DATA_SIZE-1 downto 0);
din1: in std_logic_vector(DATA_SIZE-1 downto 0);
din2: in std_logic_vector(DATA_SIZE-1 downto 0);
din3: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Reg is
generic(
DATA_SIZE: integer := C_SYS_DATA_SIZE
);
port(
rst: in std_logic;
en : in std_logic;
clk: in std_logic;
din: in std_logic_vector(DATA_SIZE-1 downto 0);
dout: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
cin: in std_logic;
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout: out std_logic
);
end component;
component RegisterFile is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_NUM : integer := C_REG_NUM
);
port(
clk : in std_logic; -- clock
rst : in std_logic; -- reset
en : in std_logic; -- enable
rd1_en : in std_logic; -- read port 1
rd2_en : in std_logic; -- read port 2
wr_en : in std_logic; -- write port
link_en : in std_logic;
rd1_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of read port 1
rd2_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of read port 2
wr_addr : in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of write port
d_out1 : out std_logic_vector(DATA_SIZE-1 downto 0); -- data out 1 bus
d_out2 : out std_logic_vector(DATA_SIZE-1 downto 0); -- data out 2 bus
d_in : in std_logic_vector(DATA_SIZE-1 downto 0); -- data in bus
d_link : in std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
component Alu is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
f : in std_logic_vector(4 downto 0); -- Function
a : in std_logic_vector(DATA_SIZE-1 downto 0); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0) -- Data Out
);
end component;
component Mul is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE/2;
STAGE : integer := C_MUL_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic;
lock: in std_logic;
sign: in std_logic;
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE*2-1 downto 0):=(others=>'0') -- Data Out
);
end component;
component Div is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
DIV_STAGE : integer := C_DIV_STAGE;
SQRT_STAGE : integer := C_SQRT_STAGE
);
port (
rst: in std_logic;
clk: in std_logic;
en: in std_logic:='0';
lock: in std_logic:='0';
sign: in std_logic:='0';
func: in std_logic:='0';
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0') -- Data Out
);
end component;
component Extender is
generic(
SRC_SIZE : integer := 1;
DEST_SIZE: integer := C_SYS_DATA_SIZE
);
port(
s : std_logic := '0';
i : in std_logic_vector(SRC_SIZE-1 downto 0);
o : out std_logic_vector(DEST_SIZE-1 downto 0)
);
end component;
component FwdMux1 is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_ADDR_SIZE : integer := MyLog2Ceil(C_REG_NUM)
);
port(
reg_c : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_f : in std_logic_vector(DATA_SIZE-1 downto 0);
addr_c : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_f : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
valid_f : in std_logic;
dirty_f : in std_logic;
output : out std_logic_vector(DATA_SIZE-1 downto 0);
match_dirty_f: out std_logic
);
end component;
component FwdMux2 is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_ADDR_SIZE : integer := MyLog2Ceil(C_REG_NUM)
);
port(
reg_c : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_f : in std_logic_vector(DATA_SIZE-1 downto 0);
reg_ff : in std_logic_vector(DATA_SIZE-1 downto 0);
addr_c : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_f : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
addr_ff : in std_logic_vector(REG_ADDR_SIZE-1 downto 0);
valid_f : in std_logic;
valid_ff: in std_logic;
dirty_f : in std_logic;
dirty_ff: in std_logic;
en : in std_logic:='1';
output : out std_logic_vector(DATA_SIZE-1 downto 0);
match_dirty_f : out std_logic;
match_dirty_ff : out std_logic
);
end component;
constant REG_NUM : integer := C_REG_NUM;
constant REG_ADDR_SIZE : integer := MyLog2Ceil(REG_NUM);
constant MUL_STAGE : integer := C_MUL_STAGE;
constant DIV_STAGE : integer := C_DIV_STAGE;
constant SQRT_STAGE : integer := C_SQRT_STAGE;
-- Program Counters
signal s1_pc, s2_pc, s1_jpc, s2_jpc, s1_npc, s2_npc: std_logic_vector(ADDR_SIZE-1 downto 0):= (others=>'0');
signal s1_4 : std_logic_vector(DATA_SIZE-1 downto 0) := (2 => '1', others => '0');
-- Instruction
signal s2_istr : std_logic_vector(ISTR_SIZE-1 downto 0):= (others=>'0');
-- Register File
signal s2_rf_en : std_logic:='0';
signal s2_rd1_addr, s3_rd1_addr, s2_rd2_addr, s3_rd2_addr, s4_rd2_addr, s2_wr_addr, s2_wr_addr_r, s2_wr_addr_i, s3_wr_addr, s4_wr_addr, s5_wr_addr, s6_wr_addr : std_logic_vector(REG_ADDR_SIZE-1 downto 0):=(others=>'0');
signal s2_wr_addr_sel: std_logic:='0';
-- ALU operands
signal s2_a, s2_b, s3_a, s3_b, s4_a, s4_b : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s2_imm_i : std_logic_vector(IMME_SIZE-1 downto 0):=(others=>'0');
signal s2_imm_j : std_logic_vector(ISTR_SIZE-OPCD_SIZE-1 downto 0):=(others=>'0');
signal s2_imm_l_ext, s2_imm_h_ext, s2_imm_j_ext, s2_imm_i_ext, s3_imm_i_ext : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s3_a_keep, s3_b_keep, s3_a_sel, s3_b_fwd, s3_b_sel, s4_b_fwd : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s3_mul_op, s3_div_op, s3_sqrt_op, s3_div_sqrt_op : std_logic:='0';
signal s3_exe_sel : std_logic_vector(1 downto 0):= "00";
signal s3_alu_out, s3_mul_out, s3_div_out, s3_exe_out, s4_exe_out : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s3_mul_lock, s3_div_lock, s3_mul_sign, s3_div_sign:std_logic:='0';
signal s4_mem_in, s4_mem_out : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s4_result, s5_result, s6_result : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
signal s3_reg_a_wait, s3_reg_b_wait: std_logic:='0';
signal s2_jump_addr_imm, s2_jump_addr_rel, s2_jump_addr_reg:std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal s2_branch_flag, s2_jr_flag, s2_j_flag, s2_jump_flag, s3_jump_flag: std_logic;
signal s2_a_f_b_en, s2_a_ff_b_en, s2_a_f_j_en, s2_a_ff_j_en: std_logic;
signal s4_reg_a_wait, s4_reg_b_wait: std_logic:='0';
signal s3_a_sel_f_en,s3_a_sel_ff_en, s3_b_sel_f_en, s3_b_sel_ff_en:std_logic;
signal s2_jump_test:std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal s2_pc_sel, s2_pc_notsel, s3_pc_notsel:std_logic_vector(ADDR_SIZE-1 downto 0):=(others=>'0');
signal s6_en_wb: std_logic:='0';
begin
-- PIPELINE STATE 1 : [IF]
istr_addr <= s1_pc; -- to IRAM
-- NPC=PC+4
ADD_4: Adder
generic map (ADDR_SIZE)
port map ('0', s1_pc, s1_4, s1_npc, open);
MUX_bpw: Mux
generic map(ADDR_SIZE)
port map (sig_bpw, s2_pc_sel, s3_pc_notsel, s1_pc);
-- REGISTERS : [IF]||[ID]
REG_PC: Reg
generic map (ADDR_SIZE)
port map (rst, cw(CW_S1_LATCH), clk, s1_pc, s2_pc);
REG_NPC: Reg
generic map (ADDR_SIZE)
port map (rst, cw(CW_S1_LATCH), clk, s1_npc, s2_npc);
-- PIPELINE STAGE 2: [ID]
s2_istr <= istr_val; -- from IRAM
ir_out <= s2_istr; -- to Control Unit
pc_out <= s2_pc;
s2_rd1_addr <= s2_istr(ISTR_SIZE-OPCD_SIZE-1 downto ISTR_SIZE-OPCD_SIZE-REG_ADDR_SIZE);
s2_rd2_addr <= s2_istr(ISTR_SIZE-OPCD_SIZE-REG_ADDR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE-2*REG_ADDR_SIZE);
s2_imm_i <= s2_istr(IMME_SIZE-1 downto 0);
s2_imm_j <= s2_istr(ISTR_SIZE-OPCD_SIZE-1 downto 0);
-- Choose from NPC and JUMP ADDRESS in case of JUMP.
MUX_PC: Mux
generic map (ADDR_SIZE)
port map (cw(CW_S2_JUMP), s2_npc, s2_jpc, s2_pc_sel);
MUX_NOTPC: Mux
generic map (ADDR_SIZE)
port map (cw(CW_S2_JUMP), s2_jpc, s2_npc, s2_pc_notsel);
----------------------------------------------------------------------------
-- FIXME
-- Weired!!!
-- Have to set the highest bit to 0 to avoid "Bound check failure"
----------------------------------------------------------------------------
s2_jpc <= s2_jump_test and x"7fffffff";
----------------------------------------------------------------------------
-- NOTE:
-- This process is used to extract the correct write back address from instruction.
-- If it's a R-TYPE instruction, the write back address should be s2_wr_addr_r,
-- ohterwise, it should be s2_wr_addr_i.
----------------------------------------------------------------------------
s2_wr_addr_r <= s2_istr(ISTR_SIZE-OPCD_SIZE-2*REG_ADDR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE-3*REG_ADDR_SIZE);
s2_wr_addr_i <= s2_istr(ISTR_SIZE-OPCD_SIZE-REG_ADDR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE-2*REG_ADDR_SIZE);
P0:process(s2_istr(ISTR_SIZE-1 downto OPCD_SIZE))
begin
if (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_R) then
s2_wr_addr_sel <= '0'; -- R_TYPE
elsif (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_F) then
s2_wr_addr_sel <= '0'; -- F_TYPE
else
s2_wr_addr_sel <= '1'; -- OTHER TYPES
end if;
end process;
MUX_WB_ADDR: Mux
generic map (REG_ADDR_SIZE)
port map (s2_wr_addr_sel, s2_wr_addr_r, s2_wr_addr_i, s2_wr_addr);
----------------------------------------------------------------------------
-- NOTE:
-- This 3 extenders are used to extend variable/address. The L-EXTENDER extends
-- immediate variable as well as relative address in either signed or unsigned
-- mode; While the J-EXTENDER deal with the 26-bit relative address in signed mode.
-- The H-EXTENDER extends 16-bit variable with 0s in lower side.(ONLY FOR LHI)
----------------------------------------------------------------------------
EXT_L: Extender
generic map(IMME_SIZE, DATA_SIZE)
port map(cw(CW_S2_EXT_S), s2_imm_i, s2_imm_l_ext);
EXT_J: Extender
generic map(ISTR_SIZE-OPCD_SIZE, ADDR_SIZE)
port map('1', s2_imm_j, s2_imm_j_ext);
-- EXT_H
s2_imm_h_ext(DATA_SIZE-1 downto DATA_SIZE/2) <= s2_imm_i;
s2_imm_h_ext(DATA_SIZE/2-1 downto 0) <= (others=>'0');
-- EXT_I final
s2_imm_i_ext <= s2_imm_h_ext when s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_LHI else s2_imm_l_ext;
----------------------------------------------------------------------------
-- NOTE:
-- Register File
----------------------------------------------------------------------------
s2_rf_en <= (cw(CW_S2_LATCH) or cw(CW_S5_EN_WB));
RF0: RegisterFile
generic map(DATA_SIZE, REG_NUM)
port map(clk, rst, s2_rf_en, cw(CW_S2_LATCH), cw(CW_S2_LATCH), cw(CW_S5_EN_WB), cw(CW_S2_LINK), s2_rd1_addr, s2_rd2_addr, s5_wr_addr, s2_a, s2_b, s5_result, s2_npc);
----------------------------------------------------------------------------
-- NOTE:
-- Jump address calculation
----------------------------------------------------------------------------
MUX_JPC0: Mux
generic map (ADDR_SIZE)
port map (cw(CW_S2_SEL_JA_0), s2_imm_i_ext, s2_imm_j_ext, s2_jump_addr_imm);
ADDER_ADDR: Adder
generic map(ADDR_SIZE)
port map('0', s2_npc, s2_jump_addr_imm, s2_jump_addr_rel, open);
MUX_JPC1: Mux
generic map (ADDR_SIZE)
port map (cw(CW_S2_SEL_JA_1), s2_jump_addr_rel, s2_jump_addr_reg, s2_jump_test);
PROG: process(s2_istr, s2_branch_flag,s2_jr_flag,s2_j_flag)
begin
if (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_BEQZ) or (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_BNEZ) then
s2_branch_flag <= '1';
else
s2_branch_flag <= '0';
end if;
if (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_JR) or (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_JALR) then
s2_jr_flag <= '1';
else
s2_jr_flag <= '0';
end if;
if (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_J) or (s2_istr(ISTR_SIZE-1 downto ISTR_SIZE-OPCD_SIZE)=OPCD_JAL) then
s2_j_flag <= '1';
else
s2_j_flag <= '0';
end if;
s2_jump_flag <= s2_branch_flag or s2_jr_flag or s2_j_flag;
end process;
s2_a_f_b_en <= cw(CW_S3_WB_FLAG) and s2_branch_flag;
s2_a_ff_b_en <= cw(CW_S4_WB_FLAG) and s2_branch_flag;
FWDMUX_2AB: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s2_a, s3_exe_out, s4_result, s2_rd1_addr, s3_wr_addr, s4_wr_addr, s2_a_f_b_en, s2_a_ff_b_en, cw(CW_S3_LD_FLAG), '0', '1', reg_a_out, sig_bal, open);
s2_a_f_j_en <= cw(CW_S3_WB_FLAG) and s2_jr_flag;
s2_a_ff_j_en <= cw(CW_S4_WB_FLAG) and s2_jr_flag;
FWDMUX_2AJ: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s2_a, s3_exe_out, s4_result, s2_rd1_addr, s3_wr_addr, s4_wr_addr, s2_a_f_j_en, s2_a_ff_j_en, cw(CW_S3_LD_FLAG), '0', '1', s2_jump_addr_reg, sig_jral, open);
-- REGISTERS : [ID]||[EXE]
REG_A: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_a, s3_a);
REG_B: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_b, s3_b);
REG_I: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_imm_i_ext, s3_imm_i_ext);
REG_WR2: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_wr_addr, s3_wr_addr);
REG_A_ADDR_2: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_rd1_addr, s3_rd1_addr);
REG_B_ADDR_2: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_rd2_addr, s3_rd2_addr);
REG_PC_NOT_SEL: Reg
generic map(ADDR_SIZE)
port map(rst, cw(CW_S2_LATCH), clk, s2_pc_notsel, s3_pc_notsel);
PROCJUMPFLAG: process(clk)
begin
if rising_edge(clk) and cw(CW_S2_LATCH)='1' then
s3_jump_flag <= s2_jump_flag;
end if;
end process;
-- PIPELIE STAGE 3 : [EXE]
MUX_KEEP_A:Mux
generic map(DATA_SIZE)
port map(s4_reg_b_wait, s3_a, s4_a, s3_a_keep);
MUX_KEEP_B:Mux
generic map(DATA_SIZE)
port map(s4_reg_a_wait, s3_b, s4_b, s3_b_keep);
----------------------------------------------------------------------------
-- NOTE:
-- When stage 3 is JUMP/BRANCH instruction, no need to forward, because JUMP/BRANCH
-- instructions have nothing to do in stage 3,4 and 5.
----------------------------------------------------------------------------
s3_a_sel_f_en <= cw(CW_S4_WB_FLAG) and (not s3_jump_flag);
s3_a_sel_ff_en <= cw(CW_S5_EN_WB) and (not s3_jump_flag);
FWDMUX_A: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s3_a_keep, s4_exe_out, s5_result, s3_rd1_addr, s4_wr_addr, s5_wr_addr, s3_a_sel_f_en, s3_a_sel_ff_en, cw(CW_S4_LD_FLAG), '0', '1', s3_a_sel, s3_reg_a_wait, open);
s3_b_sel_f_en <= cw(CW_S4_WB_FLAG) and (not cw(CW_S3_SEL_B)) and (not s3_jump_flag);
s3_b_sel_ff_en <= cw(CW_S5_EN_WB) and (not cw(CW_S3_SEL_B)) and (not s3_jump_flag);
FWDMUX_B: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s3_b_keep, s4_exe_out, s5_result, s3_rd2_addr, s4_wr_addr, s5_wr_addr, s3_b_sel_f_en, s3_b_sel_ff_en, cw(CW_S4_LD_FLAG), '0', '1', s3_b_fwd, s3_reg_b_wait, open);
PW: process(s3_reg_a_wait, s3_reg_b_wait)
begin
sig_ral<=(s3_reg_a_wait or s3_reg_b_wait);
end process;
MUXB: Mux
generic map(DATA_SIZE)
port map(cw(CW_S3_SEL_B), s3_b_fwd, s3_imm_i_ext, s3_b_sel);
ALU0: Alu
generic map(DATA_SIZE)
port map(calu, s3_a_sel, s3_b_sel, s3_alu_out);
MUL0: Mul
generic map(DATA_SIZE/2, MUL_STAGE)
port map(rst, clk, s3_mul_op, s3_mul_lock, s3_mul_sign, s3_a_sel(DATA_SIZE/2-1 downto 0), s3_b_sel(DATA_SIZE/2-1 downto 0), s3_mul_out);
DIV0: Div
generic map(DATA_SIZE, DIV_STAGE, SQRT_STAGE)
port map(rst, clk, s3_div_sqrt_op, s3_div_lock, s3_div_sign, s3_sqrt_op, s3_a_sel, s3_b_sel, s3_div_out);
----------------------------------------------------------------------------
-- FIXME
-- only signed mult and unsigned div can produce correct value.
----------------------------------------------------------------------------
s3_mul_op <= '1' when calu="01000" or calu="01001" else '0';
sig_mul <= s3_mul_op;
s3_div_op <= '1' when calu="01010" or calu="01011" else '0';
sig_div <= s3_div_op;
s3_sqrt_op <= '1' when calu="01100" else '0';
sig_sqrt <= s3_sqrt_op;
s3_div_sqrt_op <= s3_div_op or s3_sqrt_op;
s3_exe_sel <= s3_div_sqrt_op & s3_mul_op;
s3_mul_sign <= '1' when calu="01001" else '0';
s3_div_sign <= '1' when calu="01011" else '0';
s3_div_lock <= (s3_reg_a_wait or s3_reg_b_wait);
s3_mul_lock <= (s3_reg_a_wait or s3_reg_b_wait);
MUXEXE: Mux4
generic map(DATA_SIZE)
port map(s3_exe_sel, s3_alu_out, s3_mul_out, s3_div_out, (others=>'0'), s3_exe_out);
-- REGISTERS : [EXE]||[MEM]
REG_ALU: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S3_LATCH), clk, s3_exe_out, s4_exe_out);
REG_BB: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S3_LATCH), clk, s3_b_fwd, s4_b_fwd);
REG_B_ADDR_3: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S3_LATCH), clk, s3_rd2_addr, s4_rd2_addr);
REG_WR3: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S3_LATCH), clk, s3_wr_addr, s4_wr_addr);
----------------------------------------------------------------------------
-- NOTE:
-- COMP: REG_OPRD_A_WAIT, REG_OPRD_B_WAIT
-- DESC: Registers for keeping the operand A and B to PIPELINE STATGE 4 [MEM].
-- When A causes a STALL, due to forward value is not ready (Load After Read)
-- in stage 4, and B uses the value of double-forward (from stage 5)
-- which is valid. We need to keep the value of B because once the
-- STALL complete, the valid value of B in stage 5 will be stored in Register File.
-- At this moment, other instruction occupies the stage 2, so we cannot
-- get the value of B for the instruction in stage 3. Therefore, we
-- need this two registers to store the value of A and B.
----------------------------------------------------------------------------
REG_OPRD_A_WAIT: Reg
generic map(DATA_SIZE)
port map(rst, '1', clk, s3_a_sel, s4_a);
REG_OPRD_B_WAIT: Reg
generic map(DATA_SIZE)
port map(rst, '1', clk, s3_b_sel, s4_b);
PROCWAIT: process(clk)
begin
if rising_edge(clk) then
s4_reg_a_wait <= s3_reg_a_wait;
s4_reg_b_wait <= s3_reg_b_wait;
end if;
end process;
-- PIPELINE STAGE 4 : [MEM]
-- Signals to Data RAM
data_addr <= s4_exe_out; -- to DRAM
data_o_val <= s4_mem_in; -- to DRAM
s4_mem_out <= data_i_val; -- from DRAM
dr_cw <= cw(CW_S4_DRAM_WR downto CW_S4_DRAM_T_0); -- to DRAM
ld_a_out <= s4_mem_out;
FWDMUX_BB: FwdMux2
generic map(DATA_SIZE, REG_ADDR_SIZE)
port map(s4_b_fwd, s5_result, s6_result, s4_rd2_addr, s5_wr_addr, s6_wr_addr, cw(CW_S5_EN_WB), s6_en_wb, '0', '0', cw(CW_S4_DRAM_WR), s4_mem_in, open, open);
MUX_RESULT: Mux
generic map(DATA_SIZE)
port map(cw(CW_S4_SEL_WB), s4_exe_out, s4_mem_out, s4_result);
-- REGISTERS : [MEM]||[WB]
REG_RESULT: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S4_LATCH), clk, s4_result, s5_result);
REG_WR4: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S4_LATCH), clk, s4_wr_addr, s5_wr_addr);
-- PIPELINE STAGE 5 : [WB]
-- No component needed in pipeline 5, because every operation happens in Register File.
-- DELAY s5_result is to forwarding for STORE;
-- REGISTERS : [WB]||[EXTRA STAGE]
REG_RESULT5: Reg
generic map(DATA_SIZE)
port map(rst, cw(CW_S5_EN_WB), clk, s5_result, s6_result);
REG_WR5: Reg
generic map(REG_ADDR_SIZE)
port map(rst, cw(CW_S5_EN_WB), clk, s5_wr_addr, s6_wr_addr);
REG5:process(rst, clk)
begin
if rst='0' then
s6_en_wb <= '0';
else
if rising_edge(clk) and cw(CW_S5_EN_WB)='1' then
s6_en_wb <= '1';
end if;
end if;
end process;
end data_path_arch;
|
library verilog;
use verilog.vl_types.all;
entity mist1032sa_uart_receiver is
generic(
BAUDRATE_FIXED : vl_logic := Hi1;
BAUDRATE_COUNTER: vl_logic_vector(0 to 19) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi1, Hi1, Hi0, Hi1, Hi1, Hi0, Hi0)
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iEXTBAUD_COUNT : in vl_logic_vector(19 downto 0);
oRX_VALID : out vl_logic;
oRX_DATA : out vl_logic_vector(7 downto 0);
iUART_RXD : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of BAUDRATE_FIXED : constant is 1;
attribute mti_svvh_generic_type of BAUDRATE_COUNTER : constant is 1;
end mist1032sa_uart_receiver;
|
-- File: ./ex-target/Rectifier.vhd
-- Generated by MyHDL 1.0dev
-- Date: Mon Oct 5 14:11:09 2015
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity Rectifier is
port (
y: out signed (15 downto 0);
y_dx: out signed (15 downto 0);
x: in signed (15 downto 0)
);
end entity Rectifier;
-- Rectified linear unit (ReLU) and derivative model using fixbv type.
--
-- :param y: return max(0, x) as fixbv
-- :param y_dx: return d/dx max(0, x) as fixbv
-- :param x: input value as fixbv
-- :param leaky_val: factor for leaky ReLU, 0.0 without
-- :param fix_min: fixbv min value
-- :param fix_max: fixbv max value
-- :param fix_res: fixbv resolution
architecture MyHDL of Rectifier is
begin
RECTIFIER_RELU: process (x) is
variable zero: signed(15 downto 0);
variable leaky: signed(15 downto 0);
begin
if (x > zero) then
y <= x;
else
y <= to_signed((leaky * x), 16);
end if;
end process RECTIFIER_RELU;
RECTIFIER_RELU_DX: process (x) is
variable zero: signed(15 downto 0);
variable leaky: signed(15 downto 0);
variable one: signed(15 downto 0);
begin
if (x > zero) then
y_dx <= one;
else
y_dx <= leaky;
end if;
end process RECTIFIER_RELU_DX;
end architecture MyHDL;
|
--!
--! @file: exercise5_16.vhd
--! @brief: Recommended signed Multiplier Implementation
--! @author: Antonio Gutierrez
--! @date: 2013-10-23
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity signed_multiplier is
generic
port (
a, b: in std_logic_vector(4 downto 0);
prod: out std_logic_vector(9 downto 0));
end entity signed_multiplier;
--------------------------------------
architecture circuit of signed_multiplier is
signal a_un, b_un: signed(4 downto 0);
signal prod_un: signed(9 downto 0);
begin
--------------------------------------
a_un <= signed(a);
b_un <= signed(b);
--------------------------------------
prod_un <= a_un * b_un;
--------------------------------------
prod <= std_logic_vector(prod_un);
--------------------------------------
end architecture circuit;
--------------------------------------
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:00:38 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_1/zqynq_lab_1_design_axi_timer_0_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_timer_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_cdc_sync is
port (
captureTrig0_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_cdc_sync : entity is "cdc_sync";
end zqynq_lab_1_design_axi_timer_0_1_cdc_sync;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_cdc_sync is
signal CaptureTrig0_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig0,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig0_int,
R => '0'
);
captureTrig0_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig0_int,
O => captureTrig0_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1 is
port (
captureTrig1_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1 : entity is "cdc_sync";
end zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1 is
signal CaptureTrig1_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig1_int,
R => '0'
);
captureTrig1_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig1_int,
O => captureTrig1_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 );
read_Mux_In : in STD_LOGIC_VECTOR ( 7 downto 0 );
generateOutPre0 : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
Load_Counter_Reg030_out : in STD_LOGIC;
Load_Counter_Reg031_out : in STD_LOGIC;
\Load_Counter_Reg0__0\ : in STD_LOGIC;
Load_Counter_Reg028_out : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2 : entity is "cdc_sync";
end zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2 is
signal \Counter_En041_out__2\ : STD_LOGIC;
signal \Counter_En043_out__0\ : STD_LOGIC;
signal \Counter_En045_out__1\ : STD_LOGIC;
signal \Counter_En0__4\ : STD_LOGIC;
signal Freeze_int : STD_LOGIC;
signal counter_En : STD_LOGIC_VECTOR ( 0 to 1 );
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => freeze,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => Freeze_int,
R => '0'
);
\INFERRED_GEN.icount_out[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFFFCAA"
)
port map (
I0 => Load_Counter_Reg030_out,
I1 => Load_Counter_Reg031_out,
I2 => \Counter_En043_out__0\,
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => \Counter_En041_out__2\,
O => E(0)
);
\INFERRED_GEN.icount_out[31]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFFFCAA"
)
port map (
I0 => \Load_Counter_Reg0__0\,
I1 => Load_Counter_Reg028_out,
I2 => \Counter_En045_out__1\,
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => \Counter_En0__4\,
O => \INFERRED_GEN.icount_out_reg[0]\(0)
);
\INFERRED_GEN.icount_out[31]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FB0000"
)
port map (
I0 => read_Mux_In(4),
I1 => counter_TC(1),
I2 => read_Mux_In(6),
I3 => Freeze_int,
I4 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
O => \Counter_En043_out__0\
);
\INFERRED_GEN.icount_out[31]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040404040004040"
)
port map (
I0 => Freeze_int,
I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I2 => generateOutPre0,
I3 => read_Mux_In(6),
I4 => counter_TC(1),
I5 => read_Mux_In(4),
O => \Counter_En045_out__1\
);
\INFERRED_GEN.icount_out[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444404"
)
port map (
I0 => Freeze_int,
I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I2 => counter_TC(0),
I3 => read_Mux_In(7),
I4 => read_Mux_In(6),
I5 => read_Mux_In(4),
O => \Counter_En041_out__2\
);
\INFERRED_GEN.icount_out[31]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2222222222202222"
)
port map (
I0 => \TCSR1_GENERATE[24].TCSR1_FF_I\,
I1 => Freeze_int,
I2 => read_Mux_In(3),
I3 => read_Mux_In(2),
I4 => counter_TC(1),
I5 => read_Mux_In(0),
O => \Counter_En0__4\
);
icount_out0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(1),
I1 => counter_En(0),
I2 => read_Mux_In(5),
O => S(0)
);
\icount_out0_carry_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6A666AAA"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(0),
I1 => counter_En(1),
I2 => read_Mux_In(5),
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => read_Mux_In(1),
O => \INFERRED_GEN.icount_out_reg[4]\(0)
);
icount_out0_carry_i_6: unisim.vcomponents.MUXF7
port map (
I0 => \Counter_En041_out__2\,
I1 => \Counter_En043_out__0\,
O => counter_En(0),
S => \TCSR0_GENERATE[20].TCSR0_FF_I\
);
\icount_out0_carry_i_6__0\: unisim.vcomponents.MUXF7
port map (
I0 => \Counter_En0__4\,
I1 => \Counter_En045_out__1\,
O => counter_En(1),
S => \TCSR0_GENERATE[20].TCSR0_FF_I\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_counter_f is
port (
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
generateOutPre1_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
read_Mux_In : in STD_LOGIC_VECTOR ( 31 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_counter_f : entity is "counter_f";
end zqynq_lab_1_design_axi_timer_0_1_counter_f;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_counter_f is
signal \INFERRED_GEN.icount_out[0]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[10]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[11]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[12]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[13]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[14]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[15]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[16]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[17]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[18]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[19]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[1]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[20]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[21]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[22]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[23]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[24]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[25]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[26]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[27]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[28]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[29]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[2]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[30]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[31]_i_2_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[3]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[4]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[5]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[6]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[7]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[8]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[9]_i_1_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal icount_out0_carry_i_1_n_0 : STD_LOGIC;
signal icount_out0_carry_i_2_n_0 : STD_LOGIC;
signal icount_out0_carry_i_3_n_0 : STD_LOGIC;
signal icount_out0_carry_i_4_n_0 : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1\ : label is "soft_lutpair45";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
Q(31 downto 0) <= \^q\(31 downto 0);
SR(0) <= \^sr\(0);
counter_TC(0) <= \^counter_tc\(0);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(31),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(31),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(31),
O => \s_axi_rdata_i_reg[31]\
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(21),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(21),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(21),
O => \s_axi_rdata_i_reg[21]\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(20),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(20),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(20),
O => \s_axi_rdata_i_reg[20]\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(19),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(19),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(19),
O => \s_axi_rdata_i_reg[19]\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(18),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(18),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(18),
O => \s_axi_rdata_i_reg[18]\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(17),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(17),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(17),
O => \s_axi_rdata_i_reg[17]\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(16),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(16),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(16),
O => \s_axi_rdata_i_reg[16]\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(15),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(15),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(15),
O => \s_axi_rdata_i_reg[15]\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(14),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(14),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(14),
O => \s_axi_rdata_i_reg[14]\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(13),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(13),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(13),
O => \s_axi_rdata_i_reg[13]\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(12),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(12),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(12),
O => \s_axi_rdata_i_reg[12]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(30),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(30),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(30),
O => \s_axi_rdata_i_reg[30]\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(11),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(11),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(11),
O => \s_axi_rdata_i_reg[11]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(10),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(10),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(10),
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(9),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(9),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(9),
O => \s_axi_rdata_i_reg[9]\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(8),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(8),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(8),
O => \s_axi_rdata_i_reg[8]\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(7),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(7),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(7),
O => \s_axi_rdata_i_reg[7]\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(6),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(6),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(6),
O => \s_axi_rdata_i_reg[6]\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(5),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(5),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(5),
O => \s_axi_rdata_i_reg[5]\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(4),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(4),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(4),
O => \s_axi_rdata_i_reg[4]\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(3),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(3),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(3),
O => \s_axi_rdata_i_reg[3]\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(2),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(2),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(2),
O => \s_axi_rdata_i_reg[2]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(29),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(29),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(29),
O => \s_axi_rdata_i_reg[29]\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(1),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(1),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(1),
O => \s_axi_rdata_i_reg[1]\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(0),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(0),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(0),
O => \s_axi_rdata_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(28),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(28),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(28),
O => \s_axi_rdata_i_reg[28]\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(27),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(27),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(27),
O => \s_axi_rdata_i_reg[27]\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(26),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(26),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(26),
O => \s_axi_rdata_i_reg[26]\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(25),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(25),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(25),
O => \s_axi_rdata_i_reg[25]\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(24),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(24),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(24),
O => \s_axi_rdata_i_reg[24]\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(23),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(23),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(23),
O => \s_axi_rdata_i_reg[23]\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(22),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(22),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(22),
O => \s_axi_rdata_i_reg[22]\
);
GenerateOut0_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\INFERRED_GEN.icount_out[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A3"
)
port map (
I0 => read_Mux_In(0),
I1 => \^q\(0),
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[0]_i_1_n_0\
);
\INFERRED_GEN.icount_out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(10),
I1 => \icount_out0_carry__1_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[10]_i_1_n_0\
);
\INFERRED_GEN.icount_out[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(11),
I1 => \icount_out0_carry__1_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[11]_i_1_n_0\
);
\INFERRED_GEN.icount_out[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(12),
I1 => \icount_out0_carry__1_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[12]_i_1_n_0\
);
\INFERRED_GEN.icount_out[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(13),
I1 => \icount_out0_carry__2_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[13]_i_1_n_0\
);
\INFERRED_GEN.icount_out[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(14),
I1 => \icount_out0_carry__2_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[14]_i_1_n_0\
);
\INFERRED_GEN.icount_out[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(15),
I1 => \icount_out0_carry__2_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[15]_i_1_n_0\
);
\INFERRED_GEN.icount_out[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(16),
I1 => \icount_out0_carry__2_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[16]_i_1_n_0\
);
\INFERRED_GEN.icount_out[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(17),
I1 => \icount_out0_carry__3_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[17]_i_1_n_0\
);
\INFERRED_GEN.icount_out[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(18),
I1 => \icount_out0_carry__3_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[18]_i_1_n_0\
);
\INFERRED_GEN.icount_out[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(19),
I1 => \icount_out0_carry__3_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[19]_i_1_n_0\
);
\INFERRED_GEN.icount_out[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(1),
I1 => icount_out0_carry_n_7,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[1]_i_1_n_0\
);
\INFERRED_GEN.icount_out[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(20),
I1 => \icount_out0_carry__3_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[20]_i_1_n_0\
);
\INFERRED_GEN.icount_out[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(21),
I1 => \icount_out0_carry__4_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[21]_i_1_n_0\
);
\INFERRED_GEN.icount_out[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(22),
I1 => \icount_out0_carry__4_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[22]_i_1_n_0\
);
\INFERRED_GEN.icount_out[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(23),
I1 => \icount_out0_carry__4_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[23]_i_1_n_0\
);
\INFERRED_GEN.icount_out[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(24),
I1 => \icount_out0_carry__4_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[24]_i_1_n_0\
);
\INFERRED_GEN.icount_out[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(25),
I1 => \icount_out0_carry__5_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[25]_i_1_n_0\
);
\INFERRED_GEN.icount_out[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(26),
I1 => \icount_out0_carry__5_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[26]_i_1_n_0\
);
\INFERRED_GEN.icount_out[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(27),
I1 => \icount_out0_carry__5_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[27]_i_1_n_0\
);
\INFERRED_GEN.icount_out[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(28),
I1 => \icount_out0_carry__5_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[28]_i_1_n_0\
);
\INFERRED_GEN.icount_out[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(29),
I1 => \icount_out0_carry__6_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[29]_i_1_n_0\
);
\INFERRED_GEN.icount_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(2),
I1 => icount_out0_carry_n_6,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[2]_i_1_n_0\
);
\INFERRED_GEN.icount_out[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(30),
I1 => \icount_out0_carry__6_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[30]_i_1_n_0\
);
\INFERRED_GEN.icount_out[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(31),
I1 => \icount_out0_carry__6_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[31]_i_2_n_0\
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^counter_tc\(0),
I1 => E(0),
I2 => \icount_out0_carry__6_n_4\,
I3 => s_axi_aresetn,
I4 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(3),
I1 => icount_out0_carry_n_5,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[3]_i_1_n_0\
);
\INFERRED_GEN.icount_out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(4),
I1 => icount_out0_carry_n_4,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[4]_i_1_n_0\
);
\INFERRED_GEN.icount_out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(5),
I1 => \icount_out0_carry__0_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[5]_i_1_n_0\
);
\INFERRED_GEN.icount_out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(6),
I1 => \icount_out0_carry__0_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[6]_i_1_n_0\
);
\INFERRED_GEN.icount_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(7),
I1 => \icount_out0_carry__0_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[7]_i_1_n_0\
);
\INFERRED_GEN.icount_out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(8),
I1 => \icount_out0_carry__0_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[8]_i_1_n_0\
);
\INFERRED_GEN.icount_out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(9),
I1 => \icount_out0_carry__1_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[9]_i_1_n_0\
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[0]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[10]_i_1_n_0\,
Q => \^q\(10),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[11]_i_1_n_0\,
Q => \^q\(11),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[12]_i_1_n_0\,
Q => \^q\(12),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[13]_i_1_n_0\,
Q => \^q\(13),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[14]_i_1_n_0\,
Q => \^q\(14),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[15]_i_1_n_0\,
Q => \^q\(15),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[16]_i_1_n_0\,
Q => \^q\(16),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[17]_i_1_n_0\,
Q => \^q\(17),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[18]_i_1_n_0\,
Q => \^q\(18),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[19]_i_1_n_0\,
Q => \^q\(19),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[1]_i_1_n_0\,
Q => \^q\(1),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[20]_i_1_n_0\,
Q => \^q\(20),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[21]_i_1_n_0\,
Q => \^q\(21),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[22]_i_1_n_0\,
Q => \^q\(22),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[23]_i_1_n_0\,
Q => \^q\(23),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[24]_i_1_n_0\,
Q => \^q\(24),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[25]_i_1_n_0\,
Q => \^q\(25),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[26]_i_1_n_0\,
Q => \^q\(26),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[27]_i_1_n_0\,
Q => \^q\(27),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[28]_i_1_n_0\,
Q => \^q\(28),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[29]_i_1_n_0\,
Q => \^q\(29),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[2]_i_1_n_0\,
Q => \^q\(2),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[30]_i_1_n_0\,
Q => \^q\(30),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[31]_i_2_n_0\,
Q => \^q\(31),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[3]_i_1_n_0\,
Q => \^q\(3),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[4]_i_1_n_0\,
Q => \^q\(4),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[5]_i_1_n_0\,
Q => \^q\(5),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[6]_i_1_n_0\,
Q => \^q\(6),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[7]_i_1_n_0\,
Q => \^q\(7),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[8]_i_1_n_0\,
Q => \^q\(8),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[9]_i_1_n_0\,
Q => \^q\(9),
R => \^sr\(0)
);
generateOutPre1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => \counter_TC_Reg_reg[1]\(0),
O => generateOutPre1_reg
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^q\(0),
DI(3 downto 1) => \^q\(3 downto 1),
DI(0) => icount_out0_carry_i_1_n_0,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => icount_out0_carry_i_2_n_0,
S(2) => icount_out0_carry_i_3_n_0,
S(1) => icount_out0_carry_i_4_n_0,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1_n_0\,
S(2) => \icount_out0_carry__0_i_2_n_0\,
S(1) => \icount_out0_carry__0_i_3_n_0\,
S(0) => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => \^q\(8),
O => \icount_out0_carry__0_i_1_n_0\
);
\icount_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => \^q\(7),
O => \icount_out0_carry__0_i_2_n_0\
);
\icount_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => \^q\(6),
O => \icount_out0_carry__0_i_3_n_0\
);
\icount_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \^q\(5),
O => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1_n_0\,
S(2) => \icount_out0_carry__1_i_2_n_0\,
S(1) => \icount_out0_carry__1_i_3_n_0\,
S(0) => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(11),
I1 => \^q\(12),
O => \icount_out0_carry__1_i_1_n_0\
);
\icount_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => \^q\(11),
O => \icount_out0_carry__1_i_2_n_0\
);
\icount_out0_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(9),
I1 => \^q\(10),
O => \icount_out0_carry__1_i_3_n_0\
);
\icount_out0_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \^q\(9),
O => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1_n_0\,
S(2) => \icount_out0_carry__2_i_2_n_0\,
S(1) => \icount_out0_carry__2_i_3_n_0\,
S(0) => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(15),
I1 => \^q\(16),
O => \icount_out0_carry__2_i_1_n_0\
);
\icount_out0_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(14),
I1 => \^q\(15),
O => \icount_out0_carry__2_i_2_n_0\
);
\icount_out0_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(13),
I1 => \^q\(14),
O => \icount_out0_carry__2_i_3_n_0\
);
\icount_out0_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(12),
I1 => \^q\(13),
O => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1_n_0\,
S(2) => \icount_out0_carry__3_i_2_n_0\,
S(1) => \icount_out0_carry__3_i_3_n_0\,
S(0) => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(19),
I1 => \^q\(20),
O => \icount_out0_carry__3_i_1_n_0\
);
\icount_out0_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(18),
I1 => \^q\(19),
O => \icount_out0_carry__3_i_2_n_0\
);
\icount_out0_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(17),
I1 => \^q\(18),
O => \icount_out0_carry__3_i_3_n_0\
);
\icount_out0_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(16),
I1 => \^q\(17),
O => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1_n_0\,
S(2) => \icount_out0_carry__4_i_2_n_0\,
S(1) => \icount_out0_carry__4_i_3_n_0\,
S(0) => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(23),
I1 => \^q\(24),
O => \icount_out0_carry__4_i_1_n_0\
);
\icount_out0_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(22),
I1 => \^q\(23),
O => \icount_out0_carry__4_i_2_n_0\
);
\icount_out0_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(21),
I1 => \^q\(22),
O => \icount_out0_carry__4_i_3_n_0\
);
\icount_out0_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(20),
I1 => \^q\(21),
O => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1_n_0\,
S(2) => \icount_out0_carry__5_i_2_n_0\,
S(1) => \icount_out0_carry__5_i_3_n_0\,
S(0) => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(27),
I1 => \^q\(28),
O => \icount_out0_carry__5_i_1_n_0\
);
\icount_out0_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(26),
I1 => \^q\(27),
O => \icount_out0_carry__5_i_2_n_0\
);
\icount_out0_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(25),
I1 => \^q\(26),
O => \icount_out0_carry__5_i_3_n_0\
);
\icount_out0_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(24),
I1 => \^q\(25),
O => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^q\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1_n_0\,
S(2) => \icount_out0_carry__6_i_2_n_0\,
S(1) => \icount_out0_carry__6_i_3_n_0\,
S(0) => \icount_out0_carry__6_i_4_n_0\
);
\icount_out0_carry__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(31),
O => \icount_out0_carry__6_i_1_n_0\
);
\icount_out0_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(30),
I1 => \^q\(31),
O => \icount_out0_carry__6_i_2_n_0\
);
\icount_out0_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(29),
I1 => \^q\(30),
O => \icount_out0_carry__6_i_3_n_0\
);
\icount_out0_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(28),
I1 => \^q\(29),
O => \icount_out0_carry__6_i_4_n_0\
);
icount_out0_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(1),
O => icount_out0_carry_i_1_n_0
);
icount_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
O => icount_out0_carry_i_2_n_0
);
icount_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
O => icount_out0_carry_i_3_n_0
);
icount_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => icount_out0_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_counter_f_3 is
port (
\LOAD_REG_GEN[0].LOAD_REG_I\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
generateOutPre0_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
read_Mux_In : in STD_LOGIC_VECTOR ( 10 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\LOAD_REG_GEN[0].LOAD_REG_I_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_counter_f_3 : entity is "counter_f";
end zqynq_lab_1_design_axi_timer_0_1_counter_f_3;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_counter_f_3 is
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \^load_reg_gen[0].load_reg_i\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal \icount_out0_carry_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_4__0_n_0\ : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1__0\ : label is "soft_lutpair29";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) <= \^load_reg_gen[0].load_reg_i\(31 downto 0);
counter_TC(0) <= \^counter_tc\(0);
\INFERRED_GEN.icount_out[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => read_Mux_In(0),
I1 => load_Counter_Reg(0),
I2 => \^load_reg_gen[0].load_reg_i\(0),
O => p_1_in(0)
);
\INFERRED_GEN.icount_out[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_6\,
O => p_1_in(10)
);
\INFERRED_GEN.icount_out[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(0),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_5\,
O => p_1_in(11)
);
\INFERRED_GEN.icount_out[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(1),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_4\,
O => p_1_in(12)
);
\INFERRED_GEN.icount_out[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(2),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_7\,
O => p_1_in(13)
);
\INFERRED_GEN.icount_out[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(3),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_6\,
O => p_1_in(14)
);
\INFERRED_GEN.icount_out[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(4),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_5\,
O => p_1_in(15)
);
\INFERRED_GEN.icount_out[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_4\,
O => p_1_in(16)
);
\INFERRED_GEN.icount_out[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_7\,
O => p_1_in(17)
);
\INFERRED_GEN.icount_out[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_6\,
O => p_1_in(18)
);
\INFERRED_GEN.icount_out[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_5\,
O => p_1_in(19)
);
\INFERRED_GEN.icount_out[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(1),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_7,
O => p_1_in(1)
);
\INFERRED_GEN.icount_out[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_4\,
O => p_1_in(20)
);
\INFERRED_GEN.icount_out[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_7\,
O => p_1_in(21)
);
\INFERRED_GEN.icount_out[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(11),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_6\,
O => p_1_in(22)
);
\INFERRED_GEN.icount_out[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(12),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_5\,
O => p_1_in(23)
);
\INFERRED_GEN.icount_out[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(13),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_4\,
O => p_1_in(24)
);
\INFERRED_GEN.icount_out[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(14),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_7\,
O => p_1_in(25)
);
\INFERRED_GEN.icount_out[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(15),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_6\,
O => p_1_in(26)
);
\INFERRED_GEN.icount_out[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(16),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_5\,
O => p_1_in(27)
);
\INFERRED_GEN.icount_out[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(17),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_4\,
O => p_1_in(28)
);
\INFERRED_GEN.icount_out[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(18),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_7\,
O => p_1_in(29)
);
\INFERRED_GEN.icount_out[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(2),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_6,
O => p_1_in(2)
);
\INFERRED_GEN.icount_out[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(19),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_6\,
O => p_1_in(30)
);
\INFERRED_GEN.icount_out[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(20),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_5\,
O => p_1_in(31)
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^counter_tc\(0),
I1 => E(0),
I2 => \icount_out0_carry__6_n_4\,
I3 => s_axi_aresetn,
I4 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(3),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_5,
O => p_1_in(3)
);
\INFERRED_GEN.icount_out[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(4),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_4,
O => p_1_in(4)
);
\INFERRED_GEN.icount_out[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_7\,
O => p_1_in(5)
);
\INFERRED_GEN.icount_out[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_6\,
O => p_1_in(6)
);
\INFERRED_GEN.icount_out[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_5\,
O => p_1_in(7)
);
\INFERRED_GEN.icount_out[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_4\,
O => p_1_in(8)
);
\INFERRED_GEN.icount_out[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_7\,
O => p_1_in(9)
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(0),
Q => \^load_reg_gen[0].load_reg_i\(0),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(10),
Q => \^load_reg_gen[0].load_reg_i\(10),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(11),
Q => \^load_reg_gen[0].load_reg_i\(11),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(12),
Q => \^load_reg_gen[0].load_reg_i\(12),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(13),
Q => \^load_reg_gen[0].load_reg_i\(13),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(14),
Q => \^load_reg_gen[0].load_reg_i\(14),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(15),
Q => \^load_reg_gen[0].load_reg_i\(15),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(16),
Q => \^load_reg_gen[0].load_reg_i\(16),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(17),
Q => \^load_reg_gen[0].load_reg_i\(17),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(18),
Q => \^load_reg_gen[0].load_reg_i\(18),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(19),
Q => \^load_reg_gen[0].load_reg_i\(19),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(1),
Q => \^load_reg_gen[0].load_reg_i\(1),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(20),
Q => \^load_reg_gen[0].load_reg_i\(20),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(21),
Q => \^load_reg_gen[0].load_reg_i\(21),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(22),
Q => \^load_reg_gen[0].load_reg_i\(22),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(23),
Q => \^load_reg_gen[0].load_reg_i\(23),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(24),
Q => \^load_reg_gen[0].load_reg_i\(24),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(25),
Q => \^load_reg_gen[0].load_reg_i\(25),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(26),
Q => \^load_reg_gen[0].load_reg_i\(26),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(27),
Q => \^load_reg_gen[0].load_reg_i\(27),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(28),
Q => \^load_reg_gen[0].load_reg_i\(28),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(29),
Q => \^load_reg_gen[0].load_reg_i\(29),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(2),
Q => \^load_reg_gen[0].load_reg_i\(2),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(30),
Q => \^load_reg_gen[0].load_reg_i\(30),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(31),
Q => \^load_reg_gen[0].load_reg_i\(31),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(3),
Q => \^load_reg_gen[0].load_reg_i\(3),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(4),
Q => \^load_reg_gen[0].load_reg_i\(4),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(5),
Q => \^load_reg_gen[0].load_reg_i\(5),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(6),
Q => \^load_reg_gen[0].load_reg_i\(6),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(7),
Q => \^load_reg_gen[0].load_reg_i\(7),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(8),
Q => \^load_reg_gen[0].load_reg_i\(8),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(9),
Q => \^load_reg_gen[0].load_reg_i\(9),
R => s_axi_aresetn_0
);
generateOutPre0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => Q(0),
O => generateOutPre0_reg
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^load_reg_gen[0].load_reg_i\(0),
DI(3 downto 1) => \^load_reg_gen[0].load_reg_i\(3 downto 1),
DI(0) => \icount_out0_carry_i_1__0_n_0\,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => \icount_out0_carry_i_2__0_n_0\,
S(2) => \icount_out0_carry_i_3__0_n_0\,
S(1) => \icount_out0_carry_i_4__0_n_0\,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1__0_n_0\,
S(2) => \icount_out0_carry__0_i_2__0_n_0\,
S(1) => \icount_out0_carry__0_i_3__0_n_0\,
S(0) => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__0_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(7),
I1 => \^load_reg_gen[0].load_reg_i\(8),
O => \icount_out0_carry__0_i_1__0_n_0\
);
\icount_out0_carry__0_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(6),
I1 => \^load_reg_gen[0].load_reg_i\(7),
O => \icount_out0_carry__0_i_2__0_n_0\
);
\icount_out0_carry__0_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(5),
I1 => \^load_reg_gen[0].load_reg_i\(6),
O => \icount_out0_carry__0_i_3__0_n_0\
);
\icount_out0_carry__0_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(4),
I1 => \^load_reg_gen[0].load_reg_i\(5),
O => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1__0_n_0\,
S(2) => \icount_out0_carry__1_i_2__0_n_0\,
S(1) => \icount_out0_carry__1_i_3__0_n_0\,
S(0) => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(11),
I1 => \^load_reg_gen[0].load_reg_i\(12),
O => \icount_out0_carry__1_i_1__0_n_0\
);
\icount_out0_carry__1_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(10),
I1 => \^load_reg_gen[0].load_reg_i\(11),
O => \icount_out0_carry__1_i_2__0_n_0\
);
\icount_out0_carry__1_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(9),
I1 => \^load_reg_gen[0].load_reg_i\(10),
O => \icount_out0_carry__1_i_3__0_n_0\
);
\icount_out0_carry__1_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(8),
I1 => \^load_reg_gen[0].load_reg_i\(9),
O => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1__0_n_0\,
S(2) => \icount_out0_carry__2_i_2__0_n_0\,
S(1) => \icount_out0_carry__2_i_3__0_n_0\,
S(0) => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__2_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(15),
I1 => \^load_reg_gen[0].load_reg_i\(16),
O => \icount_out0_carry__2_i_1__0_n_0\
);
\icount_out0_carry__2_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(14),
I1 => \^load_reg_gen[0].load_reg_i\(15),
O => \icount_out0_carry__2_i_2__0_n_0\
);
\icount_out0_carry__2_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(13),
I1 => \^load_reg_gen[0].load_reg_i\(14),
O => \icount_out0_carry__2_i_3__0_n_0\
);
\icount_out0_carry__2_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(12),
I1 => \^load_reg_gen[0].load_reg_i\(13),
O => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1__0_n_0\,
S(2) => \icount_out0_carry__3_i_2__0_n_0\,
S(1) => \icount_out0_carry__3_i_3__0_n_0\,
S(0) => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__3_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(19),
I1 => \^load_reg_gen[0].load_reg_i\(20),
O => \icount_out0_carry__3_i_1__0_n_0\
);
\icount_out0_carry__3_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(18),
I1 => \^load_reg_gen[0].load_reg_i\(19),
O => \icount_out0_carry__3_i_2__0_n_0\
);
\icount_out0_carry__3_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(17),
I1 => \^load_reg_gen[0].load_reg_i\(18),
O => \icount_out0_carry__3_i_3__0_n_0\
);
\icount_out0_carry__3_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(16),
I1 => \^load_reg_gen[0].load_reg_i\(17),
O => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1__0_n_0\,
S(2) => \icount_out0_carry__4_i_2__0_n_0\,
S(1) => \icount_out0_carry__4_i_3__0_n_0\,
S(0) => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__4_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(23),
I1 => \^load_reg_gen[0].load_reg_i\(24),
O => \icount_out0_carry__4_i_1__0_n_0\
);
\icount_out0_carry__4_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(22),
I1 => \^load_reg_gen[0].load_reg_i\(23),
O => \icount_out0_carry__4_i_2__0_n_0\
);
\icount_out0_carry__4_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(21),
I1 => \^load_reg_gen[0].load_reg_i\(22),
O => \icount_out0_carry__4_i_3__0_n_0\
);
\icount_out0_carry__4_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(20),
I1 => \^load_reg_gen[0].load_reg_i\(21),
O => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1__0_n_0\,
S(2) => \icount_out0_carry__5_i_2__0_n_0\,
S(1) => \icount_out0_carry__5_i_3__0_n_0\,
S(0) => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__5_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(27),
I1 => \^load_reg_gen[0].load_reg_i\(28),
O => \icount_out0_carry__5_i_1__0_n_0\
);
\icount_out0_carry__5_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(26),
I1 => \^load_reg_gen[0].load_reg_i\(27),
O => \icount_out0_carry__5_i_2__0_n_0\
);
\icount_out0_carry__5_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(25),
I1 => \^load_reg_gen[0].load_reg_i\(26),
O => \icount_out0_carry__5_i_3__0_n_0\
);
\icount_out0_carry__5_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(24),
I1 => \^load_reg_gen[0].load_reg_i\(25),
O => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^load_reg_gen[0].load_reg_i\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1__0_n_0\,
S(2) => \icount_out0_carry__6_i_2__0_n_0\,
S(1) => \icount_out0_carry__6_i_3__0_n_0\,
S(0) => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry__6_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(31),
O => \icount_out0_carry__6_i_1__0_n_0\
);
\icount_out0_carry__6_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(30),
I1 => \^load_reg_gen[0].load_reg_i\(31),
O => \icount_out0_carry__6_i_2__0_n_0\
);
\icount_out0_carry__6_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(29),
I1 => \^load_reg_gen[0].load_reg_i\(30),
O => \icount_out0_carry__6_i_3__0_n_0\
);
\icount_out0_carry__6_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(28),
I1 => \^load_reg_gen[0].load_reg_i\(29),
O => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(1),
O => \icount_out0_carry_i_1__0_n_0\
);
\icount_out0_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(3),
I1 => \^load_reg_gen[0].load_reg_i\(4),
O => \icount_out0_carry_i_2__0_n_0\
);
\icount_out0_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(2),
I1 => \^load_reg_gen[0].load_reg_i\(3),
O => \icount_out0_carry_i_3__0_n_0\
);
\icount_out0_carry_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(1),
I1 => \^load_reg_gen[0].load_reg_i\(2),
O => \icount_out0_carry_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
Bus_RNW_reg_reg : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]\ : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f : entity is "mux_onehot_f";
end zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f is
signal \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal cyout_1 : STD_LOGIC;
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
begin
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(31),
CO(0) => cyout_1,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[31]\,
S(0) => Bus_RNW_reg_reg
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(21),
CO(0) => \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[21]\,
S(0) => Bus_RNW_reg_reg_9
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(20),
CO(0) => \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[20]\,
S(0) => Bus_RNW_reg_reg_10
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(19),
CO(0) => \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[19]\,
S(0) => Bus_RNW_reg_reg_11
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(18),
CO(0) => \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[18]\,
S(0) => Bus_RNW_reg_reg_12
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(17),
CO(0) => \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[17]\,
S(0) => Bus_RNW_reg_reg_13
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(16),
CO(0) => \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[16]\,
S(0) => Bus_RNW_reg_reg_14
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(15),
CO(0) => \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[15]\,
S(0) => Bus_RNW_reg_reg_15
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(14),
CO(0) => \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[14]\,
S(0) => Bus_RNW_reg_reg_16
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(13),
CO(0) => \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[13]\,
S(0) => Bus_RNW_reg_reg_17
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(12),
CO(0) => \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[12]\,
S(0) => Bus_RNW_reg_reg_18
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(30),
CO(0) => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[30]\,
S(0) => Bus_RNW_reg_reg_0
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(11),
CO(0) => \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[11]\,
S(0) => \LOAD_REG_GEN[20].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(10),
CO(0) => \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[10]\,
S(0) => \LOAD_REG_GEN[21].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(9),
CO(0) => \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[9]\,
S(0) => \LOAD_REG_GEN[22].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(8),
CO(0) => \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[8]\,
S(0) => \LOAD_REG_GEN[23].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(7),
CO(0) => \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[7]\,
S(0) => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(6),
CO(0) => \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[6]\,
S(0) => \LOAD_REG_GEN[25].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(5),
CO(0) => \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[5]\,
S(0) => \LOAD_REG_GEN[26].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(4),
CO(0) => \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[4]\,
S(0) => \LOAD_REG_GEN[27].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(3),
CO(0) => \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[3]\,
S(0) => \LOAD_REG_GEN[28].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(2),
CO(0) => \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[2]\,
S(0) => \LOAD_REG_GEN[29].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(29),
CO(0) => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[29]\,
S(0) => Bus_RNW_reg_reg_1
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(1),
CO(0) => \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[1]\,
S(0) => \LOAD_REG_GEN[30].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(0),
CO(0) => \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[0]\,
S(0) => \LOAD_REG_GEN[31].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(28),
CO(0) => \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[28]\,
S(0) => Bus_RNW_reg_reg_2
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(27),
CO(0) => \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[27]\,
S(0) => Bus_RNW_reg_reg_3
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(26),
CO(0) => \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[26]\,
S(0) => Bus_RNW_reg_reg_4
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(25),
CO(0) => \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[25]\,
S(0) => Bus_RNW_reg_reg_5
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(24),
CO(0) => \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[24]\,
S(0) => Bus_RNW_reg_reg_6
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(23),
CO(0) => \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[23]\,
S(0) => Bus_RNW_reg_reg_7
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(22),
CO(0) => \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[22]\,
S(0) => Bus_RNW_reg_reg_8
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_pselect_f is
port (
ce_expnd_i_7 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_pselect_f : entity is "pselect_f";
end zqynq_lab_1_design_axi_timer_0_1_pselect_f;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_pselect_f is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_7
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\ is
port (
ce_expnd_i_5 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_5
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\ is
port (
ce_expnd_i_3 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\ is
port (
ce_expnd_i_2 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\ is
port (
ce_expnd_i_1 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(0),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\ is
port (
ce_expnd_i_0 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_address_decoder is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_2 : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\state1__2\ : in STD_LOGIC;
s_axi_arvalid_0 : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_rvalid_i_reg_3 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
bus2ip_rnw_i : in STD_LOGIC;
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_address_decoder : entity is "address_decoder";
end zqynq_lab_1_design_axi_timer_0_1_address_decoder;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\ : STD_LOGIC;
signal \^load_reg_gen[31].load_reg_i\ : STD_LOGIC;
signal \^tcsr0_generate[23].tcsr0_ff_i\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_5 : STD_LOGIC;
signal ce_expnd_i_6 : STD_LOGIC;
signal ce_expnd_i_7 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \eqOp__4\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_axi_arready_INST_0_i_4_n_0 : STD_LOGIC;
signal \^s_axi_rvalid_i_reg\ : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_1\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC;
signal s_axi_wready_INST_0_i_2_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[9].LOAD_REG_I_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of READ_DONE0_I_i_2 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of READ_DONE1_I_i_2 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[20].TCSR0_FF_I_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[21].TCSR0_FF_I_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[23].TCSR0_FF_I_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[24].TCSR0_FF_I_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[22].TCSR1_FF_I_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[23].TCSR1_FF_I_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[24].TCSR1_FF_I_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_3 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_2 : label is "soft_lutpair2";
begin
\LOAD_REG_GEN[31].LOAD_REG_I\ <= \^load_reg_gen[31].load_reg_i\;
\TCSR0_GENERATE[23].TCSR0_FF_I\ <= \^tcsr0_generate[23].tcsr0_ff_i\;
s_axi_arready <= \^s_axi_arready\;
s_axi_rvalid_i_reg <= \^s_axi_rvalid_i_reg\;
s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\;
s_axi_rvalid_i_reg_1 <= \^s_axi_rvalid_i_reg_1\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i,
I1 => Q,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^tcsr0_generate[23].tcsr0_ff_i\,
R => '0'
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(84),
O => \s_axi_rdata_i_reg[31]\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[0]_0\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(74),
O => \s_axi_rdata_i_reg[21]\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(73),
O => \s_axi_rdata_i_reg[20]\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(72),
O => \s_axi_rdata_i_reg[19]\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(71),
O => \s_axi_rdata_i_reg[18]\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(70),
O => \s_axi_rdata_i_reg[17]\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(69),
O => \s_axi_rdata_i_reg[16]\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(68),
O => \s_axi_rdata_i_reg[15]\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(67),
O => \s_axi_rdata_i_reg[14]\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(66),
O => \s_axi_rdata_i_reg[13]\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(65),
O => \s_axi_rdata_i_reg[12]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(83),
O => \s_axi_rdata_i_reg[30]\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0777FFFF"
)
port map (
I0 => read_Mux_In(64),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(87),
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[11]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(82),
O => \s_axi_rdata_i_reg[29]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(81),
O => \s_axi_rdata_i_reg[28]\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(80),
O => \s_axi_rdata_i_reg[27]\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(79),
O => \s_axi_rdata_i_reg[26]\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(78),
O => \s_axi_rdata_i_reg[25]\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(77),
O => \s_axi_rdata_i_reg[24]\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(76),
O => \s_axi_rdata_i_reg[23]\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(75),
O => \s_axi_rdata_i_reg[22]\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_7,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_6
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_6,
Q => \^load_reg_gen[31].load_reg_i\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_5,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
R => cs_ce_clr
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(31),
I1 => read_Mux_In(31),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => D_0
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(63),
O => D_1
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \bus2ip_wrce__0\(0)
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(21),
I1 => read_Mux_In(21),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[10].LOAD_REG_I\
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(21),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(53),
O => \LOAD_REG_GEN[10].LOAD_REG_I_0\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(20),
I1 => read_Mux_In(20),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[11].LOAD_REG_I\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(20),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(52),
O => \LOAD_REG_GEN[11].LOAD_REG_I_0\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(19),
I1 => read_Mux_In(19),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[12].LOAD_REG_I\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(19),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(51),
O => \LOAD_REG_GEN[12].LOAD_REG_I_0\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(18),
I1 => read_Mux_In(18),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[13].LOAD_REG_I\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(18),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(50),
O => \LOAD_REG_GEN[13].LOAD_REG_I_0\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(17),
I1 => read_Mux_In(17),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[14].LOAD_REG_I\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(17),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(49),
O => \LOAD_REG_GEN[14].LOAD_REG_I_0\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(16),
I1 => read_Mux_In(16),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[15].LOAD_REG_I\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(16),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(48),
O => \LOAD_REG_GEN[15].LOAD_REG_I_0\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(15),
I1 => read_Mux_In(15),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[16].LOAD_REG_I\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(15),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(47),
O => \LOAD_REG_GEN[16].LOAD_REG_I_0\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(14),
I1 => read_Mux_In(14),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[17].LOAD_REG_I\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(14),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(46),
O => \LOAD_REG_GEN[17].LOAD_REG_I_0\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(13),
I1 => read_Mux_In(13),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[18].LOAD_REG_I\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(13),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(45),
O => \LOAD_REG_GEN[18].LOAD_REG_I_0\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(12),
I1 => read_Mux_In(12),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[19].LOAD_REG_I\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(12),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(44),
O => \LOAD_REG_GEN[19].LOAD_REG_I_0\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(30),
I1 => read_Mux_In(30),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[1].LOAD_REG_I\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(30),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(62),
O => \LOAD_REG_GEN[1].LOAD_REG_I_0\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(11),
I1 => read_Mux_In(11),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[20].LOAD_REG_I\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(11),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(43),
O => \LOAD_REG_GEN[20].LOAD_REG_I_0\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(10),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[21].LOAD_REG_I\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(10),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(42),
O => \LOAD_REG_GEN[21].LOAD_REG_I_0\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(9),
I1 => read_Mux_In(9),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[22].LOAD_REG_I\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(9),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(41),
O => \LOAD_REG_GEN[22].LOAD_REG_I_0\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(8),
I1 => read_Mux_In(8),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[23].LOAD_REG_I\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(8),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(40),
O => \LOAD_REG_GEN[23].LOAD_REG_I_0\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(7),
I1 => read_Mux_In(7),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(39),
O => \LOAD_REG_GEN[24].LOAD_REG_I_0\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(6),
I1 => read_Mux_In(6),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[25].LOAD_REG_I\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(38),
O => \LOAD_REG_GEN[25].LOAD_REG_I_0\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(5),
I1 => read_Mux_In(5),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[26].LOAD_REG_I\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(37),
O => \LOAD_REG_GEN[26].LOAD_REG_I_0\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(4),
I1 => read_Mux_In(4),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[27].LOAD_REG_I\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(36),
O => \LOAD_REG_GEN[27].LOAD_REG_I_0\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(3),
I1 => read_Mux_In(3),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[28].LOAD_REG_I\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(35),
O => \LOAD_REG_GEN[28].LOAD_REG_I_0\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(2),
I1 => read_Mux_In(2),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[29].LOAD_REG_I\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(34),
O => \LOAD_REG_GEN[29].LOAD_REG_I_0\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(29),
I1 => read_Mux_In(29),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[2].LOAD_REG_I\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(29),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(61),
O => \LOAD_REG_GEN[2].LOAD_REG_I_0\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(1),
I1 => read_Mux_In(1),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[30].LOAD_REG_I\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(33),
O => \LOAD_REG_GEN[30].LOAD_REG_I_0\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(0),
I1 => read_Mux_In(0),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[31].LOAD_REG_I_0\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(32),
O => \LOAD_REG_GEN[31].LOAD_REG_I_1\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(28),
I1 => read_Mux_In(28),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[3].LOAD_REG_I\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(28),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(60),
O => \LOAD_REG_GEN[3].LOAD_REG_I_0\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(27),
I1 => read_Mux_In(27),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[4].LOAD_REG_I\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(27),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(59),
O => \LOAD_REG_GEN[4].LOAD_REG_I_0\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(26),
I1 => read_Mux_In(26),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[5].LOAD_REG_I\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(26),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(58),
O => \LOAD_REG_GEN[5].LOAD_REG_I_0\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(25),
I1 => read_Mux_In(25),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[6].LOAD_REG_I\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(25),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(57),
O => \LOAD_REG_GEN[6].LOAD_REG_I_0\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(24),
I1 => read_Mux_In(24),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[7].LOAD_REG_I\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(24),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(56),
O => \LOAD_REG_GEN[7].LOAD_REG_I_0\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(23),
I1 => read_Mux_In(23),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[8].LOAD_REG_I\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(23),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(55),
O => \LOAD_REG_GEN[8].LOAD_REG_I_0\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(22),
I1 => read_Mux_In(22),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[9].LOAD_REG_I\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(22),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(54),
O => \LOAD_REG_GEN[9].LOAD_REG_I_0\
);
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.zqynq_lab_1_design_axi_timer_0_1_pselect_f
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_7 => ce_expnd_i_7
);
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_5 => ce_expnd_i_5
);
\MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_3 => ce_expnd_i_3
);
\MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_2 => ce_expnd_i_2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_1 => ce_expnd_i_1
);
\MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_0 => ce_expnd_i_0
);
READ_DONE0_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => D_2,
O => READ_DONE0_I
);
READ_DONE1_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => read_done1,
O => READ_DONE1_I
);
\TCSR0_GENERATE[20].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => bus2ip_wrce(1)
);
\TCSR0_GENERATE[21].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"32"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
O => pair0_Select
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR0_GENERATE[23].TCSR0_FF_I_0\
);
\TCSR0_GENERATE[24].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFEEEAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(86),
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => s_axi_wdata(7),
O => \TCSR0_GENERATE[24].TCSR0_FF_I\
);
\TCSR1_GENERATE[22].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => bus2ip_wrce(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR1_GENERATE[23].TCSR1_FF_I\
);
\TCSR1_GENERATE[24].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFEEEAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(85),
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I4 => s_axi_wdata(7),
O => \TCSR1_GENERATE[24].TCSR1_FF_I\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEFFFEFFFEFF"
)
port map (
I0 => \^s_axi_rvalid_i_reg\,
I1 => \^s_axi_rvalid_i_reg_0\,
I2 => \^s_axi_rvalid_i_reg_1\,
I3 => s_axi_arready_INST_0_i_4_n_0,
I4 => is_read,
I5 => \eqOp__4\,
O => \^s_axi_arready\
);
s_axi_arready_INST_0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg\
);
s_axi_arready_INST_0_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg_0\
);
s_axi_arready_INST_0_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg_1\
);
s_axi_arready_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF01FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => s_axi_arready_INST_0_i_4_n_0
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => \state_reg[1]\(1),
I2 => \state_reg[1]\(0),
I3 => s_axi_bready,
I4 => s_axi_bvalid_i_reg_0,
O => s_axi_bvalid_i_reg
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => s_axi_rready,
I4 => s_axi_rvalid_i_reg_3,
O => s_axi_rvalid_i_reg_2
);
s_axi_wready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"F777"
)
port map (
I0 => s_axi_wready_INST_0_i_1_n_0,
I1 => s_axi_wready_INST_0_i_2_n_0,
I2 => is_write_reg,
I3 => \eqOp__4\,
O => \^s_axi_wready\
);
s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F0F1"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => s_axi_wready_INST_0_i_1_n_0
);
s_axi_wready_INST_0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00FF01"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => s_axi_wready_INST_0_i_2_n_0
);
s_axi_wready_INST_0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(4),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(2),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(3),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1),
O => \eqOp__4\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => \state_reg[1]\(0),
I2 => s_axi_arvalid,
I3 => \state_reg[1]\(1),
I4 => \^s_axi_wready\,
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => s_axi_arvalid_0,
I2 => \state_reg[1]\(1),
I3 => \state_reg[1]\(0),
I4 => \^s_axi_arready\,
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_count_module is
port (
\INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC_VECTOR ( 52 downto 0 );
read_Mux_In : out STD_LOGIC_VECTOR ( 10 downto 0 );
generateOutPre0_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
\TCSR0_GENERATE[27].TCSR0_FF_I\ : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_count_module : entity is "count_module";
end zqynq_lab_1_design_axi_timer_0_1_count_module;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_count_module is
signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC_VECTOR ( 52 downto 0 );
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
\INFERRED_GEN.icount_out_reg[31]\(52 downto 0) <= \^inferred_gen.icount_out_reg[31]\(52 downto 0);
read_Mux_In(10 downto 0) <= \^read_mux_in\(10 downto 0);
COUNTER_I: entity work.zqynq_lab_1_design_axi_timer_0_1_counter_f_3
port map (
E(0) => E(0),
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) => \^inferred_gen.icount_out_reg[31]\(31 downto 0),
\LOAD_REG_GEN[0].LOAD_REG_I_0\(20 downto 0) => \^inferred_gen.icount_out_reg[31]\(52 downto 32),
Q(0) => Q(0),
S(0) => S(0),
counter_TC(0) => counter_TC(0),
generateOutPre0_reg => generateOutPre0_reg,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(10 downto 0) => \^read_mux_in\(10 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => D_1,
Q => \^inferred_gen.icount_out_reg[31]\(52),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
Q => \^inferred_gen.icount_out_reg[31]\(42),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
Q => \^inferred_gen.icount_out_reg[31]\(41),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
Q => \^inferred_gen.icount_out_reg[31]\(40),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
Q => \^inferred_gen.icount_out_reg[31]\(39),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
Q => \^inferred_gen.icount_out_reg[31]\(38),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
Q => \^inferred_gen.icount_out_reg[31]\(37),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
Q => \^inferred_gen.icount_out_reg[31]\(36),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
Q => \^inferred_gen.icount_out_reg[31]\(35),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
Q => \^inferred_gen.icount_out_reg[31]\(34),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
Q => \^inferred_gen.icount_out_reg[31]\(33),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^inferred_gen.icount_out_reg[31]\(51),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
Q => \^inferred_gen.icount_out_reg[31]\(32),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
Q => \^read_mux_in\(10),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
Q => \^read_mux_in\(9),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
Q => \^read_mux_in\(8),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
Q => \^read_mux_in\(7),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
Q => \^read_mux_in\(6),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
Q => \^read_mux_in\(5),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
Q => \^read_mux_in\(4),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
Q => \^read_mux_in\(3),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
Q => \^read_mux_in\(2),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
Q => \^inferred_gen.icount_out_reg[31]\(50),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
Q => \^read_mux_in\(1),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
Q => \^read_mux_in\(0),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
Q => \^inferred_gen.icount_out_reg[31]\(49),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
Q => \^inferred_gen.icount_out_reg[31]\(48),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
Q => \^inferred_gen.icount_out_reg[31]\(47),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
Q => \^inferred_gen.icount_out_reg[31]\(46),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
Q => \^inferred_gen.icount_out_reg[31]\(45),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
Q => \^inferred_gen.icount_out_reg[31]\(44),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
Q => \^inferred_gen.icount_out_reg[31]\(43),
R => s_axi_aresetn_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_count_module_0 is
port (
\INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
generateOutPre1_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
D_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_count_module_0 : entity is "count_module";
end zqynq_lab_1_design_axi_timer_0_1_count_module_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_count_module_0 is
signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 96 to 127 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
\INFERRED_GEN.icount_out_reg[31]\ <= \^inferred_gen.icount_out_reg[31]\;
COUNTER_I: entity work.zqynq_lab_1_design_axi_timer_0_1_counter_f
port map (
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
\INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0),
Q(31 downto 0) => Q(31 downto 0),
S(0) => S(0),
SR(0) => \^inferred_gen.icount_out_reg[31]\,
counter_TC(0) => counter_TC(0),
\counter_TC_Reg_reg[1]\(0) => \counter_TC_Reg_reg[1]\(0),
generateOutPre1_reg => generateOutPre1_reg,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(31) => read_Mux_In(96),
read_Mux_In(30) => read_Mux_In(97),
read_Mux_In(29) => read_Mux_In(98),
read_Mux_In(28) => read_Mux_In(99),
read_Mux_In(27) => read_Mux_In(100),
read_Mux_In(26) => read_Mux_In(101),
read_Mux_In(25) => read_Mux_In(102),
read_Mux_In(24) => read_Mux_In(103),
read_Mux_In(23) => read_Mux_In(104),
read_Mux_In(22) => read_Mux_In(105),
read_Mux_In(21) => read_Mux_In(106),
read_Mux_In(20) => read_Mux_In(107),
read_Mux_In(19) => read_Mux_In(108),
read_Mux_In(18) => read_Mux_In(109),
read_Mux_In(17) => read_Mux_In(110),
read_Mux_In(16) => read_Mux_In(111),
read_Mux_In(15) => read_Mux_In(112),
read_Mux_In(14) => read_Mux_In(113),
read_Mux_In(13) => read_Mux_In(114),
read_Mux_In(12) => read_Mux_In(115),
read_Mux_In(11) => read_Mux_In(116),
read_Mux_In(10) => read_Mux_In(117),
read_Mux_In(9) => read_Mux_In(118),
read_Mux_In(8) => read_Mux_In(119),
read_Mux_In(7) => read_Mux_In(120),
read_Mux_In(6) => read_Mux_In(121),
read_Mux_In(5) => read_Mux_In(122),
read_Mux_In(4) => read_Mux_In(123),
read_Mux_In(3) => read_Mux_In(124),
read_Mux_In(2) => read_Mux_In(125),
read_Mux_In(1) => read_Mux_In(126),
read_Mux_In(0) => read_Mux_In(127),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]\,
\s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]\,
\s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]\,
\s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]\,
\s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]\,
\s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]\,
\s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]\,
\s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]\,
\s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]\,
\s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]\,
\s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]\,
\s_axi_rdata_i_reg[1]\ => \s_axi_rdata_i_reg[1]\,
\s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]\,
\s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]\,
\s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]\,
\s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]\,
\s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]\,
\s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]\,
\s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]\,
\s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]\,
\s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]\,
\s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]\,
\s_axi_rdata_i_reg[2]\ => \s_axi_rdata_i_reg[2]\,
\s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]\,
\s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]\,
\s_axi_rdata_i_reg[3]\ => \s_axi_rdata_i_reg[3]\,
\s_axi_rdata_i_reg[4]\ => \s_axi_rdata_i_reg[4]\,
\s_axi_rdata_i_reg[5]\ => \s_axi_rdata_i_reg[5]\,
\s_axi_rdata_i_reg[6]\ => \s_axi_rdata_i_reg[6]\,
\s_axi_rdata_i_reg[7]\ => \s_axi_rdata_i_reg[7]\,
\s_axi_rdata_i_reg[8]\ => \s_axi_rdata_i_reg[8]\,
\s_axi_rdata_i_reg[9]\ => \s_axi_rdata_i_reg[9]\
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => D_2,
Q => read_Mux_In(96),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[21]\,
Q => read_Mux_In(106),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[20]\,
Q => read_Mux_In(107),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[19]\,
Q => read_Mux_In(108),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[18]\,
Q => read_Mux_In(109),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[17]\,
Q => read_Mux_In(110),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[16]\,
Q => read_Mux_In(111),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[15]\,
Q => read_Mux_In(112),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[14]\,
Q => read_Mux_In(113),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[13]\,
Q => read_Mux_In(114),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[12]\,
Q => read_Mux_In(115),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[30]\,
Q => read_Mux_In(97),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[11]\,
Q => read_Mux_In(116),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[10]\,
Q => read_Mux_In(117),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[9]\,
Q => read_Mux_In(118),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[8]\,
Q => read_Mux_In(119),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[7]\,
Q => read_Mux_In(120),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[6]\,
Q => read_Mux_In(121),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[5]\,
Q => read_Mux_In(122),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[4]\,
Q => read_Mux_In(123),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[3]\,
Q => read_Mux_In(124),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[2]\,
Q => read_Mux_In(125),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[29]\,
Q => read_Mux_In(98),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[1]\,
Q => read_Mux_In(126),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[0]\,
Q => read_Mux_In(127),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[28]\,
Q => read_Mux_In(99),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[27]\,
Q => read_Mux_In(100),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[26]\,
Q => read_Mux_In(101),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[25]\,
Q => read_Mux_In(102),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[24]\,
Q => read_Mux_In(103),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[23]\,
Q => read_Mux_In(104),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[22]\,
Q => read_Mux_In(105),
R => \^inferred_gen.icount_out_reg[31]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_timer_control is
port (
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
load_Counter_Reg : out STD_LOGIC_VECTOR ( 0 to 1 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
R : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
PWM_FF_I : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[32]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[32]_0\ : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
\LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I_1\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 );
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
pwm0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_timer_control : entity is "timer_control";
end zqynq_lab_1_design_axi_timer_0_1_timer_control;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_timer_control is
signal \^d_0\ : STD_LOGIC;
signal GenerateOut00 : STD_LOGIC;
signal GenerateOut10 : STD_LOGIC;
signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC;
signal Interrupt0 : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\ : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\ : STD_LOGIC;
signal Load_Counter_Reg028_out : STD_LOGIC;
signal Load_Counter_Reg030_out : STD_LOGIC;
signal Load_Counter_Reg031_out : STD_LOGIC;
signal \Load_Counter_Reg0__0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal READ_DONE0_I_i_3_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_1_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_3_n_0 : STD_LOGIC;
signal R_0 : STD_LOGIC;
signal \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\ : STD_LOGIC;
signal \^tcsr0_generate[24].tcsr0_ff_i_0\ : STD_LOGIC;
signal \TCSR0_Set2__0\ : STD_LOGIC;
signal \^tcsr1_generate[23].tcsr1_ff_i_0\ : STD_LOGIC;
signal \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\ : STD_LOGIC;
signal captureTrig0_d : STD_LOGIC;
signal captureTrig0_d0 : STD_LOGIC;
signal captureTrig0_d2 : STD_LOGIC;
signal captureTrig0_pulse_d1 : STD_LOGIC;
signal captureTrig0_pulse_d1_i_1_n_0 : STD_LOGIC;
signal captureTrig0_pulse_d2 : STD_LOGIC;
signal captureTrig1_d : STD_LOGIC;
signal captureTrig1_d0 : STD_LOGIC;
signal captureTrig1_d2 : STD_LOGIC;
signal counter_TC_Reg2 : STD_LOGIC;
signal generateOutPre0 : STD_LOGIC;
signal generateOutPre1 : STD_LOGIC;
signal \^generateout0\ : STD_LOGIC;
signal \^generateout1\ : STD_LOGIC;
signal p_33_in : STD_LOGIC;
signal p_38_in : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 21 to 63 );
signal \^read_done1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of GenerateOut0_i_2 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of GenerateOut1_i_1 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_5\ : label is "soft_lutpair53";
attribute BOX_TYPE : string;
attribute BOX_TYPE of READ_DONE0_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of READ_DONE0_I : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of READ_DONE0_I : label is "1'b0";
attribute BOX_TYPE of READ_DONE1_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED of READ_DONE1_I : label is "1'b0";
attribute IS_S_INVERTED of READ_DONE1_I : label is "1'b0";
attribute SOFT_HLUTNM of READ_DONE1_I_i_3 : label is "soft_lutpair52";
attribute BOX_TYPE of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute SOFT_HLUTNM of captureTrig0_pulse_d1_i_1 : label is "soft_lutpair52";
begin
D_0 <= \^d_0\;
\INFERRED_GEN.icount_out_reg[0]\ <= \^inferred_gen.icount_out_reg[0]\;
Q(1 downto 0) <= \^q\(1 downto 0);
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ <= \^tcsr0_generate[24].tcsr0_ff_i_0\;
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ <= \^tcsr1_generate[23].tcsr1_ff_i_0\;
generateout0 <= \^generateout0\;
generateout1 <= \^generateout1\;
read_done1 <= \^read_done1\;
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(10),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(21),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(53),
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(9),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(22),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(54),
O => \s_axi_rdata_i_reg[9]\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(8),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(23),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(55),
O => \s_axi_rdata_i_reg[8]\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(7),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => \^tcsr0_generate[24].tcsr0_ff_i_0\,
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => \^tcsr1_generate[23].tcsr1_ff_i_0\,
O => \s_axi_rdata_i_reg[7]\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(6),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(25),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(57),
O => \s_axi_rdata_i_reg[6]\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(5),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(26),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(58),
O => \s_axi_rdata_i_reg[5]\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(4),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(27),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(59),
O => \s_axi_rdata_i_reg[4]\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(3),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(28),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(60),
O => \s_axi_rdata_i_reg[3]\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(2),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(29),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(61),
O => \s_axi_rdata_i_reg[2]\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(1),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(30),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(62),
O => \s_axi_rdata_i_reg[1]\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(0),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(31),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(63),
O => \s_axi_rdata_i_reg[0]\
);
GenerateOut0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"B800"
)
port map (
I0 => generateOutPre1,
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => generateOutPre0,
I3 => read_Mux_In(29),
O => GenerateOut00
);
GenerateOut0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut00,
Q => \^generateout0\,
R => SR(0)
);
GenerateOut1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8F808080"
)
port map (
I0 => generateOutPre0,
I1 => read_Mux_In(29),
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => read_Mux_In(61),
I4 => generateOutPre1,
O => GenerateOut10
);
GenerateOut1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut10,
Q => \^generateout1\,
R => SR(0)
);
\INFERRED_GEN.icount_out[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAFEAAAA"
)
port map (
I0 => read_Mux_In(26),
I1 => read_Mux_In(22),
I2 => read_Mux_In(27),
I3 => read_Mux_In(31),
I4 => counter_TC(0),
O => Load_Counter_Reg030_out
);
\INFERRED_GEN.icount_out[31]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAEAAAAAAAEA"
)
port map (
I0 => read_Mux_In(58),
I1 => counter_TC(1),
I2 => read_Mux_In(59),
I3 => read_Mux_In(63),
I4 => read_Mux_In(54),
I5 => counter_TC(0),
O => \Load_Counter_Reg0__0\
);
\INFERRED_GEN.icount_out[31]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(58),
O => Load_Counter_Reg028_out
);
\INFERRED_GEN.icount_out[31]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(26),
O => Load_Counter_Reg031_out
);
\INFERRED_GEN.icount_out[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40FFFFFF400000"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(58),
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => \Load_Counter_Reg0__0\,
O => load_Counter_Reg(1)
);
\INFERRED_GEN.icount_out[31]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40FFFFFF400000"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(26),
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => Load_Counter_Reg030_out,
O => load_Counter_Reg(0)
);
INPUT_DOUBLE_REGS: entity work.zqynq_lab_1_design_axi_timer_0_1_cdc_sync
port map (
captureTrig0_d0 => captureTrig0_d0,
capturetrig0 => capturetrig0,
read_Mux_In(0) => read_Mux_In(28),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS2: entity work.zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1
port map (
captureTrig1_d0 => captureTrig1_d0,
capturetrig1 => capturetrig1,
read_Mux_In(0) => read_Mux_In(60),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS3: entity work.zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2
port map (
E(0) => E(0),
\INFERRED_GEN.icount_out_reg[0]\(0) => \INFERRED_GEN.icount_out_reg[0]_0\(0),
\INFERRED_GEN.icount_out_reg[1]\(1 downto 0) => \INFERRED_GEN.icount_out_reg[1]\(1 downto 0),
\INFERRED_GEN.icount_out_reg[4]\(0) => \INFERRED_GEN.icount_out_reg[4]\(0),
Load_Counter_Reg028_out => Load_Counter_Reg028_out,
Load_Counter_Reg030_out => Load_Counter_Reg030_out,
Load_Counter_Reg031_out => Load_Counter_Reg031_out,
\Load_Counter_Reg0__0\ => \Load_Counter_Reg0__0\,
S(0) => S(0),
\TCSR0_GENERATE[20].TCSR0_FF_I\ => \^inferred_gen.icount_out_reg[0]\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \^tcsr0_generate[24].tcsr0_ff_i_0\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \^tcsr1_generate[23].tcsr1_ff_i_0\,
counter_TC(0 to 1) => counter_TC(0 to 1),
freeze => freeze,
generateOutPre0 => generateOutPre0,
read_Mux_In(7) => read_Mux_In(22),
read_Mux_In(6) => read_Mux_In(27),
read_Mux_In(5) => read_Mux_In(30),
read_Mux_In(4) => read_Mux_In(31),
read_Mux_In(3) => read_Mux_In(54),
read_Mux_In(2) => read_Mux_In(59),
read_Mux_In(1) => read_Mux_In(62),
read_Mux_In(0) => read_Mux_In(63),
s_axi_aclk => s_axi_aclk
);
Interrupt_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => read_Mux_In(25),
I1 => read_Mux_In(23),
I2 => read_Mux_In(57),
I3 => read_Mux_In(55),
O => Interrupt0
);
Interrupt_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Interrupt0,
Q => interrupt,
R => SR(0)
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000FFFFE000E000"
)
port map (
I0 => read_Mux_In(27),
I1 => \^d_0\,
I2 => R_0,
I3 => read_Mux_In(31),
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
O => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF8080808"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\,
I1 => p_38_in,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\,
I4 => p_33_in,
I5 => \bus2ip_wrce__0\(0),
O => \LOAD_REG_GEN[24].LOAD_REG_I_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => read_Mux_In(59),
I1 => \^read_done1\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F40400000000"
)
port map (
I0 => captureTrig1_d2,
I1 => captureTrig1_d,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => READ_DONE1_I_i_3_n_0,
I4 => READ_DONE0_I_i_3_n_0,
I5 => read_Mux_In(63),
O => p_38_in
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => read_Mux_In(27),
I1 => \^read_done1\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F40400000000"
)
port map (
I0 => captureTrig1_d2,
I1 => captureTrig1_d,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => READ_DONE1_I_i_3_n_0,
I4 => READ_DONE0_I_i_3_n_0,
I5 => read_Mux_In(31),
O => p_33_in
);
PWM_FF_I_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \^generateout1\,
I1 => read_Mux_In(22),
I2 => read_Mux_In(54),
O => R
);
PWM_FF_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^generateout0\,
I1 => pwm0,
O => PWM_FF_I
);
READ_DONE0_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^d_0\,
R => R_0
);
READ_DONE0_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AA00AA00ABFFAA00"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => \^q\(1),
I2 => counter_TC(0),
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => captureTrig0_d,
I5 => captureTrig0_d2,
O => R_0
);
READ_DONE0_I_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => counter_TC_Reg2,
I1 => captureTrig0_pulse_d2,
I2 => captureTrig0_pulse_d1,
O => READ_DONE0_I_i_3_n_0
);
READ_DONE1_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
Q => \^read_done1\,
R => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"E0E0EFE0"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => READ_DONE1_I_i_3_n_0,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => captureTrig1_d,
I4 => captureTrig1_d2,
O => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => captureTrig0_d2,
I1 => captureTrig0_d,
I2 => counter_TC(0),
I3 => \^q\(1),
O => READ_DONE1_I_i_3_n_0
);
\TCSR0_GENERATE[20].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(9),
Q => \^inferred_gen.icount_out_reg[0]\,
R => SR(0)
);
\TCSR0_GENERATE[21].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => read_Mux_In(21),
R => SR(0)
);
\TCSR0_GENERATE[22].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(7),
Q => read_Mux_In(22),
R => SR(0)
);
\TCSR0_GENERATE[23].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\,
Q => read_Mux_In(23),
R => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF3F2F0F2"
)
port map (
I0 => generateOutPre0,
I1 => read_Mux_In(31),
I2 => \TCSR0_Set2__0\,
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => generateOutPre1,
I5 => read_Mux_In(23),
O => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8AAA80000000000"
)
port map (
I0 => read_Mux_In(31),
I1 => READ_DONE0_I_i_3_n_0,
I2 => READ_DONE1_I_i_3_n_0,
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => captureTrig0_pulse_d1_i_1_n_0,
I5 => \^tcsr0_generate[24].tcsr0_ff_i_0\,
O => \TCSR0_Set2__0\
);
\TCSR0_GENERATE[24].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR0_GENERATE[24].TCSR0_FF_I_1\,
Q => \^tcsr0_generate[24].tcsr0_ff_i_0\,
R => SR(0)
);
\TCSR0_GENERATE[25].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(6),
Q => read_Mux_In(25),
R => SR(0)
);
\TCSR0_GENERATE[26].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(5),
Q => read_Mux_In(26),
R => SR(0)
);
\TCSR0_GENERATE[27].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(4),
Q => read_Mux_In(27),
R => SR(0)
);
\TCSR0_GENERATE[28].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(3),
Q => read_Mux_In(28),
R => SR(0)
);
\TCSR0_GENERATE[29].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(2),
Q => read_Mux_In(29),
R => SR(0)
);
\TCSR0_GENERATE[30].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(1),
Q => read_Mux_In(30),
R => SR(0)
);
\TCSR0_GENERATE[31].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(0),
Q => read_Mux_In(31),
R => SR(0)
);
\TCSR1_GENERATE[21].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => read_Mux_In(53),
R => SR(0)
);
\TCSR1_GENERATE[22].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(7),
Q => read_Mux_In(54),
R => SR(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\,
Q => read_Mux_In(55),
R => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00008F80"
)
port map (
I0 => \^tcsr1_generate[23].tcsr1_ff_i_0\,
I1 => READ_DONE1_I_i_1_n_0,
I2 => read_Mux_In(63),
I3 => generateOutPre1,
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => read_Mux_In(55),
O => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\
);
\TCSR1_GENERATE[24].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR1_GENERATE[24].TCSR1_FF_I_0\,
Q => \^tcsr1_generate[23].tcsr1_ff_i_0\,
R => SR(0)
);
\TCSR1_GENERATE[25].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(6),
Q => read_Mux_In(57),
R => SR(0)
);
\TCSR1_GENERATE[26].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(5),
Q => read_Mux_In(58),
R => SR(0)
);
\TCSR1_GENERATE[27].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(4),
Q => read_Mux_In(59),
R => SR(0)
);
\TCSR1_GENERATE[28].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(3),
Q => read_Mux_In(60),
R => SR(0)
);
\TCSR1_GENERATE[29].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(2),
Q => read_Mux_In(61),
R => SR(0)
);
\TCSR1_GENERATE[30].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(1),
Q => read_Mux_In(62),
R => SR(0)
);
\TCSR1_GENERATE[31].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(0),
Q => read_Mux_In(63),
R => SR(0)
);
captureTrig0_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d,
Q => captureTrig0_d2,
R => SR(0)
);
captureTrig0_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d0,
Q => captureTrig0_d,
R => SR(0)
);
captureTrig0_pulse_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => captureTrig0_d,
I1 => captureTrig0_d2,
O => captureTrig0_pulse_d1_i_1_n_0
);
captureTrig0_pulse_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_pulse_d1_i_1_n_0,
Q => captureTrig0_pulse_d1,
R => SR(0)
);
captureTrig0_pulse_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_pulse_d1,
Q => captureTrig0_pulse_d2,
R => SR(0)
);
captureTrig1_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d,
Q => captureTrig1_d2,
R => SR(0)
);
captureTrig1_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d0,
Q => captureTrig1_d,
R => SR(0)
);
counter_TC_Reg2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(1),
Q => counter_TC_Reg2,
R => SR(0)
);
\counter_TC_Reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(0),
Q => \^q\(1),
R => SR(0)
);
\counter_TC_Reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(1),
Q => \^q\(0),
R => SR(0)
);
generateOutPre0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out_reg[32]_0\,
Q => generateOutPre0,
R => SR(0)
);
generateOutPre1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out_reg[32]\,
Q => generateOutPre1,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_slave_attachment is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[12]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[11]_0\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_2 : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_1\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_slave_attachment : entity is "slave_attachment";
end zqynq_lab_1_design_axi_timer_0_1_slave_attachment;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal I_DECODER_n_100 : STD_LOGIC;
signal I_DECODER_n_101 : STD_LOGIC;
signal I_DECODER_n_25 : STD_LOGIC;
signal I_DECODER_n_26 : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 2 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rst : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair16";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
O => plusOp(4)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
O => plusOp(5)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(4),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(5),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
R => clear
);
I_DECODER: entity work.zqynq_lab_1_design_axi_timer_0_1_address_decoder
port map (
D(1) => I_DECODER_n_25,
D(0) => I_DECODER_n_26,
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5 downto 0),
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_1\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
Q => start2,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I_0\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
\bus2ip_addr_i_reg[4]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[4]\(1) => bus2ip_addr(1),
\bus2ip_addr_i_reg[4]\(0) => bus2ip_addr(2),
bus2ip_rnw_i => bus2ip_rnw_i,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
is_read => is_read,
is_write_reg => is_write_reg_n_0,
pair0_Select => pair0_Select,
read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_arvalid_0 => \state[1]_i_3_n_0\,
s_axi_bready => s_axi_bready,
s_axi_bvalid_i_reg => I_DECODER_n_101,
s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\,
\s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]_1\,
\s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]_0\,
\s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]_0\,
\s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]_0\,
\s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]_0\,
\s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]_0\,
\s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]_0\,
\s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]_0\,
\s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]_0\,
\s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]_0\,
\s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]_0\,
\s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]_0\,
\s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]_0\,
\s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]_0\,
\s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]_0\,
\s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]_0\,
\s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]_0\,
\s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]_0\,
\s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]_0\,
\s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]_0\,
\s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]_0\,
\s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]_0\,
\s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]_0\,
s_axi_rready => s_axi_rready,
s_axi_rvalid_i_reg => s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg_1,
s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_2,
s_axi_rvalid_i_reg_2 => I_DECODER_n_100,
s_axi_rvalid_i_reg_3 => \^s_axi_rvalid\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
\state1__2\ => \state1__2\,
\state_reg[1]\(1 downto 0) => state(1 downto 0)
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(0),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(1),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(2),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[4]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(2),
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(1),
R => rst
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[4]_i_2_n_0\,
Q => bus2ip_addr(0),
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => bus2ip_rnw_i,
R => rst
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => rst
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset,
Q => rst,
R => '0'
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_101,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[31]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(0),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(10),
Q => s_axi_rdata(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(11),
Q => s_axi_rdata(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(12),
Q => s_axi_rdata(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(13),
Q => s_axi_rdata(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(14),
Q => s_axi_rdata(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(15),
Q => s_axi_rdata(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(16),
Q => s_axi_rdata(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(17),
Q => s_axi_rdata(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(18),
Q => s_axi_rdata(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(19),
Q => s_axi_rdata(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(1),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(20),
Q => s_axi_rdata(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(21),
Q => s_axi_rdata(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(22),
Q => s_axi_rdata(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(23),
Q => s_axi_rdata(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(24),
Q => s_axi_rdata(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(25),
Q => s_axi_rdata(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(26),
Q => s_axi_rdata(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(27),
Q => s_axi_rdata(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(28),
Q => s_axi_rdata(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(29),
Q => s_axi_rdata(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(2),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(30),
Q => s_axi_rdata(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(31),
Q => s_axi_rdata(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(3),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(4),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(5),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(6),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(7),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(8),
Q => s_axi_rdata(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(9),
Q => s_axi_rdata(9),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_100,
Q => \^s_axi_rvalid\,
R => rst
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_26,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_25,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_tc_core is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 87 downto 0 );
bus2ip_reset : out STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
D_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]_0\ : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_tc_core : entity is "tc_core";
end zqynq_lab_1_design_axi_timer_0_1_tc_core;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_tc_core is
signal COUNTER_0_I_n_64 : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_33\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_34\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_35\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_36\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_37\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_38\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_39\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_40\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_41\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_42\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_43\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_44\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_45\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_46\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_47\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_48\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_49\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_50\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_51\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_52\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_53\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_54\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_55\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_56\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_57\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_58\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_59\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_60\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_61\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_62\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_63\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_64\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_65\ : STD_LOGIC;
signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC_VECTOR ( 87 downto 0 );
signal R : STD_LOGIC;
signal TIMER_CONTROL_I_n_12 : STD_LOGIC;
signal TIMER_CONTROL_I_n_13 : STD_LOGIC;
signal TIMER_CONTROL_I_n_14 : STD_LOGIC;
signal TIMER_CONTROL_I_n_15 : STD_LOGIC;
signal TIMER_CONTROL_I_n_16 : STD_LOGIC;
signal TIMER_CONTROL_I_n_17 : STD_LOGIC;
signal TIMER_CONTROL_I_n_18 : STD_LOGIC;
signal TIMER_CONTROL_I_n_19 : STD_LOGIC;
signal TIMER_CONTROL_I_n_20 : STD_LOGIC;
signal TIMER_CONTROL_I_n_21 : STD_LOGIC;
signal TIMER_CONTROL_I_n_22 : STD_LOGIC;
signal TIMER_CONTROL_I_n_24 : STD_LOGIC;
signal TIMER_CONTROL_I_n_25 : STD_LOGIC;
signal TIMER_CONTROL_I_n_26 : STD_LOGIC;
signal TIMER_CONTROL_I_n_27 : STD_LOGIC;
signal TIMER_CONTROL_I_n_28 : STD_LOGIC;
signal TIMER_CONTROL_I_n_29 : STD_LOGIC;
signal TIMER_CONTROL_I_n_3 : STD_LOGIC;
signal TIMER_CONTROL_I_n_30 : STD_LOGIC;
signal TIMER_CONTROL_I_n_4 : STD_LOGIC;
signal \^bus2ip_reset\ : STD_LOGIC;
signal counter_TC : STD_LOGIC_VECTOR ( 0 to 1 );
signal load_Counter_Reg : STD_LOGIC_VECTOR ( 0 to 1 );
signal \^pwm0\ : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 85 to 95 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of PWM_FF_I : label is "PRIMITIVE";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of PWM_FF_I : label is "1'b0";
begin
\INFERRED_GEN.icount_out_reg[0]\(87 downto 0) <= \^inferred_gen.icount_out_reg[0]\(87 downto 0);
bus2ip_reset <= \^bus2ip_reset\;
pwm0 <= \^pwm0\;
COUNTER_0_I: entity work.zqynq_lab_1_design_axi_timer_0_1_count_module
port map (
D_1 => D_1,
E(0) => TIMER_CONTROL_I_n_24,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
\INFERRED_GEN.icount_out_reg[31]\(52 downto 0) => \^inferred_gen.icount_out_reg[0]\(84 downto 32),
Q(0) => TIMER_CONTROL_I_n_3,
S(0) => TIMER_CONTROL_I_n_27,
\TCSR0_GENERATE[27].TCSR0_FF_I\ => TIMER_CONTROL_I_n_28,
counter_TC(0) => counter_TC(0),
generateOutPre0_reg => COUNTER_0_I_n_64,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(10) => read_Mux_In(85),
read_Mux_In(9) => read_Mux_In(86),
read_Mux_In(8) => read_Mux_In(87),
read_Mux_In(7) => read_Mux_In(88),
read_Mux_In(6) => read_Mux_In(89),
read_Mux_In(5) => read_Mux_In(90),
read_Mux_In(4) => read_Mux_In(91),
read_Mux_In(3) => read_Mux_In(92),
read_Mux_In(2) => read_Mux_In(93),
read_Mux_In(1) => read_Mux_In(94),
read_Mux_In(0) => read_Mux_In(95),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => \^bus2ip_reset\
);
\GEN_SECOND_TIMER.COUNTER_1_I\: entity work.zqynq_lab_1_design_axi_timer_0_1_count_module_0
port map (
D_2 => D_2,
E(0) => TIMER_CONTROL_I_n_25,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
\INFERRED_GEN.icount_out_reg[0]\ => \INFERRED_GEN.icount_out_reg[0]_0\,
\INFERRED_GEN.icount_out_reg[10]\ => \INFERRED_GEN.icount_out_reg[10]\,
\INFERRED_GEN.icount_out_reg[11]\ => \INFERRED_GEN.icount_out_reg[11]\,
\INFERRED_GEN.icount_out_reg[12]\ => \INFERRED_GEN.icount_out_reg[12]\,
\INFERRED_GEN.icount_out_reg[13]\ => \INFERRED_GEN.icount_out_reg[13]\,
\INFERRED_GEN.icount_out_reg[14]\ => \INFERRED_GEN.icount_out_reg[14]\,
\INFERRED_GEN.icount_out_reg[15]\ => \INFERRED_GEN.icount_out_reg[15]\,
\INFERRED_GEN.icount_out_reg[16]\ => \INFERRED_GEN.icount_out_reg[16]\,
\INFERRED_GEN.icount_out_reg[17]\ => \INFERRED_GEN.icount_out_reg[17]\,
\INFERRED_GEN.icount_out_reg[18]\ => \INFERRED_GEN.icount_out_reg[18]\,
\INFERRED_GEN.icount_out_reg[19]\ => \INFERRED_GEN.icount_out_reg[19]\,
\INFERRED_GEN.icount_out_reg[1]\ => \INFERRED_GEN.icount_out_reg[1]\,
\INFERRED_GEN.icount_out_reg[20]\ => \INFERRED_GEN.icount_out_reg[20]\,
\INFERRED_GEN.icount_out_reg[21]\ => \INFERRED_GEN.icount_out_reg[21]\,
\INFERRED_GEN.icount_out_reg[22]\ => \INFERRED_GEN.icount_out_reg[22]\,
\INFERRED_GEN.icount_out_reg[23]\ => \INFERRED_GEN.icount_out_reg[23]\,
\INFERRED_GEN.icount_out_reg[24]\ => \INFERRED_GEN.icount_out_reg[24]\,
\INFERRED_GEN.icount_out_reg[25]\ => \INFERRED_GEN.icount_out_reg[25]\,
\INFERRED_GEN.icount_out_reg[26]\ => \INFERRED_GEN.icount_out_reg[26]\,
\INFERRED_GEN.icount_out_reg[27]\ => \INFERRED_GEN.icount_out_reg[27]\,
\INFERRED_GEN.icount_out_reg[28]\ => \INFERRED_GEN.icount_out_reg[28]\,
\INFERRED_GEN.icount_out_reg[29]\ => \INFERRED_GEN.icount_out_reg[29]\,
\INFERRED_GEN.icount_out_reg[2]\ => \INFERRED_GEN.icount_out_reg[2]\,
\INFERRED_GEN.icount_out_reg[30]\ => \INFERRED_GEN.icount_out_reg[30]\,
\INFERRED_GEN.icount_out_reg[31]\ => \^bus2ip_reset\,
\INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(63 downto 32),
\INFERRED_GEN.icount_out_reg[3]\ => \INFERRED_GEN.icount_out_reg[3]\,
\INFERRED_GEN.icount_out_reg[4]\ => \INFERRED_GEN.icount_out_reg[4]\,
\INFERRED_GEN.icount_out_reg[5]\ => \INFERRED_GEN.icount_out_reg[5]\,
\INFERRED_GEN.icount_out_reg[6]\ => \INFERRED_GEN.icount_out_reg[6]\,
\INFERRED_GEN.icount_out_reg[7]\ => \INFERRED_GEN.icount_out_reg[7]\,
\INFERRED_GEN.icount_out_reg[8]\ => \INFERRED_GEN.icount_out_reg[8]\,
\INFERRED_GEN.icount_out_reg[9]\ => \INFERRED_GEN.icount_out_reg[9]\,
Q(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(31 downto 0),
S(0) => TIMER_CONTROL_I_n_30,
\TCSR0_GENERATE[20].TCSR0_FF_I\ => TIMER_CONTROL_I_n_29,
counter_TC(0) => counter_TC(1),
\counter_TC_Reg_reg[1]\(0) => TIMER_CONTROL_I_n_4,
generateOutPre1_reg => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\,
load_Counter_Reg(0) => load_Counter_Reg(1),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\,
\s_axi_rdata_i_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\,
\s_axi_rdata_i_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\,
\s_axi_rdata_i_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\,
\s_axi_rdata_i_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\,
\s_axi_rdata_i_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\,
\s_axi_rdata_i_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\,
\s_axi_rdata_i_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\,
\s_axi_rdata_i_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\,
\s_axi_rdata_i_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\,
\s_axi_rdata_i_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\,
\s_axi_rdata_i_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\,
\s_axi_rdata_i_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\,
\s_axi_rdata_i_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\,
\s_axi_rdata_i_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\,
\s_axi_rdata_i_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\,
\s_axi_rdata_i_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\,
\s_axi_rdata_i_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\,
\s_axi_rdata_i_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\,
\s_axi_rdata_i_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\,
\s_axi_rdata_i_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\,
\s_axi_rdata_i_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\,
\s_axi_rdata_i_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\,
\s_axi_rdata_i_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\,
\s_axi_rdata_i_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\,
\s_axi_rdata_i_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\,
\s_axi_rdata_i_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\,
\s_axi_rdata_i_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\,
\s_axi_rdata_i_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\,
\s_axi_rdata_i_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\,
\s_axi_rdata_i_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\,
\s_axi_rdata_i_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\
);
PWM_FF_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => TIMER_CONTROL_I_n_26,
Q => \^pwm0\,
R => R
);
READ_MUX_I: entity work.zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f
port map (
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1 => Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_10 => Bus_RNW_reg_reg_10,
Bus_RNW_reg_reg_11 => Bus_RNW_reg_reg_11,
Bus_RNW_reg_reg_12 => Bus_RNW_reg_reg_12,
Bus_RNW_reg_reg_13 => Bus_RNW_reg_reg_13,
Bus_RNW_reg_reg_14 => Bus_RNW_reg_reg_14,
Bus_RNW_reg_reg_15 => Bus_RNW_reg_reg_15,
Bus_RNW_reg_reg_16 => Bus_RNW_reg_reg_16,
Bus_RNW_reg_reg_17 => Bus_RNW_reg_reg_17,
Bus_RNW_reg_reg_18 => Bus_RNW_reg_reg_18,
Bus_RNW_reg_reg_2 => Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3 => Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_4 => Bus_RNW_reg_reg_4,
Bus_RNW_reg_reg_5 => Bus_RNW_reg_reg_5,
Bus_RNW_reg_reg_6 => Bus_RNW_reg_reg_6,
Bus_RNW_reg_reg_7 => Bus_RNW_reg_reg_7,
Bus_RNW_reg_reg_8 => Bus_RNW_reg_reg_8,
Bus_RNW_reg_reg_9 => Bus_RNW_reg_reg_9,
D(31 downto 0) => D(31 downto 0),
\INFERRED_GEN.icount_out_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\,
\INFERRED_GEN.icount_out_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\,
\INFERRED_GEN.icount_out_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\,
\INFERRED_GEN.icount_out_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\,
\INFERRED_GEN.icount_out_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\,
\INFERRED_GEN.icount_out_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\,
\INFERRED_GEN.icount_out_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\,
\INFERRED_GEN.icount_out_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\,
\INFERRED_GEN.icount_out_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\,
\INFERRED_GEN.icount_out_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\,
\INFERRED_GEN.icount_out_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\,
\INFERRED_GEN.icount_out_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\,
\INFERRED_GEN.icount_out_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\,
\INFERRED_GEN.icount_out_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\,
\INFERRED_GEN.icount_out_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\,
\INFERRED_GEN.icount_out_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\,
\INFERRED_GEN.icount_out_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\,
\INFERRED_GEN.icount_out_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\,
\INFERRED_GEN.icount_out_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\,
\INFERRED_GEN.icount_out_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\,
\INFERRED_GEN.icount_out_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\,
\INFERRED_GEN.icount_out_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\,
\INFERRED_GEN.icount_out_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\,
\INFERRED_GEN.icount_out_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\,
\INFERRED_GEN.icount_out_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\,
\INFERRED_GEN.icount_out_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\,
\INFERRED_GEN.icount_out_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\,
\INFERRED_GEN.icount_out_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\,
\INFERRED_GEN.icount_out_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\,
\INFERRED_GEN.icount_out_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\,
\INFERRED_GEN.icount_out_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\,
\INFERRED_GEN.icount_out_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => TIMER_CONTROL_I_n_22,
\LOAD_REG_GEN[22].LOAD_REG_I\ => TIMER_CONTROL_I_n_21,
\LOAD_REG_GEN[23].LOAD_REG_I\ => TIMER_CONTROL_I_n_20,
\LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_19,
\LOAD_REG_GEN[25].LOAD_REG_I\ => TIMER_CONTROL_I_n_18,
\LOAD_REG_GEN[26].LOAD_REG_I\ => TIMER_CONTROL_I_n_17,
\LOAD_REG_GEN[27].LOAD_REG_I\ => TIMER_CONTROL_I_n_16,
\LOAD_REG_GEN[28].LOAD_REG_I\ => TIMER_CONTROL_I_n_15,
\LOAD_REG_GEN[29].LOAD_REG_I\ => TIMER_CONTROL_I_n_14,
\LOAD_REG_GEN[30].LOAD_REG_I\ => TIMER_CONTROL_I_n_13,
\LOAD_REG_GEN[31].LOAD_REG_I\ => TIMER_CONTROL_I_n_12
);
TIMER_CONTROL_I: entity work.zqynq_lab_1_design_axi_timer_0_1_timer_control
port map (
Bus_RNW_reg => Bus_RNW_reg,
D_0 => D_0,
E(0) => TIMER_CONTROL_I_n_24,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
\INFERRED_GEN.icount_out_reg[0]\ => \^inferred_gen.icount_out_reg[0]\(87),
\INFERRED_GEN.icount_out_reg[0]_0\(0) => TIMER_CONTROL_I_n_25,
\INFERRED_GEN.icount_out_reg[1]\(1) => \^inferred_gen.icount_out_reg[0]\(33),
\INFERRED_GEN.icount_out_reg[1]\(0) => \^inferred_gen.icount_out_reg[0]\(1),
\INFERRED_GEN.icount_out_reg[32]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\,
\INFERRED_GEN.icount_out_reg[32]_0\ => COUNTER_0_I_n_64,
\INFERRED_GEN.icount_out_reg[4]\(0) => TIMER_CONTROL_I_n_30,
\LOAD_REG_GEN[21].LOAD_REG_I\(10) => read_Mux_In(85),
\LOAD_REG_GEN[21].LOAD_REG_I\(9) => read_Mux_In(86),
\LOAD_REG_GEN[21].LOAD_REG_I\(8) => read_Mux_In(87),
\LOAD_REG_GEN[21].LOAD_REG_I\(7) => read_Mux_In(88),
\LOAD_REG_GEN[21].LOAD_REG_I\(6) => read_Mux_In(89),
\LOAD_REG_GEN[21].LOAD_REG_I\(5) => read_Mux_In(90),
\LOAD_REG_GEN[21].LOAD_REG_I\(4) => read_Mux_In(91),
\LOAD_REG_GEN[21].LOAD_REG_I\(3) => read_Mux_In(92),
\LOAD_REG_GEN[21].LOAD_REG_I\(2) => read_Mux_In(93),
\LOAD_REG_GEN[21].LOAD_REG_I\(1) => read_Mux_In(94),
\LOAD_REG_GEN[21].LOAD_REG_I\(0) => read_Mux_In(95),
\LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_28,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => TIMER_CONTROL_I_n_29,
PWM_FF_I => TIMER_CONTROL_I_n_26,
Q(1) => TIMER_CONTROL_I_n_3,
Q(0) => TIMER_CONTROL_I_n_4,
R => R,
S(0) => TIMER_CONTROL_I_n_27,
SR(0) => \^bus2ip_reset\,
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(86),
\TCSR0_GENERATE[24].TCSR0_FF_I_1\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(85),
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
counter_TC(0 to 1) => counter_TC(0 to 1),
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
load_Counter_Reg(0 to 1) => load_Counter_Reg(0 to 1),
pair0_Select => pair0_Select,
pwm0 => \^pwm0\,
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
\s_axi_rdata_i_reg[0]\ => TIMER_CONTROL_I_n_12,
\s_axi_rdata_i_reg[10]\ => TIMER_CONTROL_I_n_22,
\s_axi_rdata_i_reg[1]\ => TIMER_CONTROL_I_n_13,
\s_axi_rdata_i_reg[2]\ => TIMER_CONTROL_I_n_14,
\s_axi_rdata_i_reg[3]\ => TIMER_CONTROL_I_n_15,
\s_axi_rdata_i_reg[4]\ => TIMER_CONTROL_I_n_16,
\s_axi_rdata_i_reg[5]\ => TIMER_CONTROL_I_n_17,
\s_axi_rdata_i_reg[6]\ => TIMER_CONTROL_I_n_18,
\s_axi_rdata_i_reg[7]\ => TIMER_CONTROL_I_n_19,
\s_axi_rdata_i_reg[8]\ => TIMER_CONTROL_I_n_20,
\s_axi_rdata_i_reg[9]\ => TIMER_CONTROL_I_n_21,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif : entity is "axi_lite_ipif";
end zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.zqynq_lab_1_design_axi_timer_0_1_slave_attachment
port map (
D(31 downto 0) => D(31 downto 0),
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => Bus_RNW_reg,
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
pair0_Select => pair0_Select,
read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]\,
\s_axi_rdata_i_reg[0]_1\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[10]_0\ => \s_axi_rdata_i_reg[10]\,
\s_axi_rdata_i_reg[11]_0\ => \s_axi_rdata_i_reg[11]\,
\s_axi_rdata_i_reg[12]_0\ => \s_axi_rdata_i_reg[12]\,
\s_axi_rdata_i_reg[13]_0\ => \s_axi_rdata_i_reg[13]\,
\s_axi_rdata_i_reg[14]_0\ => \s_axi_rdata_i_reg[14]\,
\s_axi_rdata_i_reg[15]_0\ => \s_axi_rdata_i_reg[15]\,
\s_axi_rdata_i_reg[16]_0\ => \s_axi_rdata_i_reg[16]\,
\s_axi_rdata_i_reg[17]_0\ => \s_axi_rdata_i_reg[17]\,
\s_axi_rdata_i_reg[18]_0\ => \s_axi_rdata_i_reg[18]\,
\s_axi_rdata_i_reg[19]_0\ => \s_axi_rdata_i_reg[19]\,
\s_axi_rdata_i_reg[20]_0\ => \s_axi_rdata_i_reg[20]\,
\s_axi_rdata_i_reg[21]_0\ => \s_axi_rdata_i_reg[21]\,
\s_axi_rdata_i_reg[22]_0\ => \s_axi_rdata_i_reg[22]\,
\s_axi_rdata_i_reg[23]_0\ => \s_axi_rdata_i_reg[23]\,
\s_axi_rdata_i_reg[24]_0\ => \s_axi_rdata_i_reg[24]\,
\s_axi_rdata_i_reg[25]_0\ => \s_axi_rdata_i_reg[25]\,
\s_axi_rdata_i_reg[26]_0\ => \s_axi_rdata_i_reg[26]\,
\s_axi_rdata_i_reg[27]_0\ => \s_axi_rdata_i_reg[27]\,
\s_axi_rdata_i_reg[28]_0\ => \s_axi_rdata_i_reg[28]\,
\s_axi_rdata_i_reg[29]_0\ => \s_axi_rdata_i_reg[29]\,
\s_axi_rdata_i_reg[30]_0\ => \s_axi_rdata_i_reg[30]\,
\s_axi_rdata_i_reg[31]_0\ => \s_axi_rdata_i_reg[31]\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg,
s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_2 => s_axi_rvalid_i_reg_1,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1_axi_timer is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "zynq";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "1'b1";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "axi_timer";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_timer_0_1_axi_timer : entity is "yes";
end zqynq_lab_1_design_axi_timer_0_1_axi_timer;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1_axi_timer is
signal \<const0>\ : STD_LOGIC;
signal AXI4_LITE_I_n_10 : STD_LOGIC;
signal AXI4_LITE_I_n_100 : STD_LOGIC;
signal AXI4_LITE_I_n_101 : STD_LOGIC;
signal AXI4_LITE_I_n_102 : STD_LOGIC;
signal AXI4_LITE_I_n_103 : STD_LOGIC;
signal AXI4_LITE_I_n_104 : STD_LOGIC;
signal AXI4_LITE_I_n_105 : STD_LOGIC;
signal AXI4_LITE_I_n_106 : STD_LOGIC;
signal AXI4_LITE_I_n_11 : STD_LOGIC;
signal AXI4_LITE_I_n_12 : STD_LOGIC;
signal AXI4_LITE_I_n_13 : STD_LOGIC;
signal AXI4_LITE_I_n_14 : STD_LOGIC;
signal AXI4_LITE_I_n_15 : STD_LOGIC;
signal AXI4_LITE_I_n_16 : STD_LOGIC;
signal AXI4_LITE_I_n_17 : STD_LOGIC;
signal AXI4_LITE_I_n_18 : STD_LOGIC;
signal AXI4_LITE_I_n_19 : STD_LOGIC;
signal AXI4_LITE_I_n_20 : STD_LOGIC;
signal AXI4_LITE_I_n_21 : STD_LOGIC;
signal AXI4_LITE_I_n_22 : STD_LOGIC;
signal AXI4_LITE_I_n_23 : STD_LOGIC;
signal AXI4_LITE_I_n_27 : STD_LOGIC;
signal AXI4_LITE_I_n_28 : STD_LOGIC;
signal AXI4_LITE_I_n_29 : STD_LOGIC;
signal AXI4_LITE_I_n_30 : STD_LOGIC;
signal AXI4_LITE_I_n_31 : STD_LOGIC;
signal AXI4_LITE_I_n_32 : STD_LOGIC;
signal AXI4_LITE_I_n_33 : STD_LOGIC;
signal AXI4_LITE_I_n_34 : STD_LOGIC;
signal AXI4_LITE_I_n_35 : STD_LOGIC;
signal AXI4_LITE_I_n_36 : STD_LOGIC;
signal AXI4_LITE_I_n_37 : STD_LOGIC;
signal AXI4_LITE_I_n_38 : STD_LOGIC;
signal AXI4_LITE_I_n_39 : STD_LOGIC;
signal AXI4_LITE_I_n_4 : STD_LOGIC;
signal AXI4_LITE_I_n_40 : STD_LOGIC;
signal AXI4_LITE_I_n_41 : STD_LOGIC;
signal AXI4_LITE_I_n_42 : STD_LOGIC;
signal AXI4_LITE_I_n_43 : STD_LOGIC;
signal AXI4_LITE_I_n_44 : STD_LOGIC;
signal AXI4_LITE_I_n_45 : STD_LOGIC;
signal AXI4_LITE_I_n_46 : STD_LOGIC;
signal AXI4_LITE_I_n_47 : STD_LOGIC;
signal AXI4_LITE_I_n_48 : STD_LOGIC;
signal AXI4_LITE_I_n_49 : STD_LOGIC;
signal AXI4_LITE_I_n_5 : STD_LOGIC;
signal AXI4_LITE_I_n_50 : STD_LOGIC;
signal AXI4_LITE_I_n_51 : STD_LOGIC;
signal AXI4_LITE_I_n_52 : STD_LOGIC;
signal AXI4_LITE_I_n_53 : STD_LOGIC;
signal AXI4_LITE_I_n_54 : STD_LOGIC;
signal AXI4_LITE_I_n_55 : STD_LOGIC;
signal AXI4_LITE_I_n_56 : STD_LOGIC;
signal AXI4_LITE_I_n_57 : STD_LOGIC;
signal AXI4_LITE_I_n_58 : STD_LOGIC;
signal AXI4_LITE_I_n_59 : STD_LOGIC;
signal AXI4_LITE_I_n_6 : STD_LOGIC;
signal AXI4_LITE_I_n_60 : STD_LOGIC;
signal AXI4_LITE_I_n_65 : STD_LOGIC;
signal AXI4_LITE_I_n_66 : STD_LOGIC;
signal AXI4_LITE_I_n_67 : STD_LOGIC;
signal AXI4_LITE_I_n_68 : STD_LOGIC;
signal AXI4_LITE_I_n_69 : STD_LOGIC;
signal AXI4_LITE_I_n_7 : STD_LOGIC;
signal AXI4_LITE_I_n_70 : STD_LOGIC;
signal AXI4_LITE_I_n_71 : STD_LOGIC;
signal AXI4_LITE_I_n_72 : STD_LOGIC;
signal AXI4_LITE_I_n_73 : STD_LOGIC;
signal AXI4_LITE_I_n_74 : STD_LOGIC;
signal AXI4_LITE_I_n_75 : STD_LOGIC;
signal AXI4_LITE_I_n_76 : STD_LOGIC;
signal AXI4_LITE_I_n_77 : STD_LOGIC;
signal AXI4_LITE_I_n_78 : STD_LOGIC;
signal AXI4_LITE_I_n_79 : STD_LOGIC;
signal AXI4_LITE_I_n_8 : STD_LOGIC;
signal AXI4_LITE_I_n_80 : STD_LOGIC;
signal AXI4_LITE_I_n_81 : STD_LOGIC;
signal AXI4_LITE_I_n_82 : STD_LOGIC;
signal AXI4_LITE_I_n_83 : STD_LOGIC;
signal AXI4_LITE_I_n_84 : STD_LOGIC;
signal AXI4_LITE_I_n_85 : STD_LOGIC;
signal AXI4_LITE_I_n_86 : STD_LOGIC;
signal AXI4_LITE_I_n_87 : STD_LOGIC;
signal AXI4_LITE_I_n_88 : STD_LOGIC;
signal AXI4_LITE_I_n_89 : STD_LOGIC;
signal AXI4_LITE_I_n_9 : STD_LOGIC;
signal AXI4_LITE_I_n_90 : STD_LOGIC;
signal AXI4_LITE_I_n_91 : STD_LOGIC;
signal AXI4_LITE_I_n_92 : STD_LOGIC;
signal AXI4_LITE_I_n_93 : STD_LOGIC;
signal AXI4_LITE_I_n_94 : STD_LOGIC;
signal AXI4_LITE_I_n_95 : STD_LOGIC;
signal AXI4_LITE_I_n_97 : STD_LOGIC;
signal AXI4_LITE_I_n_98 : STD_LOGIC;
signal AXI4_LITE_I_n_99 : STD_LOGIC;
signal \COUNTER_0_I/D\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I/D\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \TIMER_CONTROL_I/D\ : STD_LOGIC;
signal \TIMER_CONTROL_I/pair0_Select\ : STD_LOGIC;
signal \TIMER_CONTROL_I/read_done1\ : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_wrce : STD_LOGIC_VECTOR ( 0 to 4 );
signal \bus2ip_wrce__0\ : STD_LOGIC_VECTOR ( 5 to 5 );
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal read_Mux_In : STD_LOGIC_VECTOR ( 20 to 191 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI4_LITE_I: entity work.zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
D_1 => \COUNTER_0_I/D\,
D_2 => \TIMER_CONTROL_I/D\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\LOAD_REG_GEN[10].LOAD_REG_I\ => AXI4_LITE_I_n_51,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => AXI4_LITE_I_n_86,
\LOAD_REG_GEN[11].LOAD_REG_I\ => AXI4_LITE_I_n_50,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => AXI4_LITE_I_n_85,
\LOAD_REG_GEN[12].LOAD_REG_I\ => AXI4_LITE_I_n_49,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => AXI4_LITE_I_n_84,
\LOAD_REG_GEN[13].LOAD_REG_I\ => AXI4_LITE_I_n_48,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => AXI4_LITE_I_n_83,
\LOAD_REG_GEN[14].LOAD_REG_I\ => AXI4_LITE_I_n_47,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => AXI4_LITE_I_n_82,
\LOAD_REG_GEN[15].LOAD_REG_I\ => AXI4_LITE_I_n_46,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => AXI4_LITE_I_n_81,
\LOAD_REG_GEN[16].LOAD_REG_I\ => AXI4_LITE_I_n_45,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => AXI4_LITE_I_n_80,
\LOAD_REG_GEN[17].LOAD_REG_I\ => AXI4_LITE_I_n_44,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => AXI4_LITE_I_n_79,
\LOAD_REG_GEN[18].LOAD_REG_I\ => AXI4_LITE_I_n_43,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => AXI4_LITE_I_n_78,
\LOAD_REG_GEN[19].LOAD_REG_I\ => AXI4_LITE_I_n_42,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => AXI4_LITE_I_n_77,
\LOAD_REG_GEN[1].LOAD_REG_I\ => AXI4_LITE_I_n_60,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => AXI4_LITE_I_n_95,
\LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_41,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => AXI4_LITE_I_n_76,
\LOAD_REG_GEN[21].LOAD_REG_I\ => AXI4_LITE_I_n_40,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => AXI4_LITE_I_n_75,
\LOAD_REG_GEN[22].LOAD_REG_I\ => AXI4_LITE_I_n_39,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => AXI4_LITE_I_n_74,
\LOAD_REG_GEN[23].LOAD_REG_I\ => AXI4_LITE_I_n_38,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => AXI4_LITE_I_n_73,
\LOAD_REG_GEN[24].LOAD_REG_I\ => AXI4_LITE_I_n_37,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => AXI4_LITE_I_n_72,
\LOAD_REG_GEN[25].LOAD_REG_I\ => AXI4_LITE_I_n_36,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => AXI4_LITE_I_n_71,
\LOAD_REG_GEN[26].LOAD_REG_I\ => AXI4_LITE_I_n_35,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => AXI4_LITE_I_n_70,
\LOAD_REG_GEN[27].LOAD_REG_I\ => AXI4_LITE_I_n_34,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => AXI4_LITE_I_n_69,
\LOAD_REG_GEN[28].LOAD_REG_I\ => AXI4_LITE_I_n_33,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => AXI4_LITE_I_n_68,
\LOAD_REG_GEN[29].LOAD_REG_I\ => AXI4_LITE_I_n_32,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => AXI4_LITE_I_n_67,
\LOAD_REG_GEN[2].LOAD_REG_I\ => AXI4_LITE_I_n_59,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => AXI4_LITE_I_n_94,
\LOAD_REG_GEN[30].LOAD_REG_I\ => AXI4_LITE_I_n_31,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => AXI4_LITE_I_n_66,
\LOAD_REG_GEN[31].LOAD_REG_I\ => AXI4_LITE_I_n_30,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => AXI4_LITE_I_n_65,
\LOAD_REG_GEN[3].LOAD_REG_I\ => AXI4_LITE_I_n_58,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => AXI4_LITE_I_n_93,
\LOAD_REG_GEN[4].LOAD_REG_I\ => AXI4_LITE_I_n_57,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => AXI4_LITE_I_n_92,
\LOAD_REG_GEN[5].LOAD_REG_I\ => AXI4_LITE_I_n_56,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => AXI4_LITE_I_n_91,
\LOAD_REG_GEN[6].LOAD_REG_I\ => AXI4_LITE_I_n_55,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => AXI4_LITE_I_n_90,
\LOAD_REG_GEN[7].LOAD_REG_I\ => AXI4_LITE_I_n_54,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => AXI4_LITE_I_n_89,
\LOAD_REG_GEN[8].LOAD_REG_I\ => AXI4_LITE_I_n_53,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => AXI4_LITE_I_n_88,
\LOAD_REG_GEN[9].LOAD_REG_I\ => AXI4_LITE_I_n_52,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => AXI4_LITE_I_n_87,
READ_DONE0_I => AXI4_LITE_I_n_105,
READ_DONE1_I => AXI4_LITE_I_n_106,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => AXI4_LITE_I_n_100,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => AXI4_LITE_I_n_101,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5),
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
read_Mux_In(87) => read_Mux_In(20),
read_Mux_In(86) => read_Mux_In(24),
read_Mux_In(85) => read_Mux_In(56),
read_Mux_In(84) => read_Mux_In(64),
read_Mux_In(83) => read_Mux_In(65),
read_Mux_In(82) => read_Mux_In(66),
read_Mux_In(81) => read_Mux_In(67),
read_Mux_In(80) => read_Mux_In(68),
read_Mux_In(79) => read_Mux_In(69),
read_Mux_In(78) => read_Mux_In(70),
read_Mux_In(77) => read_Mux_In(71),
read_Mux_In(76) => read_Mux_In(72),
read_Mux_In(75) => read_Mux_In(73),
read_Mux_In(74) => read_Mux_In(74),
read_Mux_In(73) => read_Mux_In(75),
read_Mux_In(72) => read_Mux_In(76),
read_Mux_In(71) => read_Mux_In(77),
read_Mux_In(70) => read_Mux_In(78),
read_Mux_In(69) => read_Mux_In(79),
read_Mux_In(68) => read_Mux_In(80),
read_Mux_In(67) => read_Mux_In(81),
read_Mux_In(66) => read_Mux_In(82),
read_Mux_In(65) => read_Mux_In(83),
read_Mux_In(64) => read_Mux_In(84),
read_Mux_In(63) => read_Mux_In(128),
read_Mux_In(62) => read_Mux_In(129),
read_Mux_In(61) => read_Mux_In(130),
read_Mux_In(60) => read_Mux_In(131),
read_Mux_In(59) => read_Mux_In(132),
read_Mux_In(58) => read_Mux_In(133),
read_Mux_In(57) => read_Mux_In(134),
read_Mux_In(56) => read_Mux_In(135),
read_Mux_In(55) => read_Mux_In(136),
read_Mux_In(54) => read_Mux_In(137),
read_Mux_In(53) => read_Mux_In(138),
read_Mux_In(52) => read_Mux_In(139),
read_Mux_In(51) => read_Mux_In(140),
read_Mux_In(50) => read_Mux_In(141),
read_Mux_In(49) => read_Mux_In(142),
read_Mux_In(48) => read_Mux_In(143),
read_Mux_In(47) => read_Mux_In(144),
read_Mux_In(46) => read_Mux_In(145),
read_Mux_In(45) => read_Mux_In(146),
read_Mux_In(44) => read_Mux_In(147),
read_Mux_In(43) => read_Mux_In(148),
read_Mux_In(42) => read_Mux_In(149),
read_Mux_In(41) => read_Mux_In(150),
read_Mux_In(40) => read_Mux_In(151),
read_Mux_In(39) => read_Mux_In(152),
read_Mux_In(38) => read_Mux_In(153),
read_Mux_In(37) => read_Mux_In(154),
read_Mux_In(36) => read_Mux_In(155),
read_Mux_In(35) => read_Mux_In(156),
read_Mux_In(34) => read_Mux_In(157),
read_Mux_In(33) => read_Mux_In(158),
read_Mux_In(32) => read_Mux_In(159),
read_Mux_In(31) => read_Mux_In(160),
read_Mux_In(30) => read_Mux_In(161),
read_Mux_In(29) => read_Mux_In(162),
read_Mux_In(28) => read_Mux_In(163),
read_Mux_In(27) => read_Mux_In(164),
read_Mux_In(26) => read_Mux_In(165),
read_Mux_In(25) => read_Mux_In(166),
read_Mux_In(24) => read_Mux_In(167),
read_Mux_In(23) => read_Mux_In(168),
read_Mux_In(22) => read_Mux_In(169),
read_Mux_In(21) => read_Mux_In(170),
read_Mux_In(20) => read_Mux_In(171),
read_Mux_In(19) => read_Mux_In(172),
read_Mux_In(18) => read_Mux_In(173),
read_Mux_In(17) => read_Mux_In(174),
read_Mux_In(16) => read_Mux_In(175),
read_Mux_In(15) => read_Mux_In(176),
read_Mux_In(14) => read_Mux_In(177),
read_Mux_In(13) => read_Mux_In(178),
read_Mux_In(12) => read_Mux_In(179),
read_Mux_In(11) => read_Mux_In(180),
read_Mux_In(10) => read_Mux_In(181),
read_Mux_In(9) => read_Mux_In(182),
read_Mux_In(8) => read_Mux_In(183),
read_Mux_In(7) => read_Mux_In(184),
read_Mux_In(6) => read_Mux_In(185),
read_Mux_In(5) => read_Mux_In(186),
read_Mux_In(4) => read_Mux_In(187),
read_Mux_In(3) => read_Mux_In(188),
read_Mux_In(2) => read_Mux_In(189),
read_Mux_In(1) => read_Mux_In(190),
read_Mux_In(0) => read_Mux_In(191),
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(4 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(4 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]\ => AXI4_LITE_I_n_103,
\s_axi_rdata_i_reg[0]_0\ => AXI4_LITE_I_n_104,
\s_axi_rdata_i_reg[10]\ => AXI4_LITE_I_n_102,
\s_axi_rdata_i_reg[11]\ => AXI4_LITE_I_n_27,
\s_axi_rdata_i_reg[12]\ => AXI4_LITE_I_n_4,
\s_axi_rdata_i_reg[13]\ => AXI4_LITE_I_n_5,
\s_axi_rdata_i_reg[14]\ => AXI4_LITE_I_n_6,
\s_axi_rdata_i_reg[15]\ => AXI4_LITE_I_n_7,
\s_axi_rdata_i_reg[16]\ => AXI4_LITE_I_n_8,
\s_axi_rdata_i_reg[17]\ => AXI4_LITE_I_n_9,
\s_axi_rdata_i_reg[18]\ => AXI4_LITE_I_n_10,
\s_axi_rdata_i_reg[19]\ => AXI4_LITE_I_n_11,
\s_axi_rdata_i_reg[20]\ => AXI4_LITE_I_n_12,
\s_axi_rdata_i_reg[21]\ => AXI4_LITE_I_n_13,
\s_axi_rdata_i_reg[22]\ => AXI4_LITE_I_n_14,
\s_axi_rdata_i_reg[23]\ => AXI4_LITE_I_n_15,
\s_axi_rdata_i_reg[24]\ => AXI4_LITE_I_n_16,
\s_axi_rdata_i_reg[25]\ => AXI4_LITE_I_n_17,
\s_axi_rdata_i_reg[26]\ => AXI4_LITE_I_n_18,
\s_axi_rdata_i_reg[27]\ => AXI4_LITE_I_n_19,
\s_axi_rdata_i_reg[28]\ => AXI4_LITE_I_n_20,
\s_axi_rdata_i_reg[29]\ => AXI4_LITE_I_n_21,
\s_axi_rdata_i_reg[30]\ => AXI4_LITE_I_n_22,
\s_axi_rdata_i_reg[31]\ => AXI4_LITE_I_n_23,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_rvalid_i_reg => AXI4_LITE_I_n_97,
s_axi_rvalid_i_reg_0 => AXI4_LITE_I_n_98,
s_axi_rvalid_i_reg_1 => AXI4_LITE_I_n_99,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
TC_CORE_I: entity work.zqynq_lab_1_design_axi_timer_0_1_tc_core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI4_LITE_I_n_23,
Bus_RNW_reg_reg_0 => AXI4_LITE_I_n_22,
Bus_RNW_reg_reg_1 => AXI4_LITE_I_n_21,
Bus_RNW_reg_reg_10 => AXI4_LITE_I_n_12,
Bus_RNW_reg_reg_11 => AXI4_LITE_I_n_11,
Bus_RNW_reg_reg_12 => AXI4_LITE_I_n_10,
Bus_RNW_reg_reg_13 => AXI4_LITE_I_n_9,
Bus_RNW_reg_reg_14 => AXI4_LITE_I_n_8,
Bus_RNW_reg_reg_15 => AXI4_LITE_I_n_7,
Bus_RNW_reg_reg_16 => AXI4_LITE_I_n_6,
Bus_RNW_reg_reg_17 => AXI4_LITE_I_n_5,
Bus_RNW_reg_reg_18 => AXI4_LITE_I_n_4,
Bus_RNW_reg_reg_2 => AXI4_LITE_I_n_20,
Bus_RNW_reg_reg_3 => AXI4_LITE_I_n_19,
Bus_RNW_reg_reg_4 => AXI4_LITE_I_n_18,
Bus_RNW_reg_reg_5 => AXI4_LITE_I_n_17,
Bus_RNW_reg_reg_6 => AXI4_LITE_I_n_16,
Bus_RNW_reg_reg_7 => AXI4_LITE_I_n_15,
Bus_RNW_reg_reg_8 => AXI4_LITE_I_n_14,
Bus_RNW_reg_reg_9 => AXI4_LITE_I_n_13,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \TIMER_CONTROL_I/D\,
D_1 => \COUNTER_0_I/D\,
D_2 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI4_LITE_I_n_100,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => AXI4_LITE_I_n_102,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI4_LITE_I_n_95,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => AXI4_LITE_I_n_94,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => AXI4_LITE_I_n_93,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => AXI4_LITE_I_n_84,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => AXI4_LITE_I_n_83,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => AXI4_LITE_I_n_82,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => AXI4_LITE_I_n_81,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => AXI4_LITE_I_n_80,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => AXI4_LITE_I_n_79,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => AXI4_LITE_I_n_78,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => AXI4_LITE_I_n_77,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => AXI4_LITE_I_n_76,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => AXI4_LITE_I_n_75,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => AXI4_LITE_I_n_92,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => AXI4_LITE_I_n_74,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => AXI4_LITE_I_n_73,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => AXI4_LITE_I_n_72,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => AXI4_LITE_I_n_71,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => AXI4_LITE_I_n_70,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => AXI4_LITE_I_n_69,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => AXI4_LITE_I_n_68,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => AXI4_LITE_I_n_67,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => AXI4_LITE_I_n_66,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => AXI4_LITE_I_n_65,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => AXI4_LITE_I_n_91,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ => AXI4_LITE_I_n_105,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ => AXI4_LITE_I_n_97,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => AXI4_LITE_I_n_90,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => AXI4_LITE_I_n_89,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => AXI4_LITE_I_n_88,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => AXI4_LITE_I_n_87,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => AXI4_LITE_I_n_86,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => AXI4_LITE_I_n_85,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => AXI4_LITE_I_n_99,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI4_LITE_I_n_101,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => AXI4_LITE_I_n_98,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => AXI4_LITE_I_n_106,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ => AXI4_LITE_I_n_103,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => AXI4_LITE_I_n_104,
\INFERRED_GEN.icount_out_reg[0]\(87) => read_Mux_In(20),
\INFERRED_GEN.icount_out_reg[0]\(86) => read_Mux_In(24),
\INFERRED_GEN.icount_out_reg[0]\(85) => read_Mux_In(56),
\INFERRED_GEN.icount_out_reg[0]\(84) => read_Mux_In(64),
\INFERRED_GEN.icount_out_reg[0]\(83) => read_Mux_In(65),
\INFERRED_GEN.icount_out_reg[0]\(82) => read_Mux_In(66),
\INFERRED_GEN.icount_out_reg[0]\(81) => read_Mux_In(67),
\INFERRED_GEN.icount_out_reg[0]\(80) => read_Mux_In(68),
\INFERRED_GEN.icount_out_reg[0]\(79) => read_Mux_In(69),
\INFERRED_GEN.icount_out_reg[0]\(78) => read_Mux_In(70),
\INFERRED_GEN.icount_out_reg[0]\(77) => read_Mux_In(71),
\INFERRED_GEN.icount_out_reg[0]\(76) => read_Mux_In(72),
\INFERRED_GEN.icount_out_reg[0]\(75) => read_Mux_In(73),
\INFERRED_GEN.icount_out_reg[0]\(74) => read_Mux_In(74),
\INFERRED_GEN.icount_out_reg[0]\(73) => read_Mux_In(75),
\INFERRED_GEN.icount_out_reg[0]\(72) => read_Mux_In(76),
\INFERRED_GEN.icount_out_reg[0]\(71) => read_Mux_In(77),
\INFERRED_GEN.icount_out_reg[0]\(70) => read_Mux_In(78),
\INFERRED_GEN.icount_out_reg[0]\(69) => read_Mux_In(79),
\INFERRED_GEN.icount_out_reg[0]\(68) => read_Mux_In(80),
\INFERRED_GEN.icount_out_reg[0]\(67) => read_Mux_In(81),
\INFERRED_GEN.icount_out_reg[0]\(66) => read_Mux_In(82),
\INFERRED_GEN.icount_out_reg[0]\(65) => read_Mux_In(83),
\INFERRED_GEN.icount_out_reg[0]\(64) => read_Mux_In(84),
\INFERRED_GEN.icount_out_reg[0]\(63) => read_Mux_In(128),
\INFERRED_GEN.icount_out_reg[0]\(62) => read_Mux_In(129),
\INFERRED_GEN.icount_out_reg[0]\(61) => read_Mux_In(130),
\INFERRED_GEN.icount_out_reg[0]\(60) => read_Mux_In(131),
\INFERRED_GEN.icount_out_reg[0]\(59) => read_Mux_In(132),
\INFERRED_GEN.icount_out_reg[0]\(58) => read_Mux_In(133),
\INFERRED_GEN.icount_out_reg[0]\(57) => read_Mux_In(134),
\INFERRED_GEN.icount_out_reg[0]\(56) => read_Mux_In(135),
\INFERRED_GEN.icount_out_reg[0]\(55) => read_Mux_In(136),
\INFERRED_GEN.icount_out_reg[0]\(54) => read_Mux_In(137),
\INFERRED_GEN.icount_out_reg[0]\(53) => read_Mux_In(138),
\INFERRED_GEN.icount_out_reg[0]\(52) => read_Mux_In(139),
\INFERRED_GEN.icount_out_reg[0]\(51) => read_Mux_In(140),
\INFERRED_GEN.icount_out_reg[0]\(50) => read_Mux_In(141),
\INFERRED_GEN.icount_out_reg[0]\(49) => read_Mux_In(142),
\INFERRED_GEN.icount_out_reg[0]\(48) => read_Mux_In(143),
\INFERRED_GEN.icount_out_reg[0]\(47) => read_Mux_In(144),
\INFERRED_GEN.icount_out_reg[0]\(46) => read_Mux_In(145),
\INFERRED_GEN.icount_out_reg[0]\(45) => read_Mux_In(146),
\INFERRED_GEN.icount_out_reg[0]\(44) => read_Mux_In(147),
\INFERRED_GEN.icount_out_reg[0]\(43) => read_Mux_In(148),
\INFERRED_GEN.icount_out_reg[0]\(42) => read_Mux_In(149),
\INFERRED_GEN.icount_out_reg[0]\(41) => read_Mux_In(150),
\INFERRED_GEN.icount_out_reg[0]\(40) => read_Mux_In(151),
\INFERRED_GEN.icount_out_reg[0]\(39) => read_Mux_In(152),
\INFERRED_GEN.icount_out_reg[0]\(38) => read_Mux_In(153),
\INFERRED_GEN.icount_out_reg[0]\(37) => read_Mux_In(154),
\INFERRED_GEN.icount_out_reg[0]\(36) => read_Mux_In(155),
\INFERRED_GEN.icount_out_reg[0]\(35) => read_Mux_In(156),
\INFERRED_GEN.icount_out_reg[0]\(34) => read_Mux_In(157),
\INFERRED_GEN.icount_out_reg[0]\(33) => read_Mux_In(158),
\INFERRED_GEN.icount_out_reg[0]\(32) => read_Mux_In(159),
\INFERRED_GEN.icount_out_reg[0]\(31) => read_Mux_In(160),
\INFERRED_GEN.icount_out_reg[0]\(30) => read_Mux_In(161),
\INFERRED_GEN.icount_out_reg[0]\(29) => read_Mux_In(162),
\INFERRED_GEN.icount_out_reg[0]\(28) => read_Mux_In(163),
\INFERRED_GEN.icount_out_reg[0]\(27) => read_Mux_In(164),
\INFERRED_GEN.icount_out_reg[0]\(26) => read_Mux_In(165),
\INFERRED_GEN.icount_out_reg[0]\(25) => read_Mux_In(166),
\INFERRED_GEN.icount_out_reg[0]\(24) => read_Mux_In(167),
\INFERRED_GEN.icount_out_reg[0]\(23) => read_Mux_In(168),
\INFERRED_GEN.icount_out_reg[0]\(22) => read_Mux_In(169),
\INFERRED_GEN.icount_out_reg[0]\(21) => read_Mux_In(170),
\INFERRED_GEN.icount_out_reg[0]\(20) => read_Mux_In(171),
\INFERRED_GEN.icount_out_reg[0]\(19) => read_Mux_In(172),
\INFERRED_GEN.icount_out_reg[0]\(18) => read_Mux_In(173),
\INFERRED_GEN.icount_out_reg[0]\(17) => read_Mux_In(174),
\INFERRED_GEN.icount_out_reg[0]\(16) => read_Mux_In(175),
\INFERRED_GEN.icount_out_reg[0]\(15) => read_Mux_In(176),
\INFERRED_GEN.icount_out_reg[0]\(14) => read_Mux_In(177),
\INFERRED_GEN.icount_out_reg[0]\(13) => read_Mux_In(178),
\INFERRED_GEN.icount_out_reg[0]\(12) => read_Mux_In(179),
\INFERRED_GEN.icount_out_reg[0]\(11) => read_Mux_In(180),
\INFERRED_GEN.icount_out_reg[0]\(10) => read_Mux_In(181),
\INFERRED_GEN.icount_out_reg[0]\(9) => read_Mux_In(182),
\INFERRED_GEN.icount_out_reg[0]\(8) => read_Mux_In(183),
\INFERRED_GEN.icount_out_reg[0]\(7) => read_Mux_In(184),
\INFERRED_GEN.icount_out_reg[0]\(6) => read_Mux_In(185),
\INFERRED_GEN.icount_out_reg[0]\(5) => read_Mux_In(186),
\INFERRED_GEN.icount_out_reg[0]\(4) => read_Mux_In(187),
\INFERRED_GEN.icount_out_reg[0]\(3) => read_Mux_In(188),
\INFERRED_GEN.icount_out_reg[0]\(2) => read_Mux_In(189),
\INFERRED_GEN.icount_out_reg[0]\(1) => read_Mux_In(190),
\INFERRED_GEN.icount_out_reg[0]\(0) => read_Mux_In(191),
\INFERRED_GEN.icount_out_reg[0]_0\ => AXI4_LITE_I_n_30,
\INFERRED_GEN.icount_out_reg[10]\ => AXI4_LITE_I_n_40,
\INFERRED_GEN.icount_out_reg[11]\ => AXI4_LITE_I_n_41,
\INFERRED_GEN.icount_out_reg[12]\ => AXI4_LITE_I_n_42,
\INFERRED_GEN.icount_out_reg[13]\ => AXI4_LITE_I_n_43,
\INFERRED_GEN.icount_out_reg[14]\ => AXI4_LITE_I_n_44,
\INFERRED_GEN.icount_out_reg[15]\ => AXI4_LITE_I_n_45,
\INFERRED_GEN.icount_out_reg[16]\ => AXI4_LITE_I_n_46,
\INFERRED_GEN.icount_out_reg[17]\ => AXI4_LITE_I_n_47,
\INFERRED_GEN.icount_out_reg[18]\ => AXI4_LITE_I_n_48,
\INFERRED_GEN.icount_out_reg[19]\ => AXI4_LITE_I_n_49,
\INFERRED_GEN.icount_out_reg[1]\ => AXI4_LITE_I_n_31,
\INFERRED_GEN.icount_out_reg[20]\ => AXI4_LITE_I_n_50,
\INFERRED_GEN.icount_out_reg[21]\ => AXI4_LITE_I_n_51,
\INFERRED_GEN.icount_out_reg[22]\ => AXI4_LITE_I_n_52,
\INFERRED_GEN.icount_out_reg[23]\ => AXI4_LITE_I_n_53,
\INFERRED_GEN.icount_out_reg[24]\ => AXI4_LITE_I_n_54,
\INFERRED_GEN.icount_out_reg[25]\ => AXI4_LITE_I_n_55,
\INFERRED_GEN.icount_out_reg[26]\ => AXI4_LITE_I_n_56,
\INFERRED_GEN.icount_out_reg[27]\ => AXI4_LITE_I_n_57,
\INFERRED_GEN.icount_out_reg[28]\ => AXI4_LITE_I_n_58,
\INFERRED_GEN.icount_out_reg[29]\ => AXI4_LITE_I_n_59,
\INFERRED_GEN.icount_out_reg[2]\ => AXI4_LITE_I_n_32,
\INFERRED_GEN.icount_out_reg[30]\ => AXI4_LITE_I_n_60,
\INFERRED_GEN.icount_out_reg[3]\ => AXI4_LITE_I_n_33,
\INFERRED_GEN.icount_out_reg[4]\ => AXI4_LITE_I_n_34,
\INFERRED_GEN.icount_out_reg[5]\ => AXI4_LITE_I_n_35,
\INFERRED_GEN.icount_out_reg[6]\ => AXI4_LITE_I_n_36,
\INFERRED_GEN.icount_out_reg[7]\ => AXI4_LITE_I_n_37,
\INFERRED_GEN.icount_out_reg[8]\ => AXI4_LITE_I_n_38,
\INFERRED_GEN.icount_out_reg[9]\ => AXI4_LITE_I_n_39,
\LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_27,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
pwm0 => pwm0,
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(9 downto 7) => s_axi_wdata(11 downto 9),
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_1 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_axi_timer_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_timer_0_1 : entity is "zqynq_lab_1_design_axi_timer_0_1,axi_timer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_timer_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zqynq_lab_1_design_axi_timer_0_1 : entity is "axi_timer,Vivado 2017.2";
end zqynq_lab_1_design_axi_timer_0_1;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_1 is
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of U0 : label is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of U0 : label is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of U0 : label is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of U0 : label is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of U0 : label is "1'b1";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zqynq_lab_1_design_axi_timer_0_1_axi_timer
port map (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pwm0 => pwm0,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY SimpleIfStatementMergable IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : OUT STD_LOGIC;
d : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF SimpleIfStatementMergable IS
BEGIN
assig_process_d: PROCESS(a, b)
BEGIN
IF a = '1' THEN
d <= b;
c <= b;
ELSE
d <= '0';
c <= '0';
END IF;
END PROCESS;
END ARCHITECTURE;
|
-- ps2.vhd - Kompletni radic portu PS2
-- Autori: Jakub Cabal
-- Posledni zmena: 19.11.2014
-- Popis: Tato jednotka zajistuje kompletni komunikaci s portem PS2
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PS2 is
Port (
CLK : in STD_LOGIC; -- Vychozi hodinovy signal
RST : in STD_LOGIC; -- Vychozi synchronni reset
PS2C : in STD_LOGIC; -- Hodinovy signal z PS2 portu
PS2D : in STD_LOGIC; -- Seriova vstupni data z PS2 portu
KEY_W : out STD_LOGIC; -- Znaci ze byla stisknuta klavesa W
KEY_S : out STD_LOGIC; -- Znaci ze byla stisknuta klavesa S
KEY_A : out STD_LOGIC; -- Znaci ze byla stisknuta klavesa A
KEY_D : out STD_LOGIC; -- Znaci ze byla stisknuta klavesa D
KEY_SPACE : out STD_LOGIC -- Znaci ze byla stisknuta klavesa SPACE
);
end PS2;
architecture FULL of PS2 is
signal sig_ps2c_deb : STD_LOGIC;
signal sig_ps2rx_valid : STD_LOGIC;
signal sig_ps2rx_data : STD_LOGIC_VECTOR(7 downto 0);
signal sig_key_code : STD_LOGIC_VECTOR(7 downto 0);
signal sig_key_w : STD_LOGIC;
signal sig_key_s : STD_LOGIC;
signal sig_key_a : STD_LOGIC;
signal sig_key_d : STD_LOGIC;
signal sig_key_space : STD_LOGIC;
begin
----------------------------------------------------------------------
-- Propojeni vnitrnich podkomponent
----------------------------------------------------------------------
-- PS2 Debouncer
ps2_debouncer_i: entity work.DEBOUNCER
port map(
CLK => CLK,
RST => RST,
DIN => PS2C,
DOUT => sig_ps2c_deb
);
-- Prijem seriovych dat z PS2
ps2_rx_1: entity work.PS2_RX
port map(
CLK => CLK,
RST => RST,
PS2C => sig_ps2c_deb,
PS2D => PS2D,
PS2RX_DATA => sig_ps2rx_data,
PS2RX_VALID => sig_ps2rx_valid
);
-- Ziskani kodu klavesy
kb_code_1: entity work.KB_CODE
port map(
CLK => CLK,
RST => RST,
PS2RX_DATA => sig_ps2rx_data,
PS2RX_VALID => sig_ps2rx_valid,
KEY_CODE => sig_key_code
);
----------------------------------------------------------------------
-- Generovani vystupnich signalu
----------------------------------------------------------------------
-- Generovani signalu o zmacknute klavesy W
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_w <= '0';
elsif (sig_key_code = X"1D") then
sig_key_w <= '1';
else
sig_key_w <= '0';
end if;
end if;
end process;
rised1: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_w,
VYSTUP => KEY_W
);
-- Generovani signalu o zmacknute klavesy S
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_s <= '0';
elsif (sig_key_code = X"1B") then
sig_key_s <= '1';
else
sig_key_s <= '0';
end if;
end if;
end process;
rised2: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_s,
VYSTUP => KEY_S
);
-- Generovani signalu o zmacknute klavesy A
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_a <= '0';
elsif (sig_key_code = X"1C") then
sig_key_a <= '1';
else
sig_key_a <= '0';
end if;
end if;
end process;
rised3: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_a,
VYSTUP => KEY_A
);
-- Generovani signalu o zmacknute klavesy D
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_d <= '0';
elsif (sig_key_code = X"23") then
sig_key_d <= '1';
else
sig_key_d <= '0';
end if;
end if;
end process;
rised4: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_d,
VYSTUP => KEY_D
);
-- Generovani signalu o zmacknute klavesy SPACE
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
sig_key_space <= '0';
elsif (sig_key_code = X"29") then
sig_key_space <= '1';
else
sig_key_space <= '0';
end if;
end if;
end process;
rised5: entity work.RISING_EDGE_DETECTOR
port map(
CLK => CLK,
VSTUP => sig_key_space,
VYSTUP => KEY_SPACE
);
end FULL;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: VGA_BUFFER_RAM_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY VGA_BUFFER_RAM_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE VGA_BUFFER_RAM_synth_ARCH OF VGA_BUFFER_RAM_synth IS
COMPONENT VGA_BUFFER_RAM_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: VGA_BUFFER_RAM_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
-- file: output/draw_frame.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Draw game images from current game state (player position and current
-- obstacles) using vgacon.
library ieee ;
use ieee.std_logic_1164.all ;
library module ;
use module.output.vgacon ;
use module.output.pixel_counter ;
use module.output.frame_builder ;
use module.input.clock_divider ;
entity draw_frame is
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 -- Number of obstacles
) ;
port (
-- Input data
player : in integer range 0 to V_RES - 1 ;
obst_low : in integer range 0 to V_RES - 1 ;
obst_high : in integer range 0 to V_RES - 1 ;
obst_pos : in integer range 0 to H_RES / N_OBST - 1;
obst_id : out integer range 0 to N_OBST - 1 ;
-- VGA output
red : out std_logic_vector(3 downto 0) ;
green : out std_logic_vector(3 downto 0) ;
blue : out std_logic_vector(3 downto 0) ;
hsync : out std_logic ;
vsync : out std_logic ;
-- Control signals
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end draw_frame ;
architecture behavior of draw_frame is
-- State type
type state_t is (start, clear, update_frame) ;
signal state : state_t := start ;
signal next_state : state_t := start ;
signal finish_write : std_logic ;
-- Local control signals
signal we : std_logic := '1' ; -- VGA controller write enable
signal lin : integer range 0 to V_RES - 1 ;
signal col : integer range 0 to H_RES - 1 ;
signal colour : std_logic_vector(2 downto 0) ;
-- Pixel counter signals
signal pxl_count_rst : std_logic ;
signal pxl_count_en : std_logic ;
-- Frame builder signals
signal pxl_col_en : std_logic ;
signal pxl_colour : std_logic_vector(2 downto 0) ;
-- Timer signals
signal timer : std_logic ;
signal timer_en : std_logic ;
signal timer_rst : std_logic ;
begin
-- VGA controller
vga_controller: vgacon
generic map (
NUM_HORZ_PIXELS => H_RES,
NUM_VERT_PIXELS => V_RES
)
port map (
clk27M => clock,
rstn => not reset,
red => red,
green => green,
blue => blue,
hsync => hsync,
vsync => vsync,
write_clk => clock,
write_enable => we,
write_addr => col + (128 * lin),
data_in => colour
) ;
-- Pixel counter, sweeps through each pixel of vga
count_pixel: pixel_counter
generic map (
H_RES => H_RES,
V_RES => V_RES
)
port map (
lin => lin,
col => col,
clock => clock,
reset => pxl_count_rst,
enable => pxl_count_en
) ;
-- Using the game state information, build a frame.
build_frame: frame_builder
generic map (
H_RES => H_RES,
V_RES => V_RES,
N_OBST => N_OBST
)
port map (
player => player,
obst_low => obst_low,
obst_high => obst_high,
obst_pos => obst_pos,
obst_id => obst_id,
lin => lin,
col => col,
enable => pxl_col_en,
colour => pxl_colour
) ;
frame_timer : clock_divider
generic map (
RATE => 270000
)
port map (
clk_in => clock,
clk_out => timer,
enable => timer_en,
reset => timer_rst
) ;
-- Signal end of frame write
finish_write <= '1' when (lin = V_RES - 1) and (col = H_RES - 1) else '0' ;
-- Finite State Machine for drawing frame.
fsm: process(state, finish_write, timer, enable)
begin
if enable = '0' then
next_state <= state ;
timer_en <= '0' ;
timer_rst <= '0' ;
pxl_col_en <= '0' ;
pxl_count_rst <= '0' ;
pxl_count_en <= '0' ;
we <= '0' ;
colour <= "000" ;
else
case state is
when start =>
if timer = '1' then
next_state <= update_frame ;
else
next_state <= start ;
end if ;
timer_en <= '1' ;
timer_rst <= '0' ;
pxl_col_en <= '0' ;
pxl_count_rst <= '1' ;
pxl_count_en <= '0' ;
we <= '0' ;
colour <= "000" ;
when clear =>
if finish_write = '1' then
next_state <= start ;
else
next_state <= clear ;
end if ;
timer_en <= '0' ;
timer_rst <= '1' ;
pxl_col_en <= '0' ;
pxl_count_rst <= '0' ;
pxl_count_en <= '1' ;
we <= '1' ;
colour <= "000" ;
when update_frame =>
if finish_write = '1' then
next_state <= start ;
else
next_state <= update_frame ;
end if ;
timer_en <= '0' ;
timer_rst <= '1' ;
pxl_col_en <= '1' ;
pxl_count_rst <= '0' ;
pxl_count_en <= '1' ;
we <= '1' ;
colour <= pxl_colour ;
when others =>
next_state <= start ;
timer_en <= '0' ;
timer_rst <= '1' ;
pxl_col_en <= '0' ;
pxl_count_rst <= '1' ;
pxl_count_en <= '0' ;
we <= '0' ;
colour <= "000" ;
end case ;
end if ;
end process ;
-- Update state process.
update_state: process(clock, reset)
begin
if reset = '1' then
state <= clear ;
elsif rising_edge(clock) then
state <= next_state ;
end if ;
end process ;
end behavior ;
|
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- RX filter based on work of Grant Searle (bufferedUART.vhd), copyright 2013
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity uart_rx is
port(
clock_i : in std_logic;
reset_i : in std_logic;
baud_i : in std_logic_vector(15 downto 0);
char_len_i : in std_logic_vector( 1 downto 0);
parity_i : in std_logic_vector( 1 downto 0);
data_o : out std_logic_vector( 7 downto 0);
rx_full_i : in std_logic;
fifo_wr_o : out std_logic;
errors_o : out std_logic_vector( 2 downto 0); -- Overrun, Frame, Parity
break_o : out std_logic;
rx_i : in std_logic
);
end entity;
architecture rcvr of uart_rx is
type state_t is (stIdle, stStart, stData, stParity, stStop, stBreak);
signal state_s : state_t;
signal rx_filter_q : integer range 0 to 10;
signal rx_filtered_s : std_logic := '1';
signal parity_cfg_s : std_logic_vector(1 downto 0) := (others => '0');
signal baudr_cnt_q : integer range 0 to 65536 := 0;
signal max_cnt_s : integer range 0 to 65536 := 0;
signal mid_cnt_s : integer range 0 to 32768 := 0;
signal bit_cnt_q : integer range 0 to 9 := 0;
signal bitmax_s : unsigned(3 downto 0) := (others => '0');
signal shift_q : std_logic_vector(7 downto 0) := (others => '0');
signal parity_s : std_logic;
begin
parity_s <= parity_i(1) xor shift_q(7) xor shift_q(6) xor
shift_q(5) xor shift_q(4) xor shift_q(3) xor
shift_q(2) xor shift_q(1) xor shift_q(0);
-- RX de-glitcher - important because the FPGA is very sensistive
-- Filtered RX will not switch low to high until there is 10 more high samples than lows
-- hysteresis will then not switch high to low until there is 10 more low samples than highs.
-- Introduces a minor delay
-- However, then makes serial comms 100% reliable
process (clock_i)
begin
if falling_edge(clock_i) then
if rx_i = '1' and rx_filter_q = 10 then
rx_filtered_s <= '1';
end if;
if rx_i = '1' and rx_filter_q /= 10 then
rx_filter_q <= rx_filter_q+1;
end if;
if rx_i = '0' and rx_filter_q = 0 then
rx_filtered_s <= '0';
end if;
if rx_i = '0' and rx_filter_q /= 0 then
rx_filter_q <= rx_filter_q-1;
end if;
end if;
end process;
-- Main process
process(clock_i)
variable is_parity_v : unsigned(0 downto 0);
variable break_det_v : integer range 0 to 7;
variable break_max_v : integer range 0 to 7;
begin
if rising_edge(clock_i) then
if reset_i = '1' then
parity_cfg_s <= (others => '0');
baudr_cnt_q <= 0;
shift_q <= (others => '0');
bit_cnt_q <= 0;
state_s <= stIdle;
fifo_wr_o <= '0';
errors_o <= (others => '0');
break_o <= '0';
else
fifo_wr_o <= '0';
errors_o <= (others => '0');
break_o <= '0';
case state_s is
when stIdle =>
if rx_filtered_s = '0' then -- Start bit detected
baudr_cnt_q <= 0;
bit_cnt_q <= 0;
bitmax_s <= to_unsigned(4, 4) + unsigned(char_len_i);
max_cnt_s <= to_integer(unsigned(baud_i));
mid_cnt_s <= to_integer(unsigned(baud_i)) / 2;
parity_cfg_s <= parity_i;
shift_q <= (others => '0');
is_parity_v(0) := parity_i(0) or parity_i(1);
break_det_v := 0;
break_max_v := to_integer(is_parity_v + 2);
state_s <= stStart;
end if;
when stStart =>
if baudr_cnt_q >= mid_cnt_s then
baudr_cnt_q <= 0;
state_s <= stData;
else
baudr_cnt_q <= baudr_cnt_q + 1;
end if;
when stData =>
if baudr_cnt_q >= max_cnt_s then
baudr_cnt_q <= 0;
shift_q(bit_cnt_q) <= rx_filtered_s;
if bit_cnt_q >= bitmax_s then
if shift_q = 0 then
break_det_v := break_det_v + 1;
end if;
if parity_cfg_s /= "00" then
state_s <= stParity;
else
state_s <= stStop;
end if;
else
bit_cnt_q <= bit_cnt_q + 1;
end if;
else
baudr_cnt_q <= baudr_cnt_q + 1;
end if;
when stParity =>
if baudr_cnt_q >= max_cnt_s then
baudr_cnt_q <= 0;
if parity_s /= rx_filtered_s then
errors_o(0) <= '1'; -- Parity Error
end if;
if rx_filtered_s = '0' then
break_det_v := break_det_v + 1;
end if;
state_s <= stStop;
else
baudr_cnt_q <= baudr_cnt_q + 1;
end if;
when stStop =>
if baudr_cnt_q >= max_cnt_s then
baudr_cnt_q <= 0;
if rx_filtered_s = '0' then
errors_o(1) <= '1'; -- Frame error
break_det_v := break_det_v + 1;
state_s <= stBreak;
elsif rx_full_i = '1' then
errors_o(2) <= '1'; -- Overrun error
state_s <= stIdle;
else
fifo_wr_o <= '1'; -- No errors, write data
state_s <= stIdle;
end if;
else
baudr_cnt_q <= baudr_cnt_q + 1;
end if;
when stBreak =>
if break_det_v >= break_max_v then
break_o <= '1'; -- Inform Break char detected
end if;
if rx_filtered_s = '1' then
state_s <= stIdle;
end if;
end case;
end if;
end if;
end process;
data_o <= shift_q;
end architecture; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:39:54 04/04/2013
-- Design Name:
-- Module Name: MUX8x1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX8x1 is
Port ( w : in STD_LOGIC_VECTOR (7 downto 0);
S : in STD_LOGIC_VECTOR (2 downto 0);
f : out STD_LOGIC);
end MUX8x1;
architecture Behavioral of MUX8x1 is
signal m: bit_vector(0 to 1);
component mux2x1
port( a : in bit_vector(1 downto 0);
b : in bit;
c: out bit);
end component;
component mux4x1
port( a :in bit_vector(3 downto 0);
b : in bit_vector( 1 downto 0);
c : out bit);
end component;
begin
mx1: mux2x1 port map(a(0),a(1),b,c);
mx2: mux4x1 port map(a(0),a(1),a(2),a(3),b(1 downto 0),c);
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pong is
port
(
din : in std_logic_vector(31 downto 0);
dout : in std_logic_vector(31 downto 0)
);
end entity pong;
architecture rtl of pong is
begin
dout <= din(23 downto 16) & din(23 downto 16) & din(7 downto 0) & din(7 downto 0);
end architecture rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:01:16 11/13/2015
-- Design Name:
-- Module Name: half_adder - DataFlow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity half_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC;
s : out STD_LOGIC);
end half_adder;
architecture DataFlow of half_adder is
begin
s <= a xor b;
c <= a and b;
end DataFlow;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY drigmorn1_top IS
PORT(
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(1 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT blk_mem_40K
PORT (
addra : IN std_logic_VECTOR (15 DOWNTO 0);
clka : IN std_logic;
dina : IN std_logic_VECTOR (7 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
douta : OUT std_logic_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom)
begin
case sel_s is
when "01" => dbus_in_cpu <= dbus_com1; -- UART
when "10" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when others=> dbus_in_cpu <= dbus_in; -- Embedded SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SOMA is
port (A, B: in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0);
Flag: out std_logic_vector(3 downto 0)
);
end SOMA;
architecture c1_estr of SOMA is
signal c, Bin, S: std_logic_vector(7 downto 0);
component fulladder
port (a, b, c: in std_logic;
soma, carry: out std_logic);
end component;
begin
Bin(0) <= B(0) xor '0';
Bin(1) <= B(1) xor '0';
Bin(2) <= B(2) xor '0';
Bin(3) <= B(3) xor '0';
Bin(4) <= B(4) xor '0';
Bin(5) <= B(5) xor '0';
Bin(6) <= B(6) xor '0';
Bin(7) <= B(7) xor '0';
A0: fulladder port map (A(0), Bin(0), '0', S(0), c(0));
A1: fulladder port map (A(1), Bin(1), c(0), S(1), c(1));
A2: fulladder port map (A(2), Bin(2), c(1), S(2), c(2));
A3: fulladder port map (A(3), Bin(3), c(2), S(3), c(3));
A4: fulladder port map (A(4), Bin(4), c(3), S(4), c(4));
A5: fulladder port map (A(5), Bin(5), c(4), S(5), c(5));
A6: fulladder port map (A(6), Bin(6), c(5), S(6), c(6));
A7: fulladder port map (A(7), Bin(7), c(6), S(7), c(7));
Flag(3) <= not (S(7) or S(6) or S(5) or S(4) or S(3) or S(2) or S(1) or S(0));--zero
Flag(2) <= c(7) xor c(6);--overflow
Flag(1) <= c(7);--carryout
Flag(0) <= S(7);--negativo
F <= S;
end c1_estr;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ae
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ae-e.vhd,v 1.3 2005/07/19 07:13:12 wig Exp $
-- $Date: 2005/07/19 07:13:12 $
-- $Log: ent_ae-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:12 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ae
--
entity ent_ae is
-- Generics:
-- No Generated Generics for Entity ent_ae
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0);
port_ae_5 : in std_ulogic_vector(3 downto 0);
port_ae_6 : in std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2);
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_ae
);
end ent_ae;
--
-- End of Generated Entity ent_ae
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2sp16a
-- File: ddr2sp16a.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 16-bit DDR2 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddr2sp16a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddr2sp16a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant odtvalue : std_logic_vector(1 downto 0) := conv_std_logic_vector(odten, 2);
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDR2SP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr0, wr1, wr2, wr3, wr4a, wr4b, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode23, emode, lmode, emodeocd, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cal_rst : std_logic;
readdly : std_logic_vector(1 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
write : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
sync : std_logic_vector(2 downto 1);
startsd_ack : std_logic;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(4 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(3 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector(1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
waddr_d : std_logic_vector(abuf-1 downto 0); -- Same as waddr but delayed to compensate for pipelined output data
cfg : sdram_cfg_type;
readdly : std_logic_vector(1 downto 0); -- added read latency
newcom : std_logic; -- start sec. read/write
wdata : std_logic_vector(31 downto 0);
initnopdly : std_logic_vector(7 downto 0); -- 400 ns delay
sync : std_logic;
odt : std_logic_vector(1 downto 0);
end record;
signal vcc, rwrite : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rdata, wdata, rwdata, rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal waddr2 : std_logic_vector(abuf-1 downto 0);
signal ddr_rst : std_logic;
signal ddr_rst_gen : std_logic_vector(3 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst); -- Reset signal in DDR clock domain
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
variable ready : std_logic;
begin
v := ra; v.hrdata := rdata; v.hresp := HRESP_OKAY;
v.write := '0';
-- Sync ------------------------------------------------
v.sync(1) := r.startsdold; v.sync(2) := ra.sync(1);
ready := ra.startsd_ack xor ra.sync(2);
--------------------------------------------------------
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else v.state := dwrite; v.hready := '1'; v.write := '1'; end if;
end if;
v.raddr := ra.haddr(7 downto 2);
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ready = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
v.state := midle; v.hready := not (v.hsel and v.htrans(1));
if (v.hsel and v.htrans(1) and v.hwrite) = '1' then
v.state := dwrite; v.hready := '1'; v.write := '1';
end if;
v.startsd_ack := ra.startsd;
end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.write := '1'; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or ((ra.haddr(4 downto 2) = "111") and (ra.write = '1')) then
v.startsd := not ra.startsd; v.state := whold1;
v.write := '0'; v.hready := not (v.hsel and v.htrans(1));
end if;
when whold1 =>
v.state := whold2;
when whold2 =>
if ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
v.startsd_ack := ra.startsd;
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.startsd_ack := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(ddr_rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable dqm : std_logic_vector(3 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable readdata: std_logic_vector(31 downto 0); -- data from DDR
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
readdata := sdi.data(31 downto 0);
v.qdrive :='0';
v.cfg.cal_en := (others => '0'); v.cfg.cal_inc := (others => '0');
v.cfg.cal_rst := '0';
v.wdata := wdata; -- pipeline output data
regsd := (others => '0');
if ra.acc.haddr(3 downto 2) = "00" then
regsd(31 downto 15) := r.cfg.refon & r.cfg.ocd & r.cfg.emr & '0' & r.cfg.trcd &
r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd(11 downto 0) := r.cfg.refresh;
elsif ra.acc.haddr(3 downto 2) = "01" then
regsd(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd(14 downto 12) := conv_std_logic_vector(1, 3);
else
regsd(17 downto 16) := r.cfg.readdly;
regsd(22 downto 18) := r.cfg.trfc;
regsd(27 downto 23) := r.cfg.twr;
regsd(28) := r.cfg.trp;
end if;
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(1 downto 0) is
when "00" => dqm := "0111";
when "01" => dqm := "1011";
when "10" => dqm := "1101";
when others => dqm := "1110";
end case;
when "01" =>
if ra.acc.haddr(1) = '0' then dqm := "0011"; else dqm := "1100"; end if;
when others => dqm := "0000";
end case;
-- Sync ------------------------------------------
v.sync := ra.startsd; v.startsd := r.sync;
--------------------------------------------------
--v.startsd := ra.startsd;
---- main FSM
--
-- case r.mstate is
-- when midle =>
-- if r.startsd = '1' then
-- if (r.sdstate = sidle) and (r.cfg.command = "000")
-- and (r.cmstate = midle) then
-- startsd := '1'; v.mstate := active;
-- end if;
-- end if;
-- when others => null;
-- end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(23 downto 10);
when "01" => raddr := haddr(24 downto 11);
when "10" => raddr := haddr(25 downto 12);
when others => raddr := haddr(26 downto 13);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "00000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish) then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2;
else v.sdstate := act3;
end if;
--v.waddr := ra.acc.haddr(7 downto 2);
v.waddr := ra.acc.haddr(7 downto 3) & '0'; --& ra.acc.haddr(2);
v.waddr_d := ra.acc.haddr(7 downto 3) & '0'; --& ra.acc.haddr(2);
when act2 =>
v.sdstate := act3;
when act3 =>
v.casn := '0';
--v.address := ra.acc.haddr(13 downto 11) & '0' & ra.acc.haddr(10 downto 2) & '0';
v.address := ra.acc.haddr(13 downto 11) & '0' & ra.acc.haddr(10 downto 3) & "00";
v.hready := ra.acc.hwrite;
if ra.acc.hwrite = '1' then
v.sdstate := wr0;
v.sdwen := '0';
v.waddr := r.waddr + 1;
v.trfc := r.cfg.twr;
else v.sdstate := rd1; end if;
v.burst := '0';
when wr0 =>
v.casn := '1'; v.sdwen := '1'; v.bdrive := '0'; v.qdrive := '1';
if r.waddr_d = ra.acc.haddr(7 downto 2) then
v.dqm := dqm;
v.waddr_d := r.waddr_d + 1;
v.waddr := r.waddr + 1;
v.sdstate := wr1;
if (r.waddr_d /= ra.raddr) then v.hready := '1'; end if;
else
v.burst := '1';
v.waddr_d := r.waddr_d + 1;
v.waddr := r.waddr + 1;
v.dqm := (others => '1');
end if;
if r.burst = '1' and r.address(5 downto 4) < ra.raddr(2 downto 1) then
v.address(5 downto 4) := r.address(5 downto 4) + 1;
v.sdwen := '0'; v.casn := '0';
v.trfc := r.cfg.twr;
end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr_d := r.waddr_d + 1;
v.waddr := r.waddr + 1;
if (r.waddr_d <= ra.raddr) and (r.waddr_d /= "000000") and (r.hready = '1') then
v.hready := '1';
v.burst := '0';
if r.burst = '0' and r.address(5 downto 4) < ra.raddr(2 downto 1) then
v.address(5 downto 4) := r.address(5 downto 4) + 1;
v.sdwen := '0'; v.casn := '0';
v.trfc := r.cfg.twr;
v.burst := '1';
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1');
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1'; v.qdrive := '1';
if r.trfc = "00000" then -- wait to not violate TWR timing
v.sdstate := wr4b;
end if;
when wr4b =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
v.newcom := '1';
when rd7 =>
v.casn := '1'; v.sdstate := rd8;
v.readdly := r.cfg.readdly;
v.newcom := not r.newcom;
if r.address(5 downto 4) /= "11" then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd8 => -- (CL = 3)
v.casn := '1';
v.newcom := not r.newcom;
if r.readdly = "00" then -- add read delay
v.sdstate := rd2;
else
v.readdly := r.readdly - 1;
end if;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
v.newcom := not r.newcom;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
v.newcom := not r.newcom;
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
v.newcom := not r.newcom;
if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1') then
v.burst := '0';
elsif (r.sdcsn = "11") or (r.waddr(1 downto 0) = "11") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
readdata := regsd; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
readdata := regsd; v.sdstate := sidle;
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := r.cfg.emr; --v.ba := "01";
--v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
if r.cfg.emr = "01" then
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd
& odtvalue(1)&"000"&odtvalue(0)&"00";
else
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
end if;
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00010" & r.cfg.dllrst & "0" & "01" & "10010"; -- CAS = 3 WR = 3
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "00000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
v.ba := "00"; v.cfg.ocd := '0'; v.cfg.emr := "10"; -- EMR(2)
if r.cfg.cke = '1' then
if r.initnopdly = "00000000" then -- 400 ns of NOP and CKE
v.istate := pre; v.cfg.command := CMD_PRE;
else
v.initnopdly := r.initnopdly - 1;
end if;
end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode23; else v.istate := lmode; end if;
end if;
when emode23 =>
if r.cfg.command = "000" then
if r.cfg.emr = "11" then
v.cfg.emr := "01"; -- (EMR(1))
v.istate := emode; v.cfg.command := CMD_EMR;
else
v.cfg.emr := "11"; v.cfg.command := CMD_EMR; -- EMR(3)
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := emodeocd;
v.cfg.ocd := '1'; v.cfg.command := CMD_EMR;
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when emodeocd =>
if r.cfg.command = "000" then
if r.cfg.ocd = '0' then -- Exit OCD
v.istate := finish;
v.cfg.refon := '1'; v.cfg.renable := '0';
else -- Default OCD
v.cfg.ocd := '0';
v.cfg.command := CMD_EMR;
end if;
end if;
v.cfg.cal_rst := '1'; -- reset data bit delay
when others =>
if odten /= 0 then v.odt := (others => '1'); end if;
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
v.initnopdly := (others => '1');
v.odt := (others => '0');
end if;
end case;
---- second part of main fsm
--
-- case r.mstate is
-- when active =>
-- if v.hready = '1' then
-- v.mstate := midle;
-- end if;
-- when others => null;
-- end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or (r.cfg.dllrst = '1') then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
if r.waddr(1 downto 0) = "00" then
v.cfg.refresh := r.wdata(11 downto 0);
v.cfg.cke := r.wdata(15);
v.cfg.renable := r.wdata(16);
v.cfg.dllrst := r.wdata(17);
v.cfg.command := r.wdata(20 downto 18);
v.cfg.csize := r.wdata(22 downto 21);
v.cfg.bsize := r.wdata(25 downto 23);
v.cfg.trcd := r.wdata(26);
v.cfg.emr := r.wdata(29 downto 28);
v.cfg.ocd := r.wdata(30);
v.cfg.refon := r.wdata(31);
elsif r.waddr(1 downto 0) = "10" then
v.cfg.cal_en := r.wdata( 7 downto 0);
v.cfg.cal_inc := r.wdata(15 downto 8);
v.cfg.readdly := r.wdata(17 downto 16);
v.cfg.trfc := r.wdata(22 downto 18);
v.cfg.twr := r.wdata(27 downto 23);
v.cfg.trp := r.wdata(28);
v.cfg.cal_rst := r.wdata(31);
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if ddr_rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
v.refresh := (others => '0');
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
v.cfg.ocd := '0';
v.cfg.readdly := conv_std_logic_vector(readdly, 2);
v.initnopdly := (others => '1');
if MHz > 130 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
if MHz > 130 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.odt := (others => '0');
end if;
ri <= v;
ribdrive <= vbdrive;
rwdata <= readdata;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst, ddr_rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
end if;
if (rst = '0') then
ddr_rst_gen <= "0000";
end if;
if (ddr_rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= "111111111111" & r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
--sdo.data <= zero32 & zero32 & zero32 & wdata;
sdo.data <= zero32 & zero32 & zero32 & r.wdata;
sdo.cal_en <= r.cfg.cal_en;
sdo.cal_inc <= r.cfg.cal_inc;
sdo.cal_rst <= r.cfg.cal_rst;
sdo.odt <= r.odt;
read_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr,
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr, datain => rwdata);
write_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr,
dataout => wdata, wclk => clk_ahb, write => ra.write,
waddress => ra.haddr(7 downto 2), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2sp" & tost(hindex) & ": 16-bit DDR2 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2sp16a
-- File: ddr2sp16a.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: 16-bit DDR2 memory controller with asych AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddr2sp16a is
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end;
architecture rtl of ddr2sp16a is
constant REVISION : integer := 0;
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant odtvalue : std_logic_vector(1 downto 0) := conv_std_logic_vector(odten, 2);
constant abuf : integer := 6;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_DDR2SP, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
type mcycletype is (midle, active, ext, leadout);
type ahb_state_type is (midle, rhold, dread, dwrite, whold1, whold2);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr0, wr1, wr2, wr3, wr4a, wr4b, wr4, wr5, sidle, ioreg1, ioreg2);
type icycletype is (iidle, pre, ref1, ref2, emode23, emode, lmode, emodeocd, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
cal_en : std_logic_vector(7 downto 0);
cal_inc : std_logic_vector(7 downto 0);
cal_rst : std_logic;
readdly : std_logic_vector(1 downto 0);
twr : std_logic_vector(4 downto 0);
emr : std_logic_vector(1 downto 0); -- selects EM register
ocd : std_ulogic; -- enable/disable ocd
end record;
type access_param is record
haddr : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
hio : std_ulogic;
end record;
-- local registers
type ahb_reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
hio : std_ulogic;
startsd : std_ulogic;
write : std_ulogic;
state : ahb_state_type;
haddr : std_logic_vector(31 downto 0);
hrdata : std_logic_vector(31 downto 0);
hwdata : std_logic_vector(31 downto 0);
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
raddr : std_logic_vector(abuf-1 downto 0);
size : std_logic_vector(1 downto 0);
acc : access_param;
sync : std_logic_vector(2 downto 1);
startsd_ack : std_logic;
end record;
type ddr_reg_type is record
startsd : std_ulogic;
startsdold : std_ulogic;
burst : std_ulogic;
hready : std_ulogic;
bdrive : std_ulogic;
qdrive : std_ulogic;
nbdrive : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
trfc : std_logic_vector(4 downto 0);
refresh : std_logic_vector(11 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(3 downto 0);
address : std_logic_vector(15 downto 2); -- memory address
ba : std_logic_vector(1 downto 0);
waddr : std_logic_vector(abuf-1 downto 0);
waddr_d : std_logic_vector(abuf-1 downto 0); -- Same as waddr but delayed to compensate for pipelined output data
cfg : sdram_cfg_type;
readdly : std_logic_vector(1 downto 0); -- added read latency
newcom : std_logic; -- start sec. read/write
wdata : std_logic_vector(31 downto 0);
initnopdly : std_logic_vector(7 downto 0); -- 400 ns delay
sync : std_logic;
odt : std_logic_vector(1 downto 0);
end record;
signal vcc, rwrite : std_ulogic;
signal r, ri : ddr_reg_type;
signal ra, rai : ahb_reg_type;
signal rdata, wdata, rwdata, rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal waddr2 : std_logic_vector(abuf-1 downto 0);
signal ddr_rst : std_logic;
signal ddr_rst_gen : std_logic_vector(3 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
begin
vcc <= '1';
ddr_rst <= (ddr_rst_gen(3) and ddr_rst_gen(2) and ddr_rst_gen(1) and rst); -- Reset signal in DDR clock domain
ahb_ctrl : process(rst, ahbsi, r, ra, rdata)
variable v : ahb_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dout : std_logic_vector(31 downto 0);
variable ready : std_logic;
begin
v := ra; v.hrdata := rdata; v.hresp := HRESP_OKAY;
v.write := '0';
-- Sync ------------------------------------------------
v.sync(1) := r.startsdold; v.sync(2) := ra.sync(1);
ready := ra.startsd_ack xor ra.sync(2);
--------------------------------------------------------
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.htrans := ahbsi.htrans; v.haddr := ahbsi.haddr;
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
if ahbsi.htrans(1) = '1' then
v.hio := ahbsi.hmbsel(1);
v.hsel := '1'; v.hready := '0';
end if;
end if;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
case ra.state is
when midle =>
if ((v.hsel and v.htrans(1)) = '1') then
if v.hwrite = '0' then
v.state := rhold; v.startsd := not ra.startsd;
else v.state := dwrite; v.hready := '1'; v.write := '1'; end if;
end if;
v.raddr := ra.haddr(7 downto 2);
if ahbsi.hready = '1' then
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
end if;
when rhold =>
v.raddr := ra.haddr(7 downto 2);
if ready = '1' then
v.state := dread; v.hready := '1'; v.raddr := ra.raddr + 1;
end if;
when dread =>
v.raddr := ra.raddr + 1; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or (ra.raddr(2 downto 0) = "000") then
v.state := midle; v.hready := not (v.hsel and v.htrans(1));
if (v.hsel and v.htrans(1) and v.hwrite) = '1' then
v.state := dwrite; v.hready := '1'; v.write := '1';
end if;
v.startsd_ack := ra.startsd;
end if;
v.acc := (v.haddr, v.size, v.hwrite, v.hio);
when dwrite =>
v.raddr := ra.haddr(7 downto 2); v.write := '1'; v.hready := '1';
if ((v.hsel and v.htrans(1) and v.htrans(0)) = '0')
or ((ra.haddr(4 downto 2) = "111") and (ra.write = '1')) then
v.startsd := not ra.startsd; v.state := whold1;
v.write := '0'; v.hready := not (v.hsel and v.htrans(1));
end if;
when whold1 =>
v.state := whold2;
when whold2 =>
if ready = '1' then
v.state := midle; v.acc := (v.haddr, v.size, v.hwrite, v.hio);
v.startsd_ack := ra.startsd;
end if;
end case;
v.hwdata := ahbsi.hwdata;
if (ahbsi.hready and ahbsi.hsel(hindex) ) = '1' then
if ahbsi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
dout := ra.hrdata(31 downto 0);
if rst = '0' then
v.hsel := '0';
v.hready := '1';
v.state := midle;
v.startsd := '0';
v.startsd_ack := '0';
v.hio := '0';
end if;
rai <= v;
ahbso.hready <= ra.hready;
ahbso.hresp <= ra.hresp;
ahbso.hrdata <= dout;
ahbso.hcache <= not ra.hio;
end process;
ddr_ctrl : process(ddr_rst, r, ra, sdi, rbdrive, wdata)
variable v : ddr_reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable dqm : std_logic_vector(3 downto 0);
variable raddr : std_logic_vector(13 downto 0);
variable adec : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_ulogic;
variable htrans : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable vbdrive : std_logic_vector(31 downto 0);
variable bdrive : std_ulogic;
variable writecfg: std_ulogic;
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable readdata: std_logic_vector(31 downto 0); -- data from DDR
begin
-- Variable default settings to avoid latches
v := r; v.hready := '0'; writecfg := '0'; vbdrive := rbdrive;
readdata := sdi.data(31 downto 0);
v.qdrive :='0';
v.cfg.cal_en := (others => '0'); v.cfg.cal_inc := (others => '0');
v.cfg.cal_rst := '0';
v.wdata := wdata; -- pipeline output data
regsd := (others => '0');
if ra.acc.haddr(3 downto 2) = "00" then
regsd(31 downto 15) := r.cfg.refon & r.cfg.ocd & r.cfg.emr & '0' & r.cfg.trcd &
r.cfg.bsize & r.cfg.csize & r.cfg.command &
r.cfg.dllrst & r.cfg.renable & r.cfg.cke;
regsd(11 downto 0) := r.cfg.refresh;
elsif ra.acc.haddr(3 downto 2) = "01" then
regsd(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd(14 downto 12) := conv_std_logic_vector(1, 3);
else
regsd(17 downto 16) := r.cfg.readdly;
regsd(22 downto 18) := r.cfg.trfc;
regsd(27 downto 23) := r.cfg.twr;
regsd(28) := r.cfg.trp;
end if;
-- generate DQM from address and write size
case ra.acc.size is
when "00" =>
case ra.acc.haddr(1 downto 0) is
when "00" => dqm := "0111";
when "01" => dqm := "1011";
when "10" => dqm := "1101";
when others => dqm := "1110";
end case;
when "01" =>
if ra.acc.haddr(1) = '0' then dqm := "0011"; else dqm := "1100"; end if;
when others => dqm := "0000";
end case;
-- Sync ------------------------------------------
v.sync := ra.startsd; v.startsd := r.sync;
--------------------------------------------------
--v.startsd := ra.startsd;
---- main FSM
--
-- case r.mstate is
-- when midle =>
-- if r.startsd = '1' then
-- if (r.sdstate = sidle) and (r.cfg.command = "000")
-- and (r.cmstate = midle) then
-- startsd := '1'; v.mstate := active;
-- end if;
-- end if;
-- when others => null;
-- end case;
startsd := r.startsd xor r.startsdold;
-- generate row and column address size
haddr := ra.acc.haddr;
haddr(31 downto 20) := haddr(31 downto 20) and not conv_std_logic_vector(hmask, 12);
case r.cfg.csize is
when "00" => raddr := haddr(23 downto 10);
when "01" => raddr := haddr(24 downto 11);
when "10" => raddr := haddr(25 downto 12);
when others => raddr := haddr(26 downto 13);
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(29 downto 22)) &
genmux(r.cfg.bsize, haddr(28 downto 21));
-- generate chip select
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
rams := adec & not adec;
-- sdram access FSM
if r.trfc /= "00000" then v.trfc := r.trfc - 1; end if;
case r.sdstate is
when sidle =>
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle)
and (r.istate = finish) then
v.address := raddr; v.ba := ba;
if ra.acc.hio = '0' then
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
else v.sdstate := ioreg1; end if;
end if;
v.waddr := ra.acc.haddr(7 downto 2);
when act1 =>
v.rasn := '1'; v.trfc := r.cfg.trfc;
if r.cfg.trcd = '1' then v.sdstate := act2;
else v.sdstate := act3;
end if;
--v.waddr := ra.acc.haddr(7 downto 2);
v.waddr := ra.acc.haddr(7 downto 3) & '0'; --& ra.acc.haddr(2);
v.waddr_d := ra.acc.haddr(7 downto 3) & '0'; --& ra.acc.haddr(2);
when act2 =>
v.sdstate := act3;
when act3 =>
v.casn := '0';
--v.address := ra.acc.haddr(13 downto 11) & '0' & ra.acc.haddr(10 downto 2) & '0';
v.address := ra.acc.haddr(13 downto 11) & '0' & ra.acc.haddr(10 downto 3) & "00";
v.hready := ra.acc.hwrite;
if ra.acc.hwrite = '1' then
v.sdstate := wr0;
v.sdwen := '0';
v.waddr := r.waddr + 1;
v.trfc := r.cfg.twr;
else v.sdstate := rd1; end if;
v.burst := '0';
when wr0 =>
v.casn := '1'; v.sdwen := '1'; v.bdrive := '0'; v.qdrive := '1';
if r.waddr_d = ra.acc.haddr(7 downto 2) then
v.dqm := dqm;
v.waddr_d := r.waddr_d + 1;
v.waddr := r.waddr + 1;
v.sdstate := wr1;
if (r.waddr_d /= ra.raddr) then v.hready := '1'; end if;
else
v.burst := '1';
v.waddr_d := r.waddr_d + 1;
v.waddr := r.waddr + 1;
v.dqm := (others => '1');
end if;
if r.burst = '1' and r.address(5 downto 4) < ra.raddr(2 downto 1) then
v.address(5 downto 4) := r.address(5 downto 4) + 1;
v.sdwen := '0'; v.casn := '0';
v.trfc := r.cfg.twr;
end if;
when wr1 =>
v.sdwen := '1'; v.casn := '1'; v.qdrive := '1';
v.waddr_d := r.waddr_d + 1;
v.waddr := r.waddr + 1;
if (r.waddr_d <= ra.raddr) and (r.waddr_d /= "000000") and (r.hready = '1') then
v.hready := '1';
v.burst := '0';
if r.burst = '0' and r.address(5 downto 4) < ra.raddr(2 downto 1) then
v.address(5 downto 4) := r.address(5 downto 4) + 1;
v.sdwen := '0'; v.casn := '0';
v.trfc := r.cfg.twr;
v.burst := '1';
end if;
else
v.sdstate := wr2;
v.dqm := (others => '1');
v.startsdold := r.startsd;
end if;
when wr2 =>
v.sdstate := wr3; v.qdrive := '1';
when wr3 =>
v.sdstate := wr4a; v.qdrive := '1';
when wr4a =>
v.bdrive := '1'; v.qdrive := '1';
if r.trfc = "00000" then -- wait to not violate TWR timing
v.sdstate := wr4b;
end if;
when wr4b =>
v.bdrive := '1';
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4; v.qdrive := '1';
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1'; v.qdrive := '0';
v.sdstate := wr5;
when wr5 =>
v.sdstate := sidle;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
v.newcom := '1';
when rd7 =>
v.casn := '1'; v.sdstate := rd8;
v.readdly := r.cfg.readdly;
v.newcom := not r.newcom;
if r.address(5 downto 4) /= "11" then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd8 => -- (CL = 3)
v.casn := '1';
v.newcom := not r.newcom;
if r.readdly = "00" then -- add read delay
v.sdstate := rd2;
else
v.readdly := r.readdly - 1;
end if;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
v.newcom := not r.newcom;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd3 =>
if fast = 0 then v.startsdold := r.startsd; end if;
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
v.newcom := not r.newcom;
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
v.newcom := not r.newcom;
if (r.sdcsn /= "11") and (r.waddr(1 downto 0) = "11") and (r.burst = '1') then
v.burst := '0';
elsif (r.sdcsn = "11") or (r.waddr(1 downto 0) = "11") then
v.dqm := (others => '1'); v.burst := '0';
if fast /= 0 then v.startsdold := r.startsd; end if;
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
end if;
end if;
if v.hready = '1' then v.waddr := r.waddr + 1; end if;
if r.address(5 downto 4) /= "11" and r.newcom = '1' then
v.casn := '0'; v.burst := '1'; v.address(5 downto 4) := r.address(5 downto 4) + 1;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
when rd6 =>
v.sdstate := sidle; v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when ioreg1 =>
readdata := regsd; v.sdstate := ioreg2;
if ra.acc.hwrite = '0' then v.hready := '1'; end if;
when ioreg2 =>
readdata := regsd; v.sdstate := sidle;
writecfg := ra.acc.hwrite; v.startsdold := r.startsd;
when others =>
v.sdstate := sidle;
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when CMD_PRE => -- precharge
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
when CMD_REF => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when CMD_EMR => -- load-ext-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := r.cfg.emr; --v.ba := "01";
--v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
if r.cfg.emr = "01" then
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd
& odtvalue(1)&"000"&odtvalue(0)&"00";
else
v.address := "0000"&r.cfg.ocd&r.cfg.ocd&r.cfg.ocd&"0000000";
end if;
when CMD_LMR => -- load-mode-reg
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active; v.ba := "00";
v.address := "00010" & r.cfg.dllrst & "0" & "01" & "10010"; -- CAS = 3 WR = 3
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; v.cfg.command := "000";
v.cmstate := leadout; v.trfc := r.cfg.trfc;
when others =>
if r.trfc = "00000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
if r.cfg.renable = '1' then
v.cfg.cke := '1'; v.cfg.dllrst := '1';
v.ba := "00"; v.cfg.ocd := '0'; v.cfg.emr := "10"; -- EMR(2)
if r.cfg.cke = '1' then
if r.initnopdly = "00000000" then -- 400 ns of NOP and CKE
v.istate := pre; v.cfg.command := CMD_PRE;
else
v.initnopdly := r.initnopdly - 1;
end if;
end if;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "11" & r.cfg.dllrst; -- CMD_LMR/CMD_EMR
if r.cfg.dllrst = '1' then v.istate := emode23; else v.istate := lmode; end if;
end if;
when emode23 =>
if r.cfg.command = "000" then
if r.cfg.emr = "11" then
v.cfg.emr := "01"; -- (EMR(1))
v.istate := emode; v.cfg.command := CMD_EMR;
else
v.cfg.emr := "11"; v.cfg.command := CMD_EMR; -- EMR(3)
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := lmode; v.cfg.command := CMD_LMR;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.dllrst = '1' then
if r.refresh(9 downto 8) = "00" then -- > 200 clocks delay
v.cfg.command := CMD_PRE; v.istate := ref1;
end if;
else
v.istate := emodeocd;
v.cfg.ocd := '1'; v.cfg.command := CMD_EMR;
end if;
end if;
when ref1 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.cfg.dllrst := '0'; v.istate := ref2;
end if;
when ref2 =>
if r.cfg.command = "000" then
v.cfg.command := CMD_REF; v.istate := pre;
end if;
when emodeocd =>
if r.cfg.command = "000" then
if r.cfg.ocd = '0' then -- Exit OCD
v.istate := finish;
v.cfg.refon := '1'; v.cfg.renable := '0';
else -- Default OCD
v.cfg.ocd := '0';
v.cfg.command := CMD_EMR;
end if;
end if;
v.cfg.cal_rst := '1'; -- reset data bit delay
when others =>
if odten /= 0 then v.odt := (others => '1'); end if;
if r.cfg.renable = '1' then
v.istate := iidle; v.cfg.dllrst := '1';
v.initnopdly := (others => '1');
v.odt := (others => '0');
end if;
end case;
---- second part of main fsm
--
-- case r.mstate is
-- when active =>
-- if v.hready = '1' then
-- v.mstate := midle;
-- end if;
-- when others => null;
-- end case;
-- sdram refresh counter
if ((r.cfg.refon = '1') and (r.istate = finish)) or (r.cfg.dllrst = '1') then
v.refresh := r.refresh - 1;
if (v.refresh(11) and not r.refresh(11)) = '1' then
v.refresh := r.cfg.refresh;
if r.cfg.dllrst = '0' then v.cfg.command := "100"; end if;
end if;
end if;
-- AHB register access
if (ra.acc.hio and ra.acc.hwrite and writecfg) = '1' then
if r.waddr(1 downto 0) = "00" then
v.cfg.refresh := r.wdata(11 downto 0);
v.cfg.cke := r.wdata(15);
v.cfg.renable := r.wdata(16);
v.cfg.dllrst := r.wdata(17);
v.cfg.command := r.wdata(20 downto 18);
v.cfg.csize := r.wdata(22 downto 21);
v.cfg.bsize := r.wdata(25 downto 23);
v.cfg.trcd := r.wdata(26);
v.cfg.emr := r.wdata(29 downto 28);
v.cfg.ocd := r.wdata(30);
v.cfg.refon := r.wdata(31);
elsif r.waddr(1 downto 0) = "10" then
v.cfg.cal_en := r.wdata( 7 downto 0);
v.cfg.cal_inc := r.wdata(15 downto 8);
v.cfg.readdly := r.wdata(17 downto 16);
v.cfg.trfc := r.wdata(22 downto 18);
v.cfg.twr := r.wdata(27 downto 23);
v.cfg.trp := r.wdata(28);
v.cfg.cal_rst := r.wdata(31);
end if;
end if;
v.nbdrive := not v.bdrive;
if oepol = 1 then bdrive := r.nbdrive; vbdrive := (others => v.nbdrive);
else bdrive := r.bdrive; vbdrive := (others => v.bdrive);end if;
-- reset
if ddr_rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := finish;
v.cmstate := midle;
v.cfg.command := "000";
v.cfg.csize := conv_std_logic_vector(col-9, 2);
v.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
v.cfg.refon := '0';
v.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
v.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
v.cfg.twr := conv_std_logic_vector((15)*MHz/1000+3, 5);
v.refresh := (others => '0');
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '0';
v.startsd := '0';
v.startsdold := '0';
v.cfg.dllrst := '0';
v.cfg.cke := '0';
v.cfg.ocd := '0';
v.cfg.readdly := conv_std_logic_vector(readdly, 2);
v.initnopdly := (others => '1');
if MHz > 130 then v.cfg.trcd := '1'; else v.cfg.trcd := '0'; end if;
if MHz > 130 then v.cfg.trp := '1'; else v.cfg.trp := '0'; end if;
if pwron = 1 then v.cfg.renable := '1';
else v.cfg.renable := '0'; end if;
v.odt := (others => '0');
end if;
ri <= v;
ribdrive <= vbdrive;
rwdata <= readdata;
end process;
sdo.sdcke <= (others => r.cfg.cke);
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
ahbregs : process(clk_ahb) begin
if rising_edge(clk_ahb) then
ra <= rai;
end if;
end process;
ddrregs : process(clk_ddr, rst, ddr_rst) begin
if rising_edge(clk_ddr) then
r <= ri; rbdrive <= ribdrive;
ddr_rst_gen <= ddr_rst_gen(2 downto 0) & '1';
end if;
if (rst = '0') then
ddr_rst_gen <= "0000";
end if;
if (ddr_rst = '0') then
r.sdcsn <= (others => '1'); r.bdrive <= '1'; r.nbdrive <= '0';
if oepol = 0 then rbdrive <= (others => '1');
else rbdrive <= (others => '0'); end if;
r.cfg.cke <= '0';
end if;
end process;
sdo.address <= '0' & ri.address;
sdo.ba <= ri.ba;
sdo.bdrive <= r.nbdrive when oepol = 1 else r.bdrive;
sdo.qdrive <= not (ri.qdrive or r.nbdrive);
sdo.vbdrive <= rbdrive;
sdo.sdcsn <= ri.sdcsn;
sdo.sdwen <= ri.sdwen;
sdo.dqm <= "111111111111" & r.dqm;
sdo.rasn <= ri.rasn;
sdo.casn <= ri.casn;
--sdo.data <= zero32 & zero32 & zero32 & wdata;
sdo.data <= zero32 & zero32 & zero32 & r.wdata;
sdo.cal_en <= r.cfg.cal_en;
sdo.cal_inc <= r.cfg.cal_inc;
sdo.cal_rst <= r.cfg.cal_rst;
sdo.odt <= r.odt;
read_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rai.raddr,
dataout => rdata, wclk => clk_ddr, write => ri.hready,
waddress => r.waddr, datain => rwdata);
write_buff : syncram_2p
generic map (tech => memtech, abits => 6, dbits => 32, sepclk => 1, wrfst => 0)
port map ( rclk => clk_ddr, renable => vcc, raddress => r.waddr,
dataout => wdata, wclk => clk_ahb, write => ra.write,
waddress => ra.haddr(7 downto 2), datain => ahbsi.hwdata);
-- pragma translate_off
bootmsg : report_version
generic map (
msg1 => "ddr2sp" & tost(hindex) & ": 16-bit DDR2 controller rev " &
tost(REVISION) & ", " & tost(Mbyte) & " Mbyte, " & tost(MHz) &
" MHz DDR clock");
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: l3stat
-- File: l3stat.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: LEON3 statistic counters
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
entity l3stat is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncnt : integer range 1 to 64 := 4;
ncpu : integer := 1;
nmax : integer := 0;
lahben : integer := 0;
dsuen : integer := 0;
nextev : integer range 0 to 16 := 0;
apb2en : integer := 0;
pindex2 : integer := 0;
paddr2 : integer := 0;
pmask2 : integer := 16#fff#;
astaten : integer := 0;
selreq : integer := 0;
clatch : integer := 0;
forcer0 : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
dbgo : in l3_debug_out_vector(0 to NCPU-1);
dsuo : in dsu_out_type := dsu_out_none;
stati : in l3stat_in_type := l3stat_in_none;
apb2i : in apb_slv_in_type := apb_slv_in_none;
apb2o : out apb_slv_out_type;
astat : in amba_stat_type := amba_stat_none
);
end;
architecture rtl of l3stat is
constant REVISION : integer := 1 - forcer0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_L3STAT, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant pconfig2 : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_L3STAT, 0, REVISION, 0),
1 => apb_iobar(paddr2, pmask2));
constant MAX_CNT : natural := 64 - 32*forcer0; -- Maximum number of counters
constant MADDR : natural := log2(MAX_CNT) + 2;
function op_len return integer is
begin
if selreq /= 0 then return 8; end if;
return 7;
end function op_len;
constant LATCH_CNT : boolean := clatch /= 0;
type cnt_type is record
cpu : std_logic_vector(3 downto 0);
op : std_logic_vector(op_len-1 downto 0);
en : std_logic;
clr : std_logic;
inc : std_logic;
cnt : std_logic_vector(31 downto 0);
suen : std_logic_vector(1 downto 0);
end record;
type mcnt_type is record
el : std_ulogic;
cd : std_ulogic;
max : std_logic_vector(31 downto 0);
end record;
type reg_type is record
hmaster : std_logic_vector(3 downto 0);
active : std_logic;
latcnt : std_logic;
timer : std_logic_vector(31 downto 0);
end record;
constant cnt_none : cnt_type := ("0000", zero32(op_len-1 downto 0),
'0', '0', '0', zero32, "00");
constant mcnt_none : mcnt_type := ('0', '0', zero32);
type cnt_type_vector is array (natural range <>) of cnt_type;
type mcnt_type_vector is array (natural range <>) of mcnt_type;
function calc_inc(
cnt : cnt_type;
dbgox : l3_debug_out_vector(0 to 15);
r : reg_type;
dastat : dsu_astat_type;
ev : std_logic_vector(15 downto 0);
esource: l3stat_src_array;
astat : amba_stat_type;
req : std_logic_vector(15 downto 0);
sel : std_logic_vector(15 downto 0)) return std_logic is
variable wbhold, inc, icnt, fcnt, bpmiss, dsumode : std_logic;
variable istat, dstat : l3_cstat_type;
variable cpu : natural range 0 to 15;
variable inst : std_logic_vector(5 downto 0);
variable su : std_logic;
variable op : std_logic_vector(5 downto 0);
begin
cpu := conv_integer(cnt.cpu); wbhold := dbgox(cpu).wbhold;
istat := dbgox(cpu).istat; dstat := dbgox(cpu).dstat;
icnt := dbgox(cpu).icnt; fcnt := dbgox(cpu).fcnt;
inst := dbgox(cpu).optype; bpmiss := dbgox(cpu).bpmiss;
dsumode := dbgox(cpu).dsumode;
su := dbgox(cpu).su;
inc := '0';
op := cnt.op(5 downto 0);
if selreq = 0 or cnt.op(cnt.op'left) = '0' then
if (nextev = 0 and dsuen = 0 and astaten = 0) or cnt.op(6) = '0' then
case op is
when "000000" => inc := istat.cmiss; -- icache miss
when "000001" => inc := istat.tmiss; -- icache tlb miss
when "000010" => inc := istat.chold; -- icache total hold
when "000011" => inc := istat.mhold; -- icache MMU hold
when "001000" => inc := dstat.cmiss;
when "001001" => inc := dstat.tmiss;
when "001010" => inc := dstat.chold;
when "001011" => inc := dstat.mhold;
when "010000" => inc := wbhold; -- dcache write buffer hold
when "010001" => inc := icnt; -- total number of instructions
when "010010" => inc := icnt and not fcnt; -- integer instructions
when "010011" => inc := fcnt; -- FPU instructions
when "010100" => inc := bpmiss; -- branch prediction miss
when "010101" => inc := not dsumode; -- total cycles
when "010111" => -- AHB utilization per master
if lahben /= 0 then
if (r.active = '1') and (r.hmaster = cnt.cpu) then inc := '1'; end if;
end if;
when "011000" => -- Total AHB utilization
if lahben /= 0 then
if (r.active = '1') then inc := '1'; end if;
end if;
when "100010" => -- integer branches
if inst(5 downto 1) = "00010" then inc := icnt; end if;
when "101000" => -- CALL
if inst(5 downto 4) = "01" then inc := icnt; end if;
when "110000" => -- Normal instructions
if inst(5 downto 4) = "10" then inc := icnt; end if;
when "111000" => -- load & store
if inst(5 downto 4) = "11" then inc := icnt; end if;
when "111001" => -- load
if (inst(5 downto 4) = "11") and ((inst(0) = '0') or inst(1) = '1') then inc := icnt; end if;
when "111010" => -- store
if (inst(5 downto 4) = "11") and (inst(0) = '1') then inc := icnt; end if;
when others => null;
end case;
case cnt.suen is
when "01" => if su = '0' then inc := '0'; end if;
when "10" => if su = '1' then inc := '0'; end if;
when others => null;
end case;
elsif dsuen /= 0 and cnt.op(6 downto 5) = "10" then
case op(4 downto 0) is
when "00000" => inc := dastat.idle;
when "00001" => inc := dastat.busy;
when "00010" => inc := dastat.nseq;
when "00011" => inc := dastat.seq;
when "00100" => inc := dastat.read;
when "00101" => inc := dastat.write;
when "00110" => inc := dastat.hsize(0);
when "00111" => inc := dastat.hsize(1);
when "01000" => inc := dastat.hsize(2);
when "01001" => inc := dastat.hsize(3);
when "01010" => inc := dastat.hsize(4);
when "01011" => inc := dastat.hsize(5);
when "01100" => inc := dastat.ws;
when "01101" => inc := dastat.retry;
when "01110" => inc := dastat.split;
when "01111" => inc := dastat.spdel;
when "10000" => inc := dastat.locked;
when others => null;
end case;
if cnt.suen(1) = '1' and cnt.cpu /= dastat.hmaster then
inc := '0';
end if;
elsif astaten /= 0 and cnt.op(6 downto 4) = "111" then -- 0x70 - 0x7F
case op(3 downto 0) is
when "0000" => inc := astat.idle;
when "0001" => inc := astat.busy;
when "0010" => inc := astat.nseq;
when "0011" => inc := astat.seq;
when "0100" => inc := astat.read;
when "0101" => inc := astat.write;
when "0110" => inc := astat.hsize(0);
when "0111" => inc := astat.hsize(1);
when "1000" => inc := astat.hsize(2);
when "1001" => inc := astat.hsize(3);
when "1010" => inc := astat.hsize(4);
when "1011" => inc := astat.hsize(5);
when "1100" => inc := astat.ws;
when "1101" => inc := astat.retry;
when "1110" => inc := astat.split;
when "1111" => inc := astat.spdel;
when others => null;
end case;
if cnt.suen(1) = '1' and cnt.cpu /= astat.hmaster then
inc := '0';
end if;
elsif nextev /= 0 then -- 0x60 - 0x6F
-- External event 0 to 15
for i in 0 to 15 loop
if i >= nextev then
exit;
end if;
if i = conv_integer(cnt.op(3 downto 0)) then
if cnt.suen(1) = '0' or cnt.cpu = esource(i) then
inc := ev(i);
end if;
end if;
end loop;
end if;
end if;
if selreq /= 0 and cnt.op(cnt.op'left) = '1' then
-- Possible extensions to the below:
-- - add check for when OP(3:0).hbusreq and AHBM.hbusreq is asserted at
-- the same time
-- - also take supervisor/usermode into account
-- - do not only check on bus master but also/instead on MMU context ID
for i in 0 to selreq loop
for j in 0 to selreq loop
if (i = conv_integer(cnt.op(3 downto 0)) and
j = conv_integer(cnt.cpu)) then
inc := req(j) and (sel(i) xor cnt.op(4));
end if;
end loop;
end loop;
end if;
return(inc);
end;
function nmax_right return integer is
begin
if nmax /= 0 then return nmax-1; end if;
return 0;
end function;
function latch_cnt_addr (paddr : std_logic_vector(31 downto 0)) return boolean is
begin
return LATCH_CNT and paddr(MADDR+1) = '1';
end function;
signal rc, rcin : cnt_type_vector(0 to ncnt-1);
signal mrc, mrcin : mcnt_type_vector(0 to nmax_right);
signal r, rin : reg_type;
begin
comb : process(r, rc, mrc, rstn, apbi, dbgo, stati, astat)
variable rdata : std_logic_vector(31 downto 0);
variable rdata2 : std_logic_vector(31 downto 0);
variable rv : cnt_type_vector(0 to MAX_CNT-1);
variable mrv : mcnt_type_vector(0 to MAX_CNT-1);
variable lrc : cnt_type_vector(0 to MAX_CNT-1);
variable lmrc : mcnt_type_vector(0 to MAX_CNT-1);
variable v : reg_type;
variable addr : natural;
variable addr2 : natural;
variable dbgol : l3_debug_out_vector(0 to 15);
begin
for i in 0 to MAX_CNT-1 loop
rv(i) := cnt_none; mrv(i) := mcnt_none;
lrc(i) := cnt_none; lmrc(i) := mcnt_none;
end loop;
rv(0 to ncnt-1) := rc; mrv(0 to nmax_right) := mrc; v := r;
lrc(0 to ncnt-1) := rc; lmrc(0 to nmax_right) := mrc;
addr := conv_integer(apbi.paddr(MADDR-1 downto 2));
rdata := zero32; rdata2 := zero32; v.latcnt := '0'; v.timer := (others => '0');
if LATCH_CNT then
v.latcnt := stati.latcnt;
if r.latcnt = '1' then v.timer := stati.timer; end if;
end if;
for i in 0 to ncpu-1 loop dbgol(i) := dbgo(i); end loop;
for i in ncpu to 15 loop dbgol(i) := l3_dbgo_none; end loop;
for i in 0 to ncnt-1 loop
rv(i).inc := calc_inc(rc(i), dbgol, r, dsuo.astat, stati.event, stati.esource,
astat, stati.req, stati.sel) and rc(i).en;
if nmax = 0 or i >= nmax or mrc(i).cd = '0' then
if rc(i).inc = '1' then rv(i).cnt := rc(i).cnt + 1; end if;
elsif nmax /= 0 and i < nmax then
-- count maximum duration
if (rc(i).en = '1') then
if rc(i).inc = mrc(i).el then
rv(i).cnt := rc(i).cnt + 1;
else
rv(i).cnt := zero32;
end if;
if rc(i).cnt > mrc(i).max then
mrv(i).max := rc(i).cnt;
end if;
end if;
end if;
if LATCH_CNT and r.latcnt = '1' and nmax /= 0 and i < nmax then
if mrc(i).cd = '0' then
mrv(i).max := rv(i).cnt;
if rc(i).clr = '1' then rv(i).cnt := (others => '0'); end if;
end if;
end if;
end loop;
if apb2en /= 0 then -- 2nd APB interface
addr2 := conv_integer(apb2i.paddr(MADDR-1 downto 2));
if (apb2i.psel(pindex2) and apb2i.penable) = '1' and (not latch_cnt_addr(apb2i.paddr)) then
if apb2i.pwrite = '0' then
if apb2i.paddr(MADDR) = '0' then
rdata2 := lrc(addr2).cnt;
if nmax = 0 or lmrc(addr2).cd = '0' then
rdata2 := lrc(addr2).cnt;
else
rdata2 := lmrc(addr2).max;
end if;
if rv(addr2).clr = '1' then
rv(addr2).cnt := zero32;
if nmax /= 0 and nmax > addr2 then mrv(addr2).max := zero32; end if;
end if;
else
if REVISION = 0 then
rdata2(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
rdata2(27 downto 23) := conv_std_logic_vector(ncnt-1, 5);
else
rdata2(31 downto 23) := conv_std_logic_vector(ncnt-1, 9);
end if;
rdata2(22) := conv_std_logic(nmax > addr2);
rdata2(21) := conv_std_logic(lahben /= 0);
rdata2(20) := conv_std_logic(dsuen /= 0);
rdata2(19) := conv_std_logic(nextev /= 0);
rdata2(18) := conv_std_logic(astaten /= 0);
if nmax /= 0 and nmax > addr2 then
rdata2(17) := lmrc(addr2).el;
rdata2(16) := lmrc(addr2).cd;
end if;
rdata2(15 downto 14) := lrc(addr2).suen;
rdata2(13) := lrc(addr2).clr;
rdata2(12) := lrc(addr2).en;
rdata2(11 downto 4) := (others => '0');
rdata2(4+op_len-1 downto 4) := lrc(addr2).op;
rdata2(3 downto 0) := lrc(addr2).cpu;
end if;
else
if apb2i.paddr(MADDR) = '0' then
rv(addr2).cnt := apb2i.pwdata;
if nmax /= 0 and nmax > addr2 then mrv(addr2).max := apbi.pwdata; end if;
else
if nmax /= 0 and nmax > addr2 then
mrv(addr2).el := apb2i.pwdata(17);
mrv(addr2).cd := apb2i.pwdata(16);
end if;
rv(addr2).suen := apb2i.pwdata(15 downto 14);
rv(addr2).clr := apb2i.pwdata(13);
rv(addr2).en := apb2i.pwdata(12);
rv(addr2).op := apb2i.pwdata(4+op_len-1 downto 4);
rv(addr2).cpu := apb2i.pwdata(3 downto 0);
end if;
end if;
end if;
if latch_cnt_addr(apb2i.paddr) and (apb2i.psel(pindex2) and apb2i.penable) = '1' then
if apb2i.paddr(7) = '0' then
rdata2 := lmrc(addr2).max;
else
rdata := r.timer;
end if;
v.latcnt := v.latcnt or apb2i.pwrite;
end if;
else
addr2 := 0;
end if;
if (apbi.psel(pindex) and apbi.penable) = '1' and (not latch_cnt_addr(apbi.paddr)) then
if apbi.pwrite = '0' then
if apbi.paddr(MADDR) = '0' then
if nmax = 0 or lmrc(addr).cd = '0' then
rdata := lrc(addr).cnt;
else
rdata := lmrc(addr).max;
end if;
if rv(addr).clr = '1' then
rv(addr).cnt := zero32;
if nmax /= 0 and nmax > addr then mrv(addr).max := zero32; end if;
end if;
else
if REVISION = 0 then
rdata(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
rdata(27 downto 23) := conv_std_logic_vector(ncnt-1, 5);
else
rdata(31 downto 23) := conv_std_logic_vector(ncnt-1, 9);
end if;
rdata(22) := conv_std_logic(nmax > addr);
rdata(21) := conv_std_logic(lahben /= 0);
rdata(20) := conv_std_logic(dsuen /= 0);
rdata(19) := conv_std_logic(nextev /= 0);
rdata(18) := conv_std_logic(astaten /= 0);
if nmax /= 0 and nmax > addr then
rdata(17) := lmrc(addr).el;
rdata(16) := lmrc(addr).cd;
end if;
rdata(15 downto 14) := lrc(addr).suen;
rdata(13) := lrc(addr).clr;
rdata(12) := lrc(addr).en;
rdata(11 downto 4) := (others => '0');
rdata(4+op_len-1 downto 4) := lrc(addr).op;
rdata(3 downto 0) := lrc(addr).cpu;
end if;
else
if apbi.paddr(MADDR) = '0' then
rv(addr).cnt := apbi.pwdata;
if nmax /= 0 and nmax > addr then mrv(addr).max := apbi.pwdata; end if;
else
if nmax /= 0 and nmax > addr then
mrv(addr).el := apbi.pwdata(17);
mrv(addr).cd := apbi.pwdata(16);
end if;
rv(addr).suen := apbi.pwdata(15 downto 14);
rv(addr).clr := apbi.pwdata(13);
rv(addr).en := apbi.pwdata(12);
rv(addr).op := apbi.pwdata(4+op_len-1 downto 4);
rv(addr).cpu := apbi.pwdata(3 downto 0);
end if;
end if;
if latch_cnt_addr(apbi.paddr) and (apbi.psel(pindex) and apbi.penable) = '1' then
if apbi.paddr(MADDR) = '0' then
rdata:= lmrc(addr).max;
else
rdata := r.timer;
end if;
v.latcnt := v.latcnt or apbi.pwrite;
end if;
end if;
if lahben /= 0 then
if ahbsi.hready = '1' then
if ahbsi.htrans(1) = '1' then v.active := '1'; v.hmaster := ahbsi.hmaster;
else v.active := '0'; end if;
end if;
else
v.active := '0'; v.hmaster := (others => '0');
end if;
if rstn = '0' then
for i in 0 to ncnt-1 loop rv(i).en := '0'; rv(i).inc := '0'; end loop;
if lahben /= 0 then v.active := '0'; end if;
end if;
if nextev = 0 and dsuen = 0 and astaten = 0 then
for i in 0 to ncnt-1 loop rv(i).op(6) := '0'; end loop;
end if;
rcin <= rv(0 to ncnt-1); mrcin <= mrv(0 to nmax_right); rin <= v;
apbo.prdata <= rdata; -- drive apb read bus
apbo.pirq <= (others => '0');
apb2o.prdata <= rdata2;
apb2o.pirq <= (others => '0');
end process;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
apb2o.pindex <= pindex2;
apb2o.pconfig <= pconfig2;
regs : process(clk)
begin
if rising_edge(clk) then
rc <= rcin;
end if;
end process;
mregs : if nmax /= 0 generate
regs : process(clk)
begin
if rising_edge(clk) then
mrc <= mrcin;
end if;
end process;
end generate;
nomregs : if nmax = 0 generate
mrc(0) <= mcnt_none;
end generate;
ahbregs : if lahben /= 0 or LATCH_CNT generate
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end generate;
noahbregs : if lahben = 0 and not LATCH_CNT generate
r <= ((others => '0'), '0', '0', (others => '0'));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("lstat_" & tost(pindex) & ": " &
"LEON Statistics Unit, " & "ncpu : " & tost(ncpu) &
", ncnt : " & tost(ncnt) & ", rev " & tost(REVISION));
-- pragma translate_on
-- pragma translate_off
cproc : process
begin
assert (clatch = 0) or (pmask /= 16#fff# and nmax /= 0)
report "LSTAT: clatch /= 0 requires pmask /= 16#fff# and nmax /= 0"
severity failure;
wait;
assert (REVISION = 1 and pmask <= 16#ffc#) or (REVISION = 0)
report "LSTAT: REVISION 1 of core requires pmask = 16#ffc# or larger area"
severity failure;
wait;
end process;
-- pragma translate_on
end;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: closest_to_point_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.filtering_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity closest_to_point_top is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
point : in data_type_ext; -- assume always ext!!
point_list_d : in data_type; -- assume FIFO interface !!!
point_list_idx : in centre_index_type;
max_idx : out centre_index_type;
min_point : out data_type;
min_index : out centre_index_type;
point_list_d_out : out data_type; -- feed input to output
point_list_idx_out : out centre_index_type; -- feed input to output
u_out : out node_data_type;
closest_n_first_rdy : out std_logic;
point_list_rdy : out std_logic
);
end closest_to_point_top;
architecture Behavioral of closest_to_point_top is
type state_type is (idle, processing);
constant LAT_DOT_PRODUCT : integer := MUL_CORE_LATENCY+2*integer(ceil(log2(real(D))));
constant LAT_SUB : integer := 2;
constant LATENCY : integer := LAT_DOT_PRODUCT+LAT_SUB;
type node_data_delay_type is array(0 to LATENCY-1) of node_data_type;
component compute_distance_top
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type_ext;
point_2 : in data_type_ext;
point_2_idx : in centre_index_type;
distance : out coord_type_ext;
point_1_out : out data_type_ext;
point_2_out : out data_type_ext;
point_2_idx_out : out centre_index_type;
rdy : out std_logic
);
end component;
component min_search is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
metric_in : in coord_type_ext;
u_in : in node_data_type;
point_in : in data_type;
point_idx_in : in centre_index_type;
min_point : out data_type;
min_index : out centre_index_type;
max_idx : out centre_index_type;
u_out : out node_data_type;
rdy : out std_logic
);
end component;
signal reg_u_in : node_data_type;
signal reg_point : data_type_ext;
signal reg_point_list_d : data_type;
signal reg_point_list_idx : centre_index_type;
signal state : state_type;
signal compute_distance_nd : std_logic;
signal compute_distance_rdy : std_logic;
signal distance : coord_type_ext;
signal point_list_d_delayed_ext : data_type_ext;
signal point_list_d_delayed : data_type;
signal point_list_idx_delayed : centre_index_type;
signal tmp_min_index : centre_index_type;
signal tmp_min_point : data_type;
signal tmp_min_search_rdy : std_logic;
signal node_data_delay : node_data_delay_type;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= idle;
elsif state = idle AND nd='1' then
state <= processing;
elsif state = processing AND nd='0' then
state <= idle;
end if;
end if;
end process fsm_proc;
-- need to delay by one cycle due to state machine
reg_point_list_d_proc : process(clk)
begin
if rising_edge(clk) then
if state = idle AND nd='1' then
reg_u_in <= u_in;
reg_point <= point;
end if;
reg_point_list_d <= point_list_d;
reg_point_list_idx <= point_list_idx;
end if;
end process reg_point_list_d_proc;
compute_distance_nd <= '1' WHEN state = processing ELSE '0';
compute_distance_top_inst : compute_distance_top
port map (
clk => clk,
sclr => sclr,
nd => compute_distance_nd,
point_1 => reg_point,
point_2 => conv_normal_2_ext(reg_point_list_d),
point_2_idx => reg_point_list_idx,
distance => distance,
point_1_out => open,
point_2_out => point_list_d_delayed_ext,
point_2_idx_out => point_list_idx_delayed,
rdy => compute_distance_rdy
);
point_list_d_delayed <= conv_ext_2_normal(point_list_d_delayed_ext);
-- feed u_in from input of dot-product to output of dot-product
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
node_data_delay(0) <= reg_u_in;
node_data_delay(1 to LATENCY-1) <= node_data_delay(0 to LATENCY-2);
end if;
end process data_delay_proc;
-- search min
min_search_inst : min_search
port map (
clk => clk,
sclr => sclr,
nd => compute_distance_rdy,
metric_in => distance,
u_in => node_data_delay(LATENCY-1),
point_in => point_list_d_delayed,
point_idx_in => point_list_idx_delayed,
min_point => tmp_min_point,
min_index => tmp_min_index,
max_idx => max_idx,
u_out => u_out,
rdy => tmp_min_search_rdy
);
min_point <= tmp_min_point;
min_index <= tmp_min_index;
closest_n_first_rdy <= tmp_min_search_rdy;
point_list_d_out <= point_list_d_delayed;
point_list_idx_out <= point_list_idx_delayed;
point_list_rdy <= compute_distance_rdy;
end Behavioral;
|
-- Design unit: reverb buffer
-- Authors : Aaron Arnason, Byron Maroney, Edrick De Guzman
-- reverbBuffer.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity reverbBuffer is
generic (
AUTO_CLOCK_CLOCK_RATE : string := "-1";
base_addr : std_logic_vector(31 downto 0) := X"00000000";
buffersize : std_logic_vector(31 downto 0) := X"000014A4"
);
port (
avm_m0_address : out std_logic_vector(31 downto 0);
avm_m0_read : out std_logic;
avm_m0_waitrequest : in std_logic := '0';
avm_m0_readdata : in std_logic_vector(15 downto 0) := (others => '0');
avm_m0_write : out std_logic;
avm_m0_writedata : out std_logic_vector(15 downto 0);
avm_m0_readdatavalid : in std_logic := '0';
dsp_ready : in std_logic;
dsp_in : in std_logic_vector(15 downto 0);
dsp_done : out std_logic;
dsp_out : out std_logic_vector(15 downto 0);
dsp_delayed_valid : out std_logic;
dsp_delayed : out std_logic_vector(15 downto 0);
clk : in std_logic := '0';
reset : in std_logic := '0'
);
end entity reverbBuffer;
architecture rtl of reverbBuffer is
type state is (idle, reading, reading2, writing);
signal current_state: state;
signal original,delayed: std_logic_vector(15 downto 0);
signal read_addr, read_delayed,write_addr: std_logic_vector(31 downto 0) := base_addr;
signal read_flag : std_logic := '0';
constant offset : std_logic_vector(31 downto 0) := std_logic_vector(signed(base_addr)+ 16);
begin
fsm: process(clk,reset)
begin
if reset = '0' then
write_addr <= base_addr;
read_addr <= offset;
current_state <= idle;
read_flag <= '0';
elsif rising_edge(clk) then
case current_state is
when idle =>
if dsp_ready = '1' then -- I have data avail.
avm_m0_write <= '1'; -- Telling the SDRAM we're writing to it.
current_state <= writing;
else
avm_m0_write <= '0';
end if;
when reading => -- Reading the SDRAM (normal read or write)
if avm_m0_waitrequest = '0' then
avm_m0_address <= read_addr;
dsp_out <= avm_m0_readdata;
if read_addr >= std_logic_vector(signed(buffersize) - 1) then
read_addr <= base_addr; -- To the beginning
elsif read_addr > write_addr then
read_addr <= std_logic_vector(signed(read_addr)+2);
else
read_addr <= std_logic_vector(signed(write_addr) - 2);
end if;
current_state <= reading2;
dsp_done <= '1';
else
dsp_done <= '0';
end if;
when reading2 => -- Reading the SDRAM (delayed read)
if avm_m0_waitrequest = '0' then
avm_m0_address <= read_delayed;
dsp_delayed <= avm_m0_readdata;
if read_delayed = std_logic_vector(signed(buffersize) - 1) then -- this line will overflow (intended behaviour).
read_delayed <= base_addr; -- To the beginning
avm_m0_read <= '0';
else
read_delayed <= std_logic_vector(signed(read_delayed) + 4096);
end if;
current_state <= idle;
dsp_delayed_valid <= '1';
else
dsp_delayed_valid <= '0';
end if;
when writing =>
if avm_m0_waitrequest = '0' then
avm_m0_address <= write_addr; -- can only write when waitrequest = 0
avm_m0_writedata <= dsp_in; -- Writes to SDRAM
if write_addr >= std_logic_vector(signed(buffersize)-1) then -- this line will overflow (intended behaviour).
write_addr <= base_addr; -- Reset the write addr
avm_m0_write <= '0'; -- Telling SDRAM we've stopped writing
avm_m0_read <= '1'; -- Read once SDRAM is full
read_flag <= '1';
else
write_addr <= std_logic_vector(signed(write_addr) + 2);
end if;
if read_flag = '1' then
current_state <= reading;
end if;
end if;
when others =>
current_state <= idle;
end case;
end if;
end process;
end architecture rtl;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Wed Apr 27 15:28:05 2016
-- Host : Dries007Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Github/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/Stack/Stack_sim_netlist.vhdl
-- Design : Stack
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Stack_spram is
port (
spo : out STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC;
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
we : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Stack_spram : entity is "spram";
end Stack_spram;
architecture STRUCTURE of Stack_spram is
signal qspo_int : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of qspo_int : signal is "true";
signal ram_reg_0_255_0_0_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_0_0_n_0 : STD_LOGIC;
signal ram_reg_0_255_10_10_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_10_10_n_0 : STD_LOGIC;
signal ram_reg_0_255_11_11_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_11_11_n_0 : STD_LOGIC;
signal ram_reg_0_255_12_12_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_12_12_n_0 : STD_LOGIC;
signal ram_reg_0_255_13_13_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_13_13_n_0 : STD_LOGIC;
signal ram_reg_0_255_14_14_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_14_14_n_0 : STD_LOGIC;
signal ram_reg_0_255_15_15_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_15_15_n_0 : STD_LOGIC;
signal ram_reg_0_255_1_1_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_1_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_2_2_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_2_2_n_0 : STD_LOGIC;
signal ram_reg_0_255_3_3_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_3_3_n_0 : STD_LOGIC;
signal ram_reg_0_255_4_4_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_4_4_n_0 : STD_LOGIC;
signal ram_reg_0_255_5_5_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_5_5_n_0 : STD_LOGIC;
signal ram_reg_0_255_6_6_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_6_6_n_0 : STD_LOGIC;
signal ram_reg_0_255_7_7_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_7_7_n_0 : STD_LOGIC;
signal ram_reg_0_255_8_8_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_8_8_n_0 : STD_LOGIC;
signal ram_reg_0_255_9_9_i_1_n_0 : STD_LOGIC;
signal ram_reg_0_255_9_9_n_0 : STD_LOGIC;
signal ram_reg_256_511_0_0_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_0_0_n_0 : STD_LOGIC;
signal ram_reg_256_511_10_10_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_10_10_n_0 : STD_LOGIC;
signal ram_reg_256_511_11_11_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_11_11_n_0 : STD_LOGIC;
signal ram_reg_256_511_12_12_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_12_12_n_0 : STD_LOGIC;
signal ram_reg_256_511_13_13_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_13_13_n_0 : STD_LOGIC;
signal ram_reg_256_511_14_14_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_14_14_n_0 : STD_LOGIC;
signal ram_reg_256_511_15_15_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_15_15_n_0 : STD_LOGIC;
signal ram_reg_256_511_1_1_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_1_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_2_2_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_2_2_n_0 : STD_LOGIC;
signal ram_reg_256_511_3_3_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_3_3_n_0 : STD_LOGIC;
signal ram_reg_256_511_4_4_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_4_4_n_0 : STD_LOGIC;
signal ram_reg_256_511_5_5_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_5_5_n_0 : STD_LOGIC;
signal ram_reg_256_511_6_6_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_6_6_n_0 : STD_LOGIC;
signal ram_reg_256_511_7_7_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_7_7_n_0 : STD_LOGIC;
signal ram_reg_256_511_8_8_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_8_8_n_0 : STD_LOGIC;
signal ram_reg_256_511_9_9_i_1_n_0 : STD_LOGIC;
signal ram_reg_256_511_9_9_n_0 : STD_LOGIC;
signal ram_reg_512_767_0_0_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_0_0_n_0 : STD_LOGIC;
signal ram_reg_512_767_10_10_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_10_10_n_0 : STD_LOGIC;
signal ram_reg_512_767_11_11_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_11_11_n_0 : STD_LOGIC;
signal ram_reg_512_767_12_12_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_12_12_n_0 : STD_LOGIC;
signal ram_reg_512_767_13_13_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_13_13_n_0 : STD_LOGIC;
signal ram_reg_512_767_14_14_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_14_14_n_0 : STD_LOGIC;
signal ram_reg_512_767_15_15_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_15_15_n_0 : STD_LOGIC;
signal ram_reg_512_767_1_1_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_1_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_2_2_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_2_2_n_0 : STD_LOGIC;
signal ram_reg_512_767_3_3_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_3_3_n_0 : STD_LOGIC;
signal ram_reg_512_767_4_4_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_4_4_n_0 : STD_LOGIC;
signal ram_reg_512_767_5_5_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_5_5_n_0 : STD_LOGIC;
signal ram_reg_512_767_6_6_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_6_6_n_0 : STD_LOGIC;
signal ram_reg_512_767_7_7_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_7_7_n_0 : STD_LOGIC;
signal ram_reg_512_767_8_8_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_8_8_n_0 : STD_LOGIC;
signal ram_reg_512_767_9_9_i_1_n_0 : STD_LOGIC;
signal ram_reg_512_767_9_9_n_0 : STD_LOGIC;
signal ram_reg_768_1023_0_0_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_0_0_n_0 : STD_LOGIC;
signal ram_reg_768_1023_10_10_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_10_10_n_0 : STD_LOGIC;
signal ram_reg_768_1023_11_11_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_11_11_n_0 : STD_LOGIC;
signal ram_reg_768_1023_12_12_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_12_12_n_0 : STD_LOGIC;
signal ram_reg_768_1023_13_13_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_13_13_n_0 : STD_LOGIC;
signal ram_reg_768_1023_14_14_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_14_14_n_0 : STD_LOGIC;
signal ram_reg_768_1023_15_15_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_15_15_n_0 : STD_LOGIC;
signal ram_reg_768_1023_1_1_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_1_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_2_2_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_2_2_n_0 : STD_LOGIC;
signal ram_reg_768_1023_3_3_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_3_3_n_0 : STD_LOGIC;
signal ram_reg_768_1023_4_4_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_4_4_n_0 : STD_LOGIC;
signal ram_reg_768_1023_5_5_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_5_5_n_0 : STD_LOGIC;
signal ram_reg_768_1023_6_6_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_6_6_n_0 : STD_LOGIC;
signal ram_reg_768_1023_7_7_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_7_7_n_0 : STD_LOGIC;
signal ram_reg_768_1023_8_8_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_8_8_n_0 : STD_LOGIC;
signal ram_reg_768_1023_9_9_i_1_n_0 : STD_LOGIC;
signal ram_reg_768_1023_9_9_n_0 : STD_LOGIC;
signal \^spo\ : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute KEEP : string;
attribute KEEP of \qspo_int_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \qspo_int_reg[0]\ : label is "no";
attribute KEEP of \qspo_int_reg[10]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[10]\ : label is "no";
attribute KEEP of \qspo_int_reg[11]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[11]\ : label is "no";
attribute KEEP of \qspo_int_reg[12]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[12]\ : label is "no";
attribute KEEP of \qspo_int_reg[13]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[13]\ : label is "no";
attribute KEEP of \qspo_int_reg[14]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[14]\ : label is "no";
attribute KEEP of \qspo_int_reg[15]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[15]\ : label is "no";
attribute KEEP of \qspo_int_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[1]\ : label is "no";
attribute KEEP of \qspo_int_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[2]\ : label is "no";
attribute KEEP of \qspo_int_reg[3]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[3]\ : label is "no";
attribute KEEP of \qspo_int_reg[4]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[4]\ : label is "no";
attribute KEEP of \qspo_int_reg[5]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[5]\ : label is "no";
attribute KEEP of \qspo_int_reg[6]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[6]\ : label is "no";
attribute KEEP of \qspo_int_reg[7]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[7]\ : label is "no";
attribute KEEP of \qspo_int_reg[8]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[8]\ : label is "no";
attribute KEEP of \qspo_int_reg[9]\ : label is "yes";
attribute equivalent_register_removal of \qspo_int_reg[9]\ : label is "no";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_0_0 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_10_10 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_11_11 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_12_12 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_13_13 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_14_14 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_15_15 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_1_1 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_2_2 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_3_3 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_4_4 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_5_5 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_6_6 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_7_7 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_8_8 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_0_255_9_9 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_0_0 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_10_10 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_11_11 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_12_12 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_13_13 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_14_14 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_15_15 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_1_1 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_2_2 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_3_3 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_4_4 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_5_5 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_6_6 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_7_7 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_8_8 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_256_511_9_9 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_0_0 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_10_10 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_11_11 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_12_12 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_13_13 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_14_14 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_15_15 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_1_1 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_2_2 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_3_3 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_4_4 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_5_5 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_6_6 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_7_7 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_8_8 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_512_767_9_9 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_0_0 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_10_10 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_11_11 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_12_12 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_13_13 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_14_14 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_15_15 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_1_1 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_2_2 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_3_3 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_4_4 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_5_5 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_6_6 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_7_7 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_8_8 : label is "{SYNTH-5 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of ram_reg_768_1023_9_9 : label is "{SYNTH-5 {cell *THIS*}}";
begin
spo(15 downto 0) <= \^spo\(15 downto 0);
\qspo_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(0),
Q => qspo_int(0),
R => '0'
);
\qspo_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(10),
Q => qspo_int(10),
R => '0'
);
\qspo_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(11),
Q => qspo_int(11),
R => '0'
);
\qspo_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(12),
Q => qspo_int(12),
R => '0'
);
\qspo_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(13),
Q => qspo_int(13),
R => '0'
);
\qspo_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(14),
Q => qspo_int(14),
R => '0'
);
\qspo_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(15),
Q => qspo_int(15),
R => '0'
);
\qspo_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(1),
Q => qspo_int(1),
R => '0'
);
\qspo_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(2),
Q => qspo_int(2),
R => '0'
);
\qspo_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(3),
Q => qspo_int(3),
R => '0'
);
\qspo_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(4),
Q => qspo_int(4),
R => '0'
);
\qspo_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(5),
Q => qspo_int(5),
R => '0'
);
\qspo_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(6),
Q => qspo_int(6),
R => '0'
);
\qspo_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(7),
Q => qspo_int(7),
R => '0'
);
\qspo_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(8),
Q => qspo_int(8),
R => '0'
);
\qspo_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \^spo\(9),
Q => qspo_int(9),
R => '0'
);
ram_reg_0_255_0_0: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(0),
O => ram_reg_0_255_0_0_n_0,
WCLK => clk,
WE => ram_reg_0_255_0_0_i_1_n_0
);
ram_reg_0_255_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_0_0_i_1_n_0
);
ram_reg_0_255_10_10: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(10),
O => ram_reg_0_255_10_10_n_0,
WCLK => clk,
WE => ram_reg_0_255_10_10_i_1_n_0
);
ram_reg_0_255_10_10_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_10_10_i_1_n_0
);
ram_reg_0_255_11_11: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(11),
O => ram_reg_0_255_11_11_n_0,
WCLK => clk,
WE => ram_reg_0_255_11_11_i_1_n_0
);
ram_reg_0_255_11_11_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_11_11_i_1_n_0
);
ram_reg_0_255_12_12: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(12),
O => ram_reg_0_255_12_12_n_0,
WCLK => clk,
WE => ram_reg_0_255_12_12_i_1_n_0
);
ram_reg_0_255_12_12_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_12_12_i_1_n_0
);
ram_reg_0_255_13_13: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(13),
O => ram_reg_0_255_13_13_n_0,
WCLK => clk,
WE => ram_reg_0_255_13_13_i_1_n_0
);
ram_reg_0_255_13_13_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_13_13_i_1_n_0
);
ram_reg_0_255_14_14: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(14),
O => ram_reg_0_255_14_14_n_0,
WCLK => clk,
WE => ram_reg_0_255_14_14_i_1_n_0
);
ram_reg_0_255_14_14_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_14_14_i_1_n_0
);
ram_reg_0_255_15_15: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(15),
O => ram_reg_0_255_15_15_n_0,
WCLK => clk,
WE => ram_reg_0_255_15_15_i_1_n_0
);
ram_reg_0_255_15_15_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_15_15_i_1_n_0
);
ram_reg_0_255_1_1: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(1),
O => ram_reg_0_255_1_1_n_0,
WCLK => clk,
WE => ram_reg_0_255_1_1_i_1_n_0
);
ram_reg_0_255_1_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_1_1_i_1_n_0
);
ram_reg_0_255_2_2: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(2),
O => ram_reg_0_255_2_2_n_0,
WCLK => clk,
WE => ram_reg_0_255_2_2_i_1_n_0
);
ram_reg_0_255_2_2_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_2_2_i_1_n_0
);
ram_reg_0_255_3_3: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(3),
O => ram_reg_0_255_3_3_n_0,
WCLK => clk,
WE => ram_reg_0_255_3_3_i_1_n_0
);
ram_reg_0_255_3_3_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_3_3_i_1_n_0
);
ram_reg_0_255_4_4: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(4),
O => ram_reg_0_255_4_4_n_0,
WCLK => clk,
WE => ram_reg_0_255_4_4_i_1_n_0
);
ram_reg_0_255_4_4_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_4_4_i_1_n_0
);
ram_reg_0_255_5_5: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(5),
O => ram_reg_0_255_5_5_n_0,
WCLK => clk,
WE => ram_reg_0_255_5_5_i_1_n_0
);
ram_reg_0_255_5_5_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_5_5_i_1_n_0
);
ram_reg_0_255_6_6: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(6),
O => ram_reg_0_255_6_6_n_0,
WCLK => clk,
WE => ram_reg_0_255_6_6_i_1_n_0
);
ram_reg_0_255_6_6_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_6_6_i_1_n_0
);
ram_reg_0_255_7_7: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(7),
O => ram_reg_0_255_7_7_n_0,
WCLK => clk,
WE => ram_reg_0_255_7_7_i_1_n_0
);
ram_reg_0_255_7_7_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_7_7_i_1_n_0
);
ram_reg_0_255_8_8: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(8),
O => ram_reg_0_255_8_8_n_0,
WCLK => clk,
WE => ram_reg_0_255_8_8_i_1_n_0
);
ram_reg_0_255_8_8_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_8_8_i_1_n_0
);
ram_reg_0_255_9_9: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(9),
O => ram_reg_0_255_9_9_n_0,
WCLK => clk,
WE => ram_reg_0_255_9_9_i_1_n_0
);
ram_reg_0_255_9_9_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_0_255_9_9_i_1_n_0
);
ram_reg_256_511_0_0: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(0),
O => ram_reg_256_511_0_0_n_0,
WCLK => clk,
WE => ram_reg_256_511_0_0_i_1_n_0
);
ram_reg_256_511_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_0_0_i_1_n_0
);
ram_reg_256_511_10_10: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(10),
O => ram_reg_256_511_10_10_n_0,
WCLK => clk,
WE => ram_reg_256_511_10_10_i_1_n_0
);
ram_reg_256_511_10_10_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_10_10_i_1_n_0
);
ram_reg_256_511_11_11: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(11),
O => ram_reg_256_511_11_11_n_0,
WCLK => clk,
WE => ram_reg_256_511_11_11_i_1_n_0
);
ram_reg_256_511_11_11_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_11_11_i_1_n_0
);
ram_reg_256_511_12_12: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(12),
O => ram_reg_256_511_12_12_n_0,
WCLK => clk,
WE => ram_reg_256_511_12_12_i_1_n_0
);
ram_reg_256_511_12_12_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_12_12_i_1_n_0
);
ram_reg_256_511_13_13: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(13),
O => ram_reg_256_511_13_13_n_0,
WCLK => clk,
WE => ram_reg_256_511_13_13_i_1_n_0
);
ram_reg_256_511_13_13_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_13_13_i_1_n_0
);
ram_reg_256_511_14_14: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(14),
O => ram_reg_256_511_14_14_n_0,
WCLK => clk,
WE => ram_reg_256_511_14_14_i_1_n_0
);
ram_reg_256_511_14_14_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_14_14_i_1_n_0
);
ram_reg_256_511_15_15: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(15),
O => ram_reg_256_511_15_15_n_0,
WCLK => clk,
WE => ram_reg_256_511_15_15_i_1_n_0
);
ram_reg_256_511_15_15_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_15_15_i_1_n_0
);
ram_reg_256_511_1_1: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(1),
O => ram_reg_256_511_1_1_n_0,
WCLK => clk,
WE => ram_reg_256_511_1_1_i_1_n_0
);
ram_reg_256_511_1_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_1_1_i_1_n_0
);
ram_reg_256_511_2_2: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(2),
O => ram_reg_256_511_2_2_n_0,
WCLK => clk,
WE => ram_reg_256_511_2_2_i_1_n_0
);
ram_reg_256_511_2_2_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_2_2_i_1_n_0
);
ram_reg_256_511_3_3: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(3),
O => ram_reg_256_511_3_3_n_0,
WCLK => clk,
WE => ram_reg_256_511_3_3_i_1_n_0
);
ram_reg_256_511_3_3_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_3_3_i_1_n_0
);
ram_reg_256_511_4_4: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(4),
O => ram_reg_256_511_4_4_n_0,
WCLK => clk,
WE => ram_reg_256_511_4_4_i_1_n_0
);
ram_reg_256_511_4_4_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_4_4_i_1_n_0
);
ram_reg_256_511_5_5: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(5),
O => ram_reg_256_511_5_5_n_0,
WCLK => clk,
WE => ram_reg_256_511_5_5_i_1_n_0
);
ram_reg_256_511_5_5_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_5_5_i_1_n_0
);
ram_reg_256_511_6_6: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(6),
O => ram_reg_256_511_6_6_n_0,
WCLK => clk,
WE => ram_reg_256_511_6_6_i_1_n_0
);
ram_reg_256_511_6_6_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_6_6_i_1_n_0
);
ram_reg_256_511_7_7: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(7),
O => ram_reg_256_511_7_7_n_0,
WCLK => clk,
WE => ram_reg_256_511_7_7_i_1_n_0
);
ram_reg_256_511_7_7_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_7_7_i_1_n_0
);
ram_reg_256_511_8_8: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(8),
O => ram_reg_256_511_8_8_n_0,
WCLK => clk,
WE => ram_reg_256_511_8_8_i_1_n_0
);
ram_reg_256_511_8_8_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_8_8_i_1_n_0
);
ram_reg_256_511_9_9: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(9),
O => ram_reg_256_511_9_9_n_0,
WCLK => clk,
WE => ram_reg_256_511_9_9_i_1_n_0
);
ram_reg_256_511_9_9_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(9),
I1 => a(8),
I2 => we,
O => ram_reg_256_511_9_9_i_1_n_0
);
ram_reg_512_767_0_0: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(0),
O => ram_reg_512_767_0_0_n_0,
WCLK => clk,
WE => ram_reg_512_767_0_0_i_1_n_0
);
ram_reg_512_767_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_0_0_i_1_n_0
);
ram_reg_512_767_10_10: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(10),
O => ram_reg_512_767_10_10_n_0,
WCLK => clk,
WE => ram_reg_512_767_10_10_i_1_n_0
);
ram_reg_512_767_10_10_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_10_10_i_1_n_0
);
ram_reg_512_767_11_11: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(11),
O => ram_reg_512_767_11_11_n_0,
WCLK => clk,
WE => ram_reg_512_767_11_11_i_1_n_0
);
ram_reg_512_767_11_11_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_11_11_i_1_n_0
);
ram_reg_512_767_12_12: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(12),
O => ram_reg_512_767_12_12_n_0,
WCLK => clk,
WE => ram_reg_512_767_12_12_i_1_n_0
);
ram_reg_512_767_12_12_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_12_12_i_1_n_0
);
ram_reg_512_767_13_13: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(13),
O => ram_reg_512_767_13_13_n_0,
WCLK => clk,
WE => ram_reg_512_767_13_13_i_1_n_0
);
ram_reg_512_767_13_13_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_13_13_i_1_n_0
);
ram_reg_512_767_14_14: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(14),
O => ram_reg_512_767_14_14_n_0,
WCLK => clk,
WE => ram_reg_512_767_14_14_i_1_n_0
);
ram_reg_512_767_14_14_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_14_14_i_1_n_0
);
ram_reg_512_767_15_15: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(15),
O => ram_reg_512_767_15_15_n_0,
WCLK => clk,
WE => ram_reg_512_767_15_15_i_1_n_0
);
ram_reg_512_767_15_15_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_15_15_i_1_n_0
);
ram_reg_512_767_1_1: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(1),
O => ram_reg_512_767_1_1_n_0,
WCLK => clk,
WE => ram_reg_512_767_1_1_i_1_n_0
);
ram_reg_512_767_1_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_1_1_i_1_n_0
);
ram_reg_512_767_2_2: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(2),
O => ram_reg_512_767_2_2_n_0,
WCLK => clk,
WE => ram_reg_512_767_2_2_i_1_n_0
);
ram_reg_512_767_2_2_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_2_2_i_1_n_0
);
ram_reg_512_767_3_3: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(3),
O => ram_reg_512_767_3_3_n_0,
WCLK => clk,
WE => ram_reg_512_767_3_3_i_1_n_0
);
ram_reg_512_767_3_3_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_3_3_i_1_n_0
);
ram_reg_512_767_4_4: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(4),
O => ram_reg_512_767_4_4_n_0,
WCLK => clk,
WE => ram_reg_512_767_4_4_i_1_n_0
);
ram_reg_512_767_4_4_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_4_4_i_1_n_0
);
ram_reg_512_767_5_5: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(5),
O => ram_reg_512_767_5_5_n_0,
WCLK => clk,
WE => ram_reg_512_767_5_5_i_1_n_0
);
ram_reg_512_767_5_5_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_5_5_i_1_n_0
);
ram_reg_512_767_6_6: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(6),
O => ram_reg_512_767_6_6_n_0,
WCLK => clk,
WE => ram_reg_512_767_6_6_i_1_n_0
);
ram_reg_512_767_6_6_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_6_6_i_1_n_0
);
ram_reg_512_767_7_7: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(7),
O => ram_reg_512_767_7_7_n_0,
WCLK => clk,
WE => ram_reg_512_767_7_7_i_1_n_0
);
ram_reg_512_767_7_7_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_7_7_i_1_n_0
);
ram_reg_512_767_8_8: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(8),
O => ram_reg_512_767_8_8_n_0,
WCLK => clk,
WE => ram_reg_512_767_8_8_i_1_n_0
);
ram_reg_512_767_8_8_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_8_8_i_1_n_0
);
ram_reg_512_767_9_9: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(9),
O => ram_reg_512_767_9_9_n_0,
WCLK => clk,
WE => ram_reg_512_767_9_9_i_1_n_0
);
ram_reg_512_767_9_9_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => a(8),
I1 => a(9),
I2 => we,
O => ram_reg_512_767_9_9_i_1_n_0
);
ram_reg_768_1023_0_0: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(0),
O => ram_reg_768_1023_0_0_n_0,
WCLK => clk,
WE => ram_reg_768_1023_0_0_i_1_n_0
);
ram_reg_768_1023_0_0_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_0_0_i_1_n_0
);
ram_reg_768_1023_10_10: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(10),
O => ram_reg_768_1023_10_10_n_0,
WCLK => clk,
WE => ram_reg_768_1023_10_10_i_1_n_0
);
ram_reg_768_1023_10_10_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_10_10_i_1_n_0
);
ram_reg_768_1023_11_11: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(11),
O => ram_reg_768_1023_11_11_n_0,
WCLK => clk,
WE => ram_reg_768_1023_11_11_i_1_n_0
);
ram_reg_768_1023_11_11_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_11_11_i_1_n_0
);
ram_reg_768_1023_12_12: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(12),
O => ram_reg_768_1023_12_12_n_0,
WCLK => clk,
WE => ram_reg_768_1023_12_12_i_1_n_0
);
ram_reg_768_1023_12_12_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_12_12_i_1_n_0
);
ram_reg_768_1023_13_13: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(13),
O => ram_reg_768_1023_13_13_n_0,
WCLK => clk,
WE => ram_reg_768_1023_13_13_i_1_n_0
);
ram_reg_768_1023_13_13_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_13_13_i_1_n_0
);
ram_reg_768_1023_14_14: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(14),
O => ram_reg_768_1023_14_14_n_0,
WCLK => clk,
WE => ram_reg_768_1023_14_14_i_1_n_0
);
ram_reg_768_1023_14_14_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_14_14_i_1_n_0
);
ram_reg_768_1023_15_15: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(15),
O => ram_reg_768_1023_15_15_n_0,
WCLK => clk,
WE => ram_reg_768_1023_15_15_i_1_n_0
);
ram_reg_768_1023_15_15_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_15_15_i_1_n_0
);
ram_reg_768_1023_1_1: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(1),
O => ram_reg_768_1023_1_1_n_0,
WCLK => clk,
WE => ram_reg_768_1023_1_1_i_1_n_0
);
ram_reg_768_1023_1_1_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_1_1_i_1_n_0
);
ram_reg_768_1023_2_2: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(2),
O => ram_reg_768_1023_2_2_n_0,
WCLK => clk,
WE => ram_reg_768_1023_2_2_i_1_n_0
);
ram_reg_768_1023_2_2_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_2_2_i_1_n_0
);
ram_reg_768_1023_3_3: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(3),
O => ram_reg_768_1023_3_3_n_0,
WCLK => clk,
WE => ram_reg_768_1023_3_3_i_1_n_0
);
ram_reg_768_1023_3_3_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_3_3_i_1_n_0
);
ram_reg_768_1023_4_4: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(4),
O => ram_reg_768_1023_4_4_n_0,
WCLK => clk,
WE => ram_reg_768_1023_4_4_i_1_n_0
);
ram_reg_768_1023_4_4_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_4_4_i_1_n_0
);
ram_reg_768_1023_5_5: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(5),
O => ram_reg_768_1023_5_5_n_0,
WCLK => clk,
WE => ram_reg_768_1023_5_5_i_1_n_0
);
ram_reg_768_1023_5_5_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_5_5_i_1_n_0
);
ram_reg_768_1023_6_6: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(6),
O => ram_reg_768_1023_6_6_n_0,
WCLK => clk,
WE => ram_reg_768_1023_6_6_i_1_n_0
);
ram_reg_768_1023_6_6_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_6_6_i_1_n_0
);
ram_reg_768_1023_7_7: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(7),
O => ram_reg_768_1023_7_7_n_0,
WCLK => clk,
WE => ram_reg_768_1023_7_7_i_1_n_0
);
ram_reg_768_1023_7_7_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_7_7_i_1_n_0
);
ram_reg_768_1023_8_8: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(8),
O => ram_reg_768_1023_8_8_n_0,
WCLK => clk,
WE => ram_reg_768_1023_8_8_i_1_n_0
);
ram_reg_768_1023_8_8_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_8_8_i_1_n_0
);
ram_reg_768_1023_9_9: unisim.vcomponents.RAM256X1S
generic map(
INIT => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
A(7 downto 0) => a(7 downto 0),
D => d(9),
O => ram_reg_768_1023_9_9_n_0,
WCLK => clk,
WE => ram_reg_768_1023_9_9_i_1_n_0
);
ram_reg_768_1023_9_9_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => we,
I1 => a(8),
I2 => a(9),
O => ram_reg_768_1023_9_9_i_1_n_0
);
\spo[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_0_0_n_0,
I1 => ram_reg_512_767_0_0_n_0,
I2 => a(9),
I3 => ram_reg_256_511_0_0_n_0,
I4 => a(8),
I5 => ram_reg_0_255_0_0_n_0,
O => \^spo\(0)
);
\spo[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_10_10_n_0,
I1 => ram_reg_512_767_10_10_n_0,
I2 => a(9),
I3 => ram_reg_256_511_10_10_n_0,
I4 => a(8),
I5 => ram_reg_0_255_10_10_n_0,
O => \^spo\(10)
);
\spo[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_11_11_n_0,
I1 => ram_reg_512_767_11_11_n_0,
I2 => a(9),
I3 => ram_reg_256_511_11_11_n_0,
I4 => a(8),
I5 => ram_reg_0_255_11_11_n_0,
O => \^spo\(11)
);
\spo[12]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_12_12_n_0,
I1 => ram_reg_512_767_12_12_n_0,
I2 => a(9),
I3 => ram_reg_256_511_12_12_n_0,
I4 => a(8),
I5 => ram_reg_0_255_12_12_n_0,
O => \^spo\(12)
);
\spo[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_13_13_n_0,
I1 => ram_reg_512_767_13_13_n_0,
I2 => a(9),
I3 => ram_reg_256_511_13_13_n_0,
I4 => a(8),
I5 => ram_reg_0_255_13_13_n_0,
O => \^spo\(13)
);
\spo[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_14_14_n_0,
I1 => ram_reg_512_767_14_14_n_0,
I2 => a(9),
I3 => ram_reg_256_511_14_14_n_0,
I4 => a(8),
I5 => ram_reg_0_255_14_14_n_0,
O => \^spo\(14)
);
\spo[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_15_15_n_0,
I1 => ram_reg_512_767_15_15_n_0,
I2 => a(9),
I3 => ram_reg_256_511_15_15_n_0,
I4 => a(8),
I5 => ram_reg_0_255_15_15_n_0,
O => \^spo\(15)
);
\spo[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_1_1_n_0,
I1 => ram_reg_512_767_1_1_n_0,
I2 => a(9),
I3 => ram_reg_256_511_1_1_n_0,
I4 => a(8),
I5 => ram_reg_0_255_1_1_n_0,
O => \^spo\(1)
);
\spo[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_2_2_n_0,
I1 => ram_reg_512_767_2_2_n_0,
I2 => a(9),
I3 => ram_reg_256_511_2_2_n_0,
I4 => a(8),
I5 => ram_reg_0_255_2_2_n_0,
O => \^spo\(2)
);
\spo[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_3_3_n_0,
I1 => ram_reg_512_767_3_3_n_0,
I2 => a(9),
I3 => ram_reg_256_511_3_3_n_0,
I4 => a(8),
I5 => ram_reg_0_255_3_3_n_0,
O => \^spo\(3)
);
\spo[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_4_4_n_0,
I1 => ram_reg_512_767_4_4_n_0,
I2 => a(9),
I3 => ram_reg_256_511_4_4_n_0,
I4 => a(8),
I5 => ram_reg_0_255_4_4_n_0,
O => \^spo\(4)
);
\spo[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_5_5_n_0,
I1 => ram_reg_512_767_5_5_n_0,
I2 => a(9),
I3 => ram_reg_256_511_5_5_n_0,
I4 => a(8),
I5 => ram_reg_0_255_5_5_n_0,
O => \^spo\(5)
);
\spo[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_6_6_n_0,
I1 => ram_reg_512_767_6_6_n_0,
I2 => a(9),
I3 => ram_reg_256_511_6_6_n_0,
I4 => a(8),
I5 => ram_reg_0_255_6_6_n_0,
O => \^spo\(6)
);
\spo[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_7_7_n_0,
I1 => ram_reg_512_767_7_7_n_0,
I2 => a(9),
I3 => ram_reg_256_511_7_7_n_0,
I4 => a(8),
I5 => ram_reg_0_255_7_7_n_0,
O => \^spo\(7)
);
\spo[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_8_8_n_0,
I1 => ram_reg_512_767_8_8_n_0,
I2 => a(9),
I3 => ram_reg_256_511_8_8_n_0,
I4 => a(8),
I5 => ram_reg_0_255_8_8_n_0,
O => \^spo\(8)
);
\spo[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => ram_reg_768_1023_9_9_n_0,
I1 => ram_reg_512_767_9_9_n_0,
I2 => a(9),
I3 => ram_reg_256_511_9_9_n_0,
I4 => a(8),
I5 => ram_reg_0_255_9_9_n_0,
O => \^spo\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Stack_dist_mem_gen_v8_0_9_synth is
port (
spo : out STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC;
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
we : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Stack_dist_mem_gen_v8_0_9_synth : entity is "dist_mem_gen_v8_0_9_synth";
end Stack_dist_mem_gen_v8_0_9_synth;
architecture STRUCTURE of Stack_dist_mem_gen_v8_0_9_synth is
begin
\gen_sp_ram.spram_inst\: entity work.Stack_spram
port map (
a(9 downto 0) => a(9 downto 0),
clk => clk,
d(15 downto 0) => d(15 downto 0),
spo(15 downto 0) => spo(15 downto 0),
we => we
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Stack_dist_mem_gen_v8_0_9 is
port (
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
dpra : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk : in STD_LOGIC;
we : in STD_LOGIC;
i_ce : in STD_LOGIC;
qspo_ce : in STD_LOGIC;
qdpo_ce : in STD_LOGIC;
qdpo_clk : in STD_LOGIC;
qspo_rst : in STD_LOGIC;
qdpo_rst : in STD_LOGIC;
qspo_srst : in STD_LOGIC;
qdpo_srst : in STD_LOGIC;
spo : out STD_LOGIC_VECTOR ( 15 downto 0 );
dpo : out STD_LOGIC_VECTOR ( 15 downto 0 );
qspo : out STD_LOGIC_VECTOR ( 15 downto 0 );
qdpo : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute C_ADDR_WIDTH : integer;
attribute C_ADDR_WIDTH of Stack_dist_mem_gen_v8_0_9 : entity is 10;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of Stack_dist_mem_gen_v8_0_9 : entity is "0";
attribute C_DEPTH : integer;
attribute C_DEPTH of Stack_dist_mem_gen_v8_0_9 : entity is 1024;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of Stack_dist_mem_gen_v8_0_9 : entity is "./";
attribute C_FAMILY : string;
attribute C_FAMILY of Stack_dist_mem_gen_v8_0_9 : entity is "artix7";
attribute C_HAS_CLK : integer;
attribute C_HAS_CLK of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_HAS_D : integer;
attribute C_HAS_D of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_HAS_DPO : integer;
attribute C_HAS_DPO of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_DPRA : integer;
attribute C_HAS_DPRA of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_I_CE : integer;
attribute C_HAS_I_CE of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO : integer;
attribute C_HAS_QDPO of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_CE : integer;
attribute C_HAS_QDPO_CE of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_CLK : integer;
attribute C_HAS_QDPO_CLK of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_RST : integer;
attribute C_HAS_QDPO_RST of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QDPO_SRST : integer;
attribute C_HAS_QDPO_SRST of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO : integer;
attribute C_HAS_QSPO of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO_CE : integer;
attribute C_HAS_QSPO_CE of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO_RST : integer;
attribute C_HAS_QSPO_RST of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_QSPO_SRST : integer;
attribute C_HAS_QSPO_SRST of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_HAS_SPO : integer;
attribute C_HAS_SPO of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_HAS_WE : integer;
attribute C_HAS_WE of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_MEM_INIT_FILE : string;
attribute C_MEM_INIT_FILE of Stack_dist_mem_gen_v8_0_9 : entity is "no_coe_file_loaded";
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_PARSER_TYPE : integer;
attribute C_PARSER_TYPE of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_PIPELINE_STAGES : integer;
attribute C_PIPELINE_STAGES of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_QCE_JOINED : integer;
attribute C_QCE_JOINED of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_QUALIFY_WE : integer;
attribute C_QUALIFY_WE of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_READ_MIF : integer;
attribute C_READ_MIF of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_REG_A_D_INPUTS : integer;
attribute C_REG_A_D_INPUTS of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_REG_DPRA_INPUT : integer;
attribute C_REG_DPRA_INPUT of Stack_dist_mem_gen_v8_0_9 : entity is 0;
attribute C_SYNC_ENABLE : integer;
attribute C_SYNC_ENABLE of Stack_dist_mem_gen_v8_0_9 : entity is 1;
attribute C_WIDTH : integer;
attribute C_WIDTH of Stack_dist_mem_gen_v8_0_9 : entity is 16;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of Stack_dist_mem_gen_v8_0_9 : entity is "dist_mem_gen_v8_0_9";
end Stack_dist_mem_gen_v8_0_9;
architecture STRUCTURE of Stack_dist_mem_gen_v8_0_9 is
signal \<const0>\ : STD_LOGIC;
begin
dpo(15) <= \<const0>\;
dpo(14) <= \<const0>\;
dpo(13) <= \<const0>\;
dpo(12) <= \<const0>\;
dpo(11) <= \<const0>\;
dpo(10) <= \<const0>\;
dpo(9) <= \<const0>\;
dpo(8) <= \<const0>\;
dpo(7) <= \<const0>\;
dpo(6) <= \<const0>\;
dpo(5) <= \<const0>\;
dpo(4) <= \<const0>\;
dpo(3) <= \<const0>\;
dpo(2) <= \<const0>\;
dpo(1) <= \<const0>\;
dpo(0) <= \<const0>\;
qdpo(15) <= \<const0>\;
qdpo(14) <= \<const0>\;
qdpo(13) <= \<const0>\;
qdpo(12) <= \<const0>\;
qdpo(11) <= \<const0>\;
qdpo(10) <= \<const0>\;
qdpo(9) <= \<const0>\;
qdpo(8) <= \<const0>\;
qdpo(7) <= \<const0>\;
qdpo(6) <= \<const0>\;
qdpo(5) <= \<const0>\;
qdpo(4) <= \<const0>\;
qdpo(3) <= \<const0>\;
qdpo(2) <= \<const0>\;
qdpo(1) <= \<const0>\;
qdpo(0) <= \<const0>\;
qspo(15) <= \<const0>\;
qspo(14) <= \<const0>\;
qspo(13) <= \<const0>\;
qspo(12) <= \<const0>\;
qspo(11) <= \<const0>\;
qspo(10) <= \<const0>\;
qspo(9) <= \<const0>\;
qspo(8) <= \<const0>\;
qspo(7) <= \<const0>\;
qspo(6) <= \<const0>\;
qspo(5) <= \<const0>\;
qspo(4) <= \<const0>\;
qspo(3) <= \<const0>\;
qspo(2) <= \<const0>\;
qspo(1) <= \<const0>\;
qspo(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\synth_options.dist_mem_inst\: entity work.Stack_dist_mem_gen_v8_0_9_synth
port map (
a(9 downto 0) => a(9 downto 0),
clk => clk,
d(15 downto 0) => d(15 downto 0),
spo(15 downto 0) => spo(15 downto 0),
we => we
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity Stack is
port (
a : in STD_LOGIC_VECTOR ( 9 downto 0 );
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
clk : in STD_LOGIC;
we : in STD_LOGIC;
spo : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of Stack : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of Stack : entity is "Stack,dist_mem_gen_v8_0_9,{}";
attribute core_generation_info : string;
attribute core_generation_info of Stack : entity is "Stack,dist_mem_gen_v8_0_9,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=10,C_DEFAULT_DATA=0,C_DEPTH=1024,C_HAS_CLK=1,C_HAS_D=1,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=1,C_MEM_INIT_FILE=no_coe_file_loaded,C_ELABORATION_DIR=./,C_MEM_TYPE=1,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=0,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=16,C_PARSER_TYPE=1}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of Stack : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of Stack : entity is "dist_mem_gen_v8_0_9,Vivado 2015.4";
end Stack;
architecture STRUCTURE of Stack is
signal NLW_U0_dpo_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_qdpo_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_qspo_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_CLK : integer;
attribute C_HAS_CLK of U0 : label is 1;
attribute C_HAS_D : integer;
attribute C_HAS_D of U0 : label is 1;
attribute C_HAS_DPO : integer;
attribute C_HAS_DPO of U0 : label is 0;
attribute C_HAS_DPRA : integer;
attribute C_HAS_DPRA of U0 : label is 0;
attribute C_HAS_QDPO : integer;
attribute C_HAS_QDPO of U0 : label is 0;
attribute C_HAS_QDPO_CE : integer;
attribute C_HAS_QDPO_CE of U0 : label is 0;
attribute C_HAS_QDPO_CLK : integer;
attribute C_HAS_QDPO_CLK of U0 : label is 0;
attribute C_HAS_QDPO_RST : integer;
attribute C_HAS_QDPO_RST of U0 : label is 0;
attribute C_HAS_QDPO_SRST : integer;
attribute C_HAS_QDPO_SRST of U0 : label is 0;
attribute C_HAS_WE : integer;
attribute C_HAS_WE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_QCE_JOINED : integer;
attribute C_QCE_JOINED of U0 : label is 0;
attribute C_REG_DPRA_INPUT : integer;
attribute C_REG_DPRA_INPUT of U0 : label is 0;
attribute c_addr_width : integer;
attribute c_addr_width of U0 : label is 10;
attribute c_default_data : string;
attribute c_default_data of U0 : label is "0";
attribute c_depth : integer;
attribute c_depth of U0 : label is 1024;
attribute c_elaboration_dir : string;
attribute c_elaboration_dir of U0 : label is "./";
attribute c_has_i_ce : integer;
attribute c_has_i_ce of U0 : label is 0;
attribute c_has_qspo : integer;
attribute c_has_qspo of U0 : label is 0;
attribute c_has_qspo_ce : integer;
attribute c_has_qspo_ce of U0 : label is 0;
attribute c_has_qspo_rst : integer;
attribute c_has_qspo_rst of U0 : label is 0;
attribute c_has_qspo_srst : integer;
attribute c_has_qspo_srst of U0 : label is 0;
attribute c_has_spo : integer;
attribute c_has_spo of U0 : label is 1;
attribute c_mem_init_file : string;
attribute c_mem_init_file of U0 : label is "no_coe_file_loaded";
attribute c_parser_type : integer;
attribute c_parser_type of U0 : label is 1;
attribute c_pipeline_stages : integer;
attribute c_pipeline_stages of U0 : label is 0;
attribute c_qualify_we : integer;
attribute c_qualify_we of U0 : label is 0;
attribute c_read_mif : integer;
attribute c_read_mif of U0 : label is 0;
attribute c_reg_a_d_inputs : integer;
attribute c_reg_a_d_inputs of U0 : label is 0;
attribute c_sync_enable : integer;
attribute c_sync_enable of U0 : label is 1;
attribute c_width : integer;
attribute c_width of U0 : label is 16;
begin
U0: entity work.Stack_dist_mem_gen_v8_0_9
port map (
a(9 downto 0) => a(9 downto 0),
clk => clk,
d(15 downto 0) => d(15 downto 0),
dpo(15 downto 0) => NLW_U0_dpo_UNCONNECTED(15 downto 0),
dpra(9 downto 0) => B"0000000000",
i_ce => '1',
qdpo(15 downto 0) => NLW_U0_qdpo_UNCONNECTED(15 downto 0),
qdpo_ce => '1',
qdpo_clk => '0',
qdpo_rst => '0',
qdpo_srst => '0',
qspo(15 downto 0) => NLW_U0_qspo_UNCONNECTED(15 downto 0),
qspo_ce => '1',
qspo_rst => '0',
qspo_srst => '0',
spo(15 downto 0) => spo(15 downto 0),
we => we
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc825.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00825ent IS
END c01s02b02x00p02n01i00825ent;
ARCHITECTURE c01s02b02x00p02n01i00825arch OF c01s02b02x00p02n01i00825ent IS
BEGIN
exit; -- illegal location for exit statement
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00825 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00825arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc825.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00825ent IS
END c01s02b02x00p02n01i00825ent;
ARCHITECTURE c01s02b02x00p02n01i00825arch OF c01s02b02x00p02n01i00825ent IS
BEGIN
exit; -- illegal location for exit statement
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00825 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00825arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc825.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00825ent IS
END c01s02b02x00p02n01i00825ent;
ARCHITECTURE c01s02b02x00p02n01i00825arch OF c01s02b02x00p02n01i00825ent IS
BEGIN
exit; -- illegal location for exit statement
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00825 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00825arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2800.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity FUNCTION is
end FUNCTION;
ENTITY c13s09b00x00p99n01i02800ent IS
END c13s09b00x00p99n01i02800ent;
ARCHITECTURE c13s09b00x00p99n01i02800arch OF c13s09b00x00p99n01i02800ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02800 - Reserved word FUNCTION can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02800arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2800.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity FUNCTION is
end FUNCTION;
ENTITY c13s09b00x00p99n01i02800ent IS
END c13s09b00x00p99n01i02800ent;
ARCHITECTURE c13s09b00x00p99n01i02800arch OF c13s09b00x00p99n01i02800ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02800 - Reserved word FUNCTION can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02800arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2800.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity FUNCTION is
end FUNCTION;
ENTITY c13s09b00x00p99n01i02800ent IS
END c13s09b00x00p99n01i02800ent;
ARCHITECTURE c13s09b00x00p99n01i02800arch OF c13s09b00x00p99n01i02800ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02800 - Reserved word FUNCTION can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02800arch;
|
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