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--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "fir_lp_15kHz".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_fir_lp_15kHz is
end tb_fir_lp_15kHz;
architecture tb of tb_fir_lp_15kHz is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(47 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(15 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(43 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.fir_lp_15kHz
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(15 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
-- Input rate is 1 input each 16 clock cycles: drive valid inputs at this rate
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 15;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 2055 ) is
variable impulse : std_logic_vector(15 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(15 downto 0) := "0100000000000000";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 80; -- provide no data for 5 input samples worth
drive_zeros(2); -- 2 normal input samples
s_axis_data_tvalid <= '1';
wait for CLOCK_PERIOD * 80; -- provide data as fast as the core can accept it for 5 input samples worth
drive_zeros(2046); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(15 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(43 downto 0) when m_axis_data_tvalid = '1';
end tb;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 23-02-2016
-- Module Name: crc_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity crc_t is
end entity;
architecture arch_crc_t of crc_t is
-- G(x) Function
constant G : std_logic_vector(3 downto 0) := "1011";
-- CRC Component definition
component crc is
generic (g : std_logic_vector);
port (d, clk : in std_logic;
r : buffer std_logic_vector(g'high - 1 downto g'low));
end component;
-- Middle signals
signal clk, d : std_logic := '0';
signal r : std_logic_vector(2 downto 0);
signal data : std_logic_vector(10 downto 0) := "10101100000";
signal run : std_logic := '1';
-- CRC Component configuration
for all:crc use entity work.crc(arch_crc);
begin
clk <= not clk after 50 ns when run = '1';
crc_1 : crc generic map (G) port map (d, clk, r);
process (clk)
variable I : natural := data'high + 1;
begin
if clk = '1' and clk'event then
if I > data'low then
I := I - 1;
d <= data(I);
else
run <= '0';
end if;
end if;
end process;
end architecture;
|
entity repro1 is
generic (c : natural := 4);
end repro1;
architecture behav of repro1 is
constant cmap : string (1 to 5) :=
(1 => 'a', 2 => 'b', 3 => 'c', 4 => 'd', 5 => 'e');
begin
process
variable v : character;
begin
v := cmap (c);
assert v = 'd' report "bad value" severity error;
wait;
end process;
end behav;
|
entity repro1 is
generic (c : natural := 4);
end repro1;
architecture behav of repro1 is
constant cmap : string (1 to 5) :=
(1 => 'a', 2 => 'b', 3 => 'c', 4 => 'd', 5 => 'e');
begin
process
variable v : character;
begin
v := cmap (c);
assert v = 'd' report "bad value" severity error;
wait;
end process;
end behav;
|
entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wait;
end process;
end behav;
|
entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wait;
end process;
end behav;
|
entity repro2 is
end repro2;
architecture behav of repro2 is
signal s : natural;
begin -- behav
process (s) is
variable v : natural;
begin
v := s'delayed (10 ns);
end process;
process
begin
s <= 3;
wait for 0 ns;
s <= 4;
wait for 0 ns;
s <= 5;
wait for 0 ns;
s <= 5;
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rx_data_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2ram
-- File: ddr2ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR2 SDRAM (JESD79-2C)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr2ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
babits: integer range 2 to 3 := 3;
colbits: integer range 9 to 11 := 9;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
swap : integer := 0; -- byte swap during srec load
fname: string;
lddelay: time := (0 ns);
ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before
-- loading RAM
-- Speed bins: 0:DDR2-400C,1:400B,2:533C,3:533B,4:667D,5:667C,6:800E,7:800D,8:800C
-- 9:800+ (MT47H-25E)
speedbin: integer range 0 to 9 := 0;
density: integer range 1 to 5 := 3; -- 1:256M 2:512M 3:1G 4:2G 5:4G bits/chip
pagesize: integer range 1 to 2 := 1 -- 1K/2K page size (controls tRRD)
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(babits-1 downto 0);
a: in std_logic_vector(abits-1 downto 0);
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0);
doload: in std_ulogic := '1'
);
end;
architecture sim of ddr2ram is
type moderegs is record
-- Mode register (0)
pd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
caslat: std_logic_vector(2 downto 0);
bt: std_ulogic;
blen: std_logic_vector(2 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
rdqsen: std_ulogic;
dqsndis: std_ulogic;
ocdprog: std_logic_vector(2 downto 0);
al: std_logic_vector(2 downto 0);
rtt: std_logic_vector(1 downto 0);
ds: std_ulogic;
dlldis: std_ulogic;
-- Extended mode register 2
srf: std_ulogic;
dccen: std_ulogic;
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
emr3: std_logic_vector(abits-1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 2;
constant tRTP: time := 7.5 ns;
type timetab is array (0 to 9) of time;
-- 400C 400B 533C 533B 667D 667C 800E 800D 800C MT-2.5E
constant tRAS : timetab := (45 ns, 40 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 40 ns);
constant tRP : timetab := (20 ns, 15 ns, 15 ns, 11.25 ns, 15 ns, 12 ns, 15 ns, 12.5 ns, 10 ns, 12.5 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(1 to 5) of time;
constant tRFC: timetab2 := (75 ns, 105 ns, 127.5 ns, 195 ns, 327.5 ns);
type timetab3 is array(1 to 2) of time;
constant tRRD: timetab3 := (7.5 ns, 10 ns);
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
variable cyctr: integer := 0;
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(1 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
cyctr := cyctr+1;
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
cyctr := cyctr+1;
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="--" or cba=ba(1 downto 0)) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t: time;
begin
initdone <= false;
-- Allow cke to be X or U for a while during sim start
if is_x(cke) then
wait until not is_x(cke);
end if;
assert cke='0' report "CKE not deasserted on power-up" severity warning;
wait until cke/='0' for 200 us;
assert cke='0' report "CKE raised with less than 200 us init delay" severity warning;
wait until cke/='0' and rising_edge(ck);
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
assert (now-t) > 400 ns report "Less than 400 ns wait period after CKE high!" severity warning;
-- EMRS EMR2
checkcmd('0','0','0',"10","----------------");
-- EMRS EMR3
checkcmd('0','0','0',"11","----------------");
-- EMRS enable DLL
checkcmd('0','0','0',"01","000---000-------");
-- MRS reset DLL
checkcmd('0','0','0',"00","000----1--------");
cyctr := 0;
-- Precharge all
checkcmd('0','1','0',"--","-----1----------");
-- 2 x auto refresh
checkcmd('0','0','1',"--","----------------");
checkcmd('0','0','1',"--","----------------");
-- MRS !reset DLL
checkcmd('0','0','0',"00","-------0--------");
-- EMRS EMR1 OCD default, EMRS EMR1 exit OCD cal
-- (assume OCD impedance adjust not performed)
checkcmd('0','0','0',"01","------111-------");
assert cyctr >= 200 report "Less than 200 cycles (" & tost(cyctr) & ") between DLL reset and OCD cal" severity warning;
checkcmd('0','0','0',"01","------000-------");
initdone <= true;
wait;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
subtype coldata is std_logic_vector(width-1 downto 0);
type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata;
variable memdata: coldata_arr;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable recdatatemp : std_logic_vector(0 to 7);
variable col, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
if swap=1 then -- byte swap during srec load
for i in 0 to 7 loop
recdatatemp := recdata(i*16 to i*16+7);
recdata(i*16 to i*16+7) := recdata(i*16+8 to i*16+15);
recdata(i*16+8 to i*16+15) := recdatatemp;
end loop;
end if;
col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8))));
coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0)));
while len > width/8 loop
assert coloffs=0;
memdata(col) := recdata(0 to width-1);
col := col+1;
len := len-width/8;
recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1);
end loop;
memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1);
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 9);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-1 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 0;
variable loaded: boolean := false;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat)); end if;
if cl<2 or cl>6 then cl:=0; end if;
if is_x(vmr.al) then al:=0; else al:=to_integer(unsigned(vmr.al)); end if;
if al>5 then al:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=1+to_integer(unsigned(vmr.wr)); end if;
if wrap<2 or wrap>6 then wrap:=0; end if;
-- Checks for all-bank commands
if mrscount > 0 then
mrscount := mrscount-1;
assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning;
end if;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(pagesize), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
-- Get additive latency
i := to_integer(unsigned(vmr.al));
assert banks(bank).openrow >= 0
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
-- Allow interrupting read in case of middle of BL8 burst only
if (accpipe(3).r and accpipe(2).r and
not (accpipe(1).r or accpipe(1).w or accpipe(0).r or accpipe(0).w)) then
accpipe(3).r := false;
accpipe(2).r := false;
end if;
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0)));
case vmr.blen is
when "010" => blen := 4;
when "011" => blen := 8;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.bt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) +
banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
end loop;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+blen/2;
else
banks(bank).autopch := cl+al-1+blen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- Reserved (Burst terminate on DDR1)
assert false report "Invalid command RAS=1 CAS=1 WE=0" severity warning;
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 3 downto 0 loop -- FIXME potential window which isn't checked if AL>0
assert (not (accpipe(x).r or accpipe(x).w)) or (a(10)='0' and bank/=accpipe(x).bank)
report "Precharging bank with access in progress"
severity warning;
end loop;
for x in 0 to (2**babits)-1 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,babits)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.pd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4);
vmr.bt := a(3);
vmr.blen := a(2 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.rdqsen := a(11);
vmr.dqsndis := a(10);
vmr.ocdprog := a(9 downto 7);
vmr.al := a(5 downto 3);
vmr.rtt := a(6) & a(2);
vmr.ds := a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.srf := a(7);
vmr.dccen := a(3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.emr3 := a;
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := tMRD_ck-1;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and (now-banks(x).opentime-deltat) < tRAS(speedbin) then
-- Auto delay auto-precharge to satisfy tRAS/tRC
banks(x).autopch := banks(x).autopch+1;
elsif banks(x).pchpush and (now-banks(x).readtime-deltat) < tRTP then
-- Auto delay auto-precharge to satisfy tRTP
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP, true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now and (ldguard=0 or doload='1') then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
read_data <= memdata(accpipe(2+cl+al).col(0)) & memdata(accpipe(2+cl+al).col(1));
else
read_en <= false;
end if;
-- tRTP is counted from read command + AL for BL4, read command + AL + 2
-- for BL8. This check covers both cases by writing readtime on the next-to-last
-- transfer.
if accpipe(3+al).r and accpipe(2+al).r and accpipe(3+al).bank=accpipe(2+al).bank then
banks(accpipe(2+al).bank).readtime := now;
end if;
write_en <= accpipe(1+cl+al).w or accpipe(2+cl+al).w;
if accpipe(3+cl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
memdata(accpipe(3+cl+al).col(x))(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
end loop;
banks(accpipe(3+cl+al).bank).writetime := now;
end if;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en;
assert not (read_en and write_en);
if read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
assert (to_X01(dqs)=(dqs'range => '0')) or ((to_X01(dqs)=(dqs'range => '1')) and (to_X01(dm)=(dm'range => '1') or dm=(dm'range => 'Z')));
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_bram_ctrl_0_0;
ARCHITECTURE design_1_axi_bram_ctrl_0_0_arch OF design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=2048,C_BRAM_ADDR_WIDTH=11,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=12,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 2048,
C_BRAM_ADDR_WIDTH => 11,
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_bram_ctrl_0_0_arch;
|
-------------------------------------------------------------------------------
-- system_ac1_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_ac1_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 0);
MPLB_Rst : out std_logic_vector(0 to 14);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 479);
M_UABus : in std_logic_vector(0 to 479);
M_BE : in std_logic_vector(0 to 119);
M_RNW : in std_logic_vector(0 to 14);
M_abort : in std_logic_vector(0 to 14);
M_busLock : in std_logic_vector(0 to 14);
M_TAttribute : in std_logic_vector(0 to 239);
M_lockErr : in std_logic_vector(0 to 14);
M_MSize : in std_logic_vector(0 to 29);
M_priority : in std_logic_vector(0 to 29);
M_rdBurst : in std_logic_vector(0 to 14);
M_request : in std_logic_vector(0 to 14);
M_size : in std_logic_vector(0 to 59);
M_type : in std_logic_vector(0 to 44);
M_wrBurst : in std_logic_vector(0 to 14);
M_wrDBus : in std_logic_vector(0 to 959);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_MRdErr : in std_logic_vector(0 to 14);
Sl_MWrErr : in std_logic_vector(0 to 14);
Sl_MBusy : in std_logic_vector(0 to 14);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 63);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_SSize : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_MIRQ : in std_logic_vector(0 to 14);
PLB_MIRQ : out std_logic_vector(0 to 14);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 14);
PLB_MTimeout : out std_logic_vector(0 to 14);
PLB_MBusy : out std_logic_vector(0 to 14);
PLB_MRdErr : out std_logic_vector(0 to 14);
PLB_MWrErr : out std_logic_vector(0 to 14);
PLB_MRdBTerm : out std_logic_vector(0 to 14);
PLB_MRdDAck : out std_logic_vector(0 to 14);
PLB_MRdDBus : out std_logic_vector(0 to 959);
PLB_MRdWdAddr : out std_logic_vector(0 to 59);
PLB_MRearbitrate : out std_logic_vector(0 to 14);
PLB_MWrBTerm : out std_logic_vector(0 to 14);
PLB_MWrDAck : out std_logic_vector(0 to 14);
PLB_MSSize : out std_logic_vector(0 to 29);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 3);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 0);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 0);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 14);
PLB_SMWrErr : out std_logic_vector(0 to 14);
PLB_SMBusy : out std_logic_vector(0 to 14);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_ac1_plb_wrapper : entity is "plb_v46_v1_05_a";
end system_ac1_plb_wrapper;
architecture STRUCTURE of system_ac1_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
ac1_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 15,
C_PLBV46_NUM_SLAVES => 1,
C_PLBV46_MID_WIDTH => 4,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
component osc is
port (
clkout : out std_logic; -- clk
oscena : in std_logic := 'X' -- oscena
);
end component osc;
u0 : component osc
port map (
clkout => CONNECTED_TO_clkout, -- clkout.clk
oscena => CONNECTED_TO_oscena -- oscena.oscena
);
|
-------------------------------------------------------------------------------
-- Title : Package for Ultrasonic transmitter
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
package uss_tx_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component uss_tx_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#);
port (
uss_tx0_out_p : out half_bridge_type;
uss_tx1_out_p : out half_bridge_type;
uss_tx2_out_p : out half_bridge_type;
clk_uss_enable_p : out std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
component serialiser is
generic (
BITPATTERN_WIDTH : positive);
port (
pattern_in_p : in std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
bitstream_out_p : out std_logic;
clk_bit : in std_logic;
clk : in std_logic);
end component serialiser;
end uss_tx_pkg;
|
-------------------------------------------------------------------------------
-- Title : Package for Ultrasonic transmitter
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bus_pkg.all;
use work.motor_control_pkg.all;
package uss_tx_pkg is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component uss_tx_module
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#);
port (
uss_tx0_out_p : out half_bridge_type;
uss_tx1_out_p : out half_bridge_type;
uss_tx2_out_p : out half_bridge_type;
clk_uss_enable_p : out std_logic;
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic);
end component;
component serialiser is
generic (
BITPATTERN_WIDTH : positive);
port (
pattern_in_p : in std_logic_vector(BITPATTERN_WIDTH - 1 downto 0);
bitstream_out_p : out std_logic;
clk_bit : in std_logic;
clk : in std_logic);
end component serialiser;
end uss_tx_pkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_Controller is
port(
CLKin : in std_logic;
READADDRin : in std_logic_vector(22 downto 0);
WRITEADDRin : in std_logic_vector(22 downto 0);
DATAin : in std_logic_vector(14 downto 0);
READin : in std_logic;
WRITEin : in std_logic;
------------------------
SRAMDATA_io : inout std_logic_vector(14 downto 0);
------------------------
SRAMADDR_out : out std_logic_vector(22 downto 0);
DATA_out : out std_logic_vector(14 downto 0);
OE_out : out std_logic;
WE_out : out std_logic;
CE1_out : out std_logic;
CE2_out : out std_logic;
UB1_out : out std_logic;
LB1_out : out std_logic
);
end SRAM_Controller;
architecture Behavioral of SRAM_Controller is
signal CLK : std_logic;
signal READENA : std_logic;
signal READCOM : std_logic;
signal WRITEENA : std_logic;
signal WRITECOM : std_logic;
signal QWRITE : std_logic_vector(1 downto 0);
signal QREAD : std_logic_vector(1 downto 0);
signal WRITESTATE : integer range 0 to 3 := 0;
signal READSTATE : integer range 0 to 3 := 0;
begin
CE1_out <= '0';
CE2_out <= '0';
UB1_out <= '0';
LB1_out <= '0';
process(CLKin)
begin
if (rising_edge(CLKin)) then
QWRITE(0) <= WRITEin;
QREAD(0) <= READin;
end if;
end process;
process(CLKin)
begin
if(rising_edge(CLKin)) then
if (READin = '1') then
SRAMADDR_out<=READADDRin;
READENA <= '1';
SRAMDATA_io <= (others => 'Z');
elsif (WRITEin = '1' and READENA = '0') then
SRAMADDR_out<=WRITEADDRin;
WRITEENA <= '1';
end if;
if (READENA = '1') then
case READSTATE is
when 0 =>
READSTATE <= 1;
when 1 =>
READSTATE <= 2;
when 2 =>
READSTATE <= 3;
when 3 =>
READSTATE <= 0;
end case;
else
if (READSTATE = 3) then
READSTATE <= 0;
end if;
end if;
if (WRITEENA = '1') then
case WRITESTATE is
when 0 =>
WRITESTATE <= 1;
when 1 =>
WRITESTATE <= 2;
when 2 =>
WRITESTATE <= 3;
when 3 =>
WRITESTATE <= 0;
end case;
else
if (WRITESTATE = 3) then
WRITESTATE <= 0;
end if;
end if;
case READSTATE is
when 0 =>
OE_out <= '1';
when 1 =>
OE_out <= '0';
DATA_out <= SRAMDATA_io(14 downto 0);
when 2 =>
OE_out <= '1';
DATA_out <= SRAMDATA_io(14 downto 0);
READENA <= '0';
when 3 =>
OE_out <= '1';
end case;
case WRITESTATE is
when 0 =>
WE_out <= '1';
when 1 =>
WE_out <= '0';
SRAMDATA_io <= DATAin;
when 2 =>
WE_out <= '1';
SRAMDATA_io <= DATAin;
WRITEENA <= '0';
when 3 =>
WE_out <= '1';
end case;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator Registers
-------------------------------------------------------------------------------
-- File : char_generator_regs.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Registers for the character generator
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_regs is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
keyb_row : in std_logic_vector(7 downto 0);
keyb_col : inout std_logic_vector(7 downto 0);
control : out t_chargen_control );
end entity;
architecture gideon of char_generator_regs is
signal control_i : t_chargen_control := c_chargen_control_init;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_chargen_line_clocks_hi =>
control_i.clocks_per_line(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when c_chargen_line_clocks_lo =>
control_i.clocks_per_line(7 downto 0) <= unsigned(io_req.data);
when c_chargen_char_width =>
control_i.char_width <= unsigned(io_req.data(2 downto 0));
when c_chargen_char_height =>
control_i.char_height <= unsigned(io_req.data(4 downto 0));
control_i.stretch_y <= io_req.data(7);
when c_chargen_chars_per_line =>
control_i.chars_per_line <= unsigned(io_req.data);
when c_chargen_active_lines =>
control_i.active_lines <= unsigned(io_req.data(5 downto 0));
when c_chargen_x_on_hi =>
control_i.x_on(11 downto 8) <= unsigned(io_req.data(3 downto 0));
when c_chargen_x_on_lo =>
control_i.x_on(7 downto 0) <= unsigned(io_req.data);
when c_chargen_y_on_hi =>
control_i.y_on(11 downto 8) <= unsigned(io_req.data(3 downto 0));
when c_chargen_y_on_lo =>
control_i.y_on(7 downto 0) <= unsigned(io_req.data);
when c_chargen_pointer_hi =>
control_i.pointer(14 downto 8) <= unsigned(io_req.data(6 downto 0));
when c_chargen_pointer_lo =>
control_i.pointer(7 downto 0) <= unsigned(io_req.data);
when c_chargen_perform_sync =>
control_i.perform_sync <= io_req.data(0);
when c_chargen_transparency =>
control_i.transparent <= io_req.data(3 downto 0);
control_i.overlay_on <= io_req.data(7);
when c_chargen_keyb_col =>
keyb_col <= io_req.data;
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_chargen_keyb_row =>
io_resp.data <= keyb_row;
when c_chargen_keyb_col =>
io_resp.data <= keyb_col;
when others =>
null;
end case;
end if;
if reset='1' then
-- control_i <= c_chargen_control_init;
keyb_col <= (others => '1');
end if;
end if;
end process;
control <= control_i;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
-- Checked !
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr /= cur_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in = '0') then
err_header_not_empty_faulty_drop_packet_in <= '1';
else
err_header_not_empty_faulty_drop_packet_in <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '0' and not (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in /= packet_drop) then
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '1';
else
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, Requests_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and Requests_in /= "00000") then
err_header_not_empty_faulty_Req_in_all_zero <= '1';
else
err_header_not_empty_faulty_Req_in_all_zero <= '0';
end if;
end process;
-- Added (according to new design)!
--process (flit_type, empty, Req_L_in, N1_out, E1_out, W1_out, S1_out)
--begin
-- if ( flit_type = "001" and empty = '0' and Req_L_in /= (not N1_out and not E1_out and not W1_out and not S1_out) ) then
-- err_header_not_empty_Req_L_in <= '1';
-- else
-- err_header_not_empty_Req_L_in <= '0';
-- end if;
--end process;
-- Updated !
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
else
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
else
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
else
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
else
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (packet_drop_order, packet_drop)
begin
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
else
err_packet_drop_order <= '0';
end if;
end process;
-- Added !
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
-- Checked !
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr /= cur_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in = '0') then
err_header_not_empty_faulty_drop_packet_in <= '1';
else
err_header_not_empty_faulty_drop_packet_in <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '0' and not (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in /= packet_drop) then
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '1';
else
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, Requests_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and Requests_in /= "00000") then
err_header_not_empty_faulty_Req_in_all_zero <= '1';
else
err_header_not_empty_faulty_Req_in_all_zero <= '0';
end if;
end process;
-- Added (according to new design)!
--process (flit_type, empty, Req_L_in, N1_out, E1_out, W1_out, S1_out)
--begin
-- if ( flit_type = "001" and empty = '0' and Req_L_in /= (not N1_out and not E1_out and not W1_out and not S1_out) ) then
-- err_header_not_empty_Req_L_in <= '1';
-- else
-- err_header_not_empty_Req_L_in <= '0';
-- end if;
--end process;
-- Updated !
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
else
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
else
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
else
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
else
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (packet_drop_order, packet_drop)
begin
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
else
err_packet_drop_order <= '0';
end if;
end process;
-- Added !
end behavior; |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR_packet_drop_routing_part_pseudo_checkers is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port (
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: in std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
Cx: in std_logic_vector(3 downto 0);
Rxy: in std_logic_vector(7 downto 0);
packet_drop: in std_logic;
N1_out, E1_out, W1_out, S1_out: in std_logic;
Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: in std_logic;
grants: in std_logic;
packet_drop_order: in std_logic;
packet_drop_in: in std_logic;
-- Checker outputs
err_header_empty_Requests_FF_Requests_in,
err_tail_Requests_in_all_zero,
err_tail_empty_Requests_FF_Requests_in,
err_tail_not_empty_not_grants_Requests_FF_Requests_in,
err_grants_onehot,
err_grants_mismatch,
err_header_tail_Requests_FF_Requests_in,
err_dst_addr_cur_addr_N1,
err_dst_addr_cur_addr_not_N1,
err_dst_addr_cur_addr_E1,
err_dst_addr_cur_addr_not_E1,
err_dst_addr_cur_addr_W1,
err_dst_addr_cur_addr_not_W1,
err_dst_addr_cur_addr_S1,
err_dst_addr_cur_addr_not_S1,
err_dst_addr_cur_addr_Req_L_in,
err_dst_addr_cur_addr_not_Req_L_in,
err_header_not_empty_faulty_drop_packet_in, -- added according to new design
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change, -- added according to new design
err_header_not_empty_faulty_Req_in_all_zero, -- added according to new design
--err_header_not_empty_Req_L_in, -- added according to new design
err_header_not_empty_Req_N_in,
err_header_not_empty_Req_E_in,
err_header_not_empty_Req_W_in,
err_header_not_empty_Req_S_in,
err_header_empty_packet_drop_in_packet_drop_equal,
err_tail_not_empty_packet_drop_not_packet_drop_in,
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal,
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal,
err_packet_drop_order : out std_logic
);
end LBDR_packet_drop_routing_part_pseudo_checkers;
architecture behavior of LBDR_packet_drop_routing_part_pseudo_checkers is
signal cur_addr: std_logic_vector(NoC_size-1 downto 0);
signal Requests_FF: std_logic_vector(4 downto 0);
signal Requests_in: std_logic_vector(4 downto 0);
signal grant_signals: std_logic_vector(4 downto 0);
begin
cur_addr <= std_logic_vector(to_unsigned(cur_addr_rst, cur_addr'length));
Requests_FF <= Req_N_FF & Req_E_FF & Req_W_FF & Req_S_FF & Req_L_FF;
Requests_in <= Req_N_in & Req_E_in & Req_W_in & Req_S_in & Req_L_in;
grant_signals <= grant_N & grant_E & grant_W & grant_S & grant_L;
-- Implementing checkers in form of concurrent assignments (combinational assertions)
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "001" and empty = '1' and Requests_FF /= Requests_in) then
err_header_empty_Requests_FF_Requests_in <= '1';
else
err_header_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '1' and Requests_in /= "00000") then
err_tail_Requests_in_all_zero <= '1';
else
err_tail_Requests_in_all_zero <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '1' and Requests_FF /= Requests_in) then
err_tail_empty_Requests_FF_Requests_in <= '1';
else
err_tail_empty_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, grants, Requests_FF, Requests_in)
begin
if (flit_type = "100" and empty = '0' and grants = '0' and Requests_FF /= Requests_in) then
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '1';
else
err_tail_not_empty_not_grants_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( (grant_signals = "00001" or grant_signals = "00010" or grant_signals = "00100" or
grant_signals = "01000" or grant_signals = "10000") and grants = '0') then
err_grants_onehot <= '1';
else
err_grants_onehot <= '0';
end if;
end process;
-- Checked !
process (grant_signals, grants)
begin
if ( grant_signals = "00000" and grants = '1') then
err_grants_mismatch <= '1';
else
err_grants_mismatch <= '0';
end if;
end process;
-- Checked !
process (flit_type, Requests_FF, Requests_FF, Requests_in)
begin
if (flit_type /= "001" and flit_type /= "100" and Requests_FF /= Requests_in) then
err_header_tail_Requests_FF_Requests_in <= '1';
else
err_header_tail_Requests_FF_Requests_in <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) < cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '0') then
err_dst_addr_cur_addr_N1 <= '1';
else
err_dst_addr_cur_addr_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, N1_out)
begin
if ( dst_addr(NoC_size-1 downto NoC_size/2) >= cur_addr(NoC_size-1 downto NoC_size/2) and N1_out = '1') then
err_dst_addr_cur_addr_not_N1 <= '1';
else
err_dst_addr_cur_addr_not_N1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) < dst_addr((NoC_size/2)-1 downto 0) and E1_out = '0') then
err_dst_addr_cur_addr_E1 <= '1';
else
err_dst_addr_cur_addr_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, E1_out)
begin
if ( cur_addr((NoC_size/2)-1 downto 0) >= dst_addr((NoC_size/2)-1 downto 0) and E1_out = '1') then
err_dst_addr_cur_addr_not_E1 <= '1';
else
err_dst_addr_cur_addr_not_E1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) < cur_addr((NoC_size/2)-1 downto 0) and W1_out = '0') then
err_dst_addr_cur_addr_W1 <= '1';
else
err_dst_addr_cur_addr_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, W1_out)
begin
if ( dst_addr((NoC_size/2)-1 downto 0) >= cur_addr((NoC_size/2)-1 downto 0) and W1_out = '1') then
err_dst_addr_cur_addr_not_W1 <= '1';
else
err_dst_addr_cur_addr_not_W1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) < dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '0') then
err_dst_addr_cur_addr_S1 <= '1';
else
err_dst_addr_cur_addr_S1 <= '0';
end if;
end process;
-- Checked !
process (cur_addr, dst_addr, S1_out)
begin
if ( cur_addr(NoC_size-1 downto NoC_size/2) >= dst_addr(NoC_size-1 downto NoC_size/2) and S1_out = '1') then
err_dst_addr_cur_addr_not_S1 <= '1';
else
err_dst_addr_cur_addr_not_S1 <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr = cur_addr and Req_L_in = '0') then
err_dst_addr_cur_addr_Req_L_in <= '1';
else
err_dst_addr_cur_addr_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, dst_addr, cur_addr, Req_L_in)
begin
if ( flit_type = "001" and empty = '0' and dst_addr /= cur_addr and Req_L_in = '1') then
err_dst_addr_cur_addr_not_Req_L_in <= '1';
else
err_dst_addr_cur_addr_not_Req_L_in <= '0';
end if;
end process;
-- Checked !
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in = '0') then
err_header_not_empty_faulty_drop_packet_in <= '1';
else
err_header_not_empty_faulty_drop_packet_in <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, packet_drop_in, packet_drop)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '0' and not (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and packet_drop_in /= packet_drop) then
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '1';
else
err_header_not_empty_not_faulty_drop_packet_in_packet_drop_not_change <= '0';
end if;
end process;
-- Added (according to new design)!
process (flit_type, empty, faulty, N1_out, E1_out, W1_out, S1_out, Rxy, Cx, dst_addr, cur_addr, Requests_in)
begin
if ( flit_type = "001" and empty = '0' and (faulty = '1' or (((((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0)) = '0') and
((((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1)) = '0') and
((((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2)) = '0') and
((((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) = '0') and
(dst_addr /= cur_addr))) and Requests_in /= "00000") then
err_header_not_empty_faulty_Req_in_all_zero <= '1';
else
err_header_not_empty_faulty_Req_in_all_zero <= '0';
end if;
end process;
-- Added (according to new design)!
--process (flit_type, empty, Req_L_in, N1_out, E1_out, W1_out, S1_out)
--begin
-- if ( flit_type = "001" and empty = '0' and Req_L_in /= (not N1_out and not E1_out and not W1_out and not S1_out) ) then
-- err_header_not_empty_Req_L_in <= '1';
-- else
-- err_header_not_empty_Req_L_in <= '0';
-- end if;
--end process;
-- Updated !
process (flit_type, empty, Req_N_in, N1_out, E1_out, W1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_N_in /= ( ((N1_out and not E1_out and not W1_out) or (N1_out and E1_out and Rxy(0)) or (N1_out and W1_out and Rxy(1))) and Cx(0) ) ) then
err_header_not_empty_Req_N_in <= '1';
else
err_header_not_empty_Req_N_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_E_in, N1_out, E1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_E_in /= ( ((E1_out and not N1_out and not S1_out) or (E1_out and N1_out and Rxy(2)) or (E1_out and S1_out and Rxy(3))) and Cx(1) ) ) then
err_header_not_empty_Req_E_in <= '1';
else
err_header_not_empty_Req_E_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_W_in, N1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_W_in /= ( ((W1_out and not N1_out and not S1_out) or (W1_out and N1_out and Rxy(4)) or (W1_out and S1_out and Rxy(5))) and Cx(2) ) ) then
err_header_not_empty_Req_W_in <= '1';
else
err_header_not_empty_Req_W_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, Req_S_in, E1_out, W1_out, S1_out, Rxy, Cx)
begin
if ( flit_type = "001" and empty = '0' and Req_S_in /= (((S1_out and not E1_out and not W1_out) or (S1_out and E1_out and Rxy(6)) or (S1_out and W1_out and Rxy(7))) and Cx(3)) ) then
err_header_not_empty_Req_S_in <= '1';
else
err_header_not_empty_Req_S_in <= '0';
end if;
end process;
-- Updated !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if (flit_type = "001" and empty = '1' and packet_drop_in /= packet_drop ) then
err_header_empty_packet_drop_in_packet_drop_equal <= '1';
else
err_header_empty_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '1' and packet_drop_in /= '0' ) then
err_tail_not_empty_packet_drop_not_packet_drop_in <= '1';
else
err_tail_not_empty_packet_drop_not_packet_drop_in <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop, packet_drop_in)
begin
if (flit_type = "100" and empty = '0' and packet_drop = '0' and packet_drop_in /= packet_drop ) then
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '1';
else
err_tail_not_empty_not_packet_drop_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (flit_type, empty, packet_drop_in, packet_drop)
begin
if ( ((flit_type /= "001" and flit_type /= "100") or empty = '1') and packet_drop_in /= packet_drop ) then
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '1';
else
err_invalid_or_body_flit_packet_drop_in_packet_drop_equal <= '0';
end if;
end process;
-- Added !
process (packet_drop_order, packet_drop)
begin
if (packet_drop_order /= packet_drop) then
err_packet_drop_order <= '1';
else
err_packet_drop_order <= '0';
end if;
end process;
-- Added !
end behavior; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- board options
constant CFG_ADS_DAU_MEZZ : integer := 1;
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (3);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000013#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 1;
constant CFG_CANIO : integer := 16#C00#;
constant CFG_CANIRQ : integer := (13);
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 2;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 16;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- ********************
-- * Flip Flop tipo D *
-- ********************
-- Con reinicio asíncrono y activador
library ieee; use ieee.std_logic_1164.all;
entity ffden is
port(
clk, rst: in std_logic;
en: in std_logic; -- Activador
d: in std_logic;
q: out std_logic
);
end ffden;
architecture arq of ffden is
begin
process(clk,rst)
begin
if (rst='1') then
q <='0';
elsif (clk'event and clk='1') then
if (en='1') then
q <= d;
end if;
end if;
end process;
end arq;
-- Con una lógica simple de siguiente estado
architecture arq_dos_est of ffden is
signal r_alm: std_logic; -- Registro almacenado
signal r_sig: std_logic; -- Registro siguiente entrada
begin
process(clk,rst)
begin
if (rst='1') then
r_alm <='0';
elsif (clk'event and clk='1') then
r_alm <= r_sig;
end if;
end process;
-- Lógica del siguiente estado
r_sig <= d when en ='1' else
r_alm;
-- Lógica de la salida
q <= r_alm;
end arq_dos_est;
|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 10:33:26 09/30/2015
-- Design Name:
-- Module Name: D_Type_FFs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Several implementations of D-Type Flip Flops
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_Type_FFs is
Port ( D : in STD_LOGIC;
Clk : in STD_LOGIC;
En : in STD_LOGIC;
Pr : in STD_LOGIC;
Clr: in STD_LOGIC;
Q : out STD_LOGIC);
end D_Type_FFs;
architecture Behavioral of D_Type_FFs is
signal Demb : STD_LOGIC;
begin
-- --Basic D Type Flip flop
-- -- with a rising edge
-- --Old school style
-- process (Clk)
-- begin
-- --check for a clk transition
-- if (Clk'event and Clk = '1') then
-- Q <= D;
-- end if;
-- end process;
-- --Basic D Type Flip flop
-- -- with a falling edge
-- --Old school style
-- process (Clk)
-- begin
-- --check for a clk transition
-- if (Clk'event and Clk = '0') then
-- Q <= D;
-- end if;
-- end process;
-- --Basic D Type Flip flop
-- -- with a rising edge
-- -- New school style
-- process (Clk)
-- begin
-- --check for a clk transition
-- if (rising_edge(Clk)) then
-- Q <= D;
-- end if;
-- end process;
-- --Basic D Type Flip flop
-- -- with a rising edge
-- -- New school style
-- process (Clk)
-- begin
-- --check for a clk transition
-- if (falling_edge(Clk)) then
-- Q <= D;
-- end if;
-- end process;
-- -- Basic D Type flip flop
-- -- with a rising edged and enable
-- process(Clk, En)
-- begin
-- if (rising_edge(Clk)) then
-- if (En = '1') then
-- Q <= D;
-- end if;
-- end if;
-- end process;
--
----D type flip flop with asynchonous clear
-- process(Clr, Clk)
-- begin
--
-- if (Clr = '1') then
-- Q <= '0';
-- elsif (rising_edge(Clk)) then
-- Q <= D;
-- end if;
-- end process;
----D type flip flop with asynchonous preset
-- process(Pr, Clk)
-- begin
-- if (Pr = '1') then
-- Q <= '1';
-- elsif (rising_edge(Clk)) then
-- Q <= D;
-- end if;
-- end process;
----D type flip flop with asynchonous preset and clear
-- process(Clr, Pr, Clk)
-- begin
-- if (Clr = '1') then
-- Q <= '0';
-- elsif (Pr = '1') then
-- Q <= '1';
-- elsif (rising_edge(Clk)) then
-- Q <= D;
-- end if;
-- end process;
--
----D type flip flop with synchonous clear
-- process(Clr, Clk)
-- begin
-- if (rising_edge(Clk)) then
-- if (Clr = '1') then
-- Q <= '0';
-- else
-- Q <= D;
-- end if;
-- end if;
-- end process;
--D type flip flop with synchonous clear, style 2
-- Demb <= D and (not Clr);
-- process(Clk)
-- begin
-- if (rising_edge(Clk)) then
-- Q <= Demb;
-- end if;
-- end process;
--D type flip flop with synchonous preset
-- process(Pr, Clk)
-- begin
-- if (rising_edge(Clk)) then
-- if (Pr = '1') then
-- Q <= '1';
-- else
-- Q <= D;
-- end if;
-- end if;
-- end process;
--D type flip flop with synchonous clear, style 2
Demb <= D or Pr;
process(Clk)
begin
if (rising_edge(Clk)) then
Q <= Demb;
end if;
end process;
----D type flip flop with synchonous preset and clear
-- process(Clr, Pr, Clk)
-- begin
-- if (rising_edge(Clk)) then
-- if (Clr = '1') then
-- Q <= '0';
-- elsif (Pr = '1') then
-- Q <= '1';
-- else
-- Q <= D;
-- end if;
-- end if;
-- end process;
--
end Behavioral; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: allclkgen
-- File: allclkgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Clock generator interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
package allclkgen is
component clkgen_virtex2
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_spartan3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex5
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic);
end component;
component clkgen_virtex7
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
freq : integer := 25000);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk90 : out std_ulogic; -- main clock 90deg
clkio : out std_ulogic; -- IO ref clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_axcelerator
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_altera_mf
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_cycloneiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_stratixiii
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end component;
component clkgen_rh_lib18t
generic (
clk_mul : integer := 1;
clk_div : integer := 1);
port (
rst : in std_logic;
clkin : in std_logic;
clk : out std_logic;
sdclk : out std_logic; -- SDRAM clock
clk2x : out std_logic;
clk4x : out std_logic
);
end component;
component clkmul_virtex2
generic ( clk_mul : integer := 2 ; clk_div : integer := 2);
port (
resetin : in std_logic;
clkin : in std_logic;
clk : out std_logic;
resetout: out std_logic
);
end component;
component clkand_unisim
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut025crh
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkand_ut90nhbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkrand_ut130hbd
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic
);
end component;
component clkand_rh_lib18t
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic
);
end component;
component clkmux_unisim
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut130hbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_ut90nhbd
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component clkmux_fusion
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic
);
end component;
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_proasic3
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_fusion
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3e
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component clkgen_proasic3l
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_odiv : integer := 1; -- output divider
pcien : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clkb_odiv: integer := 0;
clkc_odiv: integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic;
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clkb : out std_logic;
clkc : out std_logic);
end component;
component cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component stratix3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
component clkgen_rhumc
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_saed32
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_saed32
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_saed32
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_saed32
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_rhs65
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_rhs65
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_rhs65
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_rhs65
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic -- unscaled 2X clock
);
end component;
component clkinv_dare
port(
i : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_dare
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_rhumc
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_dare
generic (
noclkfb : integer := 1
);
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clk8x : out std_logic
);
end component;
component clkgen_easic90
generic (
clk_mul : integer;
clk_div : integer;
freq : integer;
pcisysclk : integer;
pcien : integer);
port (
clkin : in std_ulogic;
pciclkin : in std_ulogic;
clk : out std_ulogic;
clk2x : out std_ulogic;
clk4x : out std_ulogic;
clkn : out std_ulogic;
lock : out std_ulogic);
end component;
component clkmux_dare
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkmux_rhlib18t
port(
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkand_n2x
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux_n2x
port (
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end component;
component clkgen_n2x
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk270en : integer := 0);
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic; -- unscaled 2X clock
clk270 : out std_ulogic -- clk shifted 270 degrees
);
end component;
component clkgen_ut130hbd
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
clk4x : out std_ulogic;
clk8x : out std_ulogic;
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component clkgen_ut90nhbd is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0); -- enable clock select
port (
clkin : in std_ulogic;
pciclkin: in std_ulogic;
clk : out std_ulogic; -- main clock
clkn : out std_ulogic; -- inverted main clock
clk2x : out std_ulogic; -- double clock
sdclk : out std_ulogic; -- SDRAM clock
pciclk : out std_ulogic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk1xu : out std_ulogic; -- unscaled clock
clk2xu : out std_ulogic -- unscaled 2X clock
);
end component;
component sim_pll is
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
-- Frequency limits in kHz, for checking only
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
end;
|
-- NEED RESULT: ARCH00320.P2: Execution continues with first statement after last statement in process is executed passed
-- NEED RESULT: ARCH00320.P1: Execution continues with first statement after last statement in process is executed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00320
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.2 (8)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00320)
-- ENT00320_Test_Bench(ARCH00320_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00320 of E00000 is
signal s1, s2 : boolean := false;
begin
P1 :
process ( s1 )
variable count : Integer := 0 ;
variable First_Time : boolean := True ;
variable SavTime : Time := Std.Standard.Now ;
begin
count := count + 1;
if First_Time then
First_Time := False ;
s1 <= transport Not s1 after 10 ns ;
else
test_report ( "ARCH00320.P1" ,
"Execution continues with first statement after "&
"last statement in process is executed" ,
((SavTime + 10 ns) = Std.Standard.Now) and
(count = 2) and s1) ;
end if ;
end process P1 ;
P2 :
process
variable count : Integer := 0 ;
variable First_Time : boolean := True ;
variable SavTime : Time := Std.Standard.Now ;
variable correct : boolean := False ;
begin
count := count + 1;
if First_Time then
First_Time := False ;
s2 <= transport Not s2 after 10 ns ;
wait on s2 ;
correct := s2 and
(count = 1) and
((SavTime + 10 ns) = Std.Standard.Now) ;
SavTime := Std.Standard.Now ;
else
test_report ( "ARCH00320.P2" ,
"Execution continues with first statement after "&
"last statement in process is executed" ,
(SavTime = Std.Standard.Now) and s2 and correct and
(count = 2) ) ;
wait;
end if ;
end process P2 ;
end ARCH00320 ;
entity ENT00320_Test_Bench is
end ENT00320_Test_Bench ;
architecture ARCH00320_Test_Bench of ENT00320_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00320 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00320_Test_Bench ;
|
entity tb_arr04 is
end tb_arr04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_arr04 is
signal clk : std_logic;
signal rst : std_logic;
signal sel_i : std_logic;
signal v : std_logic;
signal r : std_logic_vector(0 to 1);
begin
dut: entity work.arr04
port map (clk => clk, rst => rst, sel_i => sel_i, v => v, res => r);
process
constant siv : std_logic_vector := b"0010";
constant v_v : std_logic_vector := b"0011";
constant r1v : std_logic_vector := b"0011";
constant r0v : std_logic_vector := b"0001";
begin
clk <= '0';
rst <= '1';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
rst <= '0';
for i in siv'range loop
sel_i <= siv (i);
v <= v_v (i);
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert r(0) = r0v(i) severity failure;
assert r(1) = r1v(i) severity failure;
end loop;
wait;
end process;
end behav;
|
--
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake ([email protected])
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
library ieee;
use ieee.std_logic_1164.all;
use work.cryptopan.all;
entity sbox is
port (
clk : in std_logic;
reset : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0));
end sbox;
architecture rtl of sbox is
signal data : std_logic_vector(7 downto 0);
attribute syn_romstyle : string;
attribute syn_romstyle of data : signal is "logic";
begin
CLKLOGIC : process (clk, reset)
begin
if reset = '1' then
douta <= (others => '0');
elsif clk'event and clk = '1' then
douta <= data;
end if;
end process CLKLOGIC;
DATALOGIC : process (addra)
begin
case addra is
when "00000000" => data <= X"63";
when "00000001" => data <= X"7C";
when "00000010" => data <= X"77";
when "00000011" => data <= X"7B";
when "00000100" => data <= X"F2";
when "00000101" => data <= X"6B";
when "00000110" => data <= X"6F";
when "00000111" => data <= X"C5";
when "00001000" => data <= X"30";
when "00001001" => data <= X"01";
when "00001010" => data <= X"67";
when "00001011" => data <= X"2B";
when "00001100" => data <= X"FE";
when "00001101" => data <= X"D7";
when "00001110" => data <= X"AB";
when "00001111" => data <= X"76";
when "00010000" => data <= X"CA";
when "00010001" => data <= X"82";
when "00010010" => data <= X"C9";
when "00010011" => data <= X"7D";
when "00010100" => data <= X"FA";
when "00010101" => data <= X"59";
when "00010110" => data <= X"47";
when "00010111" => data <= X"F0";
when "00011000" => data <= X"AD";
when "00011001" => data <= X"D4";
when "00011010" => data <= X"A2";
when "00011011" => data <= X"AF";
when "00011100" => data <= X"9C";
when "00011101" => data <= X"A4";
when "00011110" => data <= X"72";
when "00011111" => data <= X"C0";
when "00100000" => data <= X"B7";
when "00100001" => data <= X"FD";
when "00100010" => data <= X"93";
when "00100011" => data <= X"26";
when "00100100" => data <= X"36";
when "00100101" => data <= X"3F";
when "00100110" => data <= X"F7";
when "00100111" => data <= X"CC";
when "00101000" => data <= X"34";
when "00101001" => data <= X"A5";
when "00101010" => data <= X"E5";
when "00101011" => data <= X"F1";
when "00101100" => data <= X"71";
when "00101101" => data <= X"D8";
when "00101110" => data <= X"31";
when "00101111" => data <= X"15";
when "00110000" => data <= X"04";
when "00110001" => data <= X"C7";
when "00110010" => data <= X"23";
when "00110011" => data <= X"C3";
when "00110100" => data <= X"18";
when "00110101" => data <= X"96";
when "00110110" => data <= X"05";
when "00110111" => data <= X"9A";
when "00111000" => data <= X"07";
when "00111001" => data <= X"12";
when "00111010" => data <= X"80";
when "00111011" => data <= X"E2";
when "00111100" => data <= X"EB";
when "00111101" => data <= X"27";
when "00111110" => data <= X"B2";
when "00111111" => data <= X"75";
when "01000000" => data <= X"09";
when "01000001" => data <= X"83";
when "01000010" => data <= X"2C";
when "01000011" => data <= X"1A";
when "01000100" => data <= X"1B";
when "01000101" => data <= X"6E";
when "01000110" => data <= X"5A";
when "01000111" => data <= X"A0";
when "01001000" => data <= X"52";
when "01001001" => data <= X"3B";
when "01001010" => data <= X"D6";
when "01001011" => data <= X"B3";
when "01001100" => data <= X"29";
when "01001101" => data <= X"E3";
when "01001110" => data <= X"2F";
when "01001111" => data <= X"84";
when "01010000" => data <= X"53";
when "01010001" => data <= X"D1";
when "01010010" => data <= X"00";
when "01010011" => data <= X"ED";
when "01010100" => data <= X"20";
when "01010101" => data <= X"FC";
when "01010110" => data <= X"B1";
when "01010111" => data <= X"5B";
when "01011000" => data <= X"6A";
when "01011001" => data <= X"CB";
when "01011010" => data <= X"BE";
when "01011011" => data <= X"39";
when "01011100" => data <= X"4A";
when "01011101" => data <= X"4C";
when "01011110" => data <= X"58";
when "01011111" => data <= X"CF";
when "01100000" => data <= X"D0";
when "01100001" => data <= X"EF";
when "01100010" => data <= X"AA";
when "01100011" => data <= X"FB";
when "01100100" => data <= X"43";
when "01100101" => data <= X"4D";
when "01100110" => data <= X"33";
when "01100111" => data <= X"85";
when "01101000" => data <= X"45";
when "01101001" => data <= X"F9";
when "01101010" => data <= X"02";
when "01101011" => data <= X"7F";
when "01101100" => data <= X"50";
when "01101101" => data <= X"3C";
when "01101110" => data <= X"9F";
when "01101111" => data <= X"A8";
when "01110000" => data <= X"51";
when "01110001" => data <= X"A3";
when "01110010" => data <= X"40";
when "01110011" => data <= X"8F";
when "01110100" => data <= X"92";
when "01110101" => data <= X"9D";
when "01110110" => data <= X"38";
when "01110111" => data <= X"F5";
when "01111000" => data <= X"BC";
when "01111001" => data <= X"B6";
when "01111010" => data <= X"DA";
when "01111011" => data <= X"21";
when "01111100" => data <= X"10";
when "01111101" => data <= X"FF";
when "01111110" => data <= X"F3";
when "01111111" => data <= X"D2";
when "10000000" => data <= X"CD";
when "10000001" => data <= X"0C";
when "10000010" => data <= X"13";
when "10000011" => data <= X"EC";
when "10000100" => data <= X"5F";
when "10000101" => data <= X"97";
when "10000110" => data <= X"44";
when "10000111" => data <= X"17";
when "10001000" => data <= X"C4";
when "10001001" => data <= X"A7";
when "10001010" => data <= X"7E";
when "10001011" => data <= X"3D";
when "10001100" => data <= X"64";
when "10001101" => data <= X"5D";
when "10001110" => data <= X"19";
when "10001111" => data <= X"73";
when "10010000" => data <= X"60";
when "10010001" => data <= X"81";
when "10010010" => data <= X"4F";
when "10010011" => data <= X"DC";
when "10010100" => data <= X"22";
when "10010101" => data <= X"2A";
when "10010110" => data <= X"90";
when "10010111" => data <= X"88";
when "10011000" => data <= X"46";
when "10011001" => data <= X"EE";
when "10011010" => data <= X"B8";
when "10011011" => data <= X"14";
when "10011100" => data <= X"DE";
when "10011101" => data <= X"5E";
when "10011110" => data <= X"0B";
when "10011111" => data <= X"DB";
when "10100000" => data <= X"E0";
when "10100001" => data <= X"32";
when "10100010" => data <= X"3A";
when "10100011" => data <= X"0A";
when "10100100" => data <= X"49";
when "10100101" => data <= X"06";
when "10100110" => data <= X"24";
when "10100111" => data <= X"5C";
when "10101000" => data <= X"C2";
when "10101001" => data <= X"D3";
when "10101010" => data <= X"AC";
when "10101011" => data <= X"62";
when "10101100" => data <= X"91";
when "10101101" => data <= X"95";
when "10101110" => data <= X"E4";
when "10101111" => data <= X"79";
when "10110000" => data <= X"E7";
when "10110001" => data <= X"C8";
when "10110010" => data <= X"37";
when "10110011" => data <= X"6D";
when "10110100" => data <= X"8D";
when "10110101" => data <= X"D5";
when "10110110" => data <= X"4E";
when "10110111" => data <= X"A9";
when "10111000" => data <= X"6C";
when "10111001" => data <= X"56";
when "10111010" => data <= X"F4";
when "10111011" => data <= X"EA";
when "10111100" => data <= X"65";
when "10111101" => data <= X"7A";
when "10111110" => data <= X"AE";
when "10111111" => data <= X"08";
when "11000000" => data <= X"BA";
when "11000001" => data <= X"78";
when "11000010" => data <= X"25";
when "11000011" => data <= X"2E";
when "11000100" => data <= X"1C";
when "11000101" => data <= X"A6";
when "11000110" => data <= X"B4";
when "11000111" => data <= X"C6";
when "11001000" => data <= X"E8";
when "11001001" => data <= X"DD";
when "11001010" => data <= X"74";
when "11001011" => data <= X"1F";
when "11001100" => data <= X"4B";
when "11001101" => data <= X"BD";
when "11001110" => data <= X"8B";
when "11001111" => data <= X"8A";
when "11010000" => data <= X"70";
when "11010001" => data <= X"3E";
when "11010010" => data <= X"B5";
when "11010011" => data <= X"66";
when "11010100" => data <= X"48";
when "11010101" => data <= X"03";
when "11010110" => data <= X"F6";
when "11010111" => data <= X"0E";
when "11011000" => data <= X"61";
when "11011001" => data <= X"35";
when "11011010" => data <= X"57";
when "11011011" => data <= X"B9";
when "11011100" => data <= X"86";
when "11011101" => data <= X"C1";
when "11011110" => data <= X"1D";
when "11011111" => data <= X"9E";
when "11100000" => data <= X"E1";
when "11100001" => data <= X"F8";
when "11100010" => data <= X"98";
when "11100011" => data <= X"11";
when "11100100" => data <= X"69";
when "11100101" => data <= X"D9";
when "11100110" => data <= X"8E";
when "11100111" => data <= X"94";
when "11101000" => data <= X"9B";
when "11101001" => data <= X"1E";
when "11101010" => data <= X"87";
when "11101011" => data <= X"E9";
when "11101100" => data <= X"CE";
when "11101101" => data <= X"55";
when "11101110" => data <= X"28";
when "11101111" => data <= X"DF";
when "11110000" => data <= X"8C";
when "11110001" => data <= X"A1";
when "11110010" => data <= X"89";
when "11110011" => data <= X"0D";
when "11110100" => data <= X"BF";
when "11110101" => data <= X"E6";
when "11110110" => data <= X"42";
when "11110111" => data <= X"68";
when "11111000" => data <= X"41";
when "11111001" => data <= X"99";
when "11111010" => data <= X"2D";
when "11111011" => data <= X"0F";
when "11111100" => data <= X"B0";
when "11111101" => data <= X"54";
when "11111110" => data <= X"BB";
when "11111111" => data <= X"16";
when others => null;
end case;
end process DATALOGIC;
end rtl;
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
-- "Virtual" memory banks
use techmap.types_mem.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
entity asic_top is port
(
--! Input reset. Active HIGH.
i_rst : in std_logic;
--! Differential clock (LVDS) positive/negaive signal.
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
--! GPIO: [11:4] LEDs; [3:0] DIP switch
io_gpio : inout std_logic_vector(11 downto 0);
--! Timers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 TAP (debug port) signals: DO NOT SUPPORT FIRMWARE OUTPUT!
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! SPI Flash/ext OTP
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
-- OTP power
io_otp_gnd : inout std_logic;
io_otp_vdd : inout std_logic;
io_otp_vdd18 : inout std_logic;
io_otp_upp : inout std_logic;
--! Ethernet MAC PHY interface signals
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
end asic_top;
architecture arch_asic_top of asic_top is
component riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
signal ib_rst : std_logic;
signal ib_clk_tcxo : std_logic;
signal ib_sclk_n : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
signal ob_pwm : std_logic_vector(1 downto 0);
signal ib_uart1_rd : std_logic;
signal ob_uart1_td : std_logic;
signal ib_uart2_rd : std_logic;
signal ob_uart2_td : std_logic;
signal ib_flash_si : std_logic;
signal ob_flash_so : std_logic;
signal ob_flash_sck : std_logic;
signal ob_flash_csn : std_logic;
--! JTAG signals:
signal ib_jtag_tck : std_logic;
signal ib_jtag_ntrst : std_logic;
signal ib_jtag_tms : std_logic;
signal ib_jtag_tdi : std_logic;
signal ob_jtag_tdo : std_logic;
signal ob_jtag_vref : std_logic;
signal ib_gmiiclk : std_logic;
signal ib_eth_mdio : std_logic;
signal ob_eth_mdio : std_logic;
signal ob_eth_mdio_oe : std_logic;
signal w_eth_gtx_clk : std_logic;
signal w_eth_gtx_clk_90 : std_logic;
signal w_ext_reset : std_ulogic; -- External system reset or PLL unlcoked. MUST NOT USED BY DEVICES.
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal w_clk_bus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal w_pll_lock : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal wb_otp_wdata : std_logic_vector(15 downto 0);
signal wb_otp_addr : std_logic_vector(11 downto 0);
signal w_otp_we : std_logic;
signal w_otp_re : std_logic;
signal wb_otp_rdata : std_logic_vector(15 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclk0 : idsbuf_tech generic map (CFG_PADTECH) port map (
i_sclk_p, i_sclk_n, ib_clk_tcxo);
ird1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart1_rd, i_uart1_rd);
otd1 : obuf_tech generic map(CFG_PADTECH) port map (o_uart1_td, ob_uart1_td);
ird2 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart2_rd, i_uart2_rd);
otd2 : obuf_tech generic map(CFG_PADTECH) port map (o_uart2_td, ob_uart2_td);
iflshsi : ibuf_tech generic map(CFG_PADTECH) port map (ib_flash_si, i_flash_si);
oflshso : obuf_tech generic map(CFG_PADTECH) port map (o_flash_so, ob_flash_so);
oflshsck : obuf_tech generic map(CFG_PADTECH) port map (o_flash_sck, ob_flash_sck);
oflshcsn : obuf_tech generic map(CFG_PADTECH) port map (o_flash_csn, ob_flash_csn);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(CFG_PADTECH)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
pwmx : for i in 0 to 1 generate
opwm0 : obuf_tech generic map(CFG_PADTECH) port map (o_pwm(i), ob_pwm(i));
end generate;
--! JTAG signals:
ijtck0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tck, i_jtag_tck);
ijtrst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_ntrst, i_jtag_ntrst);
ijtms0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tms, i_jtag_tms);
ijtdi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tdi, i_jtag_tdi);
ojtdo0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_tdo, ob_jtag_tdo);
ojvrf0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_vref, ob_jtag_vref);
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
iomdio : iobuf_tech generic map(CFG_PADTECH)
port map (ib_eth_mdio, io_emdio, ob_eth_mdio, ob_eth_mdio_oe);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => ib_rst,
i_clk => ib_gmiiclk,
o_clk => w_eth_gtx_clk,
o_clkp90 => w_eth_gtx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
o_egtx_clk <= w_eth_gtx_clk;
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH
) port map (
i_reset => ib_rst,
i_clk_tcxo => ib_clk_tcxo,
o_clk_bus => w_clk_bus,
o_locked => w_pll_lock
);
w_ext_reset <= ib_rst or not w_pll_lock;
otp0 : otp_tech generic map (
memtech => CFG_MEMTECH
) port map (
clk => w_clk_bus, -- only for FPGA
i_we => w_otp_we,
i_re => w_otp_re,
i_addr => wb_otp_addr,
i_wdata => wb_otp_wdata,
o_rdata => wb_otp_rdata,
io_gnd => io_otp_gnd,
io_vdd => io_otp_vdd,
io_vdd18 => io_otp_vdd18,
io_upp => io_otp_upp
);
soc0 : riscv_soc port map
(
i_rst => w_ext_reset,
i_clk => w_clk_bus,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
--! GP Timers
o_pwm => ob_pwm,
--! JTAG signals:
i_jtag_tck => ib_jtag_tck,
i_jtag_ntrst => ib_jtag_ntrst,
i_jtag_tms => ib_jtag_tms,
i_jtag_tdi => ib_jtag_tdi,
o_jtag_tdo => ob_jtag_tdo,
o_jtag_vref => ob_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => ib_uart1_rd,
o_uart1_td => ob_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => ib_uart2_rd,
o_uart2_td => ob_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => ib_flash_si,
o_flash_so => ob_flash_so,
o_flash_sck => ob_flash_sck,
o_flash_csn => ob_flash_csn,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => wb_otp_rdata,
o_otp_d => wb_otp_wdata,
o_otp_a => wb_otp_addr,
o_otp_we => w_otp_we,
o_otp_re => w_otp_re,
--! Ethernet MAC PHY interface signals
i_etx_clk => i_etx_clk,
i_erx_clk => i_erx_clk,
i_erxd => i_erxd,
i_erx_dv => i_erx_dv,
i_erx_er => i_erx_er,
i_erx_col => i_erx_col,
i_erx_crs => i_erx_crs,
i_emdint => i_emdint,
o_etxd => o_etxd,
o_etx_en => o_etx_en,
o_etx_er => o_etx_er,
o_emdc => o_emdc,
i_eth_mdio => ib_eth_mdio,
o_eth_mdio => ob_eth_mdio,
o_eth_mdio_oe => ob_eth_mdio_oe,
i_eth_gtx_clk => w_eth_gtx_clk,
i_eth_gtx_clk_90 => w_eth_gtx_clk_90,
o_erstn => o_erstn,
-- GNSS Sub-system signals:
i_clk_adc => '0',
i_gps_I => "00",
i_gps_Q => "00",
i_glo_I => "00",
i_glo_Q => "00",
o_pps => open,
i_gps_ld => '0',
i_glo_ld => '0',
o_max_sclk => open,
o_max_sdata => open,
o_max_ncs => open,
i_antext_stat => '0',
i_antext_detect => '0',
o_antext_ena => open,
o_antint_contr => open
);
end arch_asic_top;
|
-------------------------------------------------------------------------------
-- Title : FSMC Slave, synchronous
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-------------------------------------------------------------------------------
-- Description: This is slave to the flexible static memory controller (FSMC)
-- of a STM32 device. The slave is a busmaster to the local bus.
-- Data can be transfered to and from the bus slaves on the bus.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2014, German Aerospace Center (DLR)
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.fsmcslave_pkg.all;
use work.bus_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity fsmcslave is
port (
-- slave side of the STM32's FSMC port
fsmcslave_o : out fsmc_in_type;
fsmcslave_i : in fsmc_out_type;
-- master port of loa bus
bus_o : out busmaster_out_type;
bus_i : in busmaster_in_type;
clk : in std_logic
);
end fsmcslave;
-------------------------------------------------------------------------------
architecture behavioral of fsmcslave is
type fsmc_out_type_array is array(1 downto 0) of fsmc_out_type;
type entity_name_state_type is (
IDLE, -- Idle state:
READ1,
READ2
);
type entity_name_type is record
nadv_old : std_logic;
addr : std_logic_vector(14 downto 0);
data : std_logic_vector(15 downto 0);
state : entity_name_state_type;
bus_o : busmaster_out_type;
reg_fsmcslave_i : fsmc_out_type_array;
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : entity_name_type :=
(nadv_old => '0',
data => (others => '0'),
addr => (others => '0'),
state => IDLE,
bus_o => (
addr => (others => '0'),
data => (others => '0'),
re => '0',
we => '0'),
reg_fsmcslave_i => ( -- init synchronizer with idle state of
-- fsmc, to aviod triggering the edge
-- detection
1 => (
data => (others => '0'),
adv_n => '1',
wr_n => '1',
oe_n => '1',
cs_n => '1'),
0 => (
data => (others => '0'),
adv_n => '1',
wr_n => '1',
oe_n => '1',
cs_n => '1'))
);
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and registered signals
----------------------------------------------------------------------------
fsmcslave_o.data <= r.data;
bus_o <= r.bus_o;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(bus_i, fsmcslave_i, r)
variable v : entity_name_type;
begin
v := r;
-- default values
v.bus_o.addr := (others => '0');
v.bus_o.data := (others => '0');
v.bus_o.we := '0';
v.bus_o.re := '0';
-- (0) is first stage of synchronizer, (1) is second
v.reg_fsmcslave_i(1 downto 0) := r.reg_fsmcslave_i(0) & fsmcslave_i;
case r.state is
when IDLE =>
-- if nadv is low, store addr
if(r.reg_fsmcslave_i(0).adv_n = '0') then
v.addr := r.reg_fsmcslave_i(0).data(14 downto 0);
end if;
-- Falling edge of WRn starts write access on loa bus
if(r.reg_fsmcslave_i(1).wr_n = '0' and r.reg_fsmcslave_i(0).wr_n = '1') then
v.bus_o.addr := r.addr;
v.bus_o.data := r.reg_fsmcslave_i(1).data;
v.bus_o.we := '1';
end if;
-- Raising edge of OEn starts read access
-- Note: Tristate driver should be in the toplevel
if(r.reg_fsmcslave_i(1).oe_n = '1' and r.reg_fsmcslave_i(0).oe_n = '0') then
v.bus_o.addr := r.addr;
v.bus_o.re := '1';
v.state := READ1;
end if;
when READ1 =>
-----------------------------------------------------------------------
-- wait for bus to react
-----------------------------------------------------------------------
v.state := READ2;
when READ2 =>
v.data := bus_i.data;
v.state := IDLE;
end case;
rin <= v;
end process comb_proc;
end behavioral;
|
-- file: UARTClockManager.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____15.360______0.000______50.0______407.321____200.759
-- CLK_OUT2____32.000______0.000______50.0______348.651____200.759
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________32.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity UARTClockManager is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic
);
end UARTClockManager;
architecture xilinx of UARTClockManager is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "UARTClockManager,clk_wiz_v3_6,{component_name=UARTClockManager,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=31.250,clkin2_period=31.250,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 24,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 50,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 24,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 31.250,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => locked_unused,
RST => RESET,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
-- $Id: sys_tst_mig_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_mig_arty - syn
-- Description: test of arty ddr and its mig controller
--
-- Dependencies: vlib/xlib/bufg_unisim
-- bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- cdclib/cdc_pulse
-- bplib/bpgen/bp_rs232_2line_iob
-- rlink/rlink_sp2c
-- tst_mig
-- bplib/arty/migui_arty (generated core)
-- bplib/sysmon/sysmonx_rbus_arty
-- rbus/rbd_usracc
-- rbus/rb_sres_or_3
--
-- Test bench: tb/tb_tst_mig_arty
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2022.1; ghdl 0.34-2.0.0
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-07-05 1247 2022.1 xc7a35t-1l 4325 4197 415 1 1699
-- 2019-02-02 1108 2018.3 xc7a35t-1l 4323 4537 444 1 1874
-- 2019-02-02 1108 2017.2 xc7a35t-1l 4330 4773 444 1 1774
-- 2019-01-02 1101 2017.2 xc7a35t-1l 4320 4773 462 1 1770
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-07-05 1247 1.0.1 use bufg_unisim
-- 2018-12-26 1094 1.0 Initial version
-- 2018-12-23 1092 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib_arty.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_mig_arty is -- top level
-- implements arty_mig_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4; -- arty pwrmon (pos)
DDR3_DQ : inout slv16; -- dram: data in/out
DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR3_ADDR : out slv14; -- dram: address
DDR3_BA : out slv3; -- dram: bank address
DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR3_WE_N : out slbit; -- dram: write enable (act.low)
DDR3_RESET_N : out slbit; -- dram: reset (act.low)
DDR3_CK_P : out slv1; -- dram: clock (diff-p)
DDR3_CK_N : out slv1; -- dram: clock (diff-n)
DDR3_CKE : out slv1; -- dram: clock enable
DDR3_CS_N : out slv1; -- dram: chip select (act.low)
DDR3_DM : out slv2; -- dram: data input mask
DDR3_ODT : out slv1 -- dram: on-die termination
);
end sys_tst_mig_arty;
architecture syn of sys_tst_mig_arty is
signal CLK100_BUF : slbit := '0';
signal XX_CLK : slbit := '0'; -- kept to keep clock setup similar
signal XX_CE_USEC : slbit := '0'; -- to w11a or other 'normal' systems
signal XX_CE_MSEC : slbit := '0'; --
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLKMIG : slbit := '0'; -- sync'ed to CLKMIG
signal MEM_RESET : slbit := '0';
signal MEM_RESET_RRI : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_CMD : slv3 := (others=>'0');
signal APP_EN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_WREN : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_WDF_RDY : slbit := '0';
signal APP_SR_REQ : slbit := '0';
signal APP_REF_REQ : slbit := '0';
signal APP_ZQ_REQ : slbit := '0';
signal APP_SR_ACTIVE : slbit := '0';
signal APP_REF_ACK : slbit := '0';
signal APP_ZQ_ACK : slbit := '0';
signal MIG_UI_CLK : slbit := '0';
signal MIG_UI_CLK_SYNC_RST : slbit := '0';
signal MIG_INIT_CALIB_COMPLETE : slbit := '0';
signal MIG_SYS_RST : slbit := '0';
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal R_DIMCNT : slv2 := (others=>'0');
signal R_DIMFLG : slbit := '0';
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0105"; -- tst_mig
constant sysid_board : slv8 := x"07"; -- arty
constant sysid_vers : slv8 := x"00";
begin
CLK100_BUFG: bufg_unisim
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 10, -- vco 1000 MHz
CLK2_OUTDIV => 6, -- mig sys 166.6 MHz
CLK3_OUTDIV => 5, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => XX_CLK,
CE0_USEC => XX_CE_USEC,
CE0_MSEC => XX_CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
-- Note: CLK0 is generated as in 'normal' systems to keep PPL/MMCM setup
-- as similar as possible. The CE_USEC and CE_MSEC pulses are forwarded
-- from the 80 MHz CLK0 domain to the 83.333 MHz MIG UI_CLK domain
CDC_CEUSEC : cdc_pulse -- provide CLK side CE_USEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_USEC,
BUSY => open,
POUT => CE_USEC
);
CDC_CEMSEC : cdc_pulse -- provide CLK side CE_MSEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_MSEC,
BUSY => open,
POUT => CE_MSEC
);
CDC_CLKMIG_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLKMIG,
DI => LOCKED,
DO => LOCKED_CLKMIG
);
IOB_RS232 : bp_rs232_2line_iob
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 8, -- 256 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => '0', -- FIXME: no RESET
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_mig
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
MAWIDTH => mig_mawidth,
MWIDTH => mig_mwidth)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
MIG_UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
MIG_INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
MIG_DEVICE_TEMP_I => XADC_TEMP
);
MIG_CTL: migui_arty -- MIG iface -----------------
port map (
DDR3_DQ => DDR3_DQ,
DDR3_DQS_P => DDR3_DQS_P,
DDR3_DQS_N => DDR3_DQS_N,
DDR3_ADDR => DDR3_ADDR,
DDR3_BA => DDR3_BA,
DDR3_RAS_N => DDR3_RAS_N,
DDR3_CAS_N => DDR3_CAS_N,
DDR3_WE_N => DDR3_WE_N,
DDR3_RESET_N => DDR3_RESET_N,
DDR3_CK_P => DDR3_CK_P,
DDR3_CK_N => DDR3_CK_N,
DDR3_CKE => DDR3_CKE,
DDR3_CS_N => DDR3_CS_N,
DDR3_DM => DDR3_DM,
DDR3_ODT => DDR3_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
UI_CLK => CLK,
UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
SYS_CLK_I => CLKMIG,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => XADC_TEMP,
SYS_RST => MIG_SYS_RST
);
MIG_SYS_RST <= (not LOCKED_CLKMIG) or I_BTN(3); -- provisional !
SMRB: sysmonx_rbus_arty
generic map ( -- use default INIT_ (LP: Vccint=0.95)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP,
VPWRN => A_VPWRN,
VPWRP => A_VPWRP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
proc_dim: process (CLKMIG)
begin
if rising_edge(CLKMIG) then
R_DIMCNT <= slv(unsigned(R_DIMCNT) + 1);
if unsigned(R_DIMCNT) = 0 then
R_DIMFLG <= '1';
else
R_DIMFLG <= '0';
end if;
end if;
end process proc_dim;
RB_LAM(0) <= RB_LAM_TST;
O_LED(1) <= SER_MONI.txact;
O_LED(0) <= SER_MONI.rxact;
-- red LED for serious error conditions
O_RGBLED0(0) <= R_DIMFLG and (I_BTN(0) or not LOCKED);
O_RGBLED1(0) <= R_DIMFLG and (I_BTN(0));
O_RGBLED2(0) <= R_DIMFLG and (I_BTN(0) or MIG_UI_CLK_SYNC_RST);
O_RGBLED3(0) <= R_DIMFLG and (I_BTN(0) or not MIG_INIT_CALIB_COMPLETE);
-- green LED for activity
O_RGBLED0(1) <= R_DIMFLG and (I_BTN(1));
O_RGBLED1(1) <= R_DIMFLG and (I_BTN(1));
O_RGBLED2(1) <= R_DIMFLG and (I_BTN(1) or not APP_RDY);
O_RGBLED3(1) <= R_DIMFLG and (I_BTN(1) or not APP_WDF_RDY);
-- blue LED currently unused
O_RGBLED0(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED1(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED2(2) <= R_DIMFLG and (I_BTN(2));
O_RGBLED3(2) <= R_DIMFLG and (I_BTN(2));
end syn;
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;
entity i2c_top is
generic(cnt_1ms : natural := 50_000; -- 20ns*50_000 = 1ms
cnt_10ms : natural := 500_000); --20ns*500_000 = 10ms
port(
clk_in : in std_logic; -- clk40, W19, LVCMOS33
phy_rstn_out : out std_logic
);
end i2c_top;
architecture rtl of i2c_top is
signal phy_resetn : std_logic := '0';
begin
phy_rstn_out <= phy_resetn;
phy_resetn_process : process(clk_in, phy_resetn) is
variable cnt : natural range 0 to cnt_1ms := 0; --1ms
begin
if (rising_edge(clk_in)) then
if phy_resetn = '0' then --resetn
if(cnt < cnt_1ms)then --cnt
cnt := cnt + 1;
elsif(cnt = cnt_1ms)then
cnt := 0;
phy_resetn <= '1';
else null;
end if; --cnt
else null;
end if; --resetn check
end if; --clk
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: NTU ATHNENS - BNL
-- Engineer: Panagiotis Gkountoumis
--
-- Create Date: 18.04.2016 13:00:21
-- Design Name:
-- Module Name: config_logic - Behavioral
-- Project Name: MMFE8
-- Target Devices: Arix7 xc7a200t-2fbg484 and xc7a200t-3fbg484
-- Tool Versions: Vivado 2016.2
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use UNISIM.VComponents.all;
entity i2c_top is
generic(cnt_1ms : natural := 50_000; -- 20ns*50_000 = 1ms
cnt_10ms : natural := 500_000); --20ns*500_000 = 10ms
port(
clk_in : in std_logic; -- clk40, W19, LVCMOS33
phy_rstn_out : out std_logic
);
end i2c_top;
architecture rtl of i2c_top is
signal phy_resetn : std_logic := '0';
begin
phy_rstn_out <= phy_resetn;
phy_resetn_process : process(clk_in, phy_resetn) is
variable cnt : natural range 0 to cnt_1ms := 0; --1ms
begin
if (rising_edge(clk_in)) then
if phy_resetn = '0' then --resetn
if(cnt < cnt_1ms)then --cnt
cnt := cnt + 1;
elsif(cnt = cnt_1ms)then
cnt := 0;
phy_resetn <= '1';
else null;
end if; --cnt
else null;
end if; --resetn check
end if; --clk
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Data de criação: 18 de setembro de 2014;
-- Module Name: Teste de interface de recepção de dados;
-- Used TAB of 4 Spaces
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity interface_tb is
end interface_tb;
architecture Behavioral of interface_tb is
----------------------------------------------
-- Constants
----------------------------------------------
constant MAIN_CLK_PER : time := 20 ns; -- 50 MHz
constant MAIN_CLK : integer := 50;
constant BAUD_RATE : integer := 9600; -- Bits per Second
constant RST_LVL : std_logic := '1'; -- Active Level of Reset
----------------------------------------------
-- Signal Declaration
----------------------------------------------
-- Clock and reset Signals
signal clk_50m : std_logic := '0';
signal rst : std_logic;
signal rx_ready_in : std_logic;
signal rx_data_in : std_logic_vector(7 downto 0);
-- componente descrito como manda o documento de arquitetura,
-- segundo fontes, caso o mapeamento das portas seja esse, funciona
-- independentemente da linguagem.
component interfaceControl is
port (
clk: in std_logic;
reset: in std_logic;
rx_data_ready: in std_logic;
rx_data: in std_logic_vector(7 downto 0);
data_a: out std_logic_vector(7 downto 0);
data_b: out std_logic_vector(7 downto 0);
operation: out std_logic_vector(7 downto 0)
);
end component;
begin
----------------------------------------------
-- Components Instantiation
----------------------------------------------
uut: component interfaceControl port map(
-- Controle
clk => clk_50m, -- seta clock para o gerado por este rtl
reset => rst, -- seta o reset para o gerado por este rtl
-- interface de entrada
rx_data_ready => rx_ready_in, -- seta o pino que anuncia a transmissão
rx_data => rx_data_in, -- seta o pino que tem os dados da transmissão
-- Saídas
data_a => open,
data_b => open,
operation => open
);
----------------------------------------------
-- Main Signals Generation
----------------------------------------------
-- gera clocl que é enviado para o modulo de interface_control
main_clock_generation : process
begin
wait for MAIN_CLK_PER / 2;
clk_50m <= not clk_50m;
end process;
envia_dados : process
variable temp : integer := 1;
begin
--verifica qual o valor de temp, pois temp define qual dado será enviado
if temp = 1 then
rx_data_in <= "00000001";
temp:= temp +1;
elsif temp = 2 then
rx_data_in <= "01000010";
temp:= temp+1;
else
rx_data_in <= "11111111";
end if;
-- atraso
wait for 100ns;
-- rx_ready_in fica com valor '1' durante tempo de um pulso de clock
rx_ready_in <= '1';
wait for MAIN_CLK_PER / 2;
rx_ready_in <= '0';
-- reinicia a variavel temp e envia um reset caso 3 dados já forem enviados
if temp = 3 then
temp := 1;
wait for 200ns;
rst <= '1';
wait for MAIN_CLK_PER /2;
rst <= '0';
end if;
end process envia_dados;
end Behavioral; |
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_dezctr is
end tb_dezctr;
-- Beim Testen den Prescaler anpassen
architecture sim of tb_dezctr is
component dezctr
port (
clk50 : in std_logic;
reset_n : in std_logic;
sw_i : in std_logic_vector(9 downto 0);
pb_i : in std_logic_vector(1 downto 0);
ss0_o : out std_logic_vector(7 downto 0);
ss1_o : out std_logic_vector(7 downto 0);
ss2_o : out std_logic_vector(7 downto 0);
ss3_o : out std_logic_vector(7 downto 0));
end component;
signal s_clk50 : std_logic := '0';
signal s_reset_n : std_logic := '0';
signal s_sw_i : std_logic_vector(9 downto 0) := (others =>'0');
signal s_pb_i : std_logic_vector(1 downto 0) := (others =>'0');
signal s_ss0_o, s_ss1_o,
s_ss2_o, s_ss3_o : std_logic_vector(7 downto 0) := (others =>'0');
begin
i_dezctr : dezctr
port map (
clk50 => s_clk50,
reset_n => s_reset_n,
sw_i => s_sw_i,
pb_i => s_pb_i,
ss0_o => s_ss0_o,
ss1_o => s_ss1_o,
ss2_o => s_ss2_o,
ss3_o => s_ss3_o
);
s_clk50 <= not s_clk50 after 1 ns;
p_test : process
begin
-- Nach Rest hochzählen
s_reset_n <= '0';
wait for 100 ns;
s_reset_n <= '1';
wait for 500 ns;
-- Runterzählen
s_pb_i(1) <= '1';
wait for 100 ns;
s_pb_i(1) <= '0';
wait for 500 ns;
end process;
end sim;
|
---------------------------------------------------------------------
-- Instruction fetch
--
-- Part of the LXP32 CPU
--
-- Copyright (c) 2016 by Alex I. Kuznetsov
--
-- The first stage of the LXP32 pipeline.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lxp32_fetch is
generic(
START_ADDR: std_logic_vector(31 downto 0)
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
lli_re_o: out std_logic;
lli_adr_o: out std_logic_vector(29 downto 0);
lli_dat_i: in std_logic_vector(31 downto 0);
lli_busy_i: in std_logic;
word_o: out std_logic_vector(31 downto 0);
current_ip_o: out std_logic_vector(29 downto 0);
next_ip_o: out std_logic_vector(29 downto 0);
valid_o: out std_logic;
ready_i: in std_logic;
jump_valid_i: in std_logic;
jump_dst_i: in std_logic_vector(29 downto 0);
jump_ready_o: out std_logic
);
end entity;
architecture rtl of lxp32_fetch is
signal init: std_logic:='1';
signal init_cnt: unsigned(7 downto 0):=(others=>'0');
signal fetch_addr: std_logic_vector(29 downto 0):=START_ADDR(31 downto 2);
signal next_word: std_logic;
signal suppress_re: std_logic:='0';
signal re: std_logic;
signal requested: std_logic:='0';
signal fifo_rst: std_logic;
signal fifo_we: std_logic;
signal fifo_din: std_logic_vector(31 downto 0);
signal fifo_re: std_logic;
signal fifo_dout: std_logic_vector(31 downto 0);
signal fifo_empty: std_logic;
signal fifo_full: std_logic;
signal jr: std_logic:='0';
signal next_ip: std_logic_vector(fetch_addr'range);
signal current_ip: std_logic_vector(fetch_addr'range);
begin
-- INIT state machine (to initialize all registers)
-- All CPU registers are expected to be zero-initialized after reset.
-- Since these registers are implemented as a RAM block, we perform
-- the initialization sequentially by generating "mov rN, 0" instructions
-- for each N from 0 to 255.
--
-- With SRAM-based FPGAs, flip-flops and RAM blocks have deterministic
-- state after configuration. On these technologies the CPU can operate
-- without reset and the initialization procedure described above is not
-- needed. However, the initialization is still performed as usual when
-- external reset signal is asserted.
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
init<='0';
init_cnt<=(others=>'0');
else
if init='0' and ready_i='1' then
init_cnt<=init_cnt+1;
if init_cnt=X"FF" then
init<='1';
end if;
end if;
end if;
end if;
end process;
-- FETCH state machine
process (clk_i) is
begin
if rising_edge(clk_i) then
if rst_i='1' then
fetch_addr<=START_ADDR(31 downto 2);
requested<='0';
jr<='0';
suppress_re<='0';
next_ip<=(others=>'-');
else
jr<='0';
-- Suppress LLI request if jump signal is active but will not be processed
-- in this cycle. Helps to reduce jump latency with high-latency LLI slaves.
-- Note: gating "re" with "jump_valid_i and not jr" asynchronously would
-- reduce jump latency even more, but we really want to avoid too large
-- clock-to-out on LLI outputs.
suppress_re<=jump_valid_i and not jr and not next_word;
if lli_busy_i='0' then
requested<=re and not (jump_valid_i and not jr);
end if;
if next_word='1' then
-- It's not immediately obvious why, but current_ip and next_ip will contain
-- the addresses of the current instruction and the next instruction to be
-- fetched, respectively, by the time the instruction is passed to the decode
-- stage. Basically, this is because when either the decoder or the IBUS
-- stalls, the fetch_addr counter will also stop incrementing.
next_ip<=fetch_addr;
current_ip<=next_ip;
if jump_valid_i='1' and jr='0' then
fetch_addr<=jump_dst_i;
jr<='1';
else
fetch_addr<=std_logic_vector(unsigned(fetch_addr)+1);
end if;
end if;
end if;
end if;
end process;
next_word<=(fifo_empty or ready_i) and not lli_busy_i and init;
re<=(fifo_empty or ready_i) and init and not suppress_re;
lli_re_o<=re;
lli_adr_o<=fetch_addr;
jump_ready_o<=jr;
-- Small instruction buffer
fifo_rst<=rst_i or (jump_valid_i and not jr);
fifo_we<=requested and not lli_busy_i;
fifo_din<=lli_dat_i;
fifo_re<=ready_i and not fifo_empty;
ubuf_inst: entity work.lxp32_ubuf(rtl)
generic map(
DATA_WIDTH=>32
)
port map(
clk_i=>clk_i,
rst_i=>fifo_rst,
we_i=>fifo_we,
d_i=>fifo_din,
re_i=>fifo_re,
d_o=>fifo_dout,
empty_o=>fifo_empty,
full_o=>fifo_full
);
next_ip_o<=next_ip;
current_ip_o<=current_ip;
word_o<=fifo_dout when init='1' else X"40"&std_logic_vector(init_cnt)&X"0000";
valid_o<=not fifo_empty or not init;
-- Note: the following code contains a few simulation-only assertions
-- to check that current_ip and next_ip signals, used in procedure calls
-- and interrupts, are correct.
-- This code should be ignored by a synthesizer since it doesn't drive
-- any signals, but we also surround it by metacomments, just in case.
-- synthesis translate_off
process (clk_i) is
type Pair is record
addr: std_logic_vector(fetch_addr'range);
data: std_logic_vector(31 downto 0);
end record;
type Pairs is array (7 downto 0) of Pair;
variable buf: Pairs;
variable count: integer range buf'range:=0;
variable current_pair: Pair;
begin
if rising_edge(clk_i) then
if fifo_rst='1' then -- jump
count:=0;
elsif fifo_we='1' then -- LLI returned data
current_pair.data:=fifo_din;
buf(count):=current_pair;
count:=count+1;
end if;
if re='1' and lli_busy_i='0' then -- data requested
current_pair.addr:=fetch_addr;
end if;
if fifo_empty='0' and fifo_rst='0' then -- fetch output is valid
assert count>0
report "Fetch: buffer should be empty"
severity failure;
assert buf(0).data=fifo_dout
report "Fetch: incorrect data"
severity failure;
assert buf(0).addr=current_ip
report "Fetch: incorrect current_ip"
severity failure;
assert std_logic_vector(unsigned(buf(0).addr)+1)=next_ip
report "Fetch: incorrect next_ip"
severity failure;
if ready_i='1' then
buf(buf'high-1 downto 0):=buf(buf'high downto 1); -- we don't care about the highest item
count:=count-1;
end if;
end if;
end if;
end process;
-- synthesis translate_on
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.std_logic_arith.ALL;
entity dynamic is
port (
clk_1hz : in std_logic;
leds : out std_logic_vector(3 downto 0)
);
end dynamic;
architecture Behavioral of dynamic is
signal output : std_logic_vector(3 downto 0) := "0000";
begin
process (clk_1hz)
begin
if rising_edge(clk_1hz) then
output <= output + 1;
end if;
end process;
leds <= output;
end Behavioral;
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 28, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's Interrupt Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_int_pack.all;
--! The Interrupt Controller is developed to extend
--! the single external interrupt of the Plasma-SoC's CPU to
--! support multiple interrupts. The only goals behind the
--! development of the Interrupt Controller are simplicity and
--! having a Slave AXI4-Lite interface.
--!
--! The operation of the Interrupt Controller is as follows. Each
--! device interrupt, which are the interrupts associated with the
--! devices connecting to the Interrupt Controller, is enabled by
--! writing to the corresponding bit at the Interrupt Enables register
--! located at axi_int_enables_offset. A device can trigger its respective
--! interrupt by setting it high. At this point, the device interrupt is
--! considered active if it is both enabled in the Interrupt Enables register
--! and set high by the respective device.
--!
--! If there is at least one active device interrupt, the Interrupt Controller
--! will set the CPU interrupt, which is the single interrupt associated with the
--! CPU, high and set the Interrupt Identifier register at axi_int_id_offset
--! as the identifier (IRQ) of the active device interrupt.
--! If there are multiple active device interrupts, the lowest identifier will
--! always have priority over the Interrupt Identifier register. The CPU
--! interrupt will remain high until there are no active device interrupts.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_int is
generic(
-- Slave AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
axi_int_id_offset : integer := 4; --! Defines the offset from axi_base_address for the Interrupt Identifier register.
axi_int_enables_offset : integer := 0; --! Defines the offset from axi_base_address for the Interrupt Enables register.
axi_int_active_offset : integer := 8; --! Defines the offset from axi_base_address for the Interrupt Active register.
-- Interrupt Controller parameters.
interrupt_total : integer := 8 --! Defines the number of available device interrupts.
);
port(
-- Global Interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- CPU interface.
cpu_int : out std_logic; --! CPU interrupt.
-- Device interface.
dev_ints : in std_logic_vector(interrupt_total-1 downto 0)); --! Device interrupts.
end plasoc_int;
architecture Behavioral of plasoc_int is
component plasoc_int_cntrl is
generic (
interrupt_total : integer := 8 );
port (
clock : in std_logic;
nreset : in std_logic;
cpu_int : out std_logic := '0';
cpu_int_id : out std_logic_vector(clogb2(interrupt_total) downto 0) := (others=>'0');
cpu_int_enables : in std_logic_vector(interrupt_total-1 downto 0);
cpu_int_active : out std_logic_vector(interrupt_total-1 downto 0);
dev_ints : in std_logic_vector(interrupt_total-1 downto 0));
end component;
component plasoc_int_axi4_read_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
int_id_address : std_logic_vector := X"0004";
int_enables_address : std_logic_vector := X"0000";
int_active_address : std_logic_vector := X"0008");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
int_id : in std_logic_vector(axi_data_width-1 downto 0);
int_enables : in std_logic_vector(axi_data_width-1 downto 0);
int_active : in std_logic_vector(axi_data_width-1 downto 0));
end component;
component plasoc_int_axi4_write_cntrl is
generic (
axi_address_width : integer := 16;
axi_data_width : integer := 32;
int_enables_address : std_logic_vector := X"0000");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
int_enables : out std_logic_vector(axi_data_width-1 downto 0));
end component;
constant axi_int_id_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_int_id_offset,axi_address_width));
constant axi_int_enables_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_int_enables_offset,axi_address_width));
constant axi_int_active_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_int_active_offset,axi_address_width));
signal int_id : std_logic_vector(axi_data_width-1 downto 0);
signal int_enables : std_logic_vector(axi_data_width-1 downto 0);
signal int_active : std_logic_vector(axi_data_width-1 downto 0);
begin
int_id(axi_data_width-1 downto clogb2(interrupt_total)+1) <= (others=>'0');
int_active(axi_data_width-1 downto interrupt_total) <= (others=>'0');
plasoc_int_cntrl_inst :
plasoc_int_cntrl
generic map (
interrupt_total => interrupt_total )
port map (
clock => aclk,
nreset => aresetn,
cpu_int => cpu_int,
cpu_int_id => int_id(clogb2(interrupt_total) downto 0),
cpu_int_enables => int_enables(interrupt_total-1 downto 0),
cpu_int_active => int_active(interrupt_total-1 downto 0),
dev_ints => dev_ints);
plasoc_int_axi4_read_cntrl_inst :
plasoc_int_axi4_read_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
int_id_address => axi_int_id_offset_slv,
int_enables_address => axi_int_enables_offset_slv,
int_active_address => axi_int_active_offset_slv )
port map (
aclk => aclk,
aresetn => aresetn,
axi_araddr => axi_araddr,
axi_arprot => axi_arprot,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rdata => axi_rdata,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
axi_rresp => axi_rresp,
int_id => int_id,
int_enables => int_enables,
int_active => int_active);
plasoc_int_axi4_write_cntrl_inst :
plasoc_int_axi4_write_cntrl
generic map (
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
int_enables_address => axi_int_enables_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_awaddr => axi_awaddr,
axi_awprot => axi_awprot,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_bresp => axi_bresp,
int_enables => int_enables);
end Behavioral;
|
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlFloat : integer := 3;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant q_width : integer := quotient'length;
constant f_width : integer := fraction'length;
constant vec_MSB : integer := q_width+f_width-1;
constant result_MSB : integer := q_width+fraction_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := ( quotient & fraction );
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant inp_width : integer := inp'length;
constant vec_MSB : integer := inp_width-1;
constant result_MSB : integer := result_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := inp;
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_simulation_pkg is
type kernel_type is ( copy, max_half_atomic, bitonic, fadd, median, floydwarshall, fir_char4, add_float, parallelSelection, mat_mul, fir, xcorr, sum_atomic, fft_hard, mul_float, sobel);
-- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CONSTANT kernel_name : kernel_type := fft_hard;
-- byte(0), half word(1), word(2)
CONSTANT COMP_TYPE : natural := 2;
-- slli(0), sll(1), srli(2), srl(3), srai(4), sra(5), andi(6), and(7), ori(8), or(9), xori(10), xor(11), nor(12), sllb(13), srlb(14), srab(15)
CONSTANT LOGIC_OP : natural := 15;
CONSTANT REDUCE_FACTOR : natural := 1;
function get_kernel_index (name: in kernel_type) return integer;
end FGPU_simulation_pkg;
package body FGPU_simulation_pkg is
function get_kernel_index (name: in kernel_type) return integer is
begin
case name is
when copy =>
return 0;
when max_half_atomic =>
return 1;
when bitonic =>
return 2;
when fadd =>
return 3;
when median =>
return 4;
when floydwarshall =>
return 5;
when fir_char4 =>
return 6;
when add_float =>
return 7;
when parallelSelection =>
return 8;
when mat_mul =>
return 9;
when fir =>
return 10;
when xcorr =>
return 11;
when sum_atomic =>
return 12;
when fft_hard =>
return 13;
when mul_float =>
return 14;
when sobel =>
return 15;
when others=>
assert(false) severity failure;
return 0;
end case;
end; -- function reverse_any_vector
end FGPU_simulation_pkg;
|
-------------------------------------------------------------------------------
-- Title : u2p_nios_ddr2
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel with just the alt-mem phy. Testing and experimenting
-- with memory latency.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity u2p_nios_ddr2 is
port (
-- slot side
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : out std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : inout std_logic;
SLOT_ROMLn : inout std_logic;
SLOT_IO1n : inout std_logic;
SLOT_IO2n : inout std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DM : inout std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_nios_ddr2 is
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component nios_solo is
port (
clk_clk : in std_logic := 'X'; -- clk
-- dram_waitrequest : in std_logic := 'X'; -- waitrequest
-- dram_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
-- dram_readdatavalid : in std_logic := 'X'; -- readdatavalid
-- dram_burstcount : out std_logic_vector(0 downto 0); -- burstcount
-- dram_writedata : out std_logic_vector(31 downto 0); -- writedata
-- dram_address : out std_logic_vector(25 downto 0); -- address
-- dram_write : out std_logic; -- write
-- dram_read : out std_logic; -- read
-- dram_byteenable : out std_logic_vector(3 downto 0); -- byteenable
-- dram_debugaccess : out std_logic; -- debugaccess
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
io_u2p_ack : in std_logic := 'X'; -- ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_u2p_read : out std_logic; -- read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- wdata
io_u2p_write : out std_logic; -- write
io_u2p_address : out std_logic_vector(19 downto 0); -- address
io_u2p_irq : in std_logic := 'X'; -- irq
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_mem_req_request : out std_logic; -- mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_rack_tag
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component nios_solo;
signal por_n : std_logic;
signal por_count : unsigned(23 downto 0) := (others => '0');
signal led_n : std_logic_vector(0 to 3);
signal ref_reset : std_logic;
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_reset_n : std_logic;
signal eth_reset : std_logic;
signal button_i : std_logic_vector(2 downto 0);
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal io_u2p_req : t_io_req;
signal io_u2p_resp : t_io_resp;
signal io_req_new_io : t_io_req;
signal io_resp_new_io : t_io_resp;
signal io_req_remote : t_io_req;
signal io_resp_remote : t_io_resp;
signal io_req_ddr2 : t_io_req;
signal io_resp_ddr2 : t_io_resp;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal dram_waitrequest : std_logic := 'X'; -- waitrequest
signal dram_readdata : std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
signal dram_readdatavalid : std_logic := 'X'; -- readdatavalid
signal dram_writedata : std_logic_vector(31 downto 0); -- writedata
signal dram_address : std_logic_vector(25 downto 0); -- address
signal dram_write : std_logic; -- write
signal dram_read : std_logic; -- read
signal dram_byteenable : std_logic_vector(3 downto 0); -- byteenable
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
signal reset_request_n : std_logic := '1';
signal is_idle : std_logic;
begin
process(RMII_REFCLK, reset_request_n)
begin
if reset_request_n = '0' then
por_count <= (others => '0');
elsif rising_edge(RMII_REFCLK) then
if por_count = X"FFFFFF" then
por_n <= '1';
else
por_n <= '0';
por_count <= por_count + 1;
end if;
end if;
end process;
ref_reset <= not por_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => open );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => not sys_reset_n,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => sys_reset,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
sys_reset_n <= not sys_reset;
i_nios: nios_solo
port map (
clk_clk => sys_clock,
reset_reset_n => sys_reset_n,
-- dram_waitrequest => dram_waitrequest,
-- dram_readdata => dram_readdata,
-- dram_readdatavalid => dram_readdatavalid,
-- dram_burstcount => open,
-- dram_writedata => dram_writedata,
-- dram_address => dram_address,
-- dram_write => dram_write,
-- dram_read => dram_read,
-- dram_byteenable => dram_byteenable,
-- dram_debugaccess => open,
io_ack => io_resp.ack,
io_rdata => io_resp.data,
io_read => io_req.read,
io_wdata => io_req.data,
io_write => io_req.write,
unsigned(io_address) => io_req.address,
io_irq => '0',
io_u2p_ack => io_u2p_resp.ack,
io_u2p_rdata => io_u2p_resp.data,
io_u2p_read => io_u2p_req.read,
io_u2p_wdata => io_u2p_req.data,
io_u2p_write => io_u2p_req.write,
unsigned(io_u2p_address) => io_u2p_req.address,
io_u2p_irq => '0',
unsigned(mem_mem_req_address) => mem_req.address,
mem_mem_req_byte_en => mem_req.byte_en,
mem_mem_req_read_writen => mem_req.read_writen,
mem_mem_req_request => mem_req.request,
mem_mem_req_tag => mem_req.tag,
mem_mem_req_wdata => mem_req.data,
mem_mem_resp_dack_tag => mem_resp.dack_tag,
mem_mem_resp_data => mem_resp.data,
mem_mem_resp_rack_tag => mem_resp.rack_tag
);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 9,
g_ports => 3
)
port map (
clock => sys_clock,
req => io_u2p_req,
resp => io_u2p_resp,
reqs(0) => io_req_new_io,
reqs(1) => io_req_ddr2,
reqs(2) => io_req_remote,
resps(0) => io_resp_new_io,
resps(1) => io_resp_ddr2,
resps(2) => io_resp_remote
);
-- i_dram_bridge: entity work.avalon_to_mem32_bridge
-- port map (
-- clock => sys_clock,
-- reset => sys_reset,
--
-- avs_read => dram_read,
-- avs_write => dram_write,
-- avs_address => dram_address,
-- avs_writedata => dram_writedata,
-- avs_byteenable => dram_byteenable,
-- avs_waitrequest => dram_waitrequest,
-- avs_readdata => dram_readdata,
-- avs_readdatavalid => dram_readdatavalid,
--
-- mem_req => mem_req,
-- mem_resp => mem_resp );
i_memphy: entity work.ddr2_ctrl
port map (
ref_clock => RMII_REFCLK,
ref_reset => ref_reset,
sys_clock_o => sys_clock,
sys_reset_o => sys_reset,
clock => sys_clock,
reset => sys_reset,
io_req => io_req_ddr2,
io_resp => io_resp_ddr2,
inhibit => '0',
is_idle => is_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CLKn => SDRAM_CLKn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_ODT => SDRAM_ODT,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_A => SDRAM_A,
SDRAM_BA => SDRAM_BA(1 downto 0),
SDRAM_DM => SDRAM_DM,
SDRAM_DQ => SDRAM_DQ,
SDRAM_DQS => SDRAM_DQS
);
i_remote: entity work.update_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_remote,
io_resp => io_resp_remote,
flash_selck => FLASH_SELCK,
flash_sel => FLASH_SEL
);
i_u2p_io: entity work.u2p_io
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_new_io,
io_resp => io_resp_new_io,
mdc => MDIO_CLK,
mdio => MDIO_DATA,
i2c_scl => I2C_SCL,
i2c_sda => I2C_SDA,
speaker_en => SPEAKER_ENABLE,
hub_reset_n=> HUB_RESETn
);
ETH_RESETn <= '1';
SLOT_ADDR <= (others => 'Z');
SLOT_DATA <= (others => 'Z');
-- top
SLOT_DMAn <= 'Z';
SLOT_ROMLn <= 'Z';
SLOT_IO2n <= 'Z';
SLOT_EXROMn <= 'Z';
SLOT_GAMEn <= 'Z';
SLOT_IO1n <= 'Z';
SLOT_RWn <= 'Z';
SLOT_IRQn <= 'Z';
SLOT_NMIn <= 'Z';
SLOT_RSTn <= 'Z';
SLOT_ROMHn <= 'Z';
-- Cassette Interface
CAS_SENSE <= '0';
CAS_READ <= '0';
CAS_WRITE <= '0';
LED_MOTORn <= sys_reset;
LED_DISKn <= is_idle;
LED_CARTn <= button_i(0) xor button_i(1) xor button_i(2);
LED_SDACTn <= SLOT_BA xor SLOT_DOTCLK xor SLOT_PHI2 xor CAS_MOTOR xor SLOT_VCC;
button_i <= not BUTTON;
SLOT_BUFFER_ENn <= '1'; -- we don't connect to a C64
-- Flash Interface
FLASH_CSn <= '1';
FLASH_SCK <= '1';
FLASH_MOSI <= '1';
-- USB Interface (ULPI)
ULPI_RESET <= por_n;
ULPI_STP <= '0';
ULPI_DATA <= (others => 'Z');
end architecture;
|
-- cb20_pwm_interface_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2020.06.03.16:36:13
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_pwm_interface_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 6;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(5 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_pwm_interface_0_avalon_slave_0_translator;
architecture rtl of cb20_pwm_interface_0_avalon_slave_0_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(5 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
pwm_interface_0_avalon_slave_0_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_pwm_interface_0_avalon_slave_0_translator
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Simple SD and MMC model
--
-- $Id: card.vhd,v 1.2 2005-02-13 17:06:22 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity card is
generic (
card_type_g : string := "none";
is_sd_card_g : integer := 1
);
port (
spi_clk_i : in std_logic;
spi_cs_n_i : in std_logic;
spi_data_i : in std_logic;
spi_data_o : out std_logic
);
end card;
library ieee;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.tb_pack.all;
architecture behav of card is
signal power_on_n_s : std_logic;
signal soft_res_n_s : std_logic;
signal res_n_s : std_logic;
signal rx_s : std_logic_vector(47 downto 0);
signal set_spi_mode_s,
spi_mode_q : boolean;
signal set_idle_mode_s,
poll_idle_mode_s : boolean;
signal idle_mode_q : natural;
signal block_len_q,
block_len_s : unsigned(31 downto 0);
signal set_block_len_s : boolean;
signal new_read_addr_s,
read_addr_q : unsigned(31 downto 0);
signal set_read_addr_s,
inc_read_addr_s : boolean;
signal cmd_spi_data_s,
read_spi_data_s : std_logic;
signal start_read_s : boolean;
signal reading_s : boolean;
procedure rise_clk is
begin
wait until spi_clk_i'event and to_X01(spi_clk_i) = '1';
end rise_clk;
-- procedure rise_clk(num : natural) is
-- begin
-- for i in 1 to num loop
-- rise_clk;
-- end loop;
-- end rise_clk;
procedure fall_clk is
begin
wait until spi_clk_i'event and to_X01(spi_clk_i) = '0';
end fall_clk;
procedure fall_clk(num : natural) is
begin
for i in 1 to num loop
fall_clk;
end loop;
end fall_clk;
begin
res_n_s <= power_on_n_s and soft_res_n_s;
-----------------------------------------------------------------------------
-- Power on reset
-----------------------------------------------------------------------------
por: process
begin
power_on_n_s <= '0';
wait for 200 ns;
power_on_n_s <= '1';
wait;
end process por;
-----------------------------------------------------------------------------
--
ctrl: process
function check_crc(payload : in std_logic_vector(47 downto 0))
return boolean is
begin
return calc_crc(payload(47 downto 8)) = payload(7 downto 1);
end check_crc;
variable rx_v : std_logic_vector(47 downto 0);
variable cmd_v : std_logic_vector( 5 downto 0);
variable arg_v : std_logic_vector(31 downto 0);
variable crc_v : std_logic_vector( 6 downto 0);
variable wrong_v : std_logic;
variable read_data_v : boolean;
begin
rx_s <= (others => '0');
set_spi_mode_s <= false;
set_idle_mode_s <= false;
poll_idle_mode_s <= false;
cmd_spi_data_s <= '1';
soft_res_n_s <= '1';
set_block_len_s <= false;
block_len_s <= (others => '0');
new_read_addr_s <= (others => '0');
set_read_addr_s <= false;
start_read_s <= false;
read_data_v := false;
loop
rise_clk;
-- wait for startbit of command
while to_X01(spi_data_i) = '1' loop
rise_clk;
end loop;
rx_v(47) := '0';
-- read remaining 47 bits of command
for i in 46 downto 0 loop
rise_clk;
rx_v(i) := to_X01(spi_data_i);
end loop;
rx_s <= rx_v;
-- dissect received data
cmd_v := rx_v(45 downto 40);
arg_v := rx_v(39 downto 8);
crc_v := rx_v( 7 downto 1);
assert spi_mode_q or check_crc(payload => rx_v)
report "CRC mismatch"
severity error;
wrong_v := '0';
case cmd_v is
-- CMD0: GO_IDLE_STATE ------------------------------------------------
when "000000" =>
set_spi_mode_s <= true;
set_idle_mode_s <= true;
-- CMD1: SEND_OP_COND -------------------------------------------------
when "000001" =>
poll_idle_mode_s <= true;
-- CMD12: STOP_TRANSMISSION -------------------------------------------
when "001100" =>
start_read_s <= false;
read_data_v := false;
-- CMD16: SET_BLOCKLEN ------------------------------------------------
when "010000" =>
block_len_s <= unsigned(arg_v);
set_block_len_s <= true;
-- CMD18: READ_MULTIPLE_BLOCK -----------------------------------------
when "010010" =>
new_read_addr_s <= unsigned(arg_v);
set_read_addr_s <= true;
read_data_v := true;
-- CMD55: APPL_CMD ----------------------------------------------------
when "110111" =>
-- command only available for SD card
if is_sd_card_g /= 1 then
wrong_v := '1';
end if;
-- ACMD41: SEND_OP_COND -----------------------------------------------
when "101001" =>
-- command only available for SD card
if is_sd_card_g /= 1 then
wrong_v := '1';
else
poll_idle_mode_s <= true;
end if;
when others =>
wrong_v := '1';
null;
end case;
-- spend some time before removing control signals
fall_clk(2);
poll_idle_mode_s <= false;
set_idle_mode_s <= false;
fall_clk(6);
set_spi_mode_s <= false;
set_block_len_s <= false;
set_read_addr_s <= false;
if reading_s then
wait until not reading_s;
end if;
-- wait for a total two "bytes" before sending out response
for i in 1 to 8 loop
fall_clk;
end loop;
for i in 7 downto 0 loop
fall_clk;
case i is
when 2 =>
cmd_spi_data_s <= wrong_v;
when 0 =>
if idle_mode_q = 0 then
cmd_spi_data_s <= '0';
else
cmd_spi_data_s <= '1';
end if;
when others =>
cmd_spi_data_s <= '0';
end case;
end loop;
fall_clk;
cmd_spi_data_s <= '1';
-- transmit data if requested
start_read_s <= read_data_v;
end loop;
end process ctrl;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--
seq: process (res_n_s,
spi_clk_i,
set_spi_mode_s,
set_idle_mode_s,
poll_idle_mode_s,
set_block_len_s,
block_len_s)
begin
if res_n_s = '0' then
spi_mode_q <= false;
idle_mode_q <= 5;
block_len_q <= (others => '0');
read_addr_q <= (others => '0');
elsif spi_clk_i'event and spi_clk_i = '1' then
if set_spi_mode_s then
spi_mode_q <= true;
end if;
if set_idle_mode_s then
idle_mode_q <= 5;
elsif poll_idle_mode_s then
if idle_mode_q > 0 then
idle_mode_q <= idle_mode_q - 1;
end if;
end if;
if set_block_len_s then
block_len_q <= block_len_s;
end if;
if set_read_addr_s then
read_addr_q <= new_read_addr_s;
elsif inc_read_addr_s then
read_addr_q <= read_addr_q + 1;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--
read_block: process
variable t_v : unsigned(7 downto 0);
begin
-- default assignments
inc_read_addr_s <= false;
reading_s <= false;
read_spi_data_s <= '1';
loop
if not start_read_s then
wait until start_read_s;
end if;
reading_s <= true;
fall_clk(8); -- delay for one "byte"
-- send data token
fall_clk(7); -- 7 ones in a data token
read_spi_data_s <= '0';
-- send payload
payload: for i in 0 to to_integer(block_len_q)-1 loop
t_v := read_addr_q(0) & calc_crc(read_addr_q);
for bit in 7 downto 0 loop
fall_clk;
read_spi_data_s <= t_v(bit);
exit payload when not start_read_s;
end loop;
inc_read_addr_s <= true;
rise_clk;
inc_read_addr_s <= false;
wait for 10 ns;
end loop;
if start_read_s then
-- send crc
for i in 0 to 15 loop
fall_clk;
t_v := to_unsigned(i, 8);
read_spi_data_s <= t_v(0);
end loop;
fall_clk;
end if;
read_spi_data_s <= '1';
reading_s <= false;
-- loop for one "byte"
fall_clk(8);
end loop;
end process read_block;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--
clk_check: process (spi_clk_i)
variable last_rising_v : time := 0 ns;
variable dump_line : line;
begin
if spi_clk_i'event and spi_clk_i = '1' then
if is_sd_card_g = 0 and card_type_g /= "Minimal Chip" and
idle_mode_q > 0 then
if now - last_rising_v < 2.5 us and last_rising_v > 0 ns then
write(dump_line, card_type_g);
write(dump_line, string'(" @ "));
write(dump_line, now);
write(dump_line, string'(": Last rising edge of SPI clock "));
write(dump_line, now - last_rising_v);
write(dump_line, string'(" ago."));
writeline(output, dump_line);
end if;
last_rising_v := now;
end if;
end if;
end process clk_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
spi_data_o <= cmd_spi_data_s and read_spi_data_s
when spi_cs_n_i = '0' else
'Z';
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1 2005/02/08 21:09:20 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Control Circuit (FSM)
ENTITY control_circuit IS
PORT (
clock, reset : IN STD_LOGIC;
func : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
done, A_in, G_in, G_out, extern, R0_in, R1_in : OUT STD_LOGIC := '0';
R0_out, R1_out, R0_xor, R1_xor, PC_in, PC_out : OUT STD_LOGIC := '0';
c_state : OUT INTEGER
);
END;
ARCHITECTURE behavioural OF control_circuit IS
COMPONENT find_ns IS
PORT (
state : IN INTEGER;
reset : IN STD_LOGIC;
instr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rx, ry : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ns : OUT INTEGER
);
END COMPONENT;
SIGNAL c_state_temp : INTEGER := 255;
SIGNAL n_state : INTEGER := 0;
BEGIN
instance1 : find_ns
PORT MAP(
reset => reset,
state => c_state_temp,
instr => func(15 DOWNTO 12),
rx => func(11 DOWNTO 8),
ry => func(7 DOWNTO 4),
ns => n_state
);
PROCESS (c_state_temp, func)
BEGIN
done <= '0';
R0_in <= '0';
R0_in <= '0';
R0_out <= '0';
R0_xor <= '0';
R1_in <= '0';
R1_out <= '0';
R1_xor <= '0';
PC_in <= '0';
PC_out <= '0';
A_in <= '0';
G_in <= '0';
G_out <= '0';
extern <= '0';
CASE c_state_temp IS
-- START state
WHEN 255 =>
done <= '1';
-- IDLE State
WHEN 0 =>
-- Wait for next instruction
-- LOAD States
WHEN 10 =>
done <= '1';
WHEN 11 =>
--Rx = R0
extern <= '1';
R0_in <= '1';
WHEN 12 =>
-- Rx = R1
extern <= '1';
R1_in <= '1';
WHEN 13 =>
extern <= '1';
done <= '1';
WHEN 14 =>
done <= '1';
-- MOV States
WHEN 20 =>
-- Rx = R0
R0_in <= '1';
R1_out <= '1';
WHEN 21 =>
-- Rx = R1
R1_in <= '1';
R0_out <= '1';
WHEN 22 =>
done <= '1';
-- ADD States
WHEN 30 =>
R0_out <= '1';
A_in <= '1';
WHEN 31 =>
R1_out <= '1';
G_in <= '1';
WHEN 32 =>
-- Rx = R0
G_out <= '1';
R0_in <= '1';
WHEN 33 =>
-- Rx = R1
G_out <= '1';
R1_in <= '1';
WHEN 34 =>
done <= '1';
-- XOR States
WHEN 40 =>
--Rx = R0
R1_out <= '1';
R0_xor <= '1';
WHEN 41 =>
--Rx = R1
R0_out <= '1';
R1_xor <= '1';
WHEN 42 =>
done <= '1';
-- LDPC, Load PC to Rx
WHEN 50 =>
--Rx = R0
R0_in <= '1';
PC_out <= '1';
WHEN 51 =>
--Rx = R1
R1_in <= '1';
PC_out <= '1';
WHEN 52 =>
done <= '1';
-- BRANCH, Load Rx to PC
WHEN 60 =>
--Rx = R0
PC_in <= '1';
R0_out <= '1';
WHEN 61 =>
--Rx = R1
PC_in <= '1';
R1_out <= '1';
WHEN 62 =>
R1_out <= '1';
done <= '1';
--Double Ry, store in Rx
WHEN 701 =>
--Rx = R0, Ry = R0
R0_out <= '1';
A_in <= '1';
WHEN 702 =>
R0_out <= '1';
G_in <= '1';
WHEN 703 =>
G_out <= '1';
R0_in <= '1';
WHEN 711 =>
--Rx = R1, Ry = R0
R0_out <= '1';
A_in <= '1';
G_in <= '1';
WHEN 712 =>
R0_out <= '1';
G_in <= '1';
WHEN 713 =>
G_out <= '1';
R1_in <= '1';
WHEN 721 =>
--Rx = R0, Ry = R1
R1_out <= '1';
A_in <= '1';
G_in <= '1';
WHEN 722 =>
R1_out <= '1';
G_in <= '1';
WHEN 723 =>
G_out <= '1';
R0_in <= '1';
WHEN 731 =>
--Rx = R1, Ry = R1
R1_out <= '1';
A_in <= '1';
G_in <= '1';
WHEN 732 =>
R1_out <= '1';
G_in <= '1';
WHEN 733 =>
G_out <= '1';
R1_in <= '1';
WHEN 740 =>
done <= '1';
WHEN OTHERS =>
-- Return to IDLE
END CASE;
END PROCESS;
PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
c_state_temp <= n_state;
END IF;
END PROCESS;
c_state <= c_state_temp;
END behavioural; |
-- $Id: tb_cdata2byte.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2014- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_cdata2byte - sim
-- Description: Test bench for cdata2byte and byte2cdata
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_cdata2byte [UUT]
--
-- To test: cdata2byte
-- byte2cdata
--
-- Target Devices: generic
--
-- Verified (with tb_cdata2byte_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2014-10-25 599 _ssim 0.31 17.1 sc6slx16 c: ok
-- 2014-10-25 599 - 0.31 - c: ok
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-10-25 599 1.1.1 use wait_* to control stim and moni timing
-- 2014-10-19 598 1.1 use simfifo with shared variables
-- 2014-10-18 597 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.comlib.all;
entity tb_cdata2byte is
end tb_cdata2byte;
architecture sim of tb_cdata2byte is
constant clk_dsc : clock_dsc := (20 ns, 1 ns, 1 ns);
constant clk_offset : Delay_length := 200 ns;
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal C2B_ESCXON : slbit := '0';
signal C2B_ESCFILL : slbit := '0';
signal C2B_DI : slv9 := (others=>'0');
signal C2B_ENA : slbit := '0';
signal C2B_BUSY : slbit := '0';
signal C2B_DO : slv8 := (others=>'0');
signal C2B_VAL : slbit := '0';
signal B2C_BUSY : slbit := '0';
signal B2C_DO : slv9 := (others=>'0');
signal B2C_VAL : slbit := '0';
signal B2C_HOLD : slbit := '0';
shared variable sv_sff_monc_cnt : natural := 0;
shared variable sv_sff_monc_arr : simfifo_type(0 to 7, 7 downto 0);
shared variable sv_sff_monb_cnt : natural := 0;
shared variable sv_sff_monb_arr : simfifo_type(0 to 7, 8 downto 0);
begin
CLKGEN : simclk
generic map (
PERIOD => clk_dsc.period,
OFFSET => clk_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_cdata2byte
port map (
CLK => CLK,
RESET => RESET,
C2B_ESCXON => C2B_ESCXON,
C2B_ESCFILL => C2B_ESCFILL,
C2B_DI => C2B_DI,
C2B_ENA => C2B_ENA,
C2B_BUSY => C2B_BUSY,
C2B_DO => C2B_DO,
C2B_VAL => C2B_VAL,
B2C_BUSY => B2C_BUSY,
B2C_DO => B2C_DO,
B2C_VAL => B2C_VAL,
B2C_HOLD => B2C_HOLD
);
proc_stim: process
file fstim : text open read_mode is "tb_cdata2byte_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idel : natural := 0;
variable ilen : natural := 0;
variable nbusy : integer := 0;
variable iesc : slbit := '0';
variable itxdata9 : slbit := '0';
variable itxdata : slv8 := (others=>'0');
variable irxdata9 : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable dat9 : slv9 := (others=>'0');
begin
wait_nextstim(CLK, clk_dsc);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait_nextstim(CLK, clk_dsc);
RESET <= '0';
wait_nextstim(CLK, clk_dsc);
when ".wait " => -- .wait
read_ea(iline, idel);
wait_nextstim(CLK, clk_dsc, idel);
when "escxon" => -- escxon
read_ea(iline, iesc);
C2B_ESCXON <= iesc;
when "escfil" => -- escfil
read_ea(iline, iesc);
C2B_ESCFILL <= iesc;
when "bhold " => -- bhold
read_ea(iline, idel);
read_ea(iline, ilen);
B2C_HOLD <= '1' after idel*clk_dsc.period,
'0' after (idel+ilen)*clk_dsc.period;
when "data " => -- data
read_ea(iline, itxdata9);
readgen_ea(iline, itxdata);
read_ea(iline, irxdata9);
if irxdata9 = '0' then
simfifo_put(sv_sff_monc_cnt, sv_sff_monc_arr, itxdata);
else
readgen_ea(iline, irxdata);
simfifo_put(sv_sff_monc_cnt, sv_sff_monc_arr, c_cdata_escape);
simfifo_put(sv_sff_monc_cnt, sv_sff_monc_arr, irxdata);
end if;
dat9 := itxdata9 & itxdata;
simfifo_put(sv_sff_monb_cnt, sv_sff_monb_arr, dat9);
C2B_DI <= dat9;
C2B_ENA <= '1';
wait_stim2moni(CLK, clk_dsc);
wait_untilsignal(CLK, clk_dsc, C2B_BUSY, '0', nbusy);
writetimestamp(oline, CLK_CYCLE, ": stim ");
write(oline, itxdata9, right, 2);
write(oline, itxdata, right, 9);
writeoptint(oline, " nbusy=", nbusy);
writeline(output, oline);
wait_nextstim(CLK, clk_dsc);
C2B_ENA <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait_nextstim(CLK, clk_dsc, 12);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_monc: process
variable oline : line;
variable nhold : integer := 0;
begin
loop
wait_nextmoni(CLK, clk_dsc);
if C2B_VAL = '1' then
if B2C_BUSY = '1' then -- c2b_hold = b2c_busy !
nhold := nhold + 1;
else
writetimestamp(oline, CLK_CYCLE, ": monc ");
write(oline, string'(" "));
write(oline, C2B_DO, right, 9);
writeoptint(oline, " nhold=", nhold);
simfifo_writetest(oline, sv_sff_monc_cnt, sv_sff_monc_arr, C2B_DO);
writeline(output, oline);
nhold := 0;
end if;
end if;
end loop;
end process proc_monc;
proc_monb: process
variable oline : line;
variable nhold : integer := 0;
begin
loop
wait_nextmoni(CLK, clk_dsc);
if B2C_VAL = '1' then
if B2C_HOLD = '1' then
nhold := nhold + 1;
else
writetimestamp(oline, CLK_CYCLE, ": monb ");
write(oline, B2C_DO(8), right, 2);
write(oline, B2C_DO(7 downto 0), right, 9);
writeoptint(oline, " nhold=", nhold);
simfifo_writetest(oline, sv_sff_monb_cnt, sv_sff_monb_arr, B2C_DO);
writeline(output, oline);
nhold := 0;
end if;
end if;
end loop;
end process proc_monb;
end sim;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity CalcBuckParams is
generic ( Vin : voltage range 1.0 to 50.0 := 42.0; -- input voltage [volts]
Vout : voltage := 4.8; -- output voltage [volts]
Vd : voltage := 0.7; -- diode voltage [volts]
Imin : current := 15.0e-3; -- min output current [amps]
Vripple : voltage range 1.0e-6 to 100.0
:= 100.0e-3 ); -- output voltage ripple [volts]
port ( quantity Fsw : in real range 1.0 to 1.0e6
:= 2.0; -- switching frequency [Hz]
quantity Lmin : out inductance; -- minimum inductance [henries]
quantity Cmin : out capacitance ); -- minimum capacitance [farads]
end entity CalcBuckParams;
----------------------------------------------------------------
architecture behavioral of CalcBuckParams is
constant D : real := (Vout + Vd) / Vin; -- duty cycle
quantity Ts : real; -- period
quantity Ton : real; -- on time
begin
Ts == 1.0 / Fsw;
Ton == D * Ts;
Lmin == (Vin - Vout) * Ton / (2.0 * Imin);
Cmin == (2.0 * Imin) / (8.0 * Fsw * Vripple);
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity CalcBuckParams is
generic ( Vin : voltage range 1.0 to 50.0 := 42.0; -- input voltage [volts]
Vout : voltage := 4.8; -- output voltage [volts]
Vd : voltage := 0.7; -- diode voltage [volts]
Imin : current := 15.0e-3; -- min output current [amps]
Vripple : voltage range 1.0e-6 to 100.0
:= 100.0e-3 ); -- output voltage ripple [volts]
port ( quantity Fsw : in real range 1.0 to 1.0e6
:= 2.0; -- switching frequency [Hz]
quantity Lmin : out inductance; -- minimum inductance [henries]
quantity Cmin : out capacitance ); -- minimum capacitance [farads]
end entity CalcBuckParams;
----------------------------------------------------------------
architecture behavioral of CalcBuckParams is
constant D : real := (Vout + Vd) / Vin; -- duty cycle
quantity Ts : real; -- period
quantity Ton : real; -- on time
begin
Ts == 1.0 / Fsw;
Ton == D * Ts;
Lmin == (Vin - Vout) * Ton / (2.0 * Imin);
Cmin == (2.0 * Imin) / (8.0 * Fsw * Vripple);
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity CalcBuckParams is
generic ( Vin : voltage range 1.0 to 50.0 := 42.0; -- input voltage [volts]
Vout : voltage := 4.8; -- output voltage [volts]
Vd : voltage := 0.7; -- diode voltage [volts]
Imin : current := 15.0e-3; -- min output current [amps]
Vripple : voltage range 1.0e-6 to 100.0
:= 100.0e-3 ); -- output voltage ripple [volts]
port ( quantity Fsw : in real range 1.0 to 1.0e6
:= 2.0; -- switching frequency [Hz]
quantity Lmin : out inductance; -- minimum inductance [henries]
quantity Cmin : out capacitance ); -- minimum capacitance [farads]
end entity CalcBuckParams;
----------------------------------------------------------------
architecture behavioral of CalcBuckParams is
constant D : real := (Vout + Vd) / Vin; -- duty cycle
quantity Ts : real; -- period
quantity Ton : real; -- on time
begin
Ts == 1.0 / Fsw;
Ton == D * Ts;
Lmin == (Vin - Vout) * Ton / (2.0 * Imin);
Cmin == (2.0 * Imin) / (8.0 * Fsw * Vripple);
end architecture behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity RomSmelk3006 is
port (
clk : in std_logic;
addr : in std_logic_vector(13 downto 0);
data : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of RomSmelk3006 is
signal rom_addr : std_logic_vector(13 downto 0);
begin
p_addr : process(addr)
begin
rom_addr <= (others => '0');
rom_addr(13 downto 0) <= addr;
end process;
p_rom : process
begin
wait until rising_edge(clk);
data <= (others => '0');
case rom_addr is
when "00" & x"000" => data <= x"00";
when "00" & x"001" => data <= x"00";
when "00" & x"002" => data <= x"00";
when "00" & x"003" => data <= x"4c";
when "00" & x"004" => data <= x"55";
when "00" & x"005" => data <= x"94";
when "00" & x"006" => data <= x"82";
when "00" & x"007" => data <= x"11";
when "00" & x"008" => data <= x"5a";
when "00" & x"009" => data <= x"53";
when "00" & x"00a" => data <= x"50";
when "00" & x"00b" => data <= x"49";
when "00" & x"00c" => data <= x"00";
when "00" & x"00d" => data <= x"30";
when "00" & x"00e" => data <= x"2e";
when "00" & x"00f" => data <= x"39";
when "00" & x"010" => data <= x"30";
when "00" & x"011" => data <= x"00";
when "00" & x"012" => data <= x"28";
when "00" & x"013" => data <= x"43";
when "00" & x"014" => data <= x"29";
when "00" & x"015" => data <= x"6c";
when "00" & x"016" => data <= x"1e";
when "00" & x"017" => data <= x"02";
when "00" & x"018" => data <= x"20";
when "00" & x"019" => data <= x"5b";
when "00" & x"01a" => data <= x"80";
when "00" & x"01b" => data <= x"44";
when "00" & x"01c" => data <= x"69";
when "00" & x"01d" => data <= x"73";
when "00" & x"01e" => data <= x"6b";
when "00" & x"01f" => data <= x"20";
when "00" & x"020" => data <= x"90";
when "00" & x"021" => data <= x"11";
when "00" & x"022" => data <= x"20";
when "00" & x"023" => data <= x"5b";
when "00" & x"024" => data <= x"80";
when "00" & x"025" => data <= x"42";
when "00" & x"026" => data <= x"61";
when "00" & x"027" => data <= x"64";
when "00" & x"028" => data <= x"20";
when "00" & x"029" => data <= x"90";
when "00" & x"02a" => data <= x"08";
when "00" & x"02b" => data <= x"20";
when "00" & x"02c" => data <= x"5b";
when "00" & x"02d" => data <= x"80";
when "00" & x"02e" => data <= x"46";
when "00" & x"02f" => data <= x"69";
when "00" & x"030" => data <= x"6c";
when "00" & x"031" => data <= x"65";
when "00" & x"032" => data <= x"20";
when "00" & x"033" => data <= x"85";
when "00" & x"034" => data <= x"b3";
when "00" & x"035" => data <= x"68";
when "00" & x"036" => data <= x"85";
when "00" & x"037" => data <= x"ae";
when "00" & x"038" => data <= x"68";
when "00" & x"039" => data <= x"85";
when "00" & x"03a" => data <= x"af";
when "00" & x"03b" => data <= x"a5";
when "00" & x"03c" => data <= x"b3";
when "00" & x"03d" => data <= x"48";
when "00" & x"03e" => data <= x"98";
when "00" & x"03f" => data <= x"48";
when "00" & x"040" => data <= x"a0";
when "00" & x"041" => data <= x"00";
when "00" & x"042" => data <= x"20";
when "00" & x"043" => data <= x"da";
when "00" & x"044" => data <= x"83";
when "00" & x"045" => data <= x"b1";
when "00" & x"046" => data <= x"ae";
when "00" & x"047" => data <= x"8d";
when "00" & x"048" => data <= x"01";
when "00" & x"049" => data <= x"01";
when "00" & x"04a" => data <= x"2c";
when "00" & x"04b" => data <= x"de";
when "00" & x"04c" => data <= x"10";
when "00" & x"04d" => data <= x"10";
when "00" & x"04e" => data <= x"25";
when "00" & x"04f" => data <= x"a9";
when "00" & x"050" => data <= x"02";
when "00" & x"051" => data <= x"8d";
when "00" & x"052" => data <= x"de";
when "00" & x"053" => data <= x"10";
when "00" & x"054" => data <= x"a9";
when "00" & x"055" => data <= x"00";
when "00" & x"056" => data <= x"8d";
when "00" & x"057" => data <= x"00";
when "00" & x"058" => data <= x"01";
when "00" & x"059" => data <= x"f0";
when "00" & x"05a" => data <= x"19";
when "00" & x"05b" => data <= x"a9";
when "00" & x"05c" => data <= x"02";
when "00" & x"05d" => data <= x"8d";
when "00" & x"05e" => data <= x"de";
when "00" & x"05f" => data <= x"10";
when "00" & x"060" => data <= x"a9";
when "00" & x"061" => data <= x"00";
when "00" & x"062" => data <= x"8d";
when "00" & x"063" => data <= x"00";
when "00" & x"064" => data <= x"01";
when "00" & x"065" => data <= x"85";
when "00" & x"066" => data <= x"b3";
when "00" & x"067" => data <= x"68";
when "00" & x"068" => data <= x"85";
when "00" & x"069" => data <= x"ae";
when "00" & x"06a" => data <= x"68";
when "00" & x"06b" => data <= x"85";
when "00" & x"06c" => data <= x"af";
when "00" & x"06d" => data <= x"a5";
when "00" & x"06e" => data <= x"b3";
when "00" & x"06f" => data <= x"48";
when "00" & x"070" => data <= x"98";
when "00" & x"071" => data <= x"48";
when "00" & x"072" => data <= x"a0";
when "00" & x"073" => data <= x"00";
when "00" & x"074" => data <= x"20";
when "00" & x"075" => data <= x"da";
when "00" & x"076" => data <= x"83";
when "00" & x"077" => data <= x"b1";
when "00" & x"078" => data <= x"ae";
when "00" & x"079" => data <= x"30";
when "00" & x"07a" => data <= x"08";
when "00" & x"07b" => data <= x"f0";
when "00" & x"07c" => data <= x"0d";
when "00" & x"07d" => data <= x"20";
when "00" & x"07e" => data <= x"9c";
when "00" & x"07f" => data <= x"80";
when "00" & x"080" => data <= x"4c";
when "00" & x"081" => data <= x"74";
when "00" & x"082" => data <= x"80";
when "00" & x"083" => data <= x"68";
when "00" & x"084" => data <= x"a8";
when "00" & x"085" => data <= x"68";
when "00" & x"086" => data <= x"18";
when "00" & x"087" => data <= x"6c";
when "00" & x"088" => data <= x"ae";
when "00" & x"089" => data <= x"00";
when "00" & x"08a" => data <= x"a9";
when "00" & x"08b" => data <= x"00";
when "00" & x"08c" => data <= x"ae";
when "00" & x"08d" => data <= x"de";
when "00" & x"08e" => data <= x"10";
when "00" & x"08f" => data <= x"9d";
when "00" & x"090" => data <= x"00";
when "00" & x"091" => data <= x"01";
when "00" & x"092" => data <= x"a9";
when "00" & x"093" => data <= x"ff";
when "00" & x"094" => data <= x"8d";
when "00" & x"095" => data <= x"de";
when "00" & x"096" => data <= x"10";
when "00" & x"097" => data <= x"4c";
when "00" & x"098" => data <= x"00";
when "00" & x"099" => data <= x"01";
when "00" & x"09a" => data <= x"a9";
when "00" & x"09b" => data <= x"2e";
when "00" & x"09c" => data <= x"20";
when "00" & x"09d" => data <= x"e1";
when "00" & x"09e" => data <= x"83";
when "00" & x"09f" => data <= x"2c";
when "00" & x"0a0" => data <= x"de";
when "00" & x"0a1" => data <= x"10";
when "00" & x"0a2" => data <= x"10";
when "00" & x"0a3" => data <= x"14";
when "00" & x"0a4" => data <= x"48";
when "00" & x"0a5" => data <= x"20";
when "00" & x"0a6" => data <= x"1c";
when "00" & x"0a7" => data <= x"99";
when "00" & x"0a8" => data <= x"8a";
when "00" & x"0a9" => data <= x"48";
when "00" & x"0aa" => data <= x"09";
when "00" & x"0ab" => data <= x"10";
when "00" & x"0ac" => data <= x"20";
when "00" & x"0ad" => data <= x"17";
when "00" & x"0ae" => data <= x"99";
when "00" & x"0af" => data <= x"68";
when "00" & x"0b0" => data <= x"aa";
when "00" & x"0b1" => data <= x"68";
when "00" & x"0b2" => data <= x"20";
when "00" & x"0b3" => data <= x"e3";
when "00" & x"0b4" => data <= x"ff";
when "00" & x"0b5" => data <= x"4c";
when "00" & x"0b6" => data <= x"18";
when "00" & x"0b7" => data <= x"99";
when "00" & x"0b8" => data <= x"ae";
when "00" & x"0b9" => data <= x"de";
when "00" & x"0ba" => data <= x"10";
when "00" & x"0bb" => data <= x"9d";
when "00" & x"0bc" => data <= x"00";
when "00" & x"0bd" => data <= x"01";
when "00" & x"0be" => data <= x"ee";
when "00" & x"0bf" => data <= x"de";
when "00" & x"0c0" => data <= x"10";
when "00" & x"0c1" => data <= x"60";
when "00" & x"0c2" => data <= x"48";
when "00" & x"0c3" => data <= x"20";
when "00" & x"0c4" => data <= x"05";
when "00" & x"0c5" => data <= x"82";
when "00" & x"0c6" => data <= x"20";
when "00" & x"0c7" => data <= x"ca";
when "00" & x"0c8" => data <= x"80";
when "00" & x"0c9" => data <= x"68";
when "00" & x"0ca" => data <= x"48";
when "00" & x"0cb" => data <= x"29";
when "00" & x"0cc" => data <= x"0f";
when "00" & x"0cd" => data <= x"c9";
when "00" & x"0ce" => data <= x"0a";
when "00" & x"0cf" => data <= x"90";
when "00" & x"0d0" => data <= x"02";
when "00" & x"0d1" => data <= x"69";
when "00" & x"0d2" => data <= x"06";
when "00" & x"0d3" => data <= x"69";
when "00" & x"0d4" => data <= x"30";
when "00" & x"0d5" => data <= x"20";
when "00" & x"0d6" => data <= x"9c";
when "00" & x"0d7" => data <= x"80";
when "00" & x"0d8" => data <= x"68";
when "00" & x"0d9" => data <= x"60";
when "00" & x"0da" => data <= x"20";
when "00" & x"0db" => data <= x"ea";
when "00" & x"0dc" => data <= x"80";
when "00" & x"0dd" => data <= x"ca";
when "00" & x"0de" => data <= x"ca";
when "00" & x"0df" => data <= x"20";
when "00" & x"0e0" => data <= x"e2";
when "00" & x"0e1" => data <= x"80";
when "00" & x"0e2" => data <= x"b1";
when "00" & x"0e3" => data <= x"b0";
when "00" & x"0e4" => data <= x"9d";
when "00" & x"0e5" => data <= x"72";
when "00" & x"0e6" => data <= x"10";
when "00" & x"0e7" => data <= x"e8";
when "00" & x"0e8" => data <= x"c8";
when "00" & x"0e9" => data <= x"60";
when "00" & x"0ea" => data <= x"20";
when "00" & x"0eb" => data <= x"ed";
when "00" & x"0ec" => data <= x"80";
when "00" & x"0ed" => data <= x"b1";
when "00" & x"0ee" => data <= x"b0";
when "00" & x"0ef" => data <= x"95";
when "00" & x"0f0" => data <= x"bc";
when "00" & x"0f1" => data <= x"e8";
when "00" & x"0f2" => data <= x"c8";
when "00" & x"0f3" => data <= x"60";
when "00" & x"0f4" => data <= x"a9";
when "00" & x"0f5" => data <= x"20";
when "00" & x"0f6" => data <= x"a2";
when "00" & x"0f7" => data <= x"06";
when "00" & x"0f8" => data <= x"95";
when "00" & x"0f9" => data <= x"c7";
when "00" & x"0fa" => data <= x"ca";
when "00" & x"0fb" => data <= x"10";
when "00" & x"0fc" => data <= x"fb";
when "00" & x"0fd" => data <= x"60";
when "00" & x"0fe" => data <= x"20";
when "00" & x"0ff" => data <= x"4d";
when "00" & x"100" => data <= x"83";
when "00" & x"101" => data <= x"20";
when "00" & x"102" => data <= x"f4";
when "00" & x"103" => data <= x"80";
when "00" & x"104" => data <= x"30";
when "00" & x"105" => data <= x"13";
when "00" & x"106" => data <= x"20";
when "00" & x"107" => data <= x"4d";
when "00" & x"108" => data <= x"83";
when "00" & x"109" => data <= x"20";
when "00" & x"10a" => data <= x"f4";
when "00" & x"10b" => data <= x"80";
when "00" & x"10c" => data <= x"a5";
when "00" & x"10d" => data <= x"bc";
when "00" & x"10e" => data <= x"85";
when "00" & x"10f" => data <= x"f2";
when "00" & x"110" => data <= x"a5";
when "00" & x"111" => data <= x"bd";
when "00" & x"112" => data <= x"85";
when "00" & x"113" => data <= x"f3";
when "00" & x"114" => data <= x"a0";
when "00" & x"115" => data <= x"00";
when "00" & x"116" => data <= x"20";
when "00" & x"117" => data <= x"bf";
when "00" & x"118" => data <= x"86";
when "00" & x"119" => data <= x"a2";
when "00" & x"11a" => data <= x"01";
when "00" & x"11b" => data <= x"20";
when "00" & x"11c" => data <= x"c5";
when "00" & x"11d" => data <= x"ff";
when "00" & x"11e" => data <= x"b0";
when "00" & x"11f" => data <= x"dd";
when "00" & x"120" => data <= x"85";
when "00" & x"121" => data <= x"c7";
when "00" & x"122" => data <= x"c9";
when "00" & x"123" => data <= x"2e";
when "00" & x"124" => data <= x"d0";
when "00" & x"125" => data <= x"04";
when "00" & x"126" => data <= x"a9";
when "00" & x"127" => data <= x"20";
when "00" & x"128" => data <= x"d0";
when "00" & x"129" => data <= x"4d";
when "00" & x"12a" => data <= x"c9";
when "00" & x"12b" => data <= x"3a";
when "00" & x"12c" => data <= x"d0";
when "00" & x"12d" => data <= x"21";
when "00" & x"12e" => data <= x"20";
when "00" & x"12f" => data <= x"c5";
when "00" & x"130" => data <= x"ff";
when "00" & x"131" => data <= x"b0";
when "00" & x"132" => data <= x"15";
when "00" & x"133" => data <= x"38";
when "00" & x"134" => data <= x"e9";
when "00" & x"135" => data <= x"30";
when "00" & x"136" => data <= x"90";
when "00" & x"137" => data <= x"10";
when "00" & x"138" => data <= x"c9";
when "00" & x"139" => data <= x"04";
when "00" & x"13a" => data <= x"b0";
when "00" & x"13b" => data <= x"0c";
when "00" & x"13c" => data <= x"20";
when "00" & x"13d" => data <= x"7e";
when "00" & x"13e" => data <= x"87";
when "00" & x"13f" => data <= x"20";
when "00" & x"140" => data <= x"c5";
when "00" & x"141" => data <= x"ff";
when "00" & x"142" => data <= x"b0";
when "00" & x"143" => data <= x"5c";
when "00" & x"144" => data <= x"c9";
when "00" & x"145" => data <= x"2e";
when "00" & x"146" => data <= x"f0";
when "00" & x"147" => data <= x"03";
when "00" & x"148" => data <= x"4c";
when "00" & x"149" => data <= x"74";
when "00" & x"14a" => data <= x"83";
when "00" & x"14b" => data <= x"a9";
when "00" & x"14c" => data <= x"24";
when "00" & x"14d" => data <= x"d0";
when "00" & x"14e" => data <= x"28";
when "00" & x"14f" => data <= x"c9";
when "00" & x"150" => data <= x"2a";
when "00" & x"151" => data <= x"d0";
when "00" & x"152" => data <= x"19";
when "00" & x"153" => data <= x"20";
when "00" & x"154" => data <= x"c5";
when "00" & x"155" => data <= x"ff";
when "00" & x"156" => data <= x"b0";
when "00" & x"157" => data <= x"08";
when "00" & x"158" => data <= x"c9";
when "00" & x"159" => data <= x"2e";
when "00" & x"15a" => data <= x"d0";
when "00" & x"15b" => data <= x"32";
when "00" & x"15c" => data <= x"a9";
when "00" & x"15d" => data <= x"23";
when "00" & x"15e" => data <= x"d0";
when "00" & x"15f" => data <= x"17";
when "00" & x"160" => data <= x"a2";
when "00" & x"161" => data <= x"00";
when "00" & x"162" => data <= x"a9";
when "00" & x"163" => data <= x"23";
when "00" & x"164" => data <= x"95";
when "00" & x"165" => data <= x"c7";
when "00" & x"166" => data <= x"e8";
when "00" & x"167" => data <= x"e0";
when "00" & x"168" => data <= x"07";
when "00" & x"169" => data <= x"d0";
when "00" & x"16a" => data <= x"f9";
when "00" & x"16b" => data <= x"60";
when "00" & x"16c" => data <= x"20";
when "00" & x"16d" => data <= x"c5";
when "00" & x"16e" => data <= x"ff";
when "00" & x"16f" => data <= x"b0";
when "00" & x"170" => data <= x"2f";
when "00" & x"171" => data <= x"c9";
when "00" & x"172" => data <= x"2e";
when "00" & x"173" => data <= x"d0";
when "00" & x"174" => data <= x"10";
when "00" & x"175" => data <= x"a5";
when "00" & x"176" => data <= x"c7";
when "00" & x"177" => data <= x"85";
when "00" & x"178" => data <= x"ce";
when "00" & x"179" => data <= x"4c";
when "00" & x"17a" => data <= x"1b";
when "00" & x"17b" => data <= x"81";
when "00" & x"17c" => data <= x"20";
when "00" & x"17d" => data <= x"c5";
when "00" & x"17e" => data <= x"ff";
when "00" & x"17f" => data <= x"b0";
when "00" & x"180" => data <= x"1f";
when "00" & x"181" => data <= x"e0";
when "00" & x"182" => data <= x"07";
when "00" & x"183" => data <= x"f0";
when "00" & x"184" => data <= x"09";
when "00" & x"185" => data <= x"c9";
when "00" & x"186" => data <= x"2a";
when "00" & x"187" => data <= x"d0";
when "00" & x"188" => data <= x"12";
when "00" & x"189" => data <= x"20";
when "00" & x"18a" => data <= x"c5";
when "00" & x"18b" => data <= x"ff";
when "00" & x"18c" => data <= x"b0";
when "00" & x"18d" => data <= x"d4";
when "00" & x"18e" => data <= x"20";
when "00" & x"18f" => data <= x"22";
when "00" & x"190" => data <= x"80";
when "00" & x"191" => data <= x"cc";
when "00" & x"192" => data <= x"66";
when "00" & x"193" => data <= x"69";
when "00" & x"194" => data <= x"6c";
when "00" & x"195" => data <= x"65";
when "00" & x"196" => data <= x"6e";
when "00" & x"197" => data <= x"61";
when "00" & x"198" => data <= x"6d";
when "00" & x"199" => data <= x"65";
when "00" & x"19a" => data <= x"00";
when "00" & x"19b" => data <= x"95";
when "00" & x"19c" => data <= x"c7";
when "00" & x"19d" => data <= x"e8";
when "00" & x"19e" => data <= x"d0";
when "00" & x"19f" => data <= x"dc";
when "00" & x"1a0" => data <= x"60";
when "00" & x"1a1" => data <= x"20";
when "00" & x"1a2" => data <= x"e1";
when "00" & x"1a3" => data <= x"83";
when "00" & x"1a4" => data <= x"ad";
when "00" & x"1a5" => data <= x"04";
when "00" & x"1a6" => data <= x"0f";
when "00" & x"1a7" => data <= x"20";
when "00" & x"1a8" => data <= x"47";
when "00" & x"1a9" => data <= x"83";
when "00" & x"1aa" => data <= x"cd";
when "00" & x"1ab" => data <= x"04";
when "00" & x"1ac" => data <= x"0f";
when "00" & x"1ad" => data <= x"f0";
when "00" & x"1ae" => data <= x"f1";
when "00" & x"1af" => data <= x"20";
when "00" & x"1b0" => data <= x"33";
when "00" & x"1b1" => data <= x"80";
when "00" & x"1b2" => data <= x"c8";
when "00" & x"1b3" => data <= x"44";
when "00" & x"1b4" => data <= x"69";
when "00" & x"1b5" => data <= x"73";
when "00" & x"1b6" => data <= x"6b";
when "00" & x"1b7" => data <= x"20";
when "00" & x"1b8" => data <= x"63";
when "00" & x"1b9" => data <= x"68";
when "00" & x"1ba" => data <= x"61";
when "00" & x"1bb" => data <= x"6e";
when "00" & x"1bc" => data <= x"67";
when "00" & x"1bd" => data <= x"65";
when "00" & x"1be" => data <= x"64";
when "00" & x"1bf" => data <= x"00";
when "00" & x"1c0" => data <= x"20";
when "00" & x"1c1" => data <= x"e1";
when "00" & x"1c2" => data <= x"83";
when "00" & x"1c3" => data <= x"b9";
when "00" & x"1c4" => data <= x"0f";
when "00" & x"1c5" => data <= x"0e";
when "00" & x"1c6" => data <= x"08";
when "00" & x"1c7" => data <= x"29";
when "00" & x"1c8" => data <= x"7f";
when "00" & x"1c9" => data <= x"d0";
when "00" & x"1ca" => data <= x"05";
when "00" & x"1cb" => data <= x"20";
when "00" & x"1cc" => data <= x"cb";
when "00" & x"1cd" => data <= x"9f";
when "00" & x"1ce" => data <= x"f0";
when "00" & x"1cf" => data <= x"06";
when "00" & x"1d0" => data <= x"20";
when "00" & x"1d1" => data <= x"9c";
when "00" & x"1d2" => data <= x"80";
when "00" & x"1d3" => data <= x"20";
when "00" & x"1d4" => data <= x"9a";
when "00" & x"1d5" => data <= x"80";
when "00" & x"1d6" => data <= x"a2";
when "00" & x"1d7" => data <= x"06";
when "00" & x"1d8" => data <= x"b9";
when "00" & x"1d9" => data <= x"08";
when "00" & x"1da" => data <= x"0e";
when "00" & x"1db" => data <= x"29";
when "00" & x"1dc" => data <= x"7f";
when "00" & x"1dd" => data <= x"20";
when "00" & x"1de" => data <= x"9c";
when "00" & x"1df" => data <= x"80";
when "00" & x"1e0" => data <= x"c8";
when "00" & x"1e1" => data <= x"ca";
when "00" & x"1e2" => data <= x"10";
when "00" & x"1e3" => data <= x"f4";
when "00" & x"1e4" => data <= x"20";
when "00" & x"1e5" => data <= x"cb";
when "00" & x"1e6" => data <= x"9f";
when "00" & x"1e7" => data <= x"a9";
when "00" & x"1e8" => data <= x"20";
when "00" & x"1e9" => data <= x"28";
when "00" & x"1ea" => data <= x"10";
when "00" & x"1eb" => data <= x"02";
when "00" & x"1ec" => data <= x"a9";
when "00" & x"1ed" => data <= x"4c";
when "00" & x"1ee" => data <= x"20";
when "00" & x"1ef" => data <= x"9c";
when "00" & x"1f0" => data <= x"80";
when "00" & x"1f1" => data <= x"4c";
when "00" & x"1f2" => data <= x"ce";
when "00" & x"1f3" => data <= x"9f";
when "00" & x"1f4" => data <= x"20";
when "00" & x"1f5" => data <= x"ce";
when "00" & x"1f6" => data <= x"9f";
when "00" & x"1f7" => data <= x"88";
when "00" & x"1f8" => data <= x"d0";
when "00" & x"1f9" => data <= x"fa";
when "00" & x"1fa" => data <= x"60";
when "00" & x"1fb" => data <= x"4a";
when "00" & x"1fc" => data <= x"4a";
when "00" & x"1fd" => data <= x"4a";
when "00" & x"1fe" => data <= x"4a";
when "00" & x"1ff" => data <= x"4a";
when "00" & x"200" => data <= x"4a";
when "00" & x"201" => data <= x"29";
when "00" & x"202" => data <= x"03";
when "00" & x"203" => data <= x"60";
when "00" & x"204" => data <= x"4a";
when "00" & x"205" => data <= x"4a";
when "00" & x"206" => data <= x"4a";
when "00" & x"207" => data <= x"4a";
when "00" & x"208" => data <= x"4a";
when "00" & x"209" => data <= x"60";
when "00" & x"20a" => data <= x"0a";
when "00" & x"20b" => data <= x"0a";
when "00" & x"20c" => data <= x"0a";
when "00" & x"20d" => data <= x"0a";
when "00" & x"20e" => data <= x"0a";
when "00" & x"20f" => data <= x"60";
when "00" & x"210" => data <= x"c8";
when "00" & x"211" => data <= x"c8";
when "00" & x"212" => data <= x"c8";
when "00" & x"213" => data <= x"c8";
when "00" & x"214" => data <= x"c8";
when "00" & x"215" => data <= x"c8";
when "00" & x"216" => data <= x"c8";
when "00" & x"217" => data <= x"c8";
when "00" & x"218" => data <= x"60";
when "00" & x"219" => data <= x"88";
when "00" & x"21a" => data <= x"88";
when "00" & x"21b" => data <= x"88";
when "00" & x"21c" => data <= x"88";
when "00" & x"21d" => data <= x"88";
when "00" & x"21e" => data <= x"88";
when "00" & x"21f" => data <= x"88";
when "00" & x"220" => data <= x"88";
when "00" & x"221" => data <= x"60";
when "00" & x"222" => data <= x"00";
when "00" & x"223" => data <= x"00";
when "00" & x"224" => data <= x"00";
when "00" & x"225" => data <= x"00";
when "00" & x"226" => data <= x"00";
when "00" & x"227" => data <= x"00";
when "00" & x"228" => data <= x"00";
when "00" & x"229" => data <= x"00";
when "00" & x"22a" => data <= x"00";
when "00" & x"22b" => data <= x"00";
when "00" & x"22c" => data <= x"00";
when "00" & x"22d" => data <= x"00";
when "00" & x"22e" => data <= x"00";
when "00" & x"22f" => data <= x"00";
when "00" & x"230" => data <= x"00";
when "00" & x"231" => data <= x"00";
when "00" & x"232" => data <= x"00";
when "00" & x"233" => data <= x"00";
when "00" & x"234" => data <= x"00";
when "00" & x"235" => data <= x"00";
when "00" & x"236" => data <= x"00";
when "00" & x"237" => data <= x"00";
when "00" & x"238" => data <= x"00";
when "00" & x"239" => data <= x"00";
when "00" & x"23a" => data <= x"00";
when "00" & x"23b" => data <= x"00";
when "00" & x"23c" => data <= x"00";
when "00" & x"23d" => data <= x"00";
when "00" & x"23e" => data <= x"00";
when "00" & x"23f" => data <= x"00";
when "00" & x"240" => data <= x"00";
when "00" & x"241" => data <= x"00";
when "00" & x"242" => data <= x"00";
when "00" & x"243" => data <= x"00";
when "00" & x"244" => data <= x"00";
when "00" & x"245" => data <= x"00";
when "00" & x"246" => data <= x"00";
when "00" & x"247" => data <= x"00";
when "00" & x"248" => data <= x"00";
when "00" & x"249" => data <= x"00";
when "00" & x"24a" => data <= x"00";
when "00" & x"24b" => data <= x"00";
when "00" & x"24c" => data <= x"00";
when "00" & x"24d" => data <= x"00";
when "00" & x"24e" => data <= x"00";
when "00" & x"24f" => data <= x"00";
when "00" & x"250" => data <= x"00";
when "00" & x"251" => data <= x"00";
when "00" & x"252" => data <= x"00";
when "00" & x"253" => data <= x"00";
when "00" & x"254" => data <= x"00";
when "00" & x"255" => data <= x"00";
when "00" & x"256" => data <= x"00";
when "00" & x"257" => data <= x"00";
when "00" & x"258" => data <= x"00";
when "00" & x"259" => data <= x"00";
when "00" & x"25a" => data <= x"00";
when "00" & x"25b" => data <= x"00";
when "00" & x"25c" => data <= x"00";
when "00" & x"25d" => data <= x"60";
when "00" & x"25e" => data <= x"a9";
when "00" & x"25f" => data <= x"23";
when "00" & x"260" => data <= x"d0";
when "00" & x"261" => data <= x"02";
when "00" & x"262" => data <= x"a9";
when "00" & x"263" => data <= x"ff";
when "00" & x"264" => data <= x"8d";
when "00" & x"265" => data <= x"cf";
when "00" & x"266" => data <= x"10";
when "00" & x"267" => data <= x"60";
when "00" & x"268" => data <= x"20";
when "00" & x"269" => data <= x"fe";
when "00" & x"26a" => data <= x"80";
when "00" & x"26b" => data <= x"4c";
when "00" & x"26c" => data <= x"71";
when "00" & x"26d" => data <= x"82";
when "00" & x"26e" => data <= x"20";
when "00" & x"26f" => data <= x"06";
when "00" & x"270" => data <= x"81";
when "00" & x"271" => data <= x"20";
when "00" & x"272" => data <= x"96";
when "00" & x"273" => data <= x"82";
when "00" & x"274" => data <= x"b0";
when "00" & x"275" => data <= x"e7";
when "00" & x"276" => data <= x"20";
when "00" & x"277" => data <= x"2b";
when "00" & x"278" => data <= x"80";
when "00" & x"279" => data <= x"d6";
when "00" & x"27a" => data <= x"6e";
when "00" & x"27b" => data <= x"6f";
when "00" & x"27c" => data <= x"74";
when "00" & x"27d" => data <= x"20";
when "00" & x"27e" => data <= x"66";
when "00" & x"27f" => data <= x"6f";
when "00" & x"280" => data <= x"75";
when "00" & x"281" => data <= x"6e";
when "00" & x"282" => data <= x"64";
when "00" & x"283" => data <= x"00";
when "00" & x"284" => data <= x"20";
when "00" & x"285" => data <= x"5e";
when "00" & x"286" => data <= x"82";
when "00" & x"287" => data <= x"20";
when "00" & x"288" => data <= x"01";
when "00" & x"289" => data <= x"9a";
when "00" & x"28a" => data <= x"20";
when "00" & x"28b" => data <= x"68";
when "00" & x"28c" => data <= x"82";
when "00" & x"28d" => data <= x"20";
when "00" & x"28e" => data <= x"01";
when "00" & x"28f" => data <= x"83";
when "00" & x"290" => data <= x"20";
when "00" & x"291" => data <= x"9d";
when "00" & x"292" => data <= x"82";
when "00" & x"293" => data <= x"b0";
when "00" & x"294" => data <= x"f8";
when "00" & x"295" => data <= x"60";
when "00" & x"296" => data <= x"20";
when "00" & x"297" => data <= x"41";
when "00" & x"298" => data <= x"af";
when "00" & x"299" => data <= x"a0";
when "00" & x"29a" => data <= x"f8";
when "00" & x"29b" => data <= x"d0";
when "00" & x"29c" => data <= x"03";
when "00" & x"29d" => data <= x"ac";
when "00" & x"29e" => data <= x"ce";
when "00" & x"29f" => data <= x"10";
when "00" & x"2a0" => data <= x"20";
when "00" & x"2a1" => data <= x"10";
when "00" & x"2a2" => data <= x"82";
when "00" & x"2a3" => data <= x"cc";
when "00" & x"2a4" => data <= x"05";
when "00" & x"2a5" => data <= x"0f";
when "00" & x"2a6" => data <= x"b0";
when "00" & x"2a7" => data <= x"44";
when "00" & x"2a8" => data <= x"20";
when "00" & x"2a9" => data <= x"10";
when "00" & x"2aa" => data <= x"82";
when "00" & x"2ab" => data <= x"a2";
when "00" & x"2ac" => data <= x"07";
when "00" & x"2ad" => data <= x"b5";
when "00" & x"2ae" => data <= x"c7";
when "00" & x"2af" => data <= x"cd";
when "00" & x"2b0" => data <= x"cf";
when "00" & x"2b1" => data <= x"10";
when "00" & x"2b2" => data <= x"f0";
when "00" & x"2b3" => data <= x"0e";
when "00" & x"2b4" => data <= x"20";
when "00" & x"2b5" => data <= x"ee";
when "00" & x"2b6" => data <= x"82";
when "00" & x"2b7" => data <= x"59";
when "00" & x"2b8" => data <= x"07";
when "00" & x"2b9" => data <= x"0e";
when "00" & x"2ba" => data <= x"b0";
when "00" & x"2bb" => data <= x"02";
when "00" & x"2bc" => data <= x"29";
when "00" & x"2bd" => data <= x"df";
when "00" & x"2be" => data <= x"29";
when "00" & x"2bf" => data <= x"7f";
when "00" & x"2c0" => data <= x"d0";
when "00" & x"2c1" => data <= x"09";
when "00" & x"2c2" => data <= x"88";
when "00" & x"2c3" => data <= x"ca";
when "00" & x"2c4" => data <= x"10";
when "00" & x"2c5" => data <= x"e7";
when "00" & x"2c6" => data <= x"8c";
when "00" & x"2c7" => data <= x"ce";
when "00" & x"2c8" => data <= x"10";
when "00" & x"2c9" => data <= x"38";
when "00" & x"2ca" => data <= x"60";
when "00" & x"2cb" => data <= x"88";
when "00" & x"2cc" => data <= x"ca";
when "00" & x"2cd" => data <= x"10";
when "00" & x"2ce" => data <= x"fc";
when "00" & x"2cf" => data <= x"30";
when "00" & x"2d0" => data <= x"cf";
when "00" & x"2d1" => data <= x"20";
when "00" & x"2d2" => data <= x"4c";
when "00" & x"2d3" => data <= x"98";
when "00" & x"2d4" => data <= x"b9";
when "00" & x"2d5" => data <= x"10";
when "00" & x"2d6" => data <= x"0e";
when "00" & x"2d7" => data <= x"99";
when "00" & x"2d8" => data <= x"08";
when "00" & x"2d9" => data <= x"0e";
when "00" & x"2da" => data <= x"b9";
when "00" & x"2db" => data <= x"10";
when "00" & x"2dc" => data <= x"0f";
when "00" & x"2dd" => data <= x"99";
when "00" & x"2de" => data <= x"08";
when "00" & x"2df" => data <= x"0f";
when "00" & x"2e0" => data <= x"c8";
when "00" & x"2e1" => data <= x"cc";
when "00" & x"2e2" => data <= x"05";
when "00" & x"2e3" => data <= x"0f";
when "00" & x"2e4" => data <= x"90";
when "00" & x"2e5" => data <= x"ee";
when "00" & x"2e6" => data <= x"98";
when "00" & x"2e7" => data <= x"e9";
when "00" & x"2e8" => data <= x"08";
when "00" & x"2e9" => data <= x"8d";
when "00" & x"2ea" => data <= x"05";
when "00" & x"2eb" => data <= x"0f";
when "00" & x"2ec" => data <= x"18";
when "00" & x"2ed" => data <= x"60";
when "00" & x"2ee" => data <= x"48";
when "00" & x"2ef" => data <= x"29";
when "00" & x"2f0" => data <= x"df";
when "00" & x"2f1" => data <= x"c9";
when "00" & x"2f2" => data <= x"41";
when "00" & x"2f3" => data <= x"90";
when "00" & x"2f4" => data <= x"04";
when "00" & x"2f5" => data <= x"c9";
when "00" & x"2f6" => data <= x"5b";
when "00" & x"2f7" => data <= x"90";
when "00" & x"2f8" => data <= x"01";
when "00" & x"2f9" => data <= x"38";
when "00" & x"2fa" => data <= x"68";
when "00" & x"2fb" => data <= x"60";
when "00" & x"2fc" => data <= x"2c";
when "00" & x"2fd" => data <= x"c7";
when "00" & x"2fe" => data <= x"10";
when "00" & x"2ff" => data <= x"30";
when "00" & x"300" => data <= x"ec";
when "00" & x"301" => data <= x"20";
when "00" & x"302" => data <= x"e1";
when "00" & x"303" => data <= x"83";
when "00" & x"304" => data <= x"20";
when "00" & x"305" => data <= x"c0";
when "00" & x"306" => data <= x"81";
when "00" & x"307" => data <= x"98";
when "00" & x"308" => data <= x"48";
when "00" & x"309" => data <= x"a9";
when "00" & x"30a" => data <= x"60";
when "00" & x"30b" => data <= x"85";
when "00" & x"30c" => data <= x"b0";
when "00" & x"30d" => data <= x"a9";
when "00" & x"30e" => data <= x"10";
when "00" & x"30f" => data <= x"85";
when "00" & x"310" => data <= x"b1";
when "00" & x"311" => data <= x"20";
when "00" & x"312" => data <= x"7e";
when "00" & x"313" => data <= x"83";
when "00" & x"314" => data <= x"a0";
when "00" & x"315" => data <= x"02";
when "00" & x"316" => data <= x"20";
when "00" & x"317" => data <= x"ce";
when "00" & x"318" => data <= x"9f";
when "00" & x"319" => data <= x"20";
when "00" & x"31a" => data <= x"35";
when "00" & x"31b" => data <= x"83";
when "00" & x"31c" => data <= x"20";
when "00" & x"31d" => data <= x"35";
when "00" & x"31e" => data <= x"83";
when "00" & x"31f" => data <= x"20";
when "00" & x"320" => data <= x"35";
when "00" & x"321" => data <= x"83";
when "00" & x"322" => data <= x"68";
when "00" & x"323" => data <= x"a8";
when "00" & x"324" => data <= x"b9";
when "00" & x"325" => data <= x"0e";
when "00" & x"326" => data <= x"0f";
when "00" & x"327" => data <= x"29";
when "00" & x"328" => data <= x"03";
when "00" & x"329" => data <= x"20";
when "00" & x"32a" => data <= x"ca";
when "00" & x"32b" => data <= x"80";
when "00" & x"32c" => data <= x"b9";
when "00" & x"32d" => data <= x"0f";
when "00" & x"32e" => data <= x"0f";
when "00" & x"32f" => data <= x"20";
when "00" & x"330" => data <= x"c2";
when "00" & x"331" => data <= x"80";
when "00" & x"332" => data <= x"4c";
when "00" & x"333" => data <= x"9a";
when "00" & x"334" => data <= x"9f";
when "00" & x"335" => data <= x"a2";
when "00" & x"336" => data <= x"03";
when "00" & x"337" => data <= x"b9";
when "00" & x"338" => data <= x"62";
when "00" & x"339" => data <= x"10";
when "00" & x"33a" => data <= x"20";
when "00" & x"33b" => data <= x"c2";
when "00" & x"33c" => data <= x"80";
when "00" & x"33d" => data <= x"88";
when "00" & x"33e" => data <= x"ca";
when "00" & x"33f" => data <= x"d0";
when "00" & x"340" => data <= x"f6";
when "00" & x"341" => data <= x"20";
when "00" & x"342" => data <= x"11";
when "00" & x"343" => data <= x"82";
when "00" & x"344" => data <= x"4c";
when "00" & x"345" => data <= x"ce";
when "00" & x"346" => data <= x"9f";
when "00" & x"347" => data <= x"20";
when "00" & x"348" => data <= x"e1";
when "00" & x"349" => data <= x"83";
when "00" & x"34a" => data <= x"4c";
when "00" & x"34b" => data <= x"41";
when "00" & x"34c" => data <= x"af";
when "00" & x"34d" => data <= x"ad";
when "00" & x"34e" => data <= x"ca";
when "00" & x"34f" => data <= x"10";
when "00" & x"350" => data <= x"85";
when "00" & x"351" => data <= x"ce";
when "00" & x"352" => data <= x"ad";
when "00" & x"353" => data <= x"cb";
when "00" & x"354" => data <= x"10";
when "00" & x"355" => data <= x"4c";
when "00" & x"356" => data <= x"7e";
when "00" & x"357" => data <= x"87";
when "00" & x"358" => data <= x"20";
when "00" & x"359" => data <= x"bf";
when "00" & x"35a" => data <= x"86";
when "00" & x"35b" => data <= x"f0";
when "00" & x"35c" => data <= x"f5";
when "00" & x"35d" => data <= x"20";
when "00" & x"35e" => data <= x"c5";
when "00" & x"35f" => data <= x"ff";
when "00" & x"360" => data <= x"b0";
when "00" & x"361" => data <= x"12";
when "00" & x"362" => data <= x"c9";
when "00" & x"363" => data <= x"3a";
when "00" & x"364" => data <= x"f0";
when "00" & x"365" => data <= x"f7";
when "00" & x"366" => data <= x"38";
when "00" & x"367" => data <= x"e9";
when "00" & x"368" => data <= x"30";
when "00" & x"369" => data <= x"90";
when "00" & x"36a" => data <= x"09";
when "00" & x"36b" => data <= x"c9";
when "00" & x"36c" => data <= x"04";
when "00" & x"36d" => data <= x"b0";
when "00" & x"36e" => data <= x"05";
when "00" & x"36f" => data <= x"20";
when "00" & x"370" => data <= x"7e";
when "00" & x"371" => data <= x"87";
when "00" & x"372" => data <= x"18";
when "00" & x"373" => data <= x"60";
when "00" & x"374" => data <= x"20";
when "00" & x"375" => data <= x"22";
when "00" & x"376" => data <= x"80";
when "00" & x"377" => data <= x"cd";
when "00" & x"378" => data <= x"64";
when "00" & x"379" => data <= x"72";
when "00" & x"37a" => data <= x"69";
when "00" & x"37b" => data <= x"76";
when "00" & x"37c" => data <= x"65";
when "00" & x"37d" => data <= x"00";
when "00" & x"37e" => data <= x"20";
when "00" & x"37f" => data <= x"e1";
when "00" & x"380" => data <= x"83";
when "00" & x"381" => data <= x"98";
when "00" & x"382" => data <= x"48";
when "00" & x"383" => data <= x"aa";
when "00" & x"384" => data <= x"a0";
when "00" & x"385" => data <= x"02";
when "00" & x"386" => data <= x"a9";
when "00" & x"387" => data <= x"00";
when "00" & x"388" => data <= x"91";
when "00" & x"389" => data <= x"b0";
when "00" & x"38a" => data <= x"c8";
when "00" & x"38b" => data <= x"c0";
when "00" & x"38c" => data <= x"12";
when "00" & x"38d" => data <= x"d0";
when "00" & x"38e" => data <= x"f9";
when "00" & x"38f" => data <= x"a0";
when "00" & x"390" => data <= x"02";
when "00" & x"391" => data <= x"20";
when "00" & x"392" => data <= x"cf";
when "00" & x"393" => data <= x"83";
when "00" & x"394" => data <= x"c8";
when "00" & x"395" => data <= x"c8";
when "00" & x"396" => data <= x"c0";
when "00" & x"397" => data <= x"0e";
when "00" & x"398" => data <= x"d0";
when "00" & x"399" => data <= x"f7";
when "00" & x"39a" => data <= x"68";
when "00" & x"39b" => data <= x"aa";
when "00" & x"39c" => data <= x"bd";
when "00" & x"39d" => data <= x"0f";
when "00" & x"39e" => data <= x"0e";
when "00" & x"39f" => data <= x"10";
when "00" & x"3a0" => data <= x"06";
when "00" & x"3a1" => data <= x"a9";
when "00" & x"3a2" => data <= x"0a";
when "00" & x"3a3" => data <= x"a0";
when "00" & x"3a4" => data <= x"0e";
when "00" & x"3a5" => data <= x"91";
when "00" & x"3a6" => data <= x"b0";
when "00" & x"3a7" => data <= x"bd";
when "00" & x"3a8" => data <= x"0e";
when "00" & x"3a9" => data <= x"0f";
when "00" & x"3aa" => data <= x"a0";
when "00" & x"3ab" => data <= x"04";
when "00" & x"3ac" => data <= x"20";
when "00" & x"3ad" => data <= x"bb";
when "00" & x"3ae" => data <= x"83";
when "00" & x"3af" => data <= x"a0";
when "00" & x"3b0" => data <= x"0c";
when "00" & x"3b1" => data <= x"4a";
when "00" & x"3b2" => data <= x"4a";
when "00" & x"3b3" => data <= x"48";
when "00" & x"3b4" => data <= x"29";
when "00" & x"3b5" => data <= x"03";
when "00" & x"3b6" => data <= x"91";
when "00" & x"3b7" => data <= x"b0";
when "00" & x"3b8" => data <= x"68";
when "00" & x"3b9" => data <= x"a0";
when "00" & x"3ba" => data <= x"08";
when "00" & x"3bb" => data <= x"4a";
when "00" & x"3bc" => data <= x"4a";
when "00" & x"3bd" => data <= x"48";
when "00" & x"3be" => data <= x"29";
when "00" & x"3bf" => data <= x"03";
when "00" & x"3c0" => data <= x"91";
when "00" & x"3c1" => data <= x"b0";
when "00" & x"3c2" => data <= x"c9";
when "00" & x"3c3" => data <= x"03";
when "00" & x"3c4" => data <= x"d0";
when "00" & x"3c5" => data <= x"07";
when "00" & x"3c6" => data <= x"a9";
when "00" & x"3c7" => data <= x"ff";
when "00" & x"3c8" => data <= x"91";
when "00" & x"3c9" => data <= x"b0";
when "00" & x"3ca" => data <= x"c8";
when "00" & x"3cb" => data <= x"91";
when "00" & x"3cc" => data <= x"b0";
when "00" & x"3cd" => data <= x"68";
when "00" & x"3ce" => data <= x"60";
when "00" & x"3cf" => data <= x"20";
when "00" & x"3d0" => data <= x"d2";
when "00" & x"3d1" => data <= x"83";
when "00" & x"3d2" => data <= x"bd";
when "00" & x"3d3" => data <= x"08";
when "00" & x"3d4" => data <= x"0f";
when "00" & x"3d5" => data <= x"91";
when "00" & x"3d6" => data <= x"b0";
when "00" & x"3d7" => data <= x"e8";
when "00" & x"3d8" => data <= x"c8";
when "00" & x"3d9" => data <= x"60";
when "00" & x"3da" => data <= x"e6";
when "00" & x"3db" => data <= x"ae";
when "00" & x"3dc" => data <= x"d0";
when "00" & x"3dd" => data <= x"02";
when "00" & x"3de" => data <= x"e6";
when "00" & x"3df" => data <= x"af";
when "00" & x"3e0" => data <= x"60";
when "00" & x"3e1" => data <= x"48";
when "00" & x"3e2" => data <= x"8a";
when "00" & x"3e3" => data <= x"48";
when "00" & x"3e4" => data <= x"98";
when "00" & x"3e5" => data <= x"48";
when "00" & x"3e6" => data <= x"a9";
when "00" & x"3e7" => data <= x"84";
when "00" & x"3e8" => data <= x"48";
when "00" & x"3e9" => data <= x"a9";
when "00" & x"3ea" => data <= x"03";
when "00" & x"3eb" => data <= x"48";
when "00" & x"3ec" => data <= x"a0";
when "00" & x"3ed" => data <= x"05";
when "00" & x"3ee" => data <= x"ba";
when "00" & x"3ef" => data <= x"bd";
when "00" & x"3f0" => data <= x"07";
when "00" & x"3f1" => data <= x"01";
when "00" & x"3f2" => data <= x"48";
when "00" & x"3f3" => data <= x"88";
when "00" & x"3f4" => data <= x"d0";
when "00" & x"3f5" => data <= x"f8";
when "00" & x"3f6" => data <= x"a0";
when "00" & x"3f7" => data <= x"0a";
when "00" & x"3f8" => data <= x"bd";
when "00" & x"3f9" => data <= x"09";
when "00" & x"3fa" => data <= x"01";
when "00" & x"3fb" => data <= x"9d";
when "00" & x"3fc" => data <= x"0b";
when "00" & x"3fd" => data <= x"01";
when "00" & x"3fe" => data <= x"ca";
when "00" & x"3ff" => data <= x"88";
when "00" & x"400" => data <= x"d0";
when "00" & x"401" => data <= x"f6";
when "00" & x"402" => data <= x"68";
when "00" & x"403" => data <= x"68";
when "00" & x"404" => data <= x"68";
when "00" & x"405" => data <= x"a8";
when "00" & x"406" => data <= x"68";
when "00" & x"407" => data <= x"aa";
when "00" & x"408" => data <= x"68";
when "00" & x"409" => data <= x"60";
when "00" & x"40a" => data <= x"ba";
when "00" & x"40b" => data <= x"9d";
when "00" & x"40c" => data <= x"03";
when "00" & x"40d" => data <= x"01";
when "00" & x"40e" => data <= x"4c";
when "00" & x"40f" => data <= x"04";
when "00" & x"410" => data <= x"84";
when "00" & x"411" => data <= x"48";
when "00" & x"412" => data <= x"8a";
when "00" & x"413" => data <= x"48";
when "00" & x"414" => data <= x"98";
when "00" & x"415" => data <= x"48";
when "00" & x"416" => data <= x"a9";
when "00" & x"417" => data <= x"84";
when "00" & x"418" => data <= x"48";
when "00" & x"419" => data <= x"a9";
when "00" & x"41a" => data <= x"09";
when "00" & x"41b" => data <= x"48";
when "00" & x"41c" => data <= x"d0";
when "00" & x"41d" => data <= x"ce";
when "00" & x"41e" => data <= x"20";
when "00" & x"41f" => data <= x"b8";
when "00" & x"420" => data <= x"86";
when "00" & x"421" => data <= x"20";
when "00" & x"422" => data <= x"3b";
when "00" & x"423" => data <= x"af";
when "00" & x"424" => data <= x"a0";
when "00" & x"425" => data <= x"ff";
when "00" & x"426" => data <= x"84";
when "00" & x"427" => data <= x"a8";
when "00" & x"428" => data <= x"c8";
when "00" & x"429" => data <= x"84";
when "00" & x"42a" => data <= x"aa";
when "00" & x"42b" => data <= x"b9";
when "00" & x"42c" => data <= x"00";
when "00" & x"42d" => data <= x"0e";
when "00" & x"42e" => data <= x"c0";
when "00" & x"42f" => data <= x"08";
when "00" & x"430" => data <= x"90";
when "00" & x"431" => data <= x"03";
when "00" & x"432" => data <= x"b9";
when "00" & x"433" => data <= x"f8";
when "00" & x"434" => data <= x"0e";
when "00" & x"435" => data <= x"20";
when "00" & x"436" => data <= x"9c";
when "00" & x"437" => data <= x"80";
when "00" & x"438" => data <= x"c8";
when "00" & x"439" => data <= x"c0";
when "00" & x"43a" => data <= x"0c";
when "00" & x"43b" => data <= x"d0";
when "00" & x"43c" => data <= x"ee";
when "00" & x"43d" => data <= x"20";
when "00" & x"43e" => data <= x"65";
when "00" & x"43f" => data <= x"80";
when "00" & x"440" => data <= x"20";
when "00" & x"441" => data <= x"28";
when "00" & x"442" => data <= x"ad";
when "00" & x"443" => data <= x"04";
when "00" & x"444" => data <= x"0f";
when "00" & x"445" => data <= x"20";
when "00" & x"446" => data <= x"c2";
when "00" & x"447" => data <= x"80";
when "00" & x"448" => data <= x"20";
when "00" & x"449" => data <= x"65";
when "00" & x"44a" => data <= x"80";
when "00" & x"44b" => data <= x"29";
when "00" & x"44c" => data <= x"0d";
when "00" & x"44d" => data <= x"44";
when "00" & x"44e" => data <= x"72";
when "00" & x"44f" => data <= x"69";
when "00" & x"450" => data <= x"76";
when "00" & x"451" => data <= x"65";
when "00" & x"452" => data <= x"20";
when "00" & x"453" => data <= x"a5";
when "00" & x"454" => data <= x"cf";
when "00" & x"455" => data <= x"20";
when "00" & x"456" => data <= x"ca";
when "00" & x"457" => data <= x"80";
when "00" & x"458" => data <= x"a0";
when "00" & x"459" => data <= x"0d";
when "00" & x"45a" => data <= x"20";
when "00" & x"45b" => data <= x"f4";
when "00" & x"45c" => data <= x"81";
when "00" & x"45d" => data <= x"20";
when "00" & x"45e" => data <= x"65";
when "00" & x"45f" => data <= x"80";
when "00" & x"460" => data <= x"4f";
when "00" & x"461" => data <= x"70";
when "00" & x"462" => data <= x"74";
when "00" & x"463" => data <= x"69";
when "00" & x"464" => data <= x"6f";
when "00" & x"465" => data <= x"6e";
when "00" & x"466" => data <= x"20";
when "00" & x"467" => data <= x"ad";
when "00" & x"468" => data <= x"06";
when "00" & x"469" => data <= x"0f";
when "00" & x"46a" => data <= x"20";
when "00" & x"46b" => data <= x"05";
when "00" & x"46c" => data <= x"82";
when "00" & x"46d" => data <= x"20";
when "00" & x"46e" => data <= x"ca";
when "00" & x"46f" => data <= x"80";
when "00" & x"470" => data <= x"20";
when "00" & x"471" => data <= x"65";
when "00" & x"472" => data <= x"80";
when "00" & x"473" => data <= x"20";
when "00" & x"474" => data <= x"28";
when "00" & x"475" => data <= x"a0";
when "00" & x"476" => data <= x"03";
when "00" & x"477" => data <= x"0a";
when "00" & x"478" => data <= x"0a";
when "00" & x"479" => data <= x"aa";
when "00" & x"47a" => data <= x"bd";
when "00" & x"47b" => data <= x"6f";
when "00" & x"47c" => data <= x"85";
when "00" & x"47d" => data <= x"20";
when "00" & x"47e" => data <= x"9c";
when "00" & x"47f" => data <= x"80";
when "00" & x"480" => data <= x"e8";
when "00" & x"481" => data <= x"88";
when "00" & x"482" => data <= x"10";
when "00" & x"483" => data <= x"f6";
when "00" & x"484" => data <= x"20";
when "00" & x"485" => data <= x"65";
when "00" & x"486" => data <= x"80";
when "00" & x"487" => data <= x"29";
when "00" & x"488" => data <= x"0d";
when "00" & x"489" => data <= x"44";
when "00" & x"48a" => data <= x"69";
when "00" & x"48b" => data <= x"72";
when "00" & x"48c" => data <= x"65";
when "00" & x"48d" => data <= x"63";
when "00" & x"48e" => data <= x"74";
when "00" & x"48f" => data <= x"6f";
when "00" & x"490" => data <= x"72";
when "00" & x"491" => data <= x"79";
when "00" & x"492" => data <= x"20";
when "00" & x"493" => data <= x"3a";
when "00" & x"494" => data <= x"ad";
when "00" & x"495" => data <= x"cb";
when "00" & x"496" => data <= x"10";
when "00" & x"497" => data <= x"20";
when "00" & x"498" => data <= x"ca";
when "00" & x"499" => data <= x"80";
when "00" & x"49a" => data <= x"20";
when "00" & x"49b" => data <= x"9a";
when "00" & x"49c" => data <= x"80";
when "00" & x"49d" => data <= x"ad";
when "00" & x"49e" => data <= x"ca";
when "00" & x"49f" => data <= x"10";
when "00" & x"4a0" => data <= x"20";
when "00" & x"4a1" => data <= x"9c";
when "00" & x"4a2" => data <= x"80";
when "00" & x"4a3" => data <= x"a0";
when "00" & x"4a4" => data <= x"06";
when "00" & x"4a5" => data <= x"20";
when "00" & x"4a6" => data <= x"f4";
when "00" & x"4a7" => data <= x"81";
when "00" & x"4a8" => data <= x"20";
when "00" & x"4a9" => data <= x"65";
when "00" & x"4aa" => data <= x"80";
when "00" & x"4ab" => data <= x"4c";
when "00" & x"4ac" => data <= x"69";
when "00" & x"4ad" => data <= x"62";
when "00" & x"4ae" => data <= x"72";
when "00" & x"4af" => data <= x"61";
when "00" & x"4b0" => data <= x"72";
when "00" & x"4b1" => data <= x"79";
when "00" & x"4b2" => data <= x"20";
when "00" & x"4b3" => data <= x"3a";
when "00" & x"4b4" => data <= x"ad";
when "00" & x"4b5" => data <= x"cd";
when "00" & x"4b6" => data <= x"10";
when "00" & x"4b7" => data <= x"20";
when "00" & x"4b8" => data <= x"ca";
when "00" & x"4b9" => data <= x"80";
when "00" & x"4ba" => data <= x"20";
when "00" & x"4bb" => data <= x"9a";
when "00" & x"4bc" => data <= x"80";
when "00" & x"4bd" => data <= x"ad";
when "00" & x"4be" => data <= x"cc";
when "00" & x"4bf" => data <= x"10";
when "00" & x"4c0" => data <= x"20";
when "00" & x"4c1" => data <= x"9c";
when "00" & x"4c2" => data <= x"80";
when "00" & x"4c3" => data <= x"20";
when "00" & x"4c4" => data <= x"9a";
when "00" & x"4c5" => data <= x"9f";
when "00" & x"4c6" => data <= x"a0";
when "00" & x"4c7" => data <= x"00";
when "00" & x"4c8" => data <= x"cc";
when "00" & x"4c9" => data <= x"05";
when "00" & x"4ca" => data <= x"0f";
when "00" & x"4cb" => data <= x"b0";
when "00" & x"4cc" => data <= x"17";
when "00" & x"4cd" => data <= x"b9";
when "00" & x"4ce" => data <= x"0f";
when "00" & x"4cf" => data <= x"0e";
when "00" & x"4d0" => data <= x"4d";
when "00" & x"4d1" => data <= x"ca";
when "00" & x"4d2" => data <= x"10";
when "00" & x"4d3" => data <= x"29";
when "00" & x"4d4" => data <= x"7f";
when "00" & x"4d5" => data <= x"d0";
when "00" & x"4d6" => data <= x"08";
when "00" & x"4d7" => data <= x"b9";
when "00" & x"4d8" => data <= x"0f";
when "00" & x"4d9" => data <= x"0e";
when "00" & x"4da" => data <= x"29";
when "00" & x"4db" => data <= x"80";
when "00" & x"4dc" => data <= x"99";
when "00" & x"4dd" => data <= x"0f";
when "00" & x"4de" => data <= x"0e";
when "00" & x"4df" => data <= x"20";
when "00" & x"4e0" => data <= x"10";
when "00" & x"4e1" => data <= x"82";
when "00" & x"4e2" => data <= x"90";
when "00" & x"4e3" => data <= x"e4";
when "00" & x"4e4" => data <= x"a0";
when "00" & x"4e5" => data <= x"00";
when "00" & x"4e6" => data <= x"20";
when "00" & x"4e7" => data <= x"f6";
when "00" & x"4e8" => data <= x"84";
when "00" & x"4e9" => data <= x"90";
when "00" & x"4ea" => data <= x"16";
when "00" & x"4eb" => data <= x"a9";
when "00" & x"4ec" => data <= x"ff";
when "00" & x"4ed" => data <= x"8d";
when "00" & x"4ee" => data <= x"82";
when "00" & x"4ef" => data <= x"10";
when "00" & x"4f0" => data <= x"4c";
when "00" & x"4f1" => data <= x"9a";
when "00" & x"4f2" => data <= x"9f";
when "00" & x"4f3" => data <= x"20";
when "00" & x"4f4" => data <= x"10";
when "00" & x"4f5" => data <= x"82";
when "00" & x"4f6" => data <= x"cc";
when "00" & x"4f7" => data <= x"05";
when "00" & x"4f8" => data <= x"0f";
when "00" & x"4f9" => data <= x"b0";
when "00" & x"4fa" => data <= x"05";
when "00" & x"4fb" => data <= x"b9";
when "00" & x"4fc" => data <= x"08";
when "00" & x"4fd" => data <= x"0e";
when "00" & x"4fe" => data <= x"30";
when "00" & x"4ff" => data <= x"f3";
when "00" & x"500" => data <= x"60";
when "00" & x"501" => data <= x"84";
when "00" & x"502" => data <= x"ab";
when "00" & x"503" => data <= x"a2";
when "00" & x"504" => data <= x"00";
when "00" & x"505" => data <= x"b9";
when "00" & x"506" => data <= x"08";
when "00" & x"507" => data <= x"0e";
when "00" & x"508" => data <= x"29";
when "00" & x"509" => data <= x"7f";
when "00" & x"50a" => data <= x"9d";
when "00" & x"50b" => data <= x"60";
when "00" & x"50c" => data <= x"10";
when "00" & x"50d" => data <= x"c8";
when "00" & x"50e" => data <= x"e8";
when "00" & x"50f" => data <= x"e0";
when "00" & x"510" => data <= x"08";
when "00" & x"511" => data <= x"d0";
when "00" & x"512" => data <= x"f2";
when "00" & x"513" => data <= x"20";
when "00" & x"514" => data <= x"f6";
when "00" & x"515" => data <= x"84";
when "00" & x"516" => data <= x"b0";
when "00" & x"517" => data <= x"1f";
when "00" & x"518" => data <= x"38";
when "00" & x"519" => data <= x"a2";
when "00" & x"51a" => data <= x"06";
when "00" & x"51b" => data <= x"b9";
when "00" & x"51c" => data <= x"0e";
when "00" & x"51d" => data <= x"0e";
when "00" & x"51e" => data <= x"fd";
when "00" & x"51f" => data <= x"60";
when "00" & x"520" => data <= x"10";
when "00" & x"521" => data <= x"88";
when "00" & x"522" => data <= x"ca";
when "00" & x"523" => data <= x"10";
when "00" & x"524" => data <= x"f6";
when "00" & x"525" => data <= x"20";
when "00" & x"526" => data <= x"11";
when "00" & x"527" => data <= x"82";
when "00" & x"528" => data <= x"b9";
when "00" & x"529" => data <= x"0f";
when "00" & x"52a" => data <= x"0e";
when "00" & x"52b" => data <= x"29";
when "00" & x"52c" => data <= x"7f";
when "00" & x"52d" => data <= x"ed";
when "00" & x"52e" => data <= x"67";
when "00" & x"52f" => data <= x"10";
when "00" & x"530" => data <= x"90";
when "00" & x"531" => data <= x"cf";
when "00" & x"532" => data <= x"20";
when "00" & x"533" => data <= x"10";
when "00" & x"534" => data <= x"82";
when "00" & x"535" => data <= x"b0";
when "00" & x"536" => data <= x"dc";
when "00" & x"537" => data <= x"a4";
when "00" & x"538" => data <= x"ab";
when "00" & x"539" => data <= x"b9";
when "00" & x"53a" => data <= x"08";
when "00" & x"53b" => data <= x"0e";
when "00" & x"53c" => data <= x"09";
when "00" & x"53d" => data <= x"80";
when "00" & x"53e" => data <= x"99";
when "00" & x"53f" => data <= x"08";
when "00" & x"540" => data <= x"0e";
when "00" & x"541" => data <= x"ad";
when "00" & x"542" => data <= x"67";
when "00" & x"543" => data <= x"10";
when "00" & x"544" => data <= x"c5";
when "00" & x"545" => data <= x"aa";
when "00" & x"546" => data <= x"f0";
when "00" & x"547" => data <= x"10";
when "00" & x"548" => data <= x"a6";
when "00" & x"549" => data <= x"aa";
when "00" & x"54a" => data <= x"85";
when "00" & x"54b" => data <= x"aa";
when "00" & x"54c" => data <= x"d0";
when "00" & x"54d" => data <= x"0a";
when "00" & x"54e" => data <= x"20";
when "00" & x"54f" => data <= x"9a";
when "00" & x"550" => data <= x"9f";
when "00" & x"551" => data <= x"20";
when "00" & x"552" => data <= x"9a";
when "00" & x"553" => data <= x"9f";
when "00" & x"554" => data <= x"a0";
when "00" & x"555" => data <= x"ff";
when "00" & x"556" => data <= x"d0";
when "00" & x"557" => data <= x"09";
when "00" & x"558" => data <= x"a4";
when "00" & x"559" => data <= x"a8";
when "00" & x"55a" => data <= x"d0";
when "00" & x"55b" => data <= x"f5";
when "00" & x"55c" => data <= x"a0";
when "00" & x"55d" => data <= x"05";
when "00" & x"55e" => data <= x"20";
when "00" & x"55f" => data <= x"f4";
when "00" & x"560" => data <= x"81";
when "00" & x"561" => data <= x"c8";
when "00" & x"562" => data <= x"84";
when "00" & x"563" => data <= x"a8";
when "00" & x"564" => data <= x"a4";
when "00" & x"565" => data <= x"ab";
when "00" & x"566" => data <= x"20";
when "00" & x"567" => data <= x"cb";
when "00" & x"568" => data <= x"9f";
when "00" & x"569" => data <= x"20";
when "00" & x"56a" => data <= x"c0";
when "00" & x"56b" => data <= x"81";
when "00" & x"56c" => data <= x"4c";
when "00" & x"56d" => data <= x"e4";
when "00" & x"56e" => data <= x"84";
when "00" & x"56f" => data <= x"6f";
when "00" & x"570" => data <= x"66";
when "00" & x"571" => data <= x"66";
when "00" & x"572" => data <= x"00";
when "00" & x"573" => data <= x"4c";
when "00" & x"574" => data <= x"4f";
when "00" & x"575" => data <= x"41";
when "00" & x"576" => data <= x"44";
when "00" & x"577" => data <= x"52";
when "00" & x"578" => data <= x"55";
when "00" & x"579" => data <= x"4e";
when "00" & x"57a" => data <= x"00";
when "00" & x"57b" => data <= x"45";
when "00" & x"57c" => data <= x"58";
when "00" & x"57d" => data <= x"45";
when "00" & x"57e" => data <= x"43";
when "00" & x"57f" => data <= x"b9";
when "00" & x"580" => data <= x"0e";
when "00" & x"581" => data <= x"0f";
when "00" & x"582" => data <= x"20";
when "00" & x"583" => data <= x"fd";
when "00" & x"584" => data <= x"81";
when "00" & x"585" => data <= x"85";
when "00" & x"586" => data <= x"c4";
when "00" & x"587" => data <= x"18";
when "00" & x"588" => data <= x"a9";
when "00" & x"589" => data <= x"ff";
when "00" & x"58a" => data <= x"79";
when "00" & x"58b" => data <= x"0c";
when "00" & x"58c" => data <= x"0f";
when "00" & x"58d" => data <= x"b9";
when "00" & x"58e" => data <= x"0f";
when "00" & x"58f" => data <= x"0f";
when "00" & x"590" => data <= x"79";
when "00" & x"591" => data <= x"0d";
when "00" & x"592" => data <= x"0f";
when "00" & x"593" => data <= x"85";
when "00" & x"594" => data <= x"c5";
when "00" & x"595" => data <= x"b9";
when "00" & x"596" => data <= x"0e";
when "00" & x"597" => data <= x"0f";
when "00" & x"598" => data <= x"29";
when "00" & x"599" => data <= x"03";
when "00" & x"59a" => data <= x"65";
when "00" & x"59b" => data <= x"c4";
when "00" & x"59c" => data <= x"85";
when "00" & x"59d" => data <= x"c4";
when "00" & x"59e" => data <= x"38";
when "00" & x"59f" => data <= x"b9";
when "00" & x"5a0" => data <= x"07";
when "00" & x"5a1" => data <= x"0f";
when "00" & x"5a2" => data <= x"e5";
when "00" & x"5a3" => data <= x"c5";
when "00" & x"5a4" => data <= x"48";
when "00" & x"5a5" => data <= x"b9";
when "00" & x"5a6" => data <= x"06";
when "00" & x"5a7" => data <= x"0f";
when "00" & x"5a8" => data <= x"29";
when "00" & x"5a9" => data <= x"03";
when "00" & x"5aa" => data <= x"e5";
when "00" & x"5ab" => data <= x"c4";
when "00" & x"5ac" => data <= x"aa";
when "00" & x"5ad" => data <= x"a9";
when "00" & x"5ae" => data <= x"00";
when "00" & x"5af" => data <= x"c5";
when "00" & x"5b0" => data <= x"c2";
when "00" & x"5b1" => data <= x"68";
when "00" & x"5b2" => data <= x"e5";
when "00" & x"5b3" => data <= x"c3";
when "00" & x"5b4" => data <= x"8a";
when "00" & x"5b5" => data <= x"e5";
when "00" & x"5b6" => data <= x"c6";
when "00" & x"5b7" => data <= x"60";
when "00" & x"5b8" => data <= x"41";
when "00" & x"5b9" => data <= x"43";
when "00" & x"5ba" => data <= x"43";
when "00" & x"5bb" => data <= x"45";
when "00" & x"5bc" => data <= x"53";
when "00" & x"5bd" => data <= x"53";
when "00" & x"5be" => data <= x"88";
when "00" & x"5bf" => data <= x"d1";
when "00" & x"5c0" => data <= x"32";
when "00" & x"5c1" => data <= x"42";
when "00" & x"5c2" => data <= x"41";
when "00" & x"5c3" => data <= x"43";
when "00" & x"5c4" => data <= x"4b";
when "00" & x"5c5" => data <= x"55";
when "00" & x"5c6" => data <= x"50";
when "00" & x"5c7" => data <= x"9c";
when "00" & x"5c8" => data <= x"ba";
when "00" & x"5c9" => data <= x"54";
when "00" & x"5ca" => data <= x"43";
when "00" & x"5cb" => data <= x"4f";
when "00" & x"5cc" => data <= x"4d";
when "00" & x"5cd" => data <= x"50";
when "00" & x"5ce" => data <= x"41";
when "00" & x"5cf" => data <= x"43";
when "00" & x"5d0" => data <= x"54";
when "00" & x"5d1" => data <= x"9a";
when "00" & x"5d2" => data <= x"bf";
when "00" & x"5d3" => data <= x"0a";
when "00" & x"5d4" => data <= x"43";
when "00" & x"5d5" => data <= x"4f";
when "00" & x"5d6" => data <= x"50";
when "00" & x"5d7" => data <= x"59";
when "00" & x"5d8" => data <= x"9d";
when "00" & x"5d9" => data <= x"26";
when "00" & x"5da" => data <= x"64";
when "00" & x"5db" => data <= x"44";
when "00" & x"5dc" => data <= x"45";
when "00" & x"5dd" => data <= x"4c";
when "00" & x"5de" => data <= x"45";
when "00" & x"5df" => data <= x"54";
when "00" & x"5e0" => data <= x"45";
when "00" & x"5e1" => data <= x"86";
when "00" & x"5e2" => data <= x"fd";
when "00" & x"5e3" => data <= x"01";
when "00" & x"5e4" => data <= x"44";
when "00" & x"5e5" => data <= x"45";
when "00" & x"5e6" => data <= x"53";
when "00" & x"5e7" => data <= x"54";
when "00" & x"5e8" => data <= x"52";
when "00" & x"5e9" => data <= x"4f";
when "00" & x"5ea" => data <= x"59";
when "00" & x"5eb" => data <= x"87";
when "00" & x"5ec" => data <= x"0f";
when "00" & x"5ed" => data <= x"02";
when "00" & x"5ee" => data <= x"44";
when "00" & x"5ef" => data <= x"49";
when "00" & x"5f0" => data <= x"52";
when "00" & x"5f1" => data <= x"88";
when "00" & x"5f2" => data <= x"4d";
when "00" & x"5f3" => data <= x"09";
when "00" & x"5f4" => data <= x"44";
when "00" & x"5f5" => data <= x"52";
when "00" & x"5f6" => data <= x"49";
when "00" & x"5f7" => data <= x"56";
when "00" & x"5f8" => data <= x"45";
when "00" & x"5f9" => data <= x"87";
when "00" & x"5fa" => data <= x"74";
when "00" & x"5fb" => data <= x"0a";
when "00" & x"5fc" => data <= x"45";
when "00" & x"5fd" => data <= x"4e";
when "00" & x"5fe" => data <= x"41";
when "00" & x"5ff" => data <= x"42";
when "00" & x"600" => data <= x"4c";
when "00" & x"601" => data <= x"45";
when "00" & x"602" => data <= x"8a";
when "00" & x"603" => data <= x"38";
when "00" & x"604" => data <= x"00";
when "00" & x"605" => data <= x"49";
when "00" & x"606" => data <= x"4e";
when "00" & x"607" => data <= x"46";
when "00" & x"608" => data <= x"4f";
when "00" & x"609" => data <= x"82";
when "00" & x"60a" => data <= x"83";
when "00" & x"60b" => data <= x"02";
when "00" & x"60c" => data <= x"4c";
when "00" & x"60d" => data <= x"49";
when "00" & x"60e" => data <= x"42";
when "00" & x"60f" => data <= x"88";
when "00" & x"610" => data <= x"51";
when "00" & x"611" => data <= x"09";
when "00" & x"612" => data <= x"52";
when "00" & x"613" => data <= x"45";
when "00" & x"614" => data <= x"4e";
when "00" & x"615" => data <= x"41";
when "00" & x"616" => data <= x"4d";
when "00" & x"617" => data <= x"45";
when "00" & x"618" => data <= x"8a";
when "00" & x"619" => data <= x"6c";
when "00" & x"61a" => data <= x"87";
when "00" & x"61b" => data <= x"54";
when "00" & x"61c" => data <= x"49";
when "00" & x"61d" => data <= x"54";
when "00" & x"61e" => data <= x"4c";
when "00" & x"61f" => data <= x"45";
when "00" & x"620" => data <= x"88";
when "00" & x"621" => data <= x"a2";
when "00" & x"622" => data <= x"0b";
when "00" & x"623" => data <= x"57";
when "00" & x"624" => data <= x"49";
when "00" & x"625" => data <= x"50";
when "00" & x"626" => data <= x"45";
when "00" & x"627" => data <= x"86";
when "00" & x"628" => data <= x"c2";
when "00" & x"629" => data <= x"02";
when "00" & x"62a" => data <= x"b4";
when "00" & x"62b" => data <= x"6b";
when "00" & x"62c" => data <= x"00";
when "00" & x"62d" => data <= x"42";
when "00" & x"62e" => data <= x"55";
when "00" & x"62f" => data <= x"49";
when "00" & x"630" => data <= x"4c";
when "00" & x"631" => data <= x"44";
when "00" & x"632" => data <= x"9f";
when "00" & x"633" => data <= x"47";
when "00" & x"634" => data <= x"01";
when "00" & x"635" => data <= x"43";
when "00" & x"636" => data <= x"41";
when "00" & x"637" => data <= x"52";
when "00" & x"638" => data <= x"44";
when "00" & x"639" => data <= x"93";
when "00" & x"63a" => data <= x"37";
when "00" & x"63b" => data <= x"00";
when "00" & x"63c" => data <= x"44";
when "00" & x"63d" => data <= x"55";
when "00" & x"63e" => data <= x"4d";
when "00" & x"63f" => data <= x"50";
when "00" & x"640" => data <= x"9e";
when "00" & x"641" => data <= x"cf";
when "00" & x"642" => data <= x"01";
when "00" & x"643" => data <= x"4c";
when "00" & x"644" => data <= x"49";
when "00" & x"645" => data <= x"53";
when "00" & x"646" => data <= x"54";
when "00" & x"647" => data <= x"9e";
when "00" & x"648" => data <= x"8d";
when "00" & x"649" => data <= x"01";
when "00" & x"64a" => data <= x"54";
when "00" & x"64b" => data <= x"59";
when "00" & x"64c" => data <= x"50";
when "00" & x"64d" => data <= x"45";
when "00" & x"64e" => data <= x"9e";
when "00" & x"64f" => data <= x"86";
when "00" & x"650" => data <= x"01";
when "00" & x"651" => data <= x"44";
when "00" & x"652" => data <= x"4d";
when "00" & x"653" => data <= x"4d";
when "00" & x"654" => data <= x"43";
when "00" & x"655" => data <= x"93";
when "00" & x"656" => data <= x"37";
when "00" & x"657" => data <= x"00";
when "00" & x"658" => data <= x"85";
when "00" & x"659" => data <= x"b6";
when "00" & x"65a" => data <= x"00";
when "00" & x"65b" => data <= x"44";
when "00" & x"65c" => data <= x"46";
when "00" & x"65d" => data <= x"53";
when "00" & x"65e" => data <= x"99";
when "00" & x"65f" => data <= x"c5";
when "00" & x"660" => data <= x"00";
when "00" & x"661" => data <= x"55";
when "00" & x"662" => data <= x"54";
when "00" & x"663" => data <= x"49";
when "00" & x"664" => data <= x"4c";
when "00" & x"665" => data <= x"53";
when "00" & x"666" => data <= x"99";
when "00" & x"667" => data <= x"ed";
when "00" & x"668" => data <= x"00";
when "00" & x"669" => data <= x"99";
when "00" & x"66a" => data <= x"f4";
when "00" & x"66b" => data <= x"00";
when "00" & x"66c" => data <= x"20";
when "00" & x"66d" => data <= x"b8";
when "00" & x"66e" => data <= x"86";
when "00" & x"66f" => data <= x"a2";
when "00" & x"670" => data <= x"fd";
when "00" & x"671" => data <= x"8a";
when "00" & x"672" => data <= x"ba";
when "00" & x"673" => data <= x"86";
when "00" & x"674" => data <= x"b6";
when "00" & x"675" => data <= x"aa";
when "00" & x"676" => data <= x"98";
when "00" & x"677" => data <= x"48";
when "00" & x"678" => data <= x"e8";
when "00" & x"679" => data <= x"e8";
when "00" & x"67a" => data <= x"68";
when "00" & x"67b" => data <= x"48";
when "00" & x"67c" => data <= x"a8";
when "00" & x"67d" => data <= x"20";
when "00" & x"67e" => data <= x"bf";
when "00" & x"67f" => data <= x"86";
when "00" & x"680" => data <= x"e8";
when "00" & x"681" => data <= x"bd";
when "00" & x"682" => data <= x"b8";
when "00" & x"683" => data <= x"85";
when "00" & x"684" => data <= x"30";
when "00" & x"685" => data <= x"28";
when "00" & x"686" => data <= x"ca";
when "00" & x"687" => data <= x"88";
when "00" & x"688" => data <= x"86";
when "00" & x"689" => data <= x"b8";
when "00" & x"68a" => data <= x"e8";
when "00" & x"68b" => data <= x"c8";
when "00" & x"68c" => data <= x"bd";
when "00" & x"68d" => data <= x"b8";
when "00" & x"68e" => data <= x"85";
when "00" & x"68f" => data <= x"30";
when "00" & x"690" => data <= x"16";
when "00" & x"691" => data <= x"51";
when "00" & x"692" => data <= x"f2";
when "00" & x"693" => data <= x"29";
when "00" & x"694" => data <= x"5f";
when "00" & x"695" => data <= x"f0";
when "00" & x"696" => data <= x"f3";
when "00" & x"697" => data <= x"ca";
when "00" & x"698" => data <= x"e8";
when "00" & x"699" => data <= x"bd";
when "00" & x"69a" => data <= x"b8";
when "00" & x"69b" => data <= x"85";
when "00" & x"69c" => data <= x"10";
when "00" & x"69d" => data <= x"fa";
when "00" & x"69e" => data <= x"b1";
when "00" & x"69f" => data <= x"f2";
when "00" & x"6a0" => data <= x"c9";
when "00" & x"6a1" => data <= x"2e";
when "00" & x"6a2" => data <= x"d0";
when "00" & x"6a3" => data <= x"d4";
when "00" & x"6a4" => data <= x"c8";
when "00" & x"6a5" => data <= x"b0";
when "00" & x"6a6" => data <= x"07";
when "00" & x"6a7" => data <= x"b1";
when "00" & x"6a8" => data <= x"f2";
when "00" & x"6a9" => data <= x"20";
when "00" & x"6aa" => data <= x"ee";
when "00" & x"6ab" => data <= x"82";
when "00" & x"6ac" => data <= x"90";
when "00" & x"6ad" => data <= x"ca";
when "00" & x"6ae" => data <= x"68";
when "00" & x"6af" => data <= x"bd";
when "00" & x"6b0" => data <= x"b8";
when "00" & x"6b1" => data <= x"85";
when "00" & x"6b2" => data <= x"48";
when "00" & x"6b3" => data <= x"bd";
when "00" & x"6b4" => data <= x"b9";
when "00" & x"6b5" => data <= x"85";
when "00" & x"6b6" => data <= x"48";
when "00" & x"6b7" => data <= x"60";
when "00" & x"6b8" => data <= x"86";
when "00" & x"6b9" => data <= x"f2";
when "00" & x"6ba" => data <= x"84";
when "00" & x"6bb" => data <= x"f3";
when "00" & x"6bc" => data <= x"a0";
when "00" & x"6bd" => data <= x"00";
when "00" & x"6be" => data <= x"60";
when "00" & x"6bf" => data <= x"18";
when "00" & x"6c0" => data <= x"4c";
when "00" & x"6c1" => data <= x"c2";
when "00" & x"6c2" => data <= x"ff";
when "00" & x"6c3" => data <= x"20";
when "00" & x"6c4" => data <= x"5e";
when "00" & x"6c5" => data <= x"82";
when "00" & x"6c6" => data <= x"20";
when "00" & x"6c7" => data <= x"01";
when "00" & x"6c8" => data <= x"9a";
when "00" & x"6c9" => data <= x"20";
when "00" & x"6ca" => data <= x"68";
when "00" & x"6cb" => data <= x"82";
when "00" & x"6cc" => data <= x"b9";
when "00" & x"6cd" => data <= x"0f";
when "00" & x"6ce" => data <= x"0e";
when "00" & x"6cf" => data <= x"30";
when "00" & x"6d0" => data <= x"12";
when "00" & x"6d1" => data <= x"20";
when "00" & x"6d2" => data <= x"c0";
when "00" & x"6d3" => data <= x"81";
when "00" & x"6d4" => data <= x"20";
when "00" & x"6d5" => data <= x"65";
when "00" & x"6d6" => data <= x"80";
when "00" & x"6d7" => data <= x"20";
when "00" & x"6d8" => data <= x"3a";
when "00" & x"6d9" => data <= x"20";
when "00" & x"6da" => data <= x"ea";
when "00" & x"6db" => data <= x"20";
when "00" & x"6dc" => data <= x"9e";
when "00" & x"6dd" => data <= x"9c";
when "00" & x"6de" => data <= x"f0";
when "00" & x"6df" => data <= x"09";
when "00" & x"6e0" => data <= x"20";
when "00" & x"6e1" => data <= x"9a";
when "00" & x"6e2" => data <= x"9f";
when "00" & x"6e3" => data <= x"20";
when "00" & x"6e4" => data <= x"9d";
when "00" & x"6e5" => data <= x"82";
when "00" & x"6e6" => data <= x"b0";
when "00" & x"6e7" => data <= x"e4";
when "00" & x"6e8" => data <= x"60";
when "00" & x"6e9" => data <= x"20";
when "00" & x"6ea" => data <= x"a1";
when "00" & x"6eb" => data <= x"81";
when "00" & x"6ec" => data <= x"20";
when "00" & x"6ed" => data <= x"d1";
when "00" & x"6ee" => data <= x"82";
when "00" & x"6ef" => data <= x"20";
when "00" & x"6f0" => data <= x"b4";
when "00" & x"6f1" => data <= x"8a";
when "00" & x"6f2" => data <= x"ac";
when "00" & x"6f3" => data <= x"ce";
when "00" & x"6f4" => data <= x"10";
when "00" & x"6f5" => data <= x"20";
when "00" & x"6f6" => data <= x"19";
when "00" & x"6f7" => data <= x"82";
when "00" & x"6f8" => data <= x"8c";
when "00" & x"6f9" => data <= x"ce";
when "00" & x"6fa" => data <= x"10";
when "00" & x"6fb" => data <= x"4c";
when "00" & x"6fc" => data <= x"e0";
when "00" & x"6fd" => data <= x"86";
when "00" & x"6fe" => data <= x"20";
when "00" & x"6ff" => data <= x"62";
when "00" & x"700" => data <= x"82";
when "00" & x"701" => data <= x"20";
when "00" & x"702" => data <= x"01";
when "00" & x"703" => data <= x"9a";
when "00" & x"704" => data <= x"20";
when "00" & x"705" => data <= x"68";
when "00" & x"706" => data <= x"82";
when "00" & x"707" => data <= x"20";
when "00" & x"708" => data <= x"fc";
when "00" & x"709" => data <= x"82";
when "00" & x"70a" => data <= x"20";
when "00" & x"70b" => data <= x"d1";
when "00" & x"70c" => data <= x"82";
when "00" & x"70d" => data <= x"4c";
when "00" & x"70e" => data <= x"b4";
when "00" & x"70f" => data <= x"8a";
when "00" & x"710" => data <= x"20";
when "00" & x"711" => data <= x"bd";
when "00" & x"712" => data <= x"9b";
when "00" & x"713" => data <= x"20";
when "00" & x"714" => data <= x"5e";
when "00" & x"715" => data <= x"82";
when "00" & x"716" => data <= x"20";
when "00" & x"717" => data <= x"01";
when "00" & x"718" => data <= x"9a";
when "00" & x"719" => data <= x"20";
when "00" & x"71a" => data <= x"68";
when "00" & x"71b" => data <= x"82";
when "00" & x"71c" => data <= x"b9";
when "00" & x"71d" => data <= x"0f";
when "00" & x"71e" => data <= x"0e";
when "00" & x"71f" => data <= x"30";
when "00" & x"720" => data <= x"06";
when "00" & x"721" => data <= x"20";
when "00" & x"722" => data <= x"c0";
when "00" & x"723" => data <= x"81";
when "00" & x"724" => data <= x"20";
when "00" & x"725" => data <= x"9a";
when "00" & x"726" => data <= x"9f";
when "00" & x"727" => data <= x"20";
when "00" & x"728" => data <= x"9d";
when "00" & x"729" => data <= x"82";
when "00" & x"72a" => data <= x"b0";
when "00" & x"72b" => data <= x"f0";
when "00" & x"72c" => data <= x"20";
when "00" & x"72d" => data <= x"65";
when "00" & x"72e" => data <= x"80";
when "00" & x"72f" => data <= x"0d";
when "00" & x"730" => data <= x"44";
when "00" & x"731" => data <= x"65";
when "00" & x"732" => data <= x"6c";
when "00" & x"733" => data <= x"65";
when "00" & x"734" => data <= x"74";
when "00" & x"735" => data <= x"65";
when "00" & x"736" => data <= x"20";
when "00" & x"737" => data <= x"28";
when "00" & x"738" => data <= x"59";
when "00" & x"739" => data <= x"2f";
when "00" & x"73a" => data <= x"4e";
when "00" & x"73b" => data <= x"29";
when "00" & x"73c" => data <= x"20";
when "00" & x"73d" => data <= x"3f";
when "00" & x"73e" => data <= x"20";
when "00" & x"73f" => data <= x"ea";
when "00" & x"740" => data <= x"20";
when "00" & x"741" => data <= x"9e";
when "00" & x"742" => data <= x"9c";
when "00" & x"743" => data <= x"f0";
when "00" & x"744" => data <= x"03";
when "00" & x"745" => data <= x"4c";
when "00" & x"746" => data <= x"9a";
when "00" & x"747" => data <= x"9f";
when "00" & x"748" => data <= x"20";
when "00" & x"749" => data <= x"a1";
when "00" & x"74a" => data <= x"81";
when "00" & x"74b" => data <= x"20";
when "00" & x"74c" => data <= x"96";
when "00" & x"74d" => data <= x"82";
when "00" & x"74e" => data <= x"b9";
when "00" & x"74f" => data <= x"0f";
when "00" & x"750" => data <= x"0e";
when "00" & x"751" => data <= x"30";
when "00" & x"752" => data <= x"0c";
when "00" & x"753" => data <= x"20";
when "00" & x"754" => data <= x"d1";
when "00" & x"755" => data <= x"82";
when "00" & x"756" => data <= x"ac";
when "00" & x"757" => data <= x"ce";
when "00" & x"758" => data <= x"10";
when "00" & x"759" => data <= x"20";
when "00" & x"75a" => data <= x"19";
when "00" & x"75b" => data <= x"82";
when "00" & x"75c" => data <= x"8c";
when "00" & x"75d" => data <= x"ce";
when "00" & x"75e" => data <= x"10";
when "00" & x"75f" => data <= x"20";
when "00" & x"760" => data <= x"9d";
when "00" & x"761" => data <= x"82";
when "00" & x"762" => data <= x"b0";
when "00" & x"763" => data <= x"ea";
when "00" & x"764" => data <= x"20";
when "00" & x"765" => data <= x"b4";
when "00" & x"766" => data <= x"8a";
when "00" & x"767" => data <= x"20";
when "00" & x"768" => data <= x"65";
when "00" & x"769" => data <= x"80";
when "00" & x"76a" => data <= x"0d";
when "00" & x"76b" => data <= x"44";
when "00" & x"76c" => data <= x"65";
when "00" & x"76d" => data <= x"6c";
when "00" & x"76e" => data <= x"65";
when "00" & x"76f" => data <= x"74";
when "00" & x"770" => data <= x"65";
when "00" & x"771" => data <= x"64";
when "00" & x"772" => data <= x"0d";
when "00" & x"773" => data <= x"ea";
when "00" & x"774" => data <= x"60";
when "00" & x"775" => data <= x"20";
when "00" & x"776" => data <= x"01";
when "00" & x"777" => data <= x"9a";
when "00" & x"778" => data <= x"20";
when "00" & x"779" => data <= x"5d";
when "00" & x"77a" => data <= x"83";
when "00" & x"77b" => data <= x"8d";
when "00" & x"77c" => data <= x"cb";
when "00" & x"77d" => data <= x"10";
when "00" & x"77e" => data <= x"ea";
when "00" & x"77f" => data <= x"ea";
when "00" & x"780" => data <= x"ea";
when "00" & x"781" => data <= x"29";
when "00" & x"782" => data <= x"03";
when "00" & x"783" => data <= x"85";
when "00" & x"784" => data <= x"cf";
when "00" & x"785" => data <= x"60";
when "00" & x"786" => data <= x"20";
when "00" & x"787" => data <= x"61";
when "00" & x"788" => data <= x"89";
when "00" & x"789" => data <= x"20";
when "00" & x"78a" => data <= x"6e";
when "00" & x"78b" => data <= x"98";
when "00" & x"78c" => data <= x"20";
when "00" & x"78d" => data <= x"7e";
when "00" & x"78e" => data <= x"83";
when "00" & x"78f" => data <= x"4c";
when "00" & x"790" => data <= x"99";
when "00" & x"791" => data <= x"af";
when "00" & x"792" => data <= x"ea";
when "00" & x"793" => data <= x"ea";
when "00" & x"794" => data <= x"20";
when "00" & x"795" => data <= x"6e";
when "00" & x"796" => data <= x"82";
when "00" & x"797" => data <= x"20";
when "00" & x"798" => data <= x"6e";
when "00" & x"799" => data <= x"98";
when "00" & x"79a" => data <= x"20";
when "00" & x"79b" => data <= x"7e";
when "00" & x"79c" => data <= x"83";
when "00" & x"79d" => data <= x"84";
when "00" & x"79e" => data <= x"bc";
when "00" & x"79f" => data <= x"a2";
when "00" & x"7a0" => data <= x"00";
when "00" & x"7a1" => data <= x"a5";
when "00" & x"7a2" => data <= x"c0";
when "00" & x"7a3" => data <= x"d0";
when "00" & x"7a4" => data <= x"06";
when "00" & x"7a5" => data <= x"c8";
when "00" & x"7a6" => data <= x"c8";
when "00" & x"7a7" => data <= x"a2";
when "00" & x"7a8" => data <= x"02";
when "00" & x"7a9" => data <= x"d0";
when "00" & x"7aa" => data <= x"08";
when "00" & x"7ab" => data <= x"b9";
when "00" & x"7ac" => data <= x"0e";
when "00" & x"7ad" => data <= x"0f";
when "00" & x"7ae" => data <= x"85";
when "00" & x"7af" => data <= x"c4";
when "00" & x"7b0" => data <= x"20";
when "00" & x"7b1" => data <= x"3f";
when "00" & x"7b2" => data <= x"8a";
when "00" & x"7b3" => data <= x"b9";
when "00" & x"7b4" => data <= x"08";
when "00" & x"7b5" => data <= x"0f";
when "00" & x"7b6" => data <= x"95";
when "00" & x"7b7" => data <= x"be";
when "00" & x"7b8" => data <= x"c8";
when "00" & x"7b9" => data <= x"e8";
when "00" & x"7ba" => data <= x"e0";
when "00" & x"7bb" => data <= x"08";
when "00" & x"7bc" => data <= x"d0";
when "00" & x"7bd" => data <= x"f5";
when "00" & x"7be" => data <= x"20";
when "00" & x"7bf" => data <= x"56";
when "00" & x"7c0" => data <= x"8a";
when "00" & x"7c1" => data <= x"a4";
when "00" & x"7c2" => data <= x"bc";
when "00" & x"7c3" => data <= x"20";
when "00" & x"7c4" => data <= x"fc";
when "00" & x"7c5" => data <= x"82";
when "00" & x"7c6" => data <= x"4c";
when "00" & x"7c7" => data <= x"8a";
when "00" & x"7c8" => data <= x"af";
when "00" & x"7c9" => data <= x"00";
when "00" & x"7ca" => data <= x"00";
when "00" & x"7cb" => data <= x"00";
when "00" & x"7cc" => data <= x"00";
when "00" & x"7cd" => data <= x"00";
when "00" & x"7ce" => data <= x"00";
when "00" & x"7cf" => data <= x"00";
when "00" & x"7d0" => data <= x"00";
when "00" & x"7d1" => data <= x"00";
when "00" & x"7d2" => data <= x"00";
when "00" & x"7d3" => data <= x"00";
when "00" & x"7d4" => data <= x"20";
when "00" & x"7d5" => data <= x"b8";
when "00" & x"7d6" => data <= x"86";
when "00" & x"7d7" => data <= x"20";
when "00" & x"7d8" => data <= x"41";
when "00" & x"7d9" => data <= x"88";
when "00" & x"7da" => data <= x"8c";
when "00" & x"7db" => data <= x"db";
when "00" & x"7dc" => data <= x"10";
when "00" & x"7dd" => data <= x"20";
when "00" & x"7de" => data <= x"06";
when "00" & x"7df" => data <= x"81";
when "00" & x"7e0" => data <= x"8c";
when "00" & x"7e1" => data <= x"da";
when "00" & x"7e2" => data <= x"10";
when "00" & x"7e3" => data <= x"20";
when "00" & x"7e4" => data <= x"96";
when "00" & x"7e5" => data <= x"82";
when "00" & x"7e6" => data <= x"b0";
when "00" & x"7e7" => data <= x"22";
when "00" & x"7e8" => data <= x"ac";
when "00" & x"7e9" => data <= x"db";
when "00" & x"7ea" => data <= x"10";
when "00" & x"7eb" => data <= x"ad";
when "00" & x"7ec" => data <= x"cc";
when "00" & x"7ed" => data <= x"10";
when "00" & x"7ee" => data <= x"85";
when "00" & x"7ef" => data <= x"ce";
when "00" & x"7f0" => data <= x"ad";
when "00" & x"7f1" => data <= x"cd";
when "00" & x"7f2" => data <= x"10";
when "00" & x"7f3" => data <= x"20";
when "00" & x"7f4" => data <= x"7e";
when "00" & x"7f5" => data <= x"87";
when "00" & x"7f6" => data <= x"20";
when "00" & x"7f7" => data <= x"09";
when "00" & x"7f8" => data <= x"81";
when "00" & x"7f9" => data <= x"20";
when "00" & x"7fa" => data <= x"96";
when "00" & x"7fb" => data <= x"82";
when "00" & x"7fc" => data <= x"b0";
when "00" & x"7fd" => data <= x"0c";
when "00" & x"7fe" => data <= x"20";
when "00" & x"7ff" => data <= x"22";
when "00" & x"800" => data <= x"80";
when "00" & x"801" => data <= x"fe";
when "00" & x"802" => data <= x"63";
when "00" & x"803" => data <= x"6f";
when "00" & x"804" => data <= x"6d";
when "00" & x"805" => data <= x"6d";
when "00" & x"806" => data <= x"61";
when "00" & x"807" => data <= x"6e";
when "00" & x"808" => data <= x"64";
when "00" & x"809" => data <= x"00";
when "00" & x"80a" => data <= x"20";
when "00" & x"80b" => data <= x"9d";
when "00" & x"80c" => data <= x"87";
when "00" & x"80d" => data <= x"18";
when "00" & x"80e" => data <= x"ad";
when "00" & x"80f" => data <= x"da";
when "00" & x"810" => data <= x"10";
when "00" & x"811" => data <= x"a8";
when "00" & x"812" => data <= x"65";
when "00" & x"813" => data <= x"f2";
when "00" & x"814" => data <= x"8d";
when "00" & x"815" => data <= x"da";
when "00" & x"816" => data <= x"10";
when "00" & x"817" => data <= x"a5";
when "00" & x"818" => data <= x"f3";
when "00" & x"819" => data <= x"69";
when "00" & x"81a" => data <= x"00";
when "00" & x"81b" => data <= x"8d";
when "00" & x"81c" => data <= x"db";
when "00" & x"81d" => data <= x"10";
when "00" & x"81e" => data <= x"ad";
when "00" & x"81f" => data <= x"76";
when "00" & x"820" => data <= x"10";
when "00" & x"821" => data <= x"2d";
when "00" & x"822" => data <= x"77";
when "00" & x"823" => data <= x"10";
when "00" & x"824" => data <= x"0d";
when "00" & x"825" => data <= x"d7";
when "00" & x"826" => data <= x"10";
when "00" & x"827" => data <= x"c9";
when "00" & x"828" => data <= x"ff";
when "00" & x"829" => data <= x"f0";
when "00" & x"82a" => data <= x"13";
when "00" & x"82b" => data <= x"a5";
when "00" & x"82c" => data <= x"c0";
when "00" & x"82d" => data <= x"8d";
when "00" & x"82e" => data <= x"74";
when "00" & x"82f" => data <= x"10";
when "00" & x"830" => data <= x"a5";
when "00" & x"831" => data <= x"c1";
when "00" & x"832" => data <= x"8d";
when "00" & x"833" => data <= x"75";
when "00" & x"834" => data <= x"10";
when "00" & x"835" => data <= x"a2";
when "00" & x"836" => data <= x"74";
when "00" & x"837" => data <= x"a0";
when "00" & x"838" => data <= x"10";
when "00" & x"839" => data <= x"a9";
when "00" & x"83a" => data <= x"04";
when "00" & x"83b" => data <= x"4c";
when "00" & x"83c" => data <= x"06";
when "00" & x"83d" => data <= x"04";
when "00" & x"83e" => data <= x"6c";
when "00" & x"83f" => data <= x"c0";
when "00" & x"840" => data <= x"00";
when "00" & x"841" => data <= x"a9";
when "00" & x"842" => data <= x"ff";
when "00" & x"843" => data <= x"85";
when "00" & x"844" => data <= x"c0";
when "00" & x"845" => data <= x"a5";
when "00" & x"846" => data <= x"f2";
when "00" & x"847" => data <= x"85";
when "00" & x"848" => data <= x"bc";
when "00" & x"849" => data <= x"a5";
when "00" & x"84a" => data <= x"f3";
when "00" & x"84b" => data <= x"85";
when "00" & x"84c" => data <= x"bd";
when "00" & x"84d" => data <= x"60";
when "00" & x"84e" => data <= x"a2";
when "00" & x"84f" => data <= x"00";
when "00" & x"850" => data <= x"f0";
when "00" & x"851" => data <= x"02";
when "00" & x"852" => data <= x"a2";
when "00" & x"853" => data <= x"02";
when "00" & x"854" => data <= x"20";
when "00" & x"855" => data <= x"60";
when "00" & x"856" => data <= x"88";
when "00" & x"857" => data <= x"9d";
when "00" & x"858" => data <= x"cb";
when "00" & x"859" => data <= x"10";
when "00" & x"85a" => data <= x"a5";
when "00" & x"85b" => data <= x"ce";
when "00" & x"85c" => data <= x"9d";
when "00" & x"85d" => data <= x"ca";
when "00" & x"85e" => data <= x"10";
when "00" & x"85f" => data <= x"60";
when "00" & x"860" => data <= x"a9";
when "00" & x"861" => data <= x"24";
when "00" & x"862" => data <= x"85";
when "00" & x"863" => data <= x"ce";
when "00" & x"864" => data <= x"20";
when "00" & x"865" => data <= x"bf";
when "00" & x"866" => data <= x"86";
when "00" & x"867" => data <= x"d0";
when "00" & x"868" => data <= x"07";
when "00" & x"869" => data <= x"a9";
when "00" & x"86a" => data <= x"00";
when "00" & x"86b" => data <= x"20";
when "00" & x"86c" => data <= x"7e";
when "00" & x"86d" => data <= x"87";
when "00" & x"86e" => data <= x"f0";
when "00" & x"86f" => data <= x"30";
when "00" & x"870" => data <= x"ad";
when "00" & x"871" => data <= x"cb";
when "00" & x"872" => data <= x"10";
when "00" & x"873" => data <= x"20";
when "00" & x"874" => data <= x"7e";
when "00" & x"875" => data <= x"87";
when "00" & x"876" => data <= x"20";
when "00" & x"877" => data <= x"c5";
when "00" & x"878" => data <= x"ff";
when "00" & x"879" => data <= x"b0";
when "00" & x"87a" => data <= x"10";
when "00" & x"87b" => data <= x"c9";
when "00" & x"87c" => data <= x"3a";
when "00" & x"87d" => data <= x"d0";
when "00" & x"87e" => data <= x"1a";
when "00" & x"87f" => data <= x"20";
when "00" & x"880" => data <= x"5d";
when "00" & x"881" => data <= x"83";
when "00" & x"882" => data <= x"20";
when "00" & x"883" => data <= x"c5";
when "00" & x"884" => data <= x"ff";
when "00" & x"885" => data <= x"b0";
when "00" & x"886" => data <= x"19";
when "00" & x"887" => data <= x"c9";
when "00" & x"888" => data <= x"2e";
when "00" & x"889" => data <= x"f0";
when "00" & x"88a" => data <= x"eb";
when "00" & x"88b" => data <= x"20";
when "00" & x"88c" => data <= x"22";
when "00" & x"88d" => data <= x"80";
when "00" & x"88e" => data <= x"ce";
when "00" & x"88f" => data <= x"64";
when "00" & x"890" => data <= x"69";
when "00" & x"891" => data <= x"72";
when "00" & x"892" => data <= x"65";
when "00" & x"893" => data <= x"63";
when "00" & x"894" => data <= x"74";
when "00" & x"895" => data <= x"6f";
when "00" & x"896" => data <= x"72";
when "00" & x"897" => data <= x"79";
when "00" & x"898" => data <= x"00";
when "00" & x"899" => data <= x"85";
when "00" & x"89a" => data <= x"ce";
when "00" & x"89b" => data <= x"20";
when "00" & x"89c" => data <= x"c5";
when "00" & x"89d" => data <= x"ff";
when "00" & x"89e" => data <= x"90";
when "00" & x"89f" => data <= x"eb";
when "00" & x"8a0" => data <= x"a5";
when "00" & x"8a1" => data <= x"cf";
when "00" & x"8a2" => data <= x"60";
when "00" & x"8a3" => data <= x"20";
when "00" & x"8a4" => data <= x"01";
when "00" & x"8a5" => data <= x"9a";
when "00" & x"8a6" => data <= x"20";
when "00" & x"8a7" => data <= x"4d";
when "00" & x"8a8" => data <= x"83";
when "00" & x"8a9" => data <= x"20";
when "00" & x"8aa" => data <= x"47";
when "00" & x"8ab" => data <= x"83";
when "00" & x"8ac" => data <= x"4c";
when "00" & x"8ad" => data <= x"ce";
when "00" & x"8ae" => data <= x"b2";
when "00" & x"8af" => data <= x"00";
when "00" & x"8b0" => data <= x"20";
when "00" & x"8b1" => data <= x"c6";
when "00" & x"8b2" => data <= x"88";
when "00" & x"8b3" => data <= x"ca";
when "00" & x"8b4" => data <= x"10";
when "00" & x"8b5" => data <= x"fa";
when "00" & x"8b6" => data <= x"e8";
when "00" & x"8b7" => data <= x"20";
when "00" & x"8b8" => data <= x"c5";
when "00" & x"8b9" => data <= x"ff";
when "00" & x"8ba" => data <= x"b0";
when "00" & x"8bb" => data <= x"07";
when "00" & x"8bc" => data <= x"20";
when "00" & x"8bd" => data <= x"c6";
when "00" & x"8be" => data <= x"88";
when "00" & x"8bf" => data <= x"e0";
when "00" & x"8c0" => data <= x"0b";
when "00" & x"8c1" => data <= x"90";
when "00" & x"8c2" => data <= x"f3";
when "00" & x"8c3" => data <= x"4c";
when "00" & x"8c4" => data <= x"b4";
when "00" & x"8c5" => data <= x"8a";
when "00" & x"8c6" => data <= x"e0";
when "00" & x"8c7" => data <= x"08";
when "00" & x"8c8" => data <= x"90";
when "00" & x"8c9" => data <= x"04";
when "00" & x"8ca" => data <= x"9d";
when "00" & x"8cb" => data <= x"f8";
when "00" & x"8cc" => data <= x"0e";
when "00" & x"8cd" => data <= x"60";
when "00" & x"8ce" => data <= x"9d";
when "00" & x"8cf" => data <= x"00";
when "00" & x"8d0" => data <= x"0e";
when "00" & x"8d1" => data <= x"60";
when "00" & x"8d2" => data <= x"20";
when "00" & x"8d3" => data <= x"5e";
when "00" & x"8d4" => data <= x"82";
when "00" & x"8d5" => data <= x"20";
when "00" & x"8d6" => data <= x"01";
when "00" & x"8d7" => data <= x"9a";
when "00" & x"8d8" => data <= x"20";
when "00" & x"8d9" => data <= x"fe";
when "00" & x"8da" => data <= x"80";
when "00" & x"8db" => data <= x"a2";
when "00" & x"8dc" => data <= x"00";
when "00" & x"8dd" => data <= x"20";
when "00" & x"8de" => data <= x"bf";
when "00" & x"8df" => data <= x"86";
when "00" & x"8e0" => data <= x"d0";
when "00" & x"8e1" => data <= x"23";
when "00" & x"8e2" => data <= x"86";
when "00" & x"8e3" => data <= x"aa";
when "00" & x"8e4" => data <= x"20";
when "00" & x"8e5" => data <= x"96";
when "00" & x"8e6" => data <= x"82";
when "00" & x"8e7" => data <= x"b0";
when "00" & x"8e8" => data <= x"03";
when "00" & x"8e9" => data <= x"4c";
when "00" & x"8ea" => data <= x"76";
when "00" & x"8eb" => data <= x"82";
when "00" & x"8ec" => data <= x"20";
when "00" & x"8ed" => data <= x"4f";
when "00" & x"8ee" => data <= x"98";
when "00" & x"8ef" => data <= x"b9";
when "00" & x"8f0" => data <= x"0f";
when "00" & x"8f1" => data <= x"0e";
when "00" & x"8f2" => data <= x"29";
when "00" & x"8f3" => data <= x"7f";
when "00" & x"8f4" => data <= x"05";
when "00" & x"8f5" => data <= x"aa";
when "00" & x"8f6" => data <= x"99";
when "00" & x"8f7" => data <= x"0f";
when "00" & x"8f8" => data <= x"0e";
when "00" & x"8f9" => data <= x"20";
when "00" & x"8fa" => data <= x"fc";
when "00" & x"8fb" => data <= x"82";
when "00" & x"8fc" => data <= x"20";
when "00" & x"8fd" => data <= x"9d";
when "00" & x"8fe" => data <= x"82";
when "00" & x"8ff" => data <= x"b0";
when "00" & x"900" => data <= x"eb";
when "00" & x"901" => data <= x"90";
when "00" & x"902" => data <= x"c0";
when "00" & x"903" => data <= x"a2";
when "00" & x"904" => data <= x"80";
when "00" & x"905" => data <= x"20";
when "00" & x"906" => data <= x"c5";
when "00" & x"907" => data <= x"ff";
when "00" & x"908" => data <= x"b0";
when "00" & x"909" => data <= x"d8";
when "00" & x"90a" => data <= x"c9";
when "00" & x"90b" => data <= x"4c";
when "00" & x"90c" => data <= x"f0";
when "00" & x"90d" => data <= x"f5";
when "00" & x"90e" => data <= x"20";
when "00" & x"90f" => data <= x"22";
when "00" & x"910" => data <= x"80";
when "00" & x"911" => data <= x"cf";
when "00" & x"912" => data <= x"61";
when "00" & x"913" => data <= x"74";
when "00" & x"914" => data <= x"74";
when "00" & x"915" => data <= x"72";
when "00" & x"916" => data <= x"69";
when "00" & x"917" => data <= x"62";
when "00" & x"918" => data <= x"75";
when "00" & x"919" => data <= x"74";
when "00" & x"91a" => data <= x"65";
when "00" & x"91b" => data <= x"00";
when "00" & x"91c" => data <= x"20";
when "00" & x"91d" => data <= x"e1";
when "00" & x"91e" => data <= x"83";
when "00" & x"91f" => data <= x"8a";
when "00" & x"920" => data <= x"c9";
when "00" & x"921" => data <= x"04";
when "00" & x"922" => data <= x"f0";
when "00" & x"923" => data <= x"1a";
when "00" & x"924" => data <= x"c9";
when "00" & x"925" => data <= x"02";
when "00" & x"926" => data <= x"90";
when "00" & x"927" => data <= x"0b";
when "00" & x"928" => data <= x"20";
when "00" & x"929" => data <= x"22";
when "00" & x"92a" => data <= x"80";
when "00" & x"92b" => data <= x"cb";
when "00" & x"92c" => data <= x"6f";
when "00" & x"92d" => data <= x"70";
when "00" & x"92e" => data <= x"74";
when "00" & x"92f" => data <= x"69";
when "00" & x"930" => data <= x"6f";
when "00" & x"931" => data <= x"6e";
when "00" & x"932" => data <= x"00";
when "00" & x"933" => data <= x"a2";
when "00" & x"934" => data <= x"ff";
when "00" & x"935" => data <= x"98";
when "00" & x"936" => data <= x"f0";
when "00" & x"937" => data <= x"02";
when "00" & x"938" => data <= x"a2";
when "00" & x"939" => data <= x"00";
when "00" & x"93a" => data <= x"8e";
when "00" & x"93b" => data <= x"c7";
when "00" & x"93c" => data <= x"10";
when "00" & x"93d" => data <= x"60";
when "00" & x"93e" => data <= x"98";
when "00" & x"93f" => data <= x"48";
when "00" & x"940" => data <= x"20";
when "00" & x"941" => data <= x"4d";
when "00" & x"942" => data <= x"83";
when "00" & x"943" => data <= x"20";
when "00" & x"944" => data <= x"41";
when "00" & x"945" => data <= x"af";
when "00" & x"946" => data <= x"68";
when "00" & x"947" => data <= x"20";
when "00" & x"948" => data <= x"0b";
when "00" & x"949" => data <= x"82";
when "00" & x"94a" => data <= x"4d";
when "00" & x"94b" => data <= x"06";
when "00" & x"94c" => data <= x"0f";
when "00" & x"94d" => data <= x"29";
when "00" & x"94e" => data <= x"30";
when "00" & x"94f" => data <= x"4d";
when "00" & x"950" => data <= x"06";
when "00" & x"951" => data <= x"0f";
when "00" & x"952" => data <= x"8d";
when "00" & x"953" => data <= x"06";
when "00" & x"954" => data <= x"0f";
when "00" & x"955" => data <= x"4c";
when "00" & x"956" => data <= x"b4";
when "00" & x"957" => data <= x"8a";
when "00" & x"958" => data <= x"20";
when "00" & x"959" => data <= x"18";
when "00" & x"95a" => data <= x"80";
when "00" & x"95b" => data <= x"c6";
when "00" & x"95c" => data <= x"66";
when "00" & x"95d" => data <= x"75";
when "00" & x"95e" => data <= x"6c";
when "00" & x"95f" => data <= x"6c";
when "00" & x"960" => data <= x"00";
when "00" & x"961" => data <= x"20";
when "00" & x"962" => data <= x"06";
when "00" & x"963" => data <= x"81";
when "00" & x"964" => data <= x"20";
when "00" & x"965" => data <= x"96";
when "00" & x"966" => data <= x"82";
when "00" & x"967" => data <= x"90";
when "00" & x"968" => data <= x"03";
when "00" & x"969" => data <= x"20";
when "00" & x"96a" => data <= x"d1";
when "00" & x"96b" => data <= x"82";
when "00" & x"96c" => data <= x"a5";
when "00" & x"96d" => data <= x"c2";
when "00" & x"96e" => data <= x"48";
when "00" & x"96f" => data <= x"a5";
when "00" & x"970" => data <= x"c3";
when "00" & x"971" => data <= x"48";
when "00" & x"972" => data <= x"38";
when "00" & x"973" => data <= x"a5";
when "00" & x"974" => data <= x"c4";
when "00" & x"975" => data <= x"e5";
when "00" & x"976" => data <= x"c2";
when "00" & x"977" => data <= x"85";
when "00" & x"978" => data <= x"c2";
when "00" & x"979" => data <= x"a5";
when "00" & x"97a" => data <= x"c5";
when "00" & x"97b" => data <= x"e5";
when "00" & x"97c" => data <= x"c3";
when "00" & x"97d" => data <= x"85";
when "00" & x"97e" => data <= x"c3";
when "00" & x"97f" => data <= x"ad";
when "00" & x"980" => data <= x"7a";
when "00" & x"981" => data <= x"10";
when "00" & x"982" => data <= x"ed";
when "00" & x"983" => data <= x"78";
when "00" & x"984" => data <= x"10";
when "00" & x"985" => data <= x"85";
when "00" & x"986" => data <= x"c6";
when "00" & x"987" => data <= x"20";
when "00" & x"988" => data <= x"9d";
when "00" & x"989" => data <= x"89";
when "00" & x"98a" => data <= x"ad";
when "00" & x"98b" => data <= x"79";
when "00" & x"98c" => data <= x"10";
when "00" & x"98d" => data <= x"8d";
when "00" & x"98e" => data <= x"75";
when "00" & x"98f" => data <= x"10";
when "00" & x"990" => data <= x"ad";
when "00" & x"991" => data <= x"78";
when "00" & x"992" => data <= x"10";
when "00" & x"993" => data <= x"8d";
when "00" & x"994" => data <= x"74";
when "00" & x"995" => data <= x"10";
when "00" & x"996" => data <= x"68";
when "00" & x"997" => data <= x"85";
when "00" & x"998" => data <= x"bf";
when "00" & x"999" => data <= x"68";
when "00" & x"99a" => data <= x"85";
when "00" & x"99b" => data <= x"be";
when "00" & x"99c" => data <= x"60";
when "00" & x"99d" => data <= x"a9";
when "00" & x"99e" => data <= x"00";
when "00" & x"99f" => data <= x"85";
when "00" & x"9a0" => data <= x"c4";
when "00" & x"9a1" => data <= x"a9";
when "00" & x"9a2" => data <= x"02";
when "00" & x"9a3" => data <= x"85";
when "00" & x"9a4" => data <= x"c5";
when "00" & x"9a5" => data <= x"ac";
when "00" & x"9a6" => data <= x"05";
when "00" & x"9a7" => data <= x"0f";
when "00" & x"9a8" => data <= x"f0";
when "00" & x"9a9" => data <= x"2d";
when "00" & x"9aa" => data <= x"c0";
when "00" & x"9ab" => data <= x"f8";
when "00" & x"9ac" => data <= x"b0";
when "00" & x"9ad" => data <= x"56";
when "00" & x"9ae" => data <= x"20";
when "00" & x"9af" => data <= x"9e";
when "00" & x"9b0" => data <= x"85";
when "00" & x"9b1" => data <= x"4c";
when "00" & x"9b2" => data <= x"bc";
when "00" & x"9b3" => data <= x"89";
when "00" & x"9b4" => data <= x"f0";
when "00" & x"9b5" => data <= x"a2";
when "00" & x"9b6" => data <= x"20";
when "00" & x"9b7" => data <= x"19";
when "00" & x"9b8" => data <= x"82";
when "00" & x"9b9" => data <= x"20";
when "00" & x"9ba" => data <= x"7f";
when "00" & x"9bb" => data <= x"85";
when "00" & x"9bc" => data <= x"98";
when "00" & x"9bd" => data <= x"90";
when "00" & x"9be" => data <= x"f5";
when "00" & x"9bf" => data <= x"84";
when "00" & x"9c0" => data <= x"b0";
when "00" & x"9c1" => data <= x"ac";
when "00" & x"9c2" => data <= x"05";
when "00" & x"9c3" => data <= x"0f";
when "00" & x"9c4" => data <= x"c4";
when "00" & x"9c5" => data <= x"b0";
when "00" & x"9c6" => data <= x"f0";
when "00" & x"9c7" => data <= x"0f";
when "00" & x"9c8" => data <= x"b9";
when "00" & x"9c9" => data <= x"07";
when "00" & x"9ca" => data <= x"0e";
when "00" & x"9cb" => data <= x"99";
when "00" & x"9cc" => data <= x"0f";
when "00" & x"9cd" => data <= x"0e";
when "00" & x"9ce" => data <= x"b9";
when "00" & x"9cf" => data <= x"07";
when "00" & x"9d0" => data <= x"0f";
when "00" & x"9d1" => data <= x"99";
when "00" & x"9d2" => data <= x"0f";
when "00" & x"9d3" => data <= x"0f";
when "00" & x"9d4" => data <= x"88";
when "00" & x"9d5" => data <= x"b0";
when "00" & x"9d6" => data <= x"ed";
when "00" & x"9d7" => data <= x"a2";
when "00" & x"9d8" => data <= x"00";
when "00" & x"9d9" => data <= x"20";
when "00" & x"9da" => data <= x"17";
when "00" & x"9db" => data <= x"8a";
when "00" & x"9dc" => data <= x"b5";
when "00" & x"9dd" => data <= x"c7";
when "00" & x"9de" => data <= x"99";
when "00" & x"9df" => data <= x"08";
when "00" & x"9e0" => data <= x"0e";
when "00" & x"9e1" => data <= x"c8";
when "00" & x"9e2" => data <= x"e8";
when "00" & x"9e3" => data <= x"e0";
when "00" & x"9e4" => data <= x"08";
when "00" & x"9e5" => data <= x"d0";
when "00" & x"9e6" => data <= x"f5";
when "00" & x"9e7" => data <= x"b5";
when "00" & x"9e8" => data <= x"bd";
when "00" & x"9e9" => data <= x"88";
when "00" & x"9ea" => data <= x"99";
when "00" & x"9eb" => data <= x"08";
when "00" & x"9ec" => data <= x"0f";
when "00" & x"9ed" => data <= x"ca";
when "00" & x"9ee" => data <= x"d0";
when "00" & x"9ef" => data <= x"f7";
when "00" & x"9f0" => data <= x"20";
when "00" & x"9f1" => data <= x"fc";
when "00" & x"9f2" => data <= x"82";
when "00" & x"9f3" => data <= x"98";
when "00" & x"9f4" => data <= x"48";
when "00" & x"9f5" => data <= x"ac";
when "00" & x"9f6" => data <= x"05";
when "00" & x"9f7" => data <= x"0f";
when "00" & x"9f8" => data <= x"20";
when "00" & x"9f9" => data <= x"10";
when "00" & x"9fa" => data <= x"82";
when "00" & x"9fb" => data <= x"8c";
when "00" & x"9fc" => data <= x"05";
when "00" & x"9fd" => data <= x"0f";
when "00" & x"9fe" => data <= x"20";
when "00" & x"9ff" => data <= x"b4";
when "00" & x"a00" => data <= x"8a";
when "00" & x"a01" => data <= x"68";
when "00" & x"a02" => data <= x"a8";
when "00" & x"a03" => data <= x"60";
when "00" & x"a04" => data <= x"20";
when "00" & x"a05" => data <= x"33";
when "00" & x"a06" => data <= x"80";
when "00" & x"a07" => data <= x"be";
when "00" & x"a08" => data <= x"43";
when "00" & x"a09" => data <= x"61";
when "00" & x"a0a" => data <= x"74";
when "00" & x"a0b" => data <= x"61";
when "00" & x"a0c" => data <= x"6c";
when "00" & x"a0d" => data <= x"6f";
when "00" & x"a0e" => data <= x"67";
when "00" & x"a0f" => data <= x"75";
when "00" & x"a10" => data <= x"65";
when "00" & x"a11" => data <= x"20";
when "00" & x"a12" => data <= x"66";
when "00" & x"a13" => data <= x"75";
when "00" & x"a14" => data <= x"6c";
when "00" & x"a15" => data <= x"6c";
when "00" & x"a16" => data <= x"00";
when "00" & x"a17" => data <= x"ad";
when "00" & x"a18" => data <= x"76";
when "00" & x"a19" => data <= x"10";
when "00" & x"a1a" => data <= x"29";
when "00" & x"a1b" => data <= x"03";
when "00" & x"a1c" => data <= x"0a";
when "00" & x"a1d" => data <= x"0a";
when "00" & x"a1e" => data <= x"45";
when "00" & x"a1f" => data <= x"c6";
when "00" & x"a20" => data <= x"29";
when "00" & x"a21" => data <= x"fc";
when "00" & x"a22" => data <= x"45";
when "00" & x"a23" => data <= x"c6";
when "00" & x"a24" => data <= x"0a";
when "00" & x"a25" => data <= x"0a";
when "00" & x"a26" => data <= x"4d";
when "00" & x"a27" => data <= x"74";
when "00" & x"a28" => data <= x"10";
when "00" & x"a29" => data <= x"29";
when "00" & x"a2a" => data <= x"fc";
when "00" & x"a2b" => data <= x"4d";
when "00" & x"a2c" => data <= x"74";
when "00" & x"a2d" => data <= x"10";
when "00" & x"a2e" => data <= x"0a";
when "00" & x"a2f" => data <= x"0a";
when "00" & x"a30" => data <= x"45";
when "00" & x"a31" => data <= x"c4";
when "00" & x"a32" => data <= x"29";
when "00" & x"a33" => data <= x"fc";
when "00" & x"a34" => data <= x"45";
when "00" & x"a35" => data <= x"c4";
when "00" & x"a36" => data <= x"85";
when "00" & x"a37" => data <= x"c4";
when "00" & x"a38" => data <= x"60";
when "00" & x"a39" => data <= x"a9";
when "00" & x"a3a" => data <= x"01";
when "00" & x"a3b" => data <= x"8d";
when "00" & x"a3c" => data <= x"c8";
when "00" & x"a3d" => data <= x"10";
when "00" & x"a3e" => data <= x"60";
when "00" & x"a3f" => data <= x"a9";
when "00" & x"a40" => data <= x"00";
when "00" & x"a41" => data <= x"8d";
when "00" & x"a42" => data <= x"75";
when "00" & x"a43" => data <= x"10";
when "00" & x"a44" => data <= x"a5";
when "00" & x"a45" => data <= x"c4";
when "00" & x"a46" => data <= x"20";
when "00" & x"a47" => data <= x"ff";
when "00" & x"a48" => data <= x"81";
when "00" & x"a49" => data <= x"c9";
when "00" & x"a4a" => data <= x"03";
when "00" & x"a4b" => data <= x"d0";
when "00" & x"a4c" => data <= x"05";
when "00" & x"a4d" => data <= x"a9";
when "00" & x"a4e" => data <= x"ff";
when "00" & x"a4f" => data <= x"8d";
when "00" & x"a50" => data <= x"75";
when "00" & x"a51" => data <= x"10";
when "00" & x"a52" => data <= x"8d";
when "00" & x"a53" => data <= x"74";
when "00" & x"a54" => data <= x"10";
when "00" & x"a55" => data <= x"60";
when "00" & x"a56" => data <= x"a9";
when "00" & x"a57" => data <= x"00";
when "00" & x"a58" => data <= x"8d";
when "00" & x"a59" => data <= x"77";
when "00" & x"a5a" => data <= x"10";
when "00" & x"a5b" => data <= x"a5";
when "00" & x"a5c" => data <= x"c4";
when "00" & x"a5d" => data <= x"20";
when "00" & x"a5e" => data <= x"fb";
when "00" & x"a5f" => data <= x"81";
when "00" & x"a60" => data <= x"c9";
when "00" & x"a61" => data <= x"03";
when "00" & x"a62" => data <= x"d0";
when "00" & x"a63" => data <= x"05";
when "00" & x"a64" => data <= x"a9";
when "00" & x"a65" => data <= x"ff";
when "00" & x"a66" => data <= x"8d";
when "00" & x"a67" => data <= x"77";
when "00" & x"a68" => data <= x"10";
when "00" & x"a69" => data <= x"8d";
when "00" & x"a6a" => data <= x"76";
when "00" & x"a6b" => data <= x"10";
when "00" & x"a6c" => data <= x"60";
when "00" & x"a6d" => data <= x"20";
when "00" & x"a6e" => data <= x"62";
when "00" & x"a6f" => data <= x"82";
when "00" & x"a70" => data <= x"20";
when "00" & x"a71" => data <= x"bf";
when "00" & x"a72" => data <= x"86";
when "00" & x"a73" => data <= x"d0";
when "00" & x"a74" => data <= x"03";
when "00" & x"a75" => data <= x"4c";
when "00" & x"a76" => data <= x"06";
when "00" & x"a77" => data <= x"9a";
when "00" & x"a78" => data <= x"20";
when "00" & x"a79" => data <= x"fe";
when "00" & x"a7a" => data <= x"80";
when "00" & x"a7b" => data <= x"98";
when "00" & x"a7c" => data <= x"48";
when "00" & x"a7d" => data <= x"20";
when "00" & x"a7e" => data <= x"96";
when "00" & x"a7f" => data <= x"82";
when "00" & x"a80" => data <= x"b0";
when "00" & x"a81" => data <= x"03";
when "00" & x"a82" => data <= x"4c";
when "00" & x"a83" => data <= x"76";
when "00" & x"a84" => data <= x"82";
when "00" & x"a85" => data <= x"20";
when "00" & x"a86" => data <= x"4c";
when "00" & x"a87" => data <= x"98";
when "00" & x"a88" => data <= x"84";
when "00" & x"a89" => data <= x"b3";
when "00" & x"a8a" => data <= x"68";
when "00" & x"a8b" => data <= x"a8";
when "00" & x"a8c" => data <= x"20";
when "00" & x"a8d" => data <= x"bf";
when "00" & x"a8e" => data <= x"86";
when "00" & x"a8f" => data <= x"f0";
when "00" & x"a90" => data <= x"e4";
when "00" & x"a91" => data <= x"20";
when "00" & x"a92" => data <= x"fe";
when "00" & x"a93" => data <= x"80";
when "00" & x"a94" => data <= x"20";
when "00" & x"a95" => data <= x"96";
when "00" & x"a96" => data <= x"82";
when "00" & x"a97" => data <= x"90";
when "00" & x"a98" => data <= x"0b";
when "00" & x"a99" => data <= x"20";
when "00" & x"a9a" => data <= x"2b";
when "00" & x"a9b" => data <= x"80";
when "00" & x"a9c" => data <= x"c4";
when "00" & x"a9d" => data <= x"65";
when "00" & x"a9e" => data <= x"78";
when "00" & x"a9f" => data <= x"69";
when "00" & x"aa0" => data <= x"73";
when "00" & x"aa1" => data <= x"74";
when "00" & x"aa2" => data <= x"73";
when "00" & x"aa3" => data <= x"00";
when "00" & x"aa4" => data <= x"a4";
when "00" & x"aa5" => data <= x"b3";
when "00" & x"aa6" => data <= x"20";
when "00" & x"aa7" => data <= x"10";
when "00" & x"aa8" => data <= x"82";
when "00" & x"aa9" => data <= x"a2";
when "00" & x"aaa" => data <= x"07";
when "00" & x"aab" => data <= x"b5";
when "00" & x"aac" => data <= x"c7";
when "00" & x"aad" => data <= x"99";
when "00" & x"aae" => data <= x"07";
when "00" & x"aaf" => data <= x"0e";
when "00" & x"ab0" => data <= x"88";
when "00" & x"ab1" => data <= x"ca";
when "00" & x"ab2" => data <= x"10";
when "00" & x"ab3" => data <= x"f7";
when "00" & x"ab4" => data <= x"18";
when "00" & x"ab5" => data <= x"f8";
when "00" & x"ab6" => data <= x"ad";
when "00" & x"ab7" => data <= x"04";
when "00" & x"ab8" => data <= x"0f";
when "00" & x"ab9" => data <= x"69";
when "00" & x"aba" => data <= x"01";
when "00" & x"abb" => data <= x"d8";
when "00" & x"abc" => data <= x"8d";
when "00" & x"abd" => data <= x"04";
when "00" & x"abe" => data <= x"0f";
when "00" & x"abf" => data <= x"4c";
when "00" & x"ac0" => data <= x"55";
when "00" & x"ac1" => data <= x"af";
when "00" & x"ac2" => data <= x"a9";
when "00" & x"ac3" => data <= x"ff";
when "00" & x"ac4" => data <= x"20";
when "00" & x"ac5" => data <= x"9e";
when "00" & x"ac6" => data <= x"06";
when "00" & x"ac7" => data <= x"ad";
when "00" & x"ac8" => data <= x"e3";
when "00" & x"ac9" => data <= x"fe";
when "00" & x"aca" => data <= x"a9";
when "00" & x"acb" => data <= x"00";
when "00" & x"acc" => data <= x"20";
when "00" & x"acd" => data <= x"95";
when "00" & x"ace" => data <= x"06";
when "00" & x"acf" => data <= x"a8";
when "00" & x"ad0" => data <= x"b1";
when "00" & x"ad1" => data <= x"fd";
when "00" & x"ad2" => data <= x"20";
when "00" & x"ad3" => data <= x"95";
when "00" & x"ad4" => data <= x"06";
when "00" & x"ad5" => data <= x"c8";
when "00" & x"ad6" => data <= x"b1";
when "00" & x"ad7" => data <= x"fd";
when "00" & x"ad8" => data <= x"20";
when "00" & x"ad9" => data <= x"95";
when "00" & x"ada" => data <= x"06";
when "00" & x"adb" => data <= x"aa";
when "00" & x"adc" => data <= x"d0";
when "00" & x"add" => data <= x"f7";
when "00" & x"ade" => data <= x"a2";
when "00" & x"adf" => data <= x"ff";
when "00" & x"ae0" => data <= x"9a";
when "00" & x"ae1" => data <= x"58";
when "00" & x"ae2" => data <= x"2c";
when "00" & x"ae3" => data <= x"e0";
when "00" & x"ae4" => data <= x"fe";
when "00" & x"ae5" => data <= x"10";
when "00" & x"ae6" => data <= x"06";
when "00" & x"ae7" => data <= x"ad";
when "00" & x"ae8" => data <= x"e1";
when "00" & x"ae9" => data <= x"fe";
when "00" & x"aea" => data <= x"20";
when "00" & x"aeb" => data <= x"ee";
when "00" & x"aec" => data <= x"ff";
when "00" & x"aed" => data <= x"2c";
when "00" & x"aee" => data <= x"e2";
when "00" & x"aef" => data <= x"fe";
when "00" & x"af0" => data <= x"10";
when "00" & x"af1" => data <= x"f0";
when "00" & x"af2" => data <= x"2c";
when "00" & x"af3" => data <= x"e0";
when "00" & x"af4" => data <= x"fe";
when "00" & x"af5" => data <= x"30";
when "00" & x"af6" => data <= x"f0";
when "00" & x"af7" => data <= x"ae";
when "00" & x"af8" => data <= x"e3";
when "00" & x"af9" => data <= x"fe";
when "00" & x"afa" => data <= x"86";
when "00" & x"afb" => data <= x"51";
when "00" & x"afc" => data <= x"6c";
when "00" & x"afd" => data <= x"00";
when "00" & x"afe" => data <= x"05";
when "00" & x"aff" => data <= x"00";
when "00" & x"b00" => data <= x"80";
when "00" & x"b01" => data <= x"00";
when "00" & x"b02" => data <= x"00";
when "00" & x"b03" => data <= x"4c";
when "00" & x"b04" => data <= x"84";
when "00" & x"b05" => data <= x"04";
when "00" & x"b06" => data <= x"4c";
when "00" & x"b07" => data <= x"a7";
when "00" & x"b08" => data <= x"06";
when "00" & x"b09" => data <= x"c9";
when "00" & x"b0a" => data <= x"80";
when "00" & x"b0b" => data <= x"90";
when "00" & x"b0c" => data <= x"2b";
when "00" & x"b0d" => data <= x"c9";
when "00" & x"b0e" => data <= x"c0";
when "00" & x"b0f" => data <= x"b0";
when "00" & x"b10" => data <= x"1a";
when "00" & x"b11" => data <= x"09";
when "00" & x"b12" => data <= x"40";
when "00" & x"b13" => data <= x"c5";
when "00" & x"b14" => data <= x"15";
when "00" & x"b15" => data <= x"d0";
when "00" & x"b16" => data <= x"20";
when "00" & x"b17" => data <= x"08";
when "00" & x"b18" => data <= x"78";
when "00" & x"b19" => data <= x"a9";
when "00" & x"b1a" => data <= x"05";
when "00" & x"b1b" => data <= x"20";
when "00" & x"b1c" => data <= x"9e";
when "00" & x"b1d" => data <= x"06";
when "00" & x"b1e" => data <= x"a5";
when "00" & x"b1f" => data <= x"15";
when "00" & x"b20" => data <= x"20";
when "00" & x"b21" => data <= x"9e";
when "00" & x"b22" => data <= x"06";
when "00" & x"b23" => data <= x"28";
when "00" & x"b24" => data <= x"a9";
when "00" & x"b25" => data <= x"80";
when "00" & x"b26" => data <= x"85";
when "00" & x"b27" => data <= x"15";
when "00" & x"b28" => data <= x"85";
when "00" & x"b29" => data <= x"14";
when "00" & x"b2a" => data <= x"60";
when "00" & x"b2b" => data <= x"06";
when "00" & x"b2c" => data <= x"14";
when "00" & x"b2d" => data <= x"b0";
when "00" & x"b2e" => data <= x"06";
when "00" & x"b2f" => data <= x"c5";
when "00" & x"b30" => data <= x"15";
when "00" & x"b31" => data <= x"f0";
when "00" & x"b32" => data <= x"04";
when "00" & x"b33" => data <= x"18";
when "00" & x"b34" => data <= x"60";
when "00" & x"b35" => data <= x"85";
when "00" & x"b36" => data <= x"15";
when "00" & x"b37" => data <= x"60";
when "00" & x"b38" => data <= x"08";
when "00" & x"b39" => data <= x"78";
when "00" & x"b3a" => data <= x"84";
when "00" & x"b3b" => data <= x"13";
when "00" & x"b3c" => data <= x"86";
when "00" & x"b3d" => data <= x"12";
when "00" & x"b3e" => data <= x"20";
when "00" & x"b3f" => data <= x"9e";
when "00" & x"b40" => data <= x"06";
when "00" & x"b41" => data <= x"aa";
when "00" & x"b42" => data <= x"a0";
when "00" & x"b43" => data <= x"03";
when "00" & x"b44" => data <= x"a5";
when "00" & x"b45" => data <= x"15";
when "00" & x"b46" => data <= x"20";
when "00" & x"b47" => data <= x"9e";
when "00" & x"b48" => data <= x"06";
when "00" & x"b49" => data <= x"b1";
when "00" & x"b4a" => data <= x"12";
when "00" & x"b4b" => data <= x"20";
when "00" & x"b4c" => data <= x"9e";
when "00" & x"b4d" => data <= x"06";
when "00" & x"b4e" => data <= x"88";
when "00" & x"b4f" => data <= x"10";
when "00" & x"b50" => data <= x"f8";
when "00" & x"b51" => data <= x"a0";
when "00" & x"b52" => data <= x"18";
when "00" & x"b53" => data <= x"8c";
when "00" & x"b54" => data <= x"e0";
when "00" & x"b55" => data <= x"fe";
when "00" & x"b56" => data <= x"bd";
when "00" & x"b57" => data <= x"18";
when "00" & x"b58" => data <= x"05";
when "00" & x"b59" => data <= x"8d";
when "00" & x"b5a" => data <= x"e0";
when "00" & x"b5b" => data <= x"fe";
when "00" & x"b5c" => data <= x"4a";
when "00" & x"b5d" => data <= x"4a";
when "00" & x"b5e" => data <= x"90";
when "00" & x"b5f" => data <= x"06";
when "00" & x"b60" => data <= x"2c";
when "00" & x"b61" => data <= x"e5";
when "00" & x"b62" => data <= x"fe";
when "00" & x"b63" => data <= x"2c";
when "00" & x"b64" => data <= x"e5";
when "00" & x"b65" => data <= x"fe";
when "00" & x"b66" => data <= x"20";
when "00" & x"b67" => data <= x"9e";
when "00" & x"b68" => data <= x"06";
when "00" & x"b69" => data <= x"2c";
when "00" & x"b6a" => data <= x"e6";
when "00" & x"b6b" => data <= x"fe";
when "00" & x"b6c" => data <= x"50";
when "00" & x"b6d" => data <= x"fb";
when "00" & x"b6e" => data <= x"b0";
when "00" & x"b6f" => data <= x"0d";
when "00" & x"b70" => data <= x"e0";
when "00" & x"b71" => data <= x"04";
when "00" & x"b72" => data <= x"d0";
when "00" & x"b73" => data <= x"11";
when "00" & x"b74" => data <= x"20";
when "00" & x"b75" => data <= x"14";
when "00" & x"b76" => data <= x"04";
when "00" & x"b77" => data <= x"20";
when "00" & x"b78" => data <= x"95";
when "00" & x"b79" => data <= x"06";
when "00" & x"b7a" => data <= x"4c";
when "00" & x"b7b" => data <= x"32";
when "00" & x"b7c" => data <= x"00";
when "00" & x"b7d" => data <= x"4a";
when "00" & x"b7e" => data <= x"90";
when "00" & x"b7f" => data <= x"05";
when "00" & x"b80" => data <= x"a0";
when "00" & x"b81" => data <= x"88";
when "00" & x"b82" => data <= x"8c";
when "00" & x"b83" => data <= x"e0";
when "00" & x"b84" => data <= x"fe";
when "00" & x"b85" => data <= x"28";
when "00" & x"b86" => data <= x"60";
when "00" & x"b87" => data <= x"58";
when "00" & x"b88" => data <= x"b0";
when "00" & x"b89" => data <= x"11";
when "00" & x"b8a" => data <= x"d0";
when "00" & x"b8b" => data <= x"03";
when "00" & x"b8c" => data <= x"4c";
when "00" & x"b8d" => data <= x"9c";
when "00" & x"b8e" => data <= x"05";
when "00" & x"b8f" => data <= x"a2";
when "00" & x"b90" => data <= x"00";
when "00" & x"b91" => data <= x"a0";
when "00" & x"b92" => data <= x"ff";
when "00" & x"b93" => data <= x"a9";
when "00" & x"b94" => data <= x"fd";
when "00" & x"b95" => data <= x"20";
when "00" & x"b96" => data <= x"f4";
when "00" & x"b97" => data <= x"ff";
when "00" & x"b98" => data <= x"8a";
when "00" & x"b99" => data <= x"f0";
when "00" & x"b9a" => data <= x"d9";
when "00" & x"b9b" => data <= x"a9";
when "00" & x"b9c" => data <= x"ff";
when "00" & x"b9d" => data <= x"20";
when "00" & x"b9e" => data <= x"06";
when "00" & x"b9f" => data <= x"04";
when "00" & x"ba0" => data <= x"90";
when "00" & x"ba1" => data <= x"f9";
when "00" & x"ba2" => data <= x"20";
when "00" & x"ba3" => data <= x"d2";
when "00" & x"ba4" => data <= x"04";
when "00" & x"ba5" => data <= x"a9";
when "00" & x"ba6" => data <= x"07";
when "00" & x"ba7" => data <= x"20";
when "00" & x"ba8" => data <= x"cb";
when "00" & x"ba9" => data <= x"04";
when "00" & x"baa" => data <= x"a0";
when "00" & x"bab" => data <= x"00";
when "00" & x"bac" => data <= x"84";
when "00" & x"bad" => data <= x"00";
when "00" & x"bae" => data <= x"b1";
when "00" & x"baf" => data <= x"00";
when "00" & x"bb0" => data <= x"8d";
when "00" & x"bb1" => data <= x"e5";
when "00" & x"bb2" => data <= x"fe";
when "00" & x"bb3" => data <= x"ea";
when "00" & x"bb4" => data <= x"ea";
when "00" & x"bb5" => data <= x"ea";
when "00" & x"bb6" => data <= x"c8";
when "00" & x"bb7" => data <= x"d0";
when "00" & x"bb8" => data <= x"f5";
when "00" & x"bb9" => data <= x"e6";
when "00" & x"bba" => data <= x"54";
when "00" & x"bbb" => data <= x"d0";
when "00" & x"bbc" => data <= x"06";
when "00" & x"bbd" => data <= x"e6";
when "00" & x"bbe" => data <= x"55";
when "00" & x"bbf" => data <= x"d0";
when "00" & x"bc0" => data <= x"02";
when "00" & x"bc1" => data <= x"e6";
when "00" & x"bc2" => data <= x"56";
when "00" & x"bc3" => data <= x"e6";
when "00" & x"bc4" => data <= x"01";
when "00" & x"bc5" => data <= x"24";
when "00" & x"bc6" => data <= x"01";
when "00" & x"bc7" => data <= x"50";
when "00" & x"bc8" => data <= x"dc";
when "00" & x"bc9" => data <= x"20";
when "00" & x"bca" => data <= x"d2";
when "00" & x"bcb" => data <= x"04";
when "00" & x"bcc" => data <= x"a9";
when "00" & x"bcd" => data <= x"04";
when "00" & x"bce" => data <= x"a0";
when "00" & x"bcf" => data <= x"00";
when "00" & x"bd0" => data <= x"a2";
when "00" & x"bd1" => data <= x"53";
when "00" & x"bd2" => data <= x"4c";
when "00" & x"bd3" => data <= x"06";
when "00" & x"bd4" => data <= x"04";
when "00" & x"bd5" => data <= x"a9";
when "00" & x"bd6" => data <= x"80";
when "00" & x"bd7" => data <= x"85";
when "00" & x"bd8" => data <= x"54";
when "00" & x"bd9" => data <= x"85";
when "00" & x"bda" => data <= x"01";
when "00" & x"bdb" => data <= x"a9";
when "00" & x"bdc" => data <= x"20";
when "00" & x"bdd" => data <= x"2d";
when "00" & x"bde" => data <= x"06";
when "00" & x"bdf" => data <= x"80";
when "00" & x"be0" => data <= x"a8";
when "00" & x"be1" => data <= x"84";
when "00" & x"be2" => data <= x"53";
when "00" & x"be3" => data <= x"f0";
when "00" & x"be4" => data <= x"19";
when "00" & x"be5" => data <= x"ae";
when "00" & x"be6" => data <= x"07";
when "00" & x"be7" => data <= x"80";
when "00" & x"be8" => data <= x"e8";
when "00" & x"be9" => data <= x"bd";
when "00" & x"bea" => data <= x"00";
when "00" & x"beb" => data <= x"80";
when "00" & x"bec" => data <= x"d0";
when "00" & x"bed" => data <= x"fa";
when "00" & x"bee" => data <= x"bd";
when "00" & x"bef" => data <= x"01";
when "00" & x"bf0" => data <= x"80";
when "00" & x"bf1" => data <= x"85";
when "00" & x"bf2" => data <= x"53";
when "00" & x"bf3" => data <= x"bd";
when "00" & x"bf4" => data <= x"02";
when "00" & x"bf5" => data <= x"80";
when "00" & x"bf6" => data <= x"85";
when "00" & x"bf7" => data <= x"54";
when "00" & x"bf8" => data <= x"bc";
when "00" & x"bf9" => data <= x"03";
when "00" & x"bfa" => data <= x"80";
when "00" & x"bfb" => data <= x"bd";
when "00" & x"bfc" => data <= x"04";
when "00" & x"bfd" => data <= x"80";
when "00" & x"bfe" => data <= x"85";
when "00" & x"bff" => data <= x"56";
when "00" & x"c00" => data <= x"84";
when "00" & x"c01" => data <= x"55";
when "00" & x"c02" => data <= x"60";
when "00" & x"c03" => data <= x"37";
when "00" & x"c04" => data <= x"05";
when "00" & x"c05" => data <= x"96";
when "00" & x"c06" => data <= x"05";
when "00" & x"c07" => data <= x"f2";
when "00" & x"c08" => data <= x"05";
when "00" & x"c09" => data <= x"07";
when "00" & x"c0a" => data <= x"06";
when "00" & x"c0b" => data <= x"27";
when "00" & x"c0c" => data <= x"06";
when "00" & x"c0d" => data <= x"68";
when "00" & x"c0e" => data <= x"06";
when "00" & x"c0f" => data <= x"5e";
when "00" & x"c10" => data <= x"05";
when "00" & x"c11" => data <= x"2d";
when "00" & x"c12" => data <= x"05";
when "00" & x"c13" => data <= x"20";
when "00" & x"c14" => data <= x"05";
when "00" & x"c15" => data <= x"42";
when "00" & x"c16" => data <= x"05";
when "00" & x"c17" => data <= x"a9";
when "00" & x"c18" => data <= x"05";
when "00" & x"c19" => data <= x"d1";
when "00" & x"c1a" => data <= x"05";
when "00" & x"c1b" => data <= x"86";
when "00" & x"c1c" => data <= x"88";
when "00" & x"c1d" => data <= x"96";
when "00" & x"c1e" => data <= x"98";
when "00" & x"c1f" => data <= x"18";
when "00" & x"c20" => data <= x"18";
when "00" & x"c21" => data <= x"82";
when "00" & x"c22" => data <= x"18";
when "00" & x"c23" => data <= x"20";
when "00" & x"c24" => data <= x"c5";
when "00" & x"c25" => data <= x"06";
when "00" & x"c26" => data <= x"a8";
when "00" & x"c27" => data <= x"20";
when "00" & x"c28" => data <= x"c5";
when "00" & x"c29" => data <= x"06";
when "00" & x"c2a" => data <= x"20";
when "00" & x"c2b" => data <= x"d4";
when "00" & x"c2c" => data <= x"ff";
when "00" & x"c2d" => data <= x"4c";
when "00" & x"c2e" => data <= x"9c";
when "00" & x"c2f" => data <= x"05";
when "00" & x"c30" => data <= x"20";
when "00" & x"c31" => data <= x"c5";
when "00" & x"c32" => data <= x"06";
when "00" & x"c33" => data <= x"a8";
when "00" & x"c34" => data <= x"20";
when "00" & x"c35" => data <= x"d7";
when "00" & x"c36" => data <= x"ff";
when "00" & x"c37" => data <= x"4c";
when "00" & x"c38" => data <= x"3a";
when "00" & x"c39" => data <= x"05";
when "00" & x"c3a" => data <= x"20";
when "00" & x"c3b" => data <= x"e0";
when "00" & x"c3c" => data <= x"ff";
when "00" & x"c3d" => data <= x"6a";
when "00" & x"c3e" => data <= x"20";
when "00" & x"c3f" => data <= x"95";
when "00" & x"c40" => data <= x"06";
when "00" & x"c41" => data <= x"2a";
when "00" & x"c42" => data <= x"4c";
when "00" & x"c43" => data <= x"9e";
when "00" & x"c44" => data <= x"05";
when "00" & x"c45" => data <= x"20";
when "00" & x"c46" => data <= x"c5";
when "00" & x"c47" => data <= x"06";
when "00" & x"c48" => data <= x"f0";
when "00" & x"c49" => data <= x"0b";
when "00" & x"c4a" => data <= x"48";
when "00" & x"c4b" => data <= x"20";
when "00" & x"c4c" => data <= x"82";
when "00" & x"c4d" => data <= x"05";
when "00" & x"c4e" => data <= x"68";
when "00" & x"c4f" => data <= x"20";
when "00" & x"c50" => data <= x"ce";
when "00" & x"c51" => data <= x"ff";
when "00" & x"c52" => data <= x"4c";
when "00" & x"c53" => data <= x"9e";
when "00" & x"c54" => data <= x"05";
when "00" & x"c55" => data <= x"20";
when "00" & x"c56" => data <= x"c5";
when "00" & x"c57" => data <= x"06";
when "00" & x"c58" => data <= x"a8";
when "00" & x"c59" => data <= x"a9";
when "00" & x"c5a" => data <= x"00";
when "00" & x"c5b" => data <= x"20";
when "00" & x"c5c" => data <= x"ce";
when "00" & x"c5d" => data <= x"ff";
when "00" & x"c5e" => data <= x"4c";
when "00" & x"c5f" => data <= x"9c";
when "00" & x"c60" => data <= x"05";
when "00" & x"c61" => data <= x"20";
when "00" & x"c62" => data <= x"c5";
when "00" & x"c63" => data <= x"06";
when "00" & x"c64" => data <= x"a8";
when "00" & x"c65" => data <= x"a2";
when "00" & x"c66" => data <= x"04";
when "00" & x"c67" => data <= x"20";
when "00" & x"c68" => data <= x"c5";
when "00" & x"c69" => data <= x"06";
when "00" & x"c6a" => data <= x"95";
when "00" & x"c6b" => data <= x"ff";
when "00" & x"c6c" => data <= x"ca";
when "00" & x"c6d" => data <= x"d0";
when "00" & x"c6e" => data <= x"f8";
when "00" & x"c6f" => data <= x"20";
when "00" & x"c70" => data <= x"c5";
when "00" & x"c71" => data <= x"06";
when "00" & x"c72" => data <= x"20";
when "00" & x"c73" => data <= x"da";
when "00" & x"c74" => data <= x"ff";
when "00" & x"c75" => data <= x"20";
when "00" & x"c76" => data <= x"95";
when "00" & x"c77" => data <= x"06";
when "00" & x"c78" => data <= x"a2";
when "00" & x"c79" => data <= x"03";
when "00" & x"c7a" => data <= x"b5";
when "00" & x"c7b" => data <= x"00";
when "00" & x"c7c" => data <= x"20";
when "00" & x"c7d" => data <= x"95";
when "00" & x"c7e" => data <= x"06";
when "00" & x"c7f" => data <= x"ca";
when "00" & x"c80" => data <= x"10";
when "00" & x"c81" => data <= x"f8";
when "00" & x"c82" => data <= x"4c";
when "00" & x"c83" => data <= x"36";
when "00" & x"c84" => data <= x"00";
when "00" & x"c85" => data <= x"a2";
when "00" & x"c86" => data <= x"00";
when "00" & x"c87" => data <= x"a0";
when "00" & x"c88" => data <= x"00";
when "00" & x"c89" => data <= x"20";
when "00" & x"c8a" => data <= x"c5";
when "00" & x"c8b" => data <= x"06";
when "00" & x"c8c" => data <= x"99";
when "00" & x"c8d" => data <= x"00";
when "00" & x"c8e" => data <= x"07";
when "00" & x"c8f" => data <= x"c8";
when "00" & x"c90" => data <= x"f0";
when "00" & x"c91" => data <= x"04";
when "00" & x"c92" => data <= x"c9";
when "00" & x"c93" => data <= x"0d";
when "00" & x"c94" => data <= x"d0";
when "00" & x"c95" => data <= x"f3";
when "00" & x"c96" => data <= x"a0";
when "00" & x"c97" => data <= x"07";
when "00" & x"c98" => data <= x"60";
when "00" & x"c99" => data <= x"20";
when "00" & x"c9a" => data <= x"82";
when "00" & x"c9b" => data <= x"05";
when "00" & x"c9c" => data <= x"20";
when "00" & x"c9d" => data <= x"f7";
when "00" & x"c9e" => data <= x"ff";
when "00" & x"c9f" => data <= x"a9";
when "00" & x"ca0" => data <= x"7f";
when "00" & x"ca1" => data <= x"2c";
when "00" & x"ca2" => data <= x"e2";
when "00" & x"ca3" => data <= x"fe";
when "00" & x"ca4" => data <= x"50";
when "00" & x"ca5" => data <= x"fb";
when "00" & x"ca6" => data <= x"8d";
when "00" & x"ca7" => data <= x"e3";
when "00" & x"ca8" => data <= x"fe";
when "00" & x"ca9" => data <= x"4c";
when "00" & x"caa" => data <= x"36";
when "00" & x"cab" => data <= x"00";
when "00" & x"cac" => data <= x"a2";
when "00" & x"cad" => data <= x"10";
when "00" & x"cae" => data <= x"20";
when "00" & x"caf" => data <= x"c5";
when "00" & x"cb0" => data <= x"06";
when "00" & x"cb1" => data <= x"95";
when "00" & x"cb2" => data <= x"01";
when "00" & x"cb3" => data <= x"ca";
when "00" & x"cb4" => data <= x"d0";
when "00" & x"cb5" => data <= x"f8";
when "00" & x"cb6" => data <= x"20";
when "00" & x"cb7" => data <= x"82";
when "00" & x"cb8" => data <= x"05";
when "00" & x"cb9" => data <= x"86";
when "00" & x"cba" => data <= x"00";
when "00" & x"cbb" => data <= x"84";
when "00" & x"cbc" => data <= x"01";
when "00" & x"cbd" => data <= x"a0";
when "00" & x"cbe" => data <= x"00";
when "00" & x"cbf" => data <= x"20";
when "00" & x"cc0" => data <= x"c5";
when "00" & x"cc1" => data <= x"06";
when "00" & x"cc2" => data <= x"20";
when "00" & x"cc3" => data <= x"dd";
when "00" & x"cc4" => data <= x"ff";
when "00" & x"cc5" => data <= x"20";
when "00" & x"cc6" => data <= x"95";
when "00" & x"cc7" => data <= x"06";
when "00" & x"cc8" => data <= x"a2";
when "00" & x"cc9" => data <= x"10";
when "00" & x"cca" => data <= x"b5";
when "00" & x"ccb" => data <= x"01";
when "00" & x"ccc" => data <= x"20";
when "00" & x"ccd" => data <= x"95";
when "00" & x"cce" => data <= x"06";
when "00" & x"ccf" => data <= x"ca";
when "00" & x"cd0" => data <= x"d0";
when "00" & x"cd1" => data <= x"f8";
when "00" & x"cd2" => data <= x"f0";
when "00" & x"cd3" => data <= x"d5";
when "00" & x"cd4" => data <= x"a2";
when "00" & x"cd5" => data <= x"0d";
when "00" & x"cd6" => data <= x"20";
when "00" & x"cd7" => data <= x"c5";
when "00" & x"cd8" => data <= x"06";
when "00" & x"cd9" => data <= x"95";
when "00" & x"cda" => data <= x"ff";
when "00" & x"cdb" => data <= x"ca";
when "00" & x"cdc" => data <= x"d0";
when "00" & x"cdd" => data <= x"f8";
when "00" & x"cde" => data <= x"20";
when "00" & x"cdf" => data <= x"c5";
when "00" & x"ce0" => data <= x"06";
when "00" & x"ce1" => data <= x"a0";
when "00" & x"ce2" => data <= x"00";
when "00" & x"ce3" => data <= x"20";
when "00" & x"ce4" => data <= x"d1";
when "00" & x"ce5" => data <= x"ff";
when "00" & x"ce6" => data <= x"48";
when "00" & x"ce7" => data <= x"a2";
when "00" & x"ce8" => data <= x"0c";
when "00" & x"ce9" => data <= x"b5";
when "00" & x"cea" => data <= x"00";
when "00" & x"ceb" => data <= x"20";
when "00" & x"cec" => data <= x"95";
when "00" & x"ced" => data <= x"06";
when "00" & x"cee" => data <= x"ca";
when "00" & x"cef" => data <= x"10";
when "00" & x"cf0" => data <= x"f8";
when "00" & x"cf1" => data <= x"68";
when "00" & x"cf2" => data <= x"4c";
when "00" & x"cf3" => data <= x"3a";
when "00" & x"cf4" => data <= x"05";
when "00" & x"cf5" => data <= x"20";
when "00" & x"cf6" => data <= x"c5";
when "00" & x"cf7" => data <= x"06";
when "00" & x"cf8" => data <= x"aa";
when "00" & x"cf9" => data <= x"20";
when "00" & x"cfa" => data <= x"c5";
when "00" & x"cfb" => data <= x"06";
when "00" & x"cfc" => data <= x"20";
when "00" & x"cfd" => data <= x"f4";
when "00" & x"cfe" => data <= x"ff";
when "00" & x"cff" => data <= x"2c";
when "00" & x"d00" => data <= x"e2";
when "00" & x"d01" => data <= x"fe";
when "00" & x"d02" => data <= x"50";
when "00" & x"d03" => data <= x"fb";
when "00" & x"d04" => data <= x"8e";
when "00" & x"d05" => data <= x"e3";
when "00" & x"d06" => data <= x"fe";
when "00" & x"d07" => data <= x"4c";
when "00" & x"d08" => data <= x"36";
when "00" & x"d09" => data <= x"00";
when "00" & x"d0a" => data <= x"20";
when "00" & x"d0b" => data <= x"c5";
when "00" & x"d0c" => data <= x"06";
when "00" & x"d0d" => data <= x"aa";
when "00" & x"d0e" => data <= x"20";
when "00" & x"d0f" => data <= x"c5";
when "00" & x"d10" => data <= x"06";
when "00" & x"d11" => data <= x"a8";
when "00" & x"d12" => data <= x"20";
when "00" & x"d13" => data <= x"c5";
when "00" & x"d14" => data <= x"06";
when "00" & x"d15" => data <= x"20";
when "00" & x"d16" => data <= x"f4";
when "00" & x"d17" => data <= x"ff";
when "00" & x"d18" => data <= x"49";
when "00" & x"d19" => data <= x"9d";
when "00" & x"d1a" => data <= x"f0";
when "00" & x"d1b" => data <= x"eb";
when "00" & x"d1c" => data <= x"6a";
when "00" & x"d1d" => data <= x"20";
when "00" & x"d1e" => data <= x"95";
when "00" & x"d1f" => data <= x"06";
when "00" & x"d20" => data <= x"2c";
when "00" & x"d21" => data <= x"e2";
when "00" & x"d22" => data <= x"fe";
when "00" & x"d23" => data <= x"50";
when "00" & x"d24" => data <= x"fb";
when "00" & x"d25" => data <= x"8c";
when "00" & x"d26" => data <= x"e3";
when "00" & x"d27" => data <= x"fe";
when "00" & x"d28" => data <= x"70";
when "00" & x"d29" => data <= x"d5";
when "00" & x"d2a" => data <= x"20";
when "00" & x"d2b" => data <= x"c5";
when "00" & x"d2c" => data <= x"06";
when "00" & x"d2d" => data <= x"a8";
when "00" & x"d2e" => data <= x"2c";
when "00" & x"d2f" => data <= x"e2";
when "00" & x"d30" => data <= x"fe";
when "00" & x"d31" => data <= x"10";
when "00" & x"d32" => data <= x"fb";
when "00" & x"d33" => data <= x"ae";
when "00" & x"d34" => data <= x"e3";
when "00" & x"d35" => data <= x"fe";
when "00" & x"d36" => data <= x"ca";
when "00" & x"d37" => data <= x"30";
when "00" & x"d38" => data <= x"0f";
when "00" & x"d39" => data <= x"2c";
when "00" & x"d3a" => data <= x"e2";
when "00" & x"d3b" => data <= x"fe";
when "00" & x"d3c" => data <= x"10";
when "00" & x"d3d" => data <= x"fb";
when "00" & x"d3e" => data <= x"ad";
when "00" & x"d3f" => data <= x"e3";
when "00" & x"d40" => data <= x"fe";
when "00" & x"d41" => data <= x"9d";
when "00" & x"d42" => data <= x"28";
when "00" & x"d43" => data <= x"01";
when "00" & x"d44" => data <= x"ca";
when "00" & x"d45" => data <= x"10";
when "00" & x"d46" => data <= x"f2";
when "00" & x"d47" => data <= x"98";
when "00" & x"d48" => data <= x"a2";
when "00" & x"d49" => data <= x"28";
when "00" & x"d4a" => data <= x"a0";
when "00" & x"d4b" => data <= x"01";
when "00" & x"d4c" => data <= x"20";
when "00" & x"d4d" => data <= x"f1";
when "00" & x"d4e" => data <= x"ff";
when "00" & x"d4f" => data <= x"2c";
when "00" & x"d50" => data <= x"e2";
when "00" & x"d51" => data <= x"fe";
when "00" & x"d52" => data <= x"10";
when "00" & x"d53" => data <= x"fb";
when "00" & x"d54" => data <= x"ae";
when "00" & x"d55" => data <= x"e3";
when "00" & x"d56" => data <= x"fe";
when "00" & x"d57" => data <= x"ca";
when "00" & x"d58" => data <= x"30";
when "00" & x"d59" => data <= x"0e";
when "00" & x"d5a" => data <= x"bc";
when "00" & x"d5b" => data <= x"28";
when "00" & x"d5c" => data <= x"01";
when "00" & x"d5d" => data <= x"2c";
when "00" & x"d5e" => data <= x"e2";
when "00" & x"d5f" => data <= x"fe";
when "00" & x"d60" => data <= x"50";
when "00" & x"d61" => data <= x"fb";
when "00" & x"d62" => data <= x"8c";
when "00" & x"d63" => data <= x"e3";
when "00" & x"d64" => data <= x"fe";
when "00" & x"d65" => data <= x"ca";
when "00" & x"d66" => data <= x"10";
when "00" & x"d67" => data <= x"f2";
when "00" & x"d68" => data <= x"4c";
when "00" & x"d69" => data <= x"36";
when "00" & x"d6a" => data <= x"00";
when "00" & x"d6b" => data <= x"a2";
when "00" & x"d6c" => data <= x"04";
when "00" & x"d6d" => data <= x"20";
when "00" & x"d6e" => data <= x"c5";
when "00" & x"d6f" => data <= x"06";
when "00" & x"d70" => data <= x"95";
when "00" & x"d71" => data <= x"00";
when "00" & x"d72" => data <= x"ca";
when "00" & x"d73" => data <= x"10";
when "00" & x"d74" => data <= x"f8";
when "00" & x"d75" => data <= x"e8";
when "00" & x"d76" => data <= x"a0";
when "00" & x"d77" => data <= x"00";
when "00" & x"d78" => data <= x"8a";
when "00" & x"d79" => data <= x"20";
when "00" & x"d7a" => data <= x"f1";
when "00" & x"d7b" => data <= x"ff";
when "00" & x"d7c" => data <= x"90";
when "00" & x"d7d" => data <= x"05";
when "00" & x"d7e" => data <= x"a9";
when "00" & x"d7f" => data <= x"ff";
when "00" & x"d80" => data <= x"4c";
when "00" & x"d81" => data <= x"9e";
when "00" & x"d82" => data <= x"05";
when "00" & x"d83" => data <= x"a2";
when "00" & x"d84" => data <= x"00";
when "00" & x"d85" => data <= x"a9";
when "00" & x"d86" => data <= x"7f";
when "00" & x"d87" => data <= x"20";
when "00" & x"d88" => data <= x"95";
when "00" & x"d89" => data <= x"06";
when "00" & x"d8a" => data <= x"bd";
when "00" & x"d8b" => data <= x"00";
when "00" & x"d8c" => data <= x"07";
when "00" & x"d8d" => data <= x"20";
when "00" & x"d8e" => data <= x"95";
when "00" & x"d8f" => data <= x"06";
when "00" & x"d90" => data <= x"e8";
when "00" & x"d91" => data <= x"c9";
when "00" & x"d92" => data <= x"0d";
when "00" & x"d93" => data <= x"d0";
when "00" & x"d94" => data <= x"f5";
when "00" & x"d95" => data <= x"4c";
when "00" & x"d96" => data <= x"36";
when "00" & x"d97" => data <= x"00";
when "00" & x"d98" => data <= x"2c";
when "00" & x"d99" => data <= x"e2";
when "00" & x"d9a" => data <= x"fe";
when "00" & x"d9b" => data <= x"50";
when "00" & x"d9c" => data <= x"fb";
when "00" & x"d9d" => data <= x"8d";
when "00" & x"d9e" => data <= x"e3";
when "00" & x"d9f" => data <= x"fe";
when "00" & x"da0" => data <= x"60";
when "00" & x"da1" => data <= x"2c";
when "00" & x"da2" => data <= x"e6";
when "00" & x"da3" => data <= x"fe";
when "00" & x"da4" => data <= x"50";
when "00" & x"da5" => data <= x"fb";
when "00" & x"da6" => data <= x"8d";
when "00" & x"da7" => data <= x"e7";
when "00" & x"da8" => data <= x"fe";
when "00" & x"da9" => data <= x"60";
when "00" & x"daa" => data <= x"a5";
when "00" & x"dab" => data <= x"ff";
when "00" & x"dac" => data <= x"38";
when "00" & x"dad" => data <= x"6a";
when "00" & x"dae" => data <= x"30";
when "00" & x"daf" => data <= x"0f";
when "00" & x"db0" => data <= x"48";
when "00" & x"db1" => data <= x"a9";
when "00" & x"db2" => data <= x"00";
when "00" & x"db3" => data <= x"20";
when "00" & x"db4" => data <= x"bc";
when "00" & x"db5" => data <= x"06";
when "00" & x"db6" => data <= x"98";
when "00" & x"db7" => data <= x"20";
when "00" & x"db8" => data <= x"bc";
when "00" & x"db9" => data <= x"06";
when "00" & x"dba" => data <= x"8a";
when "00" & x"dbb" => data <= x"20";
when "00" & x"dbc" => data <= x"bc";
when "00" & x"dbd" => data <= x"06";
when "00" & x"dbe" => data <= x"68";
when "00" & x"dbf" => data <= x"2c";
when "00" & x"dc0" => data <= x"e0";
when "00" & x"dc1" => data <= x"fe";
when "00" & x"dc2" => data <= x"50";
when "00" & x"dc3" => data <= x"fb";
when "00" & x"dc4" => data <= x"8d";
when "00" & x"dc5" => data <= x"e1";
when "00" & x"dc6" => data <= x"fe";
when "00" & x"dc7" => data <= x"60";
when "00" & x"dc8" => data <= x"2c";
when "00" & x"dc9" => data <= x"e2";
when "00" & x"dca" => data <= x"fe";
when "00" & x"dcb" => data <= x"10";
when "00" & x"dcc" => data <= x"fb";
when "00" & x"dcd" => data <= x"ad";
when "00" & x"dce" => data <= x"e3";
when "00" & x"dcf" => data <= x"fe";
when "00" & x"dd0" => data <= x"60";
when "00" & x"dd1" => data <= x"00";
when "00" & x"dd2" => data <= x"00";
when "00" & x"dd3" => data <= x"00";
when "00" & x"dd4" => data <= x"00";
when "00" & x"dd5" => data <= x"00";
when "00" & x"dd6" => data <= x"00";
when "00" & x"dd7" => data <= x"00";
when "00" & x"dd8" => data <= x"00";
when "00" & x"dd9" => data <= x"00";
when "00" & x"dda" => data <= x"00";
when "00" & x"ddb" => data <= x"00";
when "00" & x"ddc" => data <= x"00";
when "00" & x"ddd" => data <= x"a2";
when "00" & x"dde" => data <= x"11";
when "00" & x"ddf" => data <= x"a0";
when "00" & x"de0" => data <= x"13";
when "00" & x"de1" => data <= x"60";
when "00" & x"de2" => data <= x"20";
when "00" & x"de3" => data <= x"e1";
when "00" & x"de4" => data <= x"83";
when "00" & x"de5" => data <= x"a9";
when "00" & x"de6" => data <= x"77";
when "00" & x"de7" => data <= x"4c";
when "00" & x"de8" => data <= x"f4";
when "00" & x"de9" => data <= x"ff";
when "00" & x"dea" => data <= x"20";
when "00" & x"deb" => data <= x"e2";
when "00" & x"dec" => data <= x"8d";
when "00" & x"ded" => data <= x"a9";
when "00" & x"dee" => data <= x"00";
when "00" & x"def" => data <= x"18";
when "00" & x"df0" => data <= x"69";
when "00" & x"df1" => data <= x"20";
when "00" & x"df2" => data <= x"f0";
when "00" & x"df3" => data <= x"ed";
when "00" & x"df4" => data <= x"a8";
when "00" & x"df5" => data <= x"20";
when "00" & x"df6" => data <= x"05";
when "00" & x"df7" => data <= x"8e";
when "00" & x"df8" => data <= x"d0";
when "00" & x"df9" => data <= x"f5";
when "00" & x"dfa" => data <= x"98";
when "00" & x"dfb" => data <= x"f0";
when "00" & x"dfc" => data <= x"ed";
when "00" & x"dfd" => data <= x"20";
when "00" & x"dfe" => data <= x"7b";
when "00" & x"dff" => data <= x"90";
when "00" & x"e00" => data <= x"90";
when "00" & x"e01" => data <= x"03";
when "00" & x"e02" => data <= x"4c";
when "00" & x"e03" => data <= x"ad";
when "00" & x"e04" => data <= x"90";
when "00" & x"e05" => data <= x"48";
when "00" & x"e06" => data <= x"20";
when "00" & x"e07" => data <= x"51";
when "00" & x"e08" => data <= x"90";
when "00" & x"e09" => data <= x"b0";
when "00" & x"e0a" => data <= x"45";
when "00" & x"e0b" => data <= x"b9";
when "00" & x"e0c" => data <= x"1b";
when "00" & x"e0d" => data <= x"11";
when "00" & x"e0e" => data <= x"49";
when "00" & x"e0f" => data <= x"ff";
when "00" & x"e10" => data <= x"2d";
when "00" & x"e11" => data <= x"c0";
when "00" & x"e12" => data <= x"10";
when "00" & x"e13" => data <= x"8d";
when "00" & x"e14" => data <= x"c0";
when "00" & x"e15" => data <= x"10";
when "00" & x"e16" => data <= x"b9";
when "00" & x"e17" => data <= x"17";
when "00" & x"e18" => data <= x"11";
when "00" & x"e19" => data <= x"29";
when "00" & x"e1a" => data <= x"60";
when "00" & x"e1b" => data <= x"f0";
when "00" & x"e1c" => data <= x"33";
when "00" & x"e1d" => data <= x"20";
when "00" & x"e1e" => data <= x"55";
when "00" & x"e1f" => data <= x"8e";
when "00" & x"e20" => data <= x"b9";
when "00" & x"e21" => data <= x"17";
when "00" & x"e22" => data <= x"11";
when "00" & x"e23" => data <= x"29";
when "00" & x"e24" => data <= x"20";
when "00" & x"e25" => data <= x"f0";
when "00" & x"e26" => data <= x"26";
when "00" & x"e27" => data <= x"ae";
when "00" & x"e28" => data <= x"c4";
when "00" & x"e29" => data <= x"10";
when "00" & x"e2a" => data <= x"b9";
when "00" & x"e2b" => data <= x"14";
when "00" & x"e2c" => data <= x"11";
when "00" & x"e2d" => data <= x"9d";
when "00" & x"e2e" => data <= x"0c";
when "00" & x"e2f" => data <= x"0f";
when "00" & x"e30" => data <= x"b9";
when "00" & x"e31" => data <= x"15";
when "00" & x"e32" => data <= x"11";
when "00" & x"e33" => data <= x"9d";
when "00" & x"e34" => data <= x"0d";
when "00" & x"e35" => data <= x"0f";
when "00" & x"e36" => data <= x"b9";
when "00" & x"e37" => data <= x"16";
when "00" & x"e38" => data <= x"11";
when "00" & x"e39" => data <= x"20";
when "00" & x"e3a" => data <= x"0b";
when "00" & x"e3b" => data <= x"82";
when "00" & x"e3c" => data <= x"5d";
when "00" & x"e3d" => data <= x"0e";
when "00" & x"e3e" => data <= x"0f";
when "00" & x"e3f" => data <= x"29";
when "00" & x"e40" => data <= x"30";
when "00" & x"e41" => data <= x"5d";
when "00" & x"e42" => data <= x"0e";
when "00" & x"e43" => data <= x"0f";
when "00" & x"e44" => data <= x"9d";
when "00" & x"e45" => data <= x"0e";
when "00" & x"e46" => data <= x"0f";
when "00" & x"e47" => data <= x"20";
when "00" & x"e48" => data <= x"b4";
when "00" & x"e49" => data <= x"8a";
when "00" & x"e4a" => data <= x"ac";
when "00" & x"e4b" => data <= x"c2";
when "00" & x"e4c" => data <= x"10";
when "00" & x"e4d" => data <= x"20";
when "00" & x"e4e" => data <= x"4b";
when "00" & x"e4f" => data <= x"91";
when "00" & x"e50" => data <= x"ae";
when "00" & x"e51" => data <= x"c6";
when "00" & x"e52" => data <= x"10";
when "00" & x"e53" => data <= x"68";
when "00" & x"e54" => data <= x"60";
when "00" & x"e55" => data <= x"20";
when "00" & x"e56" => data <= x"83";
when "00" & x"e57" => data <= x"8e";
when "00" & x"e58" => data <= x"a2";
when "00" & x"e59" => data <= x"07";
when "00" & x"e5a" => data <= x"b9";
when "00" & x"e5b" => data <= x"0c";
when "00" & x"e5c" => data <= x"11";
when "00" & x"e5d" => data <= x"95";
when "00" & x"e5e" => data <= x"c6";
when "00" & x"e5f" => data <= x"88";
when "00" & x"e60" => data <= x"88";
when "00" & x"e61" => data <= x"ca";
when "00" & x"e62" => data <= x"d0";
when "00" & x"e63" => data <= x"f6";
when "00" & x"e64" => data <= x"20";
when "00" & x"e65" => data <= x"96";
when "00" & x"e66" => data <= x"82";
when "00" & x"e67" => data <= x"90";
when "00" & x"e68" => data <= x"27";
when "00" & x"e69" => data <= x"8c";
when "00" & x"e6a" => data <= x"c4";
when "00" & x"e6b" => data <= x"10";
when "00" & x"e6c" => data <= x"b9";
when "00" & x"e6d" => data <= x"0e";
when "00" & x"e6e" => data <= x"0f";
when "00" & x"e6f" => data <= x"be";
when "00" & x"e70" => data <= x"0f";
when "00" & x"e71" => data <= x"0f";
when "00" & x"e72" => data <= x"ac";
when "00" & x"e73" => data <= x"c2";
when "00" & x"e74" => data <= x"10";
when "00" & x"e75" => data <= x"59";
when "00" & x"e76" => data <= x"0d";
when "00" & x"e77" => data <= x"11";
when "00" & x"e78" => data <= x"29";
when "00" & x"e79" => data <= x"03";
when "00" & x"e7a" => data <= x"d0";
when "00" & x"e7b" => data <= x"14";
when "00" & x"e7c" => data <= x"8a";
when "00" & x"e7d" => data <= x"d9";
when "00" & x"e7e" => data <= x"0f";
when "00" & x"e7f" => data <= x"11";
when "00" & x"e80" => data <= x"d0";
when "00" & x"e81" => data <= x"0e";
when "00" & x"e82" => data <= x"60";
when "00" & x"e83" => data <= x"b9";
when "00" & x"e84" => data <= x"0e";
when "00" & x"e85" => data <= x"11";
when "00" & x"e86" => data <= x"29";
when "00" & x"e87" => data <= x"7f";
when "00" & x"e88" => data <= x"85";
when "00" & x"e89" => data <= x"ce";
when "00" & x"e8a" => data <= x"b9";
when "00" & x"e8b" => data <= x"17";
when "00" & x"e8c" => data <= x"11";
when "00" & x"e8d" => data <= x"4c";
when "00" & x"e8e" => data <= x"7e";
when "00" & x"e8f" => data <= x"87";
when "00" & x"e90" => data <= x"4c";
when "00" & x"e91" => data <= x"af";
when "00" & x"e92" => data <= x"81";
when "00" & x"e93" => data <= x"c9";
when "00" & x"e94" => data <= x"00";
when "00" & x"e95" => data <= x"d0";
when "00" & x"e96" => data <= x"06";
when "00" & x"e97" => data <= x"20";
when "00" & x"e98" => data <= x"e1";
when "00" & x"e99" => data <= x"83";
when "00" & x"e9a" => data <= x"4c";
when "00" & x"e9b" => data <= x"fa";
when "00" & x"e9c" => data <= x"8d";
when "00" & x"e9d" => data <= x"20";
when "00" & x"e9e" => data <= x"11";
when "00" & x"e9f" => data <= x"84";
when "00" & x"ea0" => data <= x"86";
when "00" & x"ea1" => data <= x"bc";
when "00" & x"ea2" => data <= x"84";
when "00" & x"ea3" => data <= x"bd";
when "00" & x"ea4" => data <= x"85";
when "00" & x"ea5" => data <= x"b4";
when "00" & x"ea6" => data <= x"24";
when "00" & x"ea7" => data <= x"b4";
when "00" & x"ea8" => data <= x"08";
when "00" & x"ea9" => data <= x"20";
when "00" & x"eaa" => data <= x"06";
when "00" & x"eab" => data <= x"81";
when "00" & x"eac" => data <= x"20";
when "00" & x"ead" => data <= x"96";
when "00" & x"eae" => data <= x"82";
when "00" & x"eaf" => data <= x"b0";
when "00" & x"eb0" => data <= x"1a";
when "00" & x"eb1" => data <= x"28";
when "00" & x"eb2" => data <= x"50";
when "00" & x"eb3" => data <= x"03";
when "00" & x"eb4" => data <= x"a9";
when "00" & x"eb5" => data <= x"00";
when "00" & x"eb6" => data <= x"60";
when "00" & x"eb7" => data <= x"08";
when "00" & x"eb8" => data <= x"a9";
when "00" & x"eb9" => data <= x"00";
when "00" & x"eba" => data <= x"a2";
when "00" & x"ebb" => data <= x"07";
when "00" & x"ebc" => data <= x"95";
when "00" & x"ebd" => data <= x"be";
when "00" & x"ebe" => data <= x"9d";
when "00" & x"ebf" => data <= x"74";
when "00" & x"ec0" => data <= x"10";
when "00" & x"ec1" => data <= x"ca";
when "00" & x"ec2" => data <= x"10";
when "00" & x"ec3" => data <= x"f8";
when "00" & x"ec4" => data <= x"a9";
when "00" & x"ec5" => data <= x"40";
when "00" & x"ec6" => data <= x"85";
when "00" & x"ec7" => data <= x"c5";
when "00" & x"ec8" => data <= x"20";
when "00" & x"ec9" => data <= x"61";
when "00" & x"eca" => data <= x"89";
when "00" & x"ecb" => data <= x"28";
when "00" & x"ecc" => data <= x"08";
when "00" & x"ecd" => data <= x"70";
when "00" & x"ece" => data <= x"03";
when "00" & x"ecf" => data <= x"20";
when "00" & x"ed0" => data <= x"3c";
when "00" & x"ed1" => data <= x"98";
when "00" & x"ed2" => data <= x"20";
when "00" & x"ed3" => data <= x"9e";
when "00" & x"ed4" => data <= x"8f";
when "00" & x"ed5" => data <= x"90";
when "00" & x"ed6" => data <= x"0e";
when "00" & x"ed7" => data <= x"b9";
when "00" & x"ed8" => data <= x"0c";
when "00" & x"ed9" => data <= x"11";
when "00" & x"eda" => data <= x"10";
when "00" & x"edb" => data <= x"26";
when "00" & x"edc" => data <= x"24";
when "00" & x"edd" => data <= x"b4";
when "00" & x"ede" => data <= x"30";
when "00" & x"edf" => data <= x"22";
when "00" & x"ee0" => data <= x"20";
when "00" & x"ee1" => data <= x"99";
when "00" & x"ee2" => data <= x"8f";
when "00" & x"ee3" => data <= x"b0";
when "00" & x"ee4" => data <= x"f2";
when "00" & x"ee5" => data <= x"ac";
when "00" & x"ee6" => data <= x"c2";
when "00" & x"ee7" => data <= x"10";
when "00" & x"ee8" => data <= x"d0";
when "00" & x"ee9" => data <= x"21";
when "00" & x"eea" => data <= x"20";
when "00" & x"eeb" => data <= x"33";
when "00" & x"eec" => data <= x"80";
when "00" & x"eed" => data <= x"c0";
when "00" & x"eee" => data <= x"54";
when "00" & x"eef" => data <= x"6f";
when "00" & x"ef0" => data <= x"6f";
when "00" & x"ef1" => data <= x"20";
when "00" & x"ef2" => data <= x"6d";
when "00" & x"ef3" => data <= x"61";
when "00" & x"ef4" => data <= x"6e";
when "00" & x"ef5" => data <= x"79";
when "00" & x"ef6" => data <= x"20";
when "00" & x"ef7" => data <= x"66";
when "00" & x"ef8" => data <= x"69";
when "00" & x"ef9" => data <= x"6c";
when "00" & x"efa" => data <= x"65";
when "00" & x"efb" => data <= x"73";
when "00" & x"efc" => data <= x"20";
when "00" & x"efd" => data <= x"6f";
when "00" & x"efe" => data <= x"70";
when "00" & x"eff" => data <= x"65";
when "00" & x"f00" => data <= x"6e";
when "00" & x"f01" => data <= x"00";
when "00" & x"f02" => data <= x"20";
when "00" & x"f03" => data <= x"2b";
when "00" & x"f04" => data <= x"80";
when "00" & x"f05" => data <= x"c2";
when "00" & x"f06" => data <= x"6f";
when "00" & x"f07" => data <= x"70";
when "00" & x"f08" => data <= x"65";
when "00" & x"f09" => data <= x"6e";
when "00" & x"f0a" => data <= x"00";
when "00" & x"f0b" => data <= x"a9";
when "00" & x"f0c" => data <= x"08";
when "00" & x"f0d" => data <= x"8d";
when "00" & x"f0e" => data <= x"c5";
when "00" & x"f0f" => data <= x"10";
when "00" & x"f10" => data <= x"bd";
when "00" & x"f11" => data <= x"08";
when "00" & x"f12" => data <= x"0e";
when "00" & x"f13" => data <= x"99";
when "00" & x"f14" => data <= x"00";
when "00" & x"f15" => data <= x"11";
when "00" & x"f16" => data <= x"c8";
when "00" & x"f17" => data <= x"bd";
when "00" & x"f18" => data <= x"08";
when "00" & x"f19" => data <= x"0f";
when "00" & x"f1a" => data <= x"99";
when "00" & x"f1b" => data <= x"00";
when "00" & x"f1c" => data <= x"11";
when "00" & x"f1d" => data <= x"c8";
when "00" & x"f1e" => data <= x"e8";
when "00" & x"f1f" => data <= x"ce";
when "00" & x"f20" => data <= x"c5";
when "00" & x"f21" => data <= x"10";
when "00" & x"f22" => data <= x"d0";
when "00" & x"f23" => data <= x"ec";
when "00" & x"f24" => data <= x"a2";
when "00" & x"f25" => data <= x"10";
when "00" & x"f26" => data <= x"a9";
when "00" & x"f27" => data <= x"00";
when "00" & x"f28" => data <= x"99";
when "00" & x"f29" => data <= x"00";
when "00" & x"f2a" => data <= x"11";
when "00" & x"f2b" => data <= x"c8";
when "00" & x"f2c" => data <= x"ca";
when "00" & x"f2d" => data <= x"d0";
when "00" & x"f2e" => data <= x"f9";
when "00" & x"f2f" => data <= x"ad";
when "00" & x"f30" => data <= x"c2";
when "00" & x"f31" => data <= x"10";
when "00" & x"f32" => data <= x"a8";
when "00" & x"f33" => data <= x"20";
when "00" & x"f34" => data <= x"04";
when "00" & x"f35" => data <= x"82";
when "00" & x"f36" => data <= x"69";
when "00" & x"f37" => data <= x"11";
when "00" & x"f38" => data <= x"99";
when "00" & x"f39" => data <= x"13";
when "00" & x"f3a" => data <= x"11";
when "00" & x"f3b" => data <= x"ad";
when "00" & x"f3c" => data <= x"c1";
when "00" & x"f3d" => data <= x"10";
when "00" & x"f3e" => data <= x"99";
when "00" & x"f3f" => data <= x"1b";
when "00" & x"f40" => data <= x"11";
when "00" & x"f41" => data <= x"0d";
when "00" & x"f42" => data <= x"c0";
when "00" & x"f43" => data <= x"10";
when "00" & x"f44" => data <= x"8d";
when "00" & x"f45" => data <= x"c0";
when "00" & x"f46" => data <= x"10";
when "00" & x"f47" => data <= x"b9";
when "00" & x"f48" => data <= x"09";
when "00" & x"f49" => data <= x"11";
when "00" & x"f4a" => data <= x"69";
when "00" & x"f4b" => data <= x"ff";
when "00" & x"f4c" => data <= x"b9";
when "00" & x"f4d" => data <= x"0b";
when "00" & x"f4e" => data <= x"11";
when "00" & x"f4f" => data <= x"69";
when "00" & x"f50" => data <= x"00";
when "00" & x"f51" => data <= x"99";
when "00" & x"f52" => data <= x"19";
when "00" & x"f53" => data <= x"11";
when "00" & x"f54" => data <= x"b9";
when "00" & x"f55" => data <= x"0d";
when "00" & x"f56" => data <= x"11";
when "00" & x"f57" => data <= x"09";
when "00" & x"f58" => data <= x"0f";
when "00" & x"f59" => data <= x"69";
when "00" & x"f5a" => data <= x"00";
when "00" & x"f5b" => data <= x"20";
when "00" & x"f5c" => data <= x"fd";
when "00" & x"f5d" => data <= x"81";
when "00" & x"f5e" => data <= x"99";
when "00" & x"f5f" => data <= x"1a";
when "00" & x"f60" => data <= x"11";
when "00" & x"f61" => data <= x"28";
when "00" & x"f62" => data <= x"50";
when "00" & x"f63" => data <= x"2e";
when "00" & x"f64" => data <= x"30";
when "00" & x"f65" => data <= x"08";
when "00" & x"f66" => data <= x"a9";
when "00" & x"f67" => data <= x"80";
when "00" & x"f68" => data <= x"19";
when "00" & x"f69" => data <= x"0c";
when "00" & x"f6a" => data <= x"11";
when "00" & x"f6b" => data <= x"99";
when "00" & x"f6c" => data <= x"0c";
when "00" & x"f6d" => data <= x"11";
when "00" & x"f6e" => data <= x"b9";
when "00" & x"f6f" => data <= x"09";
when "00" & x"f70" => data <= x"11";
when "00" & x"f71" => data <= x"99";
when "00" & x"f72" => data <= x"14";
when "00" & x"f73" => data <= x"11";
when "00" & x"f74" => data <= x"b9";
when "00" & x"f75" => data <= x"0b";
when "00" & x"f76" => data <= x"11";
when "00" & x"f77" => data <= x"99";
when "00" & x"f78" => data <= x"15";
when "00" & x"f79" => data <= x"11";
when "00" & x"f7a" => data <= x"b9";
when "00" & x"f7b" => data <= x"0d";
when "00" & x"f7c" => data <= x"11";
when "00" & x"f7d" => data <= x"20";
when "00" & x"f7e" => data <= x"fd";
when "00" & x"f7f" => data <= x"81";
when "00" & x"f80" => data <= x"99";
when "00" & x"f81" => data <= x"16";
when "00" & x"f82" => data <= x"11";
when "00" & x"f83" => data <= x"a5";
when "00" & x"f84" => data <= x"cf";
when "00" & x"f85" => data <= x"19";
when "00" & x"f86" => data <= x"17";
when "00" & x"f87" => data <= x"11";
when "00" & x"f88" => data <= x"99";
when "00" & x"f89" => data <= x"17";
when "00" & x"f8a" => data <= x"11";
when "00" & x"f8b" => data <= x"98";
when "00" & x"f8c" => data <= x"20";
when "00" & x"f8d" => data <= x"04";
when "00" & x"f8e" => data <= x"82";
when "00" & x"f8f" => data <= x"09";
when "00" & x"f90" => data <= x"10";
when "00" & x"f91" => data <= x"60";
when "00" & x"f92" => data <= x"a9";
when "00" & x"f93" => data <= x"20";
when "00" & x"f94" => data <= x"99";
when "00" & x"f95" => data <= x"17";
when "00" & x"f96" => data <= x"11";
when "00" & x"f97" => data <= x"d0";
when "00" & x"f98" => data <= x"ea";
when "00" & x"f99" => data <= x"8a";
when "00" & x"f9a" => data <= x"48";
when "00" & x"f9b" => data <= x"4c";
when "00" & x"f9c" => data <= x"dd";
when "00" & x"f9d" => data <= x"8f";
when "00" & x"f9e" => data <= x"a9";
when "00" & x"f9f" => data <= x"00";
when "00" & x"fa0" => data <= x"8d";
when "00" & x"fa1" => data <= x"c2";
when "00" & x"fa2" => data <= x"10";
when "00" & x"fa3" => data <= x"a9";
when "00" & x"fa4" => data <= x"08";
when "00" & x"fa5" => data <= x"85";
when "00" & x"fa6" => data <= x"b5";
when "00" & x"fa7" => data <= x"98";
when "00" & x"fa8" => data <= x"aa";
when "00" & x"fa9" => data <= x"a0";
when "00" & x"faa" => data <= x"a0";
when "00" & x"fab" => data <= x"84";
when "00" & x"fac" => data <= x"b3";
when "00" & x"fad" => data <= x"8a";
when "00" & x"fae" => data <= x"48";
when "00" & x"faf" => data <= x"a9";
when "00" & x"fb0" => data <= x"08";
when "00" & x"fb1" => data <= x"85";
when "00" & x"fb2" => data <= x"b2";
when "00" & x"fb3" => data <= x"a5";
when "00" & x"fb4" => data <= x"b5";
when "00" & x"fb5" => data <= x"2c";
when "00" & x"fb6" => data <= x"c0";
when "00" & x"fb7" => data <= x"10";
when "00" & x"fb8" => data <= x"f0";
when "00" & x"fb9" => data <= x"1d";
when "00" & x"fba" => data <= x"b9";
when "00" & x"fbb" => data <= x"17";
when "00" & x"fbc" => data <= x"11";
when "00" & x"fbd" => data <= x"45";
when "00" & x"fbe" => data <= x"cf";
when "00" & x"fbf" => data <= x"29";
when "00" & x"fc0" => data <= x"03";
when "00" & x"fc1" => data <= x"d0";
when "00" & x"fc2" => data <= x"1a";
when "00" & x"fc3" => data <= x"bd";
when "00" & x"fc4" => data <= x"08";
when "00" & x"fc5" => data <= x"0e";
when "00" & x"fc6" => data <= x"59";
when "00" & x"fc7" => data <= x"00";
when "00" & x"fc8" => data <= x"11";
when "00" & x"fc9" => data <= x"29";
when "00" & x"fca" => data <= x"7f";
when "00" & x"fcb" => data <= x"d0";
when "00" & x"fcc" => data <= x"10";
when "00" & x"fcd" => data <= x"e8";
when "00" & x"fce" => data <= x"c8";
when "00" & x"fcf" => data <= x"c8";
when "00" & x"fd0" => data <= x"c6";
when "00" & x"fd1" => data <= x"b2";
when "00" & x"fd2" => data <= x"d0";
when "00" & x"fd3" => data <= x"ef";
when "00" & x"fd4" => data <= x"38";
when "00" & x"fd5" => data <= x"b0";
when "00" & x"fd6" => data <= x"10";
when "00" & x"fd7" => data <= x"8c";
when "00" & x"fd8" => data <= x"c2";
when "00" & x"fd9" => data <= x"10";
when "00" & x"fda" => data <= x"8d";
when "00" & x"fdb" => data <= x"c1";
when "00" & x"fdc" => data <= x"10";
when "00" & x"fdd" => data <= x"38";
when "00" & x"fde" => data <= x"a5";
when "00" & x"fdf" => data <= x"b3";
when "00" & x"fe0" => data <= x"e9";
when "00" & x"fe1" => data <= x"20";
when "00" & x"fe2" => data <= x"85";
when "00" & x"fe3" => data <= x"b3";
when "00" & x"fe4" => data <= x"06";
when "00" & x"fe5" => data <= x"b5";
when "00" & x"fe6" => data <= x"18";
when "00" & x"fe7" => data <= x"68";
when "00" & x"fe8" => data <= x"aa";
when "00" & x"fe9" => data <= x"a4";
when "00" & x"fea" => data <= x"b3";
when "00" & x"feb" => data <= x"a5";
when "00" & x"fec" => data <= x"b5";
when "00" & x"fed" => data <= x"b0";
when "00" & x"fee" => data <= x"02";
when "00" & x"fef" => data <= x"d0";
when "00" & x"ff0" => data <= x"ba";
when "00" & x"ff1" => data <= x"60";
when "00" & x"ff2" => data <= x"ad";
when "00" & x"ff3" => data <= x"c0";
when "00" & x"ff4" => data <= x"10";
when "00" & x"ff5" => data <= x"48";
when "00" & x"ff6" => data <= x"20";
when "00" & x"ff7" => data <= x"ed";
when "00" & x"ff8" => data <= x"8d";
when "00" & x"ff9" => data <= x"f0";
when "00" & x"ffa" => data <= x"07";
when "00" & x"ffb" => data <= x"ad";
when "00" & x"ffc" => data <= x"c0";
when "00" & x"ffd" => data <= x"10";
when "00" & x"ffe" => data <= x"48";
when "00" & x"fff" => data <= x"20";
when "01" & x"000" => data <= x"fa";
when "01" & x"001" => data <= x"8d";
when "01" & x"002" => data <= x"68";
when "01" & x"003" => data <= x"8d";
when "01" & x"004" => data <= x"c0";
when "01" & x"005" => data <= x"10";
when "01" & x"006" => data <= x"60";
when "01" & x"007" => data <= x"c0";
when "01" & x"008" => data <= x"00";
when "01" & x"009" => data <= x"f0";
when "01" & x"00a" => data <= x"11";
when "01" & x"00b" => data <= x"20";
when "01" & x"00c" => data <= x"e1";
when "01" & x"00d" => data <= x"83";
when "01" & x"00e" => data <= x"c9";
when "01" & x"00f" => data <= x"ff";
when "01" & x"010" => data <= x"f0";
when "01" & x"011" => data <= x"e9";
when "01" & x"012" => data <= x"c9";
when "01" & x"013" => data <= x"03";
when "01" & x"014" => data <= x"b0";
when "01" & x"015" => data <= x"17";
when "01" & x"016" => data <= x"4a";
when "01" & x"017" => data <= x"90";
when "01" & x"018" => data <= x"15";
when "01" & x"019" => data <= x"4c";
when "01" & x"01a" => data <= x"a7";
when "01" & x"01b" => data <= x"92";
when "01" & x"01c" => data <= x"20";
when "01" & x"01d" => data <= x"11";
when "01" & x"01e" => data <= x"84";
when "01" & x"01f" => data <= x"a8";
when "01" & x"020" => data <= x"c8";
when "01" & x"021" => data <= x"c0";
when "01" & x"022" => data <= x"03";
when "01" & x"023" => data <= x"b0";
when "01" & x"024" => data <= x"08";
when "01" & x"025" => data <= x"b9";
when "01" & x"026" => data <= x"81";
when "01" & x"027" => data <= x"99";
when "01" & x"028" => data <= x"48";
when "01" & x"029" => data <= x"b9";
when "01" & x"02a" => data <= x"7e";
when "01" & x"02b" => data <= x"99";
when "01" & x"02c" => data <= x"48";
when "01" & x"02d" => data <= x"60";
when "01" & x"02e" => data <= x"20";
when "01" & x"02f" => data <= x"e1";
when "01" & x"030" => data <= x"83";
when "01" & x"031" => data <= x"20";
when "01" & x"032" => data <= x"a5";
when "01" & x"033" => data <= x"90";
when "01" & x"034" => data <= x"8c";
when "01" & x"035" => data <= x"c2";
when "01" & x"036" => data <= x"10";
when "01" & x"037" => data <= x"0a";
when "01" & x"038" => data <= x"0a";
when "01" & x"039" => data <= x"6d";
when "01" & x"03a" => data <= x"c2";
when "01" & x"03b" => data <= x"10";
when "01" & x"03c" => data <= x"a8";
when "01" & x"03d" => data <= x"b9";
when "01" & x"03e" => data <= x"10";
when "01" & x"03f" => data <= x"11";
when "01" & x"040" => data <= x"95";
when "01" & x"041" => data <= x"00";
when "01" & x"042" => data <= x"b9";
when "01" & x"043" => data <= x"11";
when "01" & x"044" => data <= x"11";
when "01" & x"045" => data <= x"95";
when "01" & x"046" => data <= x"01";
when "01" & x"047" => data <= x"b9";
when "01" & x"048" => data <= x"12";
when "01" & x"049" => data <= x"11";
when "01" & x"04a" => data <= x"95";
when "01" & x"04b" => data <= x"02";
when "01" & x"04c" => data <= x"a9";
when "01" & x"04d" => data <= x"00";
when "01" & x"04e" => data <= x"95";
when "01" & x"04f" => data <= x"03";
when "01" & x"050" => data <= x"60";
when "01" & x"051" => data <= x"48";
when "01" & x"052" => data <= x"8e";
when "01" & x"053" => data <= x"c6";
when "01" & x"054" => data <= x"10";
when "01" & x"055" => data <= x"98";
when "01" & x"056" => data <= x"29";
when "01" & x"057" => data <= x"e0";
when "01" & x"058" => data <= x"8d";
when "01" & x"059" => data <= x"c2";
when "01" & x"05a" => data <= x"10";
when "01" & x"05b" => data <= x"f0";
when "01" & x"05c" => data <= x"13";
when "01" & x"05d" => data <= x"20";
when "01" & x"05e" => data <= x"04";
when "01" & x"05f" => data <= x"82";
when "01" & x"060" => data <= x"a8";
when "01" & x"061" => data <= x"a9";
when "01" & x"062" => data <= x"00";
when "01" & x"063" => data <= x"38";
when "01" & x"064" => data <= x"6a";
when "01" & x"065" => data <= x"88";
when "01" & x"066" => data <= x"d0";
when "01" & x"067" => data <= x"fc";
when "01" & x"068" => data <= x"ac";
when "01" & x"069" => data <= x"c2";
when "01" & x"06a" => data <= x"10";
when "01" & x"06b" => data <= x"2c";
when "01" & x"06c" => data <= x"c0";
when "01" & x"06d" => data <= x"10";
when "01" & x"06e" => data <= x"d0";
when "01" & x"06f" => data <= x"03";
when "01" & x"070" => data <= x"68";
when "01" & x"071" => data <= x"38";
when "01" & x"072" => data <= x"60";
when "01" & x"073" => data <= x"68";
when "01" & x"074" => data <= x"18";
when "01" & x"075" => data <= x"60";
when "01" & x"076" => data <= x"48";
when "01" & x"077" => data <= x"8a";
when "01" & x"078" => data <= x"4c";
when "01" & x"079" => data <= x"7d";
when "01" & x"07a" => data <= x"90";
when "01" & x"07b" => data <= x"48";
when "01" & x"07c" => data <= x"98";
when "01" & x"07d" => data <= x"c9";
when "01" & x"07e" => data <= x"10";
when "01" & x"07f" => data <= x"90";
when "01" & x"080" => data <= x"04";
when "01" & x"081" => data <= x"c9";
when "01" & x"082" => data <= x"18";
when "01" & x"083" => data <= x"90";
when "01" & x"084" => data <= x"02";
when "01" & x"085" => data <= x"a9";
when "01" & x"086" => data <= x"08";
when "01" & x"087" => data <= x"20";
when "01" & x"088" => data <= x"0a";
when "01" & x"089" => data <= x"82";
when "01" & x"08a" => data <= x"a8";
when "01" & x"08b" => data <= x"68";
when "01" & x"08c" => data <= x"60";
when "01" & x"08d" => data <= x"48";
when "01" & x"08e" => data <= x"98";
when "01" & x"08f" => data <= x"48";
when "01" & x"090" => data <= x"8a";
when "01" & x"091" => data <= x"a8";
when "01" & x"092" => data <= x"20";
when "01" & x"093" => data <= x"a5";
when "01" & x"094" => data <= x"90";
when "01" & x"095" => data <= x"98";
when "01" & x"096" => data <= x"20";
when "01" & x"097" => data <= x"f8";
when "01" & x"098" => data <= x"92";
when "01" & x"099" => data <= x"d0";
when "01" & x"09a" => data <= x"04";
when "01" & x"09b" => data <= x"a2";
when "01" & x"09c" => data <= x"ff";
when "01" & x"09d" => data <= x"d0";
when "01" & x"09e" => data <= x"02";
when "01" & x"09f" => data <= x"a2";
when "01" & x"0a0" => data <= x"00";
when "01" & x"0a1" => data <= x"68";
when "01" & x"0a2" => data <= x"a8";
when "01" & x"0a3" => data <= x"68";
when "01" & x"0a4" => data <= x"60";
when "01" & x"0a5" => data <= x"20";
when "01" & x"0a6" => data <= x"7b";
when "01" & x"0a7" => data <= x"90";
when "01" & x"0a8" => data <= x"20";
when "01" & x"0a9" => data <= x"51";
when "01" & x"0aa" => data <= x"90";
when "01" & x"0ab" => data <= x"90";
when "01" & x"0ac" => data <= x"f7";
when "01" & x"0ad" => data <= x"20";
when "01" & x"0ae" => data <= x"33";
when "01" & x"0af" => data <= x"80";
when "01" & x"0b0" => data <= x"de";
when "01" & x"0b1" => data <= x"43";
when "01" & x"0b2" => data <= x"68";
when "01" & x"0b3" => data <= x"61";
when "01" & x"0b4" => data <= x"6e";
when "01" & x"0b5" => data <= x"6e";
when "01" & x"0b6" => data <= x"65";
when "01" & x"0b7" => data <= x"6c";
when "01" & x"0b8" => data <= x"00";
when "01" & x"0b9" => data <= x"20";
when "01" & x"0ba" => data <= x"33";
when "01" & x"0bb" => data <= x"80";
when "01" & x"0bc" => data <= x"df";
when "01" & x"0bd" => data <= x"45";
when "01" & x"0be" => data <= x"4f";
when "01" & x"0bf" => data <= x"46";
when "01" & x"0c0" => data <= x"00";
when "01" & x"0c1" => data <= x"20";
when "01" & x"0c2" => data <= x"11";
when "01" & x"0c3" => data <= x"84";
when "01" & x"0c4" => data <= x"20";
when "01" & x"0c5" => data <= x"a5";
when "01" & x"0c6" => data <= x"90";
when "01" & x"0c7" => data <= x"98";
when "01" & x"0c8" => data <= x"20";
when "01" & x"0c9" => data <= x"f8";
when "01" & x"0ca" => data <= x"92";
when "01" & x"0cb" => data <= x"d0";
when "01" & x"0cc" => data <= x"13";
when "01" & x"0cd" => data <= x"b9";
when "01" & x"0ce" => data <= x"17";
when "01" & x"0cf" => data <= x"11";
when "01" & x"0d0" => data <= x"29";
when "01" & x"0d1" => data <= x"10";
when "01" & x"0d2" => data <= x"d0";
when "01" & x"0d3" => data <= x"e5";
when "01" & x"0d4" => data <= x"a9";
when "01" & x"0d5" => data <= x"10";
when "01" & x"0d6" => data <= x"20";
when "01" & x"0d7" => data <= x"3c";
when "01" & x"0d8" => data <= x"91";
when "01" & x"0d9" => data <= x"ae";
when "01" & x"0da" => data <= x"c6";
when "01" & x"0db" => data <= x"10";
when "01" & x"0dc" => data <= x"a9";
when "01" & x"0dd" => data <= x"fe";
when "01" & x"0de" => data <= x"38";
when "01" & x"0df" => data <= x"60";
when "01" & x"0e0" => data <= x"b9";
when "01" & x"0e1" => data <= x"17";
when "01" & x"0e2" => data <= x"11";
when "01" & x"0e3" => data <= x"30";
when "01" & x"0e4" => data <= x"0a";
when "01" & x"0e5" => data <= x"20";
when "01" & x"0e6" => data <= x"83";
when "01" & x"0e7" => data <= x"8e";
when "01" & x"0e8" => data <= x"20";
when "01" & x"0e9" => data <= x"4b";
when "01" & x"0ea" => data <= x"91";
when "01" & x"0eb" => data <= x"38";
when "01" & x"0ec" => data <= x"20";
when "01" & x"0ed" => data <= x"53";
when "01" & x"0ee" => data <= x"91";
when "01" & x"0ef" => data <= x"b9";
when "01" & x"0f0" => data <= x"10";
when "01" & x"0f1" => data <= x"11";
when "01" & x"0f2" => data <= x"85";
when "01" & x"0f3" => data <= x"bc";
when "01" & x"0f4" => data <= x"b9";
when "01" & x"0f5" => data <= x"13";
when "01" & x"0f6" => data <= x"11";
when "01" & x"0f7" => data <= x"85";
when "01" & x"0f8" => data <= x"bd";
when "01" & x"0f9" => data <= x"a0";
when "01" & x"0fa" => data <= x"00";
when "01" & x"0fb" => data <= x"b1";
when "01" & x"0fc" => data <= x"bc";
when "01" & x"0fd" => data <= x"48";
when "01" & x"0fe" => data <= x"ac";
when "01" & x"0ff" => data <= x"c2";
when "01" & x"100" => data <= x"10";
when "01" & x"101" => data <= x"a6";
when "01" & x"102" => data <= x"bc";
when "01" & x"103" => data <= x"e8";
when "01" & x"104" => data <= x"8a";
when "01" & x"105" => data <= x"99";
when "01" & x"106" => data <= x"10";
when "01" & x"107" => data <= x"11";
when "01" & x"108" => data <= x"d0";
when "01" & x"109" => data <= x"14";
when "01" & x"10a" => data <= x"18";
when "01" & x"10b" => data <= x"b9";
when "01" & x"10c" => data <= x"11";
when "01" & x"10d" => data <= x"11";
when "01" & x"10e" => data <= x"69";
when "01" & x"10f" => data <= x"01";
when "01" & x"110" => data <= x"99";
when "01" & x"111" => data <= x"11";
when "01" & x"112" => data <= x"11";
when "01" & x"113" => data <= x"b9";
when "01" & x"114" => data <= x"12";
when "01" & x"115" => data <= x"11";
when "01" & x"116" => data <= x"69";
when "01" & x"117" => data <= x"00";
when "01" & x"118" => data <= x"99";
when "01" & x"119" => data <= x"12";
when "01" & x"11a" => data <= x"11";
when "01" & x"11b" => data <= x"20";
when "01" & x"11c" => data <= x"41";
when "01" & x"11d" => data <= x"91";
when "01" & x"11e" => data <= x"18";
when "01" & x"11f" => data <= x"68";
when "01" & x"120" => data <= x"60";
when "01" & x"121" => data <= x"18";
when "01" & x"122" => data <= x"b9";
when "01" & x"123" => data <= x"0f";
when "01" & x"124" => data <= x"11";
when "01" & x"125" => data <= x"79";
when "01" & x"126" => data <= x"11";
when "01" & x"127" => data <= x"11";
when "01" & x"128" => data <= x"85";
when "01" & x"129" => data <= x"c5";
when "01" & x"12a" => data <= x"99";
when "01" & x"12b" => data <= x"1c";
when "01" & x"12c" => data <= x"11";
when "01" & x"12d" => data <= x"b9";
when "01" & x"12e" => data <= x"0d";
when "01" & x"12f" => data <= x"11";
when "01" & x"130" => data <= x"29";
when "01" & x"131" => data <= x"03";
when "01" & x"132" => data <= x"79";
when "01" & x"133" => data <= x"12";
when "01" & x"134" => data <= x"11";
when "01" & x"135" => data <= x"85";
when "01" & x"136" => data <= x"c4";
when "01" & x"137" => data <= x"99";
when "01" & x"138" => data <= x"1d";
when "01" & x"139" => data <= x"11";
when "01" & x"13a" => data <= x"a9";
when "01" & x"13b" => data <= x"80";
when "01" & x"13c" => data <= x"19";
when "01" & x"13d" => data <= x"17";
when "01" & x"13e" => data <= x"11";
when "01" & x"13f" => data <= x"d0";
when "01" & x"140" => data <= x"05";
when "01" & x"141" => data <= x"a9";
when "01" & x"142" => data <= x"7f";
when "01" & x"143" => data <= x"39";
when "01" & x"144" => data <= x"17";
when "01" & x"145" => data <= x"11";
when "01" & x"146" => data <= x"99";
when "01" & x"147" => data <= x"17";
when "01" & x"148" => data <= x"11";
when "01" & x"149" => data <= x"18";
when "01" & x"14a" => data <= x"60";
when "01" & x"14b" => data <= x"b9";
when "01" & x"14c" => data <= x"17";
when "01" & x"14d" => data <= x"11";
when "01" & x"14e" => data <= x"29";
when "01" & x"14f" => data <= x"40";
when "01" & x"150" => data <= x"f0";
when "01" & x"151" => data <= x"3d";
when "01" & x"152" => data <= x"18";
when "01" & x"153" => data <= x"08";
when "01" & x"154" => data <= x"20";
when "01" & x"155" => data <= x"3e";
when "01" & x"156" => data <= x"be";
when "01" & x"157" => data <= x"ac";
when "01" & x"158" => data <= x"c2";
when "01" & x"159" => data <= x"10";
when "01" & x"15a" => data <= x"b9";
when "01" & x"15b" => data <= x"13";
when "01" & x"15c" => data <= x"11";
when "01" & x"15d" => data <= x"85";
when "01" & x"15e" => data <= x"bf";
when "01" & x"15f" => data <= x"20";
when "01" & x"160" => data <= x"8d";
when "01" & x"161" => data <= x"a0";
when "01" & x"162" => data <= x"a9";
when "01" & x"163" => data <= x"00";
when "01" & x"164" => data <= x"85";
when "01" & x"165" => data <= x"be";
when "01" & x"166" => data <= x"85";
when "01" & x"167" => data <= x"c2";
when "01" & x"168" => data <= x"a9";
when "01" & x"169" => data <= x"01";
when "01" & x"16a" => data <= x"85";
when "01" & x"16b" => data <= x"c3";
when "01" & x"16c" => data <= x"28";
when "01" & x"16d" => data <= x"b0";
when "01" & x"16e" => data <= x"17";
when "01" & x"16f" => data <= x"b9";
when "01" & x"170" => data <= x"1c";
when "01" & x"171" => data <= x"11";
when "01" & x"172" => data <= x"85";
when "01" & x"173" => data <= x"c5";
when "01" & x"174" => data <= x"b9";
when "01" & x"175" => data <= x"1d";
when "01" & x"176" => data <= x"11";
when "01" & x"177" => data <= x"85";
when "01" & x"178" => data <= x"c4";
when "01" & x"179" => data <= x"20";
when "01" & x"17a" => data <= x"8f";
when "01" & x"17b" => data <= x"87";
when "01" & x"17c" => data <= x"ac";
when "01" & x"17d" => data <= x"c2";
when "01" & x"17e" => data <= x"10";
when "01" & x"17f" => data <= x"a9";
when "01" & x"180" => data <= x"bf";
when "01" & x"181" => data <= x"20";
when "01" & x"182" => data <= x"43";
when "01" & x"183" => data <= x"91";
when "01" & x"184" => data <= x"90";
when "01" & x"185" => data <= x"06";
when "01" & x"186" => data <= x"20";
when "01" & x"187" => data <= x"21";
when "01" & x"188" => data <= x"91";
when "01" & x"189" => data <= x"20";
when "01" & x"18a" => data <= x"c6";
when "01" & x"18b" => data <= x"87";
when "01" & x"18c" => data <= x"ac";
when "01" & x"18d" => data <= x"c2";
when "01" & x"18e" => data <= x"10";
when "01" & x"18f" => data <= x"60";
when "01" & x"190" => data <= x"4c";
when "01" & x"191" => data <= x"ad";
when "01" & x"192" => data <= x"90";
when "01" & x"193" => data <= x"4c";
when "01" & x"194" => data <= x"41";
when "01" & x"195" => data <= x"98";
when "01" & x"196" => data <= x"20";
when "01" & x"197" => data <= x"2b";
when "01" & x"198" => data <= x"80";
when "01" & x"199" => data <= x"c1";
when "01" & x"19a" => data <= x"72";
when "01" & x"19b" => data <= x"65";
when "01" & x"19c" => data <= x"61";
when "01" & x"19d" => data <= x"64";
when "01" & x"19e" => data <= x"20";
when "01" & x"19f" => data <= x"6f";
when "01" & x"1a0" => data <= x"6e";
when "01" & x"1a1" => data <= x"6c";
when "01" & x"1a2" => data <= x"79";
when "01" & x"1a3" => data <= x"00";
when "01" & x"1a4" => data <= x"20";
when "01" & x"1a5" => data <= x"e1";
when "01" & x"1a6" => data <= x"83";
when "01" & x"1a7" => data <= x"4c";
when "01" & x"1a8" => data <= x"b0";
when "01" & x"1a9" => data <= x"91";
when "01" & x"1aa" => data <= x"20";
when "01" & x"1ab" => data <= x"e1";
when "01" & x"1ac" => data <= x"83";
when "01" & x"1ad" => data <= x"20";
when "01" & x"1ae" => data <= x"a5";
when "01" & x"1af" => data <= x"90";
when "01" & x"1b0" => data <= x"48";
when "01" & x"1b1" => data <= x"b9";
when "01" & x"1b2" => data <= x"0c";
when "01" & x"1b3" => data <= x"11";
when "01" & x"1b4" => data <= x"30";
when "01" & x"1b5" => data <= x"e0";
when "01" & x"1b6" => data <= x"b9";
when "01" & x"1b7" => data <= x"0e";
when "01" & x"1b8" => data <= x"11";
when "01" & x"1b9" => data <= x"30";
when "01" & x"1ba" => data <= x"d8";
when "01" & x"1bb" => data <= x"20";
when "01" & x"1bc" => data <= x"83";
when "01" & x"1bd" => data <= x"8e";
when "01" & x"1be" => data <= x"98";
when "01" & x"1bf" => data <= x"18";
when "01" & x"1c0" => data <= x"69";
when "01" & x"1c1" => data <= x"04";
when "01" & x"1c2" => data <= x"20";
when "01" & x"1c3" => data <= x"f8";
when "01" & x"1c4" => data <= x"92";
when "01" & x"1c5" => data <= x"d0";
when "01" & x"1c6" => data <= x"76";
when "01" & x"1c7" => data <= x"20";
when "01" & x"1c8" => data <= x"58";
when "01" & x"1c9" => data <= x"8e";
when "01" & x"1ca" => data <= x"ae";
when "01" & x"1cb" => data <= x"c4";
when "01" & x"1cc" => data <= x"10";
when "01" & x"1cd" => data <= x"38";
when "01" & x"1ce" => data <= x"bd";
when "01" & x"1cf" => data <= x"07";
when "01" & x"1d0" => data <= x"0f";
when "01" & x"1d1" => data <= x"fd";
when "01" & x"1d2" => data <= x"0f";
when "01" & x"1d3" => data <= x"0f";
when "01" & x"1d4" => data <= x"48";
when "01" & x"1d5" => data <= x"bd";
when "01" & x"1d6" => data <= x"06";
when "01" & x"1d7" => data <= x"0f";
when "01" & x"1d8" => data <= x"fd";
when "01" & x"1d9" => data <= x"0e";
when "01" & x"1da" => data <= x"0f";
when "01" & x"1db" => data <= x"29";
when "01" & x"1dc" => data <= x"03";
when "01" & x"1dd" => data <= x"8d";
when "01" & x"1de" => data <= x"c3";
when "01" & x"1df" => data <= x"10";
when "01" & x"1e0" => data <= x"0a";
when "01" & x"1e1" => data <= x"0a";
when "01" & x"1e2" => data <= x"0a";
when "01" & x"1e3" => data <= x"0a";
when "01" & x"1e4" => data <= x"5d";
when "01" & x"1e5" => data <= x"0e";
when "01" & x"1e6" => data <= x"0f";
when "01" & x"1e7" => data <= x"29";
when "01" & x"1e8" => data <= x"30";
when "01" & x"1e9" => data <= x"5d";
when "01" & x"1ea" => data <= x"0e";
when "01" & x"1eb" => data <= x"0f";
when "01" & x"1ec" => data <= x"9d";
when "01" & x"1ed" => data <= x"0e";
when "01" & x"1ee" => data <= x"0f";
when "01" & x"1ef" => data <= x"ad";
when "01" & x"1f0" => data <= x"c3";
when "01" & x"1f1" => data <= x"10";
when "01" & x"1f2" => data <= x"d9";
when "01" & x"1f3" => data <= x"1a";
when "01" & x"1f4" => data <= x"11";
when "01" & x"1f5" => data <= x"d0";
when "01" & x"1f6" => data <= x"2b";
when "01" & x"1f7" => data <= x"68";
when "01" & x"1f8" => data <= x"d9";
when "01" & x"1f9" => data <= x"19";
when "01" & x"1fa" => data <= x"11";
when "01" & x"1fb" => data <= x"d0";
when "01" & x"1fc" => data <= x"26";
when "01" & x"1fd" => data <= x"84";
when "01" & x"1fe" => data <= x"b4";
when "01" & x"1ff" => data <= x"20";
when "01" & x"200" => data <= x"20";
when "01" & x"201" => data <= x"99";
when "01" & x"202" => data <= x"20";
when "01" & x"203" => data <= x"76";
when "01" & x"204" => data <= x"90";
when "01" & x"205" => data <= x"c4";
when "01" & x"206" => data <= x"b4";
when "01" & x"207" => data <= x"d0";
when "01" & x"208" => data <= x"03";
when "01" & x"209" => data <= x"20";
when "01" & x"20a" => data <= x"11";
when "01" & x"20b" => data <= x"99";
when "01" & x"20c" => data <= x"a4";
when "01" & x"20d" => data <= x"b4";
when "01" & x"20e" => data <= x"20";
when "01" & x"20f" => data <= x"05";
when "01" & x"210" => data <= x"8e";
when "01" & x"211" => data <= x"20";
when "01" & x"212" => data <= x"33";
when "01" & x"213" => data <= x"80";
when "01" & x"214" => data <= x"bf";
when "01" & x"215" => data <= x"43";
when "01" & x"216" => data <= x"61";
when "01" & x"217" => data <= x"6e";
when "01" & x"218" => data <= x"27";
when "01" & x"219" => data <= x"74";
when "01" & x"21a" => data <= x"20";
when "01" & x"21b" => data <= x"65";
when "01" & x"21c" => data <= x"78";
when "01" & x"21d" => data <= x"74";
when "01" & x"21e" => data <= x"65";
when "01" & x"21f" => data <= x"6e";
when "01" & x"220" => data <= x"64";
when "01" & x"221" => data <= x"00";
when "01" & x"222" => data <= x"68";
when "01" & x"223" => data <= x"9d";
when "01" & x"224" => data <= x"0d";
when "01" & x"225" => data <= x"0f";
when "01" & x"226" => data <= x"99";
when "01" & x"227" => data <= x"19";
when "01" & x"228" => data <= x"11";
when "01" & x"229" => data <= x"ad";
when "01" & x"22a" => data <= x"c3";
when "01" & x"22b" => data <= x"10";
when "01" & x"22c" => data <= x"99";
when "01" & x"22d" => data <= x"1a";
when "01" & x"22e" => data <= x"11";
when "01" & x"22f" => data <= x"a9";
when "01" & x"230" => data <= x"00";
when "01" & x"231" => data <= x"9d";
when "01" & x"232" => data <= x"0c";
when "01" & x"233" => data <= x"0f";
when "01" & x"234" => data <= x"20";
when "01" & x"235" => data <= x"b4";
when "01" & x"236" => data <= x"8a";
when "01" & x"237" => data <= x"ea";
when "01" & x"238" => data <= x"ea";
when "01" & x"239" => data <= x"ea";
when "01" & x"23a" => data <= x"ac";
when "01" & x"23b" => data <= x"c2";
when "01" & x"23c" => data <= x"10";
when "01" & x"23d" => data <= x"b9";
when "01" & x"23e" => data <= x"17";
when "01" & x"23f" => data <= x"11";
when "01" & x"240" => data <= x"30";
when "01" & x"241" => data <= x"17";
when "01" & x"242" => data <= x"20";
when "01" & x"243" => data <= x"4b";
when "01" & x"244" => data <= x"91";
when "01" & x"245" => data <= x"b9";
when "01" & x"246" => data <= x"14";
when "01" & x"247" => data <= x"11";
when "01" & x"248" => data <= x"d0";
when "01" & x"249" => data <= x"0b";
when "01" & x"24a" => data <= x"98";
when "01" & x"24b" => data <= x"20";
when "01" & x"24c" => data <= x"f8";
when "01" & x"24d" => data <= x"92";
when "01" & x"24e" => data <= x"d0";
when "01" & x"24f" => data <= x"05";
when "01" & x"250" => data <= x"20";
when "01" & x"251" => data <= x"21";
when "01" & x"252" => data <= x"91";
when "01" & x"253" => data <= x"d0";
when "01" & x"254" => data <= x"04";
when "01" & x"255" => data <= x"38";
when "01" & x"256" => data <= x"20";
when "01" & x"257" => data <= x"53";
when "01" & x"258" => data <= x"91";
when "01" & x"259" => data <= x"b9";
when "01" & x"25a" => data <= x"10";
when "01" & x"25b" => data <= x"11";
when "01" & x"25c" => data <= x"85";
when "01" & x"25d" => data <= x"bc";
when "01" & x"25e" => data <= x"b9";
when "01" & x"25f" => data <= x"13";
when "01" & x"260" => data <= x"11";
when "01" & x"261" => data <= x"85";
when "01" & x"262" => data <= x"bd";
when "01" & x"263" => data <= x"68";
when "01" & x"264" => data <= x"a0";
when "01" & x"265" => data <= x"00";
when "01" & x"266" => data <= x"91";
when "01" & x"267" => data <= x"bc";
when "01" & x"268" => data <= x"ac";
when "01" & x"269" => data <= x"c2";
when "01" & x"26a" => data <= x"10";
when "01" & x"26b" => data <= x"a9";
when "01" & x"26c" => data <= x"40";
when "01" & x"26d" => data <= x"20";
when "01" & x"26e" => data <= x"3c";
when "01" & x"26f" => data <= x"91";
when "01" & x"270" => data <= x"e6";
when "01" & x"271" => data <= x"bc";
when "01" & x"272" => data <= x"a5";
when "01" & x"273" => data <= x"bc";
when "01" & x"274" => data <= x"99";
when "01" & x"275" => data <= x"10";
when "01" & x"276" => data <= x"11";
when "01" & x"277" => data <= x"d0";
when "01" & x"278" => data <= x"13";
when "01" & x"279" => data <= x"20";
when "01" & x"27a" => data <= x"41";
when "01" & x"27b" => data <= x"91";
when "01" & x"27c" => data <= x"b9";
when "01" & x"27d" => data <= x"11";
when "01" & x"27e" => data <= x"11";
when "01" & x"27f" => data <= x"69";
when "01" & x"280" => data <= x"01";
when "01" & x"281" => data <= x"99";
when "01" & x"282" => data <= x"11";
when "01" & x"283" => data <= x"11";
when "01" & x"284" => data <= x"b9";
when "01" & x"285" => data <= x"12";
when "01" & x"286" => data <= x"11";
when "01" & x"287" => data <= x"69";
when "01" & x"288" => data <= x"00";
when "01" & x"289" => data <= x"99";
when "01" & x"28a" => data <= x"12";
when "01" & x"28b" => data <= x"11";
when "01" & x"28c" => data <= x"98";
when "01" & x"28d" => data <= x"20";
when "01" & x"28e" => data <= x"f8";
when "01" & x"28f" => data <= x"92";
when "01" & x"290" => data <= x"90";
when "01" & x"291" => data <= x"14";
when "01" & x"292" => data <= x"a9";
when "01" & x"293" => data <= x"20";
when "01" & x"294" => data <= x"20";
when "01" & x"295" => data <= x"3c";
when "01" & x"296" => data <= x"91";
when "01" & x"297" => data <= x"a2";
when "01" & x"298" => data <= x"02";
when "01" & x"299" => data <= x"b9";
when "01" & x"29a" => data <= x"10";
when "01" & x"29b" => data <= x"11";
when "01" & x"29c" => data <= x"99";
when "01" & x"29d" => data <= x"14";
when "01" & x"29e" => data <= x"11";
when "01" & x"29f" => data <= x"c8";
when "01" & x"2a0" => data <= x"ca";
when "01" & x"2a1" => data <= x"10";
when "01" & x"2a2" => data <= x"f6";
when "01" & x"2a3" => data <= x"88";
when "01" & x"2a4" => data <= x"88";
when "01" & x"2a5" => data <= x"88";
when "01" & x"2a6" => data <= x"60";
when "01" & x"2a7" => data <= x"20";
when "01" & x"2a8" => data <= x"e1";
when "01" & x"2a9" => data <= x"83";
when "01" & x"2aa" => data <= x"20";
when "01" & x"2ab" => data <= x"a5";
when "01" & x"2ac" => data <= x"90";
when "01" & x"2ad" => data <= x"20";
when "01" & x"2ae" => data <= x"63";
when "01" & x"2af" => data <= x"a1";
when "01" & x"2b0" => data <= x"ea";
when "01" & x"2b1" => data <= x"ea";
when "01" & x"2b2" => data <= x"ea";
when "01" & x"2b3" => data <= x"ea";
when "01" & x"2b4" => data <= x"ea";
when "01" & x"2b5" => data <= x"ea";
when "01" & x"2b6" => data <= x"20";
when "01" & x"2b7" => data <= x"10";
when "01" & x"2b8" => data <= x"93";
when "01" & x"2b9" => data <= x"b0";
when "01" & x"2ba" => data <= x"08";
when "01" & x"2bb" => data <= x"a9";
when "01" & x"2bc" => data <= x"00";
when "01" & x"2bd" => data <= x"20";
when "01" & x"2be" => data <= x"a4";
when "01" & x"2bf" => data <= x"91";
when "01" & x"2c0" => data <= x"4c";
when "01" & x"2c1" => data <= x"b6";
when "01" & x"2c2" => data <= x"92";
when "01" & x"2c3" => data <= x"b5";
when "01" & x"2c4" => data <= x"00";
when "01" & x"2c5" => data <= x"99";
when "01" & x"2c6" => data <= x"10";
when "01" & x"2c7" => data <= x"11";
when "01" & x"2c8" => data <= x"b5";
when "01" & x"2c9" => data <= x"01";
when "01" & x"2ca" => data <= x"99";
when "01" & x"2cb" => data <= x"11";
when "01" & x"2cc" => data <= x"11";
when "01" & x"2cd" => data <= x"b5";
when "01" & x"2ce" => data <= x"02";
when "01" & x"2cf" => data <= x"99";
when "01" & x"2d0" => data <= x"12";
when "01" & x"2d1" => data <= x"11";
when "01" & x"2d2" => data <= x"a9";
when "01" & x"2d3" => data <= x"6f";
when "01" & x"2d4" => data <= x"20";
when "01" & x"2d5" => data <= x"43";
when "01" & x"2d6" => data <= x"91";
when "01" & x"2d7" => data <= x"b9";
when "01" & x"2d8" => data <= x"0f";
when "01" & x"2d9" => data <= x"11";
when "01" & x"2da" => data <= x"79";
when "01" & x"2db" => data <= x"11";
when "01" & x"2dc" => data <= x"11";
when "01" & x"2dd" => data <= x"8d";
when "01" & x"2de" => data <= x"c5";
when "01" & x"2df" => data <= x"10";
when "01" & x"2e0" => data <= x"b9";
when "01" & x"2e1" => data <= x"0d";
when "01" & x"2e2" => data <= x"11";
when "01" & x"2e3" => data <= x"29";
when "01" & x"2e4" => data <= x"03";
when "01" & x"2e5" => data <= x"79";
when "01" & x"2e6" => data <= x"12";
when "01" & x"2e7" => data <= x"11";
when "01" & x"2e8" => data <= x"d9";
when "01" & x"2e9" => data <= x"1d";
when "01" & x"2ea" => data <= x"11";
when "01" & x"2eb" => data <= x"d0";
when "01" & x"2ec" => data <= x"b9";
when "01" & x"2ed" => data <= x"ad";
when "01" & x"2ee" => data <= x"c5";
when "01" & x"2ef" => data <= x"10";
when "01" & x"2f0" => data <= x"d9";
when "01" & x"2f1" => data <= x"1c";
when "01" & x"2f2" => data <= x"11";
when "01" & x"2f3" => data <= x"d0";
when "01" & x"2f4" => data <= x"b1";
when "01" & x"2f5" => data <= x"4c";
when "01" & x"2f6" => data <= x"3a";
when "01" & x"2f7" => data <= x"91";
when "01" & x"2f8" => data <= x"aa";
when "01" & x"2f9" => data <= x"b9";
when "01" & x"2fa" => data <= x"12";
when "01" & x"2fb" => data <= x"11";
when "01" & x"2fc" => data <= x"dd";
when "01" & x"2fd" => data <= x"16";
when "01" & x"2fe" => data <= x"11";
when "01" & x"2ff" => data <= x"d0";
when "01" & x"300" => data <= x"0e";
when "01" & x"301" => data <= x"b9";
when "01" & x"302" => data <= x"11";
when "01" & x"303" => data <= x"11";
when "01" & x"304" => data <= x"dd";
when "01" & x"305" => data <= x"15";
when "01" & x"306" => data <= x"11";
when "01" & x"307" => data <= x"d0";
when "01" & x"308" => data <= x"06";
when "01" & x"309" => data <= x"b9";
when "01" & x"30a" => data <= x"10";
when "01" & x"30b" => data <= x"11";
when "01" & x"30c" => data <= x"dd";
when "01" & x"30d" => data <= x"14";
when "01" & x"30e" => data <= x"11";
when "01" & x"30f" => data <= x"60";
when "01" & x"310" => data <= x"b9";
when "01" & x"311" => data <= x"14";
when "01" & x"312" => data <= x"11";
when "01" & x"313" => data <= x"d5";
when "01" & x"314" => data <= x"00";
when "01" & x"315" => data <= x"b9";
when "01" & x"316" => data <= x"15";
when "01" & x"317" => data <= x"11";
when "01" & x"318" => data <= x"f5";
when "01" & x"319" => data <= x"01";
when "01" & x"31a" => data <= x"b9";
when "01" & x"31b" => data <= x"16";
when "01" & x"31c" => data <= x"11";
when "01" & x"31d" => data <= x"f5";
when "01" & x"31e" => data <= x"02";
when "01" & x"31f" => data <= x"60";
when "01" & x"320" => data <= x"a5";
when "01" & x"321" => data <= x"b3";
when "01" & x"322" => data <= x"48";
when "01" & x"323" => data <= x"a9";
when "01" & x"324" => data <= x"ff";
when "01" & x"325" => data <= x"8d";
when "01" & x"326" => data <= x"de";
when "01" & x"327" => data <= x"10";
when "01" & x"328" => data <= x"20";
when "01" & x"329" => data <= x"65";
when "01" & x"32a" => data <= x"80";
when "01" & x"32b" => data <= x"53";
when "01" & x"32c" => data <= x"6d";
when "01" & x"32d" => data <= x"61";
when "01" & x"32e" => data <= x"72";
when "01" & x"32f" => data <= x"74";
when "01" & x"330" => data <= x"20";
when "01" & x"331" => data <= x"53";
when "01" & x"332" => data <= x"50";
when "01" & x"333" => data <= x"49";
when "01" & x"334" => data <= x"0d";
when "01" & x"335" => data <= x"0d";
when "01" & x"336" => data <= x"90";
when "01" & x"337" => data <= x"03";
when "01" & x"338" => data <= x"4c";
when "01" & x"339" => data <= x"28";
when "01" & x"33a" => data <= x"b1";
when "01" & x"33b" => data <= x"a9";
when "01" & x"33c" => data <= x"00";
when "01" & x"33d" => data <= x"ba";
when "01" & x"33e" => data <= x"9d";
when "01" & x"33f" => data <= x"06";
when "01" & x"340" => data <= x"01";
when "01" & x"341" => data <= x"a9";
when "01" & x"342" => data <= x"06";
when "01" & x"343" => data <= x"20";
when "01" & x"344" => data <= x"15";
when "01" & x"345" => data <= x"80";
when "01" & x"346" => data <= x"a2";
when "01" & x"347" => data <= x"0d";
when "01" & x"348" => data <= x"bd";
when "01" & x"349" => data <= x"49";
when "01" & x"34a" => data <= x"99";
when "01" & x"34b" => data <= x"9d";
when "01" & x"34c" => data <= x"12";
when "01" & x"34d" => data <= x"02";
when "01" & x"34e" => data <= x"ca";
when "01" & x"34f" => data <= x"10";
when "01" & x"350" => data <= x"f7";
when "01" & x"351" => data <= x"20";
when "01" & x"352" => data <= x"28";
when "01" & x"353" => data <= x"99";
when "01" & x"354" => data <= x"84";
when "01" & x"355" => data <= x"b1";
when "01" & x"356" => data <= x"86";
when "01" & x"357" => data <= x"b0";
when "01" & x"358" => data <= x"a2";
when "01" & x"359" => data <= x"07";
when "01" & x"35a" => data <= x"a0";
when "01" & x"35b" => data <= x"1b";
when "01" & x"35c" => data <= x"b9";
when "01" & x"35d" => data <= x"3c";
when "01" & x"35e" => data <= x"99";
when "01" & x"35f" => data <= x"91";
when "01" & x"360" => data <= x"b0";
when "01" & x"361" => data <= x"c8";
when "01" & x"362" => data <= x"b9";
when "01" & x"363" => data <= x"3c";
when "01" & x"364" => data <= x"99";
when "01" & x"365" => data <= x"91";
when "01" & x"366" => data <= x"b0";
when "01" & x"367" => data <= x"c8";
when "01" & x"368" => data <= x"a5";
when "01" & x"369" => data <= x"f4";
when "01" & x"36a" => data <= x"91";
when "01" & x"36b" => data <= x"b0";
when "01" & x"36c" => data <= x"c8";
when "01" & x"36d" => data <= x"ca";
when "01" & x"36e" => data <= x"d0";
when "01" & x"36f" => data <= x"ec";
when "01" & x"370" => data <= x"86";
when "01" & x"371" => data <= x"cf";
when "01" & x"372" => data <= x"8c";
when "01" & x"373" => data <= x"82";
when "01" & x"374" => data <= x"10";
when "01" & x"375" => data <= x"a2";
when "01" & x"376" => data <= x"0f";
when "01" & x"377" => data <= x"20";
when "01" & x"378" => data <= x"2c";
when "01" & x"379" => data <= x"99";
when "01" & x"37a" => data <= x"20";
when "01" & x"37b" => data <= x"9e";
when "01" & x"37c" => data <= x"98";
when "01" & x"37d" => data <= x"a0";
when "01" & x"37e" => data <= x"d4";
when "01" & x"37f" => data <= x"b1";
when "01" & x"380" => data <= x"b0";
when "01" & x"381" => data <= x"10";
when "01" & x"382" => data <= x"2f";
when "01" & x"383" => data <= x"a0";
when "01" & x"384" => data <= x"d5";
when "01" & x"385" => data <= x"b1";
when "01" & x"386" => data <= x"b0";
when "01" & x"387" => data <= x"30";
when "01" & x"388" => data <= x"27";
when "01" & x"389" => data <= x"20";
when "01" & x"38a" => data <= x"8f";
when "01" & x"38b" => data <= x"98";
when "01" & x"38c" => data <= x"a0";
when "01" & x"38d" => data <= x"00";
when "01" & x"38e" => data <= x"b1";
when "01" & x"38f" => data <= x"b0";
when "01" & x"390" => data <= x"c0";
when "01" & x"391" => data <= x"c0";
when "01" & x"392" => data <= x"90";
when "01" & x"393" => data <= x"05";
when "01" & x"394" => data <= x"99";
when "01" & x"395" => data <= x"00";
when "01" & x"396" => data <= x"10";
when "01" & x"397" => data <= x"b0";
when "01" & x"398" => data <= x"03";
when "01" & x"399" => data <= x"99";
when "01" & x"39a" => data <= x"00";
when "01" & x"39b" => data <= x"11";
when "01" & x"39c" => data <= x"88";
when "01" & x"39d" => data <= x"d0";
when "01" & x"39e" => data <= x"ef";
when "01" & x"39f" => data <= x"a9";
when "01" & x"3a0" => data <= x"a0";
when "01" & x"3a1" => data <= x"a8";
when "01" & x"3a2" => data <= x"48";
when "01" & x"3a3" => data <= x"a9";
when "01" & x"3a4" => data <= x"3f";
when "01" & x"3a5" => data <= x"20";
when "01" & x"3a6" => data <= x"43";
when "01" & x"3a7" => data <= x"91";
when "01" & x"3a8" => data <= x"68";
when "01" & x"3a9" => data <= x"99";
when "01" & x"3aa" => data <= x"1d";
when "01" & x"3ab" => data <= x"11";
when "01" & x"3ac" => data <= x"e9";
when "01" & x"3ad" => data <= x"1f";
when "01" & x"3ae" => data <= x"d0";
when "01" & x"3af" => data <= x"f1";
when "01" & x"3b0" => data <= x"68";
when "01" & x"3b1" => data <= x"60";
when "01" & x"3b2" => data <= x"a9";
when "01" & x"3b3" => data <= x"ff";
when "01" & x"3b4" => data <= x"91";
when "01" & x"3b5" => data <= x"b0";
when "01" & x"3b6" => data <= x"8d";
when "01" & x"3b7" => data <= x"d4";
when "01" & x"3b8" => data <= x"10";
when "01" & x"3b9" => data <= x"20";
when "01" & x"3ba" => data <= x"8f";
when "01" & x"3bb" => data <= x"98";
when "01" & x"3bc" => data <= x"20";
when "01" & x"3bd" => data <= x"24";
when "01" & x"3be" => data <= x"99";
when "01" & x"3bf" => data <= x"8a";
when "01" & x"3c0" => data <= x"49";
when "01" & x"3c1" => data <= x"ff";
when "01" & x"3c2" => data <= x"8d";
when "01" & x"3c3" => data <= x"d7";
when "01" & x"3c4" => data <= x"10";
when "01" & x"3c5" => data <= x"a9";
when "01" & x"3c6" => data <= x"24";
when "01" & x"3c7" => data <= x"8d";
when "01" & x"3c8" => data <= x"ca";
when "01" & x"3c9" => data <= x"10";
when "01" & x"3ca" => data <= x"8d";
when "01" & x"3cb" => data <= x"cc";
when "01" & x"3cc" => data <= x"10";
when "01" & x"3cd" => data <= x"a0";
when "01" & x"3ce" => data <= x"00";
when "01" & x"3cf" => data <= x"8c";
when "01" & x"3d0" => data <= x"cb";
when "01" & x"3d1" => data <= x"10";
when "01" & x"3d2" => data <= x"8c";
when "01" & x"3d3" => data <= x"cd";
when "01" & x"3d4" => data <= x"10";
when "01" & x"3d5" => data <= x"a0";
when "01" & x"3d6" => data <= x"00";
when "01" & x"3d7" => data <= x"8c";
when "01" & x"3d8" => data <= x"c0";
when "01" & x"3d9" => data <= x"10";
when "01" & x"3da" => data <= x"8c";
when "01" & x"3db" => data <= x"c9";
when "01" & x"3dc" => data <= x"10";
when "01" & x"3dd" => data <= x"88";
when "01" & x"3de" => data <= x"8c";
when "01" & x"3df" => data <= x"c8";
when "01" & x"3e0" => data <= x"10";
when "01" & x"3e1" => data <= x"8c";
when "01" & x"3e2" => data <= x"c7";
when "01" & x"3e3" => data <= x"10";
when "01" & x"3e4" => data <= x"8c";
when "01" & x"3e5" => data <= x"de";
when "01" & x"3e6" => data <= x"10";
when "01" & x"3e7" => data <= x"20";
when "01" & x"3e8" => data <= x"37";
when "01" & x"3e9" => data <= x"b1";
when "01" & x"3ea" => data <= x"4c";
when "01" & x"3eb" => data <= x"04";
when "01" & x"3ec" => data <= x"94";
when "01" & x"3ed" => data <= x"00";
when "01" & x"3ee" => data <= x"00";
when "01" & x"3ef" => data <= x"00";
when "01" & x"3f0" => data <= x"00";
when "01" & x"3f1" => data <= x"00";
when "01" & x"3f2" => data <= x"00";
when "01" & x"3f3" => data <= x"00";
when "01" & x"3f4" => data <= x"00";
when "01" & x"3f5" => data <= x"00";
when "01" & x"3f6" => data <= x"00";
when "01" & x"3f7" => data <= x"00";
when "01" & x"3f8" => data <= x"00";
when "01" & x"3f9" => data <= x"00";
when "01" & x"3fa" => data <= x"00";
when "01" & x"3fb" => data <= x"00";
when "01" & x"3fc" => data <= x"00";
when "01" & x"3fd" => data <= x"00";
when "01" & x"3fe" => data <= x"00";
when "01" & x"3ff" => data <= x"00";
when "01" & x"400" => data <= x"00";
when "01" & x"401" => data <= x"00";
when "01" & x"402" => data <= x"00";
when "01" & x"403" => data <= x"00";
when "01" & x"404" => data <= x"68";
when "01" & x"405" => data <= x"d0";
when "01" & x"406" => data <= x"34";
when "01" & x"407" => data <= x"20";
when "01" & x"408" => data <= x"41";
when "01" & x"409" => data <= x"af";
when "01" & x"40a" => data <= x"a0";
when "01" & x"40b" => data <= x"00";
when "01" & x"40c" => data <= x"a2";
when "01" & x"40d" => data <= x"00";
when "01" & x"40e" => data <= x"ad";
when "01" & x"40f" => data <= x"06";
when "01" & x"410" => data <= x"0f";
when "01" & x"411" => data <= x"20";
when "01" & x"412" => data <= x"05";
when "01" & x"413" => data <= x"82";
when "01" & x"414" => data <= x"f0";
when "01" & x"415" => data <= x"25";
when "01" & x"416" => data <= x"48";
when "01" & x"417" => data <= x"a2";
when "01" & x"418" => data <= x"43";
when "01" & x"419" => data <= x"a0";
when "01" & x"41a" => data <= x"99";
when "01" & x"41b" => data <= x"20";
when "01" & x"41c" => data <= x"b8";
when "01" & x"41d" => data <= x"86";
when "01" & x"41e" => data <= x"20";
when "01" & x"41f" => data <= x"fe";
when "01" & x"420" => data <= x"80";
when "01" & x"421" => data <= x"20";
when "01" & x"422" => data <= x"96";
when "01" & x"423" => data <= x"82";
when "01" & x"424" => data <= x"68";
when "01" & x"425" => data <= x"b0";
when "01" & x"426" => data <= x"15";
when "01" & x"427" => data <= x"20";
when "01" & x"428" => data <= x"65";
when "01" & x"429" => data <= x"80";
when "01" & x"42a" => data <= x"46";
when "01" & x"42b" => data <= x"69";
when "01" & x"42c" => data <= x"6c";
when "01" & x"42d" => data <= x"65";
when "01" & x"42e" => data <= x"20";
when "01" & x"42f" => data <= x"6e";
when "01" & x"430" => data <= x"6f";
when "01" & x"431" => data <= x"74";
when "01" & x"432" => data <= x"20";
when "01" & x"433" => data <= x"66";
when "01" & x"434" => data <= x"6f";
when "01" & x"435" => data <= x"75";
when "01" & x"436" => data <= x"6e";
when "01" & x"437" => data <= x"64";
when "01" & x"438" => data <= x"0d";
when "01" & x"439" => data <= x"0d";
when "01" & x"43a" => data <= x"ea";
when "01" & x"43b" => data <= x"60";
when "01" & x"43c" => data <= x"c9";
when "01" & x"43d" => data <= x"02";
when "01" & x"43e" => data <= x"90";
when "01" & x"43f" => data <= x"0e";
when "01" & x"440" => data <= x"f0";
when "01" & x"441" => data <= x"06";
when "01" & x"442" => data <= x"a2";
when "01" & x"443" => data <= x"41";
when "01" & x"444" => data <= x"a0";
when "01" & x"445" => data <= x"99";
when "01" & x"446" => data <= x"d0";
when "01" & x"447" => data <= x"0a";
when "01" & x"448" => data <= x"a2";
when "01" & x"449" => data <= x"43";
when "01" & x"44a" => data <= x"a0";
when "01" & x"44b" => data <= x"99";
when "01" & x"44c" => data <= x"d0";
when "01" & x"44d" => data <= x"04";
when "01" & x"44e" => data <= x"a2";
when "01" & x"44f" => data <= x"39";
when "01" & x"450" => data <= x"a0";
when "01" & x"451" => data <= x"99";
when "01" & x"452" => data <= x"4c";
when "01" & x"453" => data <= x"f7";
when "01" & x"454" => data <= x"ff";
when "01" & x"455" => data <= x"c9";
when "01" & x"456" => data <= x"01";
when "01" & x"457" => data <= x"d0";
when "01" & x"458" => data <= x"07";
when "01" & x"459" => data <= x"c0";
when "01" & x"45a" => data <= x"17";
when "01" & x"45b" => data <= x"b0";
when "01" & x"45c" => data <= x"02";
when "01" & x"45d" => data <= x"a0";
when "01" & x"45e" => data <= x"17";
when "01" & x"45f" => data <= x"60";
when "01" & x"460" => data <= x"c9";
when "01" & x"461" => data <= x"02";
when "01" & x"462" => data <= x"d0";
when "01" & x"463" => data <= x"1a";
when "01" & x"464" => data <= x"48";
when "01" & x"465" => data <= x"69";
when "01" & x"466" => data <= x"12";
when "01" & x"467" => data <= x"85";
when "01" & x"468" => data <= x"b1";
when "01" & x"469" => data <= x"9d";
when "01" & x"46a" => data <= x"f0";
when "01" & x"46b" => data <= x"0d";
when "01" & x"46c" => data <= x"98";
when "01" & x"46d" => data <= x"ea";
when "01" & x"46e" => data <= x"48";
when "01" & x"46f" => data <= x"a9";
when "01" & x"470" => data <= x"00";
when "01" & x"471" => data <= x"85";
when "01" & x"472" => data <= x"b0";
when "01" & x"473" => data <= x"a0";
when "01" & x"474" => data <= x"d4";
when "01" & x"475" => data <= x"91";
when "01" & x"476" => data <= x"b0";
when "01" & x"477" => data <= x"c8";
when "01" & x"478" => data <= x"91";
when "01" & x"479" => data <= x"b0";
when "01" & x"47a" => data <= x"68";
when "01" & x"47b" => data <= x"a8";
when "01" & x"47c" => data <= x"68";
when "01" & x"47d" => data <= x"60";
when "01" & x"47e" => data <= x"c9";
when "01" & x"47f" => data <= x"03";
when "01" & x"480" => data <= x"d0";
when "01" & x"481" => data <= x"19";
when "01" & x"482" => data <= x"84";
when "01" & x"483" => data <= x"b3";
when "01" & x"484" => data <= x"20";
when "01" & x"485" => data <= x"e1";
when "01" & x"486" => data <= x"83";
when "01" & x"487" => data <= x"4c";
when "01" & x"488" => data <= x"8f";
when "01" & x"489" => data <= x"a9";
when "01" & x"48a" => data <= x"f4";
when "01" & x"48b" => data <= x"ff";
when "01" & x"48c" => data <= x"8a";
when "01" & x"48d" => data <= x"30";
when "01" & x"48e" => data <= x"09";
when "01" & x"48f" => data <= x"c9";
when "01" & x"490" => data <= x"32";
when "01" & x"491" => data <= x"d0";
when "01" & x"492" => data <= x"ea";
when "01" & x"493" => data <= x"a9";
when "01" & x"494" => data <= x"78";
when "01" & x"495" => data <= x"20";
when "01" & x"496" => data <= x"f4";
when "01" & x"497" => data <= x"ff";
when "01" & x"498" => data <= x"4c";
when "01" & x"499" => data <= x"20";
when "01" & x"49a" => data <= x"93";
when "01" & x"49b" => data <= x"c9";
when "01" & x"49c" => data <= x"04";
when "01" & x"49d" => data <= x"d0";
when "01" & x"49e" => data <= x"08";
when "01" & x"49f" => data <= x"20";
when "01" & x"4a0" => data <= x"e1";
when "01" & x"4a1" => data <= x"83";
when "01" & x"4a2" => data <= x"a2";
when "01" & x"4a3" => data <= x"72";
when "01" & x"4a4" => data <= x"4c";
when "01" & x"4a5" => data <= x"71";
when "01" & x"4a6" => data <= x"86";
when "01" & x"4a7" => data <= x"c9";
when "01" & x"4a8" => data <= x"09";
when "01" & x"4a9" => data <= x"d0";
when "01" & x"4aa" => data <= x"12";
when "01" & x"4ab" => data <= x"20";
when "01" & x"4ac" => data <= x"e1";
when "01" & x"4ad" => data <= x"83";
when "01" & x"4ae" => data <= x"4c";
when "01" & x"4af" => data <= x"cc";
when "01" & x"4b0" => data <= x"b3";
when "01" & x"4b1" => data <= x"a0";
when "01" & x"4b2" => data <= x"c9";
when "01" & x"4b3" => data <= x"0d";
when "01" & x"4b4" => data <= x"d0";
when "01" & x"4b5" => data <= x"ee";
when "01" & x"4b6" => data <= x"98";
when "01" & x"4b7" => data <= x"e8";
when "01" & x"4b8" => data <= x"a0";
when "01" & x"4b9" => data <= x"02";
when "01" & x"4ba" => data <= x"4c";
when "01" & x"4bb" => data <= x"cb";
when "01" & x"4bc" => data <= x"99";
when "01" & x"4bd" => data <= x"c9";
when "01" & x"4be" => data <= x"0a";
when "01" & x"4bf" => data <= x"d0";
when "01" & x"4c0" => data <= x"29";
when "01" & x"4c1" => data <= x"20";
when "01" & x"4c2" => data <= x"e1";
when "01" & x"4c3" => data <= x"83";
when "01" & x"4c4" => data <= x"20";
when "01" & x"4c5" => data <= x"9e";
when "01" & x"4c6" => data <= x"98";
when "01" & x"4c7" => data <= x"a0";
when "01" & x"4c8" => data <= x"d5";
when "01" & x"4c9" => data <= x"b1";
when "01" & x"4ca" => data <= x"b0";
when "01" & x"4cb" => data <= x"10";
when "01" & x"4cc" => data <= x"1c";
when "01" & x"4cd" => data <= x"a0";
when "01" & x"4ce" => data <= x"00";
when "01" & x"4cf" => data <= x"c0";
when "01" & x"4d0" => data <= x"c0";
when "01" & x"4d1" => data <= x"90";
when "01" & x"4d2" => data <= x"05";
when "01" & x"4d3" => data <= x"b9";
when "01" & x"4d4" => data <= x"00";
when "01" & x"4d5" => data <= x"10";
when "01" & x"4d6" => data <= x"b0";
when "01" & x"4d7" => data <= x"03";
when "01" & x"4d8" => data <= x"b9";
when "01" & x"4d9" => data <= x"00";
when "01" & x"4da" => data <= x"11";
when "01" & x"4db" => data <= x"91";
when "01" & x"4dc" => data <= x"b0";
when "01" & x"4dd" => data <= x"88";
when "01" & x"4de" => data <= x"d0";
when "01" & x"4df" => data <= x"ef";
when "01" & x"4e0" => data <= x"20";
when "01" & x"4e1" => data <= x"f2";
when "01" & x"4e2" => data <= x"8f";
when "01" & x"4e3" => data <= x"a0";
when "01" & x"4e4" => data <= x"d5";
when "01" & x"4e5" => data <= x"a9";
when "01" & x"4e6" => data <= x"00";
when "01" & x"4e7" => data <= x"91";
when "01" & x"4e8" => data <= x"b0";
when "01" & x"4e9" => data <= x"60";
when "01" & x"4ea" => data <= x"c9";
when "01" & x"4eb" => data <= x"08";
when "01" & x"4ec" => data <= x"d0";
when "01" & x"4ed" => data <= x"15";
when "01" & x"4ee" => data <= x"20";
when "01" & x"4ef" => data <= x"11";
when "01" & x"4f0" => data <= x"84";
when "01" & x"4f1" => data <= x"a4";
when "01" & x"4f2" => data <= x"f0";
when "01" & x"4f3" => data <= x"84";
when "01" & x"4f4" => data <= x"b0";
when "01" & x"4f5" => data <= x"a4";
when "01" & x"4f6" => data <= x"f1";
when "01" & x"4f7" => data <= x"84";
when "01" & x"4f8" => data <= x"b1";
when "01" & x"4f9" => data <= x"a4";
when "01" & x"4fa" => data <= x"ef";
when "01" & x"4fb" => data <= x"c0";
when "01" & x"4fc" => data <= x"7f";
when "01" & x"4fd" => data <= x"d0";
when "01" & x"4fe" => data <= x"4c";
when "01" & x"4ff" => data <= x"4c";
when "01" & x"500" => data <= x"46";
when "01" & x"501" => data <= x"be";
when "01" & x"502" => data <= x"00";
when "01" & x"503" => data <= x"4c";
when "01" & x"504" => data <= x"f6";
when "01" & x"505" => data <= x"a0";
when "01" & x"506" => data <= x"00";
when "01" & x"507" => data <= x"00";
when "01" & x"508" => data <= x"00";
when "01" & x"509" => data <= x"00";
when "01" & x"50a" => data <= x"00";
when "01" & x"50b" => data <= x"00";
when "01" & x"50c" => data <= x"00";
when "01" & x"50d" => data <= x"00";
when "01" & x"50e" => data <= x"00";
when "01" & x"50f" => data <= x"00";
when "01" & x"510" => data <= x"00";
when "01" & x"511" => data <= x"00";
when "01" & x"512" => data <= x"00";
when "01" & x"513" => data <= x"00";
when "01" & x"514" => data <= x"00";
when "01" & x"515" => data <= x"00";
when "01" & x"516" => data <= x"00";
when "01" & x"517" => data <= x"00";
when "01" & x"518" => data <= x"00";
when "01" & x"519" => data <= x"00";
when "01" & x"51a" => data <= x"00";
when "01" & x"51b" => data <= x"00";
when "01" & x"51c" => data <= x"00";
when "01" & x"51d" => data <= x"00";
when "01" & x"51e" => data <= x"00";
when "01" & x"51f" => data <= x"00";
when "01" & x"520" => data <= x"00";
when "01" & x"521" => data <= x"00";
when "01" & x"522" => data <= x"00";
when "01" & x"523" => data <= x"00";
when "01" & x"524" => data <= x"00";
when "01" & x"525" => data <= x"00";
when "01" & x"526" => data <= x"00";
when "01" & x"527" => data <= x"00";
when "01" & x"528" => data <= x"00";
when "01" & x"529" => data <= x"00";
when "01" & x"52a" => data <= x"00";
when "01" & x"52b" => data <= x"00";
when "01" & x"52c" => data <= x"00";
when "01" & x"52d" => data <= x"00";
when "01" & x"52e" => data <= x"00";
when "01" & x"52f" => data <= x"00";
when "01" & x"530" => data <= x"00";
when "01" & x"531" => data <= x"00";
when "01" & x"532" => data <= x"00";
when "01" & x"533" => data <= x"00";
when "01" & x"534" => data <= x"00";
when "01" & x"535" => data <= x"00";
when "01" & x"536" => data <= x"00";
when "01" & x"537" => data <= x"00";
when "01" & x"538" => data <= x"00";
when "01" & x"539" => data <= x"00";
when "01" & x"53a" => data <= x"00";
when "01" & x"53b" => data <= x"00";
when "01" & x"53c" => data <= x"00";
when "01" & x"53d" => data <= x"00";
when "01" & x"53e" => data <= x"00";
when "01" & x"53f" => data <= x"00";
when "01" & x"540" => data <= x"00";
when "01" & x"541" => data <= x"00";
when "01" & x"542" => data <= x"00";
when "01" & x"543" => data <= x"00";
when "01" & x"544" => data <= x"00";
when "01" & x"545" => data <= x"00";
when "01" & x"546" => data <= x"00";
when "01" & x"547" => data <= x"00";
when "01" & x"548" => data <= x"00";
when "01" & x"549" => data <= x"00";
when "01" & x"54a" => data <= x"00";
when "01" & x"54b" => data <= x"c0";
when "01" & x"54c" => data <= x"7d";
when "01" & x"54d" => data <= x"90";
when "01" & x"54e" => data <= x"2b";
when "01" & x"54f" => data <= x"20";
when "01" & x"550" => data <= x"4d";
when "01" & x"551" => data <= x"83";
when "01" & x"552" => data <= x"20";
when "01" & x"553" => data <= x"47";
when "01" & x"554" => data <= x"83";
when "01" & x"555" => data <= x"c0";
when "01" & x"556" => data <= x"7e";
when "01" & x"557" => data <= x"f0";
when "01" & x"558" => data <= x"09";
when "01" & x"559" => data <= x"a0";
when "01" & x"55a" => data <= x"00";
when "01" & x"55b" => data <= x"ad";
when "01" & x"55c" => data <= x"04";
when "01" & x"55d" => data <= x"0f";
when "01" & x"55e" => data <= x"91";
when "01" & x"55f" => data <= x"b0";
when "01" & x"560" => data <= x"98";
when "01" & x"561" => data <= x"60";
when "01" & x"562" => data <= x"a9";
when "01" & x"563" => data <= x"00";
when "01" & x"564" => data <= x"a8";
when "01" & x"565" => data <= x"91";
when "01" & x"566" => data <= x"b0";
when "01" & x"567" => data <= x"c8";
when "01" & x"568" => data <= x"ad";
when "01" & x"569" => data <= x"07";
when "01" & x"56a" => data <= x"0f";
when "01" & x"56b" => data <= x"91";
when "01" & x"56c" => data <= x"b0";
when "01" & x"56d" => data <= x"c8";
when "01" & x"56e" => data <= x"ad";
when "01" & x"56f" => data <= x"06";
when "01" & x"570" => data <= x"0f";
when "01" & x"571" => data <= x"29";
when "01" & x"572" => data <= x"03";
when "01" & x"573" => data <= x"91";
when "01" & x"574" => data <= x"b0";
when "01" & x"575" => data <= x"c8";
when "01" & x"576" => data <= x"a9";
when "01" & x"577" => data <= x"00";
when "01" & x"578" => data <= x"91";
when "01" & x"579" => data <= x"b0";
when "01" & x"57a" => data <= x"60";
when "01" & x"57b" => data <= x"20";
when "01" & x"57c" => data <= x"11";
when "01" & x"57d" => data <= x"84";
when "01" & x"57e" => data <= x"48";
when "01" & x"57f" => data <= x"20";
when "01" & x"580" => data <= x"62";
when "01" & x"581" => data <= x"82";
when "01" & x"582" => data <= x"86";
when "01" & x"583" => data <= x"b0";
when "01" & x"584" => data <= x"8e";
when "01" & x"585" => data <= x"dc";
when "01" & x"586" => data <= x"10";
when "01" & x"587" => data <= x"84";
when "01" & x"588" => data <= x"b1";
when "01" & x"589" => data <= x"8c";
when "01" & x"58a" => data <= x"dd";
when "01" & x"58b" => data <= x"10";
when "01" & x"58c" => data <= x"a2";
when "01" & x"58d" => data <= x"00";
when "01" & x"58e" => data <= x"a0";
when "01" & x"58f" => data <= x"00";
when "01" & x"590" => data <= x"20";
when "01" & x"591" => data <= x"ea";
when "01" & x"592" => data <= x"80";
when "01" & x"593" => data <= x"20";
when "01" & x"594" => data <= x"da";
when "01" & x"595" => data <= x"80";
when "01" & x"596" => data <= x"c0";
when "01" & x"597" => data <= x"12";
when "01" & x"598" => data <= x"d0";
when "01" & x"599" => data <= x"f9";
when "01" & x"59a" => data <= x"68";
when "01" & x"59b" => data <= x"aa";
when "01" & x"59c" => data <= x"e8";
when "01" & x"59d" => data <= x"e0";
when "01" & x"59e" => data <= x"08";
when "01" & x"59f" => data <= x"b0";
when "01" & x"5a0" => data <= x"08";
when "01" & x"5a1" => data <= x"bd";
when "01" & x"5a2" => data <= x"8c";
when "01" & x"5a3" => data <= x"99";
when "01" & x"5a4" => data <= x"48";
when "01" & x"5a5" => data <= x"bd";
when "01" & x"5a6" => data <= x"84";
when "01" & x"5a7" => data <= x"99";
when "01" & x"5a8" => data <= x"48";
when "01" & x"5a9" => data <= x"60";
when "01" & x"5aa" => data <= x"c9";
when "01" & x"5ab" => data <= x"09";
when "01" & x"5ac" => data <= x"b0";
when "01" & x"5ad" => data <= x"fb";
when "01" & x"5ae" => data <= x"86";
when "01" & x"5af" => data <= x"b5";
when "01" & x"5b0" => data <= x"aa";
when "01" & x"5b1" => data <= x"bd";
when "01" & x"5b2" => data <= x"75";
when "01" & x"5b3" => data <= x"99";
when "01" & x"5b4" => data <= x"48";
when "01" & x"5b5" => data <= x"bd";
when "01" & x"5b6" => data <= x"6c";
when "01" & x"5b7" => data <= x"99";
when "01" & x"5b8" => data <= x"48";
when "01" & x"5b9" => data <= x"8a";
when "01" & x"5ba" => data <= x"a6";
when "01" & x"5bb" => data <= x"b5";
when "01" & x"5bc" => data <= x"60";
when "01" & x"5bd" => data <= x"a9";
when "01" & x"5be" => data <= x"ff";
when "01" & x"5bf" => data <= x"95";
when "01" & x"5c0" => data <= x"02";
when "01" & x"5c1" => data <= x"95";
when "01" & x"5c2" => data <= x"03";
when "01" & x"5c3" => data <= x"ad";
when "01" & x"5c4" => data <= x"da";
when "01" & x"5c5" => data <= x"10";
when "01" & x"5c6" => data <= x"95";
when "01" & x"5c7" => data <= x"00";
when "01" & x"5c8" => data <= x"ad";
when "01" & x"5c9" => data <= x"db";
when "01" & x"5ca" => data <= x"10";
when "01" & x"5cb" => data <= x"95";
when "01" & x"5cc" => data <= x"01";
when "01" & x"5cd" => data <= x"a9";
when "01" & x"5ce" => data <= x"00";
when "01" & x"5cf" => data <= x"60";
when "01" & x"5d0" => data <= x"c9";
when "01" & x"5d1" => data <= x"09";
when "01" & x"5d2" => data <= x"b0";
when "01" & x"5d3" => data <= x"fb";
when "01" & x"5d4" => data <= x"20";
when "01" & x"5d5" => data <= x"e1";
when "01" & x"5d6" => data <= x"83";
when "01" & x"5d7" => data <= x"8e";
when "01" & x"5d8" => data <= x"7d";
when "01" & x"5d9" => data <= x"10";
when "01" & x"5da" => data <= x"8c";
when "01" & x"5db" => data <= x"7e";
when "01" & x"5dc" => data <= x"10";
when "01" & x"5dd" => data <= x"a8";
when "01" & x"5de" => data <= x"ba";
when "01" & x"5df" => data <= x"a9";
when "01" & x"5e0" => data <= x"00";
when "01" & x"5e1" => data <= x"4c";
when "01" & x"5e2" => data <= x"d8";
when "01" & x"5e3" => data <= x"a0";
when "01" & x"5e4" => data <= x"b9";
when "01" & x"5e5" => data <= x"ab";
when "01" & x"5e6" => data <= x"99";
when "01" & x"5e7" => data <= x"8d";
when "01" & x"5e8" => data <= x"d8";
when "01" & x"5e9" => data <= x"10";
when "01" & x"5ea" => data <= x"b9";
when "01" & x"5eb" => data <= x"b4";
when "01" & x"5ec" => data <= x"99";
when "01" & x"5ed" => data <= x"8d";
when "01" & x"5ee" => data <= x"d9";
when "01" & x"5ef" => data <= x"10";
when "01" & x"5f0" => data <= x"b9";
when "01" & x"5f1" => data <= x"bd";
when "01" & x"5f2" => data <= x"99";
when "01" & x"5f3" => data <= x"4a";
when "01" & x"5f4" => data <= x"08";
when "01" & x"5f5" => data <= x"4a";
when "01" & x"5f6" => data <= x"08";
when "01" & x"5f7" => data <= x"8d";
when "01" & x"5f8" => data <= x"7f";
when "01" & x"5f9" => data <= x"10";
when "01" & x"5fa" => data <= x"20";
when "01" & x"5fb" => data <= x"56";
when "01" & x"5fc" => data <= x"97";
when "01" & x"5fd" => data <= x"a0";
when "01" & x"5fe" => data <= x"0c";
when "01" & x"5ff" => data <= x"b1";
when "01" & x"600" => data <= x"b4";
when "01" & x"601" => data <= x"99";
when "01" & x"602" => data <= x"60";
when "01" & x"603" => data <= x"10";
when "01" & x"604" => data <= x"88";
when "01" & x"605" => data <= x"10";
when "01" & x"606" => data <= x"f8";
when "01" & x"607" => data <= x"ad";
when "01" & x"608" => data <= x"63";
when "01" & x"609" => data <= x"10";
when "01" & x"60a" => data <= x"2d";
when "01" & x"60b" => data <= x"64";
when "01" & x"60c" => data <= x"10";
when "01" & x"60d" => data <= x"0d";
when "01" & x"60e" => data <= x"d7";
when "01" & x"60f" => data <= x"10";
when "01" & x"610" => data <= x"18";
when "01" & x"611" => data <= x"69";
when "01" & x"612" => data <= x"01";
when "01" & x"613" => data <= x"4c";
when "01" & x"614" => data <= x"eb";
when "01" & x"615" => data <= x"a0";
when "01" & x"616" => data <= x"ea";
when "01" & x"617" => data <= x"8d";
when "01" & x"618" => data <= x"81";
when "01" & x"619" => data <= x"10";
when "01" & x"61a" => data <= x"ad";
when "01" & x"61b" => data <= x"7f";
when "01" & x"61c" => data <= x"10";
when "01" & x"61d" => data <= x"b0";
when "01" & x"61e" => data <= x"07";
when "01" & x"61f" => data <= x"a2";
when "01" & x"620" => data <= x"61";
when "01" & x"621" => data <= x"a0";
when "01" & x"622" => data <= x"10";
when "01" & x"623" => data <= x"20";
when "01" & x"624" => data <= x"06";
when "01" & x"625" => data <= x"04";
when "01" & x"626" => data <= x"28";
when "01" & x"627" => data <= x"b0";
when "01" & x"628" => data <= x"04";
when "01" & x"629" => data <= x"28";
when "01" & x"62a" => data <= x"6c";
when "01" & x"62b" => data <= x"d8";
when "01" & x"62c" => data <= x"10";
when "01" & x"62d" => data <= x"a2";
when "01" & x"62e" => data <= x"03";
when "01" & x"62f" => data <= x"bd";
when "01" & x"630" => data <= x"69";
when "01" & x"631" => data <= x"10";
when "01" & x"632" => data <= x"95";
when "01" & x"633" => data <= x"b6";
when "01" & x"634" => data <= x"ca";
when "01" & x"635" => data <= x"10";
when "01" & x"636" => data <= x"f8";
when "01" & x"637" => data <= x"a2";
when "01" & x"638" => data <= x"b6";
when "01" & x"639" => data <= x"ac";
when "01" & x"63a" => data <= x"60";
when "01" & x"63b" => data <= x"10";
when "01" & x"63c" => data <= x"a9";
when "01" & x"63d" => data <= x"00";
when "01" & x"63e" => data <= x"28";
when "01" & x"63f" => data <= x"b0";
when "01" & x"640" => data <= x"03";
when "01" & x"641" => data <= x"20";
when "01" & x"642" => data <= x"a7";
when "01" & x"643" => data <= x"92";
when "01" & x"644" => data <= x"20";
when "01" & x"645" => data <= x"2e";
when "01" & x"646" => data <= x"90";
when "01" & x"647" => data <= x"a2";
when "01" & x"648" => data <= x"03";
when "01" & x"649" => data <= x"b5";
when "01" & x"64a" => data <= x"b6";
when "01" & x"64b" => data <= x"9d";
when "01" & x"64c" => data <= x"69";
when "01" & x"64d" => data <= x"10";
when "01" & x"64e" => data <= x"ca";
when "01" & x"64f" => data <= x"10";
when "01" & x"650" => data <= x"f8";
when "01" & x"651" => data <= x"20";
when "01" & x"652" => data <= x"48";
when "01" & x"653" => data <= x"97";
when "01" & x"654" => data <= x"30";
when "01" & x"655" => data <= x"0d";
when "01" & x"656" => data <= x"ac";
when "01" & x"657" => data <= x"60";
when "01" & x"658" => data <= x"10";
when "01" & x"659" => data <= x"20";
when "01" & x"65a" => data <= x"2a";
when "01" & x"65b" => data <= x"96";
when "01" & x"65c" => data <= x"b0";
when "01" & x"65d" => data <= x"0d";
when "01" & x"65e" => data <= x"a2";
when "01" & x"65f" => data <= x"09";
when "01" & x"660" => data <= x"20";
when "01" & x"661" => data <= x"3c";
when "01" & x"662" => data <= x"97";
when "01" & x"663" => data <= x"a2";
when "01" & x"664" => data <= x"05";
when "01" & x"665" => data <= x"20";
when "01" & x"666" => data <= x"3c";
when "01" & x"667" => data <= x"97";
when "01" & x"668" => data <= x"d0";
when "01" & x"669" => data <= x"ec";
when "01" & x"66a" => data <= x"18";
when "01" & x"66b" => data <= x"08";
when "01" & x"66c" => data <= x"20";
when "01" & x"66d" => data <= x"48";
when "01" & x"66e" => data <= x"97";
when "01" & x"66f" => data <= x"a2";
when "01" & x"670" => data <= x"05";
when "01" & x"671" => data <= x"20";
when "01" & x"672" => data <= x"3c";
when "01" & x"673" => data <= x"97";
when "01" & x"674" => data <= x"a0";
when "01" & x"675" => data <= x"0c";
when "01" & x"676" => data <= x"20";
when "01" & x"677" => data <= x"56";
when "01" & x"678" => data <= x"97";
when "01" & x"679" => data <= x"b9";
when "01" & x"67a" => data <= x"60";
when "01" & x"67b" => data <= x"10";
when "01" & x"67c" => data <= x"91";
when "01" & x"67d" => data <= x"b4";
when "01" & x"67e" => data <= x"88";
when "01" & x"67f" => data <= x"10";
when "01" & x"680" => data <= x"f8";
when "01" & x"681" => data <= x"28";
when "01" & x"682" => data <= x"60";
when "01" & x"683" => data <= x"20";
when "01" & x"684" => data <= x"4d";
when "01" & x"685" => data <= x"83";
when "01" & x"686" => data <= x"20";
when "01" & x"687" => data <= x"41";
when "01" & x"688" => data <= x"af";
when "01" & x"689" => data <= x"a9";
when "01" & x"68a" => data <= x"95";
when "01" & x"68b" => data <= x"8d";
when "01" & x"68c" => data <= x"d8";
when "01" & x"68d" => data <= x"10";
when "01" & x"68e" => data <= x"a9";
when "01" & x"68f" => data <= x"96";
when "01" & x"690" => data <= x"8d";
when "01" & x"691" => data <= x"d9";
when "01" & x"692" => data <= x"10";
when "01" & x"693" => data <= x"d0";
when "01" & x"694" => data <= x"bc";
when "01" & x"695" => data <= x"ac";
when "01" & x"696" => data <= x"69";
when "01" & x"697" => data <= x"10";
when "01" & x"698" => data <= x"cc";
when "01" & x"699" => data <= x"05";
when "01" & x"69a" => data <= x"0f";
when "01" & x"69b" => data <= x"b0";
when "01" & x"69c" => data <= x"28";
when "01" & x"69d" => data <= x"b9";
when "01" & x"69e" => data <= x"0f";
when "01" & x"69f" => data <= x"0e";
when "01" & x"6a0" => data <= x"20";
when "01" & x"6a1" => data <= x"ee";
when "01" & x"6a2" => data <= x"82";
when "01" & x"6a3" => data <= x"45";
when "01" & x"6a4" => data <= x"ce";
when "01" & x"6a5" => data <= x"b0";
when "01" & x"6a6" => data <= x"02";
when "01" & x"6a7" => data <= x"29";
when "01" & x"6a8" => data <= x"df";
when "01" & x"6a9" => data <= x"29";
when "01" & x"6aa" => data <= x"7f";
when "01" & x"6ab" => data <= x"f0";
when "01" & x"6ac" => data <= x"05";
when "01" & x"6ad" => data <= x"20";
when "01" & x"6ae" => data <= x"10";
when "01" & x"6af" => data <= x"82";
when "01" & x"6b0" => data <= x"d0";
when "01" & x"6b1" => data <= x"e6";
when "01" & x"6b2" => data <= x"a9";
when "01" & x"6b3" => data <= x"07";
when "01" & x"6b4" => data <= x"20";
when "01" & x"6b5" => data <= x"6a";
when "01" & x"6b6" => data <= x"97";
when "01" & x"6b7" => data <= x"85";
when "01" & x"6b8" => data <= x"b0";
when "01" & x"6b9" => data <= x"b9";
when "01" & x"6ba" => data <= x"08";
when "01" & x"6bb" => data <= x"0e";
when "01" & x"6bc" => data <= x"20";
when "01" & x"6bd" => data <= x"6a";
when "01" & x"6be" => data <= x"97";
when "01" & x"6bf" => data <= x"c8";
when "01" & x"6c0" => data <= x"c6";
when "01" & x"6c1" => data <= x"b0";
when "01" & x"6c2" => data <= x"d0";
when "01" & x"6c3" => data <= x"f5";
when "01" & x"6c4" => data <= x"18";
when "01" & x"6c5" => data <= x"8c";
when "01" & x"6c6" => data <= x"69";
when "01" & x"6c7" => data <= x"10";
when "01" & x"6c8" => data <= x"ad";
when "01" & x"6c9" => data <= x"04";
when "01" & x"6ca" => data <= x"0f";
when "01" & x"6cb" => data <= x"8d";
when "01" & x"6cc" => data <= x"60";
when "01" & x"6cd" => data <= x"10";
when "01" & x"6ce" => data <= x"60";
when "01" & x"6cf" => data <= x"20";
when "01" & x"6d0" => data <= x"4d";
when "01" & x"6d1" => data <= x"83";
when "01" & x"6d2" => data <= x"20";
when "01" & x"6d3" => data <= x"41";
when "01" & x"6d4" => data <= x"af";
when "01" & x"6d5" => data <= x"a9";
when "01" & x"6d6" => data <= x"0c";
when "01" & x"6d7" => data <= x"20";
when "01" & x"6d8" => data <= x"6a";
when "01" & x"6d9" => data <= x"97";
when "01" & x"6da" => data <= x"a0";
when "01" & x"6db" => data <= x"00";
when "01" & x"6dc" => data <= x"b9";
when "01" & x"6dd" => data <= x"00";
when "01" & x"6de" => data <= x"0e";
when "01" & x"6df" => data <= x"20";
when "01" & x"6e0" => data <= x"6a";
when "01" & x"6e1" => data <= x"97";
when "01" & x"6e2" => data <= x"c8";
when "01" & x"6e3" => data <= x"c0";
when "01" & x"6e4" => data <= x"08";
when "01" & x"6e5" => data <= x"d0";
when "01" & x"6e6" => data <= x"f5";
when "01" & x"6e7" => data <= x"b9";
when "01" & x"6e8" => data <= x"f8";
when "01" & x"6e9" => data <= x"0e";
when "01" & x"6ea" => data <= x"20";
when "01" & x"6eb" => data <= x"6a";
when "01" & x"6ec" => data <= x"97";
when "01" & x"6ed" => data <= x"c8";
when "01" & x"6ee" => data <= x"c0";
when "01" & x"6ef" => data <= x"0c";
when "01" & x"6f0" => data <= x"d0";
when "01" & x"6f1" => data <= x"f5";
when "01" & x"6f2" => data <= x"ad";
when "01" & x"6f3" => data <= x"06";
when "01" & x"6f4" => data <= x"0f";
when "01" & x"6f5" => data <= x"20";
when "01" & x"6f6" => data <= x"05";
when "01" & x"6f7" => data <= x"82";
when "01" & x"6f8" => data <= x"20";
when "01" & x"6f9" => data <= x"6a";
when "01" & x"6fa" => data <= x"97";
when "01" & x"6fb" => data <= x"a5";
when "01" & x"6fc" => data <= x"cf";
when "01" & x"6fd" => data <= x"4c";
when "01" & x"6fe" => data <= x"6a";
when "01" & x"6ff" => data <= x"97";
when "01" & x"700" => data <= x"20";
when "01" & x"701" => data <= x"61";
when "01" & x"702" => data <= x"97";
when "01" & x"703" => data <= x"ad";
when "01" & x"704" => data <= x"cb";
when "01" & x"705" => data <= x"10";
when "01" & x"706" => data <= x"09";
when "01" & x"707" => data <= x"30";
when "01" & x"708" => data <= x"20";
when "01" & x"709" => data <= x"6a";
when "01" & x"70a" => data <= x"97";
when "01" & x"70b" => data <= x"20";
when "01" & x"70c" => data <= x"61";
when "01" & x"70d" => data <= x"97";
when "01" & x"70e" => data <= x"ad";
when "01" & x"70f" => data <= x"ca";
when "01" & x"710" => data <= x"10";
when "01" & x"711" => data <= x"4c";
when "01" & x"712" => data <= x"6a";
when "01" & x"713" => data <= x"97";
when "01" & x"714" => data <= x"20";
when "01" & x"715" => data <= x"61";
when "01" & x"716" => data <= x"97";
when "01" & x"717" => data <= x"ad";
when "01" & x"718" => data <= x"cd";
when "01" & x"719" => data <= x"10";
when "01" & x"71a" => data <= x"09";
when "01" & x"71b" => data <= x"30";
when "01" & x"71c" => data <= x"20";
when "01" & x"71d" => data <= x"6a";
when "01" & x"71e" => data <= x"97";
when "01" & x"71f" => data <= x"20";
when "01" & x"720" => data <= x"61";
when "01" & x"721" => data <= x"97";
when "01" & x"722" => data <= x"ad";
when "01" & x"723" => data <= x"cc";
when "01" & x"724" => data <= x"10";
when "01" & x"725" => data <= x"4c";
when "01" & x"726" => data <= x"6a";
when "01" & x"727" => data <= x"97";
when "01" & x"728" => data <= x"48";
when "01" & x"729" => data <= x"ad";
when "01" & x"72a" => data <= x"61";
when "01" & x"72b" => data <= x"10";
when "01" & x"72c" => data <= x"85";
when "01" & x"72d" => data <= x"b8";
when "01" & x"72e" => data <= x"ad";
when "01" & x"72f" => data <= x"62";
when "01" & x"730" => data <= x"10";
when "01" & x"731" => data <= x"85";
when "01" & x"732" => data <= x"b9";
when "01" & x"733" => data <= x"a2";
when "01" & x"734" => data <= x"00";
when "01" & x"735" => data <= x"68";
when "01" & x"736" => data <= x"60";
when "01" & x"737" => data <= x"20";
when "01" & x"738" => data <= x"e1";
when "01" & x"739" => data <= x"83";
when "01" & x"73a" => data <= x"a2";
when "01" & x"73b" => data <= x"01";
when "01" & x"73c" => data <= x"a0";
when "01" & x"73d" => data <= x"04";
when "01" & x"73e" => data <= x"fe";
when "01" & x"73f" => data <= x"60";
when "01" & x"740" => data <= x"10";
when "01" & x"741" => data <= x"d0";
when "01" & x"742" => data <= x"04";
when "01" & x"743" => data <= x"e8";
when "01" & x"744" => data <= x"88";
when "01" & x"745" => data <= x"d0";
when "01" & x"746" => data <= x"f7";
when "01" & x"747" => data <= x"60";
when "01" & x"748" => data <= x"a2";
when "01" & x"749" => data <= x"03";
when "01" & x"74a" => data <= x"a9";
when "01" & x"74b" => data <= x"ff";
when "01" & x"74c" => data <= x"5d";
when "01" & x"74d" => data <= x"65";
when "01" & x"74e" => data <= x"10";
when "01" & x"74f" => data <= x"9d";
when "01" & x"750" => data <= x"65";
when "01" & x"751" => data <= x"10";
when "01" & x"752" => data <= x"ca";
when "01" & x"753" => data <= x"10";
when "01" & x"754" => data <= x"f5";
when "01" & x"755" => data <= x"60";
when "01" & x"756" => data <= x"ad";
when "01" & x"757" => data <= x"7d";
when "01" & x"758" => data <= x"10";
when "01" & x"759" => data <= x"85";
when "01" & x"75a" => data <= x"b4";
when "01" & x"75b" => data <= x"ad";
when "01" & x"75c" => data <= x"7e";
when "01" & x"75d" => data <= x"10";
when "01" & x"75e" => data <= x"85";
when "01" & x"75f" => data <= x"b5";
when "01" & x"760" => data <= x"60";
when "01" & x"761" => data <= x"a9";
when "01" & x"762" => data <= x"01";
when "01" & x"763" => data <= x"d0";
when "01" & x"764" => data <= x"05";
when "01" & x"765" => data <= x"20";
when "01" & x"766" => data <= x"c1";
when "01" & x"767" => data <= x"90";
when "01" & x"768" => data <= x"b0";
when "01" & x"769" => data <= x"f6";
when "01" & x"76a" => data <= x"2c";
when "01" & x"76b" => data <= x"81";
when "01" & x"76c" => data <= x"10";
when "01" & x"76d" => data <= x"10";
when "01" & x"76e" => data <= x"06";
when "01" & x"76f" => data <= x"8d";
when "01" & x"770" => data <= x"e5";
when "01" & x"771" => data <= x"fe";
when "01" & x"772" => data <= x"4c";
when "01" & x"773" => data <= x"37";
when "01" & x"774" => data <= x"97";
when "01" & x"775" => data <= x"20";
when "01" & x"776" => data <= x"28";
when "01" & x"777" => data <= x"97";
when "01" & x"778" => data <= x"81";
when "01" & x"779" => data <= x"b8";
when "01" & x"77a" => data <= x"4c";
when "01" & x"77b" => data <= x"37";
when "01" & x"77c" => data <= x"97";
when "01" & x"77d" => data <= x"20";
when "01" & x"77e" => data <= x"85";
when "01" & x"77f" => data <= x"97";
when "01" & x"780" => data <= x"20";
when "01" & x"781" => data <= x"aa";
when "01" & x"782" => data <= x"91";
when "01" & x"783" => data <= x"18";
when "01" & x"784" => data <= x"60";
when "01" & x"785" => data <= x"2c";
when "01" & x"786" => data <= x"81";
when "01" & x"787" => data <= x"10";
when "01" & x"788" => data <= x"10";
when "01" & x"789" => data <= x"06";
when "01" & x"78a" => data <= x"ad";
when "01" & x"78b" => data <= x"e5";
when "01" & x"78c" => data <= x"fe";
when "01" & x"78d" => data <= x"4c";
when "01" & x"78e" => data <= x"37";
when "01" & x"78f" => data <= x"97";
when "01" & x"790" => data <= x"20";
when "01" & x"791" => data <= x"28";
when "01" & x"792" => data <= x"97";
when "01" & x"793" => data <= x"a1";
when "01" & x"794" => data <= x"b8";
when "01" & x"795" => data <= x"4c";
when "01" & x"796" => data <= x"37";
when "01" & x"797" => data <= x"97";
when "01" & x"798" => data <= x"2c";
when "01" & x"799" => data <= x"c8";
when "01" & x"79a" => data <= x"10";
when "01" & x"79b" => data <= x"30";
when "01" & x"79c" => data <= x"03";
when "01" & x"79d" => data <= x"ce";
when "01" & x"79e" => data <= x"c8";
when "01" & x"79f" => data <= x"10";
when "01" & x"7a0" => data <= x"60";
when "01" & x"7a1" => data <= x"20";
when "01" & x"7a2" => data <= x"5a";
when "01" & x"7a3" => data <= x"98";
when "01" & x"7a4" => data <= x"20";
when "01" & x"7a5" => data <= x"7e";
when "01" & x"7a6" => data <= x"83";
when "01" & x"7a7" => data <= x"a9";
when "01" & x"7a8" => data <= x"01";
when "01" & x"7a9" => data <= x"60";
when "01" & x"7aa" => data <= x"20";
when "01" & x"7ab" => data <= x"37";
when "01" & x"7ac" => data <= x"98";
when "01" & x"7ad" => data <= x"20";
when "01" & x"7ae" => data <= x"7e";
when "01" & x"7af" => data <= x"83";
when "01" & x"7b0" => data <= x"20";
when "01" & x"7b1" => data <= x"d1";
when "01" & x"7b2" => data <= x"82";
when "01" & x"7b3" => data <= x"90";
when "01" & x"7b4" => data <= x"24";
when "01" & x"7b5" => data <= x"20";
when "01" & x"7b6" => data <= x"37";
when "01" & x"7b7" => data <= x"98";
when "01" & x"7b8" => data <= x"20";
when "01" & x"7b9" => data <= x"df";
when "01" & x"7ba" => data <= x"97";
when "01" & x"7bb" => data <= x"20";
when "01" & x"7bc" => data <= x"fb";
when "01" & x"7bd" => data <= x"97";
when "01" & x"7be" => data <= x"50";
when "01" & x"7bf" => data <= x"16";
when "01" & x"7c0" => data <= x"20";
when "01" & x"7c1" => data <= x"37";
when "01" & x"7c2" => data <= x"98";
when "01" & x"7c3" => data <= x"20";
when "01" & x"7c4" => data <= x"df";
when "01" & x"7c5" => data <= x"97";
when "01" & x"7c6" => data <= x"50";
when "01" & x"7c7" => data <= x"11";
when "01" & x"7c8" => data <= x"20";
when "01" & x"7c9" => data <= x"37";
when "01" & x"7ca" => data <= x"98";
when "01" & x"7cb" => data <= x"20";
when "01" & x"7cc" => data <= x"fb";
when "01" & x"7cd" => data <= x"97";
when "01" & x"7ce" => data <= x"50";
when "01" & x"7cf" => data <= x"09";
when "01" & x"7d0" => data <= x"20";
when "01" & x"7d1" => data <= x"5a";
when "01" & x"7d2" => data <= x"98";
when "01" & x"7d3" => data <= x"20";
when "01" & x"7d4" => data <= x"4f";
when "01" & x"7d5" => data <= x"98";
when "01" & x"7d6" => data <= x"20";
when "01" & x"7d7" => data <= x"1e";
when "01" & x"7d8" => data <= x"98";
when "01" & x"7d9" => data <= x"20";
when "01" & x"7da" => data <= x"c3";
when "01" & x"7db" => data <= x"88";
when "01" & x"7dc" => data <= x"a9";
when "01" & x"7dd" => data <= x"01";
when "01" & x"7de" => data <= x"60";
when "01" & x"7df" => data <= x"20";
when "01" & x"7e0" => data <= x"e1";
when "01" & x"7e1" => data <= x"83";
when "01" & x"7e2" => data <= x"a0";
when "01" & x"7e3" => data <= x"02";
when "01" & x"7e4" => data <= x"b1";
when "01" & x"7e5" => data <= x"b0";
when "01" & x"7e6" => data <= x"9d";
when "01" & x"7e7" => data <= x"08";
when "01" & x"7e8" => data <= x"0f";
when "01" & x"7e9" => data <= x"c8";
when "01" & x"7ea" => data <= x"b1";
when "01" & x"7eb" => data <= x"b0";
when "01" & x"7ec" => data <= x"9d";
when "01" & x"7ed" => data <= x"09";
when "01" & x"7ee" => data <= x"0f";
when "01" & x"7ef" => data <= x"c8";
when "01" & x"7f0" => data <= x"b1";
when "01" & x"7f1" => data <= x"b0";
when "01" & x"7f2" => data <= x"0a";
when "01" & x"7f3" => data <= x"0a";
when "01" & x"7f4" => data <= x"5d";
when "01" & x"7f5" => data <= x"0e";
when "01" & x"7f6" => data <= x"0f";
when "01" & x"7f7" => data <= x"29";
when "01" & x"7f8" => data <= x"0c";
when "01" & x"7f9" => data <= x"10";
when "01" & x"7fa" => data <= x"1b";
when "01" & x"7fb" => data <= x"20";
when "01" & x"7fc" => data <= x"e1";
when "01" & x"7fd" => data <= x"83";
when "01" & x"7fe" => data <= x"a0";
when "01" & x"7ff" => data <= x"06";
when "01" & x"800" => data <= x"b1";
when "01" & x"801" => data <= x"b0";
when "01" & x"802" => data <= x"9d";
when "01" & x"803" => data <= x"0a";
when "01" & x"804" => data <= x"0f";
when "01" & x"805" => data <= x"c8";
when "01" & x"806" => data <= x"b1";
when "01" & x"807" => data <= x"b0";
when "01" & x"808" => data <= x"9d";
when "01" & x"809" => data <= x"0b";
when "01" & x"80a" => data <= x"0f";
when "01" & x"80b" => data <= x"c8";
when "01" & x"80c" => data <= x"b1";
when "01" & x"80d" => data <= x"b0";
when "01" & x"80e" => data <= x"6a";
when "01" & x"80f" => data <= x"6a";
when "01" & x"810" => data <= x"6a";
when "01" & x"811" => data <= x"5d";
when "01" & x"812" => data <= x"0e";
when "01" & x"813" => data <= x"0f";
when "01" & x"814" => data <= x"29";
when "01" & x"815" => data <= x"c0";
when "01" & x"816" => data <= x"5d";
when "01" & x"817" => data <= x"0e";
when "01" & x"818" => data <= x"0f";
when "01" & x"819" => data <= x"9d";
when "01" & x"81a" => data <= x"0e";
when "01" & x"81b" => data <= x"0f";
when "01" & x"81c" => data <= x"b8";
when "01" & x"81d" => data <= x"60";
when "01" & x"81e" => data <= x"20";
when "01" & x"81f" => data <= x"e1";
when "01" & x"820" => data <= x"83";
when "01" & x"821" => data <= x"a0";
when "01" & x"822" => data <= x"0e";
when "01" & x"823" => data <= x"b1";
when "01" & x"824" => data <= x"b0";
when "01" & x"825" => data <= x"29";
when "01" & x"826" => data <= x"0a";
when "01" & x"827" => data <= x"f0";
when "01" & x"828" => data <= x"02";
when "01" & x"829" => data <= x"a9";
when "01" & x"82a" => data <= x"80";
when "01" & x"82b" => data <= x"5d";
when "01" & x"82c" => data <= x"0f";
when "01" & x"82d" => data <= x"0e";
when "01" & x"82e" => data <= x"29";
when "01" & x"82f" => data <= x"80";
when "01" & x"830" => data <= x"5d";
when "01" & x"831" => data <= x"0f";
when "01" & x"832" => data <= x"0e";
when "01" & x"833" => data <= x"9d";
when "01" & x"834" => data <= x"0f";
when "01" & x"835" => data <= x"0e";
when "01" & x"836" => data <= x"60";
when "01" & x"837" => data <= x"20";
when "01" & x"838" => data <= x"64";
when "01" & x"839" => data <= x"98";
when "01" & x"83a" => data <= x"90";
when "01" & x"83b" => data <= x"23";
when "01" & x"83c" => data <= x"b9";
when "01" & x"83d" => data <= x"0f";
when "01" & x"83e" => data <= x"0e";
when "01" & x"83f" => data <= x"10";
when "01" & x"840" => data <= x"22";
when "01" & x"841" => data <= x"20";
when "01" & x"842" => data <= x"2b";
when "01" & x"843" => data <= x"80";
when "01" & x"844" => data <= x"c3";
when "01" & x"845" => data <= x"6c";
when "01" & x"846" => data <= x"6f";
when "01" & x"847" => data <= x"63";
when "01" & x"848" => data <= x"6b";
when "01" & x"849" => data <= x"65";
when "01" & x"84a" => data <= x"64";
when "01" & x"84b" => data <= x"00";
when "01" & x"84c" => data <= x"20";
when "01" & x"84d" => data <= x"3c";
when "01" & x"84e" => data <= x"98";
when "01" & x"84f" => data <= x"20";
when "01" & x"850" => data <= x"e1";
when "01" & x"851" => data <= x"83";
when "01" & x"852" => data <= x"20";
when "01" & x"853" => data <= x"9e";
when "01" & x"854" => data <= x"8f";
when "01" & x"855" => data <= x"90";
when "01" & x"856" => data <= x"21";
when "01" & x"857" => data <= x"4c";
when "01" & x"858" => data <= x"02";
when "01" & x"859" => data <= x"8f";
when "01" & x"85a" => data <= x"20";
when "01" & x"85b" => data <= x"64";
when "01" & x"85c" => data <= x"98";
when "01" & x"85d" => data <= x"b0";
when "01" & x"85e" => data <= x"19";
when "01" & x"85f" => data <= x"68";
when "01" & x"860" => data <= x"68";
when "01" & x"861" => data <= x"a9";
when "01" & x"862" => data <= x"00";
when "01" & x"863" => data <= x"60";
when "01" & x"864" => data <= x"20";
when "01" & x"865" => data <= x"06";
when "01" & x"866" => data <= x"81";
when "01" & x"867" => data <= x"20";
when "01" & x"868" => data <= x"96";
when "01" & x"869" => data <= x"82";
when "01" & x"86a" => data <= x"90";
when "01" & x"86b" => data <= x"0c";
when "01" & x"86c" => data <= x"98";
when "01" & x"86d" => data <= x"aa";
when "01" & x"86e" => data <= x"ad";
when "01" & x"86f" => data <= x"dc";
when "01" & x"870" => data <= x"10";
when "01" & x"871" => data <= x"85";
when "01" & x"872" => data <= x"b0";
when "01" & x"873" => data <= x"ad";
when "01" & x"874" => data <= x"dd";
when "01" & x"875" => data <= x"10";
when "01" & x"876" => data <= x"85";
when "01" & x"877" => data <= x"b1";
when "01" & x"878" => data <= x"60";
when "01" & x"879" => data <= x"a9";
when "01" & x"87a" => data <= x"83";
when "01" & x"87b" => data <= x"20";
when "01" & x"87c" => data <= x"f4";
when "01" & x"87d" => data <= x"ff";
when "01" & x"87e" => data <= x"8c";
when "01" & x"87f" => data <= x"d0";
when "01" & x"880" => data <= x"10";
when "01" & x"881" => data <= x"a9";
when "01" & x"882" => data <= x"84";
when "01" & x"883" => data <= x"20";
when "01" & x"884" => data <= x"f4";
when "01" & x"885" => data <= x"ff";
when "01" & x"886" => data <= x"98";
when "01" & x"887" => data <= x"38";
when "01" & x"888" => data <= x"ed";
when "01" & x"889" => data <= x"d0";
when "01" & x"88a" => data <= x"10";
when "01" & x"88b" => data <= x"8d";
when "01" & x"88c" => data <= x"d1";
when "01" & x"88d" => data <= x"10";
when "01" & x"88e" => data <= x"60";
when "01" & x"88f" => data <= x"a2";
when "01" & x"890" => data <= x"0a";
when "01" & x"891" => data <= x"20";
when "01" & x"892" => data <= x"2c";
when "01" & x"893" => data <= x"99";
when "01" & x"894" => data <= x"20";
when "01" & x"895" => data <= x"9e";
when "01" & x"896" => data <= x"98";
when "01" & x"897" => data <= x"a0";
when "01" & x"898" => data <= x"d5";
when "01" & x"899" => data <= x"a9";
when "01" & x"89a" => data <= x"ff";
when "01" & x"89b" => data <= x"91";
when "01" & x"89c" => data <= x"b0";
when "01" & x"89d" => data <= x"60";
when "01" & x"89e" => data <= x"48";
when "01" & x"89f" => data <= x"a6";
when "01" & x"8a0" => data <= x"f4";
when "01" & x"8a1" => data <= x"a9";
when "01" & x"8a2" => data <= x"00";
when "01" & x"8a3" => data <= x"85";
when "01" & x"8a4" => data <= x"b0";
when "01" & x"8a5" => data <= x"bd";
when "01" & x"8a6" => data <= x"f0";
when "01" & x"8a7" => data <= x"0d";
when "01" & x"8a8" => data <= x"85";
when "01" & x"8a9" => data <= x"b1";
when "01" & x"8aa" => data <= x"68";
when "01" & x"8ab" => data <= x"60";
when "01" & x"8ac" => data <= x"00";
when "01" & x"8ad" => data <= x"00";
when "01" & x"8ae" => data <= x"00";
when "01" & x"8af" => data <= x"00";
when "01" & x"8b0" => data <= x"00";
when "01" & x"8b1" => data <= x"00";
when "01" & x"8b2" => data <= x"00";
when "01" & x"8b3" => data <= x"00";
when "01" & x"8b4" => data <= x"00";
when "01" & x"8b5" => data <= x"00";
when "01" & x"8b6" => data <= x"00";
when "01" & x"8b7" => data <= x"00";
when "01" & x"8b8" => data <= x"00";
when "01" & x"8b9" => data <= x"00";
when "01" & x"8ba" => data <= x"00";
when "01" & x"8bb" => data <= x"00";
when "01" & x"8bc" => data <= x"00";
when "01" & x"8bd" => data <= x"00";
when "01" & x"8be" => data <= x"00";
when "01" & x"8bf" => data <= x"00";
when "01" & x"8c0" => data <= x"00";
when "01" & x"8c1" => data <= x"00";
when "01" & x"8c2" => data <= x"00";
when "01" & x"8c3" => data <= x"00";
when "01" & x"8c4" => data <= x"00";
when "01" & x"8c5" => data <= x"00";
when "01" & x"8c6" => data <= x"00";
when "01" & x"8c7" => data <= x"00";
when "01" & x"8c8" => data <= x"00";
when "01" & x"8c9" => data <= x"00";
when "01" & x"8ca" => data <= x"00";
when "01" & x"8cb" => data <= x"00";
when "01" & x"8cc" => data <= x"00";
when "01" & x"8cd" => data <= x"00";
when "01" & x"8ce" => data <= x"00";
when "01" & x"8cf" => data <= x"00";
when "01" & x"8d0" => data <= x"00";
when "01" & x"8d1" => data <= x"00";
when "01" & x"8d2" => data <= x"00";
when "01" & x"8d3" => data <= x"00";
when "01" & x"8d4" => data <= x"00";
when "01" & x"8d5" => data <= x"00";
when "01" & x"8d6" => data <= x"00";
when "01" & x"8d7" => data <= x"00";
when "01" & x"8d8" => data <= x"00";
when "01" & x"8d9" => data <= x"00";
when "01" & x"8da" => data <= x"00";
when "01" & x"8db" => data <= x"00";
when "01" & x"8dc" => data <= x"00";
when "01" & x"8dd" => data <= x"00";
when "01" & x"8de" => data <= x"00";
when "01" & x"8df" => data <= x"00";
when "01" & x"8e0" => data <= x"00";
when "01" & x"8e1" => data <= x"00";
when "01" & x"8e2" => data <= x"00";
when "01" & x"8e3" => data <= x"00";
when "01" & x"8e4" => data <= x"00";
when "01" & x"8e5" => data <= x"00";
when "01" & x"8e6" => data <= x"00";
when "01" & x"8e7" => data <= x"00";
when "01" & x"8e8" => data <= x"00";
when "01" & x"8e9" => data <= x"00";
when "01" & x"8ea" => data <= x"00";
when "01" & x"8eb" => data <= x"00";
when "01" & x"8ec" => data <= x"00";
when "01" & x"8ed" => data <= x"00";
when "01" & x"8ee" => data <= x"00";
when "01" & x"8ef" => data <= x"00";
when "01" & x"8f0" => data <= x"00";
when "01" & x"8f1" => data <= x"00";
when "01" & x"8f2" => data <= x"00";
when "01" & x"8f3" => data <= x"00";
when "01" & x"8f4" => data <= x"00";
when "01" & x"8f5" => data <= x"00";
when "01" & x"8f6" => data <= x"00";
when "01" & x"8f7" => data <= x"00";
when "01" & x"8f8" => data <= x"00";
when "01" & x"8f9" => data <= x"00";
when "01" & x"8fa" => data <= x"00";
when "01" & x"8fb" => data <= x"00";
when "01" & x"8fc" => data <= x"00";
when "01" & x"8fd" => data <= x"00";
when "01" & x"8fe" => data <= x"00";
when "01" & x"8ff" => data <= x"00";
when "01" & x"900" => data <= x"00";
when "01" & x"901" => data <= x"00";
when "01" & x"902" => data <= x"00";
when "01" & x"903" => data <= x"00";
when "01" & x"904" => data <= x"00";
when "01" & x"905" => data <= x"60";
when "01" & x"906" => data <= x"20";
when "01" & x"907" => data <= x"e1";
when "01" & x"908" => data <= x"83";
when "01" & x"909" => data <= x"a9";
when "01" & x"90a" => data <= x"0f";
when "01" & x"90b" => data <= x"a2";
when "01" & x"90c" => data <= x"01";
when "01" & x"90d" => data <= x"a0";
when "01" & x"90e" => data <= x"00";
when "01" & x"90f" => data <= x"f0";
when "01" & x"910" => data <= x"25";
when "01" & x"911" => data <= x"a9";
when "01" & x"912" => data <= x"c7";
when "01" & x"913" => data <= x"a2";
when "01" & x"914" => data <= x"00";
when "01" & x"915" => data <= x"f0";
when "01" & x"916" => data <= x"f6";
when "01" & x"917" => data <= x"aa";
when "01" & x"918" => data <= x"a9";
when "01" & x"919" => data <= x"03";
when "01" & x"91a" => data <= x"d0";
when "01" & x"91b" => data <= x"1a";
when "01" & x"91c" => data <= x"a9";
when "01" & x"91d" => data <= x"ec";
when "01" & x"91e" => data <= x"d0";
when "01" & x"91f" => data <= x"12";
when "01" & x"920" => data <= x"a9";
when "01" & x"921" => data <= x"c7";
when "01" & x"922" => data <= x"d0";
when "01" & x"923" => data <= x"0e";
when "01" & x"924" => data <= x"a9";
when "01" & x"925" => data <= x"ea";
when "01" & x"926" => data <= x"d0";
when "01" & x"927" => data <= x"0a";
when "01" & x"928" => data <= x"a9";
when "01" & x"929" => data <= x"a8";
when "01" & x"92a" => data <= x"d0";
when "01" & x"92b" => data <= x"06";
when "01" & x"92c" => data <= x"a9";
when "01" & x"92d" => data <= x"8f";
when "01" & x"92e" => data <= x"d0";
when "01" & x"92f" => data <= x"06";
when "01" & x"930" => data <= x"a9";
when "01" & x"931" => data <= x"ff";
when "01" & x"932" => data <= x"a2";
when "01" & x"933" => data <= x"00";
when "01" & x"934" => data <= x"a0";
when "01" & x"935" => data <= x"ff";
when "01" & x"936" => data <= x"4c";
when "01" & x"937" => data <= x"f4";
when "01" & x"938" => data <= x"ff";
when "01" & x"939" => data <= x"4c";
when "01" & x"93a" => data <= x"2e";
when "01" & x"93b" => data <= x"21";
when "01" & x"93c" => data <= x"42";
when "01" & x"93d" => data <= x"4f";
when "01" & x"93e" => data <= x"4f";
when "01" & x"93f" => data <= x"54";
when "01" & x"940" => data <= x"0d";
when "01" & x"941" => data <= x"45";
when "01" & x"942" => data <= x"2e";
when "01" & x"943" => data <= x"21";
when "01" & x"944" => data <= x"42";
when "01" & x"945" => data <= x"4f";
when "01" & x"946" => data <= x"4f";
when "01" & x"947" => data <= x"54";
when "01" & x"948" => data <= x"0d";
when "01" & x"949" => data <= x"1b";
when "01" & x"94a" => data <= x"ff";
when "01" & x"94b" => data <= x"1e";
when "01" & x"94c" => data <= x"ff";
when "01" & x"94d" => data <= x"21";
when "01" & x"94e" => data <= x"ff";
when "01" & x"94f" => data <= x"24";
when "01" & x"950" => data <= x"ff";
when "01" & x"951" => data <= x"27";
when "01" & x"952" => data <= x"ff";
when "01" & x"953" => data <= x"2a";
when "01" & x"954" => data <= x"ff";
when "01" & x"955" => data <= x"2d";
when "01" & x"956" => data <= x"ff";
when "01" & x"957" => data <= x"7b";
when "01" & x"958" => data <= x"95";
when "01" & x"959" => data <= x"00";
when "01" & x"95a" => data <= x"07";
when "01" & x"95b" => data <= x"90";
when "01" & x"95c" => data <= x"00";
when "01" & x"95d" => data <= x"c1";
when "01" & x"95e" => data <= x"90";
when "01" & x"95f" => data <= x"00";
when "01" & x"960" => data <= x"aa";
when "01" & x"961" => data <= x"91";
when "01" & x"962" => data <= x"00";
when "01" & x"963" => data <= x"d0";
when "01" & x"964" => data <= x"95";
when "01" & x"965" => data <= x"00";
when "01" & x"966" => data <= x"93";
when "01" & x"967" => data <= x"8e";
when "01" & x"968" => data <= x"00";
when "01" & x"969" => data <= x"aa";
when "01" & x"96a" => data <= x"95";
when "01" & x"96b" => data <= x"00";
when "01" & x"96c" => data <= x"1b";
when "01" & x"96d" => data <= x"8c";
when "01" & x"96e" => data <= x"d3";
when "01" & x"96f" => data <= x"6b";
when "01" & x"970" => data <= x"d3";
when "01" & x"971" => data <= x"1d";
when "01" & x"972" => data <= x"e1";
when "01" & x"973" => data <= x"dc";
when "01" & x"974" => data <= x"97";
when "01" & x"975" => data <= x"89";
when "01" & x"976" => data <= x"90";
when "01" & x"977" => data <= x"87";
when "01" & x"978" => data <= x"86";
when "01" & x"979" => data <= x"87";
when "01" & x"97a" => data <= x"84";
when "01" & x"97b" => data <= x"8d";
when "01" & x"97c" => data <= x"8d";
when "01" & x"97d" => data <= x"97";
when "01" & x"97e" => data <= x"f1";
when "01" & x"97f" => data <= x"3c";
when "01" & x"980" => data <= x"bc";
when "01" & x"981" => data <= x"8f";
when "01" & x"982" => data <= x"9b";
when "01" & x"983" => data <= x"95";
when "01" & x"984" => data <= x"93";
when "01" & x"985" => data <= x"85";
when "01" & x"986" => data <= x"b4";
when "01" & x"987" => data <= x"bf";
when "01" & x"988" => data <= x"c7";
when "01" & x"989" => data <= x"cf";
when "01" & x"98a" => data <= x"a0";
when "01" & x"98b" => data <= x"a9";
when "01" & x"98c" => data <= x"87";
when "01" & x"98d" => data <= x"87";
when "01" & x"98e" => data <= x"97";
when "01" & x"98f" => data <= x"97";
when "01" & x"990" => data <= x"97";
when "01" & x"991" => data <= x"97";
when "01" & x"992" => data <= x"97";
when "01" & x"993" => data <= x"97";
when "01" & x"994" => data <= x"12";
when "01" & x"995" => data <= x"32";
when "01" & x"996" => data <= x"5d";
when "01" & x"997" => data <= x"cd";
when "01" & x"998" => data <= x"a2";
when "01" & x"999" => data <= x"bd";
when "01" & x"99a" => data <= x"87";
when "01" & x"99b" => data <= x"8d";
when "01" & x"99c" => data <= x"8d";
when "01" & x"99d" => data <= x"8d";
when "01" & x"99e" => data <= x"8d";
when "01" & x"99f" => data <= x"8d";
when "01" & x"9a0" => data <= x"8d";
when "01" & x"9a1" => data <= x"8d";
when "01" & x"9a2" => data <= x"74";
when "01" & x"9a3" => data <= x"54";
when "01" & x"9a4" => data <= x"00";
when "01" & x"9a5" => data <= x"0f";
when "01" & x"9a6" => data <= x"1a";
when "01" & x"9a7" => data <= x"0f";
when "01" & x"9a8" => data <= x"1a";
when "01" & x"9a9" => data <= x"63";
when "01" & x"9aa" => data <= x"43";
when "01" & x"9ab" => data <= x"b7";
when "01" & x"9ac" => data <= x"7d";
when "01" & x"9ad" => data <= x"7d";
when "01" & x"9ae" => data <= x"65";
when "01" & x"9af" => data <= x"65";
when "01" & x"9b0" => data <= x"cf";
when "01" & x"9b1" => data <= x"00";
when "01" & x"9b2" => data <= x"14";
when "01" & x"9b3" => data <= x"83";
when "01" & x"9b4" => data <= x"85";
when "01" & x"9b5" => data <= x"97";
when "01" & x"9b6" => data <= x"97";
when "01" & x"9b7" => data <= x"97";
when "01" & x"9b8" => data <= x"97";
when "01" & x"9b9" => data <= x"96";
when "01" & x"9ba" => data <= x"97";
when "01" & x"9bb" => data <= x"97";
when "01" & x"9bc" => data <= x"96";
when "01" & x"9bd" => data <= x"04";
when "01" & x"9be" => data <= x"02";
when "01" & x"9bf" => data <= x"03";
when "01" & x"9c0" => data <= x"06";
when "01" & x"9c1" => data <= x"07";
when "01" & x"9c2" => data <= x"04";
when "01" & x"9c3" => data <= x"04";
when "01" & x"9c4" => data <= x"04";
when "01" & x"9c5" => data <= x"04";
when "01" & x"9c6" => data <= x"98";
when "01" & x"9c7" => data <= x"a2";
when "01" & x"9c8" => data <= x"ff";
when "01" & x"9c9" => data <= x"a0";
when "01" & x"9ca" => data <= x"0e";
when "01" & x"9cb" => data <= x"48";
when "01" & x"9cc" => data <= x"20";
when "01" & x"9cd" => data <= x"65";
when "01" & x"9ce" => data <= x"80";
when "01" & x"9cf" => data <= x"0d";
when "01" & x"9d0" => data <= x"44";
when "01" & x"9d1" => data <= x"46";
when "01" & x"9d2" => data <= x"53";
when "01" & x"9d3" => data <= x"20";
when "01" & x"9d4" => data <= x"30";
when "01" & x"9d5" => data <= x"2e";
when "01" & x"9d6" => data <= x"39";
when "01" & x"9d7" => data <= x"30";
when "01" & x"9d8" => data <= x"0d";
when "01" & x"9d9" => data <= x"86";
when "01" & x"9da" => data <= x"b8";
when "01" & x"9db" => data <= x"20";
when "01" & x"9dc" => data <= x"cb";
when "01" & x"9dd" => data <= x"9f";
when "01" & x"9de" => data <= x"20";
when "01" & x"9df" => data <= x"19";
when "01" & x"9e0" => data <= x"9a";
when "01" & x"9e1" => data <= x"20";
when "01" & x"9e2" => data <= x"9a";
when "01" & x"9e3" => data <= x"9f";
when "01" & x"9e4" => data <= x"88";
when "01" & x"9e5" => data <= x"d0";
when "01" & x"9e6" => data <= x"f4";
when "01" & x"9e7" => data <= x"68";
when "01" & x"9e8" => data <= x"a8";
when "01" & x"9e9" => data <= x"a2";
when "01" & x"9ea" => data <= x"a0";
when "01" & x"9eb" => data <= x"4c";
when "01" & x"9ec" => data <= x"71";
when "01" & x"9ed" => data <= x"86";
when "01" & x"9ee" => data <= x"98";
when "01" & x"9ef" => data <= x"a2";
when "01" & x"9f0" => data <= x"74";
when "01" & x"9f1" => data <= x"a0";
when "01" & x"9f2" => data <= x"05";
when "01" & x"9f3" => data <= x"d0";
when "01" & x"9f4" => data <= x"d6";
when "01" & x"9f5" => data <= x"20";
when "01" & x"9f6" => data <= x"bf";
when "01" & x"9f7" => data <= x"86";
when "01" & x"9f8" => data <= x"f0";
when "01" & x"9f9" => data <= x"60";
when "01" & x"9fa" => data <= x"20";
when "01" & x"9fb" => data <= x"c5";
when "01" & x"9fc" => data <= x"ff";
when "01" & x"9fd" => data <= x"90";
when "01" & x"9fe" => data <= x"fb";
when "01" & x"9ff" => data <= x"b0";
when "01" & x"a00" => data <= x"e8";
when "01" & x"a01" => data <= x"20";
when "01" & x"a02" => data <= x"bf";
when "01" & x"a03" => data <= x"86";
when "01" & x"a04" => data <= x"d0";
when "01" & x"a05" => data <= x"54";
when "01" & x"a06" => data <= x"20";
when "01" & x"a07" => data <= x"33";
when "01" & x"a08" => data <= x"80";
when "01" & x"a09" => data <= x"dc";
when "01" & x"a0a" => data <= x"53";
when "01" & x"a0b" => data <= x"79";
when "01" & x"a0c" => data <= x"6e";
when "01" & x"a0d" => data <= x"74";
when "01" & x"a0e" => data <= x"61";
when "01" & x"a0f" => data <= x"78";
when "01" & x"a10" => data <= x"3a";
when "01" & x"a11" => data <= x"20";
when "01" & x"a12" => data <= x"ea";
when "01" & x"a13" => data <= x"20";
when "01" & x"a14" => data <= x"19";
when "01" & x"a15" => data <= x"9a";
when "01" & x"a16" => data <= x"4c";
when "01" & x"a17" => data <= x"8a";
when "01" & x"a18" => data <= x"80";
when "01" & x"a19" => data <= x"a6";
when "01" & x"a1a" => data <= x"b8";
when "01" & x"a1b" => data <= x"e8";
when "01" & x"a1c" => data <= x"bd";
when "01" & x"a1d" => data <= x"b8";
when "01" & x"a1e" => data <= x"85";
when "01" & x"a1f" => data <= x"30";
when "01" & x"a20" => data <= x"06";
when "01" & x"a21" => data <= x"20";
when "01" & x"a22" => data <= x"9c";
when "01" & x"a23" => data <= x"80";
when "01" & x"a24" => data <= x"4c";
when "01" & x"a25" => data <= x"1b";
when "01" & x"a26" => data <= x"9a";
when "01" & x"a27" => data <= x"e8";
when "01" & x"a28" => data <= x"e8";
when "01" & x"a29" => data <= x"86";
when "01" & x"a2a" => data <= x"b8";
when "01" & x"a2b" => data <= x"bd";
when "01" & x"a2c" => data <= x"b8";
when "01" & x"a2d" => data <= x"85";
when "01" & x"a2e" => data <= x"20";
when "01" & x"a2f" => data <= x"34";
when "01" & x"a30" => data <= x"9a";
when "01" & x"a31" => data <= x"20";
when "01" & x"a32" => data <= x"05";
when "01" & x"a33" => data <= x"82";
when "01" & x"a34" => data <= x"20";
when "01" & x"a35" => data <= x"e1";
when "01" & x"a36" => data <= x"83";
when "01" & x"a37" => data <= x"29";
when "01" & x"a38" => data <= x"0f";
when "01" & x"a39" => data <= x"f0";
when "01" & x"a3a" => data <= x"1f";
when "01" & x"a3b" => data <= x"a8";
when "01" & x"a3c" => data <= x"a9";
when "01" & x"a3d" => data <= x"20";
when "01" & x"a3e" => data <= x"20";
when "01" & x"a3f" => data <= x"9c";
when "01" & x"a40" => data <= x"80";
when "01" & x"a41" => data <= x"a2";
when "01" & x"a42" => data <= x"00";
when "01" & x"a43" => data <= x"bd";
when "01" & x"a44" => data <= x"5b";
when "01" & x"a45" => data <= x"9a";
when "01" & x"a46" => data <= x"f0";
when "01" & x"a47" => data <= x"03";
when "01" & x"a48" => data <= x"e8";
when "01" & x"a49" => data <= x"d0";
when "01" & x"a4a" => data <= x"f8";
when "01" & x"a4b" => data <= x"88";
when "01" & x"a4c" => data <= x"d0";
when "01" & x"a4d" => data <= x"fa";
when "01" & x"a4e" => data <= x"e8";
when "01" & x"a4f" => data <= x"bd";
when "01" & x"a50" => data <= x"5b";
when "01" & x"a51" => data <= x"9a";
when "01" & x"a52" => data <= x"f0";
when "01" & x"a53" => data <= x"06";
when "01" & x"a54" => data <= x"20";
when "01" & x"a55" => data <= x"9c";
when "01" & x"a56" => data <= x"80";
when "01" & x"a57" => data <= x"4c";
when "01" & x"a58" => data <= x"4e";
when "01" & x"a59" => data <= x"9a";
when "01" & x"a5a" => data <= x"60";
when "01" & x"a5b" => data <= x"00";
when "01" & x"a5c" => data <= x"3c";
when "01" & x"a5d" => data <= x"66";
when "01" & x"a5e" => data <= x"73";
when "01" & x"a5f" => data <= x"70";
when "01" & x"a60" => data <= x"3e";
when "01" & x"a61" => data <= x"00";
when "01" & x"a62" => data <= x"3c";
when "01" & x"a63" => data <= x"61";
when "01" & x"a64" => data <= x"66";
when "01" & x"a65" => data <= x"73";
when "01" & x"a66" => data <= x"70";
when "01" & x"a67" => data <= x"3e";
when "01" & x"a68" => data <= x"00";
when "01" & x"a69" => data <= x"28";
when "01" & x"a6a" => data <= x"4c";
when "01" & x"a6b" => data <= x"29";
when "01" & x"a6c" => data <= x"00";
when "01" & x"a6d" => data <= x"3c";
when "01" & x"a6e" => data <= x"73";
when "01" & x"a6f" => data <= x"72";
when "01" & x"a70" => data <= x"63";
when "01" & x"a71" => data <= x"20";
when "01" & x"a72" => data <= x"64";
when "01" & x"a73" => data <= x"72";
when "01" & x"a74" => data <= x"76";
when "01" & x"a75" => data <= x"3e";
when "01" & x"a76" => data <= x"00";
when "01" & x"a77" => data <= x"3c";
when "01" & x"a78" => data <= x"64";
when "01" & x"a79" => data <= x"65";
when "01" & x"a7a" => data <= x"73";
when "01" & x"a7b" => data <= x"74";
when "01" & x"a7c" => data <= x"20";
when "01" & x"a7d" => data <= x"64";
when "01" & x"a7e" => data <= x"72";
when "01" & x"a7f" => data <= x"76";
when "01" & x"a80" => data <= x"3e";
when "01" & x"a81" => data <= x"00";
when "01" & x"a82" => data <= x"3c";
when "01" & x"a83" => data <= x"64";
when "01" & x"a84" => data <= x"65";
when "01" & x"a85" => data <= x"73";
when "01" & x"a86" => data <= x"74";
when "01" & x"a87" => data <= x"20";
when "01" & x"a88" => data <= x"64";
when "01" & x"a89" => data <= x"72";
when "01" & x"a8a" => data <= x"76";
when "01" & x"a8b" => data <= x"3e";
when "01" & x"a8c" => data <= x"20";
when "01" & x"a8d" => data <= x"3c";
when "01" & x"a8e" => data <= x"61";
when "01" & x"a8f" => data <= x"66";
when "01" & x"a90" => data <= x"73";
when "01" & x"a91" => data <= x"70";
when "01" & x"a92" => data <= x"3e";
when "01" & x"a93" => data <= x"00";
when "01" & x"a94" => data <= x"3c";
when "01" & x"a95" => data <= x"6f";
when "01" & x"a96" => data <= x"6c";
when "01" & x"a97" => data <= x"64";
when "01" & x"a98" => data <= x"20";
when "01" & x"a99" => data <= x"66";
when "01" & x"a9a" => data <= x"73";
when "01" & x"a9b" => data <= x"70";
when "01" & x"a9c" => data <= x"3e";
when "01" & x"a9d" => data <= x"00";
when "01" & x"a9e" => data <= x"3c";
when "01" & x"a9f" => data <= x"6e";
when "01" & x"aa0" => data <= x"65";
when "01" & x"aa1" => data <= x"77";
when "01" & x"aa2" => data <= x"20";
when "01" & x"aa3" => data <= x"66";
when "01" & x"aa4" => data <= x"73";
when "01" & x"aa5" => data <= x"70";
when "01" & x"aa6" => data <= x"3e";
when "01" & x"aa7" => data <= x"00";
when "01" & x"aa8" => data <= x"28";
when "01" & x"aa9" => data <= x"3c";
when "01" & x"aaa" => data <= x"64";
when "01" & x"aab" => data <= x"69";
when "01" & x"aac" => data <= x"72";
when "01" & x"aad" => data <= x"3e";
when "01" & x"aae" => data <= x"29";
when "01" & x"aaf" => data <= x"00";
when "01" & x"ab0" => data <= x"28";
when "01" & x"ab1" => data <= x"3c";
when "01" & x"ab2" => data <= x"64";
when "01" & x"ab3" => data <= x"72";
when "01" & x"ab4" => data <= x"76";
when "01" & x"ab5" => data <= x"3e";
when "01" & x"ab6" => data <= x"29";
when "01" & x"ab7" => data <= x"00";
when "01" & x"ab8" => data <= x"3c";
when "01" & x"ab9" => data <= x"74";
when "01" & x"aba" => data <= x"69";
when "01" & x"abb" => data <= x"74";
when "01" & x"abc" => data <= x"6c";
when "01" & x"abd" => data <= x"65";
when "01" & x"abe" => data <= x"3e";
when "01" & x"abf" => data <= x"00";
when "01" & x"ac0" => data <= x"20";
when "01" & x"ac1" => data <= x"58";
when "01" & x"ac2" => data <= x"83";
when "01" & x"ac3" => data <= x"20";
when "01" & x"ac4" => data <= x"65";
when "01" & x"ac5" => data <= x"80";
when "01" & x"ac6" => data <= x"43";
when "01" & x"ac7" => data <= x"6f";
when "01" & x"ac8" => data <= x"6d";
when "01" & x"ac9" => data <= x"70";
when "01" & x"aca" => data <= x"61";
when "01" & x"acb" => data <= x"63";
when "01" & x"acc" => data <= x"74";
when "01" & x"acd" => data <= x"69";
when "01" & x"ace" => data <= x"6e";
when "01" & x"acf" => data <= x"67";
when "01" & x"ad0" => data <= x"20";
when "01" & x"ad1" => data <= x"64";
when "01" & x"ad2" => data <= x"72";
when "01" & x"ad3" => data <= x"69";
when "01" & x"ad4" => data <= x"76";
when "01" & x"ad5" => data <= x"65";
when "01" & x"ad6" => data <= x"20";
when "01" & x"ad7" => data <= x"8d";
when "01" & x"ad8" => data <= x"d2";
when "01" & x"ad9" => data <= x"10";
when "01" & x"ada" => data <= x"8d";
when "01" & x"adb" => data <= x"d3";
when "01" & x"adc" => data <= x"10";
when "01" & x"add" => data <= x"20";
when "01" & x"ade" => data <= x"ca";
when "01" & x"adf" => data <= x"80";
when "01" & x"ae0" => data <= x"20";
when "01" & x"ae1" => data <= x"9a";
when "01" & x"ae2" => data <= x"9f";
when "01" & x"ae3" => data <= x"a0";
when "01" & x"ae4" => data <= x"00";
when "01" & x"ae5" => data <= x"20";
when "01" & x"ae6" => data <= x"05";
when "01" & x"ae7" => data <= x"8e";
when "01" & x"ae8" => data <= x"20";
when "01" & x"ae9" => data <= x"79";
when "01" & x"aea" => data <= x"98";
when "01" & x"aeb" => data <= x"20";
when "01" & x"aec" => data <= x"47";
when "01" & x"aed" => data <= x"83";
when "01" & x"aee" => data <= x"ac";
when "01" & x"aef" => data <= x"05";
when "01" & x"af0" => data <= x"0f";
when "01" & x"af1" => data <= x"84";
when "01" & x"af2" => data <= x"cc";
when "01" & x"af3" => data <= x"a9";
when "01" & x"af4" => data <= x"02";
when "01" & x"af5" => data <= x"85";
when "01" & x"af6" => data <= x"ca";
when "01" & x"af7" => data <= x"a9";
when "01" & x"af8" => data <= x"00";
when "01" & x"af9" => data <= x"85";
when "01" & x"afa" => data <= x"cb";
when "01" & x"afb" => data <= x"a4";
when "01" & x"afc" => data <= x"cc";
when "01" & x"afd" => data <= x"20";
when "01" & x"afe" => data <= x"19";
when "01" & x"aff" => data <= x"82";
when "01" & x"b00" => data <= x"c0";
when "01" & x"b01" => data <= x"f8";
when "01" & x"b02" => data <= x"d0";
when "01" & x"b03" => data <= x"3c";
when "01" & x"b04" => data <= x"20";
when "01" & x"b05" => data <= x"65";
when "01" & x"b06" => data <= x"80";
when "01" & x"b07" => data <= x"44";
when "01" & x"b08" => data <= x"69";
when "01" & x"b09" => data <= x"73";
when "01" & x"b0a" => data <= x"6b";
when "01" & x"b0b" => data <= x"20";
when "01" & x"b0c" => data <= x"63";
when "01" & x"b0d" => data <= x"6f";
when "01" & x"b0e" => data <= x"6d";
when "01" & x"b0f" => data <= x"70";
when "01" & x"b10" => data <= x"61";
when "01" & x"b11" => data <= x"63";
when "01" & x"b12" => data <= x"74";
when "01" & x"b13" => data <= x"65";
when "01" & x"b14" => data <= x"64";
when "01" & x"b15" => data <= x"20";
when "01" & x"b16" => data <= x"ea";
when "01" & x"b17" => data <= x"38";
when "01" & x"b18" => data <= x"ad";
when "01" & x"b19" => data <= x"07";
when "01" & x"b1a" => data <= x"0f";
when "01" & x"b1b" => data <= x"e5";
when "01" & x"b1c" => data <= x"ca";
when "01" & x"b1d" => data <= x"48";
when "01" & x"b1e" => data <= x"ad";
when "01" & x"b1f" => data <= x"06";
when "01" & x"b20" => data <= x"0f";
when "01" & x"b21" => data <= x"29";
when "01" & x"b22" => data <= x"03";
when "01" & x"b23" => data <= x"e5";
when "01" & x"b24" => data <= x"cb";
when "01" & x"b25" => data <= x"20";
when "01" & x"b26" => data <= x"ca";
when "01" & x"b27" => data <= x"80";
when "01" & x"b28" => data <= x"68";
when "01" & x"b29" => data <= x"20";
when "01" & x"b2a" => data <= x"c2";
when "01" & x"b2b" => data <= x"80";
when "01" & x"b2c" => data <= x"20";
when "01" & x"b2d" => data <= x"65";
when "01" & x"b2e" => data <= x"80";
when "01" & x"b2f" => data <= x"20";
when "01" & x"b30" => data <= x"66";
when "01" & x"b31" => data <= x"72";
when "01" & x"b32" => data <= x"65";
when "01" & x"b33" => data <= x"65";
when "01" & x"b34" => data <= x"20";
when "01" & x"b35" => data <= x"73";
when "01" & x"b36" => data <= x"65";
when "01" & x"b37" => data <= x"63";
when "01" & x"b38" => data <= x"74";
when "01" & x"b39" => data <= x"6f";
when "01" & x"b3a" => data <= x"72";
when "01" & x"b3b" => data <= x"73";
when "01" & x"b3c" => data <= x"0d";
when "01" & x"b3d" => data <= x"a9";
when "01" & x"b3e" => data <= x"04";
when "01" & x"b3f" => data <= x"60";
when "01" & x"b40" => data <= x"84";
when "01" & x"b41" => data <= x"cc";
when "01" & x"b42" => data <= x"20";
when "01" & x"b43" => data <= x"fc";
when "01" & x"b44" => data <= x"82";
when "01" & x"b45" => data <= x"a4";
when "01" & x"b46" => data <= x"cc";
when "01" & x"b47" => data <= x"b9";
when "01" & x"b48" => data <= x"0e";
when "01" & x"b49" => data <= x"0f";
when "01" & x"b4a" => data <= x"29";
when "01" & x"b4b" => data <= x"30";
when "01" & x"b4c" => data <= x"19";
when "01" & x"b4d" => data <= x"0d";
when "01" & x"b4e" => data <= x"0f";
when "01" & x"b4f" => data <= x"19";
when "01" & x"b50" => data <= x"0c";
when "01" & x"b51" => data <= x"0f";
when "01" & x"b52" => data <= x"f0";
when "01" & x"b53" => data <= x"61";
when "01" & x"b54" => data <= x"a9";
when "01" & x"b55" => data <= x"00";
when "01" & x"b56" => data <= x"85";
when "01" & x"b57" => data <= x"be";
when "01" & x"b58" => data <= x"85";
when "01" & x"b59" => data <= x"c2";
when "01" & x"b5a" => data <= x"a9";
when "01" & x"b5b" => data <= x"ff";
when "01" & x"b5c" => data <= x"18";
when "01" & x"b5d" => data <= x"79";
when "01" & x"b5e" => data <= x"0c";
when "01" & x"b5f" => data <= x"0f";
when "01" & x"b60" => data <= x"a9";
when "01" & x"b61" => data <= x"00";
when "01" & x"b62" => data <= x"79";
when "01" & x"b63" => data <= x"0d";
when "01" & x"b64" => data <= x"0f";
when "01" & x"b65" => data <= x"85";
when "01" & x"b66" => data <= x"c6";
when "01" & x"b67" => data <= x"b9";
when "01" & x"b68" => data <= x"0e";
when "01" & x"b69" => data <= x"0f";
when "01" & x"b6a" => data <= x"08";
when "01" & x"b6b" => data <= x"20";
when "01" & x"b6c" => data <= x"fd";
when "01" & x"b6d" => data <= x"81";
when "01" & x"b6e" => data <= x"28";
when "01" & x"b6f" => data <= x"69";
when "01" & x"b70" => data <= x"00";
when "01" & x"b71" => data <= x"85";
when "01" & x"b72" => data <= x"c7";
when "01" & x"b73" => data <= x"b9";
when "01" & x"b74" => data <= x"0f";
when "01" & x"b75" => data <= x"0f";
when "01" & x"b76" => data <= x"85";
when "01" & x"b77" => data <= x"c8";
when "01" & x"b78" => data <= x"b9";
when "01" & x"b79" => data <= x"0e";
when "01" & x"b7a" => data <= x"0f";
when "01" & x"b7b" => data <= x"29";
when "01" & x"b7c" => data <= x"03";
when "01" & x"b7d" => data <= x"85";
when "01" & x"b7e" => data <= x"c9";
when "01" & x"b7f" => data <= x"c5";
when "01" & x"b80" => data <= x"cb";
when "01" & x"b81" => data <= x"d0";
when "01" & x"b82" => data <= x"14";
when "01" & x"b83" => data <= x"a5";
when "01" & x"b84" => data <= x"c8";
when "01" & x"b85" => data <= x"c5";
when "01" & x"b86" => data <= x"ca";
when "01" & x"b87" => data <= x"d0";
when "01" & x"b88" => data <= x"0e";
when "01" & x"b89" => data <= x"18";
when "01" & x"b8a" => data <= x"65";
when "01" & x"b8b" => data <= x"c6";
when "01" & x"b8c" => data <= x"85";
when "01" & x"b8d" => data <= x"ca";
when "01" & x"b8e" => data <= x"a5";
when "01" & x"b8f" => data <= x"cb";
when "01" & x"b90" => data <= x"65";
when "01" & x"b91" => data <= x"c7";
when "01" & x"b92" => data <= x"85";
when "01" & x"b93" => data <= x"cb";
when "01" & x"b94" => data <= x"4c";
when "01" & x"b95" => data <= x"b5";
when "01" & x"b96" => data <= x"9b";
when "01" & x"b97" => data <= x"a5";
when "01" & x"b98" => data <= x"ca";
when "01" & x"b99" => data <= x"99";
when "01" & x"b9a" => data <= x"0f";
when "01" & x"b9b" => data <= x"0f";
when "01" & x"b9c" => data <= x"b9";
when "01" & x"b9d" => data <= x"0e";
when "01" & x"b9e" => data <= x"0f";
when "01" & x"b9f" => data <= x"29";
when "01" & x"ba0" => data <= x"fc";
when "01" & x"ba1" => data <= x"05";
when "01" & x"ba2" => data <= x"cb";
when "01" & x"ba3" => data <= x"99";
when "01" & x"ba4" => data <= x"0e";
when "01" & x"ba5" => data <= x"0f";
when "01" & x"ba6" => data <= x"a9";
when "01" & x"ba7" => data <= x"00";
when "01" & x"ba8" => data <= x"85";
when "01" & x"ba9" => data <= x"a8";
when "01" & x"baa" => data <= x"85";
when "01" & x"bab" => data <= x"a9";
when "01" & x"bac" => data <= x"20";
when "01" & x"bad" => data <= x"b4";
when "01" & x"bae" => data <= x"8a";
when "01" & x"baf" => data <= x"20";
when "01" & x"bb0" => data <= x"06";
when "01" & x"bb1" => data <= x"9e";
when "01" & x"bb2" => data <= x"20";
when "01" & x"bb3" => data <= x"47";
when "01" & x"bb4" => data <= x"83";
when "01" & x"bb5" => data <= x"a4";
when "01" & x"bb6" => data <= x"cc";
when "01" & x"bb7" => data <= x"20";
when "01" & x"bb8" => data <= x"01";
when "01" & x"bb9" => data <= x"83";
when "01" & x"bba" => data <= x"4c";
when "01" & x"bbb" => data <= x"fb";
when "01" & x"bbc" => data <= x"9a";
when "01" & x"bbd" => data <= x"2c";
when "01" & x"bbe" => data <= x"c8";
when "01" & x"bbf" => data <= x"10";
when "01" & x"bc0" => data <= x"10";
when "01" & x"bc1" => data <= x"75";
when "01" & x"bc2" => data <= x"20";
when "01" & x"bc3" => data <= x"33";
when "01" & x"bc4" => data <= x"80";
when "01" & x"bc5" => data <= x"bd";
when "01" & x"bc6" => data <= x"4e";
when "01" & x"bc7" => data <= x"6f";
when "01" & x"bc8" => data <= x"74";
when "01" & x"bc9" => data <= x"20";
when "01" & x"bca" => data <= x"65";
when "01" & x"bcb" => data <= x"6e";
when "01" & x"bcc" => data <= x"61";
when "01" & x"bcd" => data <= x"62";
when "01" & x"bce" => data <= x"6c";
when "01" & x"bcf" => data <= x"65";
when "01" & x"bd0" => data <= x"64";
when "01" & x"bd1" => data <= x"00";
when "01" & x"bd2" => data <= x"20";
when "01" & x"bd3" => data <= x"bf";
when "01" & x"bd4" => data <= x"86";
when "01" & x"bd5" => data <= x"d0";
when "01" & x"bd6" => data <= x"03";
when "01" & x"bd7" => data <= x"4c";
when "01" & x"bd8" => data <= x"06";
when "01" & x"bd9" => data <= x"9a";
when "01" & x"bda" => data <= x"20";
when "01" & x"bdb" => data <= x"5d";
when "01" & x"bdc" => data <= x"83";
when "01" & x"bdd" => data <= x"8d";
when "01" & x"bde" => data <= x"d2";
when "01" & x"bdf" => data <= x"10";
when "01" & x"be0" => data <= x"20";
when "01" & x"be1" => data <= x"bf";
when "01" & x"be2" => data <= x"86";
when "01" & x"be3" => data <= x"f0";
when "01" & x"be4" => data <= x"f2";
when "01" & x"be5" => data <= x"20";
when "01" & x"be6" => data <= x"5d";
when "01" & x"be7" => data <= x"83";
when "01" & x"be8" => data <= x"8d";
when "01" & x"be9" => data <= x"d3";
when "01" & x"bea" => data <= x"10";
when "01" & x"beb" => data <= x"98";
when "01" & x"bec" => data <= x"48";
when "01" & x"bed" => data <= x"a9";
when "01" & x"bee" => data <= x"00";
when "01" & x"bef" => data <= x"85";
when "01" & x"bf0" => data <= x"a9";
when "01" & x"bf1" => data <= x"ad";
when "01" & x"bf2" => data <= x"d3";
when "01" & x"bf3" => data <= x"10";
when "01" & x"bf4" => data <= x"cd";
when "01" & x"bf5" => data <= x"d2";
when "01" & x"bf6" => data <= x"10";
when "01" & x"bf7" => data <= x"d0";
when "01" & x"bf8" => data <= x"06";
when "01" & x"bf9" => data <= x"a9";
when "01" & x"bfa" => data <= x"ff";
when "01" & x"bfb" => data <= x"85";
when "01" & x"bfc" => data <= x"a9";
when "01" & x"bfd" => data <= x"85";
when "01" & x"bfe" => data <= x"aa";
when "01" & x"bff" => data <= x"20";
when "01" & x"c00" => data <= x"79";
when "01" & x"c01" => data <= x"98";
when "01" & x"c02" => data <= x"20";
when "01" & x"c03" => data <= x"65";
when "01" & x"c04" => data <= x"80";
when "01" & x"c05" => data <= x"43";
when "01" & x"c06" => data <= x"6f";
when "01" & x"c07" => data <= x"70";
when "01" & x"c08" => data <= x"79";
when "01" & x"c09" => data <= x"69";
when "01" & x"c0a" => data <= x"6e";
when "01" & x"c0b" => data <= x"67";
when "01" & x"c0c" => data <= x"20";
when "01" & x"c0d" => data <= x"66";
when "01" & x"c0e" => data <= x"72";
when "01" & x"c0f" => data <= x"6f";
when "01" & x"c10" => data <= x"6d";
when "01" & x"c11" => data <= x"20";
when "01" & x"c12" => data <= x"64";
when "01" & x"c13" => data <= x"72";
when "01" & x"c14" => data <= x"69";
when "01" & x"c15" => data <= x"76";
when "01" & x"c16" => data <= x"65";
when "01" & x"c17" => data <= x"20";
when "01" & x"c18" => data <= x"ad";
when "01" & x"c19" => data <= x"d2";
when "01" & x"c1a" => data <= x"10";
when "01" & x"c1b" => data <= x"20";
when "01" & x"c1c" => data <= x"ca";
when "01" & x"c1d" => data <= x"80";
when "01" & x"c1e" => data <= x"20";
when "01" & x"c1f" => data <= x"65";
when "01" & x"c20" => data <= x"80";
when "01" & x"c21" => data <= x"20";
when "01" & x"c22" => data <= x"74";
when "01" & x"c23" => data <= x"6f";
when "01" & x"c24" => data <= x"20";
when "01" & x"c25" => data <= x"64";
when "01" & x"c26" => data <= x"72";
when "01" & x"c27" => data <= x"69";
when "01" & x"c28" => data <= x"76";
when "01" & x"c29" => data <= x"65";
when "01" & x"c2a" => data <= x"20";
when "01" & x"c2b" => data <= x"ad";
when "01" & x"c2c" => data <= x"d3";
when "01" & x"c2d" => data <= x"10";
when "01" & x"c2e" => data <= x"20";
when "01" & x"c2f" => data <= x"ca";
when "01" & x"c30" => data <= x"80";
when "01" & x"c31" => data <= x"20";
when "01" & x"c32" => data <= x"9a";
when "01" & x"c33" => data <= x"9f";
when "01" & x"c34" => data <= x"68";
when "01" & x"c35" => data <= x"a8";
when "01" & x"c36" => data <= x"18";
when "01" & x"c37" => data <= x"60";
when "01" & x"c38" => data <= x"20";
when "01" & x"c39" => data <= x"e1";
when "01" & x"c3a" => data <= x"83";
when "01" & x"c3b" => data <= x"24";
when "01" & x"c3c" => data <= x"a9";
when "01" & x"c3d" => data <= x"10";
when "01" & x"c3e" => data <= x"0b";
when "01" & x"c3f" => data <= x"a9";
when "01" & x"c40" => data <= x"00";
when "01" & x"c41" => data <= x"f0";
when "01" & x"c42" => data <= x"0a";
when "01" & x"c43" => data <= x"20";
when "01" & x"c44" => data <= x"e1";
when "01" & x"c45" => data <= x"83";
when "01" & x"c46" => data <= x"24";
when "01" & x"c47" => data <= x"a9";
when "01" & x"c48" => data <= x"30";
when "01" & x"c49" => data <= x"01";
when "01" & x"c4a" => data <= x"60";
when "01" & x"c4b" => data <= x"a9";
when "01" & x"c4c" => data <= x"80";
when "01" & x"c4d" => data <= x"c5";
when "01" & x"c4e" => data <= x"aa";
when "01" & x"c4f" => data <= x"f0";
when "01" & x"c50" => data <= x"f9";
when "01" & x"c51" => data <= x"85";
when "01" & x"c52" => data <= x"aa";
when "01" & x"c53" => data <= x"20";
when "01" & x"c54" => data <= x"65";
when "01" & x"c55" => data <= x"80";
when "01" & x"c56" => data <= x"49";
when "01" & x"c57" => data <= x"6e";
when "01" & x"c58" => data <= x"73";
when "01" & x"c59" => data <= x"65";
when "01" & x"c5a" => data <= x"72";
when "01" & x"c5b" => data <= x"74";
when "01" & x"c5c" => data <= x"20";
when "01" & x"c5d" => data <= x"ea";
when "01" & x"c5e" => data <= x"24";
when "01" & x"c5f" => data <= x"aa";
when "01" & x"c60" => data <= x"30";
when "01" & x"c61" => data <= x"0b";
when "01" & x"c62" => data <= x"20";
when "01" & x"c63" => data <= x"65";
when "01" & x"c64" => data <= x"80";
when "01" & x"c65" => data <= x"73";
when "01" & x"c66" => data <= x"6f";
when "01" & x"c67" => data <= x"75";
when "01" & x"c68" => data <= x"72";
when "01" & x"c69" => data <= x"63";
when "01" & x"c6a" => data <= x"65";
when "01" & x"c6b" => data <= x"90";
when "01" & x"c6c" => data <= x"0f";
when "01" & x"c6d" => data <= x"20";
when "01" & x"c6e" => data <= x"65";
when "01" & x"c6f" => data <= x"80";
when "01" & x"c70" => data <= x"64";
when "01" & x"c71" => data <= x"65";
when "01" & x"c72" => data <= x"73";
when "01" & x"c73" => data <= x"74";
when "01" & x"c74" => data <= x"69";
when "01" & x"c75" => data <= x"6e";
when "01" & x"c76" => data <= x"61";
when "01" & x"c77" => data <= x"74";
when "01" & x"c78" => data <= x"69";
when "01" & x"c79" => data <= x"6f";
when "01" & x"c7a" => data <= x"6e";
when "01" & x"c7b" => data <= x"ea";
when "01" & x"c7c" => data <= x"20";
when "01" & x"c7d" => data <= x"65";
when "01" & x"c7e" => data <= x"80";
when "01" & x"c7f" => data <= x"20";
when "01" & x"c80" => data <= x"64";
when "01" & x"c81" => data <= x"69";
when "01" & x"c82" => data <= x"73";
when "01" & x"c83" => data <= x"6b";
when "01" & x"c84" => data <= x"20";
when "01" & x"c85" => data <= x"61";
when "01" & x"c86" => data <= x"6e";
when "01" & x"c87" => data <= x"64";
when "01" & x"c88" => data <= x"20";
when "01" & x"c89" => data <= x"68";
when "01" & x"c8a" => data <= x"69";
when "01" & x"c8b" => data <= x"74";
when "01" & x"c8c" => data <= x"20";
when "01" & x"c8d" => data <= x"61";
when "01" & x"c8e" => data <= x"20";
when "01" & x"c8f" => data <= x"6b";
when "01" & x"c90" => data <= x"65";
when "01" & x"c91" => data <= x"79";
when "01" & x"c92" => data <= x"ea";
when "01" & x"c93" => data <= x"20";
when "01" & x"c94" => data <= x"06";
when "01" & x"c95" => data <= x"99";
when "01" & x"c96" => data <= x"20";
when "01" & x"c97" => data <= x"e0";
when "01" & x"c98" => data <= x"ff";
when "01" & x"c99" => data <= x"b0";
when "01" & x"c9a" => data <= x"19";
when "01" & x"c9b" => data <= x"4c";
when "01" & x"c9c" => data <= x"9a";
when "01" & x"c9d" => data <= x"9f";
when "01" & x"c9e" => data <= x"20";
when "01" & x"c9f" => data <= x"06";
when "01" & x"ca0" => data <= x"99";
when "01" & x"ca1" => data <= x"20";
when "01" & x"ca2" => data <= x"e0";
when "01" & x"ca3" => data <= x"ff";
when "01" & x"ca4" => data <= x"b0";
when "01" & x"ca5" => data <= x"0e";
when "01" & x"ca6" => data <= x"29";
when "01" & x"ca7" => data <= x"5f";
when "01" & x"ca8" => data <= x"c9";
when "01" & x"ca9" => data <= x"59";
when "01" & x"caa" => data <= x"08";
when "01" & x"cab" => data <= x"f0";
when "01" & x"cac" => data <= x"02";
when "01" & x"cad" => data <= x"a9";
when "01" & x"cae" => data <= x"4e";
when "01" & x"caf" => data <= x"20";
when "01" & x"cb0" => data <= x"9c";
when "01" & x"cb1" => data <= x"80";
when "01" & x"cb2" => data <= x"28";
when "01" & x"cb3" => data <= x"60";
when "01" & x"cb4" => data <= x"a6";
when "01" & x"cb5" => data <= x"b6";
when "01" & x"cb6" => data <= x"9a";
when "01" & x"cb7" => data <= x"60";
when "01" & x"cb8" => data <= x"4c";
when "01" & x"cb9" => data <= x"58";
when "01" & x"cba" => data <= x"89";
when "01" & x"cbb" => data <= x"20";
when "01" & x"cbc" => data <= x"bd";
when "01" & x"cbd" => data <= x"9b";
when "01" & x"cbe" => data <= x"20";
when "01" & x"cbf" => data <= x"d2";
when "01" & x"cc0" => data <= x"9b";
when "01" & x"cc1" => data <= x"a9";
when "01" & x"cc2" => data <= x"00";
when "01" & x"cc3" => data <= x"85";
when "01" & x"cc4" => data <= x"c9";
when "01" & x"cc5" => data <= x"85";
when "01" & x"cc6" => data <= x"cb";
when "01" & x"cc7" => data <= x"85";
when "01" & x"cc8" => data <= x"ca";
when "01" & x"cc9" => data <= x"85";
when "01" & x"cca" => data <= x"c8";
when "01" & x"ccb" => data <= x"85";
when "01" & x"ccc" => data <= x"a8";
when "01" & x"ccd" => data <= x"20";
when "01" & x"cce" => data <= x"38";
when "01" & x"ccf" => data <= x"9c";
when "01" & x"cd0" => data <= x"ad";
when "01" & x"cd1" => data <= x"d2";
when "01" & x"cd2" => data <= x"10";
when "01" & x"cd3" => data <= x"85";
when "01" & x"cd4" => data <= x"cf";
when "01" & x"cd5" => data <= x"20";
when "01" & x"cd6" => data <= x"41";
when "01" & x"cd7" => data <= x"af";
when "01" & x"cd8" => data <= x"ad";
when "01" & x"cd9" => data <= x"07";
when "01" & x"cda" => data <= x"0f";
when "01" & x"cdb" => data <= x"85";
when "01" & x"cdc" => data <= x"c6";
when "01" & x"cdd" => data <= x"ad";
when "01" & x"cde" => data <= x"06";
when "01" & x"cdf" => data <= x"0f";
when "01" & x"ce0" => data <= x"29";
when "01" & x"ce1" => data <= x"03";
when "01" & x"ce2" => data <= x"85";
when "01" & x"ce3" => data <= x"c7";
when "01" & x"ce4" => data <= x"ad";
when "01" & x"ce5" => data <= x"06";
when "01" & x"ce6" => data <= x"0f";
when "01" & x"ce7" => data <= x"29";
when "01" & x"ce8" => data <= x"f0";
when "01" & x"ce9" => data <= x"8d";
when "01" & x"cea" => data <= x"d8";
when "01" & x"ceb" => data <= x"10";
when "01" & x"cec" => data <= x"20";
when "01" & x"ced" => data <= x"43";
when "01" & x"cee" => data <= x"9c";
when "01" & x"cef" => data <= x"ad";
when "01" & x"cf0" => data <= x"d3";
when "01" & x"cf1" => data <= x"10";
when "01" & x"cf2" => data <= x"85";
when "01" & x"cf3" => data <= x"cf";
when "01" & x"cf4" => data <= x"20";
when "01" & x"cf5" => data <= x"41";
when "01" & x"cf6" => data <= x"af";
when "01" & x"cf7" => data <= x"ad";
when "01" & x"cf8" => data <= x"06";
when "01" & x"cf9" => data <= x"0f";
when "01" & x"cfa" => data <= x"29";
when "01" & x"cfb" => data <= x"03";
when "01" & x"cfc" => data <= x"c5";
when "01" & x"cfd" => data <= x"c7";
when "01" & x"cfe" => data <= x"90";
when "01" & x"cff" => data <= x"b8";
when "01" & x"d00" => data <= x"d0";
when "01" & x"d01" => data <= x"07";
when "01" & x"d02" => data <= x"ad";
when "01" & x"d03" => data <= x"07";
when "01" & x"d04" => data <= x"0f";
when "01" & x"d05" => data <= x"c5";
when "01" & x"d06" => data <= x"c6";
when "01" & x"d07" => data <= x"90";
when "01" & x"d08" => data <= x"af";
when "01" & x"d09" => data <= x"20";
when "01" & x"d0a" => data <= x"06";
when "01" & x"d0b" => data <= x"9e";
when "01" & x"d0c" => data <= x"ad";
when "01" & x"d0d" => data <= x"06";
when "01" & x"d0e" => data <= x"0f";
when "01" & x"d0f" => data <= x"48";
when "01" & x"d10" => data <= x"ad";
when "01" & x"d11" => data <= x"07";
when "01" & x"d12" => data <= x"0f";
when "01" & x"d13" => data <= x"48";
when "01" & x"d14" => data <= x"20";
when "01" & x"d15" => data <= x"41";
when "01" & x"d16" => data <= x"af";
when "01" & x"d17" => data <= x"68";
when "01" & x"d18" => data <= x"8d";
when "01" & x"d19" => data <= x"07";
when "01" & x"d1a" => data <= x"0f";
when "01" & x"d1b" => data <= x"68";
when "01" & x"d1c" => data <= x"29";
when "01" & x"d1d" => data <= x"0f";
when "01" & x"d1e" => data <= x"0d";
when "01" & x"d1f" => data <= x"d8";
when "01" & x"d20" => data <= x"10";
when "01" & x"d21" => data <= x"8d";
when "01" & x"d22" => data <= x"06";
when "01" & x"d23" => data <= x"0f";
when "01" & x"d24" => data <= x"4c";
when "01" & x"d25" => data <= x"b4";
when "01" & x"d26" => data <= x"8a";
when "01" & x"d27" => data <= x"20";
when "01" & x"d28" => data <= x"5e";
when "01" & x"d29" => data <= x"82";
when "01" & x"d2a" => data <= x"20";
when "01" & x"d2b" => data <= x"d2";
when "01" & x"d2c" => data <= x"9b";
when "01" & x"d2d" => data <= x"20";
when "01" & x"d2e" => data <= x"bf";
when "01" & x"d2f" => data <= x"86";
when "01" & x"d30" => data <= x"d0";
when "01" & x"d31" => data <= x"03";
when "01" & x"d32" => data <= x"4c";
when "01" & x"d33" => data <= x"06";
when "01" & x"d34" => data <= x"9a";
when "01" & x"d35" => data <= x"20";
when "01" & x"d36" => data <= x"fe";
when "01" & x"d37" => data <= x"80";
when "01" & x"d38" => data <= x"20";
when "01" & x"d39" => data <= x"38";
when "01" & x"d3a" => data <= x"9c";
when "01" & x"d3b" => data <= x"ad";
when "01" & x"d3c" => data <= x"d2";
when "01" & x"d3d" => data <= x"10";
when "01" & x"d3e" => data <= x"20";
when "01" & x"d3f" => data <= x"7e";
when "01" & x"d40" => data <= x"87";
when "01" & x"d41" => data <= x"20";
when "01" & x"d42" => data <= x"96";
when "01" & x"d43" => data <= x"82";
when "01" & x"d44" => data <= x"b0";
when "01" & x"d45" => data <= x"03";
when "01" & x"d46" => data <= x"4c";
when "01" & x"d47" => data <= x"76";
when "01" & x"d48" => data <= x"82";
when "01" & x"d49" => data <= x"84";
when "01" & x"d4a" => data <= x"ab";
when "01" & x"d4b" => data <= x"20";
when "01" & x"d4c" => data <= x"01";
when "01" & x"d4d" => data <= x"83";
when "01" & x"d4e" => data <= x"a2";
when "01" & x"d4f" => data <= x"00";
when "01" & x"d50" => data <= x"b5";
when "01" & x"d51" => data <= x"c7";
when "01" & x"d52" => data <= x"9d";
when "01" & x"d53" => data <= x"58";
when "01" & x"d54" => data <= x"10";
when "01" & x"d55" => data <= x"b9";
when "01" & x"d56" => data <= x"08";
when "01" & x"d57" => data <= x"0e";
when "01" & x"d58" => data <= x"95";
when "01" & x"d59" => data <= x"c7";
when "01" & x"d5a" => data <= x"9d";
when "01" & x"d5b" => data <= x"50";
when "01" & x"d5c" => data <= x"10";
when "01" & x"d5d" => data <= x"b9";
when "01" & x"d5e" => data <= x"08";
when "01" & x"d5f" => data <= x"0f";
when "01" & x"d60" => data <= x"95";
when "01" & x"d61" => data <= x"bd";
when "01" & x"d62" => data <= x"9d";
when "01" & x"d63" => data <= x"47";
when "01" & x"d64" => data <= x"10";
when "01" & x"d65" => data <= x"e8";
when "01" & x"d66" => data <= x"c8";
when "01" & x"d67" => data <= x"e0";
when "01" & x"d68" => data <= x"08";
when "01" & x"d69" => data <= x"d0";
when "01" & x"d6a" => data <= x"e5";
when "01" & x"d6b" => data <= x"a5";
when "01" & x"d6c" => data <= x"c3";
when "01" & x"d6d" => data <= x"20";
when "01" & x"d6e" => data <= x"fd";
when "01" & x"d6f" => data <= x"81";
when "01" & x"d70" => data <= x"85";
when "01" & x"d71" => data <= x"c5";
when "01" & x"d72" => data <= x"a5";
when "01" & x"d73" => data <= x"c1";
when "01" & x"d74" => data <= x"18";
when "01" & x"d75" => data <= x"69";
when "01" & x"d76" => data <= x"ff";
when "01" & x"d77" => data <= x"a5";
when "01" & x"d78" => data <= x"c2";
when "01" & x"d79" => data <= x"69";
when "01" & x"d7a" => data <= x"00";
when "01" & x"d7b" => data <= x"85";
when "01" & x"d7c" => data <= x"c6";
when "01" & x"d7d" => data <= x"a5";
when "01" & x"d7e" => data <= x"c5";
when "01" & x"d7f" => data <= x"69";
when "01" & x"d80" => data <= x"00";
when "01" & x"d81" => data <= x"85";
when "01" & x"d82" => data <= x"c7";
when "01" & x"d83" => data <= x"ad";
when "01" & x"d84" => data <= x"4e";
when "01" & x"d85" => data <= x"10";
when "01" & x"d86" => data <= x"85";
when "01" & x"d87" => data <= x"c8";
when "01" & x"d88" => data <= x"ad";
when "01" & x"d89" => data <= x"4d";
when "01" & x"d8a" => data <= x"10";
when "01" & x"d8b" => data <= x"29";
when "01" & x"d8c" => data <= x"03";
when "01" & x"d8d" => data <= x"85";
when "01" & x"d8e" => data <= x"c9";
when "01" & x"d8f" => data <= x"a9";
when "01" & x"d90" => data <= x"ff";
when "01" & x"d91" => data <= x"85";
when "01" & x"d92" => data <= x"a8";
when "01" & x"d93" => data <= x"20";
when "01" & x"d94" => data <= x"06";
when "01" & x"d95" => data <= x"9e";
when "01" & x"d96" => data <= x"20";
when "01" & x"d97" => data <= x"38";
when "01" & x"d98" => data <= x"9c";
when "01" & x"d99" => data <= x"ad";
when "01" & x"d9a" => data <= x"d2";
when "01" & x"d9b" => data <= x"10";
when "01" & x"d9c" => data <= x"20";
when "01" & x"d9d" => data <= x"7e";
when "01" & x"d9e" => data <= x"87";
when "01" & x"d9f" => data <= x"20";
when "01" & x"da0" => data <= x"47";
when "01" & x"da1" => data <= x"83";
when "01" & x"da2" => data <= x"a2";
when "01" & x"da3" => data <= x"07";
when "01" & x"da4" => data <= x"bd";
when "01" & x"da5" => data <= x"58";
when "01" & x"da6" => data <= x"10";
when "01" & x"da7" => data <= x"95";
when "01" & x"da8" => data <= x"c7";
when "01" & x"da9" => data <= x"ca";
when "01" & x"daa" => data <= x"10";
when "01" & x"dab" => data <= x"f8";
when "01" & x"dac" => data <= x"a4";
when "01" & x"dad" => data <= x"ab";
when "01" & x"dae" => data <= x"8c";
when "01" & x"daf" => data <= x"ce";
when "01" & x"db0" => data <= x"10";
when "01" & x"db1" => data <= x"20";
when "01" & x"db2" => data <= x"9d";
when "01" & x"db3" => data <= x"82";
when "01" & x"db4" => data <= x"b0";
when "01" & x"db5" => data <= x"93";
when "01" & x"db6" => data <= x"60";
when "01" & x"db7" => data <= x"20";
when "01" & x"db8" => data <= x"f5";
when "01" & x"db9" => data <= x"9d";
when "01" & x"dba" => data <= x"20";
when "01" & x"dbb" => data <= x"43";
when "01" & x"dbc" => data <= x"9c";
when "01" & x"dbd" => data <= x"ad";
when "01" & x"dbe" => data <= x"d3";
when "01" & x"dbf" => data <= x"10";
when "01" & x"dc0" => data <= x"85";
when "01" & x"dc1" => data <= x"cf";
when "01" & x"dc2" => data <= x"a5";
when "01" & x"dc3" => data <= x"ce";
when "01" & x"dc4" => data <= x"48";
when "01" & x"dc5" => data <= x"20";
when "01" & x"dc6" => data <= x"47";
when "01" & x"dc7" => data <= x"83";
when "01" & x"dc8" => data <= x"20";
when "01" & x"dc9" => data <= x"96";
when "01" & x"dca" => data <= x"82";
when "01" & x"dcb" => data <= x"90";
when "01" & x"dcc" => data <= x"03";
when "01" & x"dcd" => data <= x"20";
when "01" & x"dce" => data <= x"d1";
when "01" & x"dcf" => data <= x"82";
when "01" & x"dd0" => data <= x"68";
when "01" & x"dd1" => data <= x"85";
when "01" & x"dd2" => data <= x"ce";
when "01" & x"dd3" => data <= x"20";
when "01" & x"dd4" => data <= x"3f";
when "01" & x"dd5" => data <= x"8a";
when "01" & x"dd6" => data <= x"20";
when "01" & x"dd7" => data <= x"56";
when "01" & x"dd8" => data <= x"8a";
when "01" & x"dd9" => data <= x"a5";
when "01" & x"dda" => data <= x"c4";
when "01" & x"ddb" => data <= x"20";
when "01" & x"ddc" => data <= x"fd";
when "01" & x"ddd" => data <= x"81";
when "01" & x"dde" => data <= x"85";
when "01" & x"ddf" => data <= x"c6";
when "01" & x"de0" => data <= x"20";
when "01" & x"de1" => data <= x"9d";
when "01" & x"de2" => data <= x"89";
when "01" & x"de3" => data <= x"a5";
when "01" & x"de4" => data <= x"c4";
when "01" & x"de5" => data <= x"29";
when "01" & x"de6" => data <= x"03";
when "01" & x"de7" => data <= x"48";
when "01" & x"de8" => data <= x"a5";
when "01" & x"de9" => data <= x"c5";
when "01" & x"dea" => data <= x"48";
when "01" & x"deb" => data <= x"20";
when "01" & x"dec" => data <= x"f5";
when "01" & x"ded" => data <= x"9d";
when "01" & x"dee" => data <= x"68";
when "01" & x"def" => data <= x"85";
when "01" & x"df0" => data <= x"ca";
when "01" & x"df1" => data <= x"68";
when "01" & x"df2" => data <= x"85";
when "01" & x"df3" => data <= x"cb";
when "01" & x"df4" => data <= x"60";
when "01" & x"df5" => data <= x"a2";
when "01" & x"df6" => data <= x"11";
when "01" & x"df7" => data <= x"bd";
when "01" & x"df8" => data <= x"45";
when "01" & x"df9" => data <= x"10";
when "01" & x"dfa" => data <= x"b4";
when "01" & x"dfb" => data <= x"bc";
when "01" & x"dfc" => data <= x"95";
when "01" & x"dfd" => data <= x"bc";
when "01" & x"dfe" => data <= x"98";
when "01" & x"dff" => data <= x"9d";
when "01" & x"e00" => data <= x"45";
when "01" & x"e01" => data <= x"10";
when "01" & x"e02" => data <= x"ca";
when "01" & x"e03" => data <= x"10";
when "01" & x"e04" => data <= x"f2";
when "01" & x"e05" => data <= x"60";
when "01" & x"e06" => data <= x"20";
when "01" & x"e07" => data <= x"8d";
when "01" & x"e08" => data <= x"a0";
when "01" & x"e09" => data <= x"a9";
when "01" & x"e0a" => data <= x"00";
when "01" & x"e0b" => data <= x"85";
when "01" & x"e0c" => data <= x"be";
when "01" & x"e0d" => data <= x"85";
when "01" & x"e0e" => data <= x"c2";
when "01" & x"e0f" => data <= x"a5";
when "01" & x"e10" => data <= x"c6";
when "01" & x"e11" => data <= x"a8";
when "01" & x"e12" => data <= x"cd";
when "01" & x"e13" => data <= x"d1";
when "01" & x"e14" => data <= x"10";
when "01" & x"e15" => data <= x"a5";
when "01" & x"e16" => data <= x"c7";
when "01" & x"e17" => data <= x"e9";
when "01" & x"e18" => data <= x"00";
when "01" & x"e19" => data <= x"90";
when "01" & x"e1a" => data <= x"03";
when "01" & x"e1b" => data <= x"ac";
when "01" & x"e1c" => data <= x"d1";
when "01" & x"e1d" => data <= x"10";
when "01" & x"e1e" => data <= x"84";
when "01" & x"e1f" => data <= x"c3";
when "01" & x"e20" => data <= x"a5";
when "01" & x"e21" => data <= x"c8";
when "01" & x"e22" => data <= x"85";
when "01" & x"e23" => data <= x"c5";
when "01" & x"e24" => data <= x"a5";
when "01" & x"e25" => data <= x"c9";
when "01" & x"e26" => data <= x"85";
when "01" & x"e27" => data <= x"c4";
when "01" & x"e28" => data <= x"ad";
when "01" & x"e29" => data <= x"d0";
when "01" & x"e2a" => data <= x"10";
when "01" & x"e2b" => data <= x"85";
when "01" & x"e2c" => data <= x"bf";
when "01" & x"e2d" => data <= x"ad";
when "01" & x"e2e" => data <= x"d2";
when "01" & x"e2f" => data <= x"10";
when "01" & x"e30" => data <= x"85";
when "01" & x"e31" => data <= x"cf";
when "01" & x"e32" => data <= x"20";
when "01" & x"e33" => data <= x"38";
when "01" & x"e34" => data <= x"9c";
when "01" & x"e35" => data <= x"20";
when "01" & x"e36" => data <= x"3e";
when "01" & x"e37" => data <= x"be";
when "01" & x"e38" => data <= x"20";
when "01" & x"e39" => data <= x"c6";
when "01" & x"e3a" => data <= x"87";
when "01" & x"e3b" => data <= x"ad";
when "01" & x"e3c" => data <= x"d3";
when "01" & x"e3d" => data <= x"10";
when "01" & x"e3e" => data <= x"85";
when "01" & x"e3f" => data <= x"cf";
when "01" & x"e40" => data <= x"24";
when "01" & x"e41" => data <= x"a8";
when "01" & x"e42" => data <= x"10";
when "01" & x"e43" => data <= x"07";
when "01" & x"e44" => data <= x"20";
when "01" & x"e45" => data <= x"b7";
when "01" & x"e46" => data <= x"9d";
when "01" & x"e47" => data <= x"a9";
when "01" & x"e48" => data <= x"00";
when "01" & x"e49" => data <= x"85";
when "01" & x"e4a" => data <= x"a8";
when "01" & x"e4b" => data <= x"a5";
when "01" & x"e4c" => data <= x"ca";
when "01" & x"e4d" => data <= x"85";
when "01" & x"e4e" => data <= x"c5";
when "01" & x"e4f" => data <= x"a5";
when "01" & x"e50" => data <= x"cb";
when "01" & x"e51" => data <= x"85";
when "01" & x"e52" => data <= x"c4";
when "01" & x"e53" => data <= x"ad";
when "01" & x"e54" => data <= x"d0";
when "01" & x"e55" => data <= x"10";
when "01" & x"e56" => data <= x"85";
when "01" & x"e57" => data <= x"bf";
when "01" & x"e58" => data <= x"20";
when "01" & x"e59" => data <= x"43";
when "01" & x"e5a" => data <= x"9c";
when "01" & x"e5b" => data <= x"20";
when "01" & x"e5c" => data <= x"3e";
when "01" & x"e5d" => data <= x"be";
when "01" & x"e5e" => data <= x"20";
when "01" & x"e5f" => data <= x"8f";
when "01" & x"e60" => data <= x"87";
when "01" & x"e61" => data <= x"a5";
when "01" & x"e62" => data <= x"c3";
when "01" & x"e63" => data <= x"18";
when "01" & x"e64" => data <= x"65";
when "01" & x"e65" => data <= x"ca";
when "01" & x"e66" => data <= x"85";
when "01" & x"e67" => data <= x"ca";
when "01" & x"e68" => data <= x"90";
when "01" & x"e69" => data <= x"02";
when "01" & x"e6a" => data <= x"e6";
when "01" & x"e6b" => data <= x"cb";
when "01" & x"e6c" => data <= x"a5";
when "01" & x"e6d" => data <= x"c3";
when "01" & x"e6e" => data <= x"18";
when "01" & x"e6f" => data <= x"65";
when "01" & x"e70" => data <= x"c8";
when "01" & x"e71" => data <= x"85";
when "01" & x"e72" => data <= x"c8";
when "01" & x"e73" => data <= x"90";
when "01" & x"e74" => data <= x"02";
when "01" & x"e75" => data <= x"e6";
when "01" & x"e76" => data <= x"c9";
when "01" & x"e77" => data <= x"38";
when "01" & x"e78" => data <= x"a5";
when "01" & x"e79" => data <= x"c6";
when "01" & x"e7a" => data <= x"e5";
when "01" & x"e7b" => data <= x"c3";
when "01" & x"e7c" => data <= x"85";
when "01" & x"e7d" => data <= x"c6";
when "01" & x"e7e" => data <= x"b0";
when "01" & x"e7f" => data <= x"02";
when "01" & x"e80" => data <= x"c6";
when "01" & x"e81" => data <= x"c7";
when "01" & x"e82" => data <= x"05";
when "01" & x"e83" => data <= x"c7";
when "01" & x"e84" => data <= x"d0";
when "01" & x"e85" => data <= x"89";
when "01" & x"e86" => data <= x"60";
when "01" & x"e87" => data <= x"20";
when "01" & x"e88" => data <= x"d7";
when "01" & x"e89" => data <= x"9f";
when "01" & x"e8a" => data <= x"a9";
when "01" & x"e8b" => data <= x"00";
when "01" & x"e8c" => data <= x"f0";
when "01" & x"e8d" => data <= x"05";
when "01" & x"e8e" => data <= x"20";
when "01" & x"e8f" => data <= x"d7";
when "01" & x"e90" => data <= x"9f";
when "01" & x"e91" => data <= x"a9";
when "01" & x"e92" => data <= x"ff";
when "01" & x"e93" => data <= x"85";
when "01" & x"e94" => data <= x"ab";
when "01" & x"e95" => data <= x"a9";
when "01" & x"e96" => data <= x"c0";
when "01" & x"e97" => data <= x"20";
when "01" & x"e98" => data <= x"ce";
when "01" & x"e99" => data <= x"ff";
when "01" & x"e9a" => data <= x"a8";
when "01" & x"e9b" => data <= x"a9";
when "01" & x"e9c" => data <= x"0d";
when "01" & x"e9d" => data <= x"c0";
when "01" & x"e9e" => data <= x"00";
when "01" & x"e9f" => data <= x"d0";
when "01" & x"ea0" => data <= x"1e";
when "01" & x"ea1" => data <= x"4c";
when "01" & x"ea2" => data <= x"76";
when "01" & x"ea3" => data <= x"82";
when "01" & x"ea4" => data <= x"20";
when "01" & x"ea5" => data <= x"d7";
when "01" & x"ea6" => data <= x"ff";
when "01" & x"ea7" => data <= x"b0";
when "01" & x"ea8" => data <= x"1e";
when "01" & x"ea9" => data <= x"c9";
when "01" & x"eaa" => data <= x"0a";
when "01" & x"eab" => data <= x"f0";
when "01" & x"eac" => data <= x"f7";
when "01" & x"ead" => data <= x"28";
when "01" & x"eae" => data <= x"d0";
when "01" & x"eaf" => data <= x"08";
when "01" & x"eb0" => data <= x"48";
when "01" & x"eb1" => data <= x"20";
when "01" & x"eb2" => data <= x"a2";
when "01" & x"eb3" => data <= x"9f";
when "01" & x"eb4" => data <= x"20";
when "01" & x"eb5" => data <= x"ce";
when "01" & x"eb6" => data <= x"9f";
when "01" & x"eb7" => data <= x"68";
when "01" & x"eb8" => data <= x"20";
when "01" & x"eb9" => data <= x"e3";
when "01" & x"eba" => data <= x"ff";
when "01" & x"ebb" => data <= x"24";
when "01" & x"ebc" => data <= x"ff";
when "01" & x"ebd" => data <= x"30";
when "01" & x"ebe" => data <= x"09";
when "01" & x"ebf" => data <= x"25";
when "01" & x"ec0" => data <= x"ab";
when "01" & x"ec1" => data <= x"c9";
when "01" & x"ec2" => data <= x"0d";
when "01" & x"ec3" => data <= x"08";
when "01" & x"ec4" => data <= x"4c";
when "01" & x"ec5" => data <= x"a4";
when "01" & x"ec6" => data <= x"9e";
when "01" & x"ec7" => data <= x"28";
when "01" & x"ec8" => data <= x"20";
when "01" & x"ec9" => data <= x"9a";
when "01" & x"eca" => data <= x"9f";
when "01" & x"ecb" => data <= x"a9";
when "01" & x"ecc" => data <= x"00";
when "01" & x"ecd" => data <= x"4c";
when "01" & x"ece" => data <= x"ce";
when "01" & x"ecf" => data <= x"ff";
when "01" & x"ed0" => data <= x"20";
when "01" & x"ed1" => data <= x"d7";
when "01" & x"ed2" => data <= x"9f";
when "01" & x"ed3" => data <= x"a9";
when "01" & x"ed4" => data <= x"c0";
when "01" & x"ed5" => data <= x"20";
when "01" & x"ed6" => data <= x"ce";
when "01" & x"ed7" => data <= x"ff";
when "01" & x"ed8" => data <= x"a8";
when "01" & x"ed9" => data <= x"f0";
when "01" & x"eda" => data <= x"c6";
when "01" & x"edb" => data <= x"a6";
when "01" & x"edc" => data <= x"f4";
when "01" & x"edd" => data <= x"bd";
when "01" & x"ede" => data <= x"f0";
when "01" & x"edf" => data <= x"0d";
when "01" & x"ee0" => data <= x"85";
when "01" & x"ee1" => data <= x"ad";
when "01" & x"ee2" => data <= x"e6";
when "01" & x"ee3" => data <= x"ad";
when "01" & x"ee4" => data <= x"24";
when "01" & x"ee5" => data <= x"ff";
when "01" & x"ee6" => data <= x"30";
when "01" & x"ee7" => data <= x"e3";
when "01" & x"ee8" => data <= x"a5";
when "01" & x"ee9" => data <= x"a9";
when "01" & x"eea" => data <= x"20";
when "01" & x"eeb" => data <= x"c2";
when "01" & x"eec" => data <= x"80";
when "01" & x"eed" => data <= x"a5";
when "01" & x"eee" => data <= x"a8";
when "01" & x"eef" => data <= x"20";
when "01" & x"ef0" => data <= x"c2";
when "01" & x"ef1" => data <= x"80";
when "01" & x"ef2" => data <= x"20";
when "01" & x"ef3" => data <= x"ce";
when "01" & x"ef4" => data <= x"9f";
when "01" & x"ef5" => data <= x"a9";
when "01" & x"ef6" => data <= x"07";
when "01" & x"ef7" => data <= x"85";
when "01" & x"ef8" => data <= x"ac";
when "01" & x"ef9" => data <= x"a2";
when "01" & x"efa" => data <= x"00";
when "01" & x"efb" => data <= x"20";
when "01" & x"efc" => data <= x"d7";
when "01" & x"efd" => data <= x"ff";
when "01" & x"efe" => data <= x"b0";
when "01" & x"eff" => data <= x"0d";
when "01" & x"f00" => data <= x"81";
when "01" & x"f01" => data <= x"ac";
when "01" & x"f02" => data <= x"20";
when "01" & x"f03" => data <= x"c2";
when "01" & x"f04" => data <= x"80";
when "01" & x"f05" => data <= x"20";
when "01" & x"f06" => data <= x"ce";
when "01" & x"f07" => data <= x"9f";
when "01" & x"f08" => data <= x"c6";
when "01" & x"f09" => data <= x"ac";
when "01" & x"f0a" => data <= x"10";
when "01" & x"f0b" => data <= x"ef";
when "01" & x"f0c" => data <= x"18";
when "01" & x"f0d" => data <= x"08";
when "01" & x"f0e" => data <= x"90";
when "01" & x"f0f" => data <= x"0e";
when "01" & x"f10" => data <= x"20";
when "01" & x"f11" => data <= x"65";
when "01" & x"f12" => data <= x"80";
when "01" & x"f13" => data <= x"2a";
when "01" & x"f14" => data <= x"2a";
when "01" & x"f15" => data <= x"20";
when "01" & x"f16" => data <= x"a9";
when "01" & x"f17" => data <= x"00";
when "01" & x"f18" => data <= x"81";
when "01" & x"f19" => data <= x"ac";
when "01" & x"f1a" => data <= x"c6";
when "01" & x"f1b" => data <= x"ac";
when "01" & x"f1c" => data <= x"10";
when "01" & x"f1d" => data <= x"f2";
when "01" & x"f1e" => data <= x"a9";
when "01" & x"f1f" => data <= x"07";
when "01" & x"f20" => data <= x"85";
when "01" & x"f21" => data <= x"ac";
when "01" & x"f22" => data <= x"a1";
when "01" & x"f23" => data <= x"ac";
when "01" & x"f24" => data <= x"c9";
when "01" & x"f25" => data <= x"7f";
when "01" & x"f26" => data <= x"b0";
when "01" & x"f27" => data <= x"04";
when "01" & x"f28" => data <= x"c9";
when "01" & x"f29" => data <= x"20";
when "01" & x"f2a" => data <= x"b0";
when "01" & x"f2b" => data <= x"02";
when "01" & x"f2c" => data <= x"a9";
when "01" & x"f2d" => data <= x"2e";
when "01" & x"f2e" => data <= x"20";
when "01" & x"f2f" => data <= x"e3";
when "01" & x"f30" => data <= x"ff";
when "01" & x"f31" => data <= x"c6";
when "01" & x"f32" => data <= x"ac";
when "01" & x"f33" => data <= x"10";
when "01" & x"f34" => data <= x"ed";
when "01" & x"f35" => data <= x"20";
when "01" & x"f36" => data <= x"9a";
when "01" & x"f37" => data <= x"9f";
when "01" & x"f38" => data <= x"a9";
when "01" & x"f39" => data <= x"08";
when "01" & x"f3a" => data <= x"18";
when "01" & x"f3b" => data <= x"65";
when "01" & x"f3c" => data <= x"a8";
when "01" & x"f3d" => data <= x"85";
when "01" & x"f3e" => data <= x"a8";
when "01" & x"f3f" => data <= x"90";
when "01" & x"f40" => data <= x"02";
when "01" & x"f41" => data <= x"e6";
when "01" & x"f42" => data <= x"a9";
when "01" & x"f43" => data <= x"28";
when "01" & x"f44" => data <= x"90";
when "01" & x"f45" => data <= x"9e";
when "01" & x"f46" => data <= x"b0";
when "01" & x"f47" => data <= x"83";
when "01" & x"f48" => data <= x"20";
when "01" & x"f49" => data <= x"d7";
when "01" & x"f4a" => data <= x"9f";
when "01" & x"f4b" => data <= x"a9";
when "01" & x"f4c" => data <= x"80";
when "01" & x"f4d" => data <= x"20";
when "01" & x"f4e" => data <= x"ce";
when "01" & x"f4f" => data <= x"ff";
when "01" & x"f50" => data <= x"85";
when "01" & x"f51" => data <= x"ab";
when "01" & x"f52" => data <= x"20";
when "01" & x"f53" => data <= x"a2";
when "01" & x"f54" => data <= x"9f";
when "01" & x"f55" => data <= x"20";
when "01" & x"f56" => data <= x"ce";
when "01" & x"f57" => data <= x"9f";
when "01" & x"f58" => data <= x"a6";
when "01" & x"f59" => data <= x"f4";
when "01" & x"f5a" => data <= x"bc";
when "01" & x"f5b" => data <= x"f0";
when "01" & x"f5c" => data <= x"0d";
when "01" & x"f5d" => data <= x"c8";
when "01" & x"f5e" => data <= x"84";
when "01" & x"f5f" => data <= x"ad";
when "01" & x"f60" => data <= x"a2";
when "01" & x"f61" => data <= x"ac";
when "01" & x"f62" => data <= x"a0";
when "01" & x"f63" => data <= x"ff";
when "01" & x"f64" => data <= x"84";
when "01" & x"f65" => data <= x"ae";
when "01" & x"f66" => data <= x"84";
when "01" & x"f67" => data <= x"b0";
when "01" & x"f68" => data <= x"c8";
when "01" & x"f69" => data <= x"84";
when "01" & x"f6a" => data <= x"ac";
when "01" & x"f6b" => data <= x"84";
when "01" & x"f6c" => data <= x"af";
when "01" & x"f6d" => data <= x"98";
when "01" & x"f6e" => data <= x"20";
when "01" & x"f6f" => data <= x"f1";
when "01" & x"f70" => data <= x"ff";
when "01" & x"f71" => data <= x"08";
when "01" & x"f72" => data <= x"84";
when "01" & x"f73" => data <= x"aa";
when "01" & x"f74" => data <= x"a4";
when "01" & x"f75" => data <= x"ab";
when "01" & x"f76" => data <= x"a2";
when "01" & x"f77" => data <= x"00";
when "01" & x"f78" => data <= x"f0";
when "01" & x"f79" => data <= x"07";
when "01" & x"f7a" => data <= x"a1";
when "01" & x"f7b" => data <= x"ac";
when "01" & x"f7c" => data <= x"20";
when "01" & x"f7d" => data <= x"d4";
when "01" & x"f7e" => data <= x"ff";
when "01" & x"f7f" => data <= x"e6";
when "01" & x"f80" => data <= x"ac";
when "01" & x"f81" => data <= x"a5";
when "01" & x"f82" => data <= x"ac";
when "01" & x"f83" => data <= x"c5";
when "01" & x"f84" => data <= x"aa";
when "01" & x"f85" => data <= x"d0";
when "01" & x"f86" => data <= x"f3";
when "01" & x"f87" => data <= x"28";
when "01" & x"f88" => data <= x"b0";
when "01" & x"f89" => data <= x"08";
when "01" & x"f8a" => data <= x"a9";
when "01" & x"f8b" => data <= x"0d";
when "01" & x"f8c" => data <= x"20";
when "01" & x"f8d" => data <= x"d4";
when "01" & x"f8e" => data <= x"ff";
when "01" & x"f8f" => data <= x"4c";
when "01" & x"f90" => data <= x"52";
when "01" & x"f91" => data <= x"9f";
when "01" & x"f92" => data <= x"a9";
when "01" & x"f93" => data <= x"7e";
when "01" & x"f94" => data <= x"20";
when "01" & x"f95" => data <= x"f4";
when "01" & x"f96" => data <= x"ff";
when "01" & x"f97" => data <= x"20";
when "01" & x"f98" => data <= x"cb";
when "01" & x"f99" => data <= x"9e";
when "01" & x"f9a" => data <= x"48";
when "01" & x"f9b" => data <= x"a9";
when "01" & x"f9c" => data <= x"0d";
when "01" & x"f9d" => data <= x"20";
when "01" & x"f9e" => data <= x"9c";
when "01" & x"f9f" => data <= x"80";
when "01" & x"fa0" => data <= x"68";
when "01" & x"fa1" => data <= x"60";
when "01" & x"fa2" => data <= x"f8";
when "01" & x"fa3" => data <= x"18";
when "01" & x"fa4" => data <= x"a5";
when "01" & x"fa5" => data <= x"a8";
when "01" & x"fa6" => data <= x"69";
when "01" & x"fa7" => data <= x"01";
when "01" & x"fa8" => data <= x"85";
when "01" & x"fa9" => data <= x"a8";
when "01" & x"faa" => data <= x"a5";
when "01" & x"fab" => data <= x"a9";
when "01" & x"fac" => data <= x"69";
when "01" & x"fad" => data <= x"00";
when "01" & x"fae" => data <= x"85";
when "01" & x"faf" => data <= x"a9";
when "01" & x"fb0" => data <= x"d8";
when "01" & x"fb1" => data <= x"18";
when "01" & x"fb2" => data <= x"20";
when "01" & x"fb3" => data <= x"b7";
when "01" & x"fb4" => data <= x"9f";
when "01" & x"fb5" => data <= x"a5";
when "01" & x"fb6" => data <= x"a8";
when "01" & x"fb7" => data <= x"48";
when "01" & x"fb8" => data <= x"08";
when "01" & x"fb9" => data <= x"20";
when "01" & x"fba" => data <= x"05";
when "01" & x"fbb" => data <= x"82";
when "01" & x"fbc" => data <= x"28";
when "01" & x"fbd" => data <= x"20";
when "01" & x"fbe" => data <= x"c1";
when "01" & x"fbf" => data <= x"9f";
when "01" & x"fc0" => data <= x"68";
when "01" & x"fc1" => data <= x"aa";
when "01" & x"fc2" => data <= x"b0";
when "01" & x"fc3" => data <= x"02";
when "01" & x"fc4" => data <= x"f0";
when "01" & x"fc5" => data <= x"08";
when "01" & x"fc6" => data <= x"20";
when "01" & x"fc7" => data <= x"ca";
when "01" & x"fc8" => data <= x"80";
when "01" & x"fc9" => data <= x"38";
when "01" & x"fca" => data <= x"60";
when "01" & x"fcb" => data <= x"20";
when "01" & x"fcc" => data <= x"ce";
when "01" & x"fcd" => data <= x"9f";
when "01" & x"fce" => data <= x"48";
when "01" & x"fcf" => data <= x"a9";
when "01" & x"fd0" => data <= x"20";
when "01" & x"fd1" => data <= x"20";
when "01" & x"fd2" => data <= x"9c";
when "01" & x"fd3" => data <= x"80";
when "01" & x"fd4" => data <= x"68";
when "01" & x"fd5" => data <= x"18";
when "01" & x"fd6" => data <= x"60";
when "01" & x"fd7" => data <= x"ba";
when "01" & x"fd8" => data <= x"a9";
when "01" & x"fd9" => data <= x"00";
when "01" & x"fda" => data <= x"9d";
when "01" & x"fdb" => data <= x"07";
when "01" & x"fdc" => data <= x"01";
when "01" & x"fdd" => data <= x"88";
when "01" & x"fde" => data <= x"c8";
when "01" & x"fdf" => data <= x"b1";
when "01" & x"fe0" => data <= x"f2";
when "01" & x"fe1" => data <= x"c9";
when "01" & x"fe2" => data <= x"20";
when "01" & x"fe3" => data <= x"f0";
when "01" & x"fe4" => data <= x"f9";
when "01" & x"fe5" => data <= x"c9";
when "01" & x"fe6" => data <= x"0d";
when "01" & x"fe7" => data <= x"d0";
when "01" & x"fe8" => data <= x"03";
when "01" & x"fe9" => data <= x"4c";
when "01" & x"fea" => data <= x"06";
when "01" & x"feb" => data <= x"9a";
when "01" & x"fec" => data <= x"a9";
when "01" & x"fed" => data <= x"00";
when "01" & x"fee" => data <= x"85";
when "01" & x"fef" => data <= x"a8";
when "01" & x"ff0" => data <= x"85";
when "01" & x"ff1" => data <= x"a9";
when "01" & x"ff2" => data <= x"48";
when "01" & x"ff3" => data <= x"98";
when "01" & x"ff4" => data <= x"18";
when "01" & x"ff5" => data <= x"65";
when "01" & x"ff6" => data <= x"f2";
when "01" & x"ff7" => data <= x"aa";
when "01" & x"ff8" => data <= x"a5";
when "01" & x"ff9" => data <= x"f3";
when "01" & x"ffa" => data <= x"69";
when "01" & x"ffb" => data <= x"00";
when "01" & x"ffc" => data <= x"a8";
when "01" & x"ffd" => data <= x"68";
when "01" & x"ffe" => data <= x"60";
when "01" & x"fff" => data <= x"6d";
when "10" & x"000" => data <= x"20";
when "10" & x"001" => data <= x"80";
when "10" & x"002" => data <= x"a1";
when "10" & x"003" => data <= x"68";
when "10" & x"004" => data <= x"85";
when "10" & x"005" => data <= x"b8";
when "10" & x"006" => data <= x"68";
when "10" & x"007" => data <= x"85";
when "10" & x"008" => data <= x"b9";
when "10" & x"009" => data <= x"20";
when "10" & x"00a" => data <= x"0f";
when "10" & x"00b" => data <= x"a0";
when "10" & x"00c" => data <= x"4c";
when "10" & x"00d" => data <= x"00";
when "10" & x"00e" => data <= x"01";
when "10" & x"00f" => data <= x"a0";
when "10" & x"010" => data <= x"00";
when "10" & x"011" => data <= x"8c";
when "10" & x"012" => data <= x"00";
when "10" & x"013" => data <= x"01";
when "10" & x"014" => data <= x"c8";
when "10" & x"015" => data <= x"f0";
when "10" & x"016" => data <= x"07";
when "10" & x"017" => data <= x"b1";
when "10" & x"018" => data <= x"b8";
when "10" & x"019" => data <= x"99";
when "10" & x"01a" => data <= x"00";
when "10" & x"01b" => data <= x"01";
when "10" & x"01c" => data <= x"d0";
when "10" & x"01d" => data <= x"f6";
when "10" & x"01e" => data <= x"60";
when "10" & x"01f" => data <= x"a2";
when "10" & x"020" => data <= x"ff";
when "10" & x"021" => data <= x"d0";
when "10" & x"022" => data <= x"02";
when "10" & x"023" => data <= x"a2";
when "10" & x"024" => data <= x"00";
when "10" & x"025" => data <= x"a0";
when "10" & x"026" => data <= x"ff";
when "10" & x"027" => data <= x"8c";
when "10" & x"028" => data <= x"82";
when "10" & x"029" => data <= x"10";
when "10" & x"02a" => data <= x"85";
when "10" & x"02b" => data <= x"b0";
when "10" & x"02c" => data <= x"86";
when "10" & x"02d" => data <= x"b1";
when "10" & x"02e" => data <= x"8d";
when "10" & x"02f" => data <= x"02";
when "10" & x"030" => data <= x"0d";
when "10" & x"031" => data <= x"20";
when "10" & x"032" => data <= x"80";
when "10" & x"033" => data <= x"a1";
when "10" & x"034" => data <= x"68";
when "10" & x"035" => data <= x"85";
when "10" & x"036" => data <= x"b8";
when "10" & x"037" => data <= x"68";
when "10" & x"038" => data <= x"85";
when "10" & x"039" => data <= x"b9";
when "10" & x"03a" => data <= x"20";
when "10" & x"03b" => data <= x"0f";
when "10" & x"03c" => data <= x"a0";
when "10" & x"03d" => data <= x"a5";
when "10" & x"03e" => data <= x"b0";
when "10" & x"03f" => data <= x"20";
when "10" & x"040" => data <= x"69";
when "10" & x"041" => data <= x"a0";
when "10" & x"042" => data <= x"a5";
when "10" & x"043" => data <= x"b1";
when "10" & x"044" => data <= x"f0";
when "10" & x"045" => data <= x"1b";
when "10" & x"046" => data <= x"a9";
when "10" & x"047" => data <= x"2f";
when "10" & x"048" => data <= x"99";
when "10" & x"049" => data <= x"00";
when "10" & x"04a" => data <= x"01";
when "10" & x"04b" => data <= x"c8";
when "10" & x"04c" => data <= x"ae";
when "10" & x"04d" => data <= x"41";
when "10" & x"04e" => data <= x"0d";
when "10" & x"04f" => data <= x"bd";
when "10" & x"050" => data <= x"44";
when "10" & x"051" => data <= x"0d";
when "10" & x"052" => data <= x"20";
when "10" & x"053" => data <= x"69";
when "10" & x"054" => data <= x"a0";
when "10" & x"055" => data <= x"bd";
when "10" & x"056" => data <= x"45";
when "10" & x"057" => data <= x"0d";
when "10" & x"058" => data <= x"20";
when "10" & x"059" => data <= x"69";
when "10" & x"05a" => data <= x"a0";
when "10" & x"05b" => data <= x"bd";
when "10" & x"05c" => data <= x"46";
when "10" & x"05d" => data <= x"0d";
when "10" & x"05e" => data <= x"20";
when "10" & x"05f" => data <= x"69";
when "10" & x"060" => data <= x"a0";
when "10" & x"061" => data <= x"a9";
when "10" & x"062" => data <= x"00";
when "10" & x"063" => data <= x"99";
when "10" & x"064" => data <= x"00";
when "10" & x"065" => data <= x"01";
when "10" & x"066" => data <= x"4c";
when "10" & x"067" => data <= x"00";
when "10" & x"068" => data <= x"01";
when "10" & x"069" => data <= x"48";
when "10" & x"06a" => data <= x"4a";
when "10" & x"06b" => data <= x"4a";
when "10" & x"06c" => data <= x"4a";
when "10" & x"06d" => data <= x"4a";
when "10" & x"06e" => data <= x"20";
when "10" & x"06f" => data <= x"74";
when "10" & x"070" => data <= x"a0";
when "10" & x"071" => data <= x"68";
when "10" & x"072" => data <= x"29";
when "10" & x"073" => data <= x"0f";
when "10" & x"074" => data <= x"18";
when "10" & x"075" => data <= x"69";
when "10" & x"076" => data <= x"30";
when "10" & x"077" => data <= x"c9";
when "10" & x"078" => data <= x"3a";
when "10" & x"079" => data <= x"90";
when "10" & x"07a" => data <= x"02";
when "10" & x"07b" => data <= x"69";
when "10" & x"07c" => data <= x"06";
when "10" & x"07d" => data <= x"99";
when "10" & x"07e" => data <= x"00";
when "10" & x"07f" => data <= x"01";
when "10" & x"080" => data <= x"c8";
when "10" & x"081" => data <= x"60";
when "10" & x"082" => data <= x"20";
when "10" & x"083" => data <= x"00";
when "10" & x"084" => data <= x"a0";
when "10" & x"085" => data <= x"11";
when "10" & x"086" => data <= x"45";
when "10" & x"087" => data <= x"73";
when "10" & x"088" => data <= x"63";
when "10" & x"089" => data <= x"61";
when "10" & x"08a" => data <= x"70";
when "10" & x"08b" => data <= x"65";
when "10" & x"08c" => data <= x"00";
when "10" & x"08d" => data <= x"48";
when "10" & x"08e" => data <= x"a9";
when "10" & x"08f" => data <= x"ff";
when "10" & x"090" => data <= x"8d";
when "10" & x"091" => data <= x"74";
when "10" & x"092" => data <= x"10";
when "10" & x"093" => data <= x"8d";
when "10" & x"094" => data <= x"75";
when "10" & x"095" => data <= x"10";
when "10" & x"096" => data <= x"68";
when "10" & x"097" => data <= x"60";
when "10" & x"098" => data <= x"48";
when "10" & x"099" => data <= x"a5";
when "10" & x"09a" => data <= x"be";
when "10" & x"09b" => data <= x"8d";
when "10" & x"09c" => data <= x"72";
when "10" & x"09d" => data <= x"10";
when "10" & x"09e" => data <= x"a5";
when "10" & x"09f" => data <= x"bf";
when "10" & x"0a0" => data <= x"8d";
when "10" & x"0a1" => data <= x"73";
when "10" & x"0a2" => data <= x"10";
when "10" & x"0a3" => data <= x"ad";
when "10" & x"0a4" => data <= x"74";
when "10" & x"0a5" => data <= x"10";
when "10" & x"0a6" => data <= x"2d";
when "10" & x"0a7" => data <= x"75";
when "10" & x"0a8" => data <= x"10";
when "10" & x"0a9" => data <= x"0d";
when "10" & x"0aa" => data <= x"d7";
when "10" & x"0ab" => data <= x"10";
when "10" & x"0ac" => data <= x"49";
when "10" & x"0ad" => data <= x"ff";
when "10" & x"0ae" => data <= x"8d";
when "10" & x"0af" => data <= x"d6";
when "10" & x"0b0" => data <= x"10";
when "10" & x"0b1" => data <= x"38";
when "10" & x"0b2" => data <= x"f0";
when "10" & x"0b3" => data <= x"0d";
when "10" & x"0b4" => data <= x"20";
when "10" & x"0b5" => data <= x"c3";
when "10" & x"0b6" => data <= x"a0";
when "10" & x"0b7" => data <= x"a2";
when "10" & x"0b8" => data <= x"72";
when "10" & x"0b9" => data <= x"a0";
when "10" & x"0ba" => data <= x"10";
when "10" & x"0bb" => data <= x"68";
when "10" & x"0bc" => data <= x"48";
when "10" & x"0bd" => data <= x"20";
when "10" & x"0be" => data <= x"06";
when "10" & x"0bf" => data <= x"04";
when "10" & x"0c0" => data <= x"18";
when "10" & x"0c1" => data <= x"68";
when "10" & x"0c2" => data <= x"60";
when "10" & x"0c3" => data <= x"48";
when "10" & x"0c4" => data <= x"a9";
when "10" & x"0c5" => data <= x"c1";
when "10" & x"0c6" => data <= x"20";
when "10" & x"0c7" => data <= x"06";
when "10" & x"0c8" => data <= x"04";
when "10" & x"0c9" => data <= x"90";
when "10" & x"0ca" => data <= x"f9";
when "10" & x"0cb" => data <= x"68";
when "10" & x"0cc" => data <= x"60";
when "10" & x"0cd" => data <= x"ad";
when "10" & x"0ce" => data <= x"d6";
when "10" & x"0cf" => data <= x"10";
when "10" & x"0d0" => data <= x"f0";
when "10" & x"0d1" => data <= x"05";
when "10" & x"0d2" => data <= x"a9";
when "10" & x"0d3" => data <= x"81";
when "10" & x"0d4" => data <= x"20";
when "10" & x"0d5" => data <= x"06";
when "10" & x"0d6" => data <= x"04";
when "10" & x"0d7" => data <= x"60";
when "10" & x"0d8" => data <= x"9d";
when "10" & x"0d9" => data <= x"05";
when "10" & x"0da" => data <= x"01";
when "10" & x"0db" => data <= x"20";
when "10" & x"0dc" => data <= x"e4";
when "10" & x"0dd" => data <= x"95";
when "10" & x"0de" => data <= x"08";
when "10" & x"0df" => data <= x"ad";
when "10" & x"0e0" => data <= x"81";
when "10" & x"0e1" => data <= x"10";
when "10" & x"0e2" => data <= x"f0";
when "10" & x"0e3" => data <= x"05";
when "10" & x"0e4" => data <= x"a9";
when "10" & x"0e5" => data <= x"81";
when "10" & x"0e6" => data <= x"20";
when "10" & x"0e7" => data <= x"06";
when "10" & x"0e8" => data <= x"04";
when "10" & x"0e9" => data <= x"28";
when "10" & x"0ea" => data <= x"60";
when "10" & x"0eb" => data <= x"f0";
when "10" & x"0ec" => data <= x"06";
when "10" & x"0ed" => data <= x"20";
when "10" & x"0ee" => data <= x"c3";
when "10" & x"0ef" => data <= x"a0";
when "10" & x"0f0" => data <= x"18";
when "10" & x"0f1" => data <= x"a9";
when "10" & x"0f2" => data <= x"ff";
when "10" & x"0f3" => data <= x"4c";
when "10" & x"0f4" => data <= x"17";
when "10" & x"0f5" => data <= x"96";
when "10" & x"0f6" => data <= x"c9";
when "10" & x"0f7" => data <= x"fe";
when "10" & x"0f8" => data <= x"90";
when "10" & x"0f9" => data <= x"5a";
when "10" & x"0fa" => data <= x"d0";
when "10" & x"0fb" => data <= x"1b";
when "10" & x"0fc" => data <= x"c0";
when "10" & x"0fd" => data <= x"00";
when "10" & x"0fe" => data <= x"f0";
when "10" & x"0ff" => data <= x"54";
when "10" & x"100" => data <= x"a2";
when "10" & x"101" => data <= x"06";
when "10" & x"102" => data <= x"a9";
when "10" & x"103" => data <= x"14";
when "10" & x"104" => data <= x"20";
when "10" & x"105" => data <= x"f4";
when "10" & x"106" => data <= x"ff";
when "10" & x"107" => data <= x"2c";
when "10" & x"108" => data <= x"e0";
when "10" & x"109" => data <= x"fe";
when "10" & x"10a" => data <= x"10";
when "10" & x"10b" => data <= x"fb";
when "10" & x"10c" => data <= x"ad";
when "10" & x"10d" => data <= x"e1";
when "10" & x"10e" => data <= x"fe";
when "10" & x"10f" => data <= x"f0";
when "10" & x"110" => data <= x"41";
when "10" & x"111" => data <= x"20";
when "10" & x"112" => data <= x"ee";
when "10" & x"113" => data <= x"ff";
when "10" & x"114" => data <= x"4c";
when "10" & x"115" => data <= x"07";
when "10" & x"116" => data <= x"a1";
when "10" & x"117" => data <= x"a9";
when "10" & x"118" => data <= x"ad";
when "10" & x"119" => data <= x"8d";
when "10" & x"11a" => data <= x"20";
when "10" & x"11b" => data <= x"02";
when "10" & x"11c" => data <= x"a9";
when "10" & x"11d" => data <= x"06";
when "10" & x"11e" => data <= x"8d";
when "10" & x"11f" => data <= x"21";
when "10" & x"120" => data <= x"02";
when "10" & x"121" => data <= x"a9";
when "10" & x"122" => data <= x"16";
when "10" & x"123" => data <= x"8d";
when "10" & x"124" => data <= x"02";
when "10" & x"125" => data <= x"02";
when "10" & x"126" => data <= x"a0";
when "10" & x"127" => data <= x"00";
when "10" & x"128" => data <= x"8c";
when "10" & x"129" => data <= x"03";
when "10" & x"12a" => data <= x"02";
when "10" & x"12b" => data <= x"a9";
when "10" & x"12c" => data <= x"8e";
when "10" & x"12d" => data <= x"8d";
when "10" & x"12e" => data <= x"e0";
when "10" & x"12f" => data <= x"fe";
when "10" & x"130" => data <= x"b9";
when "10" & x"131" => data <= x"03";
when "10" & x"132" => data <= x"8b";
when "10" & x"133" => data <= x"99";
when "10" & x"134" => data <= x"00";
when "10" & x"135" => data <= x"04";
when "10" & x"136" => data <= x"b9";
when "10" & x"137" => data <= x"03";
when "10" & x"138" => data <= x"8c";
when "10" & x"139" => data <= x"99";
when "10" & x"13a" => data <= x"00";
when "10" & x"13b" => data <= x"05";
when "10" & x"13c" => data <= x"b9";
when "10" & x"13d" => data <= x"03";
when "10" & x"13e" => data <= x"8d";
when "10" & x"13f" => data <= x"99";
when "10" & x"140" => data <= x"00";
when "10" & x"141" => data <= x"06";
when "10" & x"142" => data <= x"88";
when "10" & x"143" => data <= x"d0";
when "10" & x"144" => data <= x"eb";
when "10" & x"145" => data <= x"20";
when "10" & x"146" => data <= x"21";
when "10" & x"147" => data <= x"04";
when "10" & x"148" => data <= x"a2";
when "10" & x"149" => data <= x"40";
when "10" & x"14a" => data <= x"bd";
when "10" & x"14b" => data <= x"c2";
when "10" & x"14c" => data <= x"8a";
when "10" & x"14d" => data <= x"95";
when "10" & x"14e" => data <= x"16";
when "10" & x"14f" => data <= x"ca";
when "10" & x"150" => data <= x"10";
when "10" & x"151" => data <= x"f8";
when "10" & x"152" => data <= x"a9";
when "10" & x"153" => data <= x"00";
when "10" & x"154" => data <= x"60";
when "10" & x"155" => data <= x"a9";
when "10" & x"156" => data <= x"00";
when "10" & x"157" => data <= x"8d";
when "10" & x"158" => data <= x"04";
when "10" & x"159" => data <= x"0d";
when "10" & x"15a" => data <= x"a9";
when "10" & x"15b" => data <= x"ff";
when "10" & x"15c" => data <= x"8d";
when "10" & x"15d" => data <= x"52";
when "10" & x"15e" => data <= x"0d";
when "10" & x"15f" => data <= x"48";
when "10" & x"160" => data <= x"4c";
when "10" & x"161" => data <= x"3b";
when "10" & x"162" => data <= x"93";
when "10" & x"163" => data <= x"b9";
when "10" & x"164" => data <= x"14";
when "10" & x"165" => data <= x"11";
when "10" & x"166" => data <= x"99";
when "10" & x"167" => data <= x"10";
when "10" & x"168" => data <= x"11";
when "10" & x"169" => data <= x"b9";
when "10" & x"16a" => data <= x"15";
when "10" & x"16b" => data <= x"11";
when "10" & x"16c" => data <= x"99";
when "10" & x"16d" => data <= x"11";
when "10" & x"16e" => data <= x"11";
when "10" & x"16f" => data <= x"b9";
when "10" & x"170" => data <= x"16";
when "10" & x"171" => data <= x"11";
when "10" & x"172" => data <= x"99";
when "10" & x"173" => data <= x"12";
when "10" & x"174" => data <= x"11";
when "10" & x"175" => data <= x"60";
when "10" & x"176" => data <= x"60";
when "10" & x"177" => data <= x"a2";
when "10" & x"178" => data <= x"06";
when "10" & x"179" => data <= x"8e";
when "10" & x"17a" => data <= x"40";
when "10" & x"17b" => data <= x"fe";
when "10" & x"17c" => data <= x"e8";
when "10" & x"17d" => data <= x"8e";
when "10" & x"17e" => data <= x"40";
when "10" & x"17f" => data <= x"fe";
when "10" & x"180" => data <= x"60";
when "10" & x"181" => data <= x"a9";
when "10" & x"182" => data <= x"76";
when "10" & x"183" => data <= x"ea";
when "10" & x"184" => data <= x"ea";
when "10" & x"185" => data <= x"ea";
when "10" & x"186" => data <= x"ea";
when "10" & x"187" => data <= x"ea";
when "10" & x"188" => data <= x"ea";
when "10" & x"189" => data <= x"60";
when "10" & x"18a" => data <= x"48";
when "10" & x"18b" => data <= x"68";
when "10" & x"18c" => data <= x"20";
when "10" & x"18d" => data <= x"85";
when "10" & x"18e" => data <= x"a1";
when "10" & x"18f" => data <= x"60";
when "10" & x"190" => data <= x"ad";
when "10" & x"191" => data <= x"bb";
when "10" & x"192" => data <= x"fc";
when "10" & x"193" => data <= x"8d";
when "10" & x"194" => data <= x"3a";
when "10" & x"195" => data <= x"0d";
when "10" & x"196" => data <= x"ad";
when "10" & x"197" => data <= x"b2";
when "10" & x"198" => data <= x"fc";
when "10" & x"199" => data <= x"8d";
when "10" & x"19a" => data <= x"3b";
when "10" & x"19b" => data <= x"0d";
when "10" & x"19c" => data <= x"60";
when "10" & x"19d" => data <= x"a9";
when "10" & x"19e" => data <= x"08";
when "10" & x"19f" => data <= x"8d";
when "10" & x"1a0" => data <= x"bb";
when "10" & x"1a1" => data <= x"fc";
when "10" & x"1a2" => data <= x"ad";
when "10" & x"1a3" => data <= x"b2";
when "10" & x"1a4" => data <= x"fc";
when "10" & x"1a5" => data <= x"4d";
when "10" & x"1a6" => data <= x"4c";
when "10" & x"1a7" => data <= x"0d";
when "10" & x"1a8" => data <= x"0d";
when "10" & x"1a9" => data <= x"4b";
when "10" & x"1aa" => data <= x"0d";
when "10" & x"1ab" => data <= x"8d";
when "10" & x"1ac" => data <= x"b2";
when "10" & x"1ad" => data <= x"fc";
when "10" & x"1ae" => data <= x"ad";
when "10" & x"1af" => data <= x"4b";
when "10" & x"1b0" => data <= x"0d";
when "10" & x"1b1" => data <= x"0d";
when "10" & x"1b2" => data <= x"3f";
when "10" & x"1b3" => data <= x"0d";
when "10" & x"1b4" => data <= x"0d";
when "10" & x"1b5" => data <= x"51";
when "10" & x"1b6" => data <= x"0d";
when "10" & x"1b7" => data <= x"8d";
when "10" & x"1b8" => data <= x"b0";
when "10" & x"1b9" => data <= x"fc";
when "10" & x"1ba" => data <= x"ad";
when "10" & x"1bb" => data <= x"ba";
when "10" & x"1bc" => data <= x"fc";
when "10" & x"1bd" => data <= x"60";
when "10" & x"1be" => data <= x"ad";
when "10" & x"1bf" => data <= x"bd";
when "10" & x"1c0" => data <= x"fc";
when "10" & x"1c1" => data <= x"29";
when "10" & x"1c2" => data <= x"04";
when "10" & x"1c3" => data <= x"f0";
when "10" & x"1c4" => data <= x"f9";
when "10" & x"1c5" => data <= x"60";
when "10" & x"1c6" => data <= x"ad";
when "10" & x"1c7" => data <= x"4c";
when "10" & x"1c8" => data <= x"0d";
when "10" & x"1c9" => data <= x"0d";
when "10" & x"1ca" => data <= x"3f";
when "10" & x"1cb" => data <= x"0d";
when "10" & x"1cc" => data <= x"0d";
when "10" & x"1cd" => data <= x"51";
when "10" & x"1ce" => data <= x"0d";
when "10" & x"1cf" => data <= x"8d";
when "10" & x"1d0" => data <= x"b0";
when "10" & x"1d1" => data <= x"fc";
when "10" & x"1d2" => data <= x"ad";
when "10" & x"1d3" => data <= x"3b";
when "10" & x"1d4" => data <= x"0d";
when "10" & x"1d5" => data <= x"8d";
when "10" & x"1d6" => data <= x"b2";
when "10" & x"1d7" => data <= x"fc";
when "10" & x"1d8" => data <= x"ad";
when "10" & x"1d9" => data <= x"3a";
when "10" & x"1da" => data <= x"0d";
when "10" & x"1db" => data <= x"8d";
when "10" & x"1dc" => data <= x"bb";
when "10" & x"1dd" => data <= x"fc";
when "10" & x"1de" => data <= x"ad";
when "10" & x"1df" => data <= x"ba";
when "10" & x"1e0" => data <= x"fc";
when "10" & x"1e1" => data <= x"60";
when "10" & x"1e2" => data <= x"20";
when "10" & x"1e3" => data <= x"90";
when "10" & x"1e4" => data <= x"a1";
when "10" & x"1e5" => data <= x"20";
when "10" & x"1e6" => data <= x"9d";
when "10" & x"1e7" => data <= x"a1";
when "10" & x"1e8" => data <= x"20";
when "10" & x"1e9" => data <= x"be";
when "10" & x"1ea" => data <= x"a1";
when "10" & x"1eb" => data <= x"20";
when "10" & x"1ec" => data <= x"c6";
when "10" & x"1ed" => data <= x"a1";
when "10" & x"1ee" => data <= x"60";
when "10" & x"1ef" => data <= x"20";
when "10" & x"1f0" => data <= x"90";
when "10" & x"1f1" => data <= x"a1";
when "10" & x"1f2" => data <= x"20";
when "10" & x"1f3" => data <= x"9d";
when "10" & x"1f4" => data <= x"a1";
when "10" & x"1f5" => data <= x"c0";
when "10" & x"1f6" => data <= x"ff";
when "10" & x"1f7" => data <= x"f0";
when "10" & x"1f8" => data <= x"0b";
when "10" & x"1f9" => data <= x"20";
when "10" & x"1fa" => data <= x"be";
when "10" & x"1fb" => data <= x"a1";
when "10" & x"1fc" => data <= x"ad";
when "10" & x"1fd" => data <= x"ba";
when "10" & x"1fe" => data <= x"fc";
when "10" & x"1ff" => data <= x"91";
when "10" & x"200" => data <= x"a0";
when "10" & x"201" => data <= x"c8";
when "10" & x"202" => data <= x"d0";
when "10" & x"203" => data <= x"f1";
when "10" & x"204" => data <= x"20";
when "10" & x"205" => data <= x"be";
when "10" & x"206" => data <= x"a1";
when "10" & x"207" => data <= x"20";
when "10" & x"208" => data <= x"c6";
when "10" & x"209" => data <= x"a1";
when "10" & x"20a" => data <= x"91";
when "10" & x"20b" => data <= x"a0";
when "10" & x"20c" => data <= x"e8";
when "10" & x"20d" => data <= x"c8";
when "10" & x"20e" => data <= x"60";
when "10" & x"20f" => data <= x"ad";
when "10" & x"210" => data <= x"4b";
when "10" & x"211" => data <= x"0d";
when "10" & x"212" => data <= x"0d";
when "10" & x"213" => data <= x"3f";
when "10" & x"214" => data <= x"0d";
when "10" & x"215" => data <= x"0d";
when "10" & x"216" => data <= x"51";
when "10" & x"217" => data <= x"0d";
when "10" & x"218" => data <= x"aa";
when "10" & x"219" => data <= x"ad";
when "10" & x"21a" => data <= x"4c";
when "10" & x"21b" => data <= x"0d";
when "10" & x"21c" => data <= x"0d";
when "10" & x"21d" => data <= x"3f";
when "10" & x"21e" => data <= x"0d";
when "10" & x"21f" => data <= x"0d";
when "10" & x"220" => data <= x"51";
when "10" & x"221" => data <= x"0d";
when "10" & x"222" => data <= x"8e";
when "10" & x"223" => data <= x"b0";
when "10" & x"224" => data <= x"fc";
when "10" & x"225" => data <= x"8d";
when "10" & x"226" => data <= x"b0";
when "10" & x"227" => data <= x"fc";
when "10" & x"228" => data <= x"8e";
when "10" & x"229" => data <= x"b0";
when "10" & x"22a" => data <= x"fc";
when "10" & x"22b" => data <= x"8d";
when "10" & x"22c" => data <= x"b0";
when "10" & x"22d" => data <= x"fc";
when "10" & x"22e" => data <= x"8e";
when "10" & x"22f" => data <= x"b0";
when "10" & x"230" => data <= x"fc";
when "10" & x"231" => data <= x"8d";
when "10" & x"232" => data <= x"b0";
when "10" & x"233" => data <= x"fc";
when "10" & x"234" => data <= x"8e";
when "10" & x"235" => data <= x"b0";
when "10" & x"236" => data <= x"fc";
when "10" & x"237" => data <= x"8d";
when "10" & x"238" => data <= x"b0";
when "10" & x"239" => data <= x"fc";
when "10" & x"23a" => data <= x"8e";
when "10" & x"23b" => data <= x"b0";
when "10" & x"23c" => data <= x"fc";
when "10" & x"23d" => data <= x"8d";
when "10" & x"23e" => data <= x"b0";
when "10" & x"23f" => data <= x"fc";
when "10" & x"240" => data <= x"8e";
when "10" & x"241" => data <= x"b0";
when "10" & x"242" => data <= x"fc";
when "10" & x"243" => data <= x"8d";
when "10" & x"244" => data <= x"b0";
when "10" & x"245" => data <= x"fc";
when "10" & x"246" => data <= x"8e";
when "10" & x"247" => data <= x"b0";
when "10" & x"248" => data <= x"fc";
when "10" & x"249" => data <= x"8d";
when "10" & x"24a" => data <= x"b0";
when "10" & x"24b" => data <= x"fc";
when "10" & x"24c" => data <= x"8e";
when "10" & x"24d" => data <= x"b0";
when "10" & x"24e" => data <= x"fc";
when "10" & x"24f" => data <= x"8d";
when "10" & x"250" => data <= x"b0";
when "10" & x"251" => data <= x"fc";
when "10" & x"252" => data <= x"ad";
when "10" & x"253" => data <= x"ba";
when "10" & x"254" => data <= x"fc";
when "10" & x"255" => data <= x"60";
when "10" & x"256" => data <= x"a9";
when "10" & x"257" => data <= x"18";
when "10" & x"258" => data <= x"8d";
when "10" & x"259" => data <= x"bb";
when "10" & x"25a" => data <= x"fc";
when "10" & x"25b" => data <= x"a9";
when "10" & x"25c" => data <= x"1d";
when "10" & x"25d" => data <= x"8d";
when "10" & x"25e" => data <= x"b2";
when "10" & x"25f" => data <= x"fc";
when "10" & x"260" => data <= x"a9";
when "10" & x"261" => data <= x"14";
when "10" & x"262" => data <= x"8d";
when "10" & x"263" => data <= x"b0";
when "10" & x"264" => data <= x"fc";
when "10" & x"265" => data <= x"60";
when "10" & x"266" => data <= x"20";
when "10" & x"267" => data <= x"90";
when "10" & x"268" => data <= x"a1";
when "10" & x"269" => data <= x"20";
when "10" & x"26a" => data <= x"56";
when "10" & x"26b" => data <= x"a2";
when "10" & x"26c" => data <= x"68";
when "10" & x"26d" => data <= x"8d";
when "10" & x"26e" => data <= x"ba";
when "10" & x"26f" => data <= x"fc";
when "10" & x"270" => data <= x"20";
when "10" & x"271" => data <= x"be";
when "10" & x"272" => data <= x"a1";
when "10" & x"273" => data <= x"20";
when "10" & x"274" => data <= x"8a";
when "10" & x"275" => data <= x"a1";
when "10" & x"276" => data <= x"4c";
when "10" & x"277" => data <= x"c6";
when "10" & x"278" => data <= x"a1";
when "10" & x"279" => data <= x"20";
when "10" & x"27a" => data <= x"90";
when "10" & x"27b" => data <= x"a1";
when "10" & x"27c" => data <= x"20";
when "10" & x"27d" => data <= x"56";
when "10" & x"27e" => data <= x"a2";
when "10" & x"27f" => data <= x"b1";
when "10" & x"280" => data <= x"a0";
when "10" & x"281" => data <= x"8d";
when "10" & x"282" => data <= x"ba";
when "10" & x"283" => data <= x"fc";
when "10" & x"284" => data <= x"20";
when "10" & x"285" => data <= x"be";
when "10" & x"286" => data <= x"a1";
when "10" & x"287" => data <= x"c8";
when "10" & x"288" => data <= x"d0";
when "10" & x"289" => data <= x"f5";
when "10" & x"28a" => data <= x"4c";
when "10" & x"28b" => data <= x"c6";
when "10" & x"28c" => data <= x"a1";
when "10" & x"28d" => data <= x"ad";
when "10" & x"28e" => data <= x"3f";
when "10" & x"28f" => data <= x"0d";
when "10" & x"290" => data <= x"d0";
when "10" & x"291" => data <= x"e7";
when "10" & x"292" => data <= x"b1";
when "10" & x"293" => data <= x"a0";
when "10" & x"294" => data <= x"20";
when "10" & x"295" => data <= x"9b";
when "10" & x"296" => data <= x"a2";
when "10" & x"297" => data <= x"c8";
when "10" & x"298" => data <= x"d0";
when "10" & x"299" => data <= x"f8";
when "10" & x"29a" => data <= x"60";
when "10" & x"29b" => data <= x"86";
when "10" & x"29c" => data <= x"b0";
when "10" & x"29d" => data <= x"ae";
when "10" & x"29e" => data <= x"4a";
when "10" & x"29f" => data <= x"0d";
when "10" & x"2a0" => data <= x"18";
when "10" & x"2a1" => data <= x"2a";
when "10" & x"2a2" => data <= x"2a";
when "10" & x"2a3" => data <= x"ca";
when "10" & x"2a4" => data <= x"d0";
when "10" & x"2a5" => data <= x"fb";
when "10" & x"2a6" => data <= x"48";
when "10" & x"2a7" => data <= x"2d";
when "10" & x"2a8" => data <= x"4c";
when "10" & x"2a9" => data <= x"0d";
when "10" & x"2aa" => data <= x"0d";
when "10" & x"2ab" => data <= x"3f";
when "10" & x"2ac" => data <= x"0d";
when "10" & x"2ad" => data <= x"0d";
when "10" & x"2ae" => data <= x"51";
when "10" & x"2af" => data <= x"0d";
when "10" & x"2b0" => data <= x"8d";
when "10" & x"2b1" => data <= x"b0";
when "10" & x"2b2" => data <= x"fc";
when "10" & x"2b3" => data <= x"0d";
when "10" & x"2b4" => data <= x"4e";
when "10" & x"2b5" => data <= x"0d";
when "10" & x"2b6" => data <= x"8d";
when "10" & x"2b7" => data <= x"b0";
when "10" & x"2b8" => data <= x"fc";
when "10" & x"2b9" => data <= x"68";
when "10" & x"2ba" => data <= x"a2";
when "10" & x"2bb" => data <= x"07";
when "10" & x"2bc" => data <= x"2a";
when "10" & x"2bd" => data <= x"48";
when "10" & x"2be" => data <= x"2d";
when "10" & x"2bf" => data <= x"4c";
when "10" & x"2c0" => data <= x"0d";
when "10" & x"2c1" => data <= x"0d";
when "10" & x"2c2" => data <= x"3f";
when "10" & x"2c3" => data <= x"0d";
when "10" & x"2c4" => data <= x"0d";
when "10" & x"2c5" => data <= x"51";
when "10" & x"2c6" => data <= x"0d";
when "10" & x"2c7" => data <= x"2d";
when "10" & x"2c8" => data <= x"4d";
when "10" & x"2c9" => data <= x"0d";
when "10" & x"2ca" => data <= x"8d";
when "10" & x"2cb" => data <= x"b0";
when "10" & x"2cc" => data <= x"fc";
when "10" & x"2cd" => data <= x"0d";
when "10" & x"2ce" => data <= x"4e";
when "10" & x"2cf" => data <= x"0d";
when "10" & x"2d0" => data <= x"8d";
when "10" & x"2d1" => data <= x"b0";
when "10" & x"2d2" => data <= x"fc";
when "10" & x"2d3" => data <= x"68";
when "10" & x"2d4" => data <= x"ca";
when "10" & x"2d5" => data <= x"d0";
when "10" & x"2d6" => data <= x"e5";
when "10" & x"2d7" => data <= x"a6";
when "10" & x"2d8" => data <= x"b0";
when "10" & x"2d9" => data <= x"60";
when "10" & x"2da" => data <= x"2c";
when "10" & x"2db" => data <= x"40";
when "10" & x"2dc" => data <= x"0d";
when "10" & x"2dd" => data <= x"30";
when "10" & x"2de" => data <= x"47";
when "10" & x"2df" => data <= x"ad";
when "10" & x"2e0" => data <= x"4b";
when "10" & x"2e1" => data <= x"0d";
when "10" & x"2e2" => data <= x"0d";
when "10" & x"2e3" => data <= x"3f";
when "10" & x"2e4" => data <= x"0d";
when "10" & x"2e5" => data <= x"0d";
when "10" & x"2e6" => data <= x"51";
when "10" & x"2e7" => data <= x"0d";
when "10" & x"2e8" => data <= x"aa";
when "10" & x"2e9" => data <= x"ad";
when "10" & x"2ea" => data <= x"4c";
when "10" & x"2eb" => data <= x"0d";
when "10" & x"2ec" => data <= x"0d";
when "10" & x"2ed" => data <= x"3f";
when "10" & x"2ee" => data <= x"0d";
when "10" & x"2ef" => data <= x"0d";
when "10" & x"2f0" => data <= x"51";
when "10" & x"2f1" => data <= x"0d";
when "10" & x"2f2" => data <= x"8e";
when "10" & x"2f3" => data <= x"b0";
when "10" & x"2f4" => data <= x"fc";
when "10" & x"2f5" => data <= x"8d";
when "10" & x"2f6" => data <= x"b0";
when "10" & x"2f7" => data <= x"fc";
when "10" & x"2f8" => data <= x"8e";
when "10" & x"2f9" => data <= x"b0";
when "10" & x"2fa" => data <= x"fc";
when "10" & x"2fb" => data <= x"8d";
when "10" & x"2fc" => data <= x"b0";
when "10" & x"2fd" => data <= x"fc";
when "10" & x"2fe" => data <= x"8e";
when "10" & x"2ff" => data <= x"b0";
when "10" & x"300" => data <= x"fc";
when "10" & x"301" => data <= x"8d";
when "10" & x"302" => data <= x"b0";
when "10" & x"303" => data <= x"fc";
when "10" & x"304" => data <= x"8e";
when "10" & x"305" => data <= x"b0";
when "10" & x"306" => data <= x"fc";
when "10" & x"307" => data <= x"8d";
when "10" & x"308" => data <= x"b0";
when "10" & x"309" => data <= x"fc";
when "10" & x"30a" => data <= x"8e";
when "10" & x"30b" => data <= x"b0";
when "10" & x"30c" => data <= x"fc";
when "10" & x"30d" => data <= x"8d";
when "10" & x"30e" => data <= x"b0";
when "10" & x"30f" => data <= x"fc";
when "10" & x"310" => data <= x"8e";
when "10" & x"311" => data <= x"b0";
when "10" & x"312" => data <= x"fc";
when "10" & x"313" => data <= x"8d";
when "10" & x"314" => data <= x"b0";
when "10" & x"315" => data <= x"fc";
when "10" & x"316" => data <= x"8e";
when "10" & x"317" => data <= x"b0";
when "10" & x"318" => data <= x"fc";
when "10" & x"319" => data <= x"8d";
when "10" & x"31a" => data <= x"b0";
when "10" & x"31b" => data <= x"fc";
when "10" & x"31c" => data <= x"8e";
when "10" & x"31d" => data <= x"b0";
when "10" & x"31e" => data <= x"fc";
when "10" & x"31f" => data <= x"8d";
when "10" & x"320" => data <= x"b0";
when "10" & x"321" => data <= x"fc";
when "10" & x"322" => data <= x"88";
when "10" & x"323" => data <= x"d0";
when "10" & x"324" => data <= x"cd";
when "10" & x"325" => data <= x"60";
when "10" & x"326" => data <= x"a9";
when "10" & x"327" => data <= x"ff";
when "10" & x"328" => data <= x"8d";
when "10" & x"329" => data <= x"28";
when "10" & x"32a" => data <= x"fc";
when "10" & x"32b" => data <= x"ea";
when "10" & x"32c" => data <= x"ea";
when "10" & x"32d" => data <= x"ea";
when "10" & x"32e" => data <= x"88";
when "10" & x"32f" => data <= x"d0";
when "10" & x"330" => data <= x"f7";
when "10" & x"331" => data <= x"60";
when "10" & x"332" => data <= x"a2";
when "10" & x"333" => data <= x"00";
when "10" & x"334" => data <= x"2c";
when "10" & x"335" => data <= x"40";
when "10" & x"336" => data <= x"0d";
when "10" & x"337" => data <= x"30";
when "10" & x"338" => data <= x"46";
when "10" & x"339" => data <= x"8e";
when "10" & x"33a" => data <= x"41";
when "10" & x"33b" => data <= x"0d";
when "10" & x"33c" => data <= x"a0";
when "10" & x"33d" => data <= x"07";
when "10" & x"33e" => data <= x"bd";
when "10" & x"33f" => data <= x"42";
when "10" & x"340" => data <= x"0d";
when "10" & x"341" => data <= x"20";
when "10" & x"342" => data <= x"9b";
when "10" & x"343" => data <= x"a2";
when "10" & x"344" => data <= x"e8";
when "10" & x"345" => data <= x"88";
when "10" & x"346" => data <= x"d0";
when "10" & x"347" => data <= x"f6";
when "10" & x"348" => data <= x"20";
when "10" & x"349" => data <= x"4e";
when "10" & x"34a" => data <= x"a3";
when "10" & x"34b" => data <= x"4c";
when "10" & x"34c" => data <= x"28";
when "10" & x"34d" => data <= x"a2";
when "10" & x"34e" => data <= x"a0";
when "10" & x"34f" => data <= x"00";
when "10" & x"350" => data <= x"84";
when "10" & x"351" => data <= x"b0";
when "10" & x"352" => data <= x"ad";
when "10" & x"353" => data <= x"4b";
when "10" & x"354" => data <= x"0d";
when "10" & x"355" => data <= x"0d";
when "10" & x"356" => data <= x"3f";
when "10" & x"357" => data <= x"0d";
when "10" & x"358" => data <= x"0d";
when "10" & x"359" => data <= x"51";
when "10" & x"35a" => data <= x"0d";
when "10" & x"35b" => data <= x"aa";
when "10" & x"35c" => data <= x"ad";
when "10" & x"35d" => data <= x"4c";
when "10" & x"35e" => data <= x"0d";
when "10" & x"35f" => data <= x"0d";
when "10" & x"360" => data <= x"3f";
when "10" & x"361" => data <= x"0d";
when "10" & x"362" => data <= x"0d";
when "10" & x"363" => data <= x"51";
when "10" & x"364" => data <= x"0d";
when "10" & x"365" => data <= x"a8";
when "10" & x"366" => data <= x"c6";
when "10" & x"367" => data <= x"b0";
when "10" & x"368" => data <= x"f0";
when "10" & x"369" => data <= x"0f";
when "10" & x"36a" => data <= x"8e";
when "10" & x"36b" => data <= x"b0";
when "10" & x"36c" => data <= x"fc";
when "10" & x"36d" => data <= x"8c";
when "10" & x"36e" => data <= x"b0";
when "10" & x"36f" => data <= x"fc";
when "10" & x"370" => data <= x"ad";
when "10" & x"371" => data <= x"ba";
when "10" & x"372" => data <= x"fc";
when "10" & x"373" => data <= x"29";
when "10" & x"374" => data <= x"01";
when "10" & x"375" => data <= x"d0";
when "10" & x"376" => data <= x"ef";
when "10" & x"377" => data <= x"98";
when "10" & x"378" => data <= x"60";
when "10" & x"379" => data <= x"ad";
when "10" & x"37a" => data <= x"ba";
when "10" & x"37b" => data <= x"fc";
when "10" & x"37c" => data <= x"c9";
when "10" & x"37d" => data <= x"00";
when "10" & x"37e" => data <= x"60";
when "10" & x"37f" => data <= x"8e";
when "10" & x"380" => data <= x"41";
when "10" & x"381" => data <= x"0d";
when "10" & x"382" => data <= x"a0";
when "10" & x"383" => data <= x"08";
when "10" & x"384" => data <= x"bd";
when "10" & x"385" => data <= x"42";
when "10" & x"386" => data <= x"0d";
when "10" & x"387" => data <= x"8d";
when "10" & x"388" => data <= x"28";
when "10" & x"389" => data <= x"fc";
when "10" & x"38a" => data <= x"ea";
when "10" & x"38b" => data <= x"ea";
when "10" & x"38c" => data <= x"e8";
when "10" & x"38d" => data <= x"88";
when "10" & x"38e" => data <= x"d0";
when "10" & x"38f" => data <= x"f4";
when "10" & x"390" => data <= x"8d";
when "10" & x"391" => data <= x"28";
when "10" & x"392" => data <= x"fc";
when "10" & x"393" => data <= x"20";
when "10" & x"394" => data <= x"31";
when "10" & x"395" => data <= x"a3";
when "10" & x"396" => data <= x"ad";
when "10" & x"397" => data <= x"28";
when "10" & x"398" => data <= x"fc";
when "10" & x"399" => data <= x"10";
when "10" & x"39a" => data <= x"e3";
when "10" & x"39b" => data <= x"88";
when "10" & x"39c" => data <= x"d0";
when "10" & x"39d" => data <= x"f5";
when "10" & x"39e" => data <= x"4c";
when "10" & x"39f" => data <= x"7c";
when "10" & x"3a0" => data <= x"a3";
when "10" & x"3a1" => data <= x"2c";
when "10" & x"3a2" => data <= x"40";
when "10" & x"3a3" => data <= x"0d";
when "10" & x"3a4" => data <= x"30";
when "10" & x"3a5" => data <= x"08";
when "10" & x"3a6" => data <= x"20";
when "10" & x"3a7" => data <= x"e2";
when "10" & x"3a8" => data <= x"a1";
when "10" & x"3a9" => data <= x"c9";
when "10" & x"3aa" => data <= x"fe";
when "10" & x"3ab" => data <= x"d0";
when "10" & x"3ac" => data <= x"f9";
when "10" & x"3ad" => data <= x"60";
when "10" & x"3ae" => data <= x"a2";
when "10" & x"3af" => data <= x"ff";
when "10" & x"3b0" => data <= x"8e";
when "10" & x"3b1" => data <= x"28";
when "10" & x"3b2" => data <= x"fc";
when "10" & x"3b3" => data <= x"20";
when "10" & x"3b4" => data <= x"31";
when "10" & x"3b5" => data <= x"a3";
when "10" & x"3b6" => data <= x"ad";
when "10" & x"3b7" => data <= x"28";
when "10" & x"3b8" => data <= x"fc";
when "10" & x"3b9" => data <= x"c9";
when "10" & x"3ba" => data <= x"fe";
when "10" & x"3bb" => data <= x"d0";
when "10" & x"3bc" => data <= x"f3";
when "10" & x"3bd" => data <= x"60";
when "10" & x"3be" => data <= x"2c";
when "10" & x"3bf" => data <= x"40";
when "10" & x"3c0" => data <= x"0d";
when "10" & x"3c1" => data <= x"30";
when "10" & x"3c2" => data <= x"0d";
when "10" & x"3c3" => data <= x"ac";
when "10" & x"3c4" => data <= x"d6";
when "10" & x"3c5" => data <= x"10";
when "10" & x"3c6" => data <= x"d0";
when "10" & x"3c7" => data <= x"03";
when "10" & x"3c8" => data <= x"4c";
when "10" & x"3c9" => data <= x"ef";
when "10" & x"3ca" => data <= x"a1";
when "10" & x"3cb" => data <= x"a0";
when "10" & x"3cc" => data <= x"00";
when "10" & x"3cd" => data <= x"4c";
when "10" & x"3ce" => data <= x"0e";
when "10" & x"3cf" => data <= x"a4";
when "10" & x"3d0" => data <= x"a2";
when "10" & x"3d1" => data <= x"ff";
when "10" & x"3d2" => data <= x"8e";
when "10" & x"3d3" => data <= x"28";
when "10" & x"3d4" => data <= x"fc";
when "10" & x"3d5" => data <= x"ac";
when "10" & x"3d6" => data <= x"d6";
when "10" & x"3d7" => data <= x"10";
when "10" & x"3d8" => data <= x"d0";
when "10" & x"3d9" => data <= x"16";
when "10" & x"3da" => data <= x"ea";
when "10" & x"3db" => data <= x"ea";
when "10" & x"3dc" => data <= x"ea";
when "10" & x"3dd" => data <= x"ad";
when "10" & x"3de" => data <= x"28";
when "10" & x"3df" => data <= x"fc";
when "10" & x"3e0" => data <= x"8e";
when "10" & x"3e1" => data <= x"28";
when "10" & x"3e2" => data <= x"fc";
when "10" & x"3e3" => data <= x"91";
when "10" & x"3e4" => data <= x"a0";
when "10" & x"3e5" => data <= x"c8";
when "10" & x"3e6" => data <= x"c0";
when "10" & x"3e7" => data <= x"ff";
when "10" & x"3e8" => data <= x"d0";
when "10" & x"3e9" => data <= x"f3";
when "10" & x"3ea" => data <= x"ad";
when "10" & x"3eb" => data <= x"28";
when "10" & x"3ec" => data <= x"fc";
when "10" & x"3ed" => data <= x"91";
when "10" & x"3ee" => data <= x"a0";
when "10" & x"3ef" => data <= x"60";
when "10" & x"3f0" => data <= x"a0";
when "10" & x"3f1" => data <= x"00";
when "10" & x"3f2" => data <= x"4c";
when "10" & x"3f3" => data <= x"3e";
when "10" & x"3f4" => data <= x"a4";
when "10" & x"3f5" => data <= x"2c";
when "10" & x"3f6" => data <= x"40";
when "10" & x"3f7" => data <= x"0d";
when "10" & x"3f8" => data <= x"30";
when "10" & x"3f9" => data <= x"1e";
when "10" & x"3fa" => data <= x"ac";
when "10" & x"3fb" => data <= x"d6";
when "10" & x"3fc" => data <= x"10";
when "10" & x"3fd" => data <= x"d0";
when "10" & x"3fe" => data <= x"0c";
when "10" & x"3ff" => data <= x"20";
when "10" & x"400" => data <= x"e2";
when "10" & x"401" => data <= x"a1";
when "10" & x"402" => data <= x"91";
when "10" & x"403" => data <= x"a0";
when "10" & x"404" => data <= x"c8";
when "10" & x"405" => data <= x"ce";
when "10" & x"406" => data <= x"29";
when "10" & x"407" => data <= x"0d";
when "10" & x"408" => data <= x"d0";
when "10" & x"409" => data <= x"f5";
when "10" & x"40a" => data <= x"60";
when "10" & x"40b" => data <= x"ac";
when "10" & x"40c" => data <= x"29";
when "10" & x"40d" => data <= x"0d";
when "10" & x"40e" => data <= x"20";
when "10" & x"40f" => data <= x"e2";
when "10" & x"410" => data <= x"a1";
when "10" & x"411" => data <= x"8d";
when "10" & x"412" => data <= x"e5";
when "10" & x"413" => data <= x"fe";
when "10" & x"414" => data <= x"88";
when "10" & x"415" => data <= x"d0";
when "10" & x"416" => data <= x"f7";
when "10" & x"417" => data <= x"60";
when "10" & x"418" => data <= x"a2";
when "10" & x"419" => data <= x"ff";
when "10" & x"41a" => data <= x"8e";
when "10" & x"41b" => data <= x"28";
when "10" & x"41c" => data <= x"fc";
when "10" & x"41d" => data <= x"ac";
when "10" & x"41e" => data <= x"d6";
when "10" & x"41f" => data <= x"10";
when "10" & x"420" => data <= x"d0";
when "10" & x"421" => data <= x"19";
when "10" & x"422" => data <= x"ce";
when "10" & x"423" => data <= x"29";
when "10" & x"424" => data <= x"0d";
when "10" & x"425" => data <= x"f0";
when "10" & x"426" => data <= x"0e";
when "10" & x"427" => data <= x"ad";
when "10" & x"428" => data <= x"28";
when "10" & x"429" => data <= x"fc";
when "10" & x"42a" => data <= x"8e";
when "10" & x"42b" => data <= x"28";
when "10" & x"42c" => data <= x"fc";
when "10" & x"42d" => data <= x"91";
when "10" & x"42e" => data <= x"a0";
when "10" & x"42f" => data <= x"c8";
when "10" & x"430" => data <= x"ce";
when "10" & x"431" => data <= x"29";
when "10" & x"432" => data <= x"0d";
when "10" & x"433" => data <= x"d0";
when "10" & x"434" => data <= x"f2";
when "10" & x"435" => data <= x"ad";
when "10" & x"436" => data <= x"28";
when "10" & x"437" => data <= x"fc";
when "10" & x"438" => data <= x"91";
when "10" & x"439" => data <= x"a0";
when "10" & x"43a" => data <= x"60";
when "10" & x"43b" => data <= x"ac";
when "10" & x"43c" => data <= x"29";
when "10" & x"43d" => data <= x"0d";
when "10" & x"43e" => data <= x"88";
when "10" & x"43f" => data <= x"f0";
when "10" & x"440" => data <= x"1a";
when "10" & x"441" => data <= x"ea";
when "10" & x"442" => data <= x"ad";
when "10" & x"443" => data <= x"28";
when "10" & x"444" => data <= x"fc";
when "10" & x"445" => data <= x"8e";
when "10" & x"446" => data <= x"28";
when "10" & x"447" => data <= x"fc";
when "10" & x"448" => data <= x"8d";
when "10" & x"449" => data <= x"e5";
when "10" & x"44a" => data <= x"fe";
when "10" & x"44b" => data <= x"20";
when "10" & x"44c" => data <= x"31";
when "10" & x"44d" => data <= x"a3";
when "10" & x"44e" => data <= x"20";
when "10" & x"44f" => data <= x"31";
when "10" & x"450" => data <= x"a3";
when "10" & x"451" => data <= x"ea";
when "10" & x"452" => data <= x"ea";
when "10" & x"453" => data <= x"ea";
when "10" & x"454" => data <= x"88";
when "10" & x"455" => data <= x"d0";
when "10" & x"456" => data <= x"ea";
when "10" & x"457" => data <= x"ea";
when "10" & x"458" => data <= x"ea";
when "10" & x"459" => data <= x"ea";
when "10" & x"45a" => data <= x"ea";
when "10" & x"45b" => data <= x"ad";
when "10" & x"45c" => data <= x"28";
when "10" & x"45d" => data <= x"fc";
when "10" & x"45e" => data <= x"8d";
when "10" & x"45f" => data <= x"e5";
when "10" & x"460" => data <= x"fe";
when "10" & x"461" => data <= x"60";
when "10" & x"462" => data <= x"2c";
when "10" & x"463" => data <= x"40";
when "10" & x"464" => data <= x"0d";
when "10" & x"465" => data <= x"30";
when "10" & x"466" => data <= x"0c";
when "10" & x"467" => data <= x"a0";
when "10" & x"468" => data <= x"00";
when "10" & x"469" => data <= x"20";
when "10" & x"46a" => data <= x"e2";
when "10" & x"46b" => data <= x"a1";
when "10" & x"46c" => data <= x"99";
when "10" & x"46d" => data <= x"00";
when "10" & x"46e" => data <= x"0e";
when "10" & x"46f" => data <= x"c8";
when "10" & x"470" => data <= x"d0";
when "10" & x"471" => data <= x"f7";
when "10" & x"472" => data <= x"60";
when "10" & x"473" => data <= x"a0";
when "10" & x"474" => data <= x"00";
when "10" & x"475" => data <= x"a2";
when "10" & x"476" => data <= x"ff";
when "10" & x"477" => data <= x"8e";
when "10" & x"478" => data <= x"28";
when "10" & x"479" => data <= x"fc";
when "10" & x"47a" => data <= x"20";
when "10" & x"47b" => data <= x"31";
when "10" & x"47c" => data <= x"a3";
when "10" & x"47d" => data <= x"ad";
when "10" & x"47e" => data <= x"28";
when "10" & x"47f" => data <= x"fc";
when "10" & x"480" => data <= x"8e";
when "10" & x"481" => data <= x"28";
when "10" & x"482" => data <= x"fc";
when "10" & x"483" => data <= x"99";
when "10" & x"484" => data <= x"00";
when "10" & x"485" => data <= x"0e";
when "10" & x"486" => data <= x"c8";
when "10" & x"487" => data <= x"c0";
when "10" & x"488" => data <= x"ff";
when "10" & x"489" => data <= x"d0";
when "10" & x"48a" => data <= x"f2";
when "10" & x"48b" => data <= x"ad";
when "10" & x"48c" => data <= x"28";
when "10" & x"48d" => data <= x"fc";
when "10" & x"48e" => data <= x"99";
when "10" & x"48f" => data <= x"00";
when "10" & x"490" => data <= x"0e";
when "10" & x"491" => data <= x"60";
when "10" & x"492" => data <= x"2c";
when "10" & x"493" => data <= x"40";
when "10" & x"494" => data <= x"0d";
when "10" & x"495" => data <= x"30";
when "10" & x"496" => data <= x"0a";
when "10" & x"497" => data <= x"a0";
when "10" & x"498" => data <= x"02";
when "10" & x"499" => data <= x"20";
when "10" & x"49a" => data <= x"df";
when "10" & x"49b" => data <= x"a2";
when "10" & x"49c" => data <= x"a9";
when "10" & x"49d" => data <= x"fe";
when "10" & x"49e" => data <= x"4c";
when "10" & x"49f" => data <= x"9b";
when "10" & x"4a0" => data <= x"a2";
when "10" & x"4a1" => data <= x"a2";
when "10" & x"4a2" => data <= x"ff";
when "10" & x"4a3" => data <= x"8e";
when "10" & x"4a4" => data <= x"28";
when "10" & x"4a5" => data <= x"fc";
when "10" & x"4a6" => data <= x"20";
when "10" & x"4a7" => data <= x"31";
when "10" & x"4a8" => data <= x"a3";
when "10" & x"4a9" => data <= x"8e";
when "10" & x"4aa" => data <= x"28";
when "10" & x"4ab" => data <= x"fc";
when "10" & x"4ac" => data <= x"20";
when "10" & x"4ad" => data <= x"31";
when "10" & x"4ae" => data <= x"a3";
when "10" & x"4af" => data <= x"ca";
when "10" & x"4b0" => data <= x"8e";
when "10" & x"4b1" => data <= x"28";
when "10" & x"4b2" => data <= x"fc";
when "10" & x"4b3" => data <= x"60";
when "10" & x"4b4" => data <= x"a0";
when "10" & x"4b5" => data <= x"02";
when "10" & x"4b6" => data <= x"2c";
when "10" & x"4b7" => data <= x"40";
when "10" & x"4b8" => data <= x"0d";
when "10" & x"4b9" => data <= x"30";
when "10" & x"4ba" => data <= x"18";
when "10" & x"4bb" => data <= x"20";
when "10" & x"4bc" => data <= x"df";
when "10" & x"4bd" => data <= x"a2";
when "10" & x"4be" => data <= x"20";
when "10" & x"4bf" => data <= x"4e";
when "10" & x"4c0" => data <= x"a3";
when "10" & x"4c1" => data <= x"20";
when "10" & x"4c2" => data <= x"3a";
when "10" & x"4c3" => data <= x"a2";
when "10" & x"4c4" => data <= x"a8";
when "10" & x"4c5" => data <= x"29";
when "10" & x"4c6" => data <= x"1f";
when "10" & x"4c7" => data <= x"c9";
when "10" & x"4c8" => data <= x"05";
when "10" & x"4c9" => data <= x"d0";
when "10" & x"4ca" => data <= x"2b";
when "10" & x"4cb" => data <= x"20";
when "10" & x"4cc" => data <= x"e2";
when "10" & x"4cd" => data <= x"a1";
when "10" & x"4ce" => data <= x"c9";
when "10" & x"4cf" => data <= x"ff";
when "10" & x"4d0" => data <= x"d0";
when "10" & x"4d1" => data <= x"f9";
when "10" & x"4d2" => data <= x"60";
when "10" & x"4d3" => data <= x"20";
when "10" & x"4d4" => data <= x"26";
when "10" & x"4d5" => data <= x"a3";
when "10" & x"4d6" => data <= x"a2";
when "10" & x"4d7" => data <= x"ff";
when "10" & x"4d8" => data <= x"8e";
when "10" & x"4d9" => data <= x"28";
when "10" & x"4da" => data <= x"fc";
when "10" & x"4db" => data <= x"20";
when "10" & x"4dc" => data <= x"31";
when "10" & x"4dd" => data <= x"a3";
when "10" & x"4de" => data <= x"ad";
when "10" & x"4df" => data <= x"28";
when "10" & x"4e0" => data <= x"fc";
when "10" & x"4e1" => data <= x"a8";
when "10" & x"4e2" => data <= x"29";
when "10" & x"4e3" => data <= x"1f";
when "10" & x"4e4" => data <= x"c9";
when "10" & x"4e5" => data <= x"05";
when "10" & x"4e6" => data <= x"d0";
when "10" & x"4e7" => data <= x"0e";
when "10" & x"4e8" => data <= x"a9";
when "10" & x"4e9" => data <= x"ff";
when "10" & x"4ea" => data <= x"8e";
when "10" & x"4eb" => data <= x"28";
when "10" & x"4ec" => data <= x"fc";
when "10" & x"4ed" => data <= x"20";
when "10" & x"4ee" => data <= x"31";
when "10" & x"4ef" => data <= x"a3";
when "10" & x"4f0" => data <= x"cd";
when "10" & x"4f1" => data <= x"28";
when "10" & x"4f2" => data <= x"fc";
when "10" & x"4f3" => data <= x"d0";
when "10" & x"4f4" => data <= x"f5";
when "10" & x"4f5" => data <= x"60";
when "10" & x"4f6" => data <= x"98";
when "10" & x"4f7" => data <= x"20";
when "10" & x"4f8" => data <= x"1f";
when "10" & x"4f9" => data <= x"a0";
when "10" & x"4fa" => data <= x"c5";
when "10" & x"4fb" => data <= x"4d";
when "10" & x"4fc" => data <= x"4d";
when "10" & x"4fd" => data <= x"43";
when "10" & x"4fe" => data <= x"20";
when "10" & x"4ff" => data <= x"57";
when "10" & x"500" => data <= x"72";
when "10" & x"501" => data <= x"69";
when "10" & x"502" => data <= x"74";
when "10" & x"503" => data <= x"65";
when "10" & x"504" => data <= x"20";
when "10" & x"505" => data <= x"72";
when "10" & x"506" => data <= x"65";
when "10" & x"507" => data <= x"73";
when "10" & x"508" => data <= x"70";
when "10" & x"509" => data <= x"6f";
when "10" & x"50a" => data <= x"6e";
when "10" & x"50b" => data <= x"73";
when "10" & x"50c" => data <= x"65";
when "10" & x"50d" => data <= x"20";
when "10" & x"50e" => data <= x"66";
when "10" & x"50f" => data <= x"61";
when "10" & x"510" => data <= x"75";
when "10" & x"511" => data <= x"6c";
when "10" & x"512" => data <= x"74";
when "10" & x"513" => data <= x"20";
when "10" & x"514" => data <= x"00";
when "10" & x"515" => data <= x"2c";
when "10" & x"516" => data <= x"40";
when "10" & x"517" => data <= x"0d";
when "10" & x"518" => data <= x"30";
when "10" & x"519" => data <= x"14";
when "10" & x"51a" => data <= x"ac";
when "10" & x"51b" => data <= x"d6";
when "10" & x"51c" => data <= x"10";
when "10" & x"51d" => data <= x"d0";
when "10" & x"51e" => data <= x"03";
when "10" & x"51f" => data <= x"4c";
when "10" & x"520" => data <= x"8d";
when "10" & x"521" => data <= x"a2";
when "10" & x"522" => data <= x"a0";
when "10" & x"523" => data <= x"00";
when "10" & x"524" => data <= x"ad";
when "10" & x"525" => data <= x"e5";
when "10" & x"526" => data <= x"fe";
when "10" & x"527" => data <= x"20";
when "10" & x"528" => data <= x"9b";
when "10" & x"529" => data <= x"a2";
when "10" & x"52a" => data <= x"c8";
when "10" & x"52b" => data <= x"d0";
when "10" & x"52c" => data <= x"f7";
when "10" & x"52d" => data <= x"60";
when "10" & x"52e" => data <= x"ac";
when "10" & x"52f" => data <= x"d6";
when "10" & x"530" => data <= x"10";
when "10" & x"531" => data <= x"d0";
when "10" & x"532" => data <= x"09";
when "10" & x"533" => data <= x"b1";
when "10" & x"534" => data <= x"a0";
when "10" & x"535" => data <= x"8d";
when "10" & x"536" => data <= x"28";
when "10" & x"537" => data <= x"fc";
when "10" & x"538" => data <= x"c8";
when "10" & x"539" => data <= x"d0";
when "10" & x"53a" => data <= x"f8";
when "10" & x"53b" => data <= x"60";
when "10" & x"53c" => data <= x"a0";
when "10" & x"53d" => data <= x"00";
when "10" & x"53e" => data <= x"ad";
when "10" & x"53f" => data <= x"e5";
when "10" & x"540" => data <= x"fe";
when "10" & x"541" => data <= x"8d";
when "10" & x"542" => data <= x"28";
when "10" & x"543" => data <= x"fc";
when "10" & x"544" => data <= x"20";
when "10" & x"545" => data <= x"31";
when "10" & x"546" => data <= x"a3";
when "10" & x"547" => data <= x"20";
when "10" & x"548" => data <= x"31";
when "10" & x"549" => data <= x"a3";
when "10" & x"54a" => data <= x"20";
when "10" & x"54b" => data <= x"31";
when "10" & x"54c" => data <= x"a3";
when "10" & x"54d" => data <= x"c8";
when "10" & x"54e" => data <= x"d0";
when "10" & x"54f" => data <= x"ee";
when "10" & x"550" => data <= x"60";
when "10" & x"551" => data <= x"2c";
when "10" & x"552" => data <= x"40";
when "10" & x"553" => data <= x"0d";
when "10" & x"554" => data <= x"30";
when "10" & x"555" => data <= x"0c";
when "10" & x"556" => data <= x"a0";
when "10" & x"557" => data <= x"00";
when "10" & x"558" => data <= x"b9";
when "10" & x"559" => data <= x"00";
when "10" & x"55a" => data <= x"0e";
when "10" & x"55b" => data <= x"20";
when "10" & x"55c" => data <= x"9b";
when "10" & x"55d" => data <= x"a2";
when "10" & x"55e" => data <= x"c8";
when "10" & x"55f" => data <= x"d0";
when "10" & x"560" => data <= x"f7";
when "10" & x"561" => data <= x"60";
when "10" & x"562" => data <= x"a0";
when "10" & x"563" => data <= x"00";
when "10" & x"564" => data <= x"ea";
when "10" & x"565" => data <= x"b9";
when "10" & x"566" => data <= x"00";
when "10" & x"567" => data <= x"0e";
when "10" & x"568" => data <= x"8d";
when "10" & x"569" => data <= x"28";
when "10" & x"56a" => data <= x"fc";
when "10" & x"56b" => data <= x"c8";
when "10" & x"56c" => data <= x"d0";
when "10" & x"56d" => data <= x"f6";
when "10" & x"56e" => data <= x"60";
when "10" & x"56f" => data <= x"a2";
when "10" & x"570" => data <= x"00";
when "10" & x"571" => data <= x"9d";
when "10" & x"572" => data <= x"43";
when "10" & x"573" => data <= x"0d";
when "10" & x"574" => data <= x"a9";
when "10" & x"575" => data <= x"00";
when "10" & x"576" => data <= x"9d";
when "10" & x"577" => data <= x"44";
when "10" & x"578" => data <= x"0d";
when "10" & x"579" => data <= x"9d";
when "10" & x"57a" => data <= x"45";
when "10" & x"57b" => data <= x"0d";
when "10" & x"57c" => data <= x"9d";
when "10" & x"57d" => data <= x"46";
when "10" & x"57e" => data <= x"0d";
when "10" & x"57f" => data <= x"9d";
when "10" & x"580" => data <= x"47";
when "10" & x"581" => data <= x"0d";
when "10" & x"582" => data <= x"a9";
when "10" & x"583" => data <= x"ff";
when "10" & x"584" => data <= x"9d";
when "10" & x"585" => data <= x"42";
when "10" & x"586" => data <= x"0d";
when "10" & x"587" => data <= x"9d";
when "10" & x"588" => data <= x"48";
when "10" & x"589" => data <= x"0d";
when "10" & x"58a" => data <= x"9d";
when "10" & x"58b" => data <= x"49";
when "10" & x"58c" => data <= x"0d";
when "10" & x"58d" => data <= x"ae";
when "10" & x"58e" => data <= x"03";
when "10" & x"58f" => data <= x"0d";
when "10" & x"590" => data <= x"bd";
when "10" & x"591" => data <= x"ae";
when "10" & x"592" => data <= x"a5";
when "10" & x"593" => data <= x"8d";
when "10" & x"594" => data <= x"40";
when "10" & x"595" => data <= x"0d";
when "10" & x"596" => data <= x"60";
when "10" & x"597" => data <= x"2c";
when "10" & x"598" => data <= x"c9";
when "10" & x"599" => data <= x"10";
when "10" & x"59a" => data <= x"30";
when "10" & x"59b" => data <= x"11";
when "10" & x"59c" => data <= x"a9";
when "10" & x"59d" => data <= x"8f";
when "10" & x"59e" => data <= x"a2";
when "10" & x"59f" => data <= x"0c";
when "10" & x"5a0" => data <= x"a0";
when "10" & x"5a1" => data <= x"ff";
when "10" & x"5a2" => data <= x"20";
when "10" & x"5a3" => data <= x"f4";
when "10" & x"5a4" => data <= x"ff";
when "10" & x"5a5" => data <= x"8c";
when "10" & x"5a6" => data <= x"01";
when "10" & x"5a7" => data <= x"0d";
when "10" & x"5a8" => data <= x"a9";
when "10" & x"5a9" => data <= x"ff";
when "10" & x"5aa" => data <= x"8d";
when "10" & x"5ab" => data <= x"c9";
when "10" & x"5ac" => data <= x"10";
when "10" & x"5ad" => data <= x"60";
when "10" & x"5ae" => data <= x"00";
when "10" & x"5af" => data <= x"80";
when "10" & x"5b0" => data <= x"ad";
when "10" & x"5b1" => data <= x"4f";
when "10" & x"5b2" => data <= x"0d";
when "10" & x"5b3" => data <= x"f0";
when "10" & x"5b4" => data <= x"15";
when "10" & x"5b5" => data <= x"ad";
when "10" & x"5b6" => data <= x"3f";
when "10" & x"5b7" => data <= x"0d";
when "10" & x"5b8" => data <= x"d0";
when "10" & x"5b9" => data <= x"26";
when "10" & x"5ba" => data <= x"ad";
when "10" & x"5bb" => data <= x"50";
when "10" & x"5bc" => data <= x"0d";
when "10" & x"5bd" => data <= x"d0";
when "10" & x"5be" => data <= x"0b";
when "10" & x"5bf" => data <= x"ad";
when "10" & x"5c0" => data <= x"b2";
when "10" & x"5c1" => data <= x"fc";
when "10" & x"5c2" => data <= x"cd";
when "10" & x"5c3" => data <= x"4c";
when "10" & x"5c4" => data <= x"0d";
when "10" & x"5c5" => data <= x"f0";
when "10" & x"5c6" => data <= x"03";
when "10" & x"5c7" => data <= x"20";
when "10" & x"5c8" => data <= x"d6";
when "10" & x"5c9" => data <= x"a9";
when "10" & x"5ca" => data <= x"ad";
when "10" & x"5cb" => data <= x"4c";
when "10" & x"5cc" => data <= x"0d";
when "10" & x"5cd" => data <= x"2d";
when "10" & x"5ce" => data <= x"50";
when "10" & x"5cf" => data <= x"0d";
when "10" & x"5d0" => data <= x"d0";
when "10" & x"5d1" => data <= x"36";
when "10" & x"5d2" => data <= x"ad";
when "10" & x"5d3" => data <= x"4c";
when "10" & x"5d4" => data <= x"0d";
when "10" & x"5d5" => data <= x"0d";
when "10" & x"5d6" => data <= x"50";
when "10" & x"5d7" => data <= x"0d";
when "10" & x"5d8" => data <= x"8d";
when "10" & x"5d9" => data <= x"b2";
when "10" & x"5da" => data <= x"fc";
when "10" & x"5db" => data <= x"ad";
when "10" & x"5dc" => data <= x"3f";
when "10" & x"5dd" => data <= x"0d";
when "10" & x"5de" => data <= x"f0";
when "10" & x"5df" => data <= x"0a";
when "10" & x"5e0" => data <= x"a9";
when "10" & x"5e1" => data <= x"1f";
when "10" & x"5e2" => data <= x"8d";
when "10" & x"5e3" => data <= x"b2";
when "10" & x"5e4" => data <= x"fc";
when "10" & x"5e5" => data <= x"a9";
when "10" & x"5e6" => data <= x"00";
when "10" & x"5e7" => data <= x"8d";
when "10" & x"5e8" => data <= x"50";
when "10" & x"5e9" => data <= x"0d";
when "10" & x"5ea" => data <= x"ad";
when "10" & x"5eb" => data <= x"3f";
when "10" & x"5ec" => data <= x"0d";
when "10" & x"5ed" => data <= x"d0";
when "10" & x"5ee" => data <= x"03";
when "10" & x"5ef" => data <= x"0d";
when "10" & x"5f0" => data <= x"51";
when "10" & x"5f1" => data <= x"0d";
when "10" & x"5f2" => data <= x"8d";
when "10" & x"5f3" => data <= x"b0";
when "10" & x"5f4" => data <= x"fc";
when "10" & x"5f5" => data <= x"ad";
when "10" & x"5f6" => data <= x"bb";
when "10" & x"5f7" => data <= x"fc";
when "10" & x"5f8" => data <= x"29";
when "10" & x"5f9" => data <= x"e3";
when "10" & x"5fa" => data <= x"8d";
when "10" & x"5fb" => data <= x"bb";
when "10" & x"5fc" => data <= x"fc";
when "10" & x"5fd" => data <= x"a9";
when "10" & x"5fe" => data <= x"1c";
when "10" & x"5ff" => data <= x"8d";
when "10" & x"600" => data <= x"be";
when "10" & x"601" => data <= x"fc";
when "10" & x"602" => data <= x"a9";
when "10" & x"603" => data <= x"00";
when "10" & x"604" => data <= x"8d";
when "10" & x"605" => data <= x"ba";
when "10" & x"606" => data <= x"fc";
when "10" & x"607" => data <= x"60";
when "10" & x"608" => data <= x"20";
when "10" & x"609" => data <= x"00";
when "10" & x"60a" => data <= x"a0";
when "10" & x"60b" => data <= x"ff";
when "10" & x"60c" => data <= x"55";
when "10" & x"60d" => data <= x"73";
when "10" & x"60e" => data <= x"65";
when "10" & x"60f" => data <= x"72";
when "10" & x"610" => data <= x"20";
when "10" & x"611" => data <= x"70";
when "10" & x"612" => data <= x"6f";
when "10" & x"613" => data <= x"72";
when "10" & x"614" => data <= x"74";
when "10" & x"615" => data <= x"20";
when "10" & x"616" => data <= x"63";
when "10" & x"617" => data <= x"6f";
when "10" & x"618" => data <= x"6e";
when "10" & x"619" => data <= x"66";
when "10" & x"61a" => data <= x"6c";
when "10" & x"61b" => data <= x"69";
when "10" & x"61c" => data <= x"63";
when "10" & x"61d" => data <= x"74";
when "10" & x"61e" => data <= x"00";
when "10" & x"61f" => data <= x"ad";
when "10" & x"620" => data <= x"02";
when "10" & x"621" => data <= x"0d";
when "10" & x"622" => data <= x"c9";
when "10" & x"623" => data <= x"54";
when "10" & x"624" => data <= x"d0";
when "10" & x"625" => data <= x"04";
when "10" & x"626" => data <= x"20";
when "10" & x"627" => data <= x"b0";
when "10" & x"628" => data <= x"a5";
when "10" & x"629" => data <= x"60";
when "10" & x"62a" => data <= x"20";
when "10" & x"62b" => data <= x"43";
when "10" & x"62c" => data <= x"a6";
when "10" & x"62d" => data <= x"d0";
when "10" & x"62e" => data <= x"fa";
when "10" & x"62f" => data <= x"20";
when "10" & x"630" => data <= x"eb";
when "10" & x"631" => data <= x"a9";
when "10" & x"632" => data <= x"c9";
when "10" & x"633" => data <= x"ff";
when "10" & x"634" => data <= x"f0";
when "10" & x"635" => data <= x"f3";
when "10" & x"636" => data <= x"20";
when "10" & x"637" => data <= x"00";
when "10" & x"638" => data <= x"a0";
when "10" & x"639" => data <= x"ff";
when "10" & x"63a" => data <= x"43";
when "10" & x"63b" => data <= x"61";
when "10" & x"63c" => data <= x"72";
when "10" & x"63d" => data <= x"64";
when "10" & x"63e" => data <= x"3f";
when "10" & x"63f" => data <= x"00";
when "10" & x"640" => data <= x"20";
when "10" & x"641" => data <= x"76";
when "10" & x"642" => data <= x"a1";
when "10" & x"643" => data <= x"20";
when "10" & x"644" => data <= x"b0";
when "10" & x"645" => data <= x"a5";
when "10" & x"646" => data <= x"a0";
when "10" & x"647" => data <= x"0a";
when "10" & x"648" => data <= x"20";
when "10" & x"649" => data <= x"da";
when "10" & x"64a" => data <= x"a2";
when "10" & x"64b" => data <= x"a9";
when "10" & x"64c" => data <= x"40";
when "10" & x"64d" => data <= x"20";
when "10" & x"64e" => data <= x"6f";
when "10" & x"64f" => data <= x"a5";
when "10" & x"650" => data <= x"a9";
when "10" & x"651" => data <= x"95";
when "10" & x"652" => data <= x"8d";
when "10" & x"653" => data <= x"48";
when "10" & x"654" => data <= x"0d";
when "10" & x"655" => data <= x"20";
when "10" & x"656" => data <= x"32";
when "10" & x"657" => data <= x"a3";
when "10" & x"658" => data <= x"c9";
when "10" & x"659" => data <= x"01";
when "10" & x"65a" => data <= x"f0";
when "10" & x"65b" => data <= x"03";
when "10" & x"65c" => data <= x"4c";
when "10" & x"65d" => data <= x"07";
when "10" & x"65e" => data <= x"a7";
when "10" & x"65f" => data <= x"a9";
when "10" & x"660" => data <= x"01";
when "10" & x"661" => data <= x"8d";
when "10" & x"662" => data <= x"4f";
when "10" & x"663" => data <= x"0d";
when "10" & x"664" => data <= x"a9";
when "10" & x"665" => data <= x"48";
when "10" & x"666" => data <= x"20";
when "10" & x"667" => data <= x"6f";
when "10" & x"668" => data <= x"a5";
when "10" & x"669" => data <= x"a9";
when "10" & x"66a" => data <= x"01";
when "10" & x"66b" => data <= x"8d";
when "10" & x"66c" => data <= x"46";
when "10" & x"66d" => data <= x"0d";
when "10" & x"66e" => data <= x"a9";
when "10" & x"66f" => data <= x"aa";
when "10" & x"670" => data <= x"8d";
when "10" & x"671" => data <= x"47";
when "10" & x"672" => data <= x"0d";
when "10" & x"673" => data <= x"a9";
when "10" & x"674" => data <= x"87";
when "10" & x"675" => data <= x"8d";
when "10" & x"676" => data <= x"48";
when "10" & x"677" => data <= x"0d";
when "10" & x"678" => data <= x"20";
when "10" & x"679" => data <= x"32";
when "10" & x"67a" => data <= x"a3";
when "10" & x"67b" => data <= x"c9";
when "10" & x"67c" => data <= x"01";
when "10" & x"67d" => data <= x"f0";
when "10" & x"67e" => data <= x"20";
when "10" & x"67f" => data <= x"a9";
when "10" & x"680" => data <= x"02";
when "10" & x"681" => data <= x"8d";
when "10" & x"682" => data <= x"4f";
when "10" & x"683" => data <= x"0d";
when "10" & x"684" => data <= x"a9";
when "10" & x"685" => data <= x"41";
when "10" & x"686" => data <= x"20";
when "10" & x"687" => data <= x"6f";
when "10" & x"688" => data <= x"a5";
when "10" & x"689" => data <= x"20";
when "10" & x"68a" => data <= x"32";
when "10" & x"68b" => data <= x"a3";
when "10" & x"68c" => data <= x"c9";
when "10" & x"68d" => data <= x"02";
when "10" & x"68e" => data <= x"90";
when "10" & x"68f" => data <= x"03";
when "10" & x"690" => data <= x"4c";
when "10" & x"691" => data <= x"07";
when "10" & x"692" => data <= x"a7";
when "10" & x"693" => data <= x"c9";
when "10" & x"694" => data <= x"00";
when "10" & x"695" => data <= x"d0";
when "10" & x"696" => data <= x"ed";
when "10" & x"697" => data <= x"a9";
when "10" & x"698" => data <= x"02";
when "10" & x"699" => data <= x"8d";
when "10" & x"69a" => data <= x"4f";
when "10" & x"69b" => data <= x"0d";
when "10" & x"69c" => data <= x"4c";
when "10" & x"69d" => data <= x"e7";
when "10" & x"69e" => data <= x"a6";
when "10" & x"69f" => data <= x"20";
when "10" & x"6a0" => data <= x"e2";
when "10" & x"6a1" => data <= x"a1";
when "10" & x"6a2" => data <= x"20";
when "10" & x"6a3" => data <= x"e2";
when "10" & x"6a4" => data <= x"a1";
when "10" & x"6a5" => data <= x"20";
when "10" & x"6a6" => data <= x"e2";
when "10" & x"6a7" => data <= x"a1";
when "10" & x"6a8" => data <= x"20";
when "10" & x"6a9" => data <= x"e2";
when "10" & x"6aa" => data <= x"a1";
when "10" & x"6ab" => data <= x"a9";
when "10" & x"6ac" => data <= x"77";
when "10" & x"6ad" => data <= x"20";
when "10" & x"6ae" => data <= x"6f";
when "10" & x"6af" => data <= x"a5";
when "10" & x"6b0" => data <= x"20";
when "10" & x"6b1" => data <= x"32";
when "10" & x"6b2" => data <= x"a3";
when "10" & x"6b3" => data <= x"a9";
when "10" & x"6b4" => data <= x"69";
when "10" & x"6b5" => data <= x"20";
when "10" & x"6b6" => data <= x"6f";
when "10" & x"6b7" => data <= x"a5";
when "10" & x"6b8" => data <= x"a9";
when "10" & x"6b9" => data <= x"40";
when "10" & x"6ba" => data <= x"8d";
when "10" & x"6bb" => data <= x"44";
when "10" & x"6bc" => data <= x"0d";
when "10" & x"6bd" => data <= x"20";
when "10" & x"6be" => data <= x"32";
when "10" & x"6bf" => data <= x"a3";
when "10" & x"6c0" => data <= x"c9";
when "10" & x"6c1" => data <= x"00";
when "10" & x"6c2" => data <= x"d0";
when "10" & x"6c3" => data <= x"e7";
when "10" & x"6c4" => data <= x"a9";
when "10" & x"6c5" => data <= x"7a";
when "10" & x"6c6" => data <= x"20";
when "10" & x"6c7" => data <= x"6f";
when "10" & x"6c8" => data <= x"a5";
when "10" & x"6c9" => data <= x"20";
when "10" & x"6ca" => data <= x"32";
when "10" & x"6cb" => data <= x"a3";
when "10" & x"6cc" => data <= x"c9";
when "10" & x"6cd" => data <= x"00";
when "10" & x"6ce" => data <= x"d0";
when "10" & x"6cf" => data <= x"37";
when "10" & x"6d0" => data <= x"20";
when "10" & x"6d1" => data <= x"e2";
when "10" & x"6d2" => data <= x"a1";
when "10" & x"6d3" => data <= x"29";
when "10" & x"6d4" => data <= x"40";
when "10" & x"6d5" => data <= x"48";
when "10" & x"6d6" => data <= x"20";
when "10" & x"6d7" => data <= x"e2";
when "10" & x"6d8" => data <= x"a1";
when "10" & x"6d9" => data <= x"20";
when "10" & x"6da" => data <= x"e2";
when "10" & x"6db" => data <= x"a1";
when "10" & x"6dc" => data <= x"20";
when "10" & x"6dd" => data <= x"e2";
when "10" & x"6de" => data <= x"a1";
when "10" & x"6df" => data <= x"68";
when "10" & x"6e0" => data <= x"d0";
when "10" & x"6e1" => data <= x"05";
when "10" & x"6e2" => data <= x"a9";
when "10" & x"6e3" => data <= x"02";
when "10" & x"6e4" => data <= x"8d";
when "10" & x"6e5" => data <= x"4f";
when "10" & x"6e6" => data <= x"0d";
when "10" & x"6e7" => data <= x"a9";
when "10" & x"6e8" => data <= x"50";
when "10" & x"6e9" => data <= x"20";
when "10" & x"6ea" => data <= x"6f";
when "10" & x"6eb" => data <= x"a5";
when "10" & x"6ec" => data <= x"a9";
when "10" & x"6ed" => data <= x"02";
when "10" & x"6ee" => data <= x"8d";
when "10" & x"6ef" => data <= x"46";
when "10" & x"6f0" => data <= x"0d";
when "10" & x"6f1" => data <= x"20";
when "10" & x"6f2" => data <= x"32";
when "10" & x"6f3" => data <= x"a3";
when "10" & x"6f4" => data <= x"d0";
when "10" & x"6f5" => data <= x"2e";
when "10" & x"6f6" => data <= x"a9";
when "10" & x"6f7" => data <= x"54";
when "10" & x"6f8" => data <= x"8d";
when "10" & x"6f9" => data <= x"02";
when "10" & x"6fa" => data <= x"0d";
when "10" & x"6fb" => data <= x"ad";
when "10" & x"6fc" => data <= x"03";
when "10" & x"6fd" => data <= x"0d";
when "10" & x"6fe" => data <= x"8d";
when "10" & x"6ff" => data <= x"04";
when "10" & x"700" => data <= x"0d";
when "10" & x"701" => data <= x"20";
when "10" & x"702" => data <= x"80";
when "10" & x"703" => data <= x"a1";
when "10" & x"704" => data <= x"a9";
when "10" & x"705" => data <= x"ff";
when "10" & x"706" => data <= x"60";
when "10" & x"707" => data <= x"ae";
when "10" & x"708" => data <= x"03";
when "10" & x"709" => data <= x"0d";
when "10" & x"70a" => data <= x"e8";
when "10" & x"70b" => data <= x"e0";
when "10" & x"70c" => data <= x"02";
when "10" & x"70d" => data <= x"b0";
when "10" & x"70e" => data <= x"09";
when "10" & x"70f" => data <= x"8e";
when "10" & x"710" => data <= x"03";
when "10" & x"711" => data <= x"0d";
when "10" & x"712" => data <= x"20";
when "10" & x"713" => data <= x"8d";
when "10" & x"714" => data <= x"a5";
when "10" & x"715" => data <= x"4c";
when "10" & x"716" => data <= x"46";
when "10" & x"717" => data <= x"a6";
when "10" & x"718" => data <= x"a9";
when "10" & x"719" => data <= x"00";
when "10" & x"71a" => data <= x"8d";
when "10" & x"71b" => data <= x"03";
when "10" & x"71c" => data <= x"0d";
when "10" & x"71d" => data <= x"20";
when "10" & x"71e" => data <= x"8d";
when "10" & x"71f" => data <= x"a5";
when "10" & x"720" => data <= x"8d";
when "10" & x"721" => data <= x"02";
when "10" & x"722" => data <= x"0d";
when "10" & x"723" => data <= x"60";
when "10" & x"724" => data <= x"20";
when "10" & x"725" => data <= x"1f";
when "10" & x"726" => data <= x"a0";
when "10" & x"727" => data <= x"ff";
when "10" & x"728" => data <= x"53";
when "10" & x"729" => data <= x"65";
when "10" & x"72a" => data <= x"74";
when "10" & x"72b" => data <= x"20";
when "10" & x"72c" => data <= x"62";
when "10" & x"72d" => data <= x"6c";
when "10" & x"72e" => data <= x"6f";
when "10" & x"72f" => data <= x"63";
when "10" & x"730" => data <= x"6b";
when "10" & x"731" => data <= x"20";
when "10" & x"732" => data <= x"6c";
when "10" & x"733" => data <= x"65";
when "10" & x"734" => data <= x"6e";
when "10" & x"735" => data <= x"20";
when "10" & x"736" => data <= x"65";
when "10" & x"737" => data <= x"72";
when "10" & x"738" => data <= x"72";
when "10" & x"739" => data <= x"6f";
when "10" & x"73a" => data <= x"72";
when "10" & x"73b" => data <= x"20";
when "10" & x"73c" => data <= x"00";
when "10" & x"73d" => data <= x"a9";
when "10" & x"73e" => data <= x"51";
when "10" & x"73f" => data <= x"20";
when "10" & x"740" => data <= x"6f";
when "10" & x"741" => data <= x"a5";
when "10" & x"742" => data <= x"60";
when "10" & x"743" => data <= x"20";
when "10" & x"744" => data <= x"21";
when "10" & x"745" => data <= x"aa";
when "10" & x"746" => data <= x"20";
when "10" & x"747" => data <= x"32";
when "10" & x"748" => data <= x"a3";
when "10" & x"749" => data <= x"d0";
when "10" & x"74a" => data <= x"07";
when "10" & x"74b" => data <= x"20";
when "10" & x"74c" => data <= x"a1";
when "10" & x"74d" => data <= x"a3";
when "10" & x"74e" => data <= x"20";
when "10" & x"74f" => data <= x"83";
when "10" & x"750" => data <= x"aa";
when "10" & x"751" => data <= x"60";
when "10" & x"752" => data <= x"20";
when "10" & x"753" => data <= x"1f";
when "10" & x"754" => data <= x"a0";
when "10" & x"755" => data <= x"c5";
when "10" & x"756" => data <= x"4d";
when "10" & x"757" => data <= x"4d";
when "10" & x"758" => data <= x"43";
when "10" & x"759" => data <= x"20";
when "10" & x"75a" => data <= x"52";
when "10" & x"75b" => data <= x"65";
when "10" & x"75c" => data <= x"61";
when "10" & x"75d" => data <= x"64";
when "10" & x"75e" => data <= x"20";
when "10" & x"75f" => data <= x"66";
when "10" & x"760" => data <= x"61";
when "10" & x"761" => data <= x"75";
when "10" & x"762" => data <= x"6c";
when "10" & x"763" => data <= x"74";
when "10" & x"764" => data <= x"20";
when "10" & x"765" => data <= x"00";
when "10" & x"766" => data <= x"20";
when "10" & x"767" => data <= x"21";
when "10" & x"768" => data <= x"aa";
when "10" & x"769" => data <= x"20";
when "10" & x"76a" => data <= x"32";
when "10" & x"76b" => data <= x"a3";
when "10" & x"76c" => data <= x"d0";
when "10" & x"76d" => data <= x"07";
when "10" & x"76e" => data <= x"20";
when "10" & x"76f" => data <= x"92";
when "10" & x"770" => data <= x"a4";
when "10" & x"771" => data <= x"20";
when "10" & x"772" => data <= x"83";
when "10" & x"773" => data <= x"aa";
when "10" & x"774" => data <= x"60";
when "10" & x"775" => data <= x"20";
when "10" & x"776" => data <= x"1f";
when "10" & x"777" => data <= x"a0";
when "10" & x"778" => data <= x"c5";
when "10" & x"779" => data <= x"4d";
when "10" & x"77a" => data <= x"4d";
when "10" & x"77b" => data <= x"43";
when "10" & x"77c" => data <= x"20";
when "10" & x"77d" => data <= x"57";
when "10" & x"77e" => data <= x"72";
when "10" & x"77f" => data <= x"69";
when "10" & x"780" => data <= x"74";
when "10" & x"781" => data <= x"65";
when "10" & x"782" => data <= x"20";
when "10" & x"783" => data <= x"66";
when "10" & x"784" => data <= x"61";
when "10" & x"785" => data <= x"75";
when "10" & x"786" => data <= x"6c";
when "10" & x"787" => data <= x"74";
when "10" & x"788" => data <= x"20";
when "10" & x"789" => data <= x"00";
when "10" & x"78a" => data <= x"20";
when "10" & x"78b" => data <= x"76";
when "10" & x"78c" => data <= x"a1";
when "10" & x"78d" => data <= x"a9";
when "10" & x"78e" => data <= x"00";
when "10" & x"78f" => data <= x"8d";
when "10" & x"790" => data <= x"d6";
when "10" & x"791" => data <= x"10";
when "10" & x"792" => data <= x"85";
when "10" & x"793" => data <= x"a0";
when "10" & x"794" => data <= x"a9";
when "10" & x"795" => data <= x"0e";
when "10" & x"796" => data <= x"85";
when "10" & x"797" => data <= x"a1";
when "10" & x"798" => data <= x"60";
when "10" & x"799" => data <= x"20";
when "10" & x"79a" => data <= x"8a";
when "10" & x"79b" => data <= x"a7";
when "10" & x"79c" => data <= x"20";
when "10" & x"79d" => data <= x"3d";
when "10" & x"79e" => data <= x"a7";
when "10" & x"79f" => data <= x"20";
when "10" & x"7a0" => data <= x"43";
when "10" & x"7a1" => data <= x"a7";
when "10" & x"7a2" => data <= x"20";
when "10" & x"7a3" => data <= x"be";
when "10" & x"7a4" => data <= x"a3";
when "10" & x"7a5" => data <= x"e6";
when "10" & x"7a6" => data <= x"a1";
when "10" & x"7a7" => data <= x"20";
when "10" & x"7a8" => data <= x"be";
when "10" & x"7a9" => data <= x"a3";
when "10" & x"7aa" => data <= x"a0";
when "10" & x"7ab" => data <= x"02";
when "10" & x"7ac" => data <= x"20";
when "10" & x"7ad" => data <= x"da";
when "10" & x"7ae" => data <= x"a2";
when "10" & x"7af" => data <= x"4c";
when "10" & x"7b0" => data <= x"80";
when "10" & x"7b1" => data <= x"a1";
when "10" & x"7b2" => data <= x"20";
when "10" & x"7b3" => data <= x"8a";
when "10" & x"7b4" => data <= x"a7";
when "10" & x"7b5" => data <= x"a9";
when "10" & x"7b6" => data <= x"58";
when "10" & x"7b7" => data <= x"20";
when "10" & x"7b8" => data <= x"3f";
when "10" & x"7b9" => data <= x"a7";
when "10" & x"7ba" => data <= x"20";
when "10" & x"7bb" => data <= x"66";
when "10" & x"7bc" => data <= x"a7";
when "10" & x"7bd" => data <= x"20";
when "10" & x"7be" => data <= x"15";
when "10" & x"7bf" => data <= x"a5";
when "10" & x"7c0" => data <= x"e6";
when "10" & x"7c1" => data <= x"a1";
when "10" & x"7c2" => data <= x"20";
when "10" & x"7c3" => data <= x"15";
when "10" & x"7c4" => data <= x"a5";
when "10" & x"7c5" => data <= x"20";
when "10" & x"7c6" => data <= x"b4";
when "10" & x"7c7" => data <= x"a4";
when "10" & x"7c8" => data <= x"4c";
when "10" & x"7c9" => data <= x"80";
when "10" & x"7ca" => data <= x"a1";
when "10" & x"7cb" => data <= x"60";
when "10" & x"7cc" => data <= x"20";
when "10" & x"7cd" => data <= x"76";
when "10" & x"7ce" => data <= x"a1";
when "10" & x"7cf" => data <= x"20";
when "10" & x"7d0" => data <= x"d5";
when "10" & x"7d1" => data <= x"a7";
when "10" & x"7d2" => data <= x"4c";
when "10" & x"7d3" => data <= x"80";
when "10" & x"7d4" => data <= x"a1";
when "10" & x"7d5" => data <= x"ae";
when "10" & x"7d6" => data <= x"27";
when "10" & x"7d7" => data <= x"0d";
when "10" & x"7d8" => data <= x"f0";
when "10" & x"7d9" => data <= x"f1";
when "10" & x"7da" => data <= x"a9";
when "10" & x"7db" => data <= x"01";
when "10" & x"7dc" => data <= x"20";
when "10" & x"7dd" => data <= x"98";
when "10" & x"7de" => data <= x"a0";
when "10" & x"7df" => data <= x"ae";
when "10" & x"7e0" => data <= x"27";
when "10" & x"7e1" => data <= x"0d";
when "10" & x"7e2" => data <= x"2c";
when "10" & x"7e3" => data <= x"28";
when "10" & x"7e4" => data <= x"0d";
when "10" & x"7e5" => data <= x"10";
when "10" & x"7e6" => data <= x"01";
when "10" & x"7e7" => data <= x"e8";
when "10" & x"7e8" => data <= x"8e";
when "10" & x"7e9" => data <= x"27";
when "10" & x"7ea" => data <= x"0d";
when "10" & x"7eb" => data <= x"20";
when "10" & x"7ec" => data <= x"3d";
when "10" & x"7ed" => data <= x"a7";
when "10" & x"7ee" => data <= x"ae";
when "10" & x"7ef" => data <= x"27";
when "10" & x"7f0" => data <= x"0d";
when "10" & x"7f1" => data <= x"e0";
when "10" & x"7f2" => data <= x"03";
when "10" & x"7f3" => data <= x"b0";
when "10" & x"7f4" => data <= x"09";
when "10" & x"7f5" => data <= x"ad";
when "10" & x"7f6" => data <= x"29";
when "10" & x"7f7" => data <= x"0d";
when "10" & x"7f8" => data <= x"d0";
when "10" & x"7f9" => data <= x"46";
when "10" & x"7fa" => data <= x"e0";
when "10" & x"7fb" => data <= x"01";
when "10" & x"7fc" => data <= x"f0";
when "10" & x"7fd" => data <= x"39";
when "10" & x"7fe" => data <= x"2c";
when "10" & x"7ff" => data <= x"28";
when "10" & x"800" => data <= x"0d";
when "10" & x"801" => data <= x"10";
when "10" & x"802" => data <= x"0e";
when "10" & x"803" => data <= x"20";
when "10" & x"804" => data <= x"43";
when "10" & x"805" => data <= x"a7";
when "10" & x"806" => data <= x"a0";
when "10" & x"807" => data <= x"00";
when "10" & x"808" => data <= x"8c";
when "10" & x"809" => data <= x"28";
when "10" & x"80a" => data <= x"0d";
when "10" & x"80b" => data <= x"20";
when "10" & x"80c" => data <= x"da";
when "10" & x"80d" => data <= x"a2";
when "10" & x"80e" => data <= x"4c";
when "10" & x"80f" => data <= x"19";
when "10" & x"810" => data <= x"a8";
when "10" & x"811" => data <= x"20";
when "10" & x"812" => data <= x"43";
when "10" & x"813" => data <= x"a7";
when "10" & x"814" => data <= x"20";
when "10" & x"815" => data <= x"be";
when "10" & x"816" => data <= x"a3";
when "10" & x"817" => data <= x"e6";
when "10" & x"818" => data <= x"a1";
when "10" & x"819" => data <= x"20";
when "10" & x"81a" => data <= x"be";
when "10" & x"81b" => data <= x"a3";
when "10" & x"81c" => data <= x"e6";
when "10" & x"81d" => data <= x"a1";
when "10" & x"81e" => data <= x"a0";
when "10" & x"81f" => data <= x"02";
when "10" & x"820" => data <= x"20";
when "10" & x"821" => data <= x"da";
when "10" & x"822" => data <= x"a2";
when "10" & x"823" => data <= x"20";
when "10" & x"824" => data <= x"61";
when "10" & x"825" => data <= x"aa";
when "10" & x"826" => data <= x"ae";
when "10" & x"827" => data <= x"27";
when "10" & x"828" => data <= x"0d";
when "10" & x"829" => data <= x"ca";
when "10" & x"82a" => data <= x"ca";
when "10" & x"82b" => data <= x"f0";
when "10" & x"82c" => data <= x"9e";
when "10" & x"82d" => data <= x"8e";
when "10" & x"82e" => data <= x"27";
when "10" & x"82f" => data <= x"0d";
when "10" & x"830" => data <= x"e0";
when "10" & x"831" => data <= x"03";
when "10" & x"832" => data <= x"b0";
when "10" & x"833" => data <= x"dd";
when "10" & x"834" => data <= x"4c";
when "10" & x"835" => data <= x"f5";
when "10" & x"836" => data <= x"a7";
when "10" & x"837" => data <= x"20";
when "10" & x"838" => data <= x"43";
when "10" & x"839" => data <= x"a7";
when "10" & x"83a" => data <= x"20";
when "10" & x"83b" => data <= x"be";
when "10" & x"83c" => data <= x"a3";
when "10" & x"83d" => data <= x"4c";
when "10" & x"83e" => data <= x"6d";
when "10" & x"83f" => data <= x"a8";
when "10" & x"840" => data <= x"20";
when "10" & x"841" => data <= x"43";
when "10" & x"842" => data <= x"a7";
when "10" & x"843" => data <= x"2c";
when "10" & x"844" => data <= x"28";
when "10" & x"845" => data <= x"0d";
when "10" & x"846" => data <= x"10";
when "10" & x"847" => data <= x"0b";
when "10" & x"848" => data <= x"a0";
when "10" & x"849" => data <= x"00";
when "10" & x"84a" => data <= x"8c";
when "10" & x"84b" => data <= x"28";
when "10" & x"84c" => data <= x"0d";
when "10" & x"84d" => data <= x"20";
when "10" & x"84e" => data <= x"da";
when "10" & x"84f" => data <= x"a2";
when "10" & x"850" => data <= x"4c";
when "10" & x"851" => data <= x"5d";
when "10" & x"852" => data <= x"a8";
when "10" & x"853" => data <= x"ce";
when "10" & x"854" => data <= x"27";
when "10" & x"855" => data <= x"0d";
when "10" & x"856" => data <= x"f0";
when "10" & x"857" => data <= x"05";
when "10" & x"858" => data <= x"20";
when "10" & x"859" => data <= x"be";
when "10" & x"85a" => data <= x"a3";
when "10" & x"85b" => data <= x"e6";
when "10" & x"85c" => data <= x"a1";
when "10" & x"85d" => data <= x"20";
when "10" & x"85e" => data <= x"f5";
when "10" & x"85f" => data <= x"a3";
when "10" & x"860" => data <= x"98";
when "10" & x"861" => data <= x"49";
when "10" & x"862" => data <= x"ff";
when "10" & x"863" => data <= x"a8";
when "10" & x"864" => data <= x"c8";
when "10" & x"865" => data <= x"20";
when "10" & x"866" => data <= x"da";
when "10" & x"867" => data <= x"a2";
when "10" & x"868" => data <= x"ad";
when "10" & x"869" => data <= x"27";
when "10" & x"86a" => data <= x"0d";
when "10" & x"86b" => data <= x"d0";
when "10" & x"86c" => data <= x"05";
when "10" & x"86d" => data <= x"a0";
when "10" & x"86e" => data <= x"00";
when "10" & x"86f" => data <= x"20";
when "10" & x"870" => data <= x"da";
when "10" & x"871" => data <= x"a2";
when "10" & x"872" => data <= x"a0";
when "10" & x"873" => data <= x"02";
when "10" & x"874" => data <= x"4c";
when "10" & x"875" => data <= x"da";
when "10" & x"876" => data <= x"a2";
when "10" & x"877" => data <= x"60";
when "10" & x"878" => data <= x"20";
when "10" & x"879" => data <= x"76";
when "10" & x"87a" => data <= x"a1";
when "10" & x"87b" => data <= x"20";
when "10" & x"87c" => data <= x"81";
when "10" & x"87d" => data <= x"a8";
when "10" & x"87e" => data <= x"4c";
when "10" & x"87f" => data <= x"80";
when "10" & x"880" => data <= x"a1";
when "10" & x"881" => data <= x"ae";
when "10" & x"882" => data <= x"27";
when "10" & x"883" => data <= x"0d";
when "10" & x"884" => data <= x"f0";
when "10" & x"885" => data <= x"f1";
when "10" & x"886" => data <= x"a9";
when "10" & x"887" => data <= x"00";
when "10" & x"888" => data <= x"20";
when "10" & x"889" => data <= x"98";
when "10" & x"88a" => data <= x"a0";
when "10" & x"88b" => data <= x"a9";
when "10" & x"88c" => data <= x"58";
when "10" & x"88d" => data <= x"20";
when "10" & x"88e" => data <= x"3f";
when "10" & x"88f" => data <= x"a7";
when "10" & x"890" => data <= x"ae";
when "10" & x"891" => data <= x"27";
when "10" & x"892" => data <= x"0d";
when "10" & x"893" => data <= x"2c";
when "10" & x"894" => data <= x"28";
when "10" & x"895" => data <= x"0d";
when "10" & x"896" => data <= x"10";
when "10" & x"897" => data <= x"3a";
when "10" & x"898" => data <= x"a9";
when "10" & x"899" => data <= x"00";
when "10" & x"89a" => data <= x"8d";
when "10" & x"89b" => data <= x"28";
when "10" & x"89c" => data <= x"0d";
when "10" & x"89d" => data <= x"a9";
when "10" & x"89e" => data <= x"ff";
when "10" & x"89f" => data <= x"8d";
when "10" & x"8a0" => data <= x"82";
when "10" & x"8a1" => data <= x"10";
when "10" & x"8a2" => data <= x"a9";
when "10" & x"8a3" => data <= x"51";
when "10" & x"8a4" => data <= x"8d";
when "10" & x"8a5" => data <= x"43";
when "10" & x"8a6" => data <= x"0d";
when "10" & x"8a7" => data <= x"20";
when "10" & x"8a8" => data <= x"43";
when "10" & x"8a9" => data <= x"a7";
when "10" & x"8aa" => data <= x"20";
when "10" & x"8ab" => data <= x"62";
when "10" & x"8ac" => data <= x"a4";
when "10" & x"8ad" => data <= x"a0";
when "10" & x"8ae" => data <= x"00";
when "10" & x"8af" => data <= x"20";
when "10" & x"8b0" => data <= x"da";
when "10" & x"8b1" => data <= x"a2";
when "10" & x"8b2" => data <= x"a0";
when "10" & x"8b3" => data <= x"02";
when "10" & x"8b4" => data <= x"20";
when "10" & x"8b5" => data <= x"da";
when "10" & x"8b6" => data <= x"a2";
when "10" & x"8b7" => data <= x"a9";
when "10" & x"8b8" => data <= x"58";
when "10" & x"8b9" => data <= x"8d";
when "10" & x"8ba" => data <= x"43";
when "10" & x"8bb" => data <= x"0d";
when "10" & x"8bc" => data <= x"20";
when "10" & x"8bd" => data <= x"66";
when "10" & x"8be" => data <= x"a7";
when "10" & x"8bf" => data <= x"20";
when "10" & x"8c0" => data <= x"51";
when "10" & x"8c1" => data <= x"a5";
when "10" & x"8c2" => data <= x"20";
when "10" & x"8c3" => data <= x"15";
when "10" & x"8c4" => data <= x"a5";
when "10" & x"8c5" => data <= x"20";
when "10" & x"8c6" => data <= x"b4";
when "10" & x"8c7" => data <= x"a4";
when "10" & x"8c8" => data <= x"ce";
when "10" & x"8c9" => data <= x"27";
when "10" & x"8ca" => data <= x"0d";
when "10" & x"8cb" => data <= x"f0";
when "10" & x"8cc" => data <= x"aa";
when "10" & x"8cd" => data <= x"e6";
when "10" & x"8ce" => data <= x"a1";
when "10" & x"8cf" => data <= x"20";
when "10" & x"8d0" => data <= x"61";
when "10" & x"8d1" => data <= x"aa";
when "10" & x"8d2" => data <= x"ae";
when "10" & x"8d3" => data <= x"27";
when "10" & x"8d4" => data <= x"0d";
when "10" & x"8d5" => data <= x"f0";
when "10" & x"8d6" => data <= x"46";
when "10" & x"8d7" => data <= x"ca";
when "10" & x"8d8" => data <= x"d0";
when "10" & x"8d9" => data <= x"2b";
when "10" & x"8da" => data <= x"a9";
when "10" & x"8db" => data <= x"ff";
when "10" & x"8dc" => data <= x"8d";
when "10" & x"8dd" => data <= x"82";
when "10" & x"8de" => data <= x"10";
when "10" & x"8df" => data <= x"a9";
when "10" & x"8e0" => data <= x"51";
when "10" & x"8e1" => data <= x"8d";
when "10" & x"8e2" => data <= x"43";
when "10" & x"8e3" => data <= x"0d";
when "10" & x"8e4" => data <= x"20";
when "10" & x"8e5" => data <= x"43";
when "10" & x"8e6" => data <= x"a7";
when "10" & x"8e7" => data <= x"a0";
when "10" & x"8e8" => data <= x"00";
when "10" & x"8e9" => data <= x"20";
when "10" & x"8ea" => data <= x"da";
when "10" & x"8eb" => data <= x"a2";
when "10" & x"8ec" => data <= x"20";
when "10" & x"8ed" => data <= x"62";
when "10" & x"8ee" => data <= x"a4";
when "10" & x"8ef" => data <= x"a0";
when "10" & x"8f0" => data <= x"02";
when "10" & x"8f1" => data <= x"20";
when "10" & x"8f2" => data <= x"da";
when "10" & x"8f3" => data <= x"a2";
when "10" & x"8f4" => data <= x"a9";
when "10" & x"8f5" => data <= x"58";
when "10" & x"8f6" => data <= x"8d";
when "10" & x"8f7" => data <= x"43";
when "10" & x"8f8" => data <= x"0d";
when "10" & x"8f9" => data <= x"20";
when "10" & x"8fa" => data <= x"66";
when "10" & x"8fb" => data <= x"a7";
when "10" & x"8fc" => data <= x"20";
when "10" & x"8fd" => data <= x"15";
when "10" & x"8fe" => data <= x"a5";
when "10" & x"8ff" => data <= x"20";
when "10" & x"900" => data <= x"51";
when "10" & x"901" => data <= x"a5";
when "10" & x"902" => data <= x"4c";
when "10" & x"903" => data <= x"b4";
when "10" & x"904" => data <= x"a4";
when "10" & x"905" => data <= x"20";
when "10" & x"906" => data <= x"66";
when "10" & x"907" => data <= x"a7";
when "10" & x"908" => data <= x"20";
when "10" & x"909" => data <= x"15";
when "10" & x"90a" => data <= x"a5";
when "10" & x"90b" => data <= x"e6";
when "10" & x"90c" => data <= x"a1";
when "10" & x"90d" => data <= x"20";
when "10" & x"90e" => data <= x"15";
when "10" & x"90f" => data <= x"a5";
when "10" & x"910" => data <= x"e6";
when "10" & x"911" => data <= x"a1";
when "10" & x"912" => data <= x"20";
when "10" & x"913" => data <= x"b4";
when "10" & x"914" => data <= x"a4";
when "10" & x"915" => data <= x"ce";
when "10" & x"916" => data <= x"27";
when "10" & x"917" => data <= x"0d";
when "10" & x"918" => data <= x"ce";
when "10" & x"919" => data <= x"27";
when "10" & x"91a" => data <= x"0d";
when "10" & x"91b" => data <= x"d0";
when "10" & x"91c" => data <= x"b2";
when "10" & x"91d" => data <= x"60";
when "10" & x"91e" => data <= x"a9";
when "10" & x"91f" => data <= x"51";
when "10" & x"920" => data <= x"20";
when "10" & x"921" => data <= x"6f";
when "10" & x"922" => data <= x"a5";
when "10" & x"923" => data <= x"60";
when "10" & x"924" => data <= x"20";
when "10" & x"925" => data <= x"76";
when "10" & x"926" => data <= x"a1";
when "10" & x"927" => data <= x"20";
when "10" & x"928" => data <= x"43";
when "10" & x"929" => data <= x"a7";
when "10" & x"92a" => data <= x"a9";
when "10" & x"92b" => data <= x"5f";
when "10" & x"92c" => data <= x"85";
when "10" & x"92d" => data <= x"a0";
when "10" & x"92e" => data <= x"a9";
when "10" & x"92f" => data <= x"0d";
when "10" & x"930" => data <= x"85";
when "10" & x"931" => data <= x"a1";
when "10" & x"932" => data <= x"a9";
when "10" & x"933" => data <= x"08";
when "10" & x"934" => data <= x"8d";
when "10" & x"935" => data <= x"29";
when "10" & x"936" => data <= x"0d";
when "10" & x"937" => data <= x"20";
when "10" & x"938" => data <= x"f5";
when "10" & x"939" => data <= x"a3";
when "10" & x"93a" => data <= x"a0";
when "10" & x"93b" => data <= x"f8";
when "10" & x"93c" => data <= x"20";
when "10" & x"93d" => data <= x"da";
when "10" & x"93e" => data <= x"a2";
when "10" & x"93f" => data <= x"a9";
when "10" & x"940" => data <= x"67";
when "10" & x"941" => data <= x"85";
when "10" & x"942" => data <= x"a0";
when "10" & x"943" => data <= x"a9";
when "10" & x"944" => data <= x"08";
when "10" & x"945" => data <= x"8d";
when "10" & x"946" => data <= x"29";
when "10" & x"947" => data <= x"0d";
when "10" & x"948" => data <= x"20";
when "10" & x"949" => data <= x"f5";
when "10" & x"94a" => data <= x"a3";
when "10" & x"94b" => data <= x"a0";
when "10" & x"94c" => data <= x"fa";
when "10" & x"94d" => data <= x"20";
when "10" & x"94e" => data <= x"da";
when "10" & x"94f" => data <= x"a2";
when "10" & x"950" => data <= x"ad";
when "10" & x"951" => data <= x"4f";
when "10" & x"952" => data <= x"0d";
when "10" & x"953" => data <= x"c9";
when "10" & x"954" => data <= x"02";
when "10" & x"955" => data <= x"f0";
when "10" & x"956" => data <= x"1e";
when "10" & x"957" => data <= x"18";
when "10" & x"958" => data <= x"ad";
when "10" & x"959" => data <= x"47";
when "10" & x"95a" => data <= x"0d";
when "10" & x"95b" => data <= x"69";
when "10" & x"95c" => data <= x"90";
when "10" & x"95d" => data <= x"8d";
when "10" & x"95e" => data <= x"47";
when "10" & x"95f" => data <= x"0d";
when "10" & x"960" => data <= x"ad";
when "10" & x"961" => data <= x"46";
when "10" & x"962" => data <= x"0d";
when "10" & x"963" => data <= x"69";
when "10" & x"964" => data <= x"01";
when "10" & x"965" => data <= x"8d";
when "10" & x"966" => data <= x"46";
when "10" & x"967" => data <= x"0d";
when "10" & x"968" => data <= x"90";
when "10" & x"969" => data <= x"08";
when "10" & x"96a" => data <= x"ee";
when "10" & x"96b" => data <= x"45";
when "10" & x"96c" => data <= x"0d";
when "10" & x"96d" => data <= x"f0";
when "10" & x"96e" => data <= x"03";
when "10" & x"96f" => data <= x"ee";
when "10" & x"970" => data <= x"44";
when "10" & x"971" => data <= x"0d";
when "10" & x"972" => data <= x"4c";
when "10" & x"973" => data <= x"8b";
when "10" & x"974" => data <= x"a9";
when "10" & x"975" => data <= x"18";
when "10" & x"976" => data <= x"ad";
when "10" & x"977" => data <= x"46";
when "10" & x"978" => data <= x"0d";
when "10" & x"979" => data <= x"69";
when "10" & x"97a" => data <= x"20";
when "10" & x"97b" => data <= x"8d";
when "10" & x"97c" => data <= x"46";
when "10" & x"97d" => data <= x"0d";
when "10" & x"97e" => data <= x"ad";
when "10" & x"97f" => data <= x"45";
when "10" & x"980" => data <= x"0d";
when "10" & x"981" => data <= x"69";
when "10" & x"982" => data <= x"03";
when "10" & x"983" => data <= x"8d";
when "10" & x"984" => data <= x"45";
when "10" & x"985" => data <= x"0d";
when "10" & x"986" => data <= x"90";
when "10" & x"987" => data <= x"03";
when "10" & x"988" => data <= x"ee";
when "10" & x"989" => data <= x"44";
when "10" & x"98a" => data <= x"0d";
when "10" & x"98b" => data <= x"4c";
when "10" & x"98c" => data <= x"80";
when "10" & x"98d" => data <= x"a1";
when "10" & x"98e" => data <= x"60";
when "10" & x"98f" => data <= x"a9";
when "10" & x"990" => data <= x"00";
when "10" & x"991" => data <= x"8d";
when "10" & x"992" => data <= x"50";
when "10" & x"993" => data <= x"0d";
when "10" & x"994" => data <= x"8d";
when "10" & x"995" => data <= x"51";
when "10" & x"996" => data <= x"0d";
when "10" & x"997" => data <= x"20";
when "10" & x"998" => data <= x"eb";
when "10" & x"999" => data <= x"a9";
when "10" & x"99a" => data <= x"a9";
when "10" & x"99b" => data <= x"7a";
when "10" & x"99c" => data <= x"20";
when "10" & x"99d" => data <= x"f4";
when "10" & x"99e" => data <= x"ff";
when "10" & x"99f" => data <= x"8a";
when "10" & x"9a0" => data <= x"30";
when "10" & x"9a1" => data <= x"0d";
when "10" & x"9a2" => data <= x"c9";
when "10" & x"9a3" => data <= x"51";
when "10" & x"9a4" => data <= x"f0";
when "10" & x"9a5" => data <= x"04";
when "10" & x"9a6" => data <= x"c9";
when "10" & x"9a7" => data <= x"42";
when "10" & x"9a8" => data <= x"d0";
when "10" & x"9a9" => data <= x"e4";
when "10" & x"9aa" => data <= x"a9";
when "10" & x"9ab" => data <= x"78";
when "10" & x"9ac" => data <= x"20";
when "10" & x"9ad" => data <= x"f4";
when "10" & x"9ae" => data <= x"ff";
when "10" & x"9af" => data <= x"8e";
when "10" & x"9b0" => data <= x"52";
when "10" & x"9b1" => data <= x"0d";
when "10" & x"9b2" => data <= x"4c";
when "10" & x"9b3" => data <= x"20";
when "10" & x"9b4" => data <= x"93";
when "10" & x"9b5" => data <= x"ae";
when "10" & x"9b6" => data <= x"4a";
when "10" & x"9b7" => data <= x"0d";
when "10" & x"9b8" => data <= x"18";
when "10" & x"9b9" => data <= x"a9";
when "10" & x"9ba" => data <= x"80";
when "10" & x"9bb" => data <= x"2a";
when "10" & x"9bc" => data <= x"2a";
when "10" & x"9bd" => data <= x"ca";
when "10" & x"9be" => data <= x"d0";
when "10" & x"9bf" => data <= x"fb";
when "10" & x"9c0" => data <= x"8d";
when "10" & x"9c1" => data <= x"4b";
when "10" & x"9c2" => data <= x"0d";
when "10" & x"9c3" => data <= x"0a";
when "10" & x"9c4" => data <= x"8d";
when "10" & x"9c5" => data <= x"4e";
when "10" & x"9c6" => data <= x"0d";
when "10" & x"9c7" => data <= x"aa";
when "10" & x"9c8" => data <= x"18";
when "10" & x"9c9" => data <= x"6d";
when "10" & x"9ca" => data <= x"4b";
when "10" & x"9cb" => data <= x"0d";
when "10" & x"9cc" => data <= x"8d";
when "10" & x"9cd" => data <= x"4c";
when "10" & x"9ce" => data <= x"0d";
when "10" & x"9cf" => data <= x"8a";
when "10" & x"9d0" => data <= x"49";
when "10" & x"9d1" => data <= x"ff";
when "10" & x"9d2" => data <= x"8d";
when "10" & x"9d3" => data <= x"4d";
when "10" & x"9d4" => data <= x"0d";
when "10" & x"9d5" => data <= x"60";
when "10" & x"9d6" => data <= x"ad";
when "10" & x"9d7" => data <= x"b2";
when "10" & x"9d8" => data <= x"fc";
when "10" & x"9d9" => data <= x"8d";
when "10" & x"9da" => data <= x"50";
when "10" & x"9db" => data <= x"0d";
when "10" & x"9dc" => data <= x"49";
when "10" & x"9dd" => data <= x"ff";
when "10" & x"9de" => data <= x"8d";
when "10" & x"9df" => data <= x"51";
when "10" & x"9e0" => data <= x"0d";
when "10" & x"9e1" => data <= x"ad";
when "10" & x"9e2" => data <= x"b0";
when "10" & x"9e3" => data <= x"fc";
when "10" & x"9e4" => data <= x"4d";
when "10" & x"9e5" => data <= x"51";
when "10" & x"9e6" => data <= x"0d";
when "10" & x"9e7" => data <= x"8d";
when "10" & x"9e8" => data <= x"51";
when "10" & x"9e9" => data <= x"0d";
when "10" & x"9ea" => data <= x"60";
when "10" & x"9eb" => data <= x"a9";
when "10" & x"9ec" => data <= x"00";
when "10" & x"9ed" => data <= x"8d";
when "10" & x"9ee" => data <= x"3f";
when "10" & x"9ef" => data <= x"0d";
when "10" & x"9f0" => data <= x"8d";
when "10" & x"9f1" => data <= x"4f";
when "10" & x"9f2" => data <= x"0d";
when "10" & x"9f3" => data <= x"a2";
when "10" & x"9f4" => data <= x"04";
when "10" & x"9f5" => data <= x"8e";
when "10" & x"9f6" => data <= x"4a";
when "10" & x"9f7" => data <= x"0d";
when "10" & x"9f8" => data <= x"20";
when "10" & x"9f9" => data <= x"b5";
when "10" & x"9fa" => data <= x"a9";
when "10" & x"9fb" => data <= x"20";
when "10" & x"9fc" => data <= x"43";
when "10" & x"9fd" => data <= x"a6";
when "10" & x"9fe" => data <= x"c9";
when "10" & x"9ff" => data <= x"ff";
when "10" & x"a00" => data <= x"f0";
when "10" & x"a01" => data <= x"1e";
when "10" & x"a02" => data <= x"ae";
when "10" & x"a03" => data <= x"4a";
when "10" & x"a04" => data <= x"0d";
when "10" & x"a05" => data <= x"ca";
when "10" & x"a06" => data <= x"d0";
when "10" & x"a07" => data <= x"ed";
when "10" & x"a08" => data <= x"8e";
when "10" & x"a09" => data <= x"4a";
when "10" & x"a0a" => data <= x"0d";
when "10" & x"a0b" => data <= x"8e";
when "10" & x"a0c" => data <= x"4f";
when "10" & x"a0d" => data <= x"0d";
when "10" & x"a0e" => data <= x"ad";
when "10" & x"a0f" => data <= x"3f";
when "10" & x"a10" => data <= x"0d";
when "10" & x"a11" => data <= x"d0";
when "10" & x"a12" => data <= x"0a";
when "10" & x"a13" => data <= x"a2";
when "10" & x"a14" => data <= x"08";
when "10" & x"a15" => data <= x"8e";
when "10" & x"a16" => data <= x"3f";
when "10" & x"a17" => data <= x"0d";
when "10" & x"a18" => data <= x"a2";
when "10" & x"a19" => data <= x"01";
when "10" & x"a1a" => data <= x"4c";
when "10" & x"a1b" => data <= x"f5";
when "10" & x"a1c" => data <= x"a9";
when "10" & x"a1d" => data <= x"20";
when "10" & x"a1e" => data <= x"07";
when "10" & x"a1f" => data <= x"a7";
when "10" & x"a20" => data <= x"60";
when "10" & x"a21" => data <= x"ad";
when "10" & x"a22" => data <= x"4f";
when "10" & x"a23" => data <= x"0d";
when "10" & x"a24" => data <= x"c9";
when "10" & x"a25" => data <= x"02";
when "10" & x"a26" => data <= x"d0";
when "10" & x"a27" => data <= x"20";
when "10" & x"a28" => data <= x"ad";
when "10" & x"a29" => data <= x"26";
when "10" & x"a2a" => data <= x"0d";
when "10" & x"a2b" => data <= x"18";
when "10" & x"a2c" => data <= x"ac";
when "10" & x"a2d" => data <= x"25";
when "10" & x"a2e" => data <= x"0d";
when "10" & x"a2f" => data <= x"ae";
when "10" & x"a30" => data <= x"24";
when "10" & x"a31" => data <= x"0d";
when "10" & x"a32" => data <= x"ad";
when "10" & x"a33" => data <= x"23";
when "10" & x"a34" => data <= x"0d";
when "10" & x"a35" => data <= x"0a";
when "10" & x"a36" => data <= x"8d";
when "10" & x"a37" => data <= x"24";
when "10" & x"a38" => data <= x"0d";
when "10" & x"a39" => data <= x"8a";
when "10" & x"a3a" => data <= x"2a";
when "10" & x"a3b" => data <= x"8d";
when "10" & x"a3c" => data <= x"25";
when "10" & x"a3d" => data <= x"0d";
when "10" & x"a3e" => data <= x"98";
when "10" & x"a3f" => data <= x"2a";
when "10" & x"a40" => data <= x"8d";
when "10" & x"a41" => data <= x"26";
when "10" & x"a42" => data <= x"0d";
when "10" & x"a43" => data <= x"a9";
when "10" & x"a44" => data <= x"00";
when "10" & x"a45" => data <= x"8d";
when "10" & x"a46" => data <= x"23";
when "10" & x"a47" => data <= x"0d";
when "10" & x"a48" => data <= x"ad";
when "10" & x"a49" => data <= x"23";
when "10" & x"a4a" => data <= x"0d";
when "10" & x"a4b" => data <= x"8d";
when "10" & x"a4c" => data <= x"47";
when "10" & x"a4d" => data <= x"0d";
when "10" & x"a4e" => data <= x"ad";
when "10" & x"a4f" => data <= x"24";
when "10" & x"a50" => data <= x"0d";
when "10" & x"a51" => data <= x"8d";
when "10" & x"a52" => data <= x"46";
when "10" & x"a53" => data <= x"0d";
when "10" & x"a54" => data <= x"ad";
when "10" & x"a55" => data <= x"25";
when "10" & x"a56" => data <= x"0d";
when "10" & x"a57" => data <= x"8d";
when "10" & x"a58" => data <= x"45";
when "10" & x"a59" => data <= x"0d";
when "10" & x"a5a" => data <= x"ad";
when "10" & x"a5b" => data <= x"26";
when "10" & x"a5c" => data <= x"0d";
when "10" & x"a5d" => data <= x"8d";
when "10" & x"a5e" => data <= x"44";
when "10" & x"a5f" => data <= x"0d";
when "10" & x"a60" => data <= x"60";
when "10" & x"a61" => data <= x"18";
when "10" & x"a62" => data <= x"a9";
when "10" & x"a63" => data <= x"01";
when "10" & x"a64" => data <= x"6d";
when "10" & x"a65" => data <= x"23";
when "10" & x"a66" => data <= x"0d";
when "10" & x"a67" => data <= x"8d";
when "10" & x"a68" => data <= x"23";
when "10" & x"a69" => data <= x"0d";
when "10" & x"a6a" => data <= x"ad";
when "10" & x"a6b" => data <= x"24";
when "10" & x"a6c" => data <= x"0d";
when "10" & x"a6d" => data <= x"69";
when "10" & x"a6e" => data <= x"00";
when "10" & x"a6f" => data <= x"8d";
when "10" & x"a70" => data <= x"24";
when "10" & x"a71" => data <= x"0d";
when "10" & x"a72" => data <= x"ad";
when "10" & x"a73" => data <= x"25";
when "10" & x"a74" => data <= x"0d";
when "10" & x"a75" => data <= x"69";
when "10" & x"a76" => data <= x"00";
when "10" & x"a77" => data <= x"8d";
when "10" & x"a78" => data <= x"25";
when "10" & x"a79" => data <= x"0d";
when "10" & x"a7a" => data <= x"ad";
when "10" & x"a7b" => data <= x"26";
when "10" & x"a7c" => data <= x"0d";
when "10" & x"a7d" => data <= x"69";
when "10" & x"a7e" => data <= x"00";
when "10" & x"a7f" => data <= x"8d";
when "10" & x"a80" => data <= x"26";
when "10" & x"a81" => data <= x"0d";
when "10" & x"a82" => data <= x"60";
when "10" & x"a83" => data <= x"ad";
when "10" & x"a84" => data <= x"4f";
when "10" & x"a85" => data <= x"0d";
when "10" & x"a86" => data <= x"c9";
when "10" & x"a87" => data <= x"02";
when "10" & x"a88" => data <= x"d0";
when "10" & x"a89" => data <= x"1c";
when "10" & x"a8a" => data <= x"ac";
when "10" & x"a8b" => data <= x"24";
when "10" & x"a8c" => data <= x"0d";
when "10" & x"a8d" => data <= x"ae";
when "10" & x"a8e" => data <= x"25";
when "10" & x"a8f" => data <= x"0d";
when "10" & x"a90" => data <= x"ad";
when "10" & x"a91" => data <= x"26";
when "10" & x"a92" => data <= x"0d";
when "10" & x"a93" => data <= x"4a";
when "10" & x"a94" => data <= x"8d";
when "10" & x"a95" => data <= x"25";
when "10" & x"a96" => data <= x"0d";
when "10" & x"a97" => data <= x"8a";
when "10" & x"a98" => data <= x"6a";
when "10" & x"a99" => data <= x"8d";
when "10" & x"a9a" => data <= x"24";
when "10" & x"a9b" => data <= x"0d";
when "10" & x"a9c" => data <= x"98";
when "10" & x"a9d" => data <= x"6a";
when "10" & x"a9e" => data <= x"8d";
when "10" & x"a9f" => data <= x"23";
when "10" & x"aa0" => data <= x"0d";
when "10" & x"aa1" => data <= x"a9";
when "10" & x"aa2" => data <= x"00";
when "10" & x"aa3" => data <= x"8d";
when "10" & x"aa4" => data <= x"26";
when "10" & x"aa5" => data <= x"0d";
when "10" & x"aa6" => data <= x"60";
when "10" & x"aa7" => data <= x"ad";
when "10" & x"aa8" => data <= x"05";
when "10" & x"aa9" => data <= x"0d";
when "10" & x"aaa" => data <= x"c9";
when "10" & x"aab" => data <= x"54";
when "10" & x"aac" => data <= x"d0";
when "10" & x"aad" => data <= x"15";
when "10" & x"aae" => data <= x"ad";
when "10" & x"aaf" => data <= x"06";
when "10" & x"ab0" => data <= x"0d";
when "10" & x"ab1" => data <= x"4d";
when "10" & x"ab2" => data <= x"0a";
when "10" & x"ab3" => data <= x"0d";
when "10" & x"ab4" => data <= x"c9";
when "10" & x"ab5" => data <= x"ff";
when "10" & x"ab6" => data <= x"d0";
when "10" & x"ab7" => data <= x"0b";
when "10" & x"ab8" => data <= x"ad";
when "10" & x"ab9" => data <= x"07";
when "10" & x"aba" => data <= x"0d";
when "10" & x"abb" => data <= x"4d";
when "10" & x"abc" => data <= x"0b";
when "10" & x"abd" => data <= x"0d";
when "10" & x"abe" => data <= x"c9";
when "10" & x"abf" => data <= x"ff";
when "10" & x"ac0" => data <= x"d0";
when "10" & x"ac1" => data <= x"01";
when "10" & x"ac2" => data <= x"60";
when "10" & x"ac3" => data <= x"a2";
when "10" & x"ac4" => data <= x"0b";
when "10" & x"ac5" => data <= x"bd";
when "10" & x"ac6" => data <= x"22";
when "10" & x"ac7" => data <= x"0d";
when "10" & x"ac8" => data <= x"48";
when "10" & x"ac9" => data <= x"ca";
when "10" & x"aca" => data <= x"d0";
when "10" & x"acb" => data <= x"f9";
when "10" & x"acc" => data <= x"a9";
when "10" & x"acd" => data <= x"00";
when "10" & x"ace" => data <= x"8d";
when "10" & x"acf" => data <= x"23";
when "10" & x"ad0" => data <= x"0d";
when "10" & x"ad1" => data <= x"8d";
when "10" & x"ad2" => data <= x"24";
when "10" & x"ad3" => data <= x"0d";
when "10" & x"ad4" => data <= x"8d";
when "10" & x"ad5" => data <= x"25";
when "10" & x"ad6" => data <= x"0d";
when "10" & x"ad7" => data <= x"8d";
when "10" & x"ad8" => data <= x"26";
when "10" & x"ad9" => data <= x"0d";
when "10" & x"ada" => data <= x"20";
when "10" & x"adb" => data <= x"99";
when "10" & x"adc" => data <= x"a7";
when "10" & x"add" => data <= x"a9";
when "10" & x"ade" => data <= x"dd";
when "10" & x"adf" => data <= x"8d";
when "10" & x"ae0" => data <= x"82";
when "10" & x"ae1" => data <= x"10";
when "10" & x"ae2" => data <= x"20";
when "10" & x"ae3" => data <= x"00";
when "10" & x"ae4" => data <= x"ab";
when "10" & x"ae5" => data <= x"f0";
when "10" & x"ae6" => data <= x"29";
when "10" & x"ae7" => data <= x"a9";
when "10" & x"ae8" => data <= x"00";
when "10" & x"ae9" => data <= x"8d";
when "10" & x"aea" => data <= x"06";
when "10" & x"aeb" => data <= x"0d";
when "10" & x"aec" => data <= x"8d";
when "10" & x"aed" => data <= x"07";
when "10" & x"aee" => data <= x"0d";
when "10" & x"aef" => data <= x"8d";
when "10" & x"af0" => data <= x"08";
when "10" & x"af1" => data <= x"0d";
when "10" & x"af2" => data <= x"8d";
when "10" & x"af3" => data <= x"09";
when "10" & x"af4" => data <= x"0d";
when "10" & x"af5" => data <= x"a9";
when "10" & x"af6" => data <= x"ff";
when "10" & x"af7" => data <= x"8d";
when "10" & x"af8" => data <= x"0a";
when "10" & x"af9" => data <= x"0d";
when "10" & x"afa" => data <= x"8d";
when "10" & x"afb" => data <= x"0b";
when "10" & x"afc" => data <= x"0d";
when "10" & x"afd" => data <= x"4c";
when "10" & x"afe" => data <= x"e0";
when "10" & x"aff" => data <= x"ac";
when "10" & x"b00" => data <= x"ad";
when "10" & x"b01" => data <= x"fe";
when "10" & x"b02" => data <= x"0f";
when "10" & x"b03" => data <= x"c9";
when "10" & x"b04" => data <= x"55";
when "10" & x"b05" => data <= x"d0";
when "10" & x"b06" => data <= x"05";
when "10" & x"b07" => data <= x"ad";
when "10" & x"b08" => data <= x"ff";
when "10" & x"b09" => data <= x"0f";
when "10" & x"b0a" => data <= x"c9";
when "10" & x"b0b" => data <= x"aa";
when "10" & x"b0c" => data <= x"60";
when "10" & x"b0d" => data <= x"4c";
when "10" & x"b0e" => data <= x"f1";
when "10" & x"b0f" => data <= x"ac";
when "10" & x"b10" => data <= x"ad";
when "10" & x"b11" => data <= x"00";
when "10" & x"b12" => data <= x"0e";
when "10" & x"b13" => data <= x"c9";
when "10" & x"b14" => data <= x"eb";
when "10" & x"b15" => data <= x"d0";
when "10" & x"b16" => data <= x"0e";
when "10" & x"b17" => data <= x"ad";
when "10" & x"b18" => data <= x"02";
when "10" & x"b19" => data <= x"0e";
when "10" & x"b1a" => data <= x"c9";
when "10" & x"b1b" => data <= x"90";
when "10" & x"b1c" => data <= x"d0";
when "10" & x"b1d" => data <= x"07";
when "10" & x"b1e" => data <= x"ad";
when "10" & x"b1f" => data <= x"0c";
when "10" & x"b20" => data <= x"0e";
when "10" & x"b21" => data <= x"c9";
when "10" & x"b22" => data <= x"02";
when "10" & x"b23" => data <= x"f0";
when "10" & x"b24" => data <= x"26";
when "10" & x"b25" => data <= x"ad";
when "10" & x"b26" => data <= x"c6";
when "10" & x"b27" => data <= x"0f";
when "10" & x"b28" => data <= x"8d";
when "10" & x"b29" => data <= x"23";
when "10" & x"b2a" => data <= x"0d";
when "10" & x"b2b" => data <= x"ad";
when "10" & x"b2c" => data <= x"c7";
when "10" & x"b2d" => data <= x"0f";
when "10" & x"b2e" => data <= x"8d";
when "10" & x"b2f" => data <= x"24";
when "10" & x"b30" => data <= x"0d";
when "10" & x"b31" => data <= x"ad";
when "10" & x"b32" => data <= x"c8";
when "10" & x"b33" => data <= x"0f";
when "10" & x"b34" => data <= x"8d";
when "10" & x"b35" => data <= x"25";
when "10" & x"b36" => data <= x"0d";
when "10" & x"b37" => data <= x"ad";
when "10" & x"b38" => data <= x"c9";
when "10" & x"b39" => data <= x"0f";
when "10" & x"b3a" => data <= x"8d";
when "10" & x"b3b" => data <= x"26";
when "10" & x"b3c" => data <= x"0d";
when "10" & x"b3d" => data <= x"20";
when "10" & x"b3e" => data <= x"0a";
when "10" & x"b3f" => data <= x"ad";
when "10" & x"b40" => data <= x"20";
when "10" & x"b41" => data <= x"99";
when "10" & x"b42" => data <= x"a7";
when "10" & x"b43" => data <= x"20";
when "10" & x"b44" => data <= x"23";
when "10" & x"b45" => data <= x"ad";
when "10" & x"b46" => data <= x"20";
when "10" & x"b47" => data <= x"00";
when "10" & x"b48" => data <= x"ab";
when "10" & x"b49" => data <= x"d0";
when "10" & x"b4a" => data <= x"c2";
when "10" & x"b4b" => data <= x"ad";
when "10" & x"b4c" => data <= x"0b";
when "10" & x"b4d" => data <= x"0e";
when "10" & x"b4e" => data <= x"d0";
when "10" & x"b4f" => data <= x"bd";
when "10" & x"b50" => data <= x"ad";
when "10" & x"b51" => data <= x"0c";
when "10" & x"b52" => data <= x"0e";
when "10" & x"b53" => data <= x"c9";
when "10" & x"b54" => data <= x"02";
when "10" & x"b55" => data <= x"d0";
when "10" & x"b56" => data <= x"b6";
when "10" & x"b57" => data <= x"a2";
when "10" & x"b58" => data <= x"05";
when "10" & x"b59" => data <= x"0e";
when "10" & x"b5a" => data <= x"11";
when "10" & x"b5b" => data <= x"0e";
when "10" & x"b5c" => data <= x"2e";
when "10" & x"b5d" => data <= x"12";
when "10" & x"b5e" => data <= x"0e";
when "10" & x"b5f" => data <= x"ca";
when "10" & x"b60" => data <= x"d0";
when "10" & x"b61" => data <= x"f7";
when "10" & x"b62" => data <= x"4e";
when "10" & x"b63" => data <= x"12";
when "10" & x"b64" => data <= x"0e";
when "10" & x"b65" => data <= x"ad";
when "10" & x"b66" => data <= x"12";
when "10" & x"b67" => data <= x"0e";
when "10" & x"b68" => data <= x"8d";
when "10" & x"b69" => data <= x"39";
when "10" & x"b6a" => data <= x"0d";
when "10" & x"b6b" => data <= x"ad";
when "10" & x"b6c" => data <= x"0d";
when "10" & x"b6d" => data <= x"0e";
when "10" & x"b6e" => data <= x"8d";
when "10" & x"b6f" => data <= x"29";
when "10" & x"b70" => data <= x"0d";
when "10" & x"b71" => data <= x"18";
when "10" & x"b72" => data <= x"ad";
when "10" & x"b73" => data <= x"0e";
when "10" & x"b74" => data <= x"0e";
when "10" & x"b75" => data <= x"6d";
when "10" & x"b76" => data <= x"23";
when "10" & x"b77" => data <= x"0d";
when "10" & x"b78" => data <= x"8d";
when "10" & x"b79" => data <= x"23";
when "10" & x"b7a" => data <= x"0d";
when "10" & x"b7b" => data <= x"ad";
when "10" & x"b7c" => data <= x"0f";
when "10" & x"b7d" => data <= x"0e";
when "10" & x"b7e" => data <= x"6d";
when "10" & x"b7f" => data <= x"24";
when "10" & x"b80" => data <= x"0d";
when "10" & x"b81" => data <= x"8d";
when "10" & x"b82" => data <= x"24";
when "10" & x"b83" => data <= x"0d";
when "10" & x"b84" => data <= x"a9";
when "10" & x"b85" => data <= x"00";
when "10" & x"b86" => data <= x"6d";
when "10" & x"b87" => data <= x"25";
when "10" & x"b88" => data <= x"0d";
when "10" & x"b89" => data <= x"8d";
when "10" & x"b8a" => data <= x"25";
when "10" & x"b8b" => data <= x"0d";
when "10" & x"b8c" => data <= x"a9";
when "10" & x"b8d" => data <= x"00";
when "10" & x"b8e" => data <= x"6d";
when "10" & x"b8f" => data <= x"26";
when "10" & x"b90" => data <= x"0d";
when "10" & x"b91" => data <= x"8d";
when "10" & x"b92" => data <= x"26";
when "10" & x"b93" => data <= x"0d";
when "10" & x"b94" => data <= x"90";
when "10" & x"b95" => data <= x"03";
when "10" & x"b96" => data <= x"4c";
when "10" & x"b97" => data <= x"f1";
when "10" & x"b98" => data <= x"ac";
when "10" & x"b99" => data <= x"ad";
when "10" & x"b9a" => data <= x"11";
when "10" & x"b9b" => data <= x"0e";
when "10" & x"b9c" => data <= x"0d";
when "10" & x"b9d" => data <= x"12";
when "10" & x"b9e" => data <= x"0e";
when "10" & x"b9f" => data <= x"8d";
when "10" & x"ba0" => data <= x"22";
when "10" & x"ba1" => data <= x"0d";
when "10" & x"ba2" => data <= x"f0";
when "10" & x"ba3" => data <= x"14";
when "10" & x"ba4" => data <= x"a9";
when "10" & x"ba5" => data <= x"00";
when "10" & x"ba6" => data <= x"8d";
when "10" & x"ba7" => data <= x"26";
when "10" & x"ba8" => data <= x"0e";
when "10" & x"ba9" => data <= x"8d";
when "10" & x"baa" => data <= x"27";
when "10" & x"bab" => data <= x"0e";
when "10" & x"bac" => data <= x"ad";
when "10" & x"bad" => data <= x"16";
when "10" & x"bae" => data <= x"0e";
when "10" & x"baf" => data <= x"8d";
when "10" & x"bb0" => data <= x"24";
when "10" & x"bb1" => data <= x"0e";
when "10" & x"bb2" => data <= x"ad";
when "10" & x"bb3" => data <= x"17";
when "10" & x"bb4" => data <= x"0e";
when "10" & x"bb5" => data <= x"8d";
when "10" & x"bb6" => data <= x"25";
when "10" & x"bb7" => data <= x"0e";
when "10" & x"bb8" => data <= x"ae";
when "10" & x"bb9" => data <= x"10";
when "10" & x"bba" => data <= x"0e";
when "10" & x"bbb" => data <= x"18";
when "10" & x"bbc" => data <= x"ad";
when "10" & x"bbd" => data <= x"23";
when "10" & x"bbe" => data <= x"0d";
when "10" & x"bbf" => data <= x"6d";
when "10" & x"bc0" => data <= x"24";
when "10" & x"bc1" => data <= x"0e";
when "10" & x"bc2" => data <= x"8d";
when "10" & x"bc3" => data <= x"23";
when "10" & x"bc4" => data <= x"0d";
when "10" & x"bc5" => data <= x"ad";
when "10" & x"bc6" => data <= x"24";
when "10" & x"bc7" => data <= x"0d";
when "10" & x"bc8" => data <= x"6d";
when "10" & x"bc9" => data <= x"25";
when "10" & x"bca" => data <= x"0e";
when "10" & x"bcb" => data <= x"8d";
when "10" & x"bcc" => data <= x"24";
when "10" & x"bcd" => data <= x"0d";
when "10" & x"bce" => data <= x"ad";
when "10" & x"bcf" => data <= x"25";
when "10" & x"bd0" => data <= x"0d";
when "10" & x"bd1" => data <= x"6d";
when "10" & x"bd2" => data <= x"26";
when "10" & x"bd3" => data <= x"0e";
when "10" & x"bd4" => data <= x"8d";
when "10" & x"bd5" => data <= x"25";
when "10" & x"bd6" => data <= x"0d";
when "10" & x"bd7" => data <= x"ad";
when "10" & x"bd8" => data <= x"26";
when "10" & x"bd9" => data <= x"0d";
when "10" & x"bda" => data <= x"6d";
when "10" & x"bdb" => data <= x"27";
when "10" & x"bdc" => data <= x"0e";
when "10" & x"bdd" => data <= x"8d";
when "10" & x"bde" => data <= x"26";
when "10" & x"bdf" => data <= x"0d";
when "10" & x"be0" => data <= x"90";
when "10" & x"be1" => data <= x"03";
when "10" & x"be2" => data <= x"4c";
when "10" & x"be3" => data <= x"0d";
when "10" & x"be4" => data <= x"ab";
when "10" & x"be5" => data <= x"ca";
when "10" & x"be6" => data <= x"d0";
when "10" & x"be7" => data <= x"d3";
when "10" & x"be8" => data <= x"a9";
when "10" & x"be9" => data <= x"20";
when "10" & x"bea" => data <= x"8d";
when "10" & x"beb" => data <= x"21";
when "10" & x"bec" => data <= x"0d";
when "10" & x"bed" => data <= x"20";
when "10" & x"bee" => data <= x"0a";
when "10" & x"bef" => data <= x"ad";
when "10" & x"bf0" => data <= x"20";
when "10" & x"bf1" => data <= x"99";
when "10" & x"bf2" => data <= x"a7";
when "10" & x"bf3" => data <= x"20";
when "10" & x"bf4" => data <= x"23";
when "10" & x"bf5" => data <= x"ad";
when "10" & x"bf6" => data <= x"a9";
when "10" & x"bf7" => data <= x"00";
when "10" & x"bf8" => data <= x"85";
when "10" & x"bf9" => data <= x"a2";
when "10" & x"bfa" => data <= x"a9";
when "10" & x"bfb" => data <= x"0e";
when "10" & x"bfc" => data <= x"85";
when "10" & x"bfd" => data <= x"a3";
when "10" & x"bfe" => data <= x"a0";
when "10" & x"bff" => data <= x"0b";
when "10" & x"c00" => data <= x"b1";
when "10" & x"c01" => data <= x"a2";
when "10" & x"c02" => data <= x"29";
when "10" & x"c03" => data <= x"0f";
when "10" & x"c04" => data <= x"d0";
when "10" & x"c05" => data <= x"10";
when "10" & x"c06" => data <= x"a0";
when "10" & x"c07" => data <= x"00";
when "10" & x"c08" => data <= x"b1";
when "10" & x"c09" => data <= x"a2";
when "10" & x"c0a" => data <= x"d9";
when "10" & x"c0b" => data <= x"70";
when "10" & x"c0c" => data <= x"0d";
when "10" & x"c0d" => data <= x"d0";
when "10" & x"c0e" => data <= x"07";
when "10" & x"c0f" => data <= x"c8";
when "10" & x"c10" => data <= x"c0";
when "10" & x"c11" => data <= x"0b";
when "10" & x"c12" => data <= x"f0";
when "10" & x"c13" => data <= x"38";
when "10" & x"c14" => data <= x"d0";
when "10" & x"c15" => data <= x"f2";
when "10" & x"c16" => data <= x"18";
when "10" & x"c17" => data <= x"a5";
when "10" & x"c18" => data <= x"a2";
when "10" & x"c19" => data <= x"69";
when "10" & x"c1a" => data <= x"20";
when "10" & x"c1b" => data <= x"85";
when "10" & x"c1c" => data <= x"a2";
when "10" & x"c1d" => data <= x"d0";
when "10" & x"c1e" => data <= x"df";
when "10" & x"c1f" => data <= x"e6";
when "10" & x"c20" => data <= x"a3";
when "10" & x"c21" => data <= x"a5";
when "10" & x"c22" => data <= x"a3";
when "10" & x"c23" => data <= x"c9";
when "10" & x"c24" => data <= x"0f";
when "10" & x"c25" => data <= x"f0";
when "10" & x"c26" => data <= x"d7";
when "10" & x"c27" => data <= x"ce";
when "10" & x"c28" => data <= x"21";
when "10" & x"c29" => data <= x"0d";
when "10" & x"c2a" => data <= x"ad";
when "10" & x"c2b" => data <= x"21";
when "10" & x"c2c" => data <= x"0d";
when "10" & x"c2d" => data <= x"f0";
when "10" & x"c2e" => data <= x"08";
when "10" & x"c2f" => data <= x"a9";
when "10" & x"c30" => data <= x"01";
when "10" & x"c31" => data <= x"20";
when "10" & x"c32" => data <= x"3c";
when "10" & x"c33" => data <= x"ad";
when "10" & x"c34" => data <= x"4c";
when "10" & x"c35" => data <= x"ed";
when "10" & x"c36" => data <= x"ab";
when "10" & x"c37" => data <= x"20";
when "10" & x"c38" => data <= x"00";
when "10" & x"c39" => data <= x"a0";
when "10" & x"c3a" => data <= x"ff";
when "10" & x"c3b" => data <= x"49";
when "10" & x"c3c" => data <= x"6d";
when "10" & x"c3d" => data <= x"61";
when "10" & x"c3e" => data <= x"67";
when "10" & x"c3f" => data <= x"65";
when "10" & x"c40" => data <= x"20";
when "10" & x"c41" => data <= x"6e";
when "10" & x"c42" => data <= x"6f";
when "10" & x"c43" => data <= x"74";
when "10" & x"c44" => data <= x"20";
when "10" & x"c45" => data <= x"66";
when "10" & x"c46" => data <= x"6f";
when "10" & x"c47" => data <= x"75";
when "10" & x"c48" => data <= x"6e";
when "10" & x"c49" => data <= x"64";
when "10" & x"c4a" => data <= x"21";
when "10" & x"c4b" => data <= x"00";
when "10" & x"c4c" => data <= x"a0";
when "10" & x"c4d" => data <= x"14";
when "10" & x"c4e" => data <= x"b1";
when "10" & x"c4f" => data <= x"a2";
when "10" & x"c50" => data <= x"8d";
when "10" & x"c51" => data <= x"2c";
when "10" & x"c52" => data <= x"0d";
when "10" & x"c53" => data <= x"c8";
when "10" & x"c54" => data <= x"b1";
when "10" & x"c55" => data <= x"a2";
when "10" & x"c56" => data <= x"8d";
when "10" & x"c57" => data <= x"2d";
when "10" & x"c58" => data <= x"0d";
when "10" & x"c59" => data <= x"a0";
when "10" & x"c5a" => data <= x"1b";
when "10" & x"c5b" => data <= x"b1";
when "10" & x"c5c" => data <= x"a2";
when "10" & x"c5d" => data <= x"48";
when "10" & x"c5e" => data <= x"88";
when "10" & x"c5f" => data <= x"b1";
when "10" & x"c60" => data <= x"a2";
when "10" & x"c61" => data <= x"38";
when "10" & x"c62" => data <= x"e9";
when "10" & x"c63" => data <= x"02";
when "10" & x"c64" => data <= x"8d";
when "10" & x"c65" => data <= x"2a";
when "10" & x"c66" => data <= x"0d";
when "10" & x"c67" => data <= x"68";
when "10" & x"c68" => data <= x"e9";
when "10" & x"c69" => data <= x"00";
when "10" & x"c6a" => data <= x"8d";
when "10" & x"c6b" => data <= x"2b";
when "10" & x"c6c" => data <= x"0d";
when "10" & x"c6d" => data <= x"ad";
when "10" & x"c6e" => data <= x"2c";
when "10" & x"c6f" => data <= x"0d";
when "10" & x"c70" => data <= x"e9";
when "10" & x"c71" => data <= x"00";
when "10" & x"c72" => data <= x"8d";
when "10" & x"c73" => data <= x"2c";
when "10" & x"c74" => data <= x"0d";
when "10" & x"c75" => data <= x"ad";
when "10" & x"c76" => data <= x"2d";
when "10" & x"c77" => data <= x"0d";
when "10" & x"c78" => data <= x"e9";
when "10" & x"c79" => data <= x"00";
when "10" & x"c7a" => data <= x"8d";
when "10" & x"c7b" => data <= x"2d";
when "10" & x"c7c" => data <= x"0d";
when "10" & x"c7d" => data <= x"0d";
when "10" & x"c7e" => data <= x"2c";
when "10" & x"c7f" => data <= x"0d";
when "10" & x"c80" => data <= x"0d";
when "10" & x"c81" => data <= x"2b";
when "10" & x"c82" => data <= x"0d";
when "10" & x"c83" => data <= x"0d";
when "10" & x"c84" => data <= x"2a";
when "10" & x"c85" => data <= x"0d";
when "10" & x"c86" => data <= x"f0";
when "10" & x"c87" => data <= x"2b";
when "10" & x"c88" => data <= x"ae";
when "10" & x"c89" => data <= x"29";
when "10" & x"c8a" => data <= x"0d";
when "10" & x"c8b" => data <= x"18";
when "10" & x"c8c" => data <= x"ad";
when "10" & x"c8d" => data <= x"23";
when "10" & x"c8e" => data <= x"0d";
when "10" & x"c8f" => data <= x"6d";
when "10" & x"c90" => data <= x"2a";
when "10" & x"c91" => data <= x"0d";
when "10" & x"c92" => data <= x"8d";
when "10" & x"c93" => data <= x"23";
when "10" & x"c94" => data <= x"0d";
when "10" & x"c95" => data <= x"ad";
when "10" & x"c96" => data <= x"24";
when "10" & x"c97" => data <= x"0d";
when "10" & x"c98" => data <= x"6d";
when "10" & x"c99" => data <= x"2b";
when "10" & x"c9a" => data <= x"0d";
when "10" & x"c9b" => data <= x"8d";
when "10" & x"c9c" => data <= x"24";
when "10" & x"c9d" => data <= x"0d";
when "10" & x"c9e" => data <= x"ad";
when "10" & x"c9f" => data <= x"25";
when "10" & x"ca0" => data <= x"0d";
when "10" & x"ca1" => data <= x"6d";
when "10" & x"ca2" => data <= x"2c";
when "10" & x"ca3" => data <= x"0d";
when "10" & x"ca4" => data <= x"8d";
when "10" & x"ca5" => data <= x"25";
when "10" & x"ca6" => data <= x"0d";
when "10" & x"ca7" => data <= x"ad";
when "10" & x"ca8" => data <= x"26";
when "10" & x"ca9" => data <= x"0d";
when "10" & x"caa" => data <= x"6d";
when "10" & x"cab" => data <= x"2d";
when "10" & x"cac" => data <= x"0d";
when "10" & x"cad" => data <= x"8d";
when "10" & x"cae" => data <= x"26";
when "10" & x"caf" => data <= x"0d";
when "10" & x"cb0" => data <= x"ca";
when "10" & x"cb1" => data <= x"d0";
when "10" & x"cb2" => data <= x"d8";
when "10" & x"cb3" => data <= x"ad";
when "10" & x"cb4" => data <= x"22";
when "10" & x"cb5" => data <= x"0d";
when "10" & x"cb6" => data <= x"f0";
when "10" & x"cb7" => data <= x"06";
when "10" & x"cb8" => data <= x"ad";
when "10" & x"cb9" => data <= x"39";
when "10" & x"cba" => data <= x"0d";
when "10" & x"cbb" => data <= x"20";
when "10" & x"cbc" => data <= x"3c";
when "10" & x"cbd" => data <= x"ad";
when "10" & x"cbe" => data <= x"ad";
when "10" & x"cbf" => data <= x"23";
when "10" & x"cc0" => data <= x"0d";
when "10" & x"cc1" => data <= x"8d";
when "10" & x"cc2" => data <= x"06";
when "10" & x"cc3" => data <= x"0d";
when "10" & x"cc4" => data <= x"49";
when "10" & x"cc5" => data <= x"ff";
when "10" & x"cc6" => data <= x"8d";
when "10" & x"cc7" => data <= x"0a";
when "10" & x"cc8" => data <= x"0d";
when "10" & x"cc9" => data <= x"ad";
when "10" & x"cca" => data <= x"24";
when "10" & x"ccb" => data <= x"0d";
when "10" & x"ccc" => data <= x"8d";
when "10" & x"ccd" => data <= x"07";
when "10" & x"cce" => data <= x"0d";
when "10" & x"ccf" => data <= x"49";
when "10" & x"cd0" => data <= x"ff";
when "10" & x"cd1" => data <= x"8d";
when "10" & x"cd2" => data <= x"0b";
when "10" & x"cd3" => data <= x"0d";
when "10" & x"cd4" => data <= x"ad";
when "10" & x"cd5" => data <= x"25";
when "10" & x"cd6" => data <= x"0d";
when "10" & x"cd7" => data <= x"8d";
when "10" & x"cd8" => data <= x"08";
when "10" & x"cd9" => data <= x"0d";
when "10" & x"cda" => data <= x"ad";
when "10" & x"cdb" => data <= x"26";
when "10" & x"cdc" => data <= x"0d";
when "10" & x"cdd" => data <= x"8d";
when "10" & x"cde" => data <= x"09";
when "10" & x"cdf" => data <= x"0d";
when "10" & x"ce0" => data <= x"a9";
when "10" & x"ce1" => data <= x"54";
when "10" & x"ce2" => data <= x"8d";
when "10" & x"ce3" => data <= x"05";
when "10" & x"ce4" => data <= x"0d";
when "10" & x"ce5" => data <= x"a2";
when "10" & x"ce6" => data <= x"00";
when "10" & x"ce7" => data <= x"68";
when "10" & x"ce8" => data <= x"9d";
when "10" & x"ce9" => data <= x"23";
when "10" & x"cea" => data <= x"0d";
when "10" & x"ceb" => data <= x"e8";
when "10" & x"cec" => data <= x"e0";
when "10" & x"ced" => data <= x"0b";
when "10" & x"cee" => data <= x"d0";
when "10" & x"cef" => data <= x"f7";
when "10" & x"cf0" => data <= x"60";
when "10" & x"cf1" => data <= x"20";
when "10" & x"cf2" => data <= x"00";
when "10" & x"cf3" => data <= x"a0";
when "10" & x"cf4" => data <= x"ff";
when "10" & x"cf5" => data <= x"55";
when "10" & x"cf6" => data <= x"6e";
when "10" & x"cf7" => data <= x"72";
when "10" & x"cf8" => data <= x"65";
when "10" & x"cf9" => data <= x"63";
when "10" & x"cfa" => data <= x"6f";
when "10" & x"cfb" => data <= x"67";
when "10" & x"cfc" => data <= x"6e";
when "10" & x"cfd" => data <= x"69";
when "10" & x"cfe" => data <= x"73";
when "10" & x"cff" => data <= x"65";
when "10" & x"d00" => data <= x"64";
when "10" & x"d01" => data <= x"20";
when "10" & x"d02" => data <= x"66";
when "10" & x"d03" => data <= x"6f";
when "10" & x"d04" => data <= x"72";
when "10" & x"d05" => data <= x"6d";
when "10" & x"d06" => data <= x"61";
when "10" & x"d07" => data <= x"74";
when "10" & x"d08" => data <= x"21";
when "10" & x"d09" => data <= x"00";
when "10" & x"d0a" => data <= x"ad";
when "10" & x"d0b" => data <= x"23";
when "10" & x"d0c" => data <= x"0d";
when "10" & x"d0d" => data <= x"8d";
when "10" & x"d0e" => data <= x"06";
when "10" & x"d0f" => data <= x"0d";
when "10" & x"d10" => data <= x"ad";
when "10" & x"d11" => data <= x"24";
when "10" & x"d12" => data <= x"0d";
when "10" & x"d13" => data <= x"8d";
when "10" & x"d14" => data <= x"07";
when "10" & x"d15" => data <= x"0d";
when "10" & x"d16" => data <= x"ad";
when "10" & x"d17" => data <= x"25";
when "10" & x"d18" => data <= x"0d";
when "10" & x"d19" => data <= x"8d";
when "10" & x"d1a" => data <= x"08";
when "10" & x"d1b" => data <= x"0d";
when "10" & x"d1c" => data <= x"ad";
when "10" & x"d1d" => data <= x"26";
when "10" & x"d1e" => data <= x"0d";
when "10" & x"d1f" => data <= x"8d";
when "10" & x"d20" => data <= x"09";
when "10" & x"d21" => data <= x"0d";
when "10" & x"d22" => data <= x"60";
when "10" & x"d23" => data <= x"ad";
when "10" & x"d24" => data <= x"06";
when "10" & x"d25" => data <= x"0d";
when "10" & x"d26" => data <= x"8d";
when "10" & x"d27" => data <= x"23";
when "10" & x"d28" => data <= x"0d";
when "10" & x"d29" => data <= x"ad";
when "10" & x"d2a" => data <= x"07";
when "10" & x"d2b" => data <= x"0d";
when "10" & x"d2c" => data <= x"8d";
when "10" & x"d2d" => data <= x"24";
when "10" & x"d2e" => data <= x"0d";
when "10" & x"d2f" => data <= x"ad";
when "10" & x"d30" => data <= x"08";
when "10" & x"d31" => data <= x"0d";
when "10" & x"d32" => data <= x"8d";
when "10" & x"d33" => data <= x"25";
when "10" & x"d34" => data <= x"0d";
when "10" & x"d35" => data <= x"ad";
when "10" & x"d36" => data <= x"09";
when "10" & x"d37" => data <= x"0d";
when "10" & x"d38" => data <= x"8d";
when "10" & x"d39" => data <= x"26";
when "10" & x"d3a" => data <= x"0d";
when "10" & x"d3b" => data <= x"60";
when "10" & x"d3c" => data <= x"18";
when "10" & x"d3d" => data <= x"6d";
when "10" & x"d3e" => data <= x"23";
when "10" & x"d3f" => data <= x"0d";
when "10" & x"d40" => data <= x"8d";
when "10" & x"d41" => data <= x"23";
when "10" & x"d42" => data <= x"0d";
when "10" & x"d43" => data <= x"ad";
when "10" & x"d44" => data <= x"24";
when "10" & x"d45" => data <= x"0d";
when "10" & x"d46" => data <= x"69";
when "10" & x"d47" => data <= x"00";
when "10" & x"d48" => data <= x"8d";
when "10" & x"d49" => data <= x"24";
when "10" & x"d4a" => data <= x"0d";
when "10" & x"d4b" => data <= x"ad";
when "10" & x"d4c" => data <= x"25";
when "10" & x"d4d" => data <= x"0d";
when "10" & x"d4e" => data <= x"69";
when "10" & x"d4f" => data <= x"00";
when "10" & x"d50" => data <= x"8d";
when "10" & x"d51" => data <= x"25";
when "10" & x"d52" => data <= x"0d";
when "10" & x"d53" => data <= x"ad";
when "10" & x"d54" => data <= x"26";
when "10" & x"d55" => data <= x"0d";
when "10" & x"d56" => data <= x"69";
when "10" & x"d57" => data <= x"00";
when "10" & x"d58" => data <= x"8d";
when "10" & x"d59" => data <= x"26";
when "10" & x"d5a" => data <= x"0d";
when "10" & x"d5b" => data <= x"90";
when "10" & x"d5c" => data <= x"03";
when "10" & x"d5d" => data <= x"4c";
when "10" & x"d5e" => data <= x"f1";
when "10" & x"d5f" => data <= x"ac";
when "10" & x"d60" => data <= x"60";
when "10" & x"d61" => data <= x"42";
when "10" & x"d62" => data <= x"45";
when "10" & x"d63" => data <= x"45";
when "10" & x"d64" => data <= x"42";
when "10" & x"d65" => data <= x"20";
when "10" & x"d66" => data <= x"20";
when "10" & x"d67" => data <= x"20";
when "10" & x"d68" => data <= x"20";
when "10" & x"d69" => data <= x"4d";
when "10" & x"d6a" => data <= x"4d";
when "10" & x"d6b" => data <= x"42";
when "10" & x"d6c" => data <= x"08";
when "10" & x"d6d" => data <= x"aa";
when "10" & x"d6e" => data <= x"20";
when "10" & x"d6f" => data <= x"a1";
when "10" & x"d70" => data <= x"ad";
when "10" & x"d71" => data <= x"85";
when "10" & x"d72" => data <= x"b2";
when "10" & x"d73" => data <= x"48";
when "10" & x"d74" => data <= x"20";
when "10" & x"d75" => data <= x"bd";
when "10" & x"d76" => data <= x"ad";
when "10" & x"d77" => data <= x"8a";
when "10" & x"d78" => data <= x"e5";
when "10" & x"d79" => data <= x"b0";
when "10" & x"d7a" => data <= x"aa";
when "10" & x"d7b" => data <= x"68";
when "10" & x"d7c" => data <= x"20";
when "10" & x"d7d" => data <= x"a1";
when "10" & x"d7e" => data <= x"ad";
when "10" & x"d7f" => data <= x"48";
when "10" & x"d80" => data <= x"20";
when "10" & x"d81" => data <= x"bd";
when "10" & x"d82" => data <= x"ad";
when "10" & x"d83" => data <= x"a5";
when "10" & x"d84" => data <= x"b2";
when "10" & x"d85" => data <= x"e5";
when "10" & x"d86" => data <= x"b0";
when "10" & x"d87" => data <= x"0a";
when "10" & x"d88" => data <= x"0a";
when "10" & x"d89" => data <= x"0a";
when "10" & x"d8a" => data <= x"0a";
when "10" & x"d8b" => data <= x"85";
when "10" & x"d8c" => data <= x"b2";
when "10" & x"d8d" => data <= x"8a";
when "10" & x"d8e" => data <= x"05";
when "10" & x"d8f" => data <= x"b2";
when "10" & x"d90" => data <= x"aa";
when "10" & x"d91" => data <= x"68";
when "10" & x"d92" => data <= x"28";
when "10" & x"d93" => data <= x"90";
when "10" & x"d94" => data <= x"0b";
when "10" & x"d95" => data <= x"48";
when "10" & x"d96" => data <= x"8a";
when "10" & x"d97" => data <= x"f8";
when "10" & x"d98" => data <= x"18";
when "10" & x"d99" => data <= x"69";
when "10" & x"d9a" => data <= x"56";
when "10" & x"d9b" => data <= x"aa";
when "10" & x"d9c" => data <= x"68";
when "10" & x"d9d" => data <= x"69";
when "10" & x"d9e" => data <= x"02";
when "10" & x"d9f" => data <= x"d8";
when "10" & x"da0" => data <= x"60";
when "10" & x"da1" => data <= x"a0";
when "10" & x"da2" => data <= x"00";
when "10" & x"da3" => data <= x"84";
when "10" & x"da4" => data <= x"b1";
when "10" & x"da5" => data <= x"a0";
when "10" & x"da6" => data <= x"a0";
when "10" & x"da7" => data <= x"84";
when "10" & x"da8" => data <= x"b0";
when "10" & x"da9" => data <= x"a0";
when "10" & x"daa" => data <= x"05";
when "10" & x"dab" => data <= x"c5";
when "10" & x"dac" => data <= x"b0";
when "10" & x"dad" => data <= x"90";
when "10" & x"dae" => data <= x"04";
when "10" & x"daf" => data <= x"38";
when "10" & x"db0" => data <= x"e5";
when "10" & x"db1" => data <= x"b0";
when "10" & x"db2" => data <= x"38";
when "10" & x"db3" => data <= x"26";
when "10" & x"db4" => data <= x"b1";
when "10" & x"db5" => data <= x"46";
when "10" & x"db6" => data <= x"b0";
when "10" & x"db7" => data <= x"88";
when "10" & x"db8" => data <= x"d0";
when "10" & x"db9" => data <= x"f1";
when "10" & x"dba" => data <= x"a5";
when "10" & x"dbb" => data <= x"b1";
when "10" & x"dbc" => data <= x"60";
when "10" & x"dbd" => data <= x"48";
when "10" & x"dbe" => data <= x"0a";
when "10" & x"dbf" => data <= x"0a";
when "10" & x"dc0" => data <= x"0a";
when "10" & x"dc1" => data <= x"85";
when "10" & x"dc2" => data <= x"b0";
when "10" & x"dc3" => data <= x"68";
when "10" & x"dc4" => data <= x"0a";
when "10" & x"dc5" => data <= x"18";
when "10" & x"dc6" => data <= x"65";
when "10" & x"dc7" => data <= x"b0";
when "10" & x"dc8" => data <= x"85";
when "10" & x"dc9" => data <= x"b0";
when "10" & x"dca" => data <= x"38";
when "10" & x"dcb" => data <= x"60";
when "10" & x"dcc" => data <= x"e0";
when "10" & x"dcd" => data <= x"ff";
when "10" & x"dce" => data <= x"f0";
when "10" & x"dcf" => data <= x"35";
when "10" & x"dd0" => data <= x"bd";
when "10" & x"dd1" => data <= x"10";
when "10" & x"dd2" => data <= x"0d";
when "10" & x"dd3" => data <= x"30";
when "10" & x"dd4" => data <= x"30";
when "10" & x"dd5" => data <= x"49";
when "10" & x"dd6" => data <= x"ff";
when "10" & x"dd7" => data <= x"dd";
when "10" & x"dd8" => data <= x"18";
when "10" & x"dd9" => data <= x"0d";
when "10" & x"dda" => data <= x"d0";
when "10" & x"ddb" => data <= x"24";
when "10" & x"ddc" => data <= x"bd";
when "10" & x"ddd" => data <= x"0c";
when "10" & x"dde" => data <= x"0d";
when "10" & x"ddf" => data <= x"49";
when "10" & x"de0" => data <= x"ff";
when "10" & x"de1" => data <= x"dd";
when "10" & x"de2" => data <= x"14";
when "10" & x"de3" => data <= x"0d";
when "10" & x"de4" => data <= x"d0";
when "10" & x"de5" => data <= x"1a";
when "10" & x"de6" => data <= x"bd";
when "10" & x"de7" => data <= x"1c";
when "10" & x"de8" => data <= x"0d";
when "10" & x"de9" => data <= x"c9";
when "10" & x"dea" => data <= x"54";
when "10" & x"deb" => data <= x"f0";
when "10" & x"dec" => data <= x"29";
when "10" & x"ded" => data <= x"20";
when "10" & x"dee" => data <= x"00";
when "10" & x"def" => data <= x"a0";
when "10" & x"df0" => data <= x"c9";
when "10" & x"df1" => data <= x"44";
when "10" & x"df2" => data <= x"69";
when "10" & x"df3" => data <= x"73";
when "10" & x"df4" => data <= x"6b";
when "10" & x"df5" => data <= x"20";
when "10" & x"df6" => data <= x"72";
when "10" & x"df7" => data <= x"65";
when "10" & x"df8" => data <= x"61";
when "10" & x"df9" => data <= x"64";
when "10" & x"dfa" => data <= x"20";
when "10" & x"dfb" => data <= x"6f";
when "10" & x"dfc" => data <= x"6e";
when "10" & x"dfd" => data <= x"6c";
when "10" & x"dfe" => data <= x"79";
when "10" & x"dff" => data <= x"00";
when "10" & x"e00" => data <= x"a9";
when "10" & x"e01" => data <= x"ff";
when "10" & x"e02" => data <= x"9d";
when "10" & x"e03" => data <= x"10";
when "10" & x"e04" => data <= x"0d";
when "10" & x"e05" => data <= x"20";
when "10" & x"e06" => data <= x"00";
when "10" & x"e07" => data <= x"a0";
when "10" & x"e08" => data <= x"c7";
when "10" & x"e09" => data <= x"4e";
when "10" & x"e0a" => data <= x"6f";
when "10" & x"e0b" => data <= x"20";
when "10" & x"e0c" => data <= x"64";
when "10" & x"e0d" => data <= x"69";
when "10" & x"e0e" => data <= x"73";
when "10" & x"e0f" => data <= x"6b";
when "10" & x"e10" => data <= x"00";
when "10" & x"e11" => data <= x"a9";
when "10" & x"e12" => data <= x"54";
when "10" & x"e13" => data <= x"9d";
when "10" & x"e14" => data <= x"1c";
when "10" & x"e15" => data <= x"0d";
when "10" & x"e16" => data <= x"60";
when "10" & x"e17" => data <= x"a9";
when "10" & x"e18" => data <= x"00";
when "10" & x"e19" => data <= x"9d";
when "10" & x"e1a" => data <= x"1c";
when "10" & x"e1b" => data <= x"0d";
when "10" & x"e1c" => data <= x"60";
when "10" & x"e1d" => data <= x"bd";
when "10" & x"e1e" => data <= x"10";
when "10" & x"e1f" => data <= x"0d";
when "10" & x"e20" => data <= x"30";
when "10" & x"e21" => data <= x"e3";
when "10" & x"e22" => data <= x"6a";
when "10" & x"e23" => data <= x"bd";
when "10" & x"e24" => data <= x"0c";
when "10" & x"e25" => data <= x"0d";
when "10" & x"e26" => data <= x"08";
when "10" & x"e27" => data <= x"aa";
when "10" & x"e28" => data <= x"a9";
when "10" & x"e29" => data <= x"00";
when "10" & x"e2a" => data <= x"8d";
when "10" & x"e2b" => data <= x"23";
when "10" & x"e2c" => data <= x"0d";
when "10" & x"e2d" => data <= x"8d";
when "10" & x"e2e" => data <= x"26";
when "10" & x"e2f" => data <= x"0d";
when "10" & x"e30" => data <= x"2a";
when "10" & x"e31" => data <= x"48";
when "10" & x"e32" => data <= x"8d";
when "10" & x"e33" => data <= x"25";
when "10" & x"e34" => data <= x"0d";
when "10" & x"e35" => data <= x"8a";
when "10" & x"e36" => data <= x"0a";
when "10" & x"e37" => data <= x"2e";
when "10" & x"e38" => data <= x"25";
when "10" & x"e39" => data <= x"0d";
when "10" & x"e3a" => data <= x"8d";
when "10" & x"e3b" => data <= x"24";
when "10" & x"e3c" => data <= x"0d";
when "10" & x"e3d" => data <= x"8a";
when "10" & x"e3e" => data <= x"6d";
when "10" & x"e3f" => data <= x"24";
when "10" & x"e40" => data <= x"0d";
when "10" & x"e41" => data <= x"8d";
when "10" & x"e42" => data <= x"24";
when "10" & x"e43" => data <= x"0d";
when "10" & x"e44" => data <= x"68";
when "10" & x"e45" => data <= x"69";
when "10" & x"e46" => data <= x"00";
when "10" & x"e47" => data <= x"6d";
when "10" & x"e48" => data <= x"25";
when "10" & x"e49" => data <= x"0d";
when "10" & x"e4a" => data <= x"8d";
when "10" & x"e4b" => data <= x"25";
when "10" & x"e4c" => data <= x"0d";
when "10" & x"e4d" => data <= x"a9";
when "10" & x"e4e" => data <= x"00";
when "10" & x"e4f" => data <= x"6d";
when "10" & x"e50" => data <= x"26";
when "10" & x"e51" => data <= x"0d";
when "10" & x"e52" => data <= x"8d";
when "10" & x"e53" => data <= x"26";
when "10" & x"e54" => data <= x"0d";
when "10" & x"e55" => data <= x"6e";
when "10" & x"e56" => data <= x"23";
when "10" & x"e57" => data <= x"0d";
when "10" & x"e58" => data <= x"8a";
when "10" & x"e59" => data <= x"28";
when "10" & x"e5a" => data <= x"6a";
when "10" & x"e5b" => data <= x"6e";
when "10" & x"e5c" => data <= x"23";
when "10" & x"e5d" => data <= x"0d";
when "10" & x"e5e" => data <= x"4a";
when "10" & x"e5f" => data <= x"6e";
when "10" & x"e60" => data <= x"23";
when "10" & x"e61" => data <= x"0d";
when "10" & x"e62" => data <= x"4a";
when "10" & x"e63" => data <= x"6e";
when "10" & x"e64" => data <= x"23";
when "10" & x"e65" => data <= x"0d";
when "10" & x"e66" => data <= x"6d";
when "10" & x"e67" => data <= x"24";
when "10" & x"e68" => data <= x"0d";
when "10" & x"e69" => data <= x"8d";
when "10" & x"e6a" => data <= x"24";
when "10" & x"e6b" => data <= x"0d";
when "10" & x"e6c" => data <= x"ad";
when "10" & x"e6d" => data <= x"25";
when "10" & x"e6e" => data <= x"0d";
when "10" & x"e6f" => data <= x"69";
when "10" & x"e70" => data <= x"00";
when "10" & x"e71" => data <= x"8d";
when "10" & x"e72" => data <= x"25";
when "10" & x"e73" => data <= x"0d";
when "10" & x"e74" => data <= x"ad";
when "10" & x"e75" => data <= x"26";
when "10" & x"e76" => data <= x"0d";
when "10" & x"e77" => data <= x"69";
when "10" & x"e78" => data <= x"00";
when "10" & x"e79" => data <= x"8d";
when "10" & x"e7a" => data <= x"26";
when "10" & x"e7b" => data <= x"0d";
when "10" & x"e7c" => data <= x"6e";
when "10" & x"e7d" => data <= x"26";
when "10" & x"e7e" => data <= x"0d";
when "10" & x"e7f" => data <= x"6e";
when "10" & x"e80" => data <= x"25";
when "10" & x"e81" => data <= x"0d";
when "10" & x"e82" => data <= x"6e";
when "10" & x"e83" => data <= x"24";
when "10" & x"e84" => data <= x"0d";
when "10" & x"e85" => data <= x"6e";
when "10" & x"e86" => data <= x"23";
when "10" & x"e87" => data <= x"0d";
when "10" & x"e88" => data <= x"20";
when "10" & x"e89" => data <= x"a7";
when "10" & x"e8a" => data <= x"aa";
when "10" & x"e8b" => data <= x"38";
when "10" & x"e8c" => data <= x"ad";
when "10" & x"e8d" => data <= x"23";
when "10" & x"e8e" => data <= x"0d";
when "10" & x"e8f" => data <= x"09";
when "10" & x"e90" => data <= x"0f";
when "10" & x"e91" => data <= x"6d";
when "10" & x"e92" => data <= x"06";
when "10" & x"e93" => data <= x"0d";
when "10" & x"e94" => data <= x"8d";
when "10" & x"e95" => data <= x"23";
when "10" & x"e96" => data <= x"0d";
when "10" & x"e97" => data <= x"ad";
when "10" & x"e98" => data <= x"24";
when "10" & x"e99" => data <= x"0d";
when "10" & x"e9a" => data <= x"6d";
when "10" & x"e9b" => data <= x"07";
when "10" & x"e9c" => data <= x"0d";
when "10" & x"e9d" => data <= x"8d";
when "10" & x"e9e" => data <= x"24";
when "10" & x"e9f" => data <= x"0d";
when "10" & x"ea0" => data <= x"ad";
when "10" & x"ea1" => data <= x"25";
when "10" & x"ea2" => data <= x"0d";
when "10" & x"ea3" => data <= x"6d";
when "10" & x"ea4" => data <= x"08";
when "10" & x"ea5" => data <= x"0d";
when "10" & x"ea6" => data <= x"8d";
when "10" & x"ea7" => data <= x"25";
when "10" & x"ea8" => data <= x"0d";
when "10" & x"ea9" => data <= x"60";
when "10" & x"eaa" => data <= x"a5";
when "10" & x"eab" => data <= x"be";
when "10" & x"eac" => data <= x"85";
when "10" & x"ead" => data <= x"a0";
when "10" & x"eae" => data <= x"a5";
when "10" & x"eaf" => data <= x"bf";
when "10" & x"eb0" => data <= x"85";
when "10" & x"eb1" => data <= x"a1";
when "10" & x"eb2" => data <= x"a6";
when "10" & x"eb3" => data <= x"cf";
when "10" & x"eb4" => data <= x"20";
when "10" & x"eb5" => data <= x"1d";
when "10" & x"eb6" => data <= x"ae";
when "10" & x"eb7" => data <= x"18";
when "10" & x"eb8" => data <= x"a5";
when "10" & x"eb9" => data <= x"c4";
when "10" & x"eba" => data <= x"29";
when "10" & x"ebb" => data <= x"03";
when "10" & x"ebc" => data <= x"48";
when "10" & x"ebd" => data <= x"6a";
when "10" & x"ebe" => data <= x"48";
when "10" & x"ebf" => data <= x"a5";
when "10" & x"ec0" => data <= x"c5";
when "10" & x"ec1" => data <= x"6a";
when "10" & x"ec2" => data <= x"48";
when "10" & x"ec3" => data <= x"90";
when "10" & x"ec4" => data <= x"03";
when "10" & x"ec5" => data <= x"6e";
when "10" & x"ec6" => data <= x"28";
when "10" & x"ec7" => data <= x"0d";
when "10" & x"ec8" => data <= x"18";
when "10" & x"ec9" => data <= x"68";
when "10" & x"eca" => data <= x"6d";
when "10" & x"ecb" => data <= x"23";
when "10" & x"ecc" => data <= x"0d";
when "10" & x"ecd" => data <= x"8d";
when "10" & x"ece" => data <= x"23";
when "10" & x"ecf" => data <= x"0d";
when "10" & x"ed0" => data <= x"68";
when "10" & x"ed1" => data <= x"6d";
when "10" & x"ed2" => data <= x"24";
when "10" & x"ed3" => data <= x"0d";
when "10" & x"ed4" => data <= x"8d";
when "10" & x"ed5" => data <= x"24";
when "10" & x"ed6" => data <= x"0d";
when "10" & x"ed7" => data <= x"a9";
when "10" & x"ed8" => data <= x"00";
when "10" & x"ed9" => data <= x"6d";
when "10" & x"eda" => data <= x"25";
when "10" & x"edb" => data <= x"0d";
when "10" & x"edc" => data <= x"8d";
when "10" & x"edd" => data <= x"25";
when "10" & x"ede" => data <= x"0d";
when "10" & x"edf" => data <= x"a9";
when "10" & x"ee0" => data <= x"00";
when "10" & x"ee1" => data <= x"6d";
when "10" & x"ee2" => data <= x"26";
when "10" & x"ee3" => data <= x"0d";
when "10" & x"ee4" => data <= x"8d";
when "10" & x"ee5" => data <= x"26";
when "10" & x"ee6" => data <= x"0d";
when "10" & x"ee7" => data <= x"a5";
when "10" & x"ee8" => data <= x"c3";
when "10" & x"ee9" => data <= x"8d";
when "10" & x"eea" => data <= x"27";
when "10" & x"eeb" => data <= x"0d";
when "10" & x"eec" => data <= x"a5";
when "10" & x"eed" => data <= x"c4";
when "10" & x"eee" => data <= x"4a";
when "10" & x"eef" => data <= x"4a";
when "10" & x"ef0" => data <= x"4a";
when "10" & x"ef1" => data <= x"4a";
when "10" & x"ef2" => data <= x"29";
when "10" & x"ef3" => data <= x"03";
when "10" & x"ef4" => data <= x"d0";
when "10" & x"ef5" => data <= x"21";
when "10" & x"ef6" => data <= x"a5";
when "10" & x"ef7" => data <= x"c2";
when "10" & x"ef8" => data <= x"8d";
when "10" & x"ef9" => data <= x"29";
when "10" & x"efa" => data <= x"0d";
when "10" & x"efb" => data <= x"f0";
when "10" & x"efc" => data <= x"05";
when "10" & x"efd" => data <= x"ee";
when "10" & x"efe" => data <= x"27";
when "10" & x"eff" => data <= x"0d";
when "10" & x"f00" => data <= x"f0";
when "10" & x"f01" => data <= x"15";
when "10" & x"f02" => data <= x"18";
when "10" & x"f03" => data <= x"a5";
when "10" & x"f04" => data <= x"c5";
when "10" & x"f05" => data <= x"6d";
when "10" & x"f06" => data <= x"27";
when "10" & x"f07" => data <= x"0d";
when "10" & x"f08" => data <= x"aa";
when "10" & x"f09" => data <= x"68";
when "10" & x"f0a" => data <= x"69";
when "10" & x"f0b" => data <= x"00";
when "10" & x"f0c" => data <= x"c9";
when "10" & x"f0d" => data <= x"03";
when "10" & x"f0e" => data <= x"90";
when "10" & x"f0f" => data <= x"06";
when "10" & x"f10" => data <= x"d0";
when "10" & x"f11" => data <= x"17";
when "10" & x"f12" => data <= x"e0";
when "10" & x"f13" => data <= x"21";
when "10" & x"f14" => data <= x"b0";
when "10" & x"f15" => data <= x"13";
when "10" & x"f16" => data <= x"60";
when "10" & x"f17" => data <= x"20";
when "10" & x"f18" => data <= x"00";
when "10" & x"f19" => data <= x"a0";
when "10" & x"f1a" => data <= x"ff";
when "10" & x"f1b" => data <= x"42";
when "10" & x"f1c" => data <= x"6c";
when "10" & x"f1d" => data <= x"6f";
when "10" & x"f1e" => data <= x"63";
when "10" & x"f1f" => data <= x"6b";
when "10" & x"f20" => data <= x"20";
when "10" & x"f21" => data <= x"74";
when "10" & x"f22" => data <= x"6f";
when "10" & x"f23" => data <= x"6f";
when "10" & x"f24" => data <= x"20";
when "10" & x"f25" => data <= x"62";
when "10" & x"f26" => data <= x"69";
when "10" & x"f27" => data <= x"67";
when "10" & x"f28" => data <= x"00";
when "10" & x"f29" => data <= x"20";
when "10" & x"f2a" => data <= x"00";
when "10" & x"f2b" => data <= x"a0";
when "10" & x"f2c" => data <= x"ff";
when "10" & x"f2d" => data <= x"44";
when "10" & x"f2e" => data <= x"69";
when "10" & x"f2f" => data <= x"73";
when "10" & x"f30" => data <= x"6b";
when "10" & x"f31" => data <= x"20";
when "10" & x"f32" => data <= x"6f";
when "10" & x"f33" => data <= x"76";
when "10" & x"f34" => data <= x"65";
when "10" & x"f35" => data <= x"72";
when "10" & x"f36" => data <= x"66";
when "10" & x"f37" => data <= x"6c";
when "10" & x"f38" => data <= x"6f";
when "10" & x"f39" => data <= x"77";
when "10" & x"f3a" => data <= x"00";
when "10" & x"f3b" => data <= x"20";
when "10" & x"f3c" => data <= x"4d";
when "10" & x"f3d" => data <= x"83";
when "10" & x"f3e" => data <= x"20";
when "10" & x"f3f" => data <= x"58";
when "10" & x"f40" => data <= x"83";
when "10" & x"f41" => data <= x"20";
when "10" & x"f42" => data <= x"1f";
when "10" & x"f43" => data <= x"a6";
when "10" & x"f44" => data <= x"a6";
when "10" & x"f45" => data <= x"cf";
when "10" & x"f46" => data <= x"8e";
when "10" & x"f47" => data <= x"20";
when "10" & x"f48" => data <= x"0d";
when "10" & x"f49" => data <= x"20";
when "10" & x"f4a" => data <= x"1d";
when "10" & x"f4b" => data <= x"ae";
when "10" & x"f4c" => data <= x"20";
when "10" & x"f4d" => data <= x"99";
when "10" & x"f4e" => data <= x"a7";
when "10" & x"f4f" => data <= x"a5";
when "10" & x"f50" => data <= x"cf";
when "10" & x"f51" => data <= x"8d";
when "10" & x"f52" => data <= x"82";
when "10" & x"f53" => data <= x"10";
when "10" & x"f54" => data <= x"60";
when "10" & x"f55" => data <= x"20";
when "10" & x"f56" => data <= x"1f";
when "10" & x"f57" => data <= x"a6";
when "10" & x"f58" => data <= x"a6";
when "10" & x"f59" => data <= x"cf";
when "10" & x"f5a" => data <= x"20";
when "10" & x"f5b" => data <= x"cc";
when "10" & x"f5c" => data <= x"ad";
when "10" & x"f5d" => data <= x"20";
when "10" & x"f5e" => data <= x"1d";
when "10" & x"f5f" => data <= x"ae";
when "10" & x"f60" => data <= x"4c";
when "10" & x"f61" => data <= x"b2";
when "10" & x"f62" => data <= x"a7";
when "10" & x"f63" => data <= x"08";
when "10" & x"f64" => data <= x"48";
when "10" & x"f65" => data <= x"a0";
when "10" & x"f66" => data <= x"ff";
when "10" & x"f67" => data <= x"8c";
when "10" & x"f68" => data <= x"82";
when "10" & x"f69" => data <= x"10";
when "10" & x"f6a" => data <= x"c8";
when "10" & x"f6b" => data <= x"98";
when "10" & x"f6c" => data <= x"99";
when "10" & x"f6d" => data <= x"00";
when "10" & x"f6e" => data <= x"0e";
when "10" & x"f6f" => data <= x"99";
when "10" & x"f70" => data <= x"00";
when "10" & x"f71" => data <= x"0f";
when "10" & x"f72" => data <= x"c8";
when "10" & x"f73" => data <= x"d0";
when "10" & x"f74" => data <= x"f7";
when "10" & x"f75" => data <= x"a9";
when "10" & x"f76" => data <= x"03";
when "10" & x"f77" => data <= x"8d";
when "10" & x"f78" => data <= x"06";
when "10" & x"f79" => data <= x"0f";
when "10" & x"f7a" => data <= x"a9";
when "10" & x"f7b" => data <= x"20";
when "10" & x"f7c" => data <= x"8d";
when "10" & x"f7d" => data <= x"07";
when "10" & x"f7e" => data <= x"0f";
when "10" & x"f7f" => data <= x"20";
when "10" & x"f80" => data <= x"1f";
when "10" & x"f81" => data <= x"a6";
when "10" & x"f82" => data <= x"68";
when "10" & x"f83" => data <= x"28";
when "10" & x"f84" => data <= x"20";
when "10" & x"f85" => data <= x"26";
when "10" & x"f86" => data <= x"ae";
when "10" & x"f87" => data <= x"4c";
when "10" & x"f88" => data <= x"b2";
when "10" & x"f89" => data <= x"a7";
when "10" & x"f8a" => data <= x"20";
when "10" & x"f8b" => data <= x"1f";
when "10" & x"f8c" => data <= x"a6";
when "10" & x"f8d" => data <= x"20";
when "10" & x"f8e" => data <= x"aa";
when "10" & x"f8f" => data <= x"ae";
when "10" & x"f90" => data <= x"20";
when "10" & x"f91" => data <= x"cc";
when "10" & x"f92" => data <= x"a7";
when "10" & x"f93" => data <= x"20";
when "10" & x"f94" => data <= x"cd";
when "10" & x"f95" => data <= x"a0";
when "10" & x"f96" => data <= x"a9";
when "10" & x"f97" => data <= x"01";
when "10" & x"f98" => data <= x"60";
when "10" & x"f99" => data <= x"20";
when "10" & x"f9a" => data <= x"1f";
when "10" & x"f9b" => data <= x"a6";
when "10" & x"f9c" => data <= x"20";
when "10" & x"f9d" => data <= x"aa";
when "10" & x"f9e" => data <= x"ae";
when "10" & x"f9f" => data <= x"a6";
when "10" & x"fa0" => data <= x"cf";
when "10" & x"fa1" => data <= x"20";
when "10" & x"fa2" => data <= x"cc";
when "10" & x"fa3" => data <= x"ad";
when "10" & x"fa4" => data <= x"20";
when "10" & x"fa5" => data <= x"78";
when "10" & x"fa6" => data <= x"a8";
when "10" & x"fa7" => data <= x"20";
when "10" & x"fa8" => data <= x"cd";
when "10" & x"fa9" => data <= x"a0";
when "10" & x"faa" => data <= x"a9";
when "10" & x"fab" => data <= x"01";
when "10" & x"fac" => data <= x"60";
when "10" & x"fad" => data <= x"a8";
when "10" & x"fae" => data <= x"c8";
when "10" & x"faf" => data <= x"98";
when "10" & x"fb0" => data <= x"d0";
when "10" & x"fb1" => data <= x"01";
when "10" & x"fb2" => data <= x"38";
when "10" & x"fb3" => data <= x"2a";
when "10" & x"fb4" => data <= x"2a";
when "10" & x"fb5" => data <= x"2a";
when "10" & x"fb6" => data <= x"2a";
when "10" & x"fb7" => data <= x"2a";
when "10" & x"fb8" => data <= x"48";
when "10" & x"fb9" => data <= x"29";
when "10" & x"fba" => data <= x"1f";
when "10" & x"fbb" => data <= x"a8";
when "10" & x"fbc" => data <= x"68";
when "10" & x"fbd" => data <= x"09";
when "10" & x"fbe" => data <= x"1f";
when "10" & x"fbf" => data <= x"6a";
when "10" & x"fc0" => data <= x"60";
when "10" & x"fc1" => data <= x"20";
when "10" & x"fc2" => data <= x"ad";
when "10" & x"fc3" => data <= x"af";
when "10" & x"fc4" => data <= x"48";
when "10" & x"fc5" => data <= x"8a";
when "10" & x"fc6" => data <= x"48";
when "10" & x"fc7" => data <= x"98";
when "10" & x"fc8" => data <= x"48";
when "10" & x"fc9" => data <= x"20";
when "10" & x"fca" => data <= x"97";
when "10" & x"fcb" => data <= x"b0";
when "10" & x"fcc" => data <= x"68";
when "10" & x"fcd" => data <= x"6a";
when "10" & x"fce" => data <= x"68";
when "10" & x"fcf" => data <= x"aa";
when "10" & x"fd0" => data <= x"68";
when "10" & x"fd1" => data <= x"a8";
when "10" & x"fd2" => data <= x"b0";
when "10" & x"fd3" => data <= x"04";
when "10" & x"fd4" => data <= x"b9";
when "10" & x"fd5" => data <= x"00";
when "10" & x"fd6" => data <= x"0e";
when "10" & x"fd7" => data <= x"60";
when "10" & x"fd8" => data <= x"b9";
when "10" & x"fd9" => data <= x"00";
when "10" & x"fda" => data <= x"0f";
when "10" & x"fdb" => data <= x"60";
when "10" & x"fdc" => data <= x"08";
when "10" & x"fdd" => data <= x"48";
when "10" & x"fde" => data <= x"8d";
when "10" & x"fdf" => data <= x"5f";
when "10" & x"fe0" => data <= x"0d";
when "10" & x"fe1" => data <= x"a9";
when "10" & x"fe2" => data <= x"00";
when "10" & x"fe3" => data <= x"2a";
when "10" & x"fe4" => data <= x"8d";
when "10" & x"fe5" => data <= x"60";
when "10" & x"fe6" => data <= x"0d";
when "10" & x"fe7" => data <= x"8e";
when "10" & x"fe8" => data <= x"61";
when "10" & x"fe9" => data <= x"0d";
when "10" & x"fea" => data <= x"a2";
when "10" & x"feb" => data <= x"03";
when "10" & x"fec" => data <= x"ec";
when "10" & x"fed" => data <= x"61";
when "10" & x"fee" => data <= x"0d";
when "10" & x"fef" => data <= x"f0";
when "10" & x"ff0" => data <= x"15";
when "10" & x"ff1" => data <= x"bd";
when "10" & x"ff2" => data <= x"0c";
when "10" & x"ff3" => data <= x"0d";
when "10" & x"ff4" => data <= x"cd";
when "10" & x"ff5" => data <= x"5f";
when "10" & x"ff6" => data <= x"0d";
when "10" & x"ff7" => data <= x"d0";
when "10" & x"ff8" => data <= x"0d";
when "10" & x"ff9" => data <= x"bd";
when "10" & x"ffa" => data <= x"10";
when "10" & x"ffb" => data <= x"0d";
when "10" & x"ffc" => data <= x"cd";
when "10" & x"ffd" => data <= x"60";
when "10" & x"ffe" => data <= x"0d";
when "10" & x"fff" => data <= x"d0";
when "11" & x"000" => data <= x"05";
when "11" & x"001" => data <= x"a9";
when "11" & x"002" => data <= x"ff";
when "11" & x"003" => data <= x"9d";
when "11" & x"004" => data <= x"10";
when "11" & x"005" => data <= x"0d";
when "11" & x"006" => data <= x"ca";
when "11" & x"007" => data <= x"10";
when "11" & x"008" => data <= x"e3";
when "11" & x"009" => data <= x"ae";
when "11" & x"00a" => data <= x"61";
when "11" & x"00b" => data <= x"0d";
when "11" & x"00c" => data <= x"68";
when "11" & x"00d" => data <= x"28";
when "11" & x"00e" => data <= x"60";
when "11" & x"00f" => data <= x"08";
when "11" & x"010" => data <= x"48";
when "11" & x"011" => data <= x"9d";
when "11" & x"012" => data <= x"0c";
when "11" & x"013" => data <= x"0d";
when "11" & x"014" => data <= x"49";
when "11" & x"015" => data <= x"ff";
when "11" & x"016" => data <= x"9d";
when "11" & x"017" => data <= x"14";
when "11" & x"018" => data <= x"0d";
when "11" & x"019" => data <= x"a9";
when "11" & x"01a" => data <= x"00";
when "11" & x"01b" => data <= x"2a";
when "11" & x"01c" => data <= x"9d";
when "11" & x"01d" => data <= x"10";
when "11" & x"01e" => data <= x"0d";
when "11" & x"01f" => data <= x"49";
when "11" & x"020" => data <= x"ff";
when "11" & x"021" => data <= x"9d";
when "11" & x"022" => data <= x"18";
when "11" & x"023" => data <= x"0d";
when "11" & x"024" => data <= x"68";
when "11" & x"025" => data <= x"28";
when "11" & x"026" => data <= x"20";
when "11" & x"027" => data <= x"dc";
when "11" & x"028" => data <= x"af";
when "11" & x"029" => data <= x"20";
when "11" & x"02a" => data <= x"c1";
when "11" & x"02b" => data <= x"af";
when "11" & x"02c" => data <= x"30";
when "11" & x"02d" => data <= x"08";
when "11" & x"02e" => data <= x"f0";
when "11" & x"02f" => data <= x"03";
when "11" & x"030" => data <= x"4c";
when "11" & x"031" => data <= x"11";
when "11" & x"032" => data <= x"ae";
when "11" & x"033" => data <= x"4c";
when "11" & x"034" => data <= x"17";
when "11" & x"035" => data <= x"ae";
when "11" & x"036" => data <= x"a8";
when "11" & x"037" => data <= x"a9";
when "11" & x"038" => data <= x"ff";
when "11" & x"039" => data <= x"9d";
when "11" & x"03a" => data <= x"10";
when "11" & x"03b" => data <= x"0d";
when "11" & x"03c" => data <= x"c8";
when "11" & x"03d" => data <= x"d0";
when "11" & x"03e" => data <= x"1a";
when "11" & x"03f" => data <= x"20";
when "11" & x"040" => data <= x"00";
when "11" & x"041" => data <= x"a0";
when "11" & x"042" => data <= x"c7";
when "11" & x"043" => data <= x"44";
when "11" & x"044" => data <= x"69";
when "11" & x"045" => data <= x"73";
when "11" & x"046" => data <= x"6b";
when "11" & x"047" => data <= x"20";
when "11" & x"048" => data <= x"6e";
when "11" & x"049" => data <= x"75";
when "11" & x"04a" => data <= x"6d";
when "11" & x"04b" => data <= x"62";
when "11" & x"04c" => data <= x"65";
when "11" & x"04d" => data <= x"72";
when "11" & x"04e" => data <= x"20";
when "11" & x"04f" => data <= x"6e";
when "11" & x"050" => data <= x"6f";
when "11" & x"051" => data <= x"74";
when "11" & x"052" => data <= x"20";
when "11" & x"053" => data <= x"76";
when "11" & x"054" => data <= x"61";
when "11" & x"055" => data <= x"6c";
when "11" & x"056" => data <= x"69";
when "11" & x"057" => data <= x"64";
when "11" & x"058" => data <= x"00";
when "11" & x"059" => data <= x"20";
when "11" & x"05a" => data <= x"00";
when "11" & x"05b" => data <= x"a0";
when "11" & x"05c" => data <= x"c7";
when "11" & x"05d" => data <= x"44";
when "11" & x"05e" => data <= x"69";
when "11" & x"05f" => data <= x"73";
when "11" & x"060" => data <= x"6b";
when "11" & x"061" => data <= x"20";
when "11" & x"062" => data <= x"6e";
when "11" & x"063" => data <= x"6f";
when "11" & x"064" => data <= x"74";
when "11" & x"065" => data <= x"20";
when "11" & x"066" => data <= x"66";
when "11" & x"067" => data <= x"6f";
when "11" & x"068" => data <= x"72";
when "11" & x"069" => data <= x"6d";
when "11" & x"06a" => data <= x"61";
when "11" & x"06b" => data <= x"74";
when "11" & x"06c" => data <= x"74";
when "11" & x"06d" => data <= x"65";
when "11" & x"06e" => data <= x"64";
when "11" & x"06f" => data <= x"00";
when "11" & x"070" => data <= x"29";
when "11" & x"071" => data <= x"7f";
when "11" & x"072" => data <= x"48";
when "11" & x"073" => data <= x"20";
when "11" & x"074" => data <= x"a7";
when "11" & x"075" => data <= x"aa";
when "11" & x"076" => data <= x"18";
when "11" & x"077" => data <= x"68";
when "11" & x"078" => data <= x"6d";
when "11" & x"079" => data <= x"06";
when "11" & x"07a" => data <= x"0d";
when "11" & x"07b" => data <= x"8d";
when "11" & x"07c" => data <= x"23";
when "11" & x"07d" => data <= x"0d";
when "11" & x"07e" => data <= x"ad";
when "11" & x"07f" => data <= x"07";
when "11" & x"080" => data <= x"0d";
when "11" & x"081" => data <= x"69";
when "11" & x"082" => data <= x"00";
when "11" & x"083" => data <= x"8d";
when "11" & x"084" => data <= x"24";
when "11" & x"085" => data <= x"0d";
when "11" & x"086" => data <= x"ad";
when "11" & x"087" => data <= x"08";
when "11" & x"088" => data <= x"0d";
when "11" & x"089" => data <= x"69";
when "11" & x"08a" => data <= x"00";
when "11" & x"08b" => data <= x"8d";
when "11" & x"08c" => data <= x"25";
when "11" & x"08d" => data <= x"0d";
when "11" & x"08e" => data <= x"ad";
when "11" & x"08f" => data <= x"09";
when "11" & x"090" => data <= x"0d";
when "11" & x"091" => data <= x"69";
when "11" & x"092" => data <= x"00";
when "11" & x"093" => data <= x"8d";
when "11" & x"094" => data <= x"26";
when "11" & x"095" => data <= x"0d";
when "11" & x"096" => data <= x"60";
when "11" & x"097" => data <= x"29";
when "11" & x"098" => data <= x"fe";
when "11" & x"099" => data <= x"4a";
when "11" & x"09a" => data <= x"09";
when "11" & x"09b" => data <= x"80";
when "11" & x"09c" => data <= x"cd";
when "11" & x"09d" => data <= x"82";
when "11" & x"09e" => data <= x"10";
when "11" & x"09f" => data <= x"f0";
when "11" & x"0a0" => data <= x"f5";
when "11" & x"0a1" => data <= x"8d";
when "11" & x"0a2" => data <= x"82";
when "11" & x"0a3" => data <= x"10";
when "11" & x"0a4" => data <= x"48";
when "11" & x"0a5" => data <= x"20";
when "11" & x"0a6" => data <= x"1f";
when "11" & x"0a7" => data <= x"a6";
when "11" & x"0a8" => data <= x"68";
when "11" & x"0a9" => data <= x"20";
when "11" & x"0aa" => data <= x"70";
when "11" & x"0ab" => data <= x"b0";
when "11" & x"0ac" => data <= x"4c";
when "11" & x"0ad" => data <= x"99";
when "11" & x"0ae" => data <= x"a7";
when "11" & x"0af" => data <= x"8d";
when "11" & x"0b0" => data <= x"82";
when "11" & x"0b1" => data <= x"10";
when "11" & x"0b2" => data <= x"20";
when "11" & x"0b3" => data <= x"70";
when "11" & x"0b4" => data <= x"b0";
when "11" & x"0b5" => data <= x"4c";
when "11" & x"0b6" => data <= x"99";
when "11" & x"0b7" => data <= x"a7";
when "11" & x"0b8" => data <= x"20";
when "11" & x"0b9" => data <= x"1f";
when "11" & x"0ba" => data <= x"a6";
when "11" & x"0bb" => data <= x"ad";
when "11" & x"0bc" => data <= x"82";
when "11" & x"0bd" => data <= x"10";
when "11" & x"0be" => data <= x"20";
when "11" & x"0bf" => data <= x"70";
when "11" & x"0c0" => data <= x"b0";
when "11" & x"0c1" => data <= x"4c";
when "11" & x"0c2" => data <= x"b2";
when "11" & x"0c3" => data <= x"a7";
when "11" & x"0c4" => data <= x"ad";
when "11" & x"0c5" => data <= x"82";
when "11" & x"0c6" => data <= x"10";
when "11" & x"0c7" => data <= x"20";
when "11" & x"0c8" => data <= x"70";
when "11" & x"0c9" => data <= x"b0";
when "11" & x"0ca" => data <= x"4c";
when "11" & x"0cb" => data <= x"b2";
when "11" & x"0cc" => data <= x"a7";
when "11" & x"0cd" => data <= x"20";
when "11" & x"0ce" => data <= x"b8";
when "11" & x"0cf" => data <= x"b0";
when "11" & x"0d0" => data <= x"a2";
when "11" & x"0d1" => data <= x"03";
when "11" & x"0d2" => data <= x"20";
when "11" & x"0d3" => data <= x"d9";
when "11" & x"0d4" => data <= x"b0";
when "11" & x"0d5" => data <= x"ca";
when "11" & x"0d6" => data <= x"10";
when "11" & x"0d7" => data <= x"fa";
when "11" & x"0d8" => data <= x"60";
when "11" & x"0d9" => data <= x"bd";
when "11" & x"0da" => data <= x"10";
when "11" & x"0db" => data <= x"0d";
when "11" & x"0dc" => data <= x"30";
when "11" & x"0dd" => data <= x"2b";
when "11" & x"0de" => data <= x"49";
when "11" & x"0df" => data <= x"ff";
when "11" & x"0e0" => data <= x"dd";
when "11" & x"0e1" => data <= x"18";
when "11" & x"0e2" => data <= x"0d";
when "11" & x"0e3" => data <= x"d0";
when "11" & x"0e4" => data <= x"18";
when "11" & x"0e5" => data <= x"bd";
when "11" & x"0e6" => data <= x"0c";
when "11" & x"0e7" => data <= x"0d";
when "11" & x"0e8" => data <= x"49";
when "11" & x"0e9" => data <= x"ff";
when "11" & x"0ea" => data <= x"dd";
when "11" & x"0eb" => data <= x"14";
when "11" & x"0ec" => data <= x"0d";
when "11" & x"0ed" => data <= x"d0";
when "11" & x"0ee" => data <= x"0e";
when "11" & x"0ef" => data <= x"bd";
when "11" & x"0f0" => data <= x"10";
when "11" & x"0f1" => data <= x"0d";
when "11" & x"0f2" => data <= x"6a";
when "11" & x"0f3" => data <= x"bd";
when "11" & x"0f4" => data <= x"0c";
when "11" & x"0f5" => data <= x"0d";
when "11" & x"0f6" => data <= x"20";
when "11" & x"0f7" => data <= x"c1";
when "11" & x"0f8" => data <= x"af";
when "11" & x"0f9" => data <= x"f0";
when "11" & x"0fa" => data <= x"0b";
when "11" & x"0fb" => data <= x"10";
when "11" & x"0fc" => data <= x"07";
when "11" & x"0fd" => data <= x"a9";
when "11" & x"0fe" => data <= x"ff";
when "11" & x"0ff" => data <= x"9d";
when "11" & x"100" => data <= x"10";
when "11" & x"101" => data <= x"0d";
when "11" & x"102" => data <= x"d0";
when "11" & x"103" => data <= x"02";
when "11" & x"104" => data <= x"a9";
when "11" & x"105" => data <= x"54";
when "11" & x"106" => data <= x"9d";
when "11" & x"107" => data <= x"1c";
when "11" & x"108" => data <= x"0d";
when "11" & x"109" => data <= x"60";
when "11" & x"10a" => data <= x"a2";
when "11" & x"10b" => data <= x"00";
when "11" & x"10c" => data <= x"bd";
when "11" & x"10d" => data <= x"20";
when "11" & x"10e" => data <= x"b3";
when "11" & x"10f" => data <= x"9d";
when "11" & x"110" => data <= x"70";
when "11" & x"111" => data <= x"0d";
when "11" & x"112" => data <= x"e8";
when "11" & x"113" => data <= x"e0";
when "11" & x"114" => data <= x"0b";
when "11" & x"115" => data <= x"d0";
when "11" & x"116" => data <= x"f5";
when "11" & x"117" => data <= x"60";
when "11" & x"118" => data <= x"a2";
when "11" & x"119" => data <= x"6f";
when "11" & x"11a" => data <= x"a9";
when "11" & x"11b" => data <= x"00";
when "11" & x"11c" => data <= x"9d";
when "11" & x"11d" => data <= x"00";
when "11" & x"11e" => data <= x"0d";
when "11" & x"11f" => data <= x"ca";
when "11" & x"120" => data <= x"d0";
when "11" & x"121" => data <= x"fa";
when "11" & x"122" => data <= x"a9";
when "11" & x"123" => data <= x"40";
when "11" & x"124" => data <= x"9d";
when "11" & x"125" => data <= x"00";
when "11" & x"126" => data <= x"0d";
when "11" & x"127" => data <= x"60";
when "11" & x"128" => data <= x"20";
when "11" & x"129" => data <= x"0a";
when "11" & x"12a" => data <= x"b1";
when "11" & x"12b" => data <= x"20";
when "11" & x"12c" => data <= x"18";
when "11" & x"12d" => data <= x"b1";
when "11" & x"12e" => data <= x"a9";
when "11" & x"12f" => data <= x"ff";
when "11" & x"130" => data <= x"8d";
when "11" & x"131" => data <= x"52";
when "11" & x"132" => data <= x"0d";
when "11" & x"133" => data <= x"48";
when "11" & x"134" => data <= x"4c";
when "11" & x"135" => data <= x"3b";
when "11" & x"136" => data <= x"93";
when "11" & x"137" => data <= x"20";
when "11" & x"138" => data <= x"0a";
when "11" & x"139" => data <= x"b1";
when "11" & x"13a" => data <= x"20";
when "11" & x"13b" => data <= x"18";
when "11" & x"13c" => data <= x"b1";
when "11" & x"13d" => data <= x"a9";
when "11" & x"13e" => data <= x"80";
when "11" & x"13f" => data <= x"20";
when "11" & x"140" => data <= x"a1";
when "11" & x"141" => data <= x"b0";
when "11" & x"142" => data <= x"a2";
when "11" & x"143" => data <= x"00";
when "11" & x"144" => data <= x"ad";
when "11" & x"145" => data <= x"52";
when "11" & x"146" => data <= x"0d";
when "11" & x"147" => data <= x"c9";
when "11" & x"148" => data <= x"42";
when "11" & x"149" => data <= x"f0";
when "11" & x"14a" => data <= x"16";
when "11" & x"14b" => data <= x"bd";
when "11" & x"14c" => data <= x"10";
when "11" & x"14d" => data <= x"0d";
when "11" & x"14e" => data <= x"30";
when "11" & x"14f" => data <= x"43";
when "11" & x"150" => data <= x"49";
when "11" & x"151" => data <= x"ff";
when "11" & x"152" => data <= x"dd";
when "11" & x"153" => data <= x"18";
when "11" & x"154" => data <= x"0d";
when "11" & x"155" => data <= x"d0";
when "11" & x"156" => data <= x"0a";
when "11" & x"157" => data <= x"bd";
when "11" & x"158" => data <= x"0c";
when "11" & x"159" => data <= x"0d";
when "11" & x"15a" => data <= x"49";
when "11" & x"15b" => data <= x"ff";
when "11" & x"15c" => data <= x"dd";
when "11" & x"15d" => data <= x"14";
when "11" & x"15e" => data <= x"0d";
when "11" & x"15f" => data <= x"f0";
when "11" & x"160" => data <= x"16";
when "11" & x"161" => data <= x"bd";
when "11" & x"162" => data <= x"00";
when "11" & x"163" => data <= x"0e";
when "11" & x"164" => data <= x"9d";
when "11" & x"165" => data <= x"0c";
when "11" & x"166" => data <= x"0d";
when "11" & x"167" => data <= x"49";
when "11" & x"168" => data <= x"ff";
when "11" & x"169" => data <= x"9d";
when "11" & x"16a" => data <= x"14";
when "11" & x"16b" => data <= x"0d";
when "11" & x"16c" => data <= x"bd";
when "11" & x"16d" => data <= x"04";
when "11" & x"16e" => data <= x"0e";
when "11" & x"16f" => data <= x"9d";
when "11" & x"170" => data <= x"10";
when "11" & x"171" => data <= x"0d";
when "11" & x"172" => data <= x"49";
when "11" & x"173" => data <= x"ff";
when "11" & x"174" => data <= x"9d";
when "11" & x"175" => data <= x"18";
when "11" & x"176" => data <= x"0d";
when "11" & x"177" => data <= x"8a";
when "11" & x"178" => data <= x"f0";
when "11" & x"179" => data <= x"1e";
when "11" & x"17a" => data <= x"a8";
when "11" & x"17b" => data <= x"88";
when "11" & x"17c" => data <= x"bd";
when "11" & x"17d" => data <= x"10";
when "11" & x"17e" => data <= x"0d";
when "11" & x"17f" => data <= x"30";
when "11" & x"180" => data <= x"17";
when "11" & x"181" => data <= x"d9";
when "11" & x"182" => data <= x"10";
when "11" & x"183" => data <= x"0d";
when "11" & x"184" => data <= x"d0";
when "11" & x"185" => data <= x"08";
when "11" & x"186" => data <= x"bd";
when "11" & x"187" => data <= x"0c";
when "11" & x"188" => data <= x"0d";
when "11" & x"189" => data <= x"d9";
when "11" & x"18a" => data <= x"0c";
when "11" & x"18b" => data <= x"0d";
when "11" & x"18c" => data <= x"f0";
when "11" & x"18d" => data <= x"05";
when "11" & x"18e" => data <= x"88";
when "11" & x"18f" => data <= x"10";
when "11" & x"190" => data <= x"eb";
when "11" & x"191" => data <= x"30";
when "11" & x"192" => data <= x"05";
when "11" & x"193" => data <= x"a9";
when "11" & x"194" => data <= x"ff";
when "11" & x"195" => data <= x"9d";
when "11" & x"196" => data <= x"10";
when "11" & x"197" => data <= x"0d";
when "11" & x"198" => data <= x"e8";
when "11" & x"199" => data <= x"e0";
when "11" & x"19a" => data <= x"04";
when "11" & x"19b" => data <= x"d0";
when "11" & x"19c" => data <= x"a7";
when "11" & x"19d" => data <= x"4c";
when "11" & x"19e" => data <= x"d0";
when "11" & x"19f" => data <= x"b0";
when "11" & x"1a0" => data <= x"08";
when "11" & x"1a1" => data <= x"48";
when "11" & x"1a2" => data <= x"8d";
when "11" & x"1a3" => data <= x"53";
when "11" & x"1a4" => data <= x"0d";
when "11" & x"1a5" => data <= x"a9";
when "11" & x"1a6" => data <= x"00";
when "11" & x"1a7" => data <= x"2a";
when "11" & x"1a8" => data <= x"8d";
when "11" & x"1a9" => data <= x"54";
when "11" & x"1aa" => data <= x"0d";
when "11" & x"1ab" => data <= x"68";
when "11" & x"1ac" => data <= x"28";
when "11" & x"1ad" => data <= x"08";
when "11" & x"1ae" => data <= x"48";
when "11" & x"1af" => data <= x"20";
when "11" & x"1b0" => data <= x"6c";
when "11" & x"1b1" => data <= x"ad";
when "11" & x"1b2" => data <= x"8e";
when "11" & x"1b3" => data <= x"55";
when "11" & x"1b4" => data <= x"0d";
when "11" & x"1b5" => data <= x"8d";
when "11" & x"1b6" => data <= x"56";
when "11" & x"1b7" => data <= x"0d";
when "11" & x"1b8" => data <= x"68";
when "11" & x"1b9" => data <= x"28";
when "11" & x"1ba" => data <= x"20";
when "11" & x"1bb" => data <= x"ad";
when "11" & x"1bc" => data <= x"af";
when "11" & x"1bd" => data <= x"29";
when "11" & x"1be" => data <= x"f0";
when "11" & x"1bf" => data <= x"85";
when "11" & x"1c0" => data <= x"f2";
when "11" & x"1c1" => data <= x"98";
when "11" & x"1c2" => data <= x"29";
when "11" & x"1c3" => data <= x"01";
when "11" & x"1c4" => data <= x"09";
when "11" & x"1c5" => data <= x"0e";
when "11" & x"1c6" => data <= x"85";
when "11" & x"1c7" => data <= x"f3";
when "11" & x"1c8" => data <= x"98";
when "11" & x"1c9" => data <= x"29";
when "11" & x"1ca" => data <= x"fe";
when "11" & x"1cb" => data <= x"4a";
when "11" & x"1cc" => data <= x"09";
when "11" & x"1cd" => data <= x"80";
when "11" & x"1ce" => data <= x"8d";
when "11" & x"1cf" => data <= x"52";
when "11" & x"1d0" => data <= x"0d";
when "11" & x"1d1" => data <= x"20";
when "11" & x"1d2" => data <= x"9c";
when "11" & x"1d3" => data <= x"b0";
when "11" & x"1d4" => data <= x"4c";
when "11" & x"1d5" => data <= x"35";
when "11" & x"1d6" => data <= x"b2";
when "11" & x"1d7" => data <= x"a9";
when "11" & x"1d8" => data <= x"00";
when "11" & x"1d9" => data <= x"8d";
when "11" & x"1da" => data <= x"55";
when "11" & x"1db" => data <= x"0d";
when "11" & x"1dc" => data <= x"8d";
when "11" & x"1dd" => data <= x"56";
when "11" & x"1de" => data <= x"0d";
when "11" & x"1df" => data <= x"8d";
when "11" & x"1e0" => data <= x"53";
when "11" & x"1e1" => data <= x"0d";
when "11" & x"1e2" => data <= x"8d";
when "11" & x"1e3" => data <= x"54";
when "11" & x"1e4" => data <= x"0d";
when "11" & x"1e5" => data <= x"a9";
when "11" & x"1e6" => data <= x"10";
when "11" & x"1e7" => data <= x"85";
when "11" & x"1e8" => data <= x"f2";
when "11" & x"1e9" => data <= x"a9";
when "11" & x"1ea" => data <= x"0e";
when "11" & x"1eb" => data <= x"85";
when "11" & x"1ec" => data <= x"f3";
when "11" & x"1ed" => data <= x"a9";
when "11" & x"1ee" => data <= x"80";
when "11" & x"1ef" => data <= x"8d";
when "11" & x"1f0" => data <= x"52";
when "11" & x"1f1" => data <= x"0d";
when "11" & x"1f2" => data <= x"20";
when "11" & x"1f3" => data <= x"9c";
when "11" & x"1f4" => data <= x"b0";
when "11" & x"1f5" => data <= x"4c";
when "11" & x"1f6" => data <= x"35";
when "11" & x"1f7" => data <= x"b2";
when "11" & x"1f8" => data <= x"c9";
when "11" & x"1f9" => data <= x"ff";
when "11" & x"1fa" => data <= x"f0";
when "11" & x"1fb" => data <= x"41";
when "11" & x"1fc" => data <= x"18";
when "11" & x"1fd" => data <= x"a5";
when "11" & x"1fe" => data <= x"f2";
when "11" & x"1ff" => data <= x"69";
when "11" & x"200" => data <= x"10";
when "11" & x"201" => data <= x"85";
when "11" & x"202" => data <= x"f2";
when "11" & x"203" => data <= x"d0";
when "11" & x"204" => data <= x"18";
when "11" & x"205" => data <= x"a5";
when "11" & x"206" => data <= x"f3";
when "11" & x"207" => data <= x"49";
when "11" & x"208" => data <= x"01";
when "11" & x"209" => data <= x"85";
when "11" & x"20a" => data <= x"f3";
when "11" & x"20b" => data <= x"6a";
when "11" & x"20c" => data <= x"b0";
when "11" & x"20d" => data <= x"0f";
when "11" & x"20e" => data <= x"ad";
when "11" & x"20f" => data <= x"52";
when "11" & x"210" => data <= x"0d";
when "11" & x"211" => data <= x"69";
when "11" & x"212" => data <= x"01";
when "11" & x"213" => data <= x"c9";
when "11" & x"214" => data <= x"90";
when "11" & x"215" => data <= x"f0";
when "11" & x"216" => data <= x"26";
when "11" & x"217" => data <= x"8d";
when "11" & x"218" => data <= x"52";
when "11" & x"219" => data <= x"0d";
when "11" & x"21a" => data <= x"20";
when "11" & x"21b" => data <= x"9c";
when "11" & x"21c" => data <= x"b0";
when "11" & x"21d" => data <= x"ee";
when "11" & x"21e" => data <= x"53";
when "11" & x"21f" => data <= x"0d";
when "11" & x"220" => data <= x"d0";
when "11" & x"221" => data <= x"03";
when "11" & x"222" => data <= x"ee";
when "11" & x"223" => data <= x"54";
when "11" & x"224" => data <= x"0d";
when "11" & x"225" => data <= x"f8";
when "11" & x"226" => data <= x"18";
when "11" & x"227" => data <= x"ad";
when "11" & x"228" => data <= x"55";
when "11" & x"229" => data <= x"0d";
when "11" & x"22a" => data <= x"69";
when "11" & x"22b" => data <= x"01";
when "11" & x"22c" => data <= x"8d";
when "11" & x"22d" => data <= x"55";
when "11" & x"22e" => data <= x"0d";
when "11" & x"22f" => data <= x"90";
when "11" & x"230" => data <= x"03";
when "11" & x"231" => data <= x"ee";
when "11" & x"232" => data <= x"56";
when "11" & x"233" => data <= x"0d";
when "11" & x"234" => data <= x"d8";
when "11" & x"235" => data <= x"a0";
when "11" & x"236" => data <= x"0f";
when "11" & x"237" => data <= x"b1";
when "11" & x"238" => data <= x"f2";
when "11" & x"239" => data <= x"30";
when "11" & x"23a" => data <= x"bd";
when "11" & x"23b" => data <= x"18";
when "11" & x"23c" => data <= x"60";
when "11" & x"23d" => data <= x"a9";
when "11" & x"23e" => data <= x"ff";
when "11" & x"23f" => data <= x"8d";
when "11" & x"240" => data <= x"54";
when "11" & x"241" => data <= x"0d";
when "11" & x"242" => data <= x"38";
when "11" & x"243" => data <= x"60";
when "11" & x"244" => data <= x"20";
when "11" & x"245" => data <= x"1f";
when "11" & x"246" => data <= x"a6";
when "11" & x"247" => data <= x"a9";
when "11" & x"248" => data <= x"80";
when "11" & x"249" => data <= x"8d";
when "11" & x"24a" => data <= x"52";
when "11" & x"24b" => data <= x"0d";
when "11" & x"24c" => data <= x"20";
when "11" & x"24d" => data <= x"af";
when "11" & x"24e" => data <= x"b0";
when "11" & x"24f" => data <= x"a9";
when "11" & x"250" => data <= x"10";
when "11" & x"251" => data <= x"85";
when "11" & x"252" => data <= x"f2";
when "11" & x"253" => data <= x"a9";
when "11" & x"254" => data <= x"0e";
when "11" & x"255" => data <= x"85";
when "11" & x"256" => data <= x"f3";
when "11" & x"257" => data <= x"20";
when "11" & x"258" => data <= x"a7";
when "11" & x"259" => data <= x"aa";
when "11" & x"25a" => data <= x"18";
when "11" & x"25b" => data <= x"ad";
when "11" & x"25c" => data <= x"06";
when "11" & x"25d" => data <= x"0d";
when "11" & x"25e" => data <= x"69";
when "11" & x"25f" => data <= x"10";
when "11" & x"260" => data <= x"8d";
when "11" & x"261" => data <= x"23";
when "11" & x"262" => data <= x"0d";
when "11" & x"263" => data <= x"ad";
when "11" & x"264" => data <= x"07";
when "11" & x"265" => data <= x"0d";
when "11" & x"266" => data <= x"69";
when "11" & x"267" => data <= x"00";
when "11" & x"268" => data <= x"8d";
when "11" & x"269" => data <= x"24";
when "11" & x"26a" => data <= x"0d";
when "11" & x"26b" => data <= x"ad";
when "11" & x"26c" => data <= x"08";
when "11" & x"26d" => data <= x"0d";
when "11" & x"26e" => data <= x"69";
when "11" & x"26f" => data <= x"00";
when "11" & x"270" => data <= x"8d";
when "11" & x"271" => data <= x"25";
when "11" & x"272" => data <= x"0d";
when "11" & x"273" => data <= x"ad";
when "11" & x"274" => data <= x"09";
when "11" & x"275" => data <= x"0d";
when "11" & x"276" => data <= x"69";
when "11" & x"277" => data <= x"00";
when "11" & x"278" => data <= x"8d";
when "11" & x"279" => data <= x"09";
when "11" & x"27a" => data <= x"0d";
when "11" & x"27b" => data <= x"20";
when "11" & x"27c" => data <= x"1e";
when "11" & x"27d" => data <= x"a9";
when "11" & x"27e" => data <= x"a0";
when "11" & x"27f" => data <= x"0f";
when "11" & x"280" => data <= x"b1";
when "11" & x"281" => data <= x"f2";
when "11" & x"282" => data <= x"c9";
when "11" & x"283" => data <= x"ff";
when "11" & x"284" => data <= x"f0";
when "11" & x"285" => data <= x"39";
when "11" & x"286" => data <= x"20";
when "11" & x"287" => data <= x"24";
when "11" & x"288" => data <= x"a9";
when "11" & x"289" => data <= x"a0";
when "11" & x"28a" => data <= x"0b";
when "11" & x"28b" => data <= x"b9";
when "11" & x"28c" => data <= x"5f";
when "11" & x"28d" => data <= x"0d";
when "11" & x"28e" => data <= x"91";
when "11" & x"28f" => data <= x"f2";
when "11" & x"290" => data <= x"88";
when "11" & x"291" => data <= x"10";
when "11" & x"292" => data <= x"f8";
when "11" & x"293" => data <= x"18";
when "11" & x"294" => data <= x"a5";
when "11" & x"295" => data <= x"f2";
when "11" & x"296" => data <= x"69";
when "11" & x"297" => data <= x"10";
when "11" & x"298" => data <= x"85";
when "11" & x"299" => data <= x"f2";
when "11" & x"29a" => data <= x"d0";
when "11" & x"29b" => data <= x"e2";
when "11" & x"29c" => data <= x"a5";
when "11" & x"29d" => data <= x"f3";
when "11" & x"29e" => data <= x"49";
when "11" & x"29f" => data <= x"01";
when "11" & x"2a0" => data <= x"85";
when "11" & x"2a1" => data <= x"f3";
when "11" & x"2a2" => data <= x"6a";
when "11" & x"2a3" => data <= x"b0";
when "11" & x"2a4" => data <= x"d9";
when "11" & x"2a5" => data <= x"20";
when "11" & x"2a6" => data <= x"c4";
when "11" & x"2a7" => data <= x"b0";
when "11" & x"2a8" => data <= x"18";
when "11" & x"2a9" => data <= x"ad";
when "11" & x"2aa" => data <= x"52";
when "11" & x"2ab" => data <= x"0d";
when "11" & x"2ac" => data <= x"69";
when "11" & x"2ad" => data <= x"01";
when "11" & x"2ae" => data <= x"c9";
when "11" & x"2af" => data <= x"90";
when "11" & x"2b0" => data <= x"f0";
when "11" & x"2b1" => data <= x"18";
when "11" & x"2b2" => data <= x"8d";
when "11" & x"2b3" => data <= x"52";
when "11" & x"2b4" => data <= x"0d";
when "11" & x"2b5" => data <= x"24";
when "11" & x"2b6" => data <= x"ff";
when "11" & x"2b7" => data <= x"30";
when "11" & x"2b8" => data <= x"12";
when "11" & x"2b9" => data <= x"20";
when "11" & x"2ba" => data <= x"af";
when "11" & x"2bb" => data <= x"b0";
when "11" & x"2bc" => data <= x"4c";
when "11" & x"2bd" => data <= x"7e";
when "11" & x"2be" => data <= x"b2";
when "11" & x"2bf" => data <= x"a5";
when "11" & x"2c0" => data <= x"f2";
when "11" & x"2c1" => data <= x"d0";
when "11" & x"2c2" => data <= x"04";
when "11" & x"2c3" => data <= x"66";
when "11" & x"2c4" => data <= x"f3";
when "11" & x"2c5" => data <= x"90";
when "11" & x"2c6" => data <= x"03";
when "11" & x"2c7" => data <= x"20";
when "11" & x"2c8" => data <= x"c4";
when "11" & x"2c9" => data <= x"b0";
when "11" & x"2ca" => data <= x"60";
when "11" & x"2cb" => data <= x"4c";
when "11" & x"2cc" => data <= x"82";
when "11" & x"2cd" => data <= x"a0";
when "11" & x"2ce" => data <= x"a2";
when "11" & x"2cf" => data <= x"0b";
when "11" & x"2d0" => data <= x"a9";
when "11" & x"2d1" => data <= x"00";
when "11" & x"2d2" => data <= x"20";
when "11" & x"2d3" => data <= x"c6";
when "11" & x"2d4" => data <= x"88";
when "11" & x"2d5" => data <= x"9d";
when "11" & x"2d6" => data <= x"5f";
when "11" & x"2d7" => data <= x"0d";
when "11" & x"2d8" => data <= x"ca";
when "11" & x"2d9" => data <= x"10";
when "11" & x"2da" => data <= x"f7";
when "11" & x"2db" => data <= x"e8";
when "11" & x"2dc" => data <= x"20";
when "11" & x"2dd" => data <= x"c5";
when "11" & x"2de" => data <= x"ff";
when "11" & x"2df" => data <= x"b0";
when "11" & x"2e0" => data <= x"0a";
when "11" & x"2e1" => data <= x"20";
when "11" & x"2e2" => data <= x"c6";
when "11" & x"2e3" => data <= x"88";
when "11" & x"2e4" => data <= x"9d";
when "11" & x"2e5" => data <= x"5f";
when "11" & x"2e6" => data <= x"0d";
when "11" & x"2e7" => data <= x"e0";
when "11" & x"2e8" => data <= x"0b";
when "11" & x"2e9" => data <= x"90";
when "11" & x"2ea" => data <= x"f0";
when "11" & x"2eb" => data <= x"20";
when "11" & x"2ec" => data <= x"b4";
when "11" & x"2ed" => data <= x"8a";
when "11" & x"2ee" => data <= x"ae";
when "11" & x"2ef" => data <= x"82";
when "11" & x"2f0" => data <= x"10";
when "11" & x"2f1" => data <= x"bd";
when "11" & x"2f2" => data <= x"10";
when "11" & x"2f3" => data <= x"0d";
when "11" & x"2f4" => data <= x"6a";
when "11" & x"2f5" => data <= x"bd";
when "11" & x"2f6" => data <= x"0c";
when "11" & x"2f7" => data <= x"0d";
when "11" & x"2f8" => data <= x"20";
when "11" & x"2f9" => data <= x"ad";
when "11" & x"2fa" => data <= x"af";
when "11" & x"2fb" => data <= x"29";
when "11" & x"2fc" => data <= x"f0";
when "11" & x"2fd" => data <= x"48";
when "11" & x"2fe" => data <= x"98";
when "11" & x"2ff" => data <= x"48";
when "11" & x"300" => data <= x"29";
when "11" & x"301" => data <= x"fe";
when "11" & x"302" => data <= x"4a";
when "11" & x"303" => data <= x"09";
when "11" & x"304" => data <= x"80";
when "11" & x"305" => data <= x"20";
when "11" & x"306" => data <= x"a1";
when "11" & x"307" => data <= x"b0";
when "11" & x"308" => data <= x"68";
when "11" & x"309" => data <= x"18";
when "11" & x"30a" => data <= x"29";
when "11" & x"30b" => data <= x"01";
when "11" & x"30c" => data <= x"69";
when "11" & x"30d" => data <= x"0e";
when "11" & x"30e" => data <= x"85";
when "11" & x"30f" => data <= x"f3";
when "11" & x"310" => data <= x"68";
when "11" & x"311" => data <= x"85";
when "11" & x"312" => data <= x"f2";
when "11" & x"313" => data <= x"a0";
when "11" & x"314" => data <= x"0b";
when "11" & x"315" => data <= x"b9";
when "11" & x"316" => data <= x"5f";
when "11" & x"317" => data <= x"0d";
when "11" & x"318" => data <= x"91";
when "11" & x"319" => data <= x"f2";
when "11" & x"31a" => data <= x"88";
when "11" & x"31b" => data <= x"10";
when "11" & x"31c" => data <= x"f8";
when "11" & x"31d" => data <= x"4c";
when "11" & x"31e" => data <= x"b8";
when "11" & x"31f" => data <= x"b0";
when "11" & x"320" => data <= x"42";
when "11" & x"321" => data <= x"45";
when "11" & x"322" => data <= x"45";
when "11" & x"323" => data <= x"42";
when "11" & x"324" => data <= x"20";
when "11" & x"325" => data <= x"20";
when "11" & x"326" => data <= x"20";
when "11" & x"327" => data <= x"20";
when "11" & x"328" => data <= x"4d";
when "11" & x"329" => data <= x"4d";
when "11" & x"32a" => data <= x"42";
when "11" & x"32b" => data <= x"44";
when "11" & x"32c" => data <= x"49";
when "11" & x"32d" => data <= x"4e";
when "11" & x"32e" => data <= x"b8";
when "11" & x"32f" => data <= x"05";
when "11" & x"330" => data <= x"12";
when "11" & x"331" => data <= x"44";
when "11" & x"332" => data <= x"42";
when "11" & x"333" => data <= x"4f";
when "11" & x"334" => data <= x"4f";
when "11" & x"335" => data <= x"54";
when "11" & x"336" => data <= x"b7";
when "11" & x"337" => data <= x"fa";
when "11" & x"338" => data <= x"02";
when "11" & x"339" => data <= x"44";
when "11" & x"33a" => data <= x"43";
when "11" & x"33b" => data <= x"41";
when "11" & x"33c" => data <= x"54";
when "11" & x"33d" => data <= x"b8";
when "11" & x"33e" => data <= x"0b";
when "11" & x"33f" => data <= x"04";
when "11" & x"340" => data <= x"44";
when "11" & x"341" => data <= x"44";
when "11" & x"342" => data <= x"49";
when "11" & x"343" => data <= x"53";
when "11" & x"344" => data <= x"4b";
when "11" & x"345" => data <= x"53";
when "11" & x"346" => data <= x"b9";
when "11" & x"347" => data <= x"bb";
when "11" & x"348" => data <= x"01";
when "11" & x"349" => data <= x"44";
when "11" & x"34a" => data <= x"4c";
when "11" & x"34b" => data <= x"4f";
when "11" & x"34c" => data <= x"43";
when "11" & x"34d" => data <= x"4b";
when "11" & x"34e" => data <= x"ba";
when "11" & x"34f" => data <= x"01";
when "11" & x"350" => data <= x"02";
when "11" & x"351" => data <= x"44";
when "11" & x"352" => data <= x"55";
when "11" & x"353" => data <= x"4e";
when "11" & x"354" => data <= x"4c";
when "11" & x"355" => data <= x"4f";
when "11" & x"356" => data <= x"43";
when "11" & x"357" => data <= x"4b";
when "11" & x"358" => data <= x"ba";
when "11" & x"359" => data <= x"05";
when "11" & x"35a" => data <= x"02";
when "11" & x"35b" => data <= x"44";
when "11" & x"35c" => data <= x"46";
when "11" & x"35d" => data <= x"52";
when "11" & x"35e" => data <= x"45";
when "11" & x"35f" => data <= x"45";
when "11" & x"360" => data <= x"b8";
when "11" & x"361" => data <= x"f5";
when "11" & x"362" => data <= x"00";
when "11" & x"363" => data <= x"44";
when "11" & x"364" => data <= x"4b";
when "11" & x"365" => data <= x"49";
when "11" & x"366" => data <= x"4c";
when "11" & x"367" => data <= x"4c";
when "11" & x"368" => data <= x"ba";
when "11" & x"369" => data <= x"28";
when "11" & x"36a" => data <= x"03";
when "11" & x"36b" => data <= x"44";
when "11" & x"36c" => data <= x"52";
when "11" & x"36d" => data <= x"45";
when "11" & x"36e" => data <= x"53";
when "11" & x"36f" => data <= x"54";
when "11" & x"370" => data <= x"4f";
when "11" & x"371" => data <= x"52";
when "11" & x"372" => data <= x"45";
when "11" & x"373" => data <= x"ba";
when "11" & x"374" => data <= x"6b";
when "11" & x"375" => data <= x"03";
when "11" & x"376" => data <= x"44";
when "11" & x"377" => data <= x"4e";
when "11" & x"378" => data <= x"45";
when "11" & x"379" => data <= x"57";
when "11" & x"37a" => data <= x"ba";
when "11" & x"37b" => data <= x"c0";
when "11" & x"37c" => data <= x"01";
when "11" & x"37d" => data <= x"44";
when "11" & x"37e" => data <= x"46";
when "11" & x"37f" => data <= x"4f";
when "11" & x"380" => data <= x"52";
when "11" & x"381" => data <= x"4d";
when "11" & x"382" => data <= x"ba";
when "11" & x"383" => data <= x"63";
when "11" & x"384" => data <= x"03";
when "11" & x"385" => data <= x"44";
when "11" & x"386" => data <= x"4f";
when "11" & x"387" => data <= x"4e";
when "11" & x"388" => data <= x"42";
when "11" & x"389" => data <= x"4f";
when "11" & x"38a" => data <= x"4f";
when "11" & x"38b" => data <= x"54";
when "11" & x"38c" => data <= x"bb";
when "11" & x"38d" => data <= x"8e";
when "11" & x"38e" => data <= x"52";
when "11" & x"38f" => data <= x"44";
when "11" & x"390" => data <= x"52";
when "11" & x"391" => data <= x"45";
when "11" & x"392" => data <= x"43";
when "11" & x"393" => data <= x"41";
when "11" & x"394" => data <= x"54";
when "11" & x"395" => data <= x"b2";
when "11" & x"396" => data <= x"43";
when "11" & x"397" => data <= x"00";
when "11" & x"398" => data <= x"44";
when "11" & x"399" => data <= x"52";
when "11" & x"39a" => data <= x"4f";
when "11" & x"39b" => data <= x"4d";
when "11" & x"39c" => data <= x"bc";
when "11" & x"39d" => data <= x"1a";
when "11" & x"39e" => data <= x"86";
when "11" & x"39f" => data <= x"42";
when "11" & x"3a0" => data <= x"45";
when "11" & x"3a1" => data <= x"45";
when "11" & x"3a2" => data <= x"42";
when "11" & x"3a3" => data <= x"bb";
when "11" & x"3a4" => data <= x"a9";
when "11" & x"3a5" => data <= x"03";
when "11" & x"3a6" => data <= x"44";
when "11" & x"3a7" => data <= x"47";
when "11" & x"3a8" => data <= x"45";
when "11" & x"3a9" => data <= x"54";
when "11" & x"3aa" => data <= x"bc";
when "11" & x"3ab" => data <= x"14";
when "11" & x"3ac" => data <= x"00";
when "11" & x"3ad" => data <= x"44";
when "11" & x"3ae" => data <= x"50";
when "11" & x"3af" => data <= x"55";
when "11" & x"3b0" => data <= x"54";
when "11" & x"3b1" => data <= x"bc";
when "11" & x"3b2" => data <= x"17";
when "11" & x"3b3" => data <= x"00";
when "11" & x"3b4" => data <= x"44";
when "11" & x"3b5" => data <= x"41";
when "11" & x"3b6" => data <= x"42";
when "11" & x"3b7" => data <= x"4f";
when "11" & x"3b8" => data <= x"55";
when "11" & x"3b9" => data <= x"54";
when "11" & x"3ba" => data <= x"b4";
when "11" & x"3bb" => data <= x"32";
when "11" & x"3bc" => data <= x"00";
when "11" & x"3bd" => data <= x"87";
when "11" & x"3be" => data <= x"d6";
when "11" & x"3bf" => data <= x"00";
when "11" & x"3c0" => data <= x"44";
when "11" & x"3c1" => data <= x"55";
when "11" & x"3c2" => data <= x"54";
when "11" & x"3c3" => data <= x"49";
when "11" & x"3c4" => data <= x"4c";
when "11" & x"3c5" => data <= x"53";
when "11" & x"3c6" => data <= x"b4";
when "11" & x"3c7" => data <= x"03";
when "11" & x"3c8" => data <= x"00";
when "11" & x"3c9" => data <= x"b3";
when "11" & x"3ca" => data <= x"f5";
when "11" & x"3cb" => data <= x"00";
when "11" & x"3cc" => data <= x"a2";
when "11" & x"3cd" => data <= x"a0";
when "11" & x"3ce" => data <= x"b1";
when "11" & x"3cf" => data <= x"f2";
when "11" & x"3d0" => data <= x"c9";
when "11" & x"3d1" => data <= x"0d";
when "11" & x"3d2" => data <= x"d0";
when "11" & x"3d3" => data <= x"16";
when "11" & x"3d4" => data <= x"98";
when "11" & x"3d5" => data <= x"e8";
when "11" & x"3d6" => data <= x"a0";
when "11" & x"3d7" => data <= x"02";
when "11" & x"3d8" => data <= x"20";
when "11" & x"3d9" => data <= x"cb";
when "11" & x"3da" => data <= x"99";
when "11" & x"3db" => data <= x"20";
when "11" & x"3dc" => data <= x"44";
when "11" & x"3dd" => data <= x"b6";
when "11" & x"3de" => data <= x"20";
when "11" & x"3df" => data <= x"20";
when "11" & x"3e0" => data <= x"44";
when "11" & x"3e1" => data <= x"55";
when "11" & x"3e2" => data <= x"54";
when "11" & x"3e3" => data <= x"49";
when "11" & x"3e4" => data <= x"4c";
when "11" & x"3e5" => data <= x"53";
when "11" & x"3e6" => data <= x"00";
when "11" & x"3e7" => data <= x"4c";
when "11" & x"3e8" => data <= x"e7";
when "11" & x"3e9" => data <= x"ff";
when "11" & x"3ea" => data <= x"98";
when "11" & x"3eb" => data <= x"48";
when "11" & x"3ec" => data <= x"20";
when "11" & x"3ed" => data <= x"71";
when "11" & x"3ee" => data <= x"86";
when "11" & x"3ef" => data <= x"68";
when "11" & x"3f0" => data <= x"a8";
when "11" & x"3f1" => data <= x"a2";
when "11" & x"3f2" => data <= x"92";
when "11" & x"3f3" => data <= x"4c";
when "11" & x"3f4" => data <= x"6e";
when "11" & x"3f5" => data <= x"b4";
when "11" & x"3f6" => data <= x"c8";
when "11" & x"3f7" => data <= x"b1";
when "11" & x"3f8" => data <= x"f2";
when "11" & x"3f9" => data <= x"c9";
when "11" & x"3fa" => data <= x"0d";
when "11" & x"3fb" => data <= x"f0";
when "11" & x"3fc" => data <= x"06";
when "11" & x"3fd" => data <= x"c9";
when "11" & x"3fe" => data <= x"20";
when "11" & x"3ff" => data <= x"f0";
when "11" & x"400" => data <= x"f0";
when "11" & x"401" => data <= x"d0";
when "11" & x"402" => data <= x"f3";
when "11" & x"403" => data <= x"60";
when "11" & x"404" => data <= x"20";
when "11" & x"405" => data <= x"e7";
when "11" & x"406" => data <= x"ff";
when "11" & x"407" => data <= x"20";
when "11" & x"408" => data <= x"44";
when "11" & x"409" => data <= x"b6";
when "11" & x"40a" => data <= x"53";
when "11" & x"40b" => data <= x"50";
when "11" & x"40c" => data <= x"49";
when "11" & x"40d" => data <= x"20";
when "11" & x"40e" => data <= x"30";
when "11" & x"40f" => data <= x"2e";
when "11" & x"410" => data <= x"30";
when "11" & x"411" => data <= x"31";
when "11" & x"412" => data <= x"00";
when "11" & x"413" => data <= x"20";
when "11" & x"414" => data <= x"e7";
when "11" & x"415" => data <= x"ff";
when "11" & x"416" => data <= x"a2";
when "11" & x"417" => data <= x"00";
when "11" & x"418" => data <= x"a9";
when "11" & x"419" => data <= x"11";
when "11" & x"41a" => data <= x"86";
when "11" & x"41b" => data <= x"b5";
when "11" & x"41c" => data <= x"85";
when "11" & x"41d" => data <= x"bf";
when "11" & x"41e" => data <= x"a2";
when "11" & x"41f" => data <= x"00";
when "11" & x"420" => data <= x"a9";
when "11" & x"421" => data <= x"20";
when "11" & x"422" => data <= x"20";
when "11" & x"423" => data <= x"ee";
when "11" & x"424" => data <= x"ff";
when "11" & x"425" => data <= x"20";
when "11" & x"426" => data <= x"ee";
when "11" & x"427" => data <= x"ff";
when "11" & x"428" => data <= x"20";
when "11" & x"429" => data <= x"08";
when "11" & x"42a" => data <= x"b7";
when "11" & x"42b" => data <= x"20";
when "11" & x"42c" => data <= x"e7";
when "11" & x"42d" => data <= x"ff";
when "11" & x"42e" => data <= x"c6";
when "11" & x"42f" => data <= x"bf";
when "11" & x"430" => data <= x"d0";
when "11" & x"431" => data <= x"ee";
when "11" & x"432" => data <= x"60";
when "11" & x"433" => data <= x"20";
when "11" & x"434" => data <= x"44";
when "11" & x"435" => data <= x"b6";
when "11" & x"436" => data <= x"44";
when "11" & x"437" => data <= x"55";
when "11" & x"438" => data <= x"54";
when "11" & x"439" => data <= x"49";
when "11" & x"43a" => data <= x"4c";
when "11" & x"43b" => data <= x"53";
when "11" & x"43c" => data <= x"20";
when "11" & x"43d" => data <= x"62";
when "11" & x"43e" => data <= x"79";
when "11" & x"43f" => data <= x"20";
when "11" & x"440" => data <= x"4d";
when "11" & x"441" => data <= x"61";
when "11" & x"442" => data <= x"72";
when "11" & x"443" => data <= x"74";
when "11" & x"444" => data <= x"69";
when "11" & x"445" => data <= x"6e";
when "11" & x"446" => data <= x"20";
when "11" & x"447" => data <= x"4d";
when "11" & x"448" => data <= x"61";
when "11" & x"449" => data <= x"74";
when "11" & x"44a" => data <= x"68";
when "11" & x"44b" => data <= x"65";
when "11" & x"44c" => data <= x"72";
when "11" & x"44d" => data <= x"20";
when "11" & x"44e" => data <= x"0a";
when "11" & x"44f" => data <= x"0d";
when "11" & x"450" => data <= x"4d";
when "11" & x"451" => data <= x"4f";
when "11" & x"452" => data <= x"44";
when "11" & x"453" => data <= x"49";
when "11" & x"454" => data <= x"46";
when "11" & x"455" => data <= x"49";
when "11" & x"456" => data <= x"45";
when "11" & x"457" => data <= x"44";
when "11" & x"458" => data <= x"20";
when "11" & x"459" => data <= x"62";
when "11" & x"45a" => data <= x"79";
when "11" & x"45b" => data <= x"20";
when "11" & x"45c" => data <= x"64";
when "11" & x"45d" => data <= x"75";
when "11" & x"45e" => data <= x"69";
when "11" & x"45f" => data <= x"6b";
when "11" & x"460" => data <= x"6b";
when "11" & x"461" => data <= x"69";
when "11" & x"462" => data <= x"65";
when "11" & x"463" => data <= x"20";
when "11" & x"464" => data <= x"32";
when "11" & x"465" => data <= x"30";
when "11" & x"466" => data <= x"31";
when "11" & x"467" => data <= x"35";
when "11" & x"468" => data <= x"00";
when "11" & x"469" => data <= x"4c";
when "11" & x"46a" => data <= x"e7";
when "11" & x"46b" => data <= x"ff";
when "11" & x"46c" => data <= x"a2";
when "11" & x"46d" => data <= x"fd";
when "11" & x"46e" => data <= x"98";
when "11" & x"46f" => data <= x"48";
when "11" & x"470" => data <= x"e8";
when "11" & x"471" => data <= x"e8";
when "11" & x"472" => data <= x"68";
when "11" & x"473" => data <= x"48";
when "11" & x"474" => data <= x"a8";
when "11" & x"475" => data <= x"20";
when "11" & x"476" => data <= x"b0";
when "11" & x"477" => data <= x"b4";
when "11" & x"478" => data <= x"e8";
when "11" & x"479" => data <= x"bd";
when "11" & x"47a" => data <= x"2b";
when "11" & x"47b" => data <= x"b3";
when "11" & x"47c" => data <= x"30";
when "11" & x"47d" => data <= x"28";
when "11" & x"47e" => data <= x"86";
when "11" & x"47f" => data <= x"b5";
when "11" & x"480" => data <= x"ca";
when "11" & x"481" => data <= x"88";
when "11" & x"482" => data <= x"e8";
when "11" & x"483" => data <= x"c8";
when "11" & x"484" => data <= x"bd";
when "11" & x"485" => data <= x"2b";
when "11" & x"486" => data <= x"b3";
when "11" & x"487" => data <= x"30";
when "11" & x"488" => data <= x"16";
when "11" & x"489" => data <= x"51";
when "11" & x"48a" => data <= x"f2";
when "11" & x"48b" => data <= x"29";
when "11" & x"48c" => data <= x"5f";
when "11" & x"48d" => data <= x"f0";
when "11" & x"48e" => data <= x"f3";
when "11" & x"48f" => data <= x"ca";
when "11" & x"490" => data <= x"e8";
when "11" & x"491" => data <= x"bd";
when "11" & x"492" => data <= x"2b";
when "11" & x"493" => data <= x"b3";
when "11" & x"494" => data <= x"10";
when "11" & x"495" => data <= x"fa";
when "11" & x"496" => data <= x"b1";
when "11" & x"497" => data <= x"f2";
when "11" & x"498" => data <= x"c9";
when "11" & x"499" => data <= x"2e";
when "11" & x"49a" => data <= x"d0";
when "11" & x"49b" => data <= x"d4";
when "11" & x"49c" => data <= x"c8";
when "11" & x"49d" => data <= x"b0";
when "11" & x"49e" => data <= x"07";
when "11" & x"49f" => data <= x"b1";
when "11" & x"4a0" => data <= x"f2";
when "11" & x"4a1" => data <= x"20";
when "11" & x"4a2" => data <= x"ee";
when "11" & x"4a3" => data <= x"82";
when "11" & x"4a4" => data <= x"90";
when "11" & x"4a5" => data <= x"ca";
when "11" & x"4a6" => data <= x"68";
when "11" & x"4a7" => data <= x"bd";
when "11" & x"4a8" => data <= x"2b";
when "11" & x"4a9" => data <= x"b3";
when "11" & x"4aa" => data <= x"48";
when "11" & x"4ab" => data <= x"bd";
when "11" & x"4ac" => data <= x"2c";
when "11" & x"4ad" => data <= x"b3";
when "11" & x"4ae" => data <= x"48";
when "11" & x"4af" => data <= x"60";
when "11" & x"4b0" => data <= x"b1";
when "11" & x"4b1" => data <= x"f2";
when "11" & x"4b2" => data <= x"c9";
when "11" & x"4b3" => data <= x"0d";
when "11" & x"4b4" => data <= x"f0";
when "11" & x"4b5" => data <= x"08";
when "11" & x"4b6" => data <= x"c8";
when "11" & x"4b7" => data <= x"f0";
when "11" & x"4b8" => data <= x"07";
when "11" & x"4b9" => data <= x"c9";
when "11" & x"4ba" => data <= x"20";
when "11" & x"4bb" => data <= x"f0";
when "11" & x"4bc" => data <= x"f3";
when "11" & x"4bd" => data <= x"18";
when "11" & x"4be" => data <= x"88";
when "11" & x"4bf" => data <= x"60";
when "11" & x"4c0" => data <= x"4c";
when "11" & x"4c1" => data <= x"f5";
when "11" & x"4c2" => data <= x"b6";
when "11" & x"4c3" => data <= x"98";
when "11" & x"4c4" => data <= x"48";
when "11" & x"4c5" => data <= x"a9";
when "11" & x"4c6" => data <= x"00";
when "11" & x"4c7" => data <= x"8d";
when "11" & x"4c8" => data <= x"55";
when "11" & x"4c9" => data <= x"0d";
when "11" & x"4ca" => data <= x"8d";
when "11" & x"4cb" => data <= x"56";
when "11" & x"4cc" => data <= x"0d";
when "11" & x"4cd" => data <= x"20";
when "11" & x"4ce" => data <= x"b0";
when "11" & x"4cf" => data <= x"b4";
when "11" & x"4d0" => data <= x"b0";
when "11" & x"4d1" => data <= x"62";
when "11" & x"4d2" => data <= x"b1";
when "11" & x"4d3" => data <= x"f2";
when "11" & x"4d4" => data <= x"c9";
when "11" & x"4d5" => data <= x"0d";
when "11" & x"4d6" => data <= x"f0";
when "11" & x"4d7" => data <= x"5c";
when "11" & x"4d8" => data <= x"38";
when "11" & x"4d9" => data <= x"e9";
when "11" & x"4da" => data <= x"30";
when "11" & x"4db" => data <= x"30";
when "11" & x"4dc" => data <= x"57";
when "11" & x"4dd" => data <= x"c9";
when "11" & x"4de" => data <= x"0a";
when "11" & x"4df" => data <= x"b0";
when "11" & x"4e0" => data <= x"53";
when "11" & x"4e1" => data <= x"48";
when "11" & x"4e2" => data <= x"ad";
when "11" & x"4e3" => data <= x"55";
when "11" & x"4e4" => data <= x"0d";
when "11" & x"4e5" => data <= x"0a";
when "11" & x"4e6" => data <= x"48";
when "11" & x"4e7" => data <= x"2e";
when "11" & x"4e8" => data <= x"56";
when "11" & x"4e9" => data <= x"0d";
when "11" & x"4ea" => data <= x"ae";
when "11" & x"4eb" => data <= x"56";
when "11" & x"4ec" => data <= x"0d";
when "11" & x"4ed" => data <= x"0a";
when "11" & x"4ee" => data <= x"2e";
when "11" & x"4ef" => data <= x"56";
when "11" & x"4f0" => data <= x"0d";
when "11" & x"4f1" => data <= x"0a";
when "11" & x"4f2" => data <= x"2e";
when "11" & x"4f3" => data <= x"56";
when "11" & x"4f4" => data <= x"0d";
when "11" & x"4f5" => data <= x"8d";
when "11" & x"4f6" => data <= x"55";
when "11" & x"4f7" => data <= x"0d";
when "11" & x"4f8" => data <= x"68";
when "11" & x"4f9" => data <= x"6d";
when "11" & x"4fa" => data <= x"55";
when "11" & x"4fb" => data <= x"0d";
when "11" & x"4fc" => data <= x"8d";
when "11" & x"4fd" => data <= x"55";
when "11" & x"4fe" => data <= x"0d";
when "11" & x"4ff" => data <= x"8a";
when "11" & x"500" => data <= x"6d";
when "11" & x"501" => data <= x"56";
when "11" & x"502" => data <= x"0d";
when "11" & x"503" => data <= x"aa";
when "11" & x"504" => data <= x"68";
when "11" & x"505" => data <= x"6d";
when "11" & x"506" => data <= x"55";
when "11" & x"507" => data <= x"0d";
when "11" & x"508" => data <= x"8d";
when "11" & x"509" => data <= x"55";
when "11" & x"50a" => data <= x"0d";
when "11" & x"50b" => data <= x"8a";
when "11" & x"50c" => data <= x"69";
when "11" & x"50d" => data <= x"00";
when "11" & x"50e" => data <= x"8d";
when "11" & x"50f" => data <= x"56";
when "11" & x"510" => data <= x"0d";
when "11" & x"511" => data <= x"c9";
when "11" & x"512" => data <= x"02";
when "11" & x"513" => data <= x"b0";
when "11" & x"514" => data <= x"1f";
when "11" & x"515" => data <= x"c8";
when "11" & x"516" => data <= x"f0";
when "11" & x"517" => data <= x"1c";
when "11" & x"518" => data <= x"b1";
when "11" & x"519" => data <= x"f2";
when "11" & x"51a" => data <= x"c9";
when "11" & x"51b" => data <= x"0d";
when "11" & x"51c" => data <= x"f0";
when "11" & x"51d" => data <= x"04";
when "11" & x"51e" => data <= x"c9";
when "11" & x"51f" => data <= x"20";
when "11" & x"520" => data <= x"d0";
when "11" & x"521" => data <= x"b6";
when "11" & x"522" => data <= x"ae";
when "11" & x"523" => data <= x"55";
when "11" & x"524" => data <= x"0d";
when "11" & x"525" => data <= x"ad";
when "11" & x"526" => data <= x"56";
when "11" & x"527" => data <= x"0d";
when "11" & x"528" => data <= x"f0";
when "11" & x"529" => data <= x"04";
when "11" & x"52a" => data <= x"e8";
when "11" & x"52b" => data <= x"f0";
when "11" & x"52c" => data <= x"07";
when "11" & x"52d" => data <= x"ca";
when "11" & x"52e" => data <= x"68";
when "11" & x"52f" => data <= x"ad";
when "11" & x"530" => data <= x"56";
when "11" & x"531" => data <= x"0d";
when "11" & x"532" => data <= x"18";
when "11" & x"533" => data <= x"60";
when "11" & x"534" => data <= x"68";
when "11" & x"535" => data <= x"a8";
when "11" & x"536" => data <= x"a9";
when "11" & x"537" => data <= x"00";
when "11" & x"538" => data <= x"aa";
when "11" & x"539" => data <= x"38";
when "11" & x"53a" => data <= x"60";
when "11" & x"53b" => data <= x"a9";
when "11" & x"53c" => data <= x"0d";
when "11" & x"53d" => data <= x"8d";
when "11" & x"53e" => data <= x"5d";
when "11" & x"53f" => data <= x"0d";
when "11" & x"540" => data <= x"a2";
when "11" & x"541" => data <= x"00";
when "11" & x"542" => data <= x"8e";
when "11" & x"543" => data <= x"5e";
when "11" & x"544" => data <= x"0d";
when "11" & x"545" => data <= x"20";
when "11" & x"546" => data <= x"b0";
when "11" & x"547" => data <= x"b4";
when "11" & x"548" => data <= x"b0";
when "11" & x"549" => data <= x"49";
when "11" & x"54a" => data <= x"c9";
when "11" & x"54b" => data <= x"22";
when "11" & x"54c" => data <= x"d0";
when "11" & x"54d" => data <= x"04";
when "11" & x"54e" => data <= x"c8";
when "11" & x"54f" => data <= x"8d";
when "11" & x"550" => data <= x"5d";
when "11" & x"551" => data <= x"0d";
when "11" & x"552" => data <= x"b1";
when "11" & x"553" => data <= x"f2";
when "11" & x"554" => data <= x"c9";
when "11" & x"555" => data <= x"0d";
when "11" & x"556" => data <= x"f0";
when "11" & x"557" => data <= x"2c";
when "11" & x"558" => data <= x"c9";
when "11" & x"559" => data <= x"20";
when "11" & x"55a" => data <= x"d0";
when "11" & x"55b" => data <= x"0b";
when "11" & x"55c" => data <= x"90";
when "11" & x"55d" => data <= x"52";
when "11" & x"55e" => data <= x"ad";
when "11" & x"55f" => data <= x"5d";
when "11" & x"560" => data <= x"0d";
when "11" & x"561" => data <= x"c9";
when "11" & x"562" => data <= x"22";
when "11" & x"563" => data <= x"d0";
when "11" & x"564" => data <= x"28";
when "11" & x"565" => data <= x"a9";
when "11" & x"566" => data <= x"20";
when "11" & x"567" => data <= x"c9";
when "11" & x"568" => data <= x"22";
when "11" & x"569" => data <= x"f0";
when "11" & x"56a" => data <= x"19";
when "11" & x"56b" => data <= x"c9";
when "11" & x"56c" => data <= x"2a";
when "11" & x"56d" => data <= x"f0";
when "11" & x"56e" => data <= x"31";
when "11" & x"56f" => data <= x"c9";
when "11" & x"570" => data <= x"61";
when "11" & x"571" => data <= x"90";
when "11" & x"572" => data <= x"06";
when "11" & x"573" => data <= x"c9";
when "11" & x"574" => data <= x"7b";
when "11" & x"575" => data <= x"b0";
when "11" & x"576" => data <= x"02";
when "11" & x"577" => data <= x"49";
when "11" & x"578" => data <= x"20";
when "11" & x"579" => data <= x"9d";
when "11" & x"57a" => data <= x"5f";
when "11" & x"57b" => data <= x"0d";
when "11" & x"57c" => data <= x"c8";
when "11" & x"57d" => data <= x"e8";
when "11" & x"57e" => data <= x"e0";
when "11" & x"57f" => data <= x"0c";
when "11" & x"580" => data <= x"d0";
when "11" & x"581" => data <= x"d0";
when "11" & x"582" => data <= x"b1";
when "11" & x"583" => data <= x"f2";
when "11" & x"584" => data <= x"cd";
when "11" & x"585" => data <= x"5d";
when "11" & x"586" => data <= x"0d";
when "11" & x"587" => data <= x"d0";
when "11" & x"588" => data <= x"27";
when "11" & x"589" => data <= x"c9";
when "11" & x"58a" => data <= x"0d";
when "11" & x"58b" => data <= x"f0";
when "11" & x"58c" => data <= x"06";
when "11" & x"58d" => data <= x"c8";
when "11" & x"58e" => data <= x"20";
when "11" & x"58f" => data <= x"b0";
when "11" & x"590" => data <= x"b4";
when "11" & x"591" => data <= x"90";
when "11" & x"592" => data <= x"1d";
when "11" & x"593" => data <= x"8e";
when "11" & x"594" => data <= x"5c";
when "11" & x"595" => data <= x"0d";
when "11" & x"596" => data <= x"e0";
when "11" & x"597" => data <= x"0c";
when "11" & x"598" => data <= x"f0";
when "11" & x"599" => data <= x"05";
when "11" & x"59a" => data <= x"a9";
when "11" & x"59b" => data <= x"00";
when "11" & x"59c" => data <= x"9d";
when "11" & x"59d" => data <= x"5f";
when "11" & x"59e" => data <= x"0d";
when "11" & x"59f" => data <= x"60";
when "11" & x"5a0" => data <= x"8d";
when "11" & x"5a1" => data <= x"5e";
when "11" & x"5a2" => data <= x"0d";
when "11" & x"5a3" => data <= x"ad";
when "11" & x"5a4" => data <= x"5d";
when "11" & x"5a5" => data <= x"0d";
when "11" & x"5a6" => data <= x"c9";
when "11" & x"5a7" => data <= x"0d";
when "11" & x"5a8" => data <= x"f0";
when "11" & x"5a9" => data <= x"e3";
when "11" & x"5aa" => data <= x"c8";
when "11" & x"5ab" => data <= x"b1";
when "11" & x"5ac" => data <= x"f2";
when "11" & x"5ad" => data <= x"4c";
when "11" & x"5ae" => data <= x"84";
when "11" & x"5af" => data <= x"b5";
when "11" & x"5b0" => data <= x"4c";
when "11" & x"5b1" => data <= x"f5";
when "11" & x"5b2" => data <= x"b6";
when "11" & x"5b3" => data <= x"a0";
when "11" & x"5b4" => data <= x"00";
when "11" & x"5b5" => data <= x"ae";
when "11" & x"5b6" => data <= x"5c";
when "11" & x"5b7" => data <= x"0d";
when "11" & x"5b8" => data <= x"f0";
when "11" & x"5b9" => data <= x"17";
when "11" & x"5ba" => data <= x"b1";
when "11" & x"5bb" => data <= x"f2";
when "11" & x"5bc" => data <= x"f0";
when "11" & x"5bd" => data <= x"25";
when "11" & x"5be" => data <= x"c9";
when "11" & x"5bf" => data <= x"61";
when "11" & x"5c0" => data <= x"90";
when "11" & x"5c1" => data <= x"06";
when "11" & x"5c2" => data <= x"c9";
when "11" & x"5c3" => data <= x"7b";
when "11" & x"5c4" => data <= x"b0";
when "11" & x"5c5" => data <= x"02";
when "11" & x"5c6" => data <= x"49";
when "11" & x"5c7" => data <= x"20";
when "11" & x"5c8" => data <= x"d9";
when "11" & x"5c9" => data <= x"5f";
when "11" & x"5ca" => data <= x"0d";
when "11" & x"5cb" => data <= x"d0";
when "11" & x"5cc" => data <= x"16";
when "11" & x"5cd" => data <= x"c8";
when "11" & x"5ce" => data <= x"ca";
when "11" & x"5cf" => data <= x"d0";
when "11" & x"5d0" => data <= x"e9";
when "11" & x"5d1" => data <= x"b1";
when "11" & x"5d2" => data <= x"f2";
when "11" & x"5d3" => data <= x"f0";
when "11" & x"5d4" => data <= x"0c";
when "11" & x"5d5" => data <= x"ad";
when "11" & x"5d6" => data <= x"5c";
when "11" & x"5d7" => data <= x"0d";
when "11" & x"5d8" => data <= x"c9";
when "11" & x"5d9" => data <= x"0c";
when "11" & x"5da" => data <= x"f0";
when "11" & x"5db" => data <= x"05";
when "11" & x"5dc" => data <= x"ad";
when "11" & x"5dd" => data <= x"5e";
when "11" & x"5de" => data <= x"0d";
when "11" & x"5df" => data <= x"f0";
when "11" & x"5e0" => data <= x"02";
when "11" & x"5e1" => data <= x"18";
when "11" & x"5e2" => data <= x"60";
when "11" & x"5e3" => data <= x"38";
when "11" & x"5e4" => data <= x"60";
when "11" & x"5e5" => data <= x"b0";
when "11" & x"5e6" => data <= x"05";
when "11" & x"5e7" => data <= x"a9";
when "11" & x"5e8" => data <= x"20";
when "11" & x"5e9" => data <= x"20";
when "11" & x"5ea" => data <= x"ee";
when "11" & x"5eb" => data <= x"ff";
when "11" & x"5ec" => data <= x"a2";
when "11" & x"5ed" => data <= x"20";
when "11" & x"5ee" => data <= x"a0";
when "11" & x"5ef" => data <= x"04";
when "11" & x"5f0" => data <= x"ad";
when "11" & x"5f1" => data <= x"56";
when "11" & x"5f2" => data <= x"0d";
when "11" & x"5f3" => data <= x"20";
when "11" & x"5f4" => data <= x"26";
when "11" & x"5f5" => data <= x"b6";
when "11" & x"5f6" => data <= x"ad";
when "11" & x"5f7" => data <= x"55";
when "11" & x"5f8" => data <= x"0d";
when "11" & x"5f9" => data <= x"20";
when "11" & x"5fa" => data <= x"26";
when "11" & x"5fb" => data <= x"b6";
when "11" & x"5fc" => data <= x"a9";
when "11" & x"5fd" => data <= x"20";
when "11" & x"5fe" => data <= x"20";
when "11" & x"5ff" => data <= x"ee";
when "11" & x"600" => data <= x"ff";
when "11" & x"601" => data <= x"a0";
when "11" & x"602" => data <= x"00";
when "11" & x"603" => data <= x"b1";
when "11" & x"604" => data <= x"f2";
when "11" & x"605" => data <= x"f0";
when "11" & x"606" => data <= x"08";
when "11" & x"607" => data <= x"20";
when "11" & x"608" => data <= x"ee";
when "11" & x"609" => data <= x"ff";
when "11" & x"60a" => data <= x"c8";
when "11" & x"60b" => data <= x"c0";
when "11" & x"60c" => data <= x"0c";
when "11" & x"60d" => data <= x"d0";
when "11" & x"60e" => data <= x"f4";
when "11" & x"60f" => data <= x"a9";
when "11" & x"610" => data <= x"20";
when "11" & x"611" => data <= x"20";
when "11" & x"612" => data <= x"ee";
when "11" & x"613" => data <= x"ff";
when "11" & x"614" => data <= x"c8";
when "11" & x"615" => data <= x"c0";
when "11" & x"616" => data <= x"0d";
when "11" & x"617" => data <= x"d0";
when "11" & x"618" => data <= x"f8";
when "11" & x"619" => data <= x"aa";
when "11" & x"61a" => data <= x"a0";
when "11" & x"61b" => data <= x"0f";
when "11" & x"61c" => data <= x"b1";
when "11" & x"61d" => data <= x"f2";
when "11" & x"61e" => data <= x"d0";
when "11" & x"61f" => data <= x"02";
when "11" & x"620" => data <= x"a2";
when "11" & x"621" => data <= x"50";
when "11" & x"622" => data <= x"8a";
when "11" & x"623" => data <= x"4c";
when "11" & x"624" => data <= x"ee";
when "11" & x"625" => data <= x"ff";
when "11" & x"626" => data <= x"48";
when "11" & x"627" => data <= x"4a";
when "11" & x"628" => data <= x"4a";
when "11" & x"629" => data <= x"4a";
when "11" & x"62a" => data <= x"4a";
when "11" & x"62b" => data <= x"20";
when "11" & x"62c" => data <= x"2f";
when "11" & x"62d" => data <= x"b6";
when "11" & x"62e" => data <= x"68";
when "11" & x"62f" => data <= x"29";
when "11" & x"630" => data <= x"0f";
when "11" & x"631" => data <= x"f0";
when "11" & x"632" => data <= x"08";
when "11" & x"633" => data <= x"a2";
when "11" & x"634" => data <= x"30";
when "11" & x"635" => data <= x"18";
when "11" & x"636" => data <= x"69";
when "11" & x"637" => data <= x"30";
when "11" & x"638" => data <= x"4c";
when "11" & x"639" => data <= x"ee";
when "11" & x"63a" => data <= x"ff";
when "11" & x"63b" => data <= x"88";
when "11" & x"63c" => data <= x"d0";
when "11" & x"63d" => data <= x"02";
when "11" & x"63e" => data <= x"a2";
when "11" & x"63f" => data <= x"30";
when "11" & x"640" => data <= x"8a";
when "11" & x"641" => data <= x"4c";
when "11" & x"642" => data <= x"ee";
when "11" & x"643" => data <= x"ff";
when "11" & x"644" => data <= x"a2";
when "11" & x"645" => data <= x"00";
when "11" & x"646" => data <= x"68";
when "11" & x"647" => data <= x"85";
when "11" & x"648" => data <= x"a0";
when "11" & x"649" => data <= x"68";
when "11" & x"64a" => data <= x"85";
when "11" & x"64b" => data <= x"a1";
when "11" & x"64c" => data <= x"a0";
when "11" & x"64d" => data <= x"00";
when "11" & x"64e" => data <= x"f0";
when "11" & x"64f" => data <= x"07";
when "11" & x"650" => data <= x"b1";
when "11" & x"651" => data <= x"a0";
when "11" & x"652" => data <= x"f0";
when "11" & x"653" => data <= x"0b";
when "11" & x"654" => data <= x"20";
when "11" & x"655" => data <= x"66";
when "11" & x"656" => data <= x"b6";
when "11" & x"657" => data <= x"e6";
when "11" & x"658" => data <= x"a0";
when "11" & x"659" => data <= x"d0";
when "11" & x"65a" => data <= x"f5";
when "11" & x"65b" => data <= x"e6";
when "11" & x"65c" => data <= x"a1";
when "11" & x"65d" => data <= x"d0";
when "11" & x"65e" => data <= x"f1";
when "11" & x"65f" => data <= x"a5";
when "11" & x"660" => data <= x"a1";
when "11" & x"661" => data <= x"48";
when "11" & x"662" => data <= x"a5";
when "11" & x"663" => data <= x"a0";
when "11" & x"664" => data <= x"48";
when "11" & x"665" => data <= x"60";
when "11" & x"666" => data <= x"e0";
when "11" & x"667" => data <= x"00";
when "11" & x"668" => data <= x"d0";
when "11" & x"669" => data <= x"03";
when "11" & x"66a" => data <= x"4c";
when "11" & x"66b" => data <= x"ee";
when "11" & x"66c" => data <= x"ff";
when "11" & x"66d" => data <= x"9d";
when "11" & x"66e" => data <= x"00";
when "11" & x"66f" => data <= x"01";
when "11" & x"670" => data <= x"e8";
when "11" & x"671" => data <= x"60";
when "11" & x"672" => data <= x"08";
when "11" & x"673" => data <= x"10";
when "11" & x"674" => data <= x"1c";
when "11" & x"675" => data <= x"22";
when "11" & x"676" => data <= x"43";
when "11" & x"677" => data <= x"49";
when "11" & x"678" => data <= x"4f";
when "11" & x"679" => data <= x"58";
when "11" & x"67a" => data <= x"28";
when "11" & x"67b" => data <= x"3c";
when "11" & x"67c" => data <= x"64";
when "11" & x"67d" => data <= x"72";
when "11" & x"67e" => data <= x"76";
when "11" & x"67f" => data <= x"3e";
when "11" & x"680" => data <= x"29";
when "11" & x"681" => data <= x"00";
when "11" & x"682" => data <= x"3c";
when "11" & x"683" => data <= x"64";
when "11" & x"684" => data <= x"6e";
when "11" & x"685" => data <= x"6f";
when "11" & x"686" => data <= x"3e";
when "11" & x"687" => data <= x"2f";
when "11" & x"688" => data <= x"3c";
when "11" & x"689" => data <= x"64";
when "11" & x"68a" => data <= x"73";
when "11" & x"68b" => data <= x"70";
when "11" & x"68c" => data <= x"3e";
when "11" & x"68d" => data <= x"00";
when "11" & x"68e" => data <= x"3c";
when "11" & x"68f" => data <= x"64";
when "11" & x"690" => data <= x"6e";
when "11" & x"691" => data <= x"6f";
when "11" & x"692" => data <= x"3e";
when "11" & x"693" => data <= x"00";
when "11" & x"694" => data <= x"28";
when "11" & x"695" => data <= x"28";
when "11" & x"696" => data <= x"3c";
when "11" & x"697" => data <= x"66";
when "11" & x"698" => data <= x"72";
when "11" & x"699" => data <= x"6f";
when "11" & x"69a" => data <= x"6d";
when "11" & x"69b" => data <= x"20";
when "11" & x"69c" => data <= x"64";
when "11" & x"69d" => data <= x"6e";
when "11" & x"69e" => data <= x"6f";
when "11" & x"69f" => data <= x"3e";
when "11" & x"6a0" => data <= x"29";
when "11" & x"6a1" => data <= x"20";
when "11" & x"6a2" => data <= x"3c";
when "11" & x"6a3" => data <= x"74";
when "11" & x"6a4" => data <= x"6f";
when "11" & x"6a5" => data <= x"20";
when "11" & x"6a6" => data <= x"64";
when "11" & x"6a7" => data <= x"6e";
when "11" & x"6a8" => data <= x"6f";
when "11" & x"6a9" => data <= x"3e";
when "11" & x"6aa" => data <= x"29";
when "11" & x"6ab" => data <= x"20";
when "11" & x"6ac" => data <= x"28";
when "11" & x"6ad" => data <= x"3c";
when "11" & x"6ae" => data <= x"61";
when "11" & x"6af" => data <= x"64";
when "11" & x"6b0" => data <= x"73";
when "11" & x"6b1" => data <= x"70";
when "11" & x"6b2" => data <= x"3e";
when "11" & x"6b3" => data <= x"29";
when "11" & x"6b4" => data <= x"00";
when "11" & x"6b5" => data <= x"3c";
when "11" & x"6b6" => data <= x"64";
when "11" & x"6b7" => data <= x"72";
when "11" & x"6b8" => data <= x"76";
when "11" & x"6b9" => data <= x"3e";
when "11" & x"6ba" => data <= x"00";
when "11" & x"6bb" => data <= x"3c";
when "11" & x"6bc" => data <= x"66";
when "11" & x"6bd" => data <= x"73";
when "11" & x"6be" => data <= x"70";
when "11" & x"6bf" => data <= x"3e";
when "11" & x"6c0" => data <= x"00";
when "11" & x"6c1" => data <= x"28";
when "11" & x"6c2" => data <= x"3c";
when "11" & x"6c3" => data <= x"6d";
when "11" & x"6c4" => data <= x"6f";
when "11" & x"6c5" => data <= x"64";
when "11" & x"6c6" => data <= x"65";
when "11" & x"6c7" => data <= x"3e";
when "11" & x"6c8" => data <= x"29";
when "11" & x"6c9" => data <= x"00";
when "11" & x"6ca" => data <= x"28";
when "11" & x"6cb" => data <= x"3c";
when "11" & x"6cc" => data <= x"72";
when "11" & x"6cd" => data <= x"6f";
when "11" & x"6ce" => data <= x"6d";
when "11" & x"6cf" => data <= x"3e";
when "11" & x"6d0" => data <= x"29";
when "11" & x"6d1" => data <= x"00";
when "11" & x"6d2" => data <= x"48";
when "11" & x"6d3" => data <= x"4a";
when "11" & x"6d4" => data <= x"4a";
when "11" & x"6d5" => data <= x"4a";
when "11" & x"6d6" => data <= x"4a";
when "11" & x"6d7" => data <= x"20";
when "11" & x"6d8" => data <= x"dd";
when "11" & x"6d9" => data <= x"b6";
when "11" & x"6da" => data <= x"68";
when "11" & x"6db" => data <= x"29";
when "11" & x"6dc" => data <= x"0f";
when "11" & x"6dd" => data <= x"a8";
when "11" & x"6de" => data <= x"f0";
when "11" & x"6df" => data <= x"14";
when "11" & x"6e0" => data <= x"a9";
when "11" & x"6e1" => data <= x"20";
when "11" & x"6e2" => data <= x"20";
when "11" & x"6e3" => data <= x"66";
when "11" & x"6e4" => data <= x"b6";
when "11" & x"6e5" => data <= x"b9";
when "11" & x"6e6" => data <= x"71";
when "11" & x"6e7" => data <= x"b6";
when "11" & x"6e8" => data <= x"a8";
when "11" & x"6e9" => data <= x"b9";
when "11" & x"6ea" => data <= x"72";
when "11" & x"6eb" => data <= x"b6";
when "11" & x"6ec" => data <= x"f0";
when "11" & x"6ed" => data <= x"06";
when "11" & x"6ee" => data <= x"20";
when "11" & x"6ef" => data <= x"66";
when "11" & x"6f0" => data <= x"b6";
when "11" & x"6f1" => data <= x"c8";
when "11" & x"6f2" => data <= x"d0";
when "11" & x"6f3" => data <= x"f5";
when "11" & x"6f4" => data <= x"60";
when "11" & x"6f5" => data <= x"a2";
when "11" & x"6f6" => data <= x"00";
when "11" & x"6f7" => data <= x"8e";
when "11" & x"6f8" => data <= x"00";
when "11" & x"6f9" => data <= x"01";
when "11" & x"6fa" => data <= x"e8";
when "11" & x"6fb" => data <= x"20";
when "11" & x"6fc" => data <= x"46";
when "11" & x"6fd" => data <= x"b6";
when "11" & x"6fe" => data <= x"1a";
when "11" & x"6ff" => data <= x"53";
when "11" & x"700" => data <= x"79";
when "11" & x"701" => data <= x"6e";
when "11" & x"702" => data <= x"74";
when "11" & x"703" => data <= x"61";
when "11" & x"704" => data <= x"78";
when "11" & x"705" => data <= x"3a";
when "11" & x"706" => data <= x"20";
when "11" & x"707" => data <= x"00";
when "11" & x"708" => data <= x"a4";
when "11" & x"709" => data <= x"b5";
when "11" & x"70a" => data <= x"b9";
when "11" & x"70b" => data <= x"2b";
when "11" & x"70c" => data <= x"b3";
when "11" & x"70d" => data <= x"30";
when "11" & x"70e" => data <= x"06";
when "11" & x"70f" => data <= x"20";
when "11" & x"710" => data <= x"66";
when "11" & x"711" => data <= x"b6";
when "11" & x"712" => data <= x"c8";
when "11" & x"713" => data <= x"d0";
when "11" & x"714" => data <= x"f5";
when "11" & x"715" => data <= x"c8";
when "11" & x"716" => data <= x"c8";
when "11" & x"717" => data <= x"b9";
when "11" & x"718" => data <= x"2b";
when "11" & x"719" => data <= x"b3";
when "11" & x"71a" => data <= x"c8";
when "11" & x"71b" => data <= x"84";
when "11" & x"71c" => data <= x"b5";
when "11" & x"71d" => data <= x"20";
when "11" & x"71e" => data <= x"d2";
when "11" & x"71f" => data <= x"b6";
when "11" & x"720" => data <= x"e0";
when "11" & x"721" => data <= x"00";
when "11" & x"722" => data <= x"f0";
when "11" & x"723" => data <= x"08";
when "11" & x"724" => data <= x"a9";
when "11" & x"725" => data <= x"00";
when "11" & x"726" => data <= x"9d";
when "11" & x"727" => data <= x"00";
when "11" & x"728" => data <= x"01";
when "11" & x"729" => data <= x"4c";
when "11" & x"72a" => data <= x"00";
when "11" & x"72b" => data <= x"01";
when "11" & x"72c" => data <= x"60";
when "11" & x"72d" => data <= x"4c";
when "11" & x"72e" => data <= x"f5";
when "11" & x"72f" => data <= x"b6";
when "11" & x"730" => data <= x"20";
when "11" & x"731" => data <= x"b0";
when "11" & x"732" => data <= x"b4";
when "11" & x"733" => data <= x"b0";
when "11" & x"734" => data <= x"17";
when "11" & x"735" => data <= x"20";
when "11" & x"736" => data <= x"c3";
when "11" & x"737" => data <= x"b4";
when "11" & x"738" => data <= x"b0";
when "11" & x"739" => data <= x"bb";
when "11" & x"73a" => data <= x"48";
when "11" & x"73b" => data <= x"20";
when "11" & x"73c" => data <= x"b0";
when "11" & x"73d" => data <= x"b4";
when "11" & x"73e" => data <= x"68";
when "11" & x"73f" => data <= x"90";
when "11" & x"740" => data <= x"b4";
when "11" & x"741" => data <= x"d0";
when "11" & x"742" => data <= x"26";
when "11" & x"743" => data <= x"8a";
when "11" & x"744" => data <= x"8d";
when "11" & x"745" => data <= x"5b";
when "11" & x"746" => data <= x"0d";
when "11" & x"747" => data <= x"c9";
when "11" & x"748" => data <= x"04";
when "11" & x"749" => data <= x"b0";
when "11" & x"74a" => data <= x"1e";
when "11" & x"74b" => data <= x"60";
when "11" & x"74c" => data <= x"a5";
when "11" & x"74d" => data <= x"cf";
when "11" & x"74e" => data <= x"60";
when "11" & x"74f" => data <= x"20";
when "11" & x"750" => data <= x"b0";
when "11" & x"751" => data <= x"b4";
when "11" & x"752" => data <= x"b0";
when "11" & x"753" => data <= x"a1";
when "11" & x"754" => data <= x"20";
when "11" & x"755" => data <= x"c3";
when "11" & x"756" => data <= x"b4";
when "11" & x"757" => data <= x"b0";
when "11" & x"758" => data <= x"9c";
when "11" & x"759" => data <= x"48";
when "11" & x"75a" => data <= x"20";
when "11" & x"75b" => data <= x"b0";
when "11" & x"75c" => data <= x"b4";
when "11" & x"75d" => data <= x"68";
when "11" & x"75e" => data <= x"90";
when "11" & x"75f" => data <= x"95";
when "11" & x"760" => data <= x"60";
when "11" & x"761" => data <= x"20";
when "11" & x"762" => data <= x"b0";
when "11" & x"763" => data <= x"b4";
when "11" & x"764" => data <= x"b0";
when "11" & x"765" => data <= x"8f";
when "11" & x"766" => data <= x"4c";
when "11" & x"767" => data <= x"ba";
when "11" & x"768" => data <= x"b7";
when "11" & x"769" => data <= x"20";
when "11" & x"76a" => data <= x"00";
when "11" & x"76b" => data <= x"a0";
when "11" & x"76c" => data <= x"cd";
when "11" & x"76d" => data <= x"42";
when "11" & x"76e" => data <= x"61";
when "11" & x"76f" => data <= x"64";
when "11" & x"770" => data <= x"20";
when "11" & x"771" => data <= x"64";
when "11" & x"772" => data <= x"72";
when "11" & x"773" => data <= x"69";
when "11" & x"774" => data <= x"76";
when "11" & x"775" => data <= x"65";
when "11" & x"776" => data <= x"00";
when "11" & x"777" => data <= x"20";
when "11" & x"778" => data <= x"00";
when "11" & x"779" => data <= x"a0";
when "11" & x"77a" => data <= x"d6";
when "11" & x"77b" => data <= x"44";
when "11" & x"77c" => data <= x"69";
when "11" & x"77d" => data <= x"73";
when "11" & x"77e" => data <= x"6b";
when "11" & x"77f" => data <= x"20";
when "11" & x"780" => data <= x"6e";
when "11" & x"781" => data <= x"6f";
when "11" & x"782" => data <= x"74";
when "11" & x"783" => data <= x"20";
when "11" & x"784" => data <= x"66";
when "11" & x"785" => data <= x"6f";
when "11" & x"786" => data <= x"75";
when "11" & x"787" => data <= x"6e";
when "11" & x"788" => data <= x"64";
when "11" & x"789" => data <= x"00";
when "11" & x"78a" => data <= x"20";
when "11" & x"78b" => data <= x"b0";
when "11" & x"78c" => data <= x"b4";
when "11" & x"78d" => data <= x"b0";
when "11" & x"78e" => data <= x"9e";
when "11" & x"78f" => data <= x"a9";
when "11" & x"790" => data <= x"ff";
when "11" & x"791" => data <= x"20";
when "11" & x"792" => data <= x"a2";
when "11" & x"793" => data <= x"b7";
when "11" & x"794" => data <= x"08";
when "11" & x"795" => data <= x"e0";
when "11" & x"796" => data <= x"04";
when "11" & x"797" => data <= x"b0";
when "11" & x"798" => data <= x"33";
when "11" & x"799" => data <= x"28";
when "11" & x"79a" => data <= x"60";
when "11" & x"79b" => data <= x"20";
when "11" & x"79c" => data <= x"b0";
when "11" & x"79d" => data <= x"b4";
when "11" & x"79e" => data <= x"b0";
when "11" & x"79f" => data <= x"8d";
when "11" & x"7a0" => data <= x"a5";
when "11" & x"7a1" => data <= x"cf";
when "11" & x"7a2" => data <= x"8d";
when "11" & x"7a3" => data <= x"5b";
when "11" & x"7a4" => data <= x"0d";
when "11" & x"7a5" => data <= x"20";
when "11" & x"7a6" => data <= x"c3";
when "11" & x"7a7" => data <= x"b4";
when "11" & x"7a8" => data <= x"b0";
when "11" & x"7a9" => data <= x"26";
when "11" & x"7aa" => data <= x"48";
when "11" & x"7ab" => data <= x"20";
when "11" & x"7ac" => data <= x"b0";
when "11" & x"7ad" => data <= x"b4";
when "11" & x"7ae" => data <= x"b0";
when "11" & x"7af" => data <= x"15";
when "11" & x"7b0" => data <= x"68";
when "11" & x"7b1" => data <= x"d0";
when "11" & x"7b2" => data <= x"b6";
when "11" & x"7b3" => data <= x"e0";
when "11" & x"7b4" => data <= x"04";
when "11" & x"7b5" => data <= x"b0";
when "11" & x"7b6" => data <= x"b2";
when "11" & x"7b7" => data <= x"8e";
when "11" & x"7b8" => data <= x"5b";
when "11" & x"7b9" => data <= x"0d";
when "11" & x"7ba" => data <= x"20";
when "11" & x"7bb" => data <= x"c3";
when "11" & x"7bc" => data <= x"b4";
when "11" & x"7bd" => data <= x"b0";
when "11" & x"7be" => data <= x"11";
when "11" & x"7bf" => data <= x"48";
when "11" & x"7c0" => data <= x"20";
when "11" & x"7c1" => data <= x"b0";
when "11" & x"7c2" => data <= x"b4";
when "11" & x"7c3" => data <= x"90";
when "11" & x"7c4" => data <= x"07";
when "11" & x"7c5" => data <= x"68";
when "11" & x"7c6" => data <= x"6a";
when "11" & x"7c7" => data <= x"8a";
when "11" & x"7c8" => data <= x"ae";
when "11" & x"7c9" => data <= x"5b";
when "11" & x"7ca" => data <= x"0d";
when "11" & x"7cb" => data <= x"60";
when "11" & x"7cc" => data <= x"68";
when "11" & x"7cd" => data <= x"4c";
when "11" & x"7ce" => data <= x"f5";
when "11" & x"7cf" => data <= x"b6";
when "11" & x"7d0" => data <= x"20";
when "11" & x"7d1" => data <= x"3b";
when "11" & x"7d2" => data <= x"b5";
when "11" & x"7d3" => data <= x"20";
when "11" & x"7d4" => data <= x"d7";
when "11" & x"7d5" => data <= x"b1";
when "11" & x"7d6" => data <= x"ad";
when "11" & x"7d7" => data <= x"5c";
when "11" & x"7d8" => data <= x"0d";
when "11" & x"7d9" => data <= x"f0";
when "11" & x"7da" => data <= x"f2";
when "11" & x"7db" => data <= x"ad";
when "11" & x"7dc" => data <= x"5e";
when "11" & x"7dd" => data <= x"0d";
when "11" & x"7de" => data <= x"d0";
when "11" & x"7df" => data <= x"ed";
when "11" & x"7e0" => data <= x"ad";
when "11" & x"7e1" => data <= x"54";
when "11" & x"7e2" => data <= x"0d";
when "11" & x"7e3" => data <= x"30";
when "11" & x"7e4" => data <= x"92";
when "11" & x"7e5" => data <= x"20";
when "11" & x"7e6" => data <= x"b3";
when "11" & x"7e7" => data <= x"b5";
when "11" & x"7e8" => data <= x"90";
when "11" & x"7e9" => data <= x"06";
when "11" & x"7ea" => data <= x"20";
when "11" & x"7eb" => data <= x"fc";
when "11" & x"7ec" => data <= x"b1";
when "11" & x"7ed" => data <= x"4c";
when "11" & x"7ee" => data <= x"e0";
when "11" & x"7ef" => data <= x"b7";
when "11" & x"7f0" => data <= x"ad";
when "11" & x"7f1" => data <= x"54";
when "11" & x"7f2" => data <= x"0d";
when "11" & x"7f3" => data <= x"6a";
when "11" & x"7f4" => data <= x"ad";
when "11" & x"7f5" => data <= x"53";
when "11" & x"7f6" => data <= x"0d";
when "11" & x"7f7" => data <= x"ae";
when "11" & x"7f8" => data <= x"5b";
when "11" & x"7f9" => data <= x"0d";
when "11" & x"7fa" => data <= x"60";
when "11" & x"7fb" => data <= x"20";
when "11" & x"7fc" => data <= x"61";
when "11" & x"7fd" => data <= x"b7";
when "11" & x"7fe" => data <= x"a6";
when "11" & x"7ff" => data <= x"cf";
when "11" & x"800" => data <= x"20";
when "11" & x"801" => data <= x"0f";
when "11" & x"802" => data <= x"b0";
when "11" & x"803" => data <= x"4c";
when "11" & x"804" => data <= x"07";
when "11" & x"805" => data <= x"94";
when "11" & x"806" => data <= x"20";
when "11" & x"807" => data <= x"9b";
when "11" & x"808" => data <= x"b7";
when "11" & x"809" => data <= x"4c";
when "11" & x"80a" => data <= x"0f";
when "11" & x"80b" => data <= x"b0";
when "11" & x"80c" => data <= x"a9";
when "11" & x"80d" => data <= x"00";
when "11" & x"80e" => data <= x"8d";
when "11" & x"80f" => data <= x"57";
when "11" & x"810" => data <= x"0d";
when "11" & x"811" => data <= x"8d";
when "11" & x"812" => data <= x"58";
when "11" & x"813" => data <= x"0d";
when "11" & x"814" => data <= x"20";
when "11" & x"815" => data <= x"c3";
when "11" & x"816" => data <= x"b4";
when "11" & x"817" => data <= x"b0";
when "11" & x"818" => data <= x"2d";
when "11" & x"819" => data <= x"8e";
when "11" & x"81a" => data <= x"59";
when "11" & x"81b" => data <= x"0d";
when "11" & x"81c" => data <= x"8e";
when "11" & x"81d" => data <= x"53";
when "11" & x"81e" => data <= x"0d";
when "11" & x"81f" => data <= x"8d";
when "11" & x"820" => data <= x"5a";
when "11" & x"821" => data <= x"0d";
when "11" & x"822" => data <= x"8d";
when "11" & x"823" => data <= x"54";
when "11" & x"824" => data <= x"0d";
when "11" & x"825" => data <= x"20";
when "11" & x"826" => data <= x"c3";
when "11" & x"827" => data <= x"b4";
when "11" & x"828" => data <= x"b0";
when "11" & x"829" => data <= x"25";
when "11" & x"82a" => data <= x"8e";
when "11" & x"82b" => data <= x"59";
when "11" & x"82c" => data <= x"0d";
when "11" & x"82d" => data <= x"8d";
when "11" & x"82e" => data <= x"5a";
when "11" & x"82f" => data <= x"0d";
when "11" & x"830" => data <= x"ec";
when "11" & x"831" => data <= x"53";
when "11" & x"832" => data <= x"0d";
when "11" & x"833" => data <= x"ed";
when "11" & x"834" => data <= x"54";
when "11" & x"835" => data <= x"0d";
when "11" & x"836" => data <= x"10";
when "11" & x"837" => data <= x"1f";
when "11" & x"838" => data <= x"20";
when "11" & x"839" => data <= x"00";
when "11" & x"83a" => data <= x"a0";
when "11" & x"83b" => data <= x"ff";
when "11" & x"83c" => data <= x"42";
when "11" & x"83d" => data <= x"61";
when "11" & x"83e" => data <= x"64";
when "11" & x"83f" => data <= x"20";
when "11" & x"840" => data <= x"72";
when "11" & x"841" => data <= x"61";
when "11" & x"842" => data <= x"6e";
when "11" & x"843" => data <= x"67";
when "11" & x"844" => data <= x"65";
when "11" & x"845" => data <= x"00";
when "11" & x"846" => data <= x"a2";
when "11" & x"847" => data <= x"fe";
when "11" & x"848" => data <= x"8e";
when "11" & x"849" => data <= x"59";
when "11" & x"84a" => data <= x"0d";
when "11" & x"84b" => data <= x"e8";
when "11" & x"84c" => data <= x"8e";
when "11" & x"84d" => data <= x"5a";
when "11" & x"84e" => data <= x"0d";
when "11" & x"84f" => data <= x"a9";
when "11" & x"850" => data <= x"00";
when "11" & x"851" => data <= x"8d";
when "11" & x"852" => data <= x"53";
when "11" & x"853" => data <= x"0d";
when "11" & x"854" => data <= x"8d";
when "11" & x"855" => data <= x"54";
when "11" & x"856" => data <= x"0d";
when "11" & x"857" => data <= x"ee";
when "11" & x"858" => data <= x"59";
when "11" & x"859" => data <= x"0d";
when "11" & x"85a" => data <= x"d0";
when "11" & x"85b" => data <= x"03";
when "11" & x"85c" => data <= x"ee";
when "11" & x"85d" => data <= x"5a";
when "11" & x"85e" => data <= x"0d";
when "11" & x"85f" => data <= x"20";
when "11" & x"860" => data <= x"3b";
when "11" & x"861" => data <= x"b5";
when "11" & x"862" => data <= x"ad";
when "11" & x"863" => data <= x"54";
when "11" & x"864" => data <= x"0d";
when "11" & x"865" => data <= x"6a";
when "11" & x"866" => data <= x"ad";
when "11" & x"867" => data <= x"53";
when "11" & x"868" => data <= x"0d";
when "11" & x"869" => data <= x"20";
when "11" & x"86a" => data <= x"a0";
when "11" & x"86b" => data <= x"b1";
when "11" & x"86c" => data <= x"a2";
when "11" & x"86d" => data <= x"00";
when "11" & x"86e" => data <= x"ad";
when "11" & x"86f" => data <= x"5c";
when "11" & x"870" => data <= x"0d";
when "11" & x"871" => data <= x"d0";
when "11" & x"872" => data <= x"04";
when "11" & x"873" => data <= x"ca";
when "11" & x"874" => data <= x"8e";
when "11" & x"875" => data <= x"5e";
when "11" & x"876" => data <= x"0d";
when "11" & x"877" => data <= x"ad";
when "11" & x"878" => data <= x"54";
when "11" & x"879" => data <= x"0d";
when "11" & x"87a" => data <= x"30";
when "11" & x"87b" => data <= x"33";
when "11" & x"87c" => data <= x"ad";
when "11" & x"87d" => data <= x"53";
when "11" & x"87e" => data <= x"0d";
when "11" & x"87f" => data <= x"cd";
when "11" & x"880" => data <= x"59";
when "11" & x"881" => data <= x"0d";
when "11" & x"882" => data <= x"ad";
when "11" & x"883" => data <= x"54";
when "11" & x"884" => data <= x"0d";
when "11" & x"885" => data <= x"ed";
when "11" & x"886" => data <= x"5a";
when "11" & x"887" => data <= x"0d";
when "11" & x"888" => data <= x"b0";
when "11" & x"889" => data <= x"25";
when "11" & x"88a" => data <= x"20";
when "11" & x"88b" => data <= x"b3";
when "11" & x"88c" => data <= x"b5";
when "11" & x"88d" => data <= x"b0";
when "11" & x"88e" => data <= x"16";
when "11" & x"88f" => data <= x"20";
when "11" & x"890" => data <= x"e5";
when "11" & x"891" => data <= x"b5";
when "11" & x"892" => data <= x"f8";
when "11" & x"893" => data <= x"18";
when "11" & x"894" => data <= x"ad";
when "11" & x"895" => data <= x"57";
when "11" & x"896" => data <= x"0d";
when "11" & x"897" => data <= x"69";
when "11" & x"898" => data <= x"01";
when "11" & x"899" => data <= x"8d";
when "11" & x"89a" => data <= x"57";
when "11" & x"89b" => data <= x"0d";
when "11" & x"89c" => data <= x"ad";
when "11" & x"89d" => data <= x"58";
when "11" & x"89e" => data <= x"0d";
when "11" & x"89f" => data <= x"69";
when "11" & x"8a0" => data <= x"00";
when "11" & x"8a1" => data <= x"8d";
when "11" & x"8a2" => data <= x"58";
when "11" & x"8a3" => data <= x"0d";
when "11" & x"8a4" => data <= x"d8";
when "11" & x"8a5" => data <= x"24";
when "11" & x"8a6" => data <= x"ff";
when "11" & x"8a7" => data <= x"30";
when "11" & x"8a8" => data <= x"47";
when "11" & x"8a9" => data <= x"20";
when "11" & x"8aa" => data <= x"fc";
when "11" & x"8ab" => data <= x"b1";
when "11" & x"8ac" => data <= x"4c";
when "11" & x"8ad" => data <= x"77";
when "11" & x"8ae" => data <= x"b8";
when "11" & x"8af" => data <= x"a9";
when "11" & x"8b0" => data <= x"86";
when "11" & x"8b1" => data <= x"20";
when "11" & x"8b2" => data <= x"f4";
when "11" & x"8b3" => data <= x"ff";
when "11" & x"8b4" => data <= x"e0";
when "11" & x"8b5" => data <= x"00";
when "11" & x"8b6" => data <= x"f0";
when "11" & x"8b7" => data <= x"03";
when "11" & x"8b8" => data <= x"20";
when "11" & x"8b9" => data <= x"e7";
when "11" & x"8ba" => data <= x"ff";
when "11" & x"8bb" => data <= x"ad";
when "11" & x"8bc" => data <= x"58";
when "11" & x"8bd" => data <= x"0d";
when "11" & x"8be" => data <= x"a2";
when "11" & x"8bf" => data <= x"00";
when "11" & x"8c0" => data <= x"a0";
when "11" & x"8c1" => data <= x"04";
when "11" & x"8c2" => data <= x"20";
when "11" & x"8c3" => data <= x"26";
when "11" & x"8c4" => data <= x"b6";
when "11" & x"8c5" => data <= x"ad";
when "11" & x"8c6" => data <= x"57";
when "11" & x"8c7" => data <= x"0d";
when "11" & x"8c8" => data <= x"20";
when "11" & x"8c9" => data <= x"26";
when "11" & x"8ca" => data <= x"b6";
when "11" & x"8cb" => data <= x"20";
when "11" & x"8cc" => data <= x"44";
when "11" & x"8cd" => data <= x"b6";
when "11" & x"8ce" => data <= x"20";
when "11" & x"8cf" => data <= x"64";
when "11" & x"8d0" => data <= x"69";
when "11" & x"8d1" => data <= x"73";
when "11" & x"8d2" => data <= x"6b";
when "11" & x"8d3" => data <= x"00";
when "11" & x"8d4" => data <= x"ad";
when "11" & x"8d5" => data <= x"58";
when "11" & x"8d6" => data <= x"0d";
when "11" & x"8d7" => data <= x"d0";
when "11" & x"8d8" => data <= x"05";
when "11" & x"8d9" => data <= x"ce";
when "11" & x"8da" => data <= x"57";
when "11" & x"8db" => data <= x"0d";
when "11" & x"8dc" => data <= x"f0";
when "11" & x"8dd" => data <= x"05";
when "11" & x"8de" => data <= x"a9";
when "11" & x"8df" => data <= x"73";
when "11" & x"8e0" => data <= x"20";
when "11" & x"8e1" => data <= x"ee";
when "11" & x"8e2" => data <= x"ff";
when "11" & x"8e3" => data <= x"20";
when "11" & x"8e4" => data <= x"44";
when "11" & x"8e5" => data <= x"b6";
when "11" & x"8e6" => data <= x"20";
when "11" & x"8e7" => data <= x"66";
when "11" & x"8e8" => data <= x"6f";
when "11" & x"8e9" => data <= x"75";
when "11" & x"8ea" => data <= x"6e";
when "11" & x"8eb" => data <= x"64";
when "11" & x"8ec" => data <= x"00";
when "11" & x"8ed" => data <= x"4c";
when "11" & x"8ee" => data <= x"e7";
when "11" & x"8ef" => data <= x"ff";
when "11" & x"8f0" => data <= x"4c";
when "11" & x"8f1" => data <= x"82";
when "11" & x"8f2" => data <= x"a0";
when "11" & x"8f3" => data <= x"4c";
when "11" & x"8f4" => data <= x"f5";
when "11" & x"8f5" => data <= x"b6";
when "11" & x"8f6" => data <= x"20";
when "11" & x"8f7" => data <= x"b0";
when "11" & x"8f8" => data <= x"b4";
when "11" & x"8f9" => data <= x"90";
when "11" & x"8fa" => data <= x"f8";
when "11" & x"8fb" => data <= x"a2";
when "11" & x"8fc" => data <= x"00";
when "11" & x"8fd" => data <= x"8e";
when "11" & x"8fe" => data <= x"57";
when "11" & x"8ff" => data <= x"0d";
when "11" & x"900" => data <= x"8e";
when "11" & x"901" => data <= x"58";
when "11" & x"902" => data <= x"0d";
when "11" & x"903" => data <= x"8e";
when "11" & x"904" => data <= x"59";
when "11" & x"905" => data <= x"0d";
when "11" & x"906" => data <= x"8e";
when "11" & x"907" => data <= x"5a";
when "11" & x"908" => data <= x"0d";
when "11" & x"909" => data <= x"a9";
when "11" & x"90a" => data <= x"80";
when "11" & x"90b" => data <= x"20";
when "11" & x"90c" => data <= x"9c";
when "11" & x"90d" => data <= x"b0";
when "11" & x"90e" => data <= x"a9";
when "11" & x"90f" => data <= x"10";
when "11" & x"910" => data <= x"85";
when "11" & x"911" => data <= x"f2";
when "11" & x"912" => data <= x"a9";
when "11" & x"913" => data <= x"0e";
when "11" & x"914" => data <= x"85";
when "11" & x"915" => data <= x"f3";
when "11" & x"916" => data <= x"a0";
when "11" & x"917" => data <= x"0f";
when "11" & x"918" => data <= x"b1";
when "11" & x"919" => data <= x"f2";
when "11" & x"91a" => data <= x"c9";
when "11" & x"91b" => data <= x"ff";
when "11" & x"91c" => data <= x"f0";
when "11" & x"91d" => data <= x"42";
when "11" & x"91e" => data <= x"f8";
when "11" & x"91f" => data <= x"a8";
when "11" & x"920" => data <= x"10";
when "11" & x"921" => data <= x"0e";
when "11" & x"922" => data <= x"18";
when "11" & x"923" => data <= x"ad";
when "11" & x"924" => data <= x"57";
when "11" & x"925" => data <= x"0d";
when "11" & x"926" => data <= x"69";
when "11" & x"927" => data <= x"01";
when "11" & x"928" => data <= x"8d";
when "11" & x"929" => data <= x"57";
when "11" & x"92a" => data <= x"0d";
when "11" & x"92b" => data <= x"90";
when "11" & x"92c" => data <= x"03";
when "11" & x"92d" => data <= x"ee";
when "11" & x"92e" => data <= x"58";
when "11" & x"92f" => data <= x"0d";
when "11" & x"930" => data <= x"18";
when "11" & x"931" => data <= x"ad";
when "11" & x"932" => data <= x"59";
when "11" & x"933" => data <= x"0d";
when "11" & x"934" => data <= x"69";
when "11" & x"935" => data <= x"01";
when "11" & x"936" => data <= x"8d";
when "11" & x"937" => data <= x"59";
when "11" & x"938" => data <= x"0d";
when "11" & x"939" => data <= x"90";
when "11" & x"93a" => data <= x"03";
when "11" & x"93b" => data <= x"ee";
when "11" & x"93c" => data <= x"5a";
when "11" & x"93d" => data <= x"0d";
when "11" & x"93e" => data <= x"d8";
when "11" & x"93f" => data <= x"18";
when "11" & x"940" => data <= x"a5";
when "11" & x"941" => data <= x"f2";
when "11" & x"942" => data <= x"69";
when "11" & x"943" => data <= x"10";
when "11" & x"944" => data <= x"85";
when "11" & x"945" => data <= x"f2";
when "11" & x"946" => data <= x"d0";
when "11" & x"947" => data <= x"ce";
when "11" & x"948" => data <= x"a5";
when "11" & x"949" => data <= x"f3";
when "11" & x"94a" => data <= x"49";
when "11" & x"94b" => data <= x"01";
when "11" & x"94c" => data <= x"85";
when "11" & x"94d" => data <= x"f3";
when "11" & x"94e" => data <= x"6a";
when "11" & x"94f" => data <= x"b0";
when "11" & x"950" => data <= x"c5";
when "11" & x"951" => data <= x"ad";
when "11" & x"952" => data <= x"82";
when "11" & x"953" => data <= x"10";
when "11" & x"954" => data <= x"69";
when "11" & x"955" => data <= x"01";
when "11" & x"956" => data <= x"c9";
when "11" & x"957" => data <= x"90";
when "11" & x"958" => data <= x"f0";
when "11" & x"959" => data <= x"06";
when "11" & x"95a" => data <= x"20";
when "11" & x"95b" => data <= x"9c";
when "11" & x"95c" => data <= x"b0";
when "11" & x"95d" => data <= x"4c";
when "11" & x"95e" => data <= x"16";
when "11" & x"95f" => data <= x"b9";
when "11" & x"960" => data <= x"a0";
when "11" & x"961" => data <= x"04";
when "11" & x"962" => data <= x"a2";
when "11" & x"963" => data <= x"00";
when "11" & x"964" => data <= x"ad";
when "11" & x"965" => data <= x"58";
when "11" & x"966" => data <= x"0d";
when "11" & x"967" => data <= x"20";
when "11" & x"968" => data <= x"26";
when "11" & x"969" => data <= x"b6";
when "11" & x"96a" => data <= x"ad";
when "11" & x"96b" => data <= x"57";
when "11" & x"96c" => data <= x"0d";
when "11" & x"96d" => data <= x"20";
when "11" & x"96e" => data <= x"26";
when "11" & x"96f" => data <= x"b6";
when "11" & x"970" => data <= x"20";
when "11" & x"971" => data <= x"44";
when "11" & x"972" => data <= x"b6";
when "11" & x"973" => data <= x"20";
when "11" & x"974" => data <= x"6f";
when "11" & x"975" => data <= x"66";
when "11" & x"976" => data <= x"20";
when "11" & x"977" => data <= x"00";
when "11" & x"978" => data <= x"a2";
when "11" & x"979" => data <= x"00";
when "11" & x"97a" => data <= x"a0";
when "11" & x"97b" => data <= x"04";
when "11" & x"97c" => data <= x"ad";
when "11" & x"97d" => data <= x"5a";
when "11" & x"97e" => data <= x"0d";
when "11" & x"97f" => data <= x"20";
when "11" & x"980" => data <= x"26";
when "11" & x"981" => data <= x"b6";
when "11" & x"982" => data <= x"ad";
when "11" & x"983" => data <= x"59";
when "11" & x"984" => data <= x"0d";
when "11" & x"985" => data <= x"20";
when "11" & x"986" => data <= x"26";
when "11" & x"987" => data <= x"b6";
when "11" & x"988" => data <= x"20";
when "11" & x"989" => data <= x"44";
when "11" & x"98a" => data <= x"b6";
when "11" & x"98b" => data <= x"20";
when "11" & x"98c" => data <= x"64";
when "11" & x"98d" => data <= x"69";
when "11" & x"98e" => data <= x"73";
when "11" & x"98f" => data <= x"6b";
when "11" & x"990" => data <= x"00";
when "11" & x"991" => data <= x"ad";
when "11" & x"992" => data <= x"5a";
when "11" & x"993" => data <= x"0d";
when "11" & x"994" => data <= x"d0";
when "11" & x"995" => data <= x"07";
when "11" & x"996" => data <= x"ad";
when "11" & x"997" => data <= x"59";
when "11" & x"998" => data <= x"0d";
when "11" & x"999" => data <= x"c9";
when "11" & x"99a" => data <= x"01";
when "11" & x"99b" => data <= x"f0";
when "11" & x"99c" => data <= x"05";
when "11" & x"99d" => data <= x"a9";
when "11" & x"99e" => data <= x"73";
when "11" & x"99f" => data <= x"20";
when "11" & x"9a0" => data <= x"ee";
when "11" & x"9a1" => data <= x"ff";
when "11" & x"9a2" => data <= x"20";
when "11" & x"9a3" => data <= x"44";
when "11" & x"9a4" => data <= x"b6";
when "11" & x"9a5" => data <= x"20";
when "11" & x"9a6" => data <= x"66";
when "11" & x"9a7" => data <= x"72";
when "11" & x"9a8" => data <= x"65";
when "11" & x"9a9" => data <= x"65";
when "11" & x"9aa" => data <= x"20";
when "11" & x"9ab" => data <= x"28";
when "11" & x"9ac" => data <= x"75";
when "11" & x"9ad" => data <= x"6e";
when "11" & x"9ae" => data <= x"66";
when "11" & x"9af" => data <= x"6f";
when "11" & x"9b0" => data <= x"72";
when "11" & x"9b1" => data <= x"6d";
when "11" & x"9b2" => data <= x"61";
when "11" & x"9b3" => data <= x"74";
when "11" & x"9b4" => data <= x"74";
when "11" & x"9b5" => data <= x"65";
when "11" & x"9b6" => data <= x"64";
when "11" & x"9b7" => data <= x"29";
when "11" & x"9b8" => data <= x"00";
when "11" & x"9b9" => data <= x"4c";
when "11" & x"9ba" => data <= x"e7";
when "11" & x"9bb" => data <= x"ff";
when "11" & x"9bc" => data <= x"20";
when "11" & x"9bd" => data <= x"30";
when "11" & x"9be" => data <= x"b7";
when "11" & x"9bf" => data <= x"a2";
when "11" & x"9c0" => data <= x"04";
when "11" & x"9c1" => data <= x"8e";
when "11" & x"9c2" => data <= x"5b";
when "11" & x"9c3" => data <= x"0d";
when "11" & x"9c4" => data <= x"a2";
when "11" & x"9c5" => data <= x"00";
when "11" & x"9c6" => data <= x"b0";
when "11" & x"9c7" => data <= x"06";
when "11" & x"9c8" => data <= x"aa";
when "11" & x"9c9" => data <= x"e8";
when "11" & x"9ca" => data <= x"8e";
when "11" & x"9cb" => data <= x"5b";
when "11" & x"9cc" => data <= x"0d";
when "11" & x"9cd" => data <= x"ca";
when "11" & x"9ce" => data <= x"8a";
when "11" & x"9cf" => data <= x"48";
when "11" & x"9d0" => data <= x"a2";
when "11" & x"9d1" => data <= x"20";
when "11" & x"9d2" => data <= x"a0";
when "11" & x"9d3" => data <= x"02";
when "11" & x"9d4" => data <= x"20";
when "11" & x"9d5" => data <= x"26";
when "11" & x"9d6" => data <= x"b6";
when "11" & x"9d7" => data <= x"a9";
when "11" & x"9d8" => data <= x"3a";
when "11" & x"9d9" => data <= x"20";
when "11" & x"9da" => data <= x"ee";
when "11" & x"9db" => data <= x"ff";
when "11" & x"9dc" => data <= x"68";
when "11" & x"9dd" => data <= x"aa";
when "11" & x"9de" => data <= x"48";
when "11" & x"9df" => data <= x"bd";
when "11" & x"9e0" => data <= x"10";
when "11" & x"9e1" => data <= x"0d";
when "11" & x"9e2" => data <= x"30";
when "11" & x"9e3" => data <= x"0f";
when "11" & x"9e4" => data <= x"6a";
when "11" & x"9e5" => data <= x"bd";
when "11" & x"9e6" => data <= x"0c";
when "11" & x"9e7" => data <= x"0d";
when "11" & x"9e8" => data <= x"20";
when "11" & x"9e9" => data <= x"a0";
when "11" & x"9ea" => data <= x"b1";
when "11" & x"9eb" => data <= x"c9";
when "11" & x"9ec" => data <= x"ff";
when "11" & x"9ed" => data <= x"f0";
when "11" & x"9ee" => data <= x"04";
when "11" & x"9ef" => data <= x"38";
when "11" & x"9f0" => data <= x"20";
when "11" & x"9f1" => data <= x"e5";
when "11" & x"9f2" => data <= x"b5";
when "11" & x"9f3" => data <= x"20";
when "11" & x"9f4" => data <= x"e7";
when "11" & x"9f5" => data <= x"ff";
when "11" & x"9f6" => data <= x"68";
when "11" & x"9f7" => data <= x"aa";
when "11" & x"9f8" => data <= x"e8";
when "11" & x"9f9" => data <= x"ec";
when "11" & x"9fa" => data <= x"5b";
when "11" & x"9fb" => data <= x"0d";
when "11" & x"9fc" => data <= x"90";
when "11" & x"9fd" => data <= x"d0";
when "11" & x"9fe" => data <= x"60";
when "11" & x"9ff" => data <= x"4c";
when "11" & x"a00" => data <= x"f5";
when "11" & x"a01" => data <= x"b6";
when "11" & x"a02" => data <= x"a9";
when "11" & x"a03" => data <= x"00";
when "11" & x"a04" => data <= x"f0";
when "11" & x"a05" => data <= x"02";
when "11" & x"a06" => data <= x"a9";
when "11" & x"a07" => data <= x"0f";
when "11" & x"a08" => data <= x"48";
when "11" & x"a09" => data <= x"20";
when "11" & x"a0a" => data <= x"61";
when "11" & x"a0b" => data <= x"b7";
when "11" & x"a0c" => data <= x"20";
when "11" & x"a0d" => data <= x"c1";
when "11" & x"a0e" => data <= x"af";
when "11" & x"a0f" => data <= x"30";
when "11" & x"a10" => data <= x"0e";
when "11" & x"a11" => data <= x"68";
when "11" & x"a12" => data <= x"b0";
when "11" & x"a13" => data <= x"05";
when "11" & x"a14" => data <= x"99";
when "11" & x"a15" => data <= x"00";
when "11" & x"a16" => data <= x"0e";
when "11" & x"a17" => data <= x"90";
when "11" & x"a18" => data <= x"03";
when "11" & x"a19" => data <= x"99";
when "11" & x"a1a" => data <= x"00";
when "11" & x"a1b" => data <= x"0f";
when "11" & x"a1c" => data <= x"4c";
when "11" & x"a1d" => data <= x"cd";
when "11" & x"a1e" => data <= x"b0";
when "11" & x"a1f" => data <= x"c9";
when "11" & x"a20" => data <= x"ff";
when "11" & x"a21" => data <= x"f0";
when "11" & x"a22" => data <= x"03";
when "11" & x"a23" => data <= x"4c";
when "11" & x"a24" => data <= x"59";
when "11" & x"a25" => data <= x"b0";
when "11" & x"a26" => data <= x"4c";
when "11" & x"a27" => data <= x"3f";
when "11" & x"a28" => data <= x"b0";
when "11" & x"a29" => data <= x"20";
when "11" & x"a2a" => data <= x"bd";
when "11" & x"a2b" => data <= x"9b";
when "11" & x"a2c" => data <= x"20";
when "11" & x"a2d" => data <= x"4f";
when "11" & x"a2e" => data <= x"b7";
when "11" & x"a2f" => data <= x"6a";
when "11" & x"a30" => data <= x"08";
when "11" & x"a31" => data <= x"8a";
when "11" & x"a32" => data <= x"48";
when "11" & x"a33" => data <= x"20";
when "11" & x"a34" => data <= x"c1";
when "11" & x"a35" => data <= x"af";
when "11" & x"a36" => data <= x"30";
when "11" & x"a37" => data <= x"e7";
when "11" & x"a38" => data <= x"68";
when "11" & x"a39" => data <= x"28";
when "11" & x"a3a" => data <= x"20";
when "11" & x"a3b" => data <= x"a0";
when "11" & x"a3c" => data <= x"b1";
when "11" & x"a3d" => data <= x"20";
when "11" & x"a3e" => data <= x"44";
when "11" & x"a3f" => data <= x"b6";
when "11" & x"a40" => data <= x"4b";
when "11" & x"a41" => data <= x"69";
when "11" & x"a42" => data <= x"6c";
when "11" & x"a43" => data <= x"6c";
when "11" & x"a44" => data <= x"00";
when "11" & x"a45" => data <= x"38";
when "11" & x"a46" => data <= x"20";
when "11" & x"a47" => data <= x"e5";
when "11" & x"a48" => data <= x"b5";
when "11" & x"a49" => data <= x"20";
when "11" & x"a4a" => data <= x"44";
when "11" & x"a4b" => data <= x"b6";
when "11" & x"a4c" => data <= x"20";
when "11" & x"a4d" => data <= x"3a";
when "11" & x"a4e" => data <= x"20";
when "11" & x"a4f" => data <= x"00";
when "11" & x"a50" => data <= x"20";
when "11" & x"a51" => data <= x"9e";
when "11" & x"a52" => data <= x"9c";
when "11" & x"a53" => data <= x"08";
when "11" & x"a54" => data <= x"20";
when "11" & x"a55" => data <= x"e7";
when "11" & x"a56" => data <= x"ff";
when "11" & x"a57" => data <= x"28";
when "11" & x"a58" => data <= x"d0";
when "11" & x"a59" => data <= x"09";
when "11" & x"a5a" => data <= x"a0";
when "11" & x"a5b" => data <= x"0f";
when "11" & x"a5c" => data <= x"a9";
when "11" & x"a5d" => data <= x"f0";
when "11" & x"a5e" => data <= x"91";
when "11" & x"a5f" => data <= x"f2";
when "11" & x"a60" => data <= x"4c";
when "11" & x"a61" => data <= x"cd";
when "11" & x"a62" => data <= x"b0";
when "11" & x"a63" => data <= x"60";
when "11" & x"a64" => data <= x"a9";
when "11" & x"a65" => data <= x"00";
when "11" & x"a66" => data <= x"20";
when "11" & x"a67" => data <= x"6e";
when "11" & x"a68" => data <= x"ba";
when "11" & x"a69" => data <= x"4c";
when "11" & x"a6a" => data <= x"63";
when "11" & x"a6b" => data <= x"af";
when "11" & x"a6c" => data <= x"a9";
when "11" & x"a6d" => data <= x"01";
when "11" & x"a6e" => data <= x"8d";
when "11" & x"a6f" => data <= x"5f";
when "11" & x"a70" => data <= x"0d";
when "11" & x"a71" => data <= x"20";
when "11" & x"a72" => data <= x"4f";
when "11" & x"a73" => data <= x"b7";
when "11" & x"a74" => data <= x"6a";
when "11" & x"a75" => data <= x"08";
when "11" & x"a76" => data <= x"8a";
when "11" & x"a77" => data <= x"48";
when "11" & x"a78" => data <= x"20";
when "11" & x"a79" => data <= x"c1";
when "11" & x"a7a" => data <= x"af";
when "11" & x"a7b" => data <= x"10";
when "11" & x"a7c" => data <= x"26";
when "11" & x"a7d" => data <= x"aa";
when "11" & x"a7e" => data <= x"e8";
when "11" & x"a7f" => data <= x"f0";
when "11" & x"a80" => data <= x"3d";
when "11" & x"a81" => data <= x"98";
when "11" & x"a82" => data <= x"29";
when "11" & x"a83" => data <= x"f0";
when "11" & x"a84" => data <= x"85";
when "11" & x"a85" => data <= x"f2";
when "11" & x"a86" => data <= x"a0";
when "11" & x"a87" => data <= x"0e";
when "11" & x"a88" => data <= x"90";
when "11" & x"a89" => data <= x"01";
when "11" & x"a8a" => data <= x"c8";
when "11" & x"a8b" => data <= x"84";
when "11" & x"a8c" => data <= x"f3";
when "11" & x"a8d" => data <= x"a0";
when "11" & x"a8e" => data <= x"0f";
when "11" & x"a8f" => data <= x"98";
when "11" & x"a90" => data <= x"91";
when "11" & x"a91" => data <= x"f2";
when "11" & x"a92" => data <= x"ad";
when "11" & x"a93" => data <= x"5f";
when "11" & x"a94" => data <= x"0d";
when "11" & x"a95" => data <= x"d0";
when "11" & x"a96" => data <= x"06";
when "11" & x"a97" => data <= x"88";
when "11" & x"a98" => data <= x"91";
when "11" & x"a99" => data <= x"f2";
when "11" & x"a9a" => data <= x"88";
when "11" & x"a9b" => data <= x"10";
when "11" & x"a9c" => data <= x"fb";
when "11" & x"a9d" => data <= x"20";
when "11" & x"a9e" => data <= x"cd";
when "11" & x"a9f" => data <= x"b0";
when "11" & x"aa0" => data <= x"68";
when "11" & x"aa1" => data <= x"28";
when "11" & x"aa2" => data <= x"60";
when "11" & x"aa3" => data <= x"20";
when "11" & x"aa4" => data <= x"00";
when "11" & x"aa5" => data <= x"a0";
when "11" & x"aa6" => data <= x"ff";
when "11" & x"aa7" => data <= x"44";
when "11" & x"aa8" => data <= x"69";
when "11" & x"aa9" => data <= x"73";
when "11" & x"aaa" => data <= x"6b";
when "11" & x"aab" => data <= x"20";
when "11" & x"aac" => data <= x"61";
when "11" & x"aad" => data <= x"6c";
when "11" & x"aae" => data <= x"72";
when "11" & x"aaf" => data <= x"65";
when "11" & x"ab0" => data <= x"61";
when "11" & x"ab1" => data <= x"64";
when "11" & x"ab2" => data <= x"79";
when "11" & x"ab3" => data <= x"20";
when "11" & x"ab4" => data <= x"66";
when "11" & x"ab5" => data <= x"6f";
when "11" & x"ab6" => data <= x"72";
when "11" & x"ab7" => data <= x"6d";
when "11" & x"ab8" => data <= x"61";
when "11" & x"ab9" => data <= x"74";
when "11" & x"aba" => data <= x"74";
when "11" & x"abb" => data <= x"65";
when "11" & x"abc" => data <= x"64";
when "11" & x"abd" => data <= x"00";
when "11" & x"abe" => data <= x"4c";
when "11" & x"abf" => data <= x"3f";
when "11" & x"ac0" => data <= x"b0";
when "11" & x"ac1" => data <= x"20";
when "11" & x"ac2" => data <= x"30";
when "11" & x"ac3" => data <= x"b7";
when "11" & x"ac4" => data <= x"8d";
when "11" & x"ac5" => data <= x"5b";
when "11" & x"ac6" => data <= x"0d";
when "11" & x"ac7" => data <= x"20";
when "11" & x"ac8" => data <= x"25";
when "11" & x"ac9" => data <= x"bb";
when "11" & x"aca" => data <= x"08";
when "11" & x"acb" => data <= x"48";
when "11" & x"acc" => data <= x"a9";
when "11" & x"acd" => data <= x"0f";
when "11" & x"ace" => data <= x"91";
when "11" & x"acf" => data <= x"f2";
when "11" & x"ad0" => data <= x"88";
when "11" & x"ad1" => data <= x"a9";
when "11" & x"ad2" => data <= x"00";
when "11" & x"ad3" => data <= x"91";
when "11" & x"ad4" => data <= x"f2";
when "11" & x"ad5" => data <= x"88";
when "11" & x"ad6" => data <= x"10";
when "11" & x"ad7" => data <= x"fb";
when "11" & x"ad8" => data <= x"20";
when "11" & x"ad9" => data <= x"b8";
when "11" & x"ada" => data <= x"b0";
when "11" & x"adb" => data <= x"68";
when "11" & x"adc" => data <= x"28";
when "11" & x"add" => data <= x"08";
when "11" & x"ade" => data <= x"48";
when "11" & x"adf" => data <= x"20";
when "11" & x"ae0" => data <= x"63";
when "11" & x"ae1" => data <= x"af";
when "11" & x"ae2" => data <= x"68";
when "11" & x"ae3" => data <= x"28";
when "11" & x"ae4" => data <= x"08";
when "11" & x"ae5" => data <= x"48";
when "11" & x"ae6" => data <= x"ae";
when "11" & x"ae7" => data <= x"5b";
when "11" & x"ae8" => data <= x"0d";
when "11" & x"ae9" => data <= x"20";
when "11" & x"aea" => data <= x"0f";
when "11" & x"aeb" => data <= x"b0";
when "11" & x"aec" => data <= x"20";
when "11" & x"aed" => data <= x"44";
when "11" & x"aee" => data <= x"b6";
when "11" & x"aef" => data <= x"44";
when "11" & x"af0" => data <= x"69";
when "11" & x"af1" => data <= x"73";
when "11" & x"af2" => data <= x"6b";
when "11" & x"af3" => data <= x"20";
when "11" & x"af4" => data <= x"00";
when "11" & x"af5" => data <= x"68";
when "11" & x"af6" => data <= x"28";
when "11" & x"af7" => data <= x"20";
when "11" & x"af8" => data <= x"6c";
when "11" & x"af9" => data <= x"ad";
when "11" & x"afa" => data <= x"8e";
when "11" & x"afb" => data <= x"55";
when "11" & x"afc" => data <= x"0d";
when "11" & x"afd" => data <= x"a2";
when "11" & x"afe" => data <= x"00";
when "11" & x"aff" => data <= x"a0";
when "11" & x"b00" => data <= x"04";
when "11" & x"b01" => data <= x"20";
when "11" & x"b02" => data <= x"26";
when "11" & x"b03" => data <= x"b6";
when "11" & x"b04" => data <= x"ad";
when "11" & x"b05" => data <= x"55";
when "11" & x"b06" => data <= x"0d";
when "11" & x"b07" => data <= x"20";
when "11" & x"b08" => data <= x"26";
when "11" & x"b09" => data <= x"b6";
when "11" & x"b0a" => data <= x"20";
when "11" & x"b0b" => data <= x"44";
when "11" & x"b0c" => data <= x"b6";
when "11" & x"b0d" => data <= x"20";
when "11" & x"b0e" => data <= x"69";
when "11" & x"b0f" => data <= x"6e";
when "11" & x"b10" => data <= x"20";
when "11" & x"b11" => data <= x"64";
when "11" & x"b12" => data <= x"72";
when "11" & x"b13" => data <= x"69";
when "11" & x"b14" => data <= x"76";
when "11" & x"b15" => data <= x"65";
when "11" & x"b16" => data <= x"20";
when "11" & x"b17" => data <= x"00";
when "11" & x"b18" => data <= x"ad";
when "11" & x"b19" => data <= x"5b";
when "11" & x"b1a" => data <= x"0d";
when "11" & x"b1b" => data <= x"a2";
when "11" & x"b1c" => data <= x"00";
when "11" & x"b1d" => data <= x"a0";
when "11" & x"b1e" => data <= x"02";
when "11" & x"b1f" => data <= x"20";
when "11" & x"b20" => data <= x"26";
when "11" & x"b21" => data <= x"b6";
when "11" & x"b22" => data <= x"4c";
when "11" & x"b23" => data <= x"e7";
when "11" & x"b24" => data <= x"ff";
when "11" & x"b25" => data <= x"a9";
when "11" & x"b26" => data <= x"10";
when "11" & x"b27" => data <= x"85";
when "11" & x"b28" => data <= x"f2";
when "11" & x"b29" => data <= x"a9";
when "11" & x"b2a" => data <= x"0e";
when "11" & x"b2b" => data <= x"85";
when "11" & x"b2c" => data <= x"f3";
when "11" & x"b2d" => data <= x"a9";
when "11" & x"b2e" => data <= x"80";
when "11" & x"b2f" => data <= x"8d";
when "11" & x"b30" => data <= x"52";
when "11" & x"b31" => data <= x"0d";
when "11" & x"b32" => data <= x"20";
when "11" & x"b33" => data <= x"a1";
when "11" & x"b34" => data <= x"b0";
when "11" & x"b35" => data <= x"a9";
when "11" & x"b36" => data <= x"00";
when "11" & x"b37" => data <= x"8d";
when "11" & x"b38" => data <= x"53";
when "11" & x"b39" => data <= x"0d";
when "11" & x"b3a" => data <= x"8d";
when "11" & x"b3b" => data <= x"54";
when "11" & x"b3c" => data <= x"0d";
when "11" & x"b3d" => data <= x"a0";
when "11" & x"b3e" => data <= x"0f";
when "11" & x"b3f" => data <= x"b1";
when "11" & x"b40" => data <= x"f2";
when "11" & x"b41" => data <= x"10";
when "11" & x"b42" => data <= x"0c";
when "11" & x"b43" => data <= x"c9";
when "11" & x"b44" => data <= x"ff";
when "11" & x"b45" => data <= x"f0";
when "11" & x"b46" => data <= x"36";
when "11" & x"b47" => data <= x"ad";
when "11" & x"b48" => data <= x"54";
when "11" & x"b49" => data <= x"0d";
when "11" & x"b4a" => data <= x"6a";
when "11" & x"b4b" => data <= x"ad";
when "11" & x"b4c" => data <= x"53";
when "11" & x"b4d" => data <= x"0d";
when "11" & x"b4e" => data <= x"60";
when "11" & x"b4f" => data <= x"ee";
when "11" & x"b50" => data <= x"53";
when "11" & x"b51" => data <= x"0d";
when "11" & x"b52" => data <= x"d0";
when "11" & x"b53" => data <= x"03";
when "11" & x"b54" => data <= x"ee";
when "11" & x"b55" => data <= x"54";
when "11" & x"b56" => data <= x"0d";
when "11" & x"b57" => data <= x"18";
when "11" & x"b58" => data <= x"a5";
when "11" & x"b59" => data <= x"f2";
when "11" & x"b5a" => data <= x"69";
when "11" & x"b5b" => data <= x"10";
when "11" & x"b5c" => data <= x"85";
when "11" & x"b5d" => data <= x"f2";
when "11" & x"b5e" => data <= x"d0";
when "11" & x"b5f" => data <= x"df";
when "11" & x"b60" => data <= x"a5";
when "11" & x"b61" => data <= x"f3";
when "11" & x"b62" => data <= x"49";
when "11" & x"b63" => data <= x"01";
when "11" & x"b64" => data <= x"85";
when "11" & x"b65" => data <= x"f3";
when "11" & x"b66" => data <= x"29";
when "11" & x"b67" => data <= x"01";
when "11" & x"b68" => data <= x"d0";
when "11" & x"b69" => data <= x"d5";
when "11" & x"b6a" => data <= x"18";
when "11" & x"b6b" => data <= x"ad";
when "11" & x"b6c" => data <= x"52";
when "11" & x"b6d" => data <= x"0d";
when "11" & x"b6e" => data <= x"69";
when "11" & x"b6f" => data <= x"01";
when "11" & x"b70" => data <= x"c9";
when "11" & x"b71" => data <= x"90";
when "11" & x"b72" => data <= x"f0";
when "11" & x"b73" => data <= x"09";
when "11" & x"b74" => data <= x"8d";
when "11" & x"b75" => data <= x"52";
when "11" & x"b76" => data <= x"0d";
when "11" & x"b77" => data <= x"20";
when "11" & x"b78" => data <= x"a1";
when "11" & x"b79" => data <= x"b0";
when "11" & x"b7a" => data <= x"4c";
when "11" & x"b7b" => data <= x"3d";
when "11" & x"b7c" => data <= x"bb";
when "11" & x"b7d" => data <= x"20";
when "11" & x"b7e" => data <= x"00";
when "11" & x"b7f" => data <= x"a0";
when "11" & x"b80" => data <= x"ff";
when "11" & x"b81" => data <= x"4e";
when "11" & x"b82" => data <= x"6f";
when "11" & x"b83" => data <= x"20";
when "11" & x"b84" => data <= x"66";
when "11" & x"b85" => data <= x"72";
when "11" & x"b86" => data <= x"65";
when "11" & x"b87" => data <= x"65";
when "11" & x"b88" => data <= x"20";
when "11" & x"b89" => data <= x"64";
when "11" & x"b8a" => data <= x"69";
when "11" & x"b8b" => data <= x"73";
when "11" & x"b8c" => data <= x"6b";
when "11" & x"b8d" => data <= x"73";
when "11" & x"b8e" => data <= x"00";
when "11" & x"b8f" => data <= x"20";
when "11" & x"b90" => data <= x"8a";
when "11" & x"b91" => data <= x"b7";
when "11" & x"b92" => data <= x"08";
when "11" & x"b93" => data <= x"48";
when "11" & x"b94" => data <= x"8a";
when "11" & x"b95" => data <= x"48";
when "11" & x"b96" => data <= x"a9";
when "11" & x"b97" => data <= x"80";
when "11" & x"b98" => data <= x"20";
when "11" & x"b99" => data <= x"a1";
when "11" & x"b9a" => data <= x"b0";
when "11" & x"b9b" => data <= x"68";
when "11" & x"b9c" => data <= x"aa";
when "11" & x"b9d" => data <= x"68";
when "11" & x"b9e" => data <= x"9d";
when "11" & x"b9f" => data <= x"00";
when "11" & x"ba0" => data <= x"0e";
when "11" & x"ba1" => data <= x"68";
when "11" & x"ba2" => data <= x"29";
when "11" & x"ba3" => data <= x"01";
when "11" & x"ba4" => data <= x"9d";
when "11" & x"ba5" => data <= x"04";
when "11" & x"ba6" => data <= x"0e";
when "11" & x"ba7" => data <= x"4c";
when "11" & x"ba8" => data <= x"b8";
when "11" & x"ba9" => data <= x"b0";
when "11" & x"baa" => data <= x"20";
when "11" & x"bab" => data <= x"e4";
when "11" & x"bac" => data <= x"bb";
when "11" & x"bad" => data <= x"20";
when "11" & x"bae" => data <= x"b0";
when "11" & x"baf" => data <= x"b4";
when "11" & x"bb0" => data <= x"a2";
when "11" & x"bb1" => data <= x"00";
when "11" & x"bb2" => data <= x"b0";
when "11" & x"bb3" => data <= x"10";
when "11" & x"bb4" => data <= x"20";
when "11" & x"bb5" => data <= x"c3";
when "11" & x"bb6" => data <= x"b4";
when "11" & x"bb7" => data <= x"b0";
when "11" & x"bb8" => data <= x"17";
when "11" & x"bb9" => data <= x"c9";
when "11" & x"bba" => data <= x"00";
when "11" & x"bbb" => data <= x"d0";
when "11" & x"bbc" => data <= x"04";
when "11" & x"bbd" => data <= x"e0";
when "11" & x"bbe" => data <= x"00";
when "11" & x"bbf" => data <= x"f0";
when "11" & x"bc0" => data <= x"03";
when "11" & x"bc1" => data <= x"20";
when "11" & x"bc2" => data <= x"ef";
when "11" & x"bc3" => data <= x"bb";
when "11" & x"bc4" => data <= x"20";
when "11" & x"bc5" => data <= x"e2";
when "11" & x"bc6" => data <= x"8d";
when "11" & x"bc7" => data <= x"a2";
when "11" & x"bc8" => data <= x"ff";
when "11" & x"bc9" => data <= x"8a";
when "11" & x"bca" => data <= x"8d";
when "11" & x"bcb" => data <= x"52";
when "11" & x"bcc" => data <= x"0d";
when "11" & x"bcd" => data <= x"4c";
when "11" & x"bce" => data <= x"3a";
when "11" & x"bcf" => data <= x"b1";
when "11" & x"bd0" => data <= x"20";
when "11" & x"bd1" => data <= x"00";
when "11" & x"bd2" => data <= x"a0";
when "11" & x"bd3" => data <= x"ff";
when "11" & x"bd4" => data <= x"42";
when "11" & x"bd5" => data <= x"61";
when "11" & x"bd6" => data <= x"64";
when "11" & x"bd7" => data <= x"20";
when "11" & x"bd8" => data <= x"66";
when "11" & x"bd9" => data <= x"69";
when "11" & x"bda" => data <= x"6c";
when "11" & x"bdb" => data <= x"65";
when "11" & x"bdc" => data <= x"20";
when "11" & x"bdd" => data <= x"6e";
when "11" & x"bde" => data <= x"75";
when "11" & x"bdf" => data <= x"6d";
when "11" & x"be0" => data <= x"62";
when "11" & x"be1" => data <= x"65";
when "11" & x"be2" => data <= x"72";
when "11" & x"be3" => data <= x"00";
when "11" & x"be4" => data <= x"a2";
when "11" & x"be5" => data <= x"03";
when "11" & x"be6" => data <= x"a9";
when "11" & x"be7" => data <= x"20";
when "11" & x"be8" => data <= x"9d";
when "11" & x"be9" => data <= x"74";
when "11" & x"bea" => data <= x"0d";
when "11" & x"beb" => data <= x"ca";
when "11" & x"bec" => data <= x"10";
when "11" & x"bed" => data <= x"f8";
when "11" & x"bee" => data <= x"60";
when "11" & x"bef" => data <= x"c0";
when "11" & x"bf0" => data <= x"09";
when "11" & x"bf1" => data <= x"b0";
when "11" & x"bf2" => data <= x"dd";
when "11" & x"bf3" => data <= x"a0";
when "11" & x"bf4" => data <= x"03";
when "11" & x"bf5" => data <= x"b1";
when "11" & x"bf6" => data <= x"f2";
when "11" & x"bf7" => data <= x"29";
when "11" & x"bf8" => data <= x"4f";
when "11" & x"bf9" => data <= x"c9";
when "11" & x"bfa" => data <= x"42";
when "11" & x"bfb" => data <= x"d0";
when "11" & x"bfc" => data <= x"d3";
when "11" & x"bfd" => data <= x"a2";
when "11" & x"bfe" => data <= x"00";
when "11" & x"bff" => data <= x"c8";
when "11" & x"c00" => data <= x"b1";
when "11" & x"c01" => data <= x"f2";
when "11" & x"c02" => data <= x"c9";
when "11" & x"c03" => data <= x"20";
when "11" & x"c04" => data <= x"f0";
when "11" & x"c05" => data <= x"f9";
when "11" & x"c06" => data <= x"c9";
when "11" & x"c07" => data <= x"0d";
when "11" & x"c08" => data <= x"f0";
when "11" & x"c09" => data <= x"08";
when "11" & x"c0a" => data <= x"9d";
when "11" & x"c0b" => data <= x"74";
when "11" & x"c0c" => data <= x"0d";
when "11" & x"c0d" => data <= x"e8";
when "11" & x"c0e" => data <= x"e0";
when "11" & x"c0f" => data <= x"04";
when "11" & x"c10" => data <= x"90";
when "11" & x"c11" => data <= x"ed";
when "11" & x"c12" => data <= x"a2";
when "11" & x"c13" => data <= x"00";
when "11" & x"c14" => data <= x"60";
when "11" & x"c15" => data <= x"4c";
when "11" & x"c16" => data <= x"1e";
when "11" & x"c17" => data <= x"bc";
when "11" & x"c18" => data <= x"4c";
when "11" & x"c19" => data <= x"2b";
when "11" & x"c1a" => data <= x"bc";
when "11" & x"c1b" => data <= x"4c";
when "11" & x"c1c" => data <= x"38";
when "11" & x"c1d" => data <= x"bc";
when "11" & x"c1e" => data <= x"20";
when "11" & x"c1f" => data <= x"d8";
when "11" & x"c20" => data <= x"bd";
when "11" & x"c21" => data <= x"20";
when "11" & x"c22" => data <= x"a7";
when "11" & x"c23" => data <= x"bd";
when "11" & x"c24" => data <= x"20";
when "11" & x"c25" => data <= x"d0";
when "11" & x"c26" => data <= x"bd";
when "11" & x"c27" => data <= x"20";
when "11" & x"c28" => data <= x"05";
when "11" & x"c29" => data <= x"be";
when "11" & x"c2a" => data <= x"60";
when "11" & x"c2b" => data <= x"20";
when "11" & x"c2c" => data <= x"d8";
when "11" & x"c2d" => data <= x"bd";
when "11" & x"c2e" => data <= x"20";
when "11" & x"c2f" => data <= x"a7";
when "11" & x"c30" => data <= x"bd";
when "11" & x"c31" => data <= x"20";
when "11" & x"c32" => data <= x"d4";
when "11" & x"c33" => data <= x"bd";
when "11" & x"c34" => data <= x"20";
when "11" & x"c35" => data <= x"05";
when "11" & x"c36" => data <= x"be";
when "11" & x"c37" => data <= x"60";
when "11" & x"c38" => data <= x"a9";
when "11" & x"c39" => data <= x"00";
when "11" & x"c3a" => data <= x"8d";
when "11" & x"c3b" => data <= x"28";
when "11" & x"c3c" => data <= x"0d";
when "11" & x"c3d" => data <= x"20";
when "11" & x"c3e" => data <= x"c2";
when "11" & x"c3f" => data <= x"ff";
when "11" & x"c40" => data <= x"f0";
when "11" & x"c41" => data <= x"6e";
when "11" & x"c42" => data <= x"b1";
when "11" & x"c43" => data <= x"f2";
when "11" & x"c44" => data <= x"c8";
when "11" & x"c45" => data <= x"c9";
when "11" & x"c46" => data <= x"20";
when "11" & x"c47" => data <= x"f0";
when "11" & x"c48" => data <= x"f9";
when "11" & x"c49" => data <= x"b1";
when "11" & x"c4a" => data <= x"f2";
when "11" & x"c4b" => data <= x"88";
when "11" & x"c4c" => data <= x"c9";
when "11" & x"c4d" => data <= x"20";
when "11" & x"c4e" => data <= x"d0";
when "11" & x"c4f" => data <= x"24";
when "11" & x"c50" => data <= x"b1";
when "11" & x"c51" => data <= x"f2";
when "11" & x"c52" => data <= x"38";
when "11" & x"c53" => data <= x"e9";
when "11" & x"c54" => data <= x"30";
when "11" & x"c55" => data <= x"30";
when "11" & x"c56" => data <= x"1d";
when "11" & x"c57" => data <= x"c9";
when "11" & x"c58" => data <= x"0a";
when "11" & x"c59" => data <= x"90";
when "11" & x"c5a" => data <= x"14";
when "11" & x"c5b" => data <= x"e9";
when "11" & x"c5c" => data <= x"07";
when "11" & x"c5d" => data <= x"c9";
when "11" & x"c5e" => data <= x"0a";
when "11" & x"c5f" => data <= x"90";
when "11" & x"c60" => data <= x"13";
when "11" & x"c61" => data <= x"c9";
when "11" & x"c62" => data <= x"10";
when "11" & x"c63" => data <= x"90";
when "11" & x"c64" => data <= x"0a";
when "11" & x"c65" => data <= x"e9";
when "11" & x"c66" => data <= x"20";
when "11" & x"c67" => data <= x"c9";
when "11" & x"c68" => data <= x"0a";
when "11" & x"c69" => data <= x"90";
when "11" & x"c6a" => data <= x"09";
when "11" & x"c6b" => data <= x"c9";
when "11" & x"c6c" => data <= x"10";
when "11" & x"c6d" => data <= x"b0";
when "11" & x"c6e" => data <= x"05";
when "11" & x"c6f" => data <= x"c8";
when "11" & x"c70" => data <= x"c8";
when "11" & x"c71" => data <= x"8d";
when "11" & x"c72" => data <= x"28";
when "11" & x"c73" => data <= x"0d";
when "11" & x"c74" => data <= x"a5";
when "11" & x"c75" => data <= x"f4";
when "11" & x"c76" => data <= x"8d";
when "11" & x"c77" => data <= x"29";
when "11" & x"c78" => data <= x"0d";
when "11" & x"c79" => data <= x"98";
when "11" & x"c7a" => data <= x"48";
when "11" & x"c7b" => data <= x"a0";
when "11" & x"c7c" => data <= x"26";
when "11" & x"c7d" => data <= x"b9";
when "11" & x"c7e" => data <= x"81";
when "11" & x"c7f" => data <= x"bd";
when "11" & x"c80" => data <= x"99";
when "11" & x"c81" => data <= x"52";
when "11" & x"c82" => data <= x"0d";
when "11" & x"c83" => data <= x"88";
when "11" & x"c84" => data <= x"10";
when "11" & x"c85" => data <= x"f7";
when "11" & x"c86" => data <= x"a2";
when "11" & x"c87" => data <= x"0f";
when "11" & x"c88" => data <= x"20";
when "11" & x"c89" => data <= x"52";
when "11" & x"c8a" => data <= x"0d";
when "11" & x"c8b" => data <= x"68";
when "11" & x"c8c" => data <= x"a8";
when "11" & x"c8d" => data <= x"8e";
when "11" & x"c8e" => data <= x"28";
when "11" & x"c8f" => data <= x"0d";
when "11" & x"c90" => data <= x"8a";
when "11" & x"c91" => data <= x"10";
when "11" & x"c92" => data <= x"14";
when "11" & x"c93" => data <= x"20";
when "11" & x"c94" => data <= x"00";
when "11" & x"c95" => data <= x"a0";
when "11" & x"c96" => data <= x"ff";
when "11" & x"c97" => data <= x"4e";
when "11" & x"c98" => data <= x"6f";
when "11" & x"c99" => data <= x"20";
when "11" & x"c9a" => data <= x"53";
when "11" & x"c9b" => data <= x"69";
when "11" & x"c9c" => data <= x"64";
when "11" & x"c9d" => data <= x"65";
when "11" & x"c9e" => data <= x"77";
when "11" & x"c9f" => data <= x"61";
when "11" & x"ca0" => data <= x"79";
when "11" & x"ca1" => data <= x"73";
when "11" & x"ca2" => data <= x"20";
when "11" & x"ca3" => data <= x"52";
when "11" & x"ca4" => data <= x"41";
when "11" & x"ca5" => data <= x"4d";
when "11" & x"ca6" => data <= x"00";
when "11" & x"ca7" => data <= x"20";
when "11" & x"ca8" => data <= x"62";
when "11" & x"ca9" => data <= x"82";
when "11" & x"caa" => data <= x"18";
when "11" & x"cab" => data <= x"20";
when "11" & x"cac" => data <= x"c2";
when "11" & x"cad" => data <= x"ff";
when "11" & x"cae" => data <= x"d0";
when "11" & x"caf" => data <= x"03";
when "11" & x"cb0" => data <= x"4c";
when "11" & x"cb1" => data <= x"f5";
when "11" & x"cb2" => data <= x"b6";
when "11" & x"cb3" => data <= x"20";
when "11" & x"cb4" => data <= x"fe";
when "11" & x"cb5" => data <= x"80";
when "11" & x"cb6" => data <= x"98";
when "11" & x"cb7" => data <= x"20";
when "11" & x"cb8" => data <= x"71";
when "11" & x"cb9" => data <= x"82";
when "11" & x"cba" => data <= x"b9";
when "11" & x"cbb" => data <= x"0e";
when "11" & x"cbc" => data <= x"0f";
when "11" & x"cbd" => data <= x"48";
when "11" & x"cbe" => data <= x"29";
when "11" & x"cbf" => data <= x"03";
when "11" & x"cc0" => data <= x"85";
when "11" & x"cc1" => data <= x"a1";
when "11" & x"cc2" => data <= x"b9";
when "11" & x"cc3" => data <= x"0f";
when "11" & x"cc4" => data <= x"0f";
when "11" & x"cc5" => data <= x"85";
when "11" & x"cc6" => data <= x"a0";
when "11" & x"cc7" => data <= x"68";
when "11" & x"cc8" => data <= x"4a";
when "11" & x"cc9" => data <= x"4a";
when "11" & x"cca" => data <= x"29";
when "11" & x"ccb" => data <= x"03";
when "11" & x"ccc" => data <= x"f0";
when "11" & x"ccd" => data <= x"04";
when "11" & x"cce" => data <= x"49";
when "11" & x"ccf" => data <= x"03";
when "11" & x"cd0" => data <= x"d0";
when "11" & x"cd1" => data <= x"17";
when "11" & x"cd2" => data <= x"b9";
when "11" & x"cd3" => data <= x"0c";
when "11" & x"cd4" => data <= x"0f";
when "11" & x"cd5" => data <= x"d0";
when "11" & x"cd6" => data <= x"12";
when "11" & x"cd7" => data <= x"b9";
when "11" & x"cd8" => data <= x"0d";
when "11" & x"cd9" => data <= x"0f";
when "11" & x"cda" => data <= x"30";
when "11" & x"cdb" => data <= x"0d";
when "11" & x"cdc" => data <= x"8d";
when "11" & x"cdd" => data <= x"27";
when "11" & x"cde" => data <= x"0d";
when "11" & x"cdf" => data <= x"a2";
when "11" & x"ce0" => data <= x"05";
when "11" & x"ce1" => data <= x"c9";
when "11" & x"ce2" => data <= x"40";
when "11" & x"ce3" => data <= x"f0";
when "11" & x"ce4" => data <= x"15";
when "11" & x"ce5" => data <= x"0a";
when "11" & x"ce6" => data <= x"ca";
when "11" & x"ce7" => data <= x"d0";
when "11" & x"ce8" => data <= x"f8";
when "11" & x"ce9" => data <= x"20";
when "11" & x"cea" => data <= x"00";
when "11" & x"ceb" => data <= x"a0";
when "11" & x"cec" => data <= x"ff";
when "11" & x"ced" => data <= x"42";
when "11" & x"cee" => data <= x"61";
when "11" & x"cef" => data <= x"64";
when "11" & x"cf0" => data <= x"20";
when "11" & x"cf1" => data <= x"52";
when "11" & x"cf2" => data <= x"4f";
when "11" & x"cf3" => data <= x"4d";
when "11" & x"cf4" => data <= x"20";
when "11" & x"cf5" => data <= x"73";
when "11" & x"cf6" => data <= x"69";
when "11" & x"cf7" => data <= x"7a";
when "11" & x"cf8" => data <= x"65";
when "11" & x"cf9" => data <= x"00";
when "11" & x"cfa" => data <= x"4e";
when "11" & x"cfb" => data <= x"27";
when "11" & x"cfc" => data <= x"0d";
when "11" & x"cfd" => data <= x"a6";
when "11" & x"cfe" => data <= x"cf";
when "11" & x"cff" => data <= x"20";
when "11" & x"d00" => data <= x"1d";
when "11" & x"d01" => data <= x"ae";
when "11" & x"d02" => data <= x"18";
when "11" & x"d03" => data <= x"ad";
when "11" & x"d04" => data <= x"23";
when "11" & x"d05" => data <= x"0d";
when "11" & x"d06" => data <= x"65";
when "11" & x"d07" => data <= x"a0";
when "11" & x"d08" => data <= x"8d";
when "11" & x"d09" => data <= x"23";
when "11" & x"d0a" => data <= x"0d";
when "11" & x"d0b" => data <= x"ad";
when "11" & x"d0c" => data <= x"24";
when "11" & x"d0d" => data <= x"0d";
when "11" & x"d0e" => data <= x"65";
when "11" & x"d0f" => data <= x"a1";
when "11" & x"d10" => data <= x"8d";
when "11" & x"d11" => data <= x"24";
when "11" & x"d12" => data <= x"0d";
when "11" & x"d13" => data <= x"a9";
when "11" & x"d14" => data <= x"00";
when "11" & x"d15" => data <= x"6d";
when "11" & x"d16" => data <= x"25";
when "11" & x"d17" => data <= x"0d";
when "11" & x"d18" => data <= x"8d";
when "11" & x"d19" => data <= x"25";
when "11" & x"d1a" => data <= x"0d";
when "11" & x"d1b" => data <= x"a0";
when "11" & x"d1c" => data <= x"1c";
when "11" & x"d1d" => data <= x"b9";
when "11" & x"d1e" => data <= x"65";
when "11" & x"d1f" => data <= x"bd";
when "11" & x"d20" => data <= x"99";
when "11" & x"d21" => data <= x"52";
when "11" & x"d22" => data <= x"0d";
when "11" & x"d23" => data <= x"88";
when "11" & x"d24" => data <= x"10";
when "11" & x"d25" => data <= x"f7";
when "11" & x"d26" => data <= x"ad";
when "11" & x"d27" => data <= x"28";
when "11" & x"d28" => data <= x"0d";
when "11" & x"d29" => data <= x"8d";
when "11" & x"d2a" => data <= x"53";
when "11" & x"d2b" => data <= x"0d";
when "11" & x"d2c" => data <= x"ad";
when "11" & x"d2d" => data <= x"29";
when "11" & x"d2e" => data <= x"0d";
when "11" & x"d2f" => data <= x"8d";
when "11" & x"d30" => data <= x"69";
when "11" & x"d31" => data <= x"0d";
when "11" & x"d32" => data <= x"20";
when "11" & x"d33" => data <= x"1f";
when "11" & x"d34" => data <= x"a6";
when "11" & x"d35" => data <= x"a9";
when "11" & x"d36" => data <= x"ff";
when "11" & x"d37" => data <= x"8d";
when "11" & x"d38" => data <= x"82";
when "11" & x"d39" => data <= x"10";
when "11" & x"d3a" => data <= x"20";
when "11" & x"d3b" => data <= x"99";
when "11" & x"d3c" => data <= x"a7";
when "11" & x"d3d" => data <= x"20";
when "11" & x"d3e" => data <= x"52";
when "11" & x"d3f" => data <= x"0d";
when "11" & x"d40" => data <= x"18";
when "11" & x"d41" => data <= x"ad";
when "11" & x"d42" => data <= x"23";
when "11" & x"d43" => data <= x"0d";
when "11" & x"d44" => data <= x"69";
when "11" & x"d45" => data <= x"02";
when "11" & x"d46" => data <= x"8d";
when "11" & x"d47" => data <= x"23";
when "11" & x"d48" => data <= x"0d";
when "11" & x"d49" => data <= x"90";
when "11" & x"d4a" => data <= x"08";
when "11" & x"d4b" => data <= x"ee";
when "11" & x"d4c" => data <= x"24";
when "11" & x"d4d" => data <= x"0d";
when "11" & x"d4e" => data <= x"d0";
when "11" & x"d4f" => data <= x"03";
when "11" & x"d50" => data <= x"ee";
when "11" & x"d51" => data <= x"24";
when "11" & x"d52" => data <= x"0d";
when "11" & x"d53" => data <= x"ee";
when "11" & x"d54" => data <= x"5e";
when "11" & x"d55" => data <= x"0d";
when "11" & x"d56" => data <= x"ee";
when "11" & x"d57" => data <= x"5e";
when "11" & x"d58" => data <= x"0d";
when "11" & x"d59" => data <= x"ee";
when "11" & x"d5a" => data <= x"64";
when "11" & x"d5b" => data <= x"0d";
when "11" & x"d5c" => data <= x"ee";
when "11" & x"d5d" => data <= x"64";
when "11" & x"d5e" => data <= x"0d";
when "11" & x"d5f" => data <= x"ce";
when "11" & x"d60" => data <= x"27";
when "11" & x"d61" => data <= x"0d";
when "11" & x"d62" => data <= x"d0";
when "11" & x"d63" => data <= x"d6";
when "11" & x"d64" => data <= x"60";
when "11" & x"d65" => data <= x"a9";
when "11" & x"d66" => data <= x"00";
when "11" & x"d67" => data <= x"8d";
when "11" & x"d68" => data <= x"30";
when "11" & x"d69" => data <= x"fe";
when "11" & x"d6a" => data <= x"a0";
when "11" & x"d6b" => data <= x"00";
when "11" & x"d6c" => data <= x"b9";
when "11" & x"d6d" => data <= x"00";
when "11" & x"d6e" => data <= x"0e";
when "11" & x"d6f" => data <= x"99";
when "11" & x"d70" => data <= x"00";
when "11" & x"d71" => data <= x"80";
when "11" & x"d72" => data <= x"b9";
when "11" & x"d73" => data <= x"00";
when "11" & x"d74" => data <= x"0f";
when "11" & x"d75" => data <= x"99";
when "11" & x"d76" => data <= x"00";
when "11" & x"d77" => data <= x"81";
when "11" & x"d78" => data <= x"88";
when "11" & x"d79" => data <= x"d0";
when "11" & x"d7a" => data <= x"f1";
when "11" & x"d7b" => data <= x"a9";
when "11" & x"d7c" => data <= x"00";
when "11" & x"d7d" => data <= x"8d";
when "11" & x"d7e" => data <= x"30";
when "11" & x"d7f" => data <= x"fe";
when "11" & x"d80" => data <= x"60";
when "11" & x"d81" => data <= x"8e";
when "11" & x"d82" => data <= x"30";
when "11" & x"d83" => data <= x"fe";
when "11" & x"d84" => data <= x"ad";
when "11" & x"d85" => data <= x"ff";
when "11" & x"d86" => data <= x"bf";
when "11" & x"d87" => data <= x"a8";
when "11" & x"d88" => data <= x"49";
when "11" & x"d89" => data <= x"ff";
when "11" & x"d8a" => data <= x"8d";
when "11" & x"d8b" => data <= x"ff";
when "11" & x"d8c" => data <= x"bf";
when "11" & x"d8d" => data <= x"98";
when "11" & x"d8e" => data <= x"4d";
when "11" & x"d8f" => data <= x"ff";
when "11" & x"d90" => data <= x"bf";
when "11" & x"d91" => data <= x"8c";
when "11" & x"d92" => data <= x"ff";
when "11" & x"d93" => data <= x"bf";
when "11" & x"d94" => data <= x"c9";
when "11" & x"d95" => data <= x"ff";
when "11" & x"d96" => data <= x"d0";
when "11" & x"d97" => data <= x"05";
when "11" & x"d98" => data <= x"ce";
when "11" & x"d99" => data <= x"28";
when "11" & x"d9a" => data <= x"0d";
when "11" & x"d9b" => data <= x"30";
when "11" & x"d9c" => data <= x"03";
when "11" & x"d9d" => data <= x"ca";
when "11" & x"d9e" => data <= x"10";
when "11" & x"d9f" => data <= x"e1";
when "11" & x"da0" => data <= x"ad";
when "11" & x"da1" => data <= x"29";
when "11" & x"da2" => data <= x"0d";
when "11" & x"da3" => data <= x"8d";
when "11" & x"da4" => data <= x"30";
when "11" & x"da5" => data <= x"fe";
when "11" & x"da6" => data <= x"60";
when "11" & x"da7" => data <= x"a2";
when "11" & x"da8" => data <= x"0b";
when "11" & x"da9" => data <= x"bd";
when "11" & x"daa" => data <= x"32";
when "11" & x"dab" => data <= x"be";
when "11" & x"dac" => data <= x"9d";
when "11" & x"dad" => data <= x"70";
when "11" & x"dae" => data <= x"0d";
when "11" & x"daf" => data <= x"ca";
when "11" & x"db0" => data <= x"10";
when "11" & x"db1" => data <= x"f7";
when "11" & x"db2" => data <= x"e8";
when "11" & x"db3" => data <= x"8e";
when "11" & x"db4" => data <= x"05";
when "11" & x"db5" => data <= x"0d";
when "11" & x"db6" => data <= x"8e";
when "11" & x"db7" => data <= x"28";
when "11" & x"db8" => data <= x"0d";
when "11" & x"db9" => data <= x"a9";
when "11" & x"dba" => data <= x"40";
when "11" & x"dbb" => data <= x"8d";
when "11" & x"dbc" => data <= x"27";
when "11" & x"dbd" => data <= x"0d";
when "11" & x"dbe" => data <= x"0a";
when "11" & x"dbf" => data <= x"48";
when "11" & x"dc0" => data <= x"20";
when "11" & x"dc1" => data <= x"1f";
when "11" & x"dc2" => data <= x"a6";
when "11" & x"dc3" => data <= x"68";
when "11" & x"dc4" => data <= x"20";
when "11" & x"dc5" => data <= x"70";
when "11" & x"dc6" => data <= x"b0";
when "11" & x"dc7" => data <= x"a9";
when "11" & x"dc8" => data <= x"00";
when "11" & x"dc9" => data <= x"85";
when "11" & x"dca" => data <= x"a0";
when "11" & x"dcb" => data <= x"a9";
when "11" & x"dcc" => data <= x"20";
when "11" & x"dcd" => data <= x"85";
when "11" & x"dce" => data <= x"a1";
when "11" & x"dcf" => data <= x"60";
when "11" & x"dd0" => data <= x"20";
when "11" & x"dd1" => data <= x"cc";
when "11" & x"dd2" => data <= x"a7";
when "11" & x"dd3" => data <= x"60";
when "11" & x"dd4" => data <= x"20";
when "11" & x"dd5" => data <= x"78";
when "11" & x"dd6" => data <= x"a8";
when "11" & x"dd7" => data <= x"60";
when "11" & x"dd8" => data <= x"a2";
when "11" & x"dd9" => data <= x"0b";
when "11" & x"dda" => data <= x"bd";
when "11" & x"ddb" => data <= x"70";
when "11" & x"ddc" => data <= x"0d";
when "11" & x"ddd" => data <= x"9d";
when "11" & x"dde" => data <= x"60";
when "11" & x"ddf" => data <= x"0d";
when "11" & x"de0" => data <= x"ca";
when "11" & x"de1" => data <= x"10";
when "11" & x"de2" => data <= x"f7";
when "11" & x"de3" => data <= x"a2";
when "11" & x"de4" => data <= x"06";
when "11" & x"de5" => data <= x"bd";
when "11" & x"de6" => data <= x"05";
when "11" & x"de7" => data <= x"0d";
when "11" & x"de8" => data <= x"9d";
when "11" & x"de9" => data <= x"2e";
when "11" & x"dea" => data <= x"0d";
when "11" & x"deb" => data <= x"ca";
when "11" & x"dec" => data <= x"10";
when "11" & x"ded" => data <= x"f7";
when "11" & x"dee" => data <= x"ad";
when "11" & x"def" => data <= x"28";
when "11" & x"df0" => data <= x"0d";
when "11" & x"df1" => data <= x"8d";
when "11" & x"df2" => data <= x"35";
when "11" & x"df3" => data <= x"0d";
when "11" & x"df4" => data <= x"a5";
when "11" & x"df5" => data <= x"a0";
when "11" & x"df6" => data <= x"8d";
when "11" & x"df7" => data <= x"36";
when "11" & x"df8" => data <= x"0d";
when "11" & x"df9" => data <= x"a5";
when "11" & x"dfa" => data <= x"a1";
when "11" & x"dfb" => data <= x"8d";
when "11" & x"dfc" => data <= x"37";
when "11" & x"dfd" => data <= x"0d";
when "11" & x"dfe" => data <= x"ad";
when "11" & x"dff" => data <= x"27";
when "11" & x"e00" => data <= x"0d";
when "11" & x"e01" => data <= x"8d";
when "11" & x"e02" => data <= x"38";
when "11" & x"e03" => data <= x"0d";
when "11" & x"e04" => data <= x"60";
when "11" & x"e05" => data <= x"ad";
when "11" & x"e06" => data <= x"38";
when "11" & x"e07" => data <= x"0d";
when "11" & x"e08" => data <= x"8d";
when "11" & x"e09" => data <= x"27";
when "11" & x"e0a" => data <= x"0d";
when "11" & x"e0b" => data <= x"ad";
when "11" & x"e0c" => data <= x"37";
when "11" & x"e0d" => data <= x"0d";
when "11" & x"e0e" => data <= x"85";
when "11" & x"e0f" => data <= x"a1";
when "11" & x"e10" => data <= x"ad";
when "11" & x"e11" => data <= x"36";
when "11" & x"e12" => data <= x"0d";
when "11" & x"e13" => data <= x"85";
when "11" & x"e14" => data <= x"a0";
when "11" & x"e15" => data <= x"ad";
when "11" & x"e16" => data <= x"35";
when "11" & x"e17" => data <= x"0d";
when "11" & x"e18" => data <= x"8d";
when "11" & x"e19" => data <= x"28";
when "11" & x"e1a" => data <= x"0d";
when "11" & x"e1b" => data <= x"a2";
when "11" & x"e1c" => data <= x"06";
when "11" & x"e1d" => data <= x"bd";
when "11" & x"e1e" => data <= x"2e";
when "11" & x"e1f" => data <= x"0d";
when "11" & x"e20" => data <= x"9d";
when "11" & x"e21" => data <= x"05";
when "11" & x"e22" => data <= x"0d";
when "11" & x"e23" => data <= x"ca";
when "11" & x"e24" => data <= x"10";
when "11" & x"e25" => data <= x"f7";
when "11" & x"e26" => data <= x"a2";
when "11" & x"e27" => data <= x"0b";
when "11" & x"e28" => data <= x"bd";
when "11" & x"e29" => data <= x"60";
when "11" & x"e2a" => data <= x"0d";
when "11" & x"e2b" => data <= x"9d";
when "11" & x"e2c" => data <= x"70";
when "11" & x"e2d" => data <= x"0d";
when "11" & x"e2e" => data <= x"ca";
when "11" & x"e2f" => data <= x"10";
when "11" & x"e30" => data <= x"f7";
when "11" & x"e31" => data <= x"60";
when "11" & x"e32" => data <= x"49";
when "11" & x"e33" => data <= x"4e";
when "11" & x"e34" => data <= x"4f";
when "11" & x"e35" => data <= x"55";
when "11" & x"e36" => data <= x"54";
when "11" & x"e37" => data <= x"4d";
when "11" & x"e38" => data <= x"45";
when "11" & x"e39" => data <= x"4d";
when "11" & x"e3a" => data <= x"20";
when "11" & x"e3b" => data <= x"20";
when "11" & x"e3c" => data <= x"20";
when "11" & x"e3d" => data <= x"20";
when "11" & x"e3e" => data <= x"48";
when "11" & x"e3f" => data <= x"a5";
when "11" & x"e40" => data <= x"cf";
when "11" & x"e41" => data <= x"8d";
when "11" & x"e42" => data <= x"20";
when "11" & x"e43" => data <= x"0d";
when "11" & x"e44" => data <= x"68";
when "11" & x"e45" => data <= x"60";
when "11" & x"e46" => data <= x"a0";
when "11" & x"e47" => data <= x"00";
when "11" & x"e48" => data <= x"b1";
when "11" & x"e49" => data <= x"b0";
when "11" & x"e4a" => data <= x"30";
when "11" & x"e4b" => data <= x"07";
when "11" & x"e4c" => data <= x"29";
when "11" & x"e4d" => data <= x"03";
when "11" & x"e4e" => data <= x"85";
when "11" & x"e4f" => data <= x"cf";
when "11" & x"e50" => data <= x"8d";
when "11" & x"e51" => data <= x"20";
when "11" & x"e52" => data <= x"0d";
when "11" & x"e53" => data <= x"a0";
when "11" & x"e54" => data <= x"05";
when "11" & x"e55" => data <= x"b1";
when "11" & x"e56" => data <= x"b0";
when "11" & x"e57" => data <= x"18";
when "11" & x"e58" => data <= x"69";
when "11" & x"e59" => data <= x"07";
when "11" & x"e5a" => data <= x"85";
when "11" & x"e5b" => data <= x"be";
when "11" & x"e5c" => data <= x"20";
when "11" & x"e5d" => data <= x"6a";
when "11" & x"e5e" => data <= x"be";
when "11" & x"e5f" => data <= x"a4";
when "11" & x"e60" => data <= x"be";
when "11" & x"e61" => data <= x"b0";
when "11" & x"e62" => data <= x"02";
when "11" & x"e63" => data <= x"a9";
when "11" & x"e64" => data <= x"00";
when "11" & x"e65" => data <= x"91";
when "11" & x"e66" => data <= x"b0";
when "11" & x"e67" => data <= x"a9";
when "11" & x"e68" => data <= x"00";
when "11" & x"e69" => data <= x"60";
when "11" & x"e6a" => data <= x"c8";
when "11" & x"e6b" => data <= x"b1";
when "11" & x"e6c" => data <= x"b0";
when "11" & x"e6d" => data <= x"aa";
when "11" & x"e6e" => data <= x"29";
when "11" & x"e6f" => data <= x"3f";
when "11" & x"e70" => data <= x"85";
when "11" & x"e71" => data <= x"bf";
when "11" & x"e72" => data <= x"c9";
when "11" & x"e73" => data <= x"3a";
when "11" & x"e74" => data <= x"d0";
when "11" & x"e75" => data <= x"2f";
when "11" & x"e76" => data <= x"a5";
when "11" & x"e77" => data <= x"be";
when "11" & x"e78" => data <= x"c9";
when "11" & x"e79" => data <= x"09";
when "11" & x"e7a" => data <= x"d0";
when "11" & x"e7b" => data <= x"13";
when "11" & x"e7c" => data <= x"c8";
when "11" & x"e7d" => data <= x"b1";
when "11" & x"e7e" => data <= x"b0";
when "11" & x"e7f" => data <= x"c9";
when "11" & x"e80" => data <= x"23";
when "11" & x"e81" => data <= x"d0";
when "11" & x"e82" => data <= x"0c";
when "11" & x"e83" => data <= x"c8";
when "11" & x"e84" => data <= x"b1";
when "11" & x"e85" => data <= x"b0";
when "11" & x"e86" => data <= x"29";
when "11" & x"e87" => data <= x"20";
when "11" & x"e88" => data <= x"f0";
when "11" & x"e89" => data <= x"02";
when "11" & x"e8a" => data <= x"a9";
when "11" & x"e8b" => data <= x"02";
when "11" & x"e8c" => data <= x"8d";
when "11" & x"e8d" => data <= x"20";
when "11" & x"e8e" => data <= x"0d";
when "11" & x"e8f" => data <= x"18";
when "11" & x"e90" => data <= x"60";
when "11" & x"e91" => data <= x"a9";
when "11" & x"e92" => data <= x"1e";
when "11" & x"e93" => data <= x"38";
when "11" & x"e94" => data <= x"60";
when "11" & x"e95" => data <= x"a9";
when "11" & x"e96" => data <= x"10";
when "11" & x"e97" => data <= x"38";
when "11" & x"e98" => data <= x"60";
when "11" & x"e99" => data <= x"a9";
when "11" & x"e9a" => data <= x"12";
when "11" & x"e9b" => data <= x"38";
when "11" & x"e9c" => data <= x"60";
when "11" & x"e9d" => data <= x"a9";
when "11" & x"e9e" => data <= x"ff";
when "11" & x"e9f" => data <= x"38";
when "11" & x"ea0" => data <= x"60";
when "11" & x"ea1" => data <= x"a9";
when "11" & x"ea2" => data <= x"1e";
when "11" & x"ea3" => data <= x"38";
when "11" & x"ea4" => data <= x"60";
when "11" & x"ea5" => data <= x"a5";
when "11" & x"ea6" => data <= x"cf";
when "11" & x"ea7" => data <= x"6a";
when "11" & x"ea8" => data <= x"8a";
when "11" & x"ea9" => data <= x"90";
when "11" & x"eaa" => data <= x"02";
when "11" & x"eab" => data <= x"49";
when "11" & x"eac" => data <= x"c0";
when "11" & x"ead" => data <= x"2a";
when "11" & x"eae" => data <= x"90";
when "11" & x"eaf" => data <= x"0c";
when "11" & x"eb0" => data <= x"2a";
when "11" & x"eb1" => data <= x"b0";
when "11" & x"eb2" => data <= x"de";
when "11" & x"eb3" => data <= x"ad";
when "11" & x"eb4" => data <= x"20";
when "11" & x"eb5" => data <= x"0d";
when "11" & x"eb6" => data <= x"29";
when "11" & x"eb7" => data <= x"02";
when "11" & x"eb8" => data <= x"09";
when "11" & x"eb9" => data <= x"01";
when "11" & x"eba" => data <= x"d0";
when "11" & x"ebb" => data <= x"08";
when "11" & x"ebc" => data <= x"2a";
when "11" & x"ebd" => data <= x"90";
when "11" & x"ebe" => data <= x"d6";
when "11" & x"ebf" => data <= x"ad";
when "11" & x"ec0" => data <= x"20";
when "11" & x"ec1" => data <= x"0d";
when "11" & x"ec2" => data <= x"29";
when "11" & x"ec3" => data <= x"02";
when "11" & x"ec4" => data <= x"8d";
when "11" & x"ec5" => data <= x"20";
when "11" & x"ec6" => data <= x"0d";
when "11" & x"ec7" => data <= x"aa";
when "11" & x"ec8" => data <= x"86";
when "11" & x"ec9" => data <= x"c0";
when "11" & x"eca" => data <= x"bd";
when "11" & x"ecb" => data <= x"10";
when "11" & x"ecc" => data <= x"0d";
when "11" & x"ecd" => data <= x"30";
when "11" & x"ece" => data <= x"c6";
when "11" & x"ecf" => data <= x"a5";
when "11" & x"ed0" => data <= x"bf";
when "11" & x"ed1" => data <= x"c9";
when "11" & x"ed2" => data <= x"13";
when "11" & x"ed3" => data <= x"f0";
when "11" & x"ed4" => data <= x"0b";
when "11" & x"ed5" => data <= x"c9";
when "11" & x"ed6" => data <= x"0b";
when "11" & x"ed7" => data <= x"d0";
when "11" & x"ed8" => data <= x"b6";
when "11" & x"ed9" => data <= x"bd";
when "11" & x"eda" => data <= x"1c";
when "11" & x"edb" => data <= x"0d";
when "11" & x"edc" => data <= x"c9";
when "11" & x"edd" => data <= x"54";
when "11" & x"ede" => data <= x"d0";
when "11" & x"edf" => data <= x"b9";
when "11" & x"ee0" => data <= x"a5";
when "11" & x"ee1" => data <= x"be";
when "11" & x"ee2" => data <= x"c9";
when "11" & x"ee3" => data <= x"0a";
when "11" & x"ee4" => data <= x"d0";
when "11" & x"ee5" => data <= x"b7";
when "11" & x"ee6" => data <= x"20";
when "11" & x"ee7" => data <= x"1f";
when "11" & x"ee8" => data <= x"a6";
when "11" & x"ee9" => data <= x"a9";
when "11" & x"eea" => data <= x"00";
when "11" & x"eeb" => data <= x"85";
when "11" & x"eec" => data <= x"c5";
when "11" & x"eed" => data <= x"c8";
when "11" & x"eee" => data <= x"b1";
when "11" & x"eef" => data <= x"b0";
when "11" & x"ef0" => data <= x"c9";
when "11" & x"ef1" => data <= x"50";
when "11" & x"ef2" => data <= x"b0";
when "11" & x"ef3" => data <= x"9d";
when "11" & x"ef4" => data <= x"0a";
when "11" & x"ef5" => data <= x"85";
when "11" & x"ef6" => data <= x"c4";
when "11" & x"ef7" => data <= x"0a";
when "11" & x"ef8" => data <= x"26";
when "11" & x"ef9" => data <= x"c5";
when "11" & x"efa" => data <= x"0a";
when "11" & x"efb" => data <= x"26";
when "11" & x"efc" => data <= x"c5";
when "11" & x"efd" => data <= x"65";
when "11" & x"efe" => data <= x"c4";
when "11" & x"eff" => data <= x"85";
when "11" & x"f00" => data <= x"c4";
when "11" & x"f01" => data <= x"90";
when "11" & x"f02" => data <= x"02";
when "11" & x"f03" => data <= x"e6";
when "11" & x"f04" => data <= x"c5";
when "11" & x"f05" => data <= x"c8";
when "11" & x"f06" => data <= x"b1";
when "11" & x"f07" => data <= x"b0";
when "11" & x"f08" => data <= x"c9";
when "11" & x"f09" => data <= x"0a";
when "11" & x"f0a" => data <= x"b0";
when "11" & x"f0b" => data <= x"95";
when "11" & x"f0c" => data <= x"18";
when "11" & x"f0d" => data <= x"65";
when "11" & x"f0e" => data <= x"c4";
when "11" & x"f0f" => data <= x"85";
when "11" & x"f10" => data <= x"c4";
when "11" & x"f11" => data <= x"90";
when "11" & x"f12" => data <= x"02";
when "11" & x"f13" => data <= x"e6";
when "11" & x"f14" => data <= x"c5";
when "11" & x"f15" => data <= x"18";
when "11" & x"f16" => data <= x"a9";
when "11" & x"f17" => data <= x"00";
when "11" & x"f18" => data <= x"8d";
when "11" & x"f19" => data <= x"28";
when "11" & x"f1a" => data <= x"0d";
when "11" & x"f1b" => data <= x"a5";
when "11" & x"f1c" => data <= x"c5";
when "11" & x"f1d" => data <= x"6a";
when "11" & x"f1e" => data <= x"48";
when "11" & x"f1f" => data <= x"a5";
when "11" & x"f20" => data <= x"c4";
when "11" & x"f21" => data <= x"6a";
when "11" & x"f22" => data <= x"48";
when "11" & x"f23" => data <= x"90";
when "11" & x"f24" => data <= x"03";
when "11" & x"f25" => data <= x"6e";
when "11" & x"f26" => data <= x"28";
when "11" & x"f27" => data <= x"0d";
when "11" & x"f28" => data <= x"c8";
when "11" & x"f29" => data <= x"b1";
when "11" & x"f2a" => data <= x"b0";
when "11" & x"f2b" => data <= x"29";
when "11" & x"f2c" => data <= x"1f";
when "11" & x"f2d" => data <= x"8d";
when "11" & x"f2e" => data <= x"27";
when "11" & x"f2f" => data <= x"0d";
when "11" & x"f30" => data <= x"f0";
when "11" & x"f31" => data <= x"55";
when "11" & x"f32" => data <= x"18";
when "11" & x"f33" => data <= x"65";
when "11" & x"f34" => data <= x"c4";
when "11" & x"f35" => data <= x"aa";
when "11" & x"f36" => data <= x"a9";
when "11" & x"f37" => data <= x"00";
when "11" & x"f38" => data <= x"65";
when "11" & x"f39" => data <= x"c5";
when "11" & x"f3a" => data <= x"c9";
when "11" & x"f3b" => data <= x"03";
when "11" & x"f3c" => data <= x"90";
when "11" & x"f3d" => data <= x"06";
when "11" & x"f3e" => data <= x"d0";
when "11" & x"f3f" => data <= x"51";
when "11" & x"f40" => data <= x"e0";
when "11" & x"f41" => data <= x"21";
when "11" & x"f42" => data <= x"b0";
when "11" & x"f43" => data <= x"4d";
when "11" & x"f44" => data <= x"a6";
when "11" & x"f45" => data <= x"c0";
when "11" & x"f46" => data <= x"bd";
when "11" & x"f47" => data <= x"10";
when "11" & x"f48" => data <= x"0d";
when "11" & x"f49" => data <= x"6a";
when "11" & x"f4a" => data <= x"bd";
when "11" & x"f4b" => data <= x"0c";
when "11" & x"f4c" => data <= x"0d";
when "11" & x"f4d" => data <= x"20";
when "11" & x"f4e" => data <= x"26";
when "11" & x"f4f" => data <= x"ae";
when "11" & x"f50" => data <= x"18";
when "11" & x"f51" => data <= x"68";
when "11" & x"f52" => data <= x"6d";
when "11" & x"f53" => data <= x"23";
when "11" & x"f54" => data <= x"0d";
when "11" & x"f55" => data <= x"8d";
when "11" & x"f56" => data <= x"23";
when "11" & x"f57" => data <= x"0d";
when "11" & x"f58" => data <= x"68";
when "11" & x"f59" => data <= x"6d";
when "11" & x"f5a" => data <= x"24";
when "11" & x"f5b" => data <= x"0d";
when "11" & x"f5c" => data <= x"8d";
when "11" & x"f5d" => data <= x"24";
when "11" & x"f5e" => data <= x"0d";
when "11" & x"f5f" => data <= x"ad";
when "11" & x"f60" => data <= x"25";
when "11" & x"f61" => data <= x"0d";
when "11" & x"f62" => data <= x"69";
when "11" & x"f63" => data <= x"00";
when "11" & x"f64" => data <= x"8d";
when "11" & x"f65" => data <= x"25";
when "11" & x"f66" => data <= x"0d";
when "11" & x"f67" => data <= x"ad";
when "11" & x"f68" => data <= x"26";
when "11" & x"f69" => data <= x"0d";
when "11" & x"f6a" => data <= x"69";
when "11" & x"f6b" => data <= x"00";
when "11" & x"f6c" => data <= x"8d";
when "11" & x"f6d" => data <= x"26";
when "11" & x"f6e" => data <= x"0d";
when "11" & x"f6f" => data <= x"a0";
when "11" & x"f70" => data <= x"00";
when "11" & x"f71" => data <= x"8c";
when "11" & x"f72" => data <= x"29";
when "11" & x"f73" => data <= x"0d";
when "11" & x"f74" => data <= x"c8";
when "11" & x"f75" => data <= x"b1";
when "11" & x"f76" => data <= x"b0";
when "11" & x"f77" => data <= x"85";
when "11" & x"f78" => data <= x"a0";
when "11" & x"f79" => data <= x"c8";
when "11" & x"f7a" => data <= x"b1";
when "11" & x"f7b" => data <= x"b0";
when "11" & x"f7c" => data <= x"85";
when "11" & x"f7d" => data <= x"a1";
when "11" & x"f7e" => data <= x"a5";
when "11" & x"f7f" => data <= x"bf";
when "11" & x"f80" => data <= x"c9";
when "11" & x"f81" => data <= x"13";
when "11" & x"f82" => data <= x"f0";
when "11" & x"f83" => data <= x"05";
when "11" & x"f84" => data <= x"20";
when "11" & x"f85" => data <= x"9f";
when "11" & x"f86" => data <= x"af";
when "11" & x"f87" => data <= x"18";
when "11" & x"f88" => data <= x"60";
when "11" & x"f89" => data <= x"20";
when "11" & x"f8a" => data <= x"cc";
when "11" & x"f8b" => data <= x"a7";
when "11" & x"f8c" => data <= x"20";
when "11" & x"f8d" => data <= x"cd";
when "11" & x"f8e" => data <= x"a0";
when "11" & x"f8f" => data <= x"18";
when "11" & x"f90" => data <= x"60";
when "11" & x"f91" => data <= x"a9";
when "11" & x"f92" => data <= x"1e";
when "11" & x"f93" => data <= x"38";
when "11" & x"f94" => data <= x"60";
when "11" & x"f95" => data <= x"44";
when "11" & x"f96" => data <= x"55";
when "11" & x"f97" => data <= x"49";
when "11" & x"f98" => data <= x"4b";
when "11" & x"f99" => data <= x"20";
when "11" & x"f9a" => data <= x"44";
when "11" & x"f9b" => data <= x"55";
when "11" & x"f9c" => data <= x"49";
when "11" & x"f9d" => data <= x"4b";
when "11" & x"f9e" => data <= x"20";
when "11" & x"f9f" => data <= x"44";
when "11" & x"fa0" => data <= x"55";
when "11" & x"fa1" => data <= x"49";
when "11" & x"fa2" => data <= x"4b";
when "11" & x"fa3" => data <= x"20";
when "11" & x"fa4" => data <= x"44";
when "11" & x"fa5" => data <= x"55";
when "11" & x"fa6" => data <= x"49";
when "11" & x"fa7" => data <= x"4b";
when "11" & x"fa8" => data <= x"20";
when "11" & x"fa9" => data <= x"44";
when "11" & x"faa" => data <= x"55";
when "11" & x"fab" => data <= x"49";
when "11" & x"fac" => data <= x"4b";
when "11" & x"fad" => data <= x"20";
when "11" & x"fae" => data <= x"44";
when "11" & x"faf" => data <= x"55";
when "11" & x"fb0" => data <= x"49";
when "11" & x"fb1" => data <= x"4b";
when "11" & x"fb2" => data <= x"20";
when "11" & x"fb3" => data <= x"44";
when "11" & x"fb4" => data <= x"55";
when "11" & x"fb5" => data <= x"49";
when "11" & x"fb6" => data <= x"4b";
when "11" & x"fb7" => data <= x"20";
when "11" & x"fb8" => data <= x"44";
when "11" & x"fb9" => data <= x"55";
when "11" & x"fba" => data <= x"49";
when "11" & x"fbb" => data <= x"4b";
when "11" & x"fbc" => data <= x"20";
when "11" & x"fbd" => data <= x"44";
when "11" & x"fbe" => data <= x"55";
when "11" & x"fbf" => data <= x"49";
when "11" & x"fc0" => data <= x"4b";
when "11" & x"fc1" => data <= x"20";
when "11" & x"fc2" => data <= x"44";
when "11" & x"fc3" => data <= x"55";
when "11" & x"fc4" => data <= x"49";
when "11" & x"fc5" => data <= x"4b";
when "11" & x"fc6" => data <= x"20";
when "11" & x"fc7" => data <= x"44";
when "11" & x"fc8" => data <= x"55";
when "11" & x"fc9" => data <= x"49";
when "11" & x"fca" => data <= x"4b";
when "11" & x"fcb" => data <= x"20";
when "11" & x"fcc" => data <= x"44";
when "11" & x"fcd" => data <= x"55";
when "11" & x"fce" => data <= x"49";
when "11" & x"fcf" => data <= x"4b";
when "11" & x"fd0" => data <= x"20";
when "11" & x"fd1" => data <= x"44";
when "11" & x"fd2" => data <= x"55";
when "11" & x"fd3" => data <= x"49";
when "11" & x"fd4" => data <= x"4b";
when "11" & x"fd5" => data <= x"20";
when "11" & x"fd6" => data <= x"44";
when "11" & x"fd7" => data <= x"55";
when "11" & x"fd8" => data <= x"49";
when "11" & x"fd9" => data <= x"4b";
when "11" & x"fda" => data <= x"20";
when "11" & x"fdb" => data <= x"44";
when "11" & x"fdc" => data <= x"55";
when "11" & x"fdd" => data <= x"49";
when "11" & x"fde" => data <= x"4b";
when "11" & x"fdf" => data <= x"20";
when "11" & x"fe0" => data <= x"44";
when "11" & x"fe1" => data <= x"55";
when "11" & x"fe2" => data <= x"49";
when "11" & x"fe3" => data <= x"4b";
when "11" & x"fe4" => data <= x"20";
when "11" & x"fe5" => data <= x"44";
when "11" & x"fe6" => data <= x"55";
when "11" & x"fe7" => data <= x"49";
when "11" & x"fe8" => data <= x"4b";
when "11" & x"fe9" => data <= x"20";
when "11" & x"fea" => data <= x"44";
when "11" & x"feb" => data <= x"55";
when "11" & x"fec" => data <= x"49";
when "11" & x"fed" => data <= x"4b";
when "11" & x"fee" => data <= x"20";
when "11" & x"fef" => data <= x"44";
when "11" & x"ff0" => data <= x"55";
when "11" & x"ff1" => data <= x"49";
when "11" & x"ff2" => data <= x"4b";
when "11" & x"ff3" => data <= x"20";
when "11" & x"ff4" => data <= x"44";
when "11" & x"ff5" => data <= x"55";
when "11" & x"ff6" => data <= x"49";
when "11" & x"ff7" => data <= x"4b";
when "11" & x"ff8" => data <= x"20";
when "11" & x"ff9" => data <= x"44";
when "11" & x"ffa" => data <= x"55";
when "11" & x"ffb" => data <= x"49";
when "11" & x"ffc" => data <= x"4b";
when "11" & x"ffd" => data <= x"20";
when "11" & x"ffe" => data <= x"44";
when "11" & x"fff" => data <= x"00";
when others => data <= (others => '0');
end case;
end process;
end RTL;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_reset.vhd
--
-- Description:
--
-- This VHDL file implements the reset module for the AXI Master lite.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_reset.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/26/2011$
--
-- History:
--
-- DET 1/26/2011 Initial
-- ~~~~~~
-- - Adapted from AXI Master Lite reset module
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_master_burst_reset is
port (
-----------------------------------------------------------------------
-- Clock Input
-----------------------------------------------------------------------
axi_aclk : in std_logic ;
-----------------------------------------------------------------------
-- Reset Input (active low)
-----------------------------------------------------------------------
axi_aresetn : in std_logic ;
-----------------------------------------------------------------------
-- IPIC Reset Input
-----------------------------------------------------------------------
ip2bus_mst_reset : In std_logic ;
-----------------------------------------------------------------------
-- Command Status Module Reset Output
-----------------------------------------------------------------------
rst2cmd_reset_out : out std_logic ;
-----------------------------------------------------------------------
-- Read Write controller Module Reset Output
-----------------------------------------------------------------------
rst2rdwr_reset_out : out std_logic ;
-----------------------------------------------------------------------
-- LocalLink Modules Reset Output
-----------------------------------------------------------------------
rst2llink_reset_out : out std_logic
);
end entity axi_master_burst_reset;
architecture implementation of axi_master_burst_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sig_axi_por_reg1 : std_logic := '0';
signal sig_axi_por_reg2 : std_logic := '0';
signal sig_axi_por_reg3 : std_logic := '0';
signal sig_axi_por_reg4 : std_logic := '0';
signal sig_axi_por_reg5 : std_logic := '0';
signal sig_axi_por_reg6 : std_logic := '0';
signal sig_axi_por_reg7 : std_logic := '0';
signal sig_axi_por_reg8 : std_logic := '0';
signal sig_axi_por2rst : std_logic := '0';
signal sig_axi_por2rst_out : std_logic := '0';
signal sig_axi_reset : std_logic := '0';
signal sig_ipic_reset : std_logic := '0';
signal sig_combined_reset : std_logic := '0';
signal sig_cmd_reset_reg : std_logic := '0';
signal sig_rdwr_reset_reg : std_logic := '0';
signal sig_llink_reset_reg : std_logic := '0';
-------------------------------------------------------------------------------
-- Register duplication attribute assignments to control fanout
-- on reset signals
-------------------------------------------------------------------------------
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_cmd_reset_reg : signal is "TRUE";
Attribute KEEP of sig_rdwr_reset_reg : signal is "TRUE";
Attribute KEEP of sig_llink_reset_reg : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_cmd_reset_reg : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_rdwr_reset_reg : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_llink_reset_reg : signal is "no";
begin --(architecture implementation)
-- Assign the output ports
rst2cmd_reset_out <= sig_cmd_reset_reg ;
rst2rdwr_reset_out <= sig_rdwr_reset_reg ;
rst2llink_reset_out <= sig_llink_reset_reg;
-- Generate an active high combined reset from the
-- axi reset input and the IPIC reset input
sig_axi_reset <= not(axi_aresetn);
sig_ipic_reset <= ip2bus_mst_reset;
sig_combined_reset <= sig_axi_reset or sig_ipic_reset;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_RST_REG
--
-- Process Description:
-- Implements the register for the command/status module
-- reset output.
--
-------------------------------------------------------------
IMP_CMD_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst_out = '1') then
sig_cmd_reset_reg <= '1';
else
sig_cmd_reset_reg <= sig_combined_reset;
end if;
end if;
end process IMP_CMD_RST_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RDWR_RST_REG
--
-- Process Description:
-- Implements the register for the read/write controller
-- module reset output.
--
-------------------------------------------------------------
IMP_RDWR_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst_out = '1') then
sig_rdwr_reset_reg <= '1';
else
sig_rdwr_reset_reg <= sig_combined_reset;
end if;
end if;
end process IMP_RDWR_RST_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LLINK_RST_REG
--
-- Process Description:
-- Implements the register for the LocalLink Modules
-- reset output.
--
-------------------------------------------------------------
IMP_LLINK_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst_out = '1') then
sig_llink_reset_reg <= '1';
else
sig_llink_reset_reg <= sig_combined_reset;
end if;
end if;
end process IMP_LLINK_RST_REG;
---------------------------------------------------------------
-- Start Power On Reset (POR) Logic
---------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: AXI_POR_REG
--
-- Process Description:
-- This process generates an 8-clock wide pulse that
-- only occurs immediately after FPGA initialization. This
-- pulse is used to initialize reset logic synchronous to
-- the Main axi_aclk Clock until the Bus Reset occurs.
--
-------------------------------------------------------------
AXI_POR_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
sig_axi_por_reg1 <= '1';
sig_axi_por_reg2 <= sig_axi_por_reg1;
sig_axi_por_reg3 <= sig_axi_por_reg2;
sig_axi_por_reg4 <= sig_axi_por_reg3;
sig_axi_por_reg5 <= sig_axi_por_reg4;
sig_axi_por_reg6 <= sig_axi_por_reg5;
sig_axi_por_reg7 <= sig_axi_por_reg6;
sig_axi_por_reg8 <= sig_axi_por_reg7;
sig_axi_por2rst_out <= sig_axi_por2rst ;
end if;
end process AXI_POR_REG;
sig_axi_por2rst <= not(sig_axi_por_reg1 and
sig_axi_por_reg2 and
sig_axi_por_reg3 and
sig_axi_por_reg4 and
sig_axi_por_reg5 and
sig_axi_por_reg6 and
sig_axi_por_reg7 and
sig_axi_por_reg8 );
---------------------------------------------------------------
-- End of Power On Reset (POR) Logic
---------------------------------------------------------------
end implementation;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2265.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02265ent IS
END c07s02b06x00p11n01i02265ent;
ARCHITECTURE c07s02b06x00p11n01i02265arch OF c07s02b06x00p11n01i02265ent IS
BEGIN
TESTING: PROCESS
variable V1,V2,V3 : Integer ;
variable A : Integer := 10 ;
variable B : Integer := 5 ;
BEGIN
V1 := -(A/B) ;
V2 := A/(-B) ;
assert NOT(V1 = V2)
report "***PASSED TEST: c07s02b06x00p11n01i02265"
severity NOTE;
assert (V1 = V2)
report "***FAILED TEST: c07s02b06x00p11n01i02265 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02265arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2265.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02265ent IS
END c07s02b06x00p11n01i02265ent;
ARCHITECTURE c07s02b06x00p11n01i02265arch OF c07s02b06x00p11n01i02265ent IS
BEGIN
TESTING: PROCESS
variable V1,V2,V3 : Integer ;
variable A : Integer := 10 ;
variable B : Integer := 5 ;
BEGIN
V1 := -(A/B) ;
V2 := A/(-B) ;
assert NOT(V1 = V2)
report "***PASSED TEST: c07s02b06x00p11n01i02265"
severity NOTE;
assert (V1 = V2)
report "***FAILED TEST: c07s02b06x00p11n01i02265 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02265arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2265.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p11n01i02265ent IS
END c07s02b06x00p11n01i02265ent;
ARCHITECTURE c07s02b06x00p11n01i02265arch OF c07s02b06x00p11n01i02265ent IS
BEGIN
TESTING: PROCESS
variable V1,V2,V3 : Integer ;
variable A : Integer := 10 ;
variable B : Integer := 5 ;
BEGIN
V1 := -(A/B) ;
V2 := A/(-B) ;
assert NOT(V1 = V2)
report "***PASSED TEST: c07s02b06x00p11n01i02265"
severity NOTE;
assert (V1 = V2)
report "***FAILED TEST: c07s02b06x00p11n01i02265 - Integer division satisfies the following identity: (-A)/B = -(A/B) = A/(-B)."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p11n01i02265arch;
|
--======================================================================
-- sim.vhd :: SOC simulation testbench
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity TEST_TOP is
end TEST_TOP;
architecture BEHAVIORAL of TEST_TOP is
--================================================================
-- Signal and component definition section
--================================================================
-- Output Port A
signal PORTA : std_logic_vector(7 downto 0);
-- UART
signal UART_RXD : std_logic; -- receive data
signal UART_TXD : std_logic; -- transmit data
-- reset and clock
signal RESET : std_logic; -- system reset
signal FCLK : std_logic; -- fast clock
component SOC
port (
-- Output Port A
PORTA : out std_logic_vector(7 downto 0);
-- UART
UART_RXD : in std_logic; -- receive data
UART_TXD : out std_logic; -- transmit data
-- reset and clock
SYSRESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end component;
--================================================================
-- End of types, component, and signal definition section
--================================================================
begin
MAKE_FCLK:
process(FCLK)
begin
if (FCLK = '1') then
FCLK <= '0' after 1 ns;
else
FCLK <= '1' after 1 ns;
end if;
end process;
MAKE_RESET:
process
begin
-- System Reset (active low)
RESET <= '0' after 0 ns, '1' after 10 ns;
wait;
end process;
UART_RXD <= '0';
--============================================
-- Instantiate the SOC
--============================================
MYSOC:
SOC port map (
PORTA => PORTA,
UART_RXD => UART_RXD,
UART_TXD => UART_TXD,
SYSRESET => RESET,
FCLK => FCLK
);
end BEHAVIORAL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/21/2013 02:38:36 AM
-- Design Name:
-- Module Name: ten_gig_eth_packet_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY ten_gig_eth_packet_gen IS
PORT (
RESET : IN std_logic;
MEM_CLK : IN std_logic;
MEM_WE : IN std_logic; -- memory write enable
MEM_ADDR : IN std_logic_vector(31 DOWNTO 0);
MEM_D : IN std_logic_vector(31 DOWNTO 0); -- memory data
--
TX_AXIS_ACLK : IN std_logic;
TX_START : IN std_logic; -- rising edge aligned 1-period pulse to start TX
TX_BYTES : IN std_logic_vector(15 DOWNTO 0); -- number of bytes to send
TX_AXIS_TDATA : OUT std_logic_vector(63 DOWNTO 0);
TX_AXIS_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
TX_AXIS_TVALID : OUT std_logic;
TX_AXIS_TLAST : OUT std_logic;
TX_AXIS_TREADY : IN std_logic
);
END ten_gig_eth_packet_gen;
ARCHITECTURE Behavioral OF ten_gig_eth_packet_gen IS
COMPONENT ten_gig_eth_packet_ram
PORT (
CLKA : IN std_logic;
WEA : IN std_logic_vector(0 DOWNTO 0);
ADDRA : IN std_logic_vector(11 DOWNTO 0);
DINA : IN std_logic_vector(31 DOWNTO 0);
CLKB : IN std_logic;
ADDRB : IN std_logic_vector(10 DOWNTO 0);
DOUTB : OUT std_logic_vector(63 DOWNTO 0)
);
END COMPONENT;
SIGNAL mem_clk_i : std_logic;
SIGNAL tx_clk_i : std_logic;
TYPE pktState_type IS (S0, S1, S2, S3, S4);
SIGNAL pktState : pktState_type;
SIGNAL mem_wea : std_logic_vector(0 DOWNTO 0);
SIGNAL addrb_i : std_logic_vector(10 DOWNTO 0);
SIGNAL doutb_i : std_logic_vector(63 DOWNTO 0);
SIGNAL addrCtr : unsigned(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL bytesLeft : unsigned(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL bytesLeft_reg : unsigned(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL pktCtr : unsigned(47 DOWNTO 0) := (OTHERS => '0');
BEGIN
mem_clk_i <= MEM_CLK;
tx_clk_i <= TX_AXIS_ACLK;
mem_wea <= (OTHERS => MEM_WE);
tge_packet_ram_inst : ten_gig_eth_packet_ram
PORT MAP (
CLKA => mem_clk_i,
WEA => mem_wea,
ADDRA => MEM_ADDR(11 DOWNTO 0),
DINA => MEM_D,
CLKB => tx_clk_i,
ADDRB => addrb_i,
DOUTB => doutb_i
);
PROCESS (tx_clk_i) IS
BEGIN
IF falling_edge(tx_clk_i) THEN
TX_AXIS_TDATA <= doutb_i;
IF addrCtr = 5 THEN
-- little endian of pktCtr seen by the host
TX_AXIS_TDATA <= std_logic_vector(pktCtr) & doutb_i(15 DOWNTO 0);
-- convert to big endian
--TX_AXIS_TDATA <= std_logic_vector(pktCtr(7 DOWNTO 0))
-- & std_logic_vector(pktCtr(15 DOWNTO 8))
-- & std_logic_vector(pktCtr(23 DOWNTO 16))
-- & std_logic_vector(pktCtr(31 DOWNTO 24))
-- & std_logic_vector(pktCtr(39 DOWNTO 32))
-- & std_logic_vector(pktCtr(47 DOWNTO 40))
-- & doutb_i(15 DOWNTO 0);
END IF;
END IF;
END PROCESS;
pkt_sm: PROCESS (tx_clk_i, RESET) IS
BEGIN
IF RESET = '1' THEN
pktState <= S0;
pktCtr <= (OTHERS => '0');
addrCtr <= (OTHERS => '0');
TX_AXIS_TVALID <= '0';
TX_AXIS_TLAST <= '0';
ELSIF falling_edge(tx_clk_i) THEN
TX_AXIS_TVALID <= '0';
TX_AXIS_TLAST <= '0';
CASE pktState IS
WHEN S0 =>
IF TX_START = '1' THEN
addrCtr <= (OTHERS => '0');
bytesLeft <= unsigned(TX_BYTES);
-- minimum packet length requirement
IF unsigned(TX_BYTES) < 14 THEN
pktState <= S0;
ELSE
pktState <= S1;
END IF;
END IF;
WHEN S1 =>
pktState <= S1;
TX_AXIS_TVALID <= '1';
IF TX_AXIS_TREADY = '1' THEN
addrCtr <= addrCtr + 1;
bytesLeft_reg <= bytesLeft;
bytesLeft <= bytesLeft - 8;
IF bytesLeft <= 8 THEN
pktState <= S2;
TX_AXIS_TLAST <= '1';
END IF;
END IF;
WHEN S2 =>
pktState <= S0;
pktCtr <= pktCtr + 1;
WHEN OTHERS =>
pktState <= S0;
END CASE;
END IF;
END PROCESS pkt_sm;
addrb_i <= std_logic_vector(addrCtr(10 DOWNTO 0));
WITH bytesLeft_reg SELECT
TX_AXIS_TKEEP <=
(OTHERS => '0') WHEN to_unsigned(0,bytesLeft_reg'length),
"00000001" WHEN to_unsigned(1,bytesLeft_reg'length),
"00000011" WHEN to_unsigned(2,bytesLeft_reg'length),
"00000111" WHEN to_unsigned(3,bytesLeft_reg'length),
"00001111" WHEN to_unsigned(4,bytesLeft_reg'length),
"00011111" WHEN to_unsigned(5,bytesLeft_reg'length),
"00111111" WHEN to_unsigned(6,bytesLeft_reg'length),
"01111111" WHEN to_unsigned(7,bytesLeft_reg'length),
(OTHERS => '1') WHEN OTHERS;
END Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/21/2013 02:38:36 AM
-- Design Name:
-- Module Name: ten_gig_eth_packet_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY ten_gig_eth_packet_gen IS
PORT (
RESET : IN std_logic;
MEM_CLK : IN std_logic;
MEM_WE : IN std_logic; -- memory write enable
MEM_ADDR : IN std_logic_vector(31 DOWNTO 0);
MEM_D : IN std_logic_vector(31 DOWNTO 0); -- memory data
--
TX_AXIS_ACLK : IN std_logic;
TX_START : IN std_logic; -- rising edge aligned 1-period pulse to start TX
TX_BYTES : IN std_logic_vector(15 DOWNTO 0); -- number of bytes to send
TX_AXIS_TDATA : OUT std_logic_vector(63 DOWNTO 0);
TX_AXIS_TKEEP : OUT std_logic_vector(7 DOWNTO 0);
TX_AXIS_TVALID : OUT std_logic;
TX_AXIS_TLAST : OUT std_logic;
TX_AXIS_TREADY : IN std_logic
);
END ten_gig_eth_packet_gen;
ARCHITECTURE Behavioral OF ten_gig_eth_packet_gen IS
COMPONENT ten_gig_eth_packet_ram
PORT (
CLKA : IN std_logic;
WEA : IN std_logic_vector(0 DOWNTO 0);
ADDRA : IN std_logic_vector(11 DOWNTO 0);
DINA : IN std_logic_vector(31 DOWNTO 0);
CLKB : IN std_logic;
ADDRB : IN std_logic_vector(10 DOWNTO 0);
DOUTB : OUT std_logic_vector(63 DOWNTO 0)
);
END COMPONENT;
SIGNAL mem_clk_i : std_logic;
SIGNAL tx_clk_i : std_logic;
TYPE pktState_type IS (S0, S1, S2, S3, S4);
SIGNAL pktState : pktState_type;
SIGNAL mem_wea : std_logic_vector(0 DOWNTO 0);
SIGNAL addrb_i : std_logic_vector(10 DOWNTO 0);
SIGNAL doutb_i : std_logic_vector(63 DOWNTO 0);
SIGNAL addrCtr : unsigned(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL bytesLeft : unsigned(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL bytesLeft_reg : unsigned(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL pktCtr : unsigned(47 DOWNTO 0) := (OTHERS => '0');
BEGIN
mem_clk_i <= MEM_CLK;
tx_clk_i <= TX_AXIS_ACLK;
mem_wea <= (OTHERS => MEM_WE);
tge_packet_ram_inst : ten_gig_eth_packet_ram
PORT MAP (
CLKA => mem_clk_i,
WEA => mem_wea,
ADDRA => MEM_ADDR(11 DOWNTO 0),
DINA => MEM_D,
CLKB => tx_clk_i,
ADDRB => addrb_i,
DOUTB => doutb_i
);
PROCESS (tx_clk_i) IS
BEGIN
IF falling_edge(tx_clk_i) THEN
TX_AXIS_TDATA <= doutb_i;
IF addrCtr = 5 THEN
-- little endian of pktCtr seen by the host
TX_AXIS_TDATA <= std_logic_vector(pktCtr) & doutb_i(15 DOWNTO 0);
-- convert to big endian
--TX_AXIS_TDATA <= std_logic_vector(pktCtr(7 DOWNTO 0))
-- & std_logic_vector(pktCtr(15 DOWNTO 8))
-- & std_logic_vector(pktCtr(23 DOWNTO 16))
-- & std_logic_vector(pktCtr(31 DOWNTO 24))
-- & std_logic_vector(pktCtr(39 DOWNTO 32))
-- & std_logic_vector(pktCtr(47 DOWNTO 40))
-- & doutb_i(15 DOWNTO 0);
END IF;
END IF;
END PROCESS;
pkt_sm: PROCESS (tx_clk_i, RESET) IS
BEGIN
IF RESET = '1' THEN
pktState <= S0;
pktCtr <= (OTHERS => '0');
addrCtr <= (OTHERS => '0');
TX_AXIS_TVALID <= '0';
TX_AXIS_TLAST <= '0';
ELSIF falling_edge(tx_clk_i) THEN
TX_AXIS_TVALID <= '0';
TX_AXIS_TLAST <= '0';
CASE pktState IS
WHEN S0 =>
IF TX_START = '1' THEN
addrCtr <= (OTHERS => '0');
bytesLeft <= unsigned(TX_BYTES);
-- minimum packet length requirement
IF unsigned(TX_BYTES) < 14 THEN
pktState <= S0;
ELSE
pktState <= S1;
END IF;
END IF;
WHEN S1 =>
pktState <= S1;
TX_AXIS_TVALID <= '1';
IF TX_AXIS_TREADY = '1' THEN
addrCtr <= addrCtr + 1;
bytesLeft_reg <= bytesLeft;
bytesLeft <= bytesLeft - 8;
IF bytesLeft <= 8 THEN
pktState <= S2;
TX_AXIS_TLAST <= '1';
END IF;
END IF;
WHEN S2 =>
pktState <= S0;
pktCtr <= pktCtr + 1;
WHEN OTHERS =>
pktState <= S0;
END CASE;
END IF;
END PROCESS pkt_sm;
addrb_i <= std_logic_vector(addrCtr(10 DOWNTO 0));
WITH bytesLeft_reg SELECT
TX_AXIS_TKEEP <=
(OTHERS => '0') WHEN to_unsigned(0,bytesLeft_reg'length),
"00000001" WHEN to_unsigned(1,bytesLeft_reg'length),
"00000011" WHEN to_unsigned(2,bytesLeft_reg'length),
"00000111" WHEN to_unsigned(3,bytesLeft_reg'length),
"00001111" WHEN to_unsigned(4,bytesLeft_reg'length),
"00011111" WHEN to_unsigned(5,bytesLeft_reg'length),
"00111111" WHEN to_unsigned(6,bytesLeft_reg'length),
"01111111" WHEN to_unsigned(7,bytesLeft_reg'length),
(OTHERS => '1') WHEN OTHERS;
END Behavioral;
|
---------------------------------------------------------------------------------------------------
--
-- Title : zcpsmRom
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity zcpsmRom is
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port(
reset : in std_logic;
clk : in std_logic;
port_ce : out std_logic_vector(15 downto 0);
port_id : out std_logic_vector(3 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end zcpsmRom;
--}} End of automatically maintained section
architecture behavior of zcpsmRom is
component zcpsm
Port (
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component zcpsmProgRom
generic (
AWIDTH : natural := 10;
PROG : string := "program.bit"
);
port (
clk : in std_logic;
addr : in std_logic_vector( AWIDTH-1 downto 0 );
dout : out std_logic_vector( 17 downto 0 )
);
end component;
component zcpsmDecode
port (
port_id_H : in std_logic_vector(3 downto 0);
ce : out std_logic_vector(15 downto 0)
);
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id_i : std_logic_vector(7 downto 0);
begin
port_id <= port_id_i( 3 downto 0 );
u_rx_zcpsm : zcpsm
port map(
address => address,
instruction => instruction,
port_id => port_id_i,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => '0',
reset => reset,
clk => clk
);
u_rom : zcpsmProgRom
generic map(
AWIDTH => 10,
PROG => PROG
)
port map(
clk => clk,
addr => address( AWIDTH-1 downto 0 ),
dout => instruction
);
u_decode : zcpsmDecode
port map(
port_id_H => port_id_i( 7 downto 4 ),
ce => port_ce
);
end behavior;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ent is
generic (
INT : integer := -25;
SL : std_logic := '1'
);
port (
a : in signed(7 downto 0);
b : in signed(7 downto 0);
const : out signed(7 downto 0);
absolute1 : out unsigned(7 downto 0);
absolute2 : out unsigned(7 downto 0);
sum : out signed(8 downto 0);
diff : out signed(8 downto 0);
inv_diff : out signed(8 downto 0);
quarter : out signed(7 downto 0);
int_sum : out signed(8 downto 0);
int_diff : out signed(8 downto 0);
inv_int_sum : out signed(8 downto 0);
inv_int_diff : out signed(8 downto 0);
sl_sum : out signed(8 downto 0);
sl_diff : out signed(8 downto 0);
inv_sl_sum : out signed(8 downto 0);
inv_sl_diff : out signed(8 downto 0);
lt : out boolean;
le : out boolean;
eq : out boolean;
neq : out boolean;
ge : out boolean;
gt : out boolean;
int_lt : out boolean;
int_le : out boolean;
int_eq : out boolean;
int_neq : out boolean;
int_ge : out boolean;
int_gt : out boolean;
inv_int_lt : out boolean;
inv_int_le : out boolean;
inv_int_eq : out boolean;
inv_int_neq : out boolean;
inv_int_ge : out boolean;
inv_int_gt : out boolean
);
end;
architecture a of ent is
signal ra, rb : signed(8 downto 0);
begin
ra <= resize(a, 9);
rb <= resize(b, 9);
const <= to_signed(INT, const'length);
absolute1 <= to_unsigned(abs(INT), absolute1'length);
absolute2 <= unsigned(abs(a));
sum <= ra + rb;
diff <= ra + (-rb);
inv_diff <= rb - ra;
quarter <= a / 4;
int_sum <= ra + INT;
int_diff <= ra - INT;
inv_int_sum <= INT + ra;
inv_int_diff <= INT - ra;
sl_sum <= ra + SL;
sl_diff <= ra - SL;
inv_sl_sum <= SL + ra;
inv_sl_diff <= SL - ra;
lt <= a < b;
le <= a <= b;
eq <= a = b;
neq <= a /= b;
ge <= a >= b;
gt <= a > b;
int_lt <= a < INT;
int_le <= a <= INT;
int_eq <= a = INT;
int_neq <= a /= INT;
int_ge <= a >= INT;
int_gt <= a > INT;
inv_int_lt <= INT < b;
inv_int_le <= INT <= b;
inv_int_eq <= INT = b;
inv_int_neq <= INT /= b;
inv_int_ge <= INT >= b;
inv_int_gt <= INT > b;
end;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic;
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : out std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic;
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic;
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end component;
signal clk125, clk50, clkout: std_ulogic := '0';
signal rst: std_ulogic;
signal user_led: std_logic_vector(3 downto 0);
signal address : std_logic_vector(26 downto 1);
signal data : std_logic_vector(15 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
constant lresp : boolean := false;
signal eneta_rx_clk, eneta_tx_clk, enetb_rx_clk, enetb_tx_clk: std_ulogic;
signal eneta_intn, eneta_resetn, enetb_intn, enetb_resetn: std_ulogic;
signal eneta_mdio, enetb_mdio: std_logic;
signal eneta_mdc, enetb_mdc: std_ulogic;
signal eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_rx_dv: std_ulogic;
signal enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_rx_dv: std_ulogic;
signal eneta_rx_d, enetb_rx_d: std_logic_vector(7 downto 0);
signal eneta_tx_d, enetb_tx_d: std_logic_vector(7 downto 0);
signal eneta_tx_en, eneta_tx_er, enetb_tx_en, enetb_tx_er: std_ulogic;
signal lpddr2_ck, lpddr2_ck_n, lpddr2_cke, lpddr2_cs_n: std_ulogic;
signal lpddr2_ca: std_logic_vector(9 downto 0);
signal lpddr2_dm, lpddr2_dqs, lpddr2_dqs_n: std_logic_vector(3 downto 0);
signal lpddr2_dq: std_logic_vector(31 downto 0);
begin
-- clock and reset
clk125 <= not clk125 after 4 ns;
clk50 <= not clk50 after 10 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : leon3mp
generic map ( fabtech, memtech, padtech, disas, dbguart, pclow )
port map (
-- Clock and reset
diff_clkin_top_125_p => clk125,
diff_clkin_bot_125_p => clk125,
clkin_50_fpga_right => clk50,
clkin_50_fpga_top => clk50,
clkout_sma => clkout,
cpu_resetn => rst,
-- DDR3
ddr3_ck_p => open,
ddr3_ck_n => open,
ddr3_cke => open,
ddr3_rstn => open,
ddr3_csn => open,
ddr3_rasn => open,
ddr3_casn => open,
ddr3_wen => open,
ddr3_ba => open,
ddr3_a => open,
ddr3_dqs_p => open,
ddr3_dqs_n => open,
ddr3_dq => open,
ddr3_dm => open,
ddr3_odt => open,
ddr3_oct_rzq => '0',
-- LPDDR2
lpddr2_ck_p => lpddr2_ck,
lpddr2_ck_n => lpddr2_ck_n,
lpddr2_cke => lpddr2_cke,
lpddr2_a => lpddr2_ca,
lpddr2_dqs_p => lpddr2_dqs(1 downto 0),
lpddr2_dqs_n => lpddr2_dqs_n(1 downto 0),
lpddr2_dq => lpddr2_dq(15 downto 0),
lpddr2_dm => lpddr2_dm(1 downto 0),
lpddr2_csn => lpddr2_cs_n,
lpddr2_oct_rzq => '0',
-- Flash and SSRAM interface
fm_a => address(26 downto 1),
fm_d => data,
flash_clk => open,
flash_resetn => open,
flash_cen => romsn,
flash_advn => open,
flash_wen => rwen,
flash_oen => oen,
flash_rdybsyn => '1',
ssram_clk => open,
ssram_oen => open,
sram_cen => open,
ssram_bwen => open,
ssram_bwan => open,
ssram_bwbn => open,
ssram_adscn => open,
ssram_adspn => open,
ssram_zzn => open,
ssram_advn => open,
-- EEPROM
eeprom_scl => open,
eeprom_sda => open,
-- UART
uart_rxd => rxd1,
uart_rts => '1',
uart_txd => txd1,
uart_cts => open,
-- USB UART Interface
usb_uart_rstn => '1',
usb_uart_ri => '0',
usb_uart_dcd => '1',
usb_uart_dtr => open,
usb_uart_dsr => '1',
usb_uart_txd => open,
usb_uart_rxd => '1',
usb_uart_rts => '1',
usb_uart_cts => open,
usb_uart_gpio2 => '0',
usb_uart_suspend => '0',
usb_uart_suspendn => '1',
-- Ethernet port A
eneta_rx_clk => eneta_rx_clk,
eneta_tx_clk => eneta_tx_clk,
eneta_intn => eneta_intn,
eneta_resetn => eneta_resetn,
eneta_mdio => eneta_mdio,
eneta_mdc => eneta_mdc,
eneta_rx_er => eneta_rx_er,
eneta_tx_er => eneta_tx_er,
eneta_rx_col => eneta_rx_col,
eneta_rx_crs => eneta_rx_crs,
eneta_tx_d => eneta_tx_d(3 downto 0),
eneta_rx_d => eneta_rx_d(3 downto 0),
eneta_gtx_clk => open,
eneta_tx_en => eneta_tx_en,
eneta_rx_dv => eneta_rx_dv,
-- Ethernet port B
enetb_rx_clk => enetb_rx_clk,
enetb_tx_clk => enetb_tx_clk,
enetb_intn => enetb_intn,
enetb_resetn => enetb_resetn,
enetb_mdio => enetb_mdio,
enetb_mdc => enetb_mdc,
enetb_rx_er => enetb_rx_er,
enetb_tx_er => enetb_tx_er,
enetb_rx_col => enetb_rx_col,
enetb_rx_crs => enetb_rx_crs,
enetb_tx_d => enetb_tx_d(3 downto 0),
enetb_rx_d => enetb_rx_d(3 downto 0),
enetb_gtx_clk => open,
enetb_tx_en => enetb_tx_en,
enetb_rx_dv => enetb_rx_dv,
-- LEDs, switches, GPIO
user_led => user_led,
user_dipsw => "1111",
dip_3p3V => '0',
user_pb => "0000",
overtemp_fpga => open,
header_p => "000000",
header_n => "000000",
header_d => "00000000",
-- LCD
lcd_data => "00000000",
lcd_wen => open,
lcd_csn => open,
lcd_d_cn => open,
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0 => '0',
-- hsmc_clk_out0 => open,
-- hsmc_clk_in_p => "00",
-- hsmc_clk_out_p => open,
-- hsmc_d => "0000",
-- hsmc_tx_d_p => open,
-- hsmc_rx_d_p => (others => '0'),
-- hsmc_rx_led => open,
-- hsmc_tx_led => open,
-- hsmc_scl => open,
-- hsmc_sda => '0',
-- hsmc_prsntn => '0',
-- MAX V CPLD interface
max5_csn => open,
max5_wen => open,
max5_oen => open,
max5_ben => open,
max5_clk => open,
-- USB Blaster II
usb_clk => '0',
usb_data => (others => '0'),
usb_addr => "00",
usb_scl => '0',
usb_sda => '0',
usb_resetn => '0',
usb_oen => '0',
usb_rdn => '0',
usb_wrn => '0',
usb_full => open,
usb_empty => open,
fx2_resetn => '1'
);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data,
romsn, romsn, romsn, rwen, oen);
-- ROMSN is pulled down by the MAX V system controller after FPGA programming
-- completed (bug?)
romsn <= 'L';
data <= buskeep(data), (others => 'H') after 250 ns;
error <= user_led(3);
eneta_mdio <= 'H';
enetb_mdio <= 'H';
eneta_tx_d(7 downto 4) <= "0000";
enetb_tx_d(7 downto 4) <= "0000";
p1: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 0)
port map(rst, eneta_mdio, eneta_tx_clk, eneta_rx_clk, eneta_rx_d, eneta_rx_dv,
eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_tx_d, eneta_tx_en, eneta_tx_er, eneta_mdc,
'0');
p2: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(rst, enetb_mdio, enetb_tx_clk, enetb_rx_clk, enetb_rx_d, enetb_rx_dv,
enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_tx_d, enetb_tx_en, enetb_tx_er, enetb_mdc,
'0');
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod generic map (width => 16)
port map ( rst, clk50, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
component nios_system is
port (
alu_a_export : out std_logic_vector(31 downto 0); -- export
alu_b_export : out std_logic_vector(31 downto 0); -- export
alu_carry_out_export : in std_logic := 'X'; -- export
alu_control_export : out std_logic_vector(2 downto 0); -- export
alu_negative_export : in std_logic := 'X'; -- export
alu_out_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
alu_overflow_export : in std_logic := 'X'; -- export
alu_zero_export : in std_logic := 'X'; -- export
clk_clk : in std_logic := 'X'; -- clk
hex_0_export : out std_logic_vector(3 downto 0); -- export
hex_1_export : out std_logic_vector(3 downto 0); -- export
hex_2_export : out std_logic_vector(3 downto 0); -- export
hex_3_export : out std_logic_vector(3 downto 0); -- export
hex_4_export : out std_logic_vector(3 downto 0); -- export
hex_5_export : out std_logic_vector(3 downto 0); -- export
leds_export : out std_logic_vector(9 downto 0); -- export
regfile_data_export : out std_logic_vector(31 downto 0); -- export
regfile_r1sel_export : out std_logic_vector(5 downto 0); -- export
regfile_r2sel_export : out std_logic_vector(5 downto 0); -- export
regfile_reg1_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
regfile_reg2_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
regfile_we_export : out std_logic; -- export
regfile_wsel_export : out std_logic_vector(5 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
sram_addr_export : out std_logic_vector(10 downto 0); -- export
sram_cs_export : out std_logic; -- export
sram_data_in_export : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
sram_oe_export : out std_logic; -- export
sram_read_write_export : out std_logic; -- export
switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
keys_export : in std_logic_vector(3 downto 0) := (others => 'X') -- export
);
end component nios_system;
u0 : component nios_system
port map (
alu_a_export => CONNECTED_TO_alu_a_export, -- alu_a.export
alu_b_export => CONNECTED_TO_alu_b_export, -- alu_b.export
alu_carry_out_export => CONNECTED_TO_alu_carry_out_export, -- alu_carry_out.export
alu_control_export => CONNECTED_TO_alu_control_export, -- alu_control.export
alu_negative_export => CONNECTED_TO_alu_negative_export, -- alu_negative.export
alu_out_export => CONNECTED_TO_alu_out_export, -- alu_out.export
alu_overflow_export => CONNECTED_TO_alu_overflow_export, -- alu_overflow.export
alu_zero_export => CONNECTED_TO_alu_zero_export, -- alu_zero.export
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
hex_0_export => CONNECTED_TO_hex_0_export, -- hex_0.export
hex_1_export => CONNECTED_TO_hex_1_export, -- hex_1.export
hex_2_export => CONNECTED_TO_hex_2_export, -- hex_2.export
hex_3_export => CONNECTED_TO_hex_3_export, -- hex_3.export
hex_4_export => CONNECTED_TO_hex_4_export, -- hex_4.export
hex_5_export => CONNECTED_TO_hex_5_export, -- hex_5.export
leds_export => CONNECTED_TO_leds_export, -- leds.export
regfile_data_export => CONNECTED_TO_regfile_data_export, -- regfile_data.export
regfile_r1sel_export => CONNECTED_TO_regfile_r1sel_export, -- regfile_r1sel.export
regfile_r2sel_export => CONNECTED_TO_regfile_r2sel_export, -- regfile_r2sel.export
regfile_reg1_export => CONNECTED_TO_regfile_reg1_export, -- regfile_reg1.export
regfile_reg2_export => CONNECTED_TO_regfile_reg2_export, -- regfile_reg2.export
regfile_we_export => CONNECTED_TO_regfile_we_export, -- regfile_we.export
regfile_wsel_export => CONNECTED_TO_regfile_wsel_export, -- regfile_wsel.export
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sram_addr_export => CONNECTED_TO_sram_addr_export, -- sram_addr.export
sram_cs_export => CONNECTED_TO_sram_cs_export, -- sram_cs.export
sram_data_in_export => CONNECTED_TO_sram_data_in_export, -- sram_data_in.export
sram_oe_export => CONNECTED_TO_sram_oe_export, -- sram_oe.export
sram_read_write_export => CONNECTED_TO_sram_read_write_export, -- sram_read_write.export
switches_export => CONNECTED_TO_switches_export, -- switches.export
keys_export => CONNECTED_TO_keys_export -- keys.export
);
|
-------------------------------------------------------------------------------
-- $Id: wrpfifo_dp_cntl.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--wrpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Write Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
--
-- wrpfifo_dp_cntl.vhd
-- |
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- | |
-- | |-- pf_adder_bit.vhd
-- |
-- |
-- |
-- |-- pf_dly1_mux.vhd
--
--
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe April 6, 2001 -- V1.00b (Backup of read count at end of
-- read)
--
-- DET May 24, 2001 -- V1.00c (fixed bug where RdAck was
-- issued if RdReq from IP occured on the
-- immediatly following clock cycle after
-- a 'Release' command
--
-- DET June 25, 2001 -- Added the DP Core with the ENB input
-- so that the DP port B (Read port) is
-- disabled when the WrFIFO is empty. This
-- clears up MTI sim warnings.
--
--
-- DET Sept. 27, 2001 -- Size Optimized redesign and
-- parameterization
--
-- DET Oct. 10, 2001 -- added pf_dly1_mux module to design
--
--
-- DET 1/21/2003 V2_00_a
-- ~~~~~~
-- - Corrected a burst read problem where the IP stops a burst read
-- with one data value left in the FIFO.
-- ^^^^^^
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
-- Designed by: D. Thorpe
-- Xilinx Mona Loa IP Team
-- Albuquerque, NM
-- APR 10, 2001
--
--
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_top;
use opb_ipif_v2_00_h.pf_occ_counter_top;
use opb_ipif_v2_00_h.pf_adder;
use opb_ipif_v2_00_h.pf_dly1_mux;
----------------------------------------------------------------------
entity wrpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 5;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port(
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_wr_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end wrpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
Constant DLY_MUX_WIDTH : integer := OCC_CNTR_WIDTH+2;
--Shared internal signals
Signal base_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
-------------------------- start processes ------------------------------------
begin -- architecture
---------------------------------------------------------------------------
-- Generate the Write PFIFO with packetizing features included
---------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (reset1,
--reset2,
--reset3,
normal_op,
packet_op,
rest1,
rest2,
mark1,
--mark2,
rls1,
--rls2,
--pkt_rd_backup,
--nml_rd_backup,
pkt_update,
nml_update
);
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal decr_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_read : std_logic;
signal ld_addr_read_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_decr : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
--signal sig_normal_occupancy_dly1 : std_logic_vector(0 to
-- OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
base_occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib)
-- needed during burst to fill pipeline
-- (1 clock) out of DPort Block
and not(hold_ack);
-- added May 24 to fix RdAck generation
-- immediately after release
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_ipif_v2_00_h.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
dly_sel1 => '0',
dly_sel2 => back_to_back_rd,
Inputs => dly_mux_in,
Y_out => dly_mux_out
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
--------------------------------------------------------------------
-- Transition sequence state machine
--------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
trans_state <= reset1;
hold_ack <= '1';
Elsif (Bus_clk'event and Bus_clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Case trans_state Is
When reset1 =>
--trans_state <= reset2;
trans_state <= normal_op;
hold_ack <= '1';
enable_wr_addr_inc <= '0';
-- When reset2 =>
-- trans_state <= reset3;
-- hold_ack <= '1';
-- When reset3 =>
-- trans_state <= normal_op;
-- hold_ack <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
-- Elsif (rd_backup = '1') Then
-- trans_state <= nml_rd_backup;
-- hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
-- elsif (rd_backup = '1') then
-- trans_state <= pkt_rd_backup;
-- hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
ld_addr_mark_into_read <= '1';
ld_occ_mark_into_norm <= '1';
trans_state <= rest2;
--trans_state <= pkt_update;
hold_ack <= '1';
When rest2 =>
trans_state <= pkt_update;
hold_ack <= '1';
When mark1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= mark2;
trans_state <= pkt_update;
hold_ack <= '1';
-- When mark2 =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
When rls1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= rls2;
trans_state <= nml_update;
hold_ack <= '1';
-- When rls2 =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
-- When pkt_rd_backup =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
-- When nml_rd_backup =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
When nml_update =>
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking
-- operations. This counter establishes the full flag states
------------------------------------------------------------------
--inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc_by_2 <= decr_mark_addr and inc_wr_addr;
inc_mocc <= decr_mark_addr or inc_wr_addr;
I_MARK_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_mark_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup) ;
-- added as part of V0_00c mods
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
-- inc_wr_addr <= WrReq
-- and not(int_full)
-- and not(int_full_dly1)
-- and not(int_full_dly2)
-- and not(hold_ack)
-- and not(rd_backup and int_almost_full)
-- and enable_wr_addr_inc;
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and enable_wr_addr_inc;
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- process_name
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(hold_ack)
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_read,
Load_value => mark_address,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_rd_addr
and enable_mark_addr_inc;
decr_mark_addr <= rd_backup
and enable_rd_addr_decr
and enable_mark_addr_decr;
I_MARKREG_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_read_into_mark,
Load_value => read_address,
Count_Down => decr_mark_addr,
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
----------------------------------------------------------------------------
-- Generate the Write PFIFO with no packetizing features
----------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
-- Internal signals
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_wr_addr : std_logic;
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal rd_backup : std_logic;
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal occ_load_value : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib);
-- needed during burst to fill
-- pipeline (1 clock) out of DPort
-- Block
DeadLock <= int_full and int_empty; -- both full and empty
-- at the same time
DP_core_rden <= not(int_empty)-- assert read enable when not
or Bus_rst; -- empty or during reset
DP_core_wren <= not(int_full) -- assert write enable when not
or Bus_rst; -- full or during reset
base_occupancy <= sig_normal_occupancy;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_ipif_v2_00_h.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,-- : in std_logic;
Rst => Bus_rst,-- : In std_logic;
dly_sel1 => '0', --burst_ack_inhib,-- : in std_logic;
dly_sel2 => back_to_back_rd,-- : in std_logic;
Inputs => dly_mux_in,-- : in std_logic_vector;
Y_out => dly_mux_out-- : out std_logic_vector
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup);
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2);
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- REG_READ_REQUEST
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(int_empty)
and not(int_empty_dly1);
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup;
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_ipif_v2_00_h.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => base_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: wrpfifo_dp_cntl.vhd,v 1.2 2004/11/23 01:04:03 jcanaris Exp $
-------------------------------------------------------------------------------
--wrpfifo_dp_cntl.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: wrpfifo_dp_cntl.vhd
--
-- Description: This VHDL design file is for the Mauna Loa Write Packet
-- FIFO Dual Port Control block and the status
-- calculations for the Occupancy, Vacancy, Full, and Empty.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the WPFIFO design.
--
--
-- wrpfifo_dp_cntl.vhd
-- |
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- | |
-- | |-- pf_adder_bit.vhd
-- |
-- |
-- |
-- |-- pf_dly1_mux.vhd
--
--
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe April 6, 2001 -- V1.00b (Backup of read count at end of
-- read)
--
-- DET May 24, 2001 -- V1.00c (fixed bug where RdAck was
-- issued if RdReq from IP occured on the
-- immediatly following clock cycle after
-- a 'Release' command
--
-- DET June 25, 2001 -- Added the DP Core with the ENB input
-- so that the DP port B (Read port) is
-- disabled when the WrFIFO is empty. This
-- clears up MTI sim warnings.
--
--
-- DET Sept. 27, 2001 -- Size Optimized redesign and
-- parameterization
--
-- DET Oct. 10, 2001 -- added pf_dly1_mux module to design
--
--
-- DET 1/21/2003 V2_00_a
-- ~~~~~~
-- - Corrected a burst read problem where the IP stops a burst read
-- with one data value left in the FIFO.
-- ^^^^^^
-- LCW Nov 8, 2004 -- updated for NCSim
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
-- Designed by: D. Thorpe
-- Xilinx Mona Loa IP Team
-- Albuquerque, NM
-- APR 10, 2001
--
--
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library opb_ipif_v2_00_h;
use opb_ipif_v2_00_h.pf_counter_top;
use opb_ipif_v2_00_h.pf_occ_counter_top;
use opb_ipif_v2_00_h.pf_adder;
use opb_ipif_v2_00_h.pf_dly1_mux;
----------------------------------------------------------------------
entity wrpfifo_dp_cntl is
Generic (
C_DP_ADDRESS_WIDTH : Integer := 5;
-- number of bits needed for dual port addressing
-- of requested FIFO depth
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/ommision of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true
-- Enable for Vacancy calc feature
);
port(
-- Inputs
Bus_rst : In std_logic;
Bus_clk : In std_logic;
Rdreq : In std_logic;
Wrreq : In std_logic;
Burst_wr_xfer : In std_logic;
Mark : In std_logic;
Restore : In std_logic;
Release : In std_logic;
-- Outputs
WrAck : Out std_logic;
RdAck : Out std_logic;
Full : Out std_logic;
Empty : Out std_logic;
Almost_Full : Out std_logic;
Almost_Empty : Out std_logic;
DeadLock : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Vacancy : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
DP_core_wren : Out std_logic;
Wr_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1);
DP_core_rden : Out std_logic;
Rd_Addr : Out std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1)
);
end wrpfifo_dp_cntl ;
-------------------------------------------------------------------------------
architecture implementation of wrpfifo_dp_cntl is
-- Components
-- CONSTANTS
Constant OCC_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH+1;
Constant ADDR_CNTR_WIDTH : integer := C_DP_ADDRESS_WIDTH;
Constant MAX_OCCUPANCY : integer := 2**ADDR_CNTR_WIDTH;
Constant LOGIC_LOW : std_logic := '0';
Constant DLY_MUX_WIDTH : integer := OCC_CNTR_WIDTH+2;
--Shared internal signals
Signal base_occupancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
-------------------------------------------------------------------------------
-------------------------- start processes ------------------------------------
begin -- architecture
---------------------------------------------------------------------------
-- Generate the Write PFIFO with packetizing features included
---------------------------------------------------------------------------
INCLUDE_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = true) generate
--TYPES
type transition_state_type is (reset1,
--reset2,
--reset3,
normal_op,
packet_op,
rest1,
rest2,
mark1,
--mark2,
rls1,
--rls2,
--pkt_rd_backup,
--nml_rd_backup,
pkt_update,
nml_update
);
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal trans_state : transition_state_type;
signal hold_ack : std_logic;
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal inc_wr_addr : std_logic;
Signal inc_mark_addr : std_logic;
Signal decr_mark_addr : std_logic;
Signal rd_backup : std_logic;
Signal dummy_empty : std_logic;
Signal dummy_almost_empty : std_logic;
Signal dummy_full : std_logic;
Signal dummy_almost_full : std_logic;
signal ld_occ_norm_into_mark : std_logic;
signal ld_addr_mark_into_read : std_logic;
signal ld_addr_read_into_mark : std_logic;
signal ld_occ_mark_into_norm : std_logic;
signal enable_mark_addr_decr : std_logic;
signal enable_mark_addr_inc : std_logic;
signal enable_wr_addr_inc : std_logic;
signal enable_rd_addr_inc : std_logic;
signal enable_rd_addr_decr : std_logic;
signal sig_mark_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
--signal sig_normal_occupancy_dly1 : std_logic_vector(0 to
-- OCC_CNTR_WIDTH-1);
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal mark_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_mocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal inc_mocc_by_2 : std_logic;
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
base_occupancy <= sig_mark_occupancy;
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib)
-- needed during burst to fill pipeline
-- (1 clock) out of DPort Block
and not(hold_ack);
-- added May 24 to fix RdAck generation
-- immediately after release
DeadLock <= int_full and int_empty; -- both full and empty at
-- the same time
DP_core_rden <= not(int_empty)-- assert read enable when not empty
or Bus_rst; -- or during reset
DP_core_wren <= not(int_full) -- assert write enable when not full
or Bus_rst; -- or during reset
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_ipif_v2_00_h.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
dly_sel1 => '0',
dly_sel2 => back_to_back_rd,
Inputs => dly_mux_in,
Y_out => dly_mux_out
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
--------------------------------------------------------------------
-- Transition sequence state machine
--------------------------------------------------------------------
TRANSITION_STATE_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '0';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
trans_state <= reset1;
hold_ack <= '1';
Elsif (Bus_clk'event and Bus_clk = '1') Then
-- set default values
trans_state <= reset1;
hold_ack <= '1';
ld_occ_norm_into_mark <= '0';
ld_addr_read_into_mark <= '0';
ld_addr_mark_into_read <= '0';
ld_occ_mark_into_norm <= '0';
enable_mark_addr_inc <= '0';
enable_mark_addr_decr <= '0';
enable_wr_addr_inc <= '1';
enable_rd_addr_inc <= '0';
enable_rd_addr_decr <= '0';
Case trans_state Is
When reset1 =>
--trans_state <= reset2;
trans_state <= normal_op;
hold_ack <= '1';
enable_wr_addr_inc <= '0';
-- When reset2 =>
-- trans_state <= reset3;
-- hold_ack <= '1';
-- When reset3 =>
-- trans_state <= normal_op;
-- hold_ack <= '0';
When normal_op => -- Ignore restore and release inputs
-- during normal op
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Mark = '1') Then -- transition to packet op on a
-- Mark command
trans_state <= mark1;
hold_ack <= '1';
-- Elsif (rd_backup = '1') Then
-- trans_state <= nml_rd_backup;
-- hold_ack <= '1';
else
trans_state <= normal_op;
hold_ack <= '0';
End if;
When packet_op =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
If (Restore = '1') Then
trans_state <= rest1;
hold_ack <= '1';
Elsif (Mark = '1') Then
trans_state <= mark1;
hold_ack <= '1';
Elsif (Release = '1') Then
trans_state <= rls1;
hold_ack <= '1';
-- elsif (rd_backup = '1') then
-- trans_state <= pkt_rd_backup;
-- hold_ack <= '1';
else
trans_state <= packet_op;
hold_ack <= '0';
End if;
When rest1 =>
ld_addr_mark_into_read <= '1';
ld_occ_mark_into_norm <= '1';
trans_state <= rest2;
--trans_state <= pkt_update;
hold_ack <= '1';
When rest2 =>
trans_state <= pkt_update;
hold_ack <= '1';
When mark1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= mark2;
trans_state <= pkt_update;
hold_ack <= '1';
-- When mark2 =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
When rls1 =>
ld_occ_norm_into_mark <= '1';
ld_addr_read_into_mark <= '1';
--trans_state <= rls2;
trans_state <= nml_update;
hold_ack <= '1';
-- When rls2 =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
-- When pkt_rd_backup =>
-- trans_state <= pkt_update;
-- hold_ack <= '1';
-- When nml_rd_backup =>
-- trans_state <= nml_update;
-- hold_ack <= '1';
When nml_update =>
enable_mark_addr_inc <= '1';
enable_mark_addr_decr <= '1';
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= normal_op;
hold_ack <= '0';
When pkt_update =>
enable_rd_addr_inc <= '1';
enable_rd_addr_decr <= '1';
trans_state <= packet_op;
hold_ack <= '0';
When others =>
trans_state <= normal_op;
hold_ack <= '0';
End case;
Else
null;
End if;
End process; -- TRANSITION_STATE_PROCESS
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to marking
-- operations. This counter establishes the full flag states
------------------------------------------------------------------
--inc_mocc_by_2 <= decr_rd_addr and inc_mark_addr;
inc_mocc_by_2 <= decr_mark_addr and inc_wr_addr;
inc_mocc <= decr_mark_addr or inc_wr_addr;
I_MARK_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_norm_into_mark,
Load_value => sig_normal_occupancy,
Count_Down => inc_mark_addr,
Count_Up => inc_mocc,
By_2 => inc_mocc_by_2,
Count_Out => sig_mark_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => dummy_almost_empty,
empty => dummy_empty
);
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_occ_mark_into_norm,
Load_value => sig_mark_occupancy,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => dummy_almost_full,
full => dummy_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup) ;
-- added as part of V0_00c mods
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
-- inc_wr_addr <= WrReq
-- and not(int_full)
-- and not(int_full_dly1)
-- and not(int_full_dly2)
-- and not(hold_ack)
-- and not(rd_backup and int_almost_full)
-- and enable_wr_addr_inc;
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2)
and enable_wr_addr_inc;
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- process_name
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(hold_ack)
and not(int_empty)
and not(int_empty_dly1)
and enable_rd_addr_inc;
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup
and enable_rd_addr_decr;
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_mark_into_read,
Load_value => mark_address,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Mark Register Control
inc_mark_addr <= inc_rd_addr
and enable_mark_addr_inc;
decr_mark_addr <= rd_backup
and enable_rd_addr_decr
and enable_mark_addr_decr;
I_MARKREG_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => ld_addr_read_into_mark,
Load_value => read_address,
Count_Down => decr_mark_addr,
Count_Up => inc_mark_addr,
Count_Out => mark_address
);
-- end mark address counter logic
------------------------------------------------------------------
end generate INCLUDE_PACKET_FEATURES;
----------------------------------------------------------------------------
-- Generate the Write PFIFO with no packetizing features
----------------------------------------------------------------------------
OMIT_PACKET_FEATURES : if (C_INCLUDE_PACKET_MODE = false) generate
-- Internal signals
signal int_full : std_logic;
signal int_full_dly1 : std_logic;
signal int_full_dly2 : std_logic;
signal int_almost_full : std_logic;
signal int_empty : std_logic;
signal int_almost_empty : std_logic;
Signal int_almost_empty_dly1 : std_logic;
Signal int_empty_dly1 : std_logic;
Signal inc_wr_addr : std_logic;
signal write_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
Signal inc_rd_addr : std_logic;
Signal decr_rd_addr : std_logic;
Signal rd_backup : std_logic;
signal read_address : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal sig_zeros : std_logic_vector(0 to
ADDR_CNTR_WIDTH-1);
signal inc_nocc : std_logic;
signal inc_nocc_by_2 : std_logic;
signal sig_normal_occupancy : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
signal occ_load_value : std_logic_vector(0 to
OCC_CNTR_WIDTH-1);
Signal burst_ack_inhib : std_logic;
signal int_rdack : std_logic;
Signal valid_read : std_logic;
Signal back_to_back_rd : std_logic;
Signal rdreq_dly1 : std_logic;
Signal dly_mux_in :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal dly_mux_out :std_logic_vector(0 to
DLY_MUX_WIDTH-1);
Signal rdack_dly1 : std_logic;
Signal rdack_i : std_logic;
Signal bkup_recover : std_logic;
begin
--Misc I/O Assignments
Full <= int_full
or int_full_dly1
or int_full_dly2;
Almost_Full <= int_almost_full
and not(int_full_dly1)
and not(int_full_dly2);
Wr_Addr <= write_address;
Rd_Addr <= read_address;
WrAck <= inc_wr_addr ; -- currently combinitorial
RdAck <= rdack_i;
rdack_i <= int_rdack
and Rdreq -- RdReq used to terminate acknowledge
and not(burst_ack_inhib);
-- needed during burst to fill
-- pipeline (1 clock) out of DPort
-- Block
DeadLock <= int_full and int_empty; -- both full and empty
-- at the same time
DP_core_rden <= not(int_empty)-- assert read enable when not
or Bus_rst; -- empty or during reset
DP_core_wren <= not(int_full) -- assert write enable when not
or Bus_rst; -- full or during reset
base_occupancy <= sig_normal_occupancy;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RDACK
--
-- Process Description:
-- Register the RdAck by one clock.
--
-------------------------------------------------------------
REG_RDACK : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
rdack_dly1 <= '0';
else
rdack_dly1 <= rdack_i;
end if;
else
null;
end if;
end process REG_RDACK;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_BKUP_RECOVER
--
-- Process Description:
-- This process generates a signal indicating the required
-- recovery cycle after a backup condition has occured.
--
-------------------------------------------------------------
GEN_BKUP_RECOVER : process (bus_clk)
begin
if (Bus_Clk'event and Bus_Clk = '1') then
if (Bus_Rst = '1') then
bkup_recover <= '0';
else
bkup_recover <= rd_backup;
end if;
else
null;
end if;
end process GEN_BKUP_RECOVER;
----------------------------------------------------------------------
-- Compensate for timing differences needed for Empty flag and
-- Occupancy outputs during single cycle reads and burst reads
-- No delay on single cycle reads
-- 1 clock delay during burst reads
dly_mux_in(0) <= int_empty;
dly_mux_in(1) <= int_almost_empty;
dly_mux_in(2 to DLY_MUX_WIDTH-1) <= sig_normal_occupancy;
I_DELAY_MUX : entity opb_ipif_v2_00_h.pf_dly1_mux
Generic map(C_MUX_WIDTH => DLY_MUX_WIDTH
)
port map(
Clk => Bus_clk,-- : in std_logic;
Rst => Bus_rst,-- : In std_logic;
dly_sel1 => '0', --burst_ack_inhib,-- : in std_logic;
dly_sel2 => back_to_back_rd,-- : in std_logic;
Inputs => dly_mux_in,-- : in std_logic_vector;
Y_out => dly_mux_out-- : out std_logic_vector
);
Empty <= dly_mux_out(0);
Almost_empty <= dly_mux_out(1);
Occupancy <= dly_mux_out(2 to DLY_MUX_WIDTH-1);
---------------------------------------------------------------------
------------------------------------------------------------------
-- Instantiate the Occupancy Counter relative to normal operations
-- This counter establishes the empty flag states.
------------------------------------------------------------------
inc_nocc_by_2 <= decr_rd_addr and inc_wr_addr;
inc_nocc <= decr_rd_addr or inc_wr_addr;
occ_load_value <= (others => '0');
I_NORMAL_OCCUPANCY : entity opb_ipif_v2_00_h.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => occ_load_value,
Count_Down => inc_rd_addr,
Count_Up => inc_nocc,
By_2 => inc_nocc_by_2,
Count_Out => sig_normal_occupancy,
almost_full => int_almost_full,
full => int_full,
almost_empty => int_almost_empty,
empty => int_empty
);
------------------------------------------------------------------
-- Register and delay Full/Empty flags
------------------------------------------------------------------
REGISTER_FLAG_PROCESS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
int_empty_dly1 <= '1';
int_almost_empty_dly1 <= '0';
int_rdack <= '0';
int_full_dly1 <= '0';
int_full_dly2 <= '0';
--sig_normal_occupancy_dly1 <= (others => '0');
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
int_empty_dly1 <= int_empty;
int_almost_empty_dly1 <= int_almost_empty;
int_rdack <= not(int_empty)
and not(rd_backup);
int_full_dly1 <= int_full;
int_full_dly2 <= int_full_dly1;
--sig_normal_occupancy_dly1 <= sig_normal_occupancy;
else
null;
End if;
End process; -- REGISTER_FLAG_PROCESS
------------------------------------------------------------------
-- Write Address Counter Logic
inc_wr_addr <= WrReq
and not(int_full)
and not(int_full_dly1)
and not(int_full_dly2);
sig_zeros <= (others => '0');
I_WRITE_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map (
C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => '0',
Count_Up => inc_wr_addr,
Count_Out => write_address
);
-- end of write counter logic
------------------------------------------------------------------
------------------------------------------------------------------
-- Read Address Counter Logic
---------------------------------------------------------------
-- Detect Back to back reads
---------------------------------------------------------------
BACK_TO_BACK_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
valid_read <= '0';
back_to_back_rd <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (inc_rd_addr = '1') Then
valid_read <= '1';
back_to_back_rd <= valid_read;
else
valid_read <= '0';
back_to_back_rd <= '0';
End if;
else
null;
End if;
End process; -- BACK_TO_BACK_DETECT
-- Must create a rdack inhibit the second clock into a burst
-- read to allow the data pipeline to catch up.
--
burst_ack_inhib <= RdReq
and valid_read
and not(back_to_back_rd) -- not yet detected a back to back
and rdack_dly1; -- must have ack'd a read one clock before
---------------------------------------------------------------
-- Register the IP Read Request for use in read counter backup
-- function
---------------------------------------------------------------
REG_READ_REQUEST : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rdreq_dly1 <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
rdreq_dly1 <= RdReq;
else
null;
End if;
End process; -- REG_READ_REQUEST
inc_rd_addr <= RdReq
And not(bkup_recover) -- DET added for
and not(int_empty)
and not(int_empty_dly1);
rd_backup <= not(RdReq)
And back_to_back_rd
-- DET Test fix for --And not(int_empty);
And not(int_empty_dly1);
decr_rd_addr <= rd_backup;
I_READ_ADDR_CNTR : entity opb_ipif_v2_00_h.pf_counter_top
Generic Map ( C_COUNT_WIDTH => ADDR_CNTR_WIDTH
)
Port Map (
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => '0',
Load_value => sig_zeros,
Count_Down => decr_rd_addr,
Count_Up => inc_rd_addr,
Count_Out => read_address
);
-- end read address counter logic
------------------------------------------------------------------
end generate OMIT_PACKET_FEATURES;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity opb_ipif_v2_00_h.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => base_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end implementation;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.15e-06,
W => Wdiff_0,
Wdiff_0init => 2.185e-05,
scope => private
)
port map(
D => net1,
G => in1,
S => net7
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.15e-06,
W => Wdiff_0,
Wdiff_0init => 2.185e-05,
scope => private
)
port map(
D => net2,
G => in2,
S => net7
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => W_0,
W_0init => 3.35e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.15e-06,
W => Wdiff_0,
Wdiff_0init => 2.185e-05,
scope => private
)
port map(
D => net8,
G => in1,
S => net7
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.15e-06,
W => Wdiff_0,
Wdiff_0init => 2.185e-05,
scope => private
)
port map(
D => net8,
G => in2,
S => net7
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.1e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.5e-07,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.1e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.5e-07,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.1e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.5e-07,
scope => private
)
port map(
D => net1,
G => net8,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.1e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5.5e-07,
scope => private
)
port map(
D => net2,
G => net8,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => L_2,
L_2init => 4.6e-06,
W => Wsrc_1,
Wsrc_1init => 2.87e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => L_3,
L_3init => 2.9e-06,
W => Wsrc_1,
Wsrc_1init => 2.87e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcm_2,
Wcm_2init => 1.245e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcmcout_2,
Wcmcout_2init => 3.63e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => C_4,
C_4init => 2.257e-12,
symmetry_scope => sym_4
)
port map(
P => net5,
N => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcm_2,
Wcm_2init => 1.245e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.5e-07,
W => Wcmcout_2,
Wcmcout_2init => 3.63e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net6,
G => net4,
S => gnd
);
subnet0_subnet4_c1 : entity cap(behave)
generic map(
C => C_5,
C_5init => 2.958e-12,
symmetry_scope => sym_4
)
port map(
P => net6,
N => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 1.185e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 6.31e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet0_subnet5_c1 : entity cap(behave)
generic map(
C => C_6,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net5
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 1.185e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet6_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 6.31e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net6,
S => vdd
);
subnet0_subnet6_c1 : entity cap(behave)
generic map(
C => C_7,
symmetry_scope => sym_5
)
port map(
P => out2,
N => net6
);
subnet0_subnet7_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => Wcursrc_4,
Wcursrc_4init => 2.67e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet8_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => Wcursrc_4,
Wcursrc_4init => 2.67e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net9,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net12,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net11,
N => net9
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => W_1,
W_1init => 4.285e-05
)
port map(
D => net10,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.105e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 4.57e-05,
scope => private
)
port map(
D => net12,
G => vref,
S => net10
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.105e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 4.57e-05,
scope => private
)
port map(
D => net11,
G => net9,
S => net10
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 4.25e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1e-06,
scope => private
)
port map(
D => net11,
G => net11,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 4.25e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1e-06,
scope => private
)
port map(
D => net12,
G => net11,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 2.6e-06,
W => Wcmbias_0,
Wcmbias_0init => 4.725e-05,
scope => private
)
port map(
D => out1,
G => net12,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 2.6e-06,
W => Wcmbias_0,
Wcmbias_0init => 4.725e-05,
scope => private
)
port map(
D => out2,
G => net12,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => (pfak)*(WBias),
WBiasinit => 4.45e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.3e-06,
W => (pfak)*(WBias),
WBiasinit => 4.45e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.3e-06,
W => WBias,
WBiasinit => 4.45e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => WBias,
WBiasinit => 4.45e-05
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => WBias,
WBiasinit => 4.45e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.3e-06,
W => WBias,
WBiasinit => 4.45e-05
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--USE ieee.numeric_std.ALL;
ENTITY tb_controller IS
END tb_controller;
ARCHITECTURE behavior OF tb_controller IS
--Inputs
SIGNAL tb_opcode : std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_regDst : std_logic;
SIGNAL tb_jump : std_logic;
SIGNAL tb_branch : std_logic;
SIGNAL tb_memRead : std_logic;
SIGNAL tb_memToRegister : std_logic;
SIGNAL tb_ALUop : std_logic_vector(1 DOWNTO 0);
SIGNAL tb_memWrite : std_logic;
SIGNAL tb_ALUsrc : std_logic;
SIGNAL tb_regWrite : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
U1_Test : ENTITY work.Controller(Behavioral)
PORT MAP(
opcode => tb_opcode,
regDst => tb_regDst,
jump => tb_jump,
branch => tb_branch,
memRead => tb_memRead,
memToRegister => tb_memToRegister,
ALUop => tb_ALUop,
memWrite => tb_memWrite,
ALUsrc => tb_ALUsrc,
regWrite => tb_regWrite
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
tb_opcode <= "000000"; --R-type
WAIT FOR 50 ns;
tb_opcode <= "100011"; --load word
WAIT FOR 50 ns;
tb_opcode <= "101011"; --store word
WAIT FOR 50 ns;
tb_opcode <= "000100"; --breanh equal
WAIT FOR 50 ns;
tb_opcode <= "000010"; --jump
WAIT FOR 50 ns;
tb_opcode <= "111111"; --unknown
WAIT FOR 50 ns;
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; |
-- $Id: rlink_cext_vhpi.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: rlink_cext_vhpi
-- Description: VHDL procedural interface: VHDL declaration side
--
-- Dependencies: -
-- Tool versions: ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-29 351 1.1 rename vhpi_rriext->rlink_cext_vhpi; new rbv3 names
-- 2007-08-26 76 1.0 Initial version
------------------------------------------------------------------------------
package rlink_cext_vhpi is
impure function rlink_cext_getbyte (
clk : integer) -- clock cycle
return integer;
attribute foreign of rlink_cext_getbyte :
function is "VHPIDIRECT rlink_cext_getbyte";
impure function rlink_cext_putbyte (
dat : integer) -- data byte
return integer;
attribute foreign of rlink_cext_putbyte :
function is "VHPIDIRECT rlink_cext_putbyte";
end package rlink_cext_vhpi;
package body rlink_cext_vhpi is
impure function rlink_cext_getbyte (
clk : integer) -- clock cycle
return integer is
begin
report "rlink_cext_getbyte not vhpi'ed" severity failure;
end rlink_cext_getbyte;
impure function rlink_cext_putbyte (
dat : integer) -- data byte
return integer is
begin
report "rlink_cext_getbyte not vhpi'ed" severity failure;
end rlink_cext_putbyte;
end package body rlink_cext_vhpi;
|
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap;
use axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap ;
use axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_CACHE_USER : integer range 0 to 1 := 0;
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0;
C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_CMD_WIDTH : integer range 72 to 112 := 72;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_datamover;
architecture implementation of axi_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
function funct_fix_addr (in_addr_width : integer) return integer is
Variable new_addr_width : Integer;
begin
If (in_addr_width <= 32) Then
new_addr_width := 32;
elsif (in_addr_width > 32 and in_addr_width <= 40) Then
new_addr_width := 40;
elsif (in_addr_width > 40 and in_addr_width <= 48) Then
new_addr_width := 48;
elsif (in_addr_width > 48 and in_addr_width <= 56) Then
new_addr_width := 56;
else
new_addr_width := 64;
End if;
Return (new_addr_width);
end function funct_fix_addr;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH);
constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ;
signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ;
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
end generate GEN_MM2S_TKEEP_ENABLE1;
GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
m_axis_mm2s_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE1;
GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
end generate GEN_S2MM_TKEEP_ENABLE1;
GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_s2mm_tstrb <= (others => '1');
end generate GEN_S2MM_TKEEP_DISABLE1;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_OMIT
--
-- If Generate Description:
-- Instantiate the MM2S OMIT Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_OMIT_WRAPPER
--
-- Description:
-- Read omit Wrapper Instance
--
------------------------------------------------------------
I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_FULL
--
-- If Generate Description:
-- Instantiate the MM2S Full Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_FULL_WRAPPER
--
-- Description:
-- Read Full Wrapper Instance
--
------------------------------------------------------------
I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr_int ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_OMIT
--
-- If Generate Description:
-- Instantiate the S2MM OMIT Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_OMIT_WRAPPER
--
-- Description:
-- Write Omit Wrapper Instance
--
------------------------------------------------------------
I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_OMIT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_FULL
--
-- If Generate Description:
-- Instantiate the S2MM FULL Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_FULL_WRAPPER
--
-- Description:
-- Write Full Wrapper Instance
--
------------------------------------------------------------
I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED ,
C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr_int ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0);
m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0);
end implementation;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--
-- ZPUINO implementation on Gadget Factory 'Papilio One' Board
--
-- Copyright 2010 Alvaro Lopes <[email protected]>
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library zpuino;
use zpuino.pad.all;
use zpuino.papilio_pkg.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
use board.zpuinopkg.all;
library unisim;
use unisim.vcomponents.all;
entity ZPUino_Papilio_One_V1 is
port (
--32Mhz input clock is converted to a 96Mhz clock
CLK: in std_logic;
--RST: in std_logic; -- No reset on papilio
--Clock outputs to be used in schematic
clk_96Mhz: out std_logic; --This is the clock that the system runs on.
clk_1Mhz: out std_logic; --This is a 1Mhz clock for symbols like the C64 SID chip.
clk_osc_32Mhz: out std_logic; --This is the 32Mhz clock from external oscillator.
-- Connection to the main SPI flash
SPI_FLASH_SCK: out std_logic;
SPI_FLASH_MISO: in std_logic;
SPI_FLASH_MOSI: out std_logic;
SPI_FLASH_CS: inout std_logic;
gpio_bus_in : in std_logic_vector(97 downto 0);
gpio_bus_out : out std_logic_vector(147 downto 0);
-- UART (FTDI) connection
TXD: out std_logic;
RXD: in std_logic;
--There are more bits in the address for this wishbone connection
wishbone_slot_video_in : in std_logic_vector(63 downto 0);
wishbone_slot_video_out : out std_logic_vector(33 downto 0);
vgaclkout: out std_logic;
-- Unfortunately the Xilinx Schematic Editor does not support records, so we have to put all wishbone signals into one array.
-- This is a little cumbersome but is better then dealing with all the signals in the schematic editor.
-- This is what the original record base approach looked like:
--
-- type wishbone_bus_in_type is record
-- wb_clk_i: std_logic; -- Wishbone clock
-- wb_rst_i: std_logic; -- Wishbone reset (synchronous)
-- wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
-- wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
-- wb_we_i: std_logic; -- Wishbone write enable signal
-- wb_cyc_i: std_logic; -- Wishbone cycle signal
-- wb_stb_i: std_logic; -- Wishbone strobe signal
-- end record;
--
-- type wishbone_bus_out_type is record
-- wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
-- wb_ack_o: std_logic; -- Wishbone acknowledge out signal
-- wb_inta_o: std_logic;
-- end record;
--
-- Turning them into an array looks like this:
--
-- wishbone_in : in std_logic_vector(61 downto 0);
--
-- wishbone_in_record.wb_clk_i <= wishbone_in(61);
-- wishbone_in_record.wb_rst_i <= wishbone_in(60);
-- wishbone_in_record.wb_dat_i <= wishbone_in(59 downto 28);
-- wishbone_in_record.wb_adr_i <= wishbone_in(27 downto 3);
-- wishbone_in_record.wb_we_i <= wishbone_in(2);
-- wishbone_in_record.wb_cyc_i <= wishbone_in(1);
-- wishbone_in_record.wb_stb_i <= wishbone_in(0);
--
-- wishbone_out : out std_logic_vector(33 downto 0);
--
-- wishbone_out(33 downto 2) <= wishbone_out_record.wb_dat_o;
-- wishbone_out(1) <= wishbone_out_record.wb_ack_o;
-- wishbone_out(0) <= wishbone_out_record.wb_inta_o;
--Input and output reversed for the master
wishbone_slot_5_in : out std_logic_vector(61 downto 0);
wishbone_slot_5_out : in std_logic_vector(33 downto 0);
wishbone_slot_6_in : out std_logic_vector(61 downto 0);
wishbone_slot_6_out : in std_logic_vector(33 downto 0);
wishbone_slot_8_in : out std_logic_vector(61 downto 0);
wishbone_slot_8_out : in std_logic_vector(33 downto 0);
wishbone_slot_9_in : out std_logic_vector(61 downto 0);
wishbone_slot_9_out : in std_logic_vector(33 downto 0);
wishbone_slot_10_in : out std_logic_vector(61 downto 0);
wishbone_slot_10_out : in std_logic_vector(33 downto 0);
wishbone_slot_11_in : out std_logic_vector(61 downto 0);
wishbone_slot_11_out : in std_logic_vector(33 downto 0);
wishbone_slot_12_in : out std_logic_vector(61 downto 0);
wishbone_slot_12_out : in std_logic_vector(33 downto 0);
wishbone_slot_13_in : out std_logic_vector(61 downto 0);
wishbone_slot_13_out : in std_logic_vector(33 downto 0);
wishbone_slot_14_in : out std_logic_vector(61 downto 0);
wishbone_slot_14_out : in std_logic_vector(33 downto 0);
wishbone_slot_15_in : out std_logic_vector(61 downto 0);
wishbone_slot_15_out : in std_logic_vector(33 downto 0)
);
-- attribute LOC: string;
-- attribute LOC of CLK: signal is "P89";
-- attribute LOC of RXD: signal is "P88";
-- attribute LOC of TXD: signal is "P90";
-- attribute LOC of SPI_FLASH_CS: signal is "P24";
-- attribute LOC of SPI_FLASH_SCK: signal is "P50";
-- attribute LOC of SPI_FLASH_MISO: signal is "P44";
-- attribute LOC of SPI_FLASH_MOSI: signal is "P27";
--
-- attribute IOSTANDARD: string;
-- attribute IOSTANDARD of CLK: signal is "LVCMOS33";
-- attribute IOSTANDARD of RXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of TXD: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_CS: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_SCK: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MISO: signal is "LVCMOS33";
-- attribute IOSTANDARD of SPI_FLASH_MOSI: signal is "LVCMOS33";
--
-- attribute PERIOD: string;
-- attribute PERIOD of CLK: signal is "31.00ns";
end entity ZPUino_Papilio_One_V1;
architecture behave of ZPUino_Papilio_One_V1 is
component clkgen is
port (
clkin: in std_logic;
rstin: in std_logic;
clkout: out std_logic;
clkout_1mhz: out std_logic;
clk_osc_32Mhz: out std_logic;
vgaclkout: out std_logic;
rstout: out std_logic
);
end component clkgen;
component zpuino_serialreset is
generic (
SYSTEM_CLOCK_MHZ: integer := 96
);
port (
clk: in std_logic;
rx: in std_logic;
rstin: in std_logic;
rstout: out std_logic
);
end component zpuino_serialreset;
signal sysrst: std_logic;
signal sysclk: std_logic;
signal sysclk_1mhz: std_logic;
signal dbg_reset: std_logic;
signal clkgen_rst: std_logic;
signal gpio_o_reg: std_logic_vector(zpuino_gpio_count-1 downto 0);
signal rx: std_logic;
signal tx: std_logic;
constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
"0" &
"0000000000000000" &
"0000000000000000" &
"0000000000000000";
-- constant spp_cap_in: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- constant spp_cap_out: std_logic_vector(zpuino_gpio_count-1 downto 0) :=
-- "0" &
-- "1111111111111111" &
-- "1111111111111111" &
-- "1111111111111111";
-- I/O Signals
signal slot_cyc: slot_std_logic_type;
signal slot_we: slot_std_logic_type;
signal slot_stb: slot_std_logic_type;
signal slot_read: slot_cpuword_type;
signal slot_write: slot_cpuword_type;
signal slot_address: slot_address_type;
signal slot_ack: slot_std_logic_type;
signal slot_interrupt: slot_std_logic_type;
signal spi_enabled: std_logic;
signal uart_enabled: std_logic;
signal timers_interrupt: std_logic_vector(1 downto 0);
signal timers_pwm: std_logic_vector(1 downto 0);
signal ivecs, sigmadelta_raw: std_logic_vector(17 downto 0);
signal sigmadelta_spp_en: std_logic_vector(1 downto 0);
signal sigmadelta_spp_data: std_logic_vector(1 downto 0);
-- For busy-implementation
signal addr_save_q: std_logic_vector(maxAddrBitIncIO downto 0);
signal write_save_q: std_logic_vector(wordSize-1 downto 0);
signal spi_pf_miso: std_logic;
signal spi_pf_mosi: std_logic;
signal spi_pf_sck: std_logic;
signal adc_mosi: std_logic;
signal adc_miso: std_logic;
signal adc_sck: std_logic;
signal adc_seln: std_logic;
signal adc_enabled: std_logic;
signal wb_clk_i: std_logic;
signal wb_rst_i: std_logic;
signal uart2_tx, uart2_rx: std_logic;
signal jtag_data_chain_out: std_logic_vector(98 downto 0);
signal jtag_ctrl_chain_in: std_logic_vector(11 downto 0);
signal wishbone_slot_video_in_record : wishbone_bus_in_type;
signal wishbone_slot_video_out_record : wishbone_bus_out_type;
signal wishbone_slot_5_in_record : wishbone_bus_in_type;
signal wishbone_slot_5_out_record : wishbone_bus_out_type;
signal wishbone_slot_6_in_record : wishbone_bus_in_type;
signal wishbone_slot_6_out_record : wishbone_bus_out_type;
signal wishbone_slot_8_in_record : wishbone_bus_in_type;
signal wishbone_slot_8_out_record : wishbone_bus_out_type;
signal wishbone_slot_9_in_record : wishbone_bus_in_type;
signal wishbone_slot_9_out_record : wishbone_bus_out_type;
signal wishbone_slot_10_in_record : wishbone_bus_in_type;
signal wishbone_slot_10_out_record : wishbone_bus_out_type;
signal wishbone_slot_11_in_record : wishbone_bus_in_type;
signal wishbone_slot_11_out_record : wishbone_bus_out_type;
signal wishbone_slot_12_in_record : wishbone_bus_in_type;
signal wishbone_slot_12_out_record : wishbone_bus_out_type;
signal wishbone_slot_13_in_record : wishbone_bus_in_type;
signal wishbone_slot_13_out_record : wishbone_bus_out_type;
signal wishbone_slot_14_in_record : wishbone_bus_in_type;
signal wishbone_slot_14_out_record : wishbone_bus_out_type;
signal wishbone_slot_15_in_record : wishbone_bus_in_type;
signal wishbone_slot_15_out_record : wishbone_bus_out_type;
signal gpio_bus_in_record : gpio_bus_in_type;
signal gpio_bus_out_record : gpio_bus_out_type;
component zpuino_debug_spartan3e is
port (
TCK: out std_logic;
TDI: out std_logic;
CAPTUREIR: out std_logic;
UPDATEIR: out std_logic;
SHIFTIR: out std_logic;
CAPTUREDR: out std_logic;
UPDATEDR: out std_logic;
SHIFTDR: out std_logic;
TLR: out std_logic;
TDO_IR: in std_logic;
TDO_DR: in std_logic
);
end component;
begin
-- Unpack the wishbone array into a record so the modules code is not confusing.
-- These are backwards for the master.
-- wishbone_slot_video_in_record.wb_clk_i <= wishbone_slot_video_in(61);
-- wishbone_slot_video_in_record.wb_rst_i <= wishbone_slot_video_in(60);
-- wishbone_slot_video_in_record.wb_dat_i <= wishbone_slot_video_in(59 downto 28);
-- wishbone_slot_video_in_record.wb_adr_i <= wishbone_slot_video_in(27 downto 3);
-- wishbone_slot_video_in_record.wb_we_i <= wishbone_slot_video_in(2);
-- wishbone_slot_video_in_record.wb_cyc_i <= wishbone_slot_video_in(1);
-- wishbone_slot_video_in_record.wb_stb_i <= wishbone_slot_video_in(0);
-- wishbone_slot_video_out(33 downto 2) <= wishbone_slot_video_out_record.wb_dat_o;
-- wishbone_slot_video_out(1) <= wishbone_slot_video_out_record.wb_ack_o;
-- wishbone_slot_video_out(0) <= wishbone_slot_video_out_record.wb_inta_o;
wishbone_slot_5_in(61) <= wishbone_slot_5_in_record.wb_clk_i;
wishbone_slot_5_in(60) <= wishbone_slot_5_in_record.wb_rst_i;
wishbone_slot_5_in(59 downto 28) <= wishbone_slot_5_in_record.wb_dat_i;
wishbone_slot_5_in(27 downto 3) <= wishbone_slot_5_in_record.wb_adr_i;
wishbone_slot_5_in(2) <= wishbone_slot_5_in_record.wb_we_i;
wishbone_slot_5_in(1) <= wishbone_slot_5_in_record.wb_cyc_i;
wishbone_slot_5_in(0) <= wishbone_slot_5_in_record.wb_stb_i;
wishbone_slot_5_out_record.wb_dat_o <= wishbone_slot_5_out(33 downto 2);
wishbone_slot_5_out_record.wb_ack_o <= wishbone_slot_5_out(1);
wishbone_slot_5_out_record.wb_inta_o <= wishbone_slot_5_out(0);
wishbone_slot_6_in(61) <= wishbone_slot_6_in_record.wb_clk_i;
wishbone_slot_6_in(60) <= wishbone_slot_6_in_record.wb_rst_i;
wishbone_slot_6_in(59 downto 28) <= wishbone_slot_6_in_record.wb_dat_i;
wishbone_slot_6_in(27 downto 3) <= wishbone_slot_6_in_record.wb_adr_i;
wishbone_slot_6_in(2) <= wishbone_slot_6_in_record.wb_we_i;
wishbone_slot_6_in(1) <= wishbone_slot_6_in_record.wb_cyc_i;
wishbone_slot_6_in(0) <= wishbone_slot_6_in_record.wb_stb_i;
wishbone_slot_6_out_record.wb_dat_o <= wishbone_slot_6_out(33 downto 2);
wishbone_slot_6_out_record.wb_ack_o <= wishbone_slot_6_out(1);
wishbone_slot_6_out_record.wb_inta_o <= wishbone_slot_6_out(0);
wishbone_slot_8_in(61) <= wishbone_slot_8_in_record.wb_clk_i;
wishbone_slot_8_in(60) <= wishbone_slot_8_in_record.wb_rst_i;
wishbone_slot_8_in(59 downto 28) <= wishbone_slot_8_in_record.wb_dat_i;
wishbone_slot_8_in(27 downto 3) <= wishbone_slot_8_in_record.wb_adr_i;
wishbone_slot_8_in(2) <= wishbone_slot_8_in_record.wb_we_i;
wishbone_slot_8_in(1) <= wishbone_slot_8_in_record.wb_cyc_i;
wishbone_slot_8_in(0) <= wishbone_slot_8_in_record.wb_stb_i;
wishbone_slot_8_out_record.wb_dat_o <= wishbone_slot_8_out(33 downto 2);
wishbone_slot_8_out_record.wb_ack_o <= wishbone_slot_8_out(1);
wishbone_slot_8_out_record.wb_inta_o <= wishbone_slot_8_out(0);
wishbone_slot_9_in(61) <= wishbone_slot_9_in_record.wb_clk_i;
wishbone_slot_9_in(60) <= wishbone_slot_9_in_record.wb_rst_i;
wishbone_slot_9_in(59 downto 28) <= wishbone_slot_9_in_record.wb_dat_i;
wishbone_slot_9_in(27 downto 3) <= wishbone_slot_9_in_record.wb_adr_i;
wishbone_slot_9_in(2) <= wishbone_slot_9_in_record.wb_we_i;
wishbone_slot_9_in(1) <= wishbone_slot_9_in_record.wb_cyc_i;
wishbone_slot_9_in(0) <= wishbone_slot_9_in_record.wb_stb_i;
wishbone_slot_9_out_record.wb_dat_o <= wishbone_slot_9_out(33 downto 2);
wishbone_slot_9_out_record.wb_ack_o <= wishbone_slot_9_out(1);
wishbone_slot_9_out_record.wb_inta_o <= wishbone_slot_9_out(0);
wishbone_slot_10_in(61) <= wishbone_slot_10_in_record.wb_clk_i;
wishbone_slot_10_in(60) <= wishbone_slot_10_in_record.wb_rst_i;
wishbone_slot_10_in(59 downto 28) <= wishbone_slot_10_in_record.wb_dat_i;
wishbone_slot_10_in(27 downto 3) <= wishbone_slot_10_in_record.wb_adr_i;
wishbone_slot_10_in(2) <= wishbone_slot_10_in_record.wb_we_i;
wishbone_slot_10_in(1) <= wishbone_slot_10_in_record.wb_cyc_i;
wishbone_slot_10_in(0) <= wishbone_slot_10_in_record.wb_stb_i;
wishbone_slot_10_out_record.wb_dat_o <= wishbone_slot_10_out(33 downto 2);
wishbone_slot_10_out_record.wb_ack_o <= wishbone_slot_10_out(1);
wishbone_slot_10_out_record.wb_inta_o <= wishbone_slot_10_out(0);
wishbone_slot_11_in(61) <= wishbone_slot_11_in_record.wb_clk_i;
wishbone_slot_11_in(60) <= wishbone_slot_11_in_record.wb_rst_i;
wishbone_slot_11_in(59 downto 28) <= wishbone_slot_11_in_record.wb_dat_i;
wishbone_slot_11_in(27 downto 3) <= wishbone_slot_11_in_record.wb_adr_i;
wishbone_slot_11_in(2) <= wishbone_slot_11_in_record.wb_we_i;
wishbone_slot_11_in(1) <= wishbone_slot_11_in_record.wb_cyc_i;
wishbone_slot_11_in(0) <= wishbone_slot_11_in_record.wb_stb_i;
wishbone_slot_11_out_record.wb_dat_o <= wishbone_slot_11_out(33 downto 2);
wishbone_slot_11_out_record.wb_ack_o <= wishbone_slot_11_out(1);
wishbone_slot_11_out_record.wb_inta_o <= wishbone_slot_11_out(0);
wishbone_slot_12_in(61) <= wishbone_slot_12_in_record.wb_clk_i;
wishbone_slot_12_in(60) <= wishbone_slot_12_in_record.wb_rst_i;
wishbone_slot_12_in(59 downto 28) <= wishbone_slot_12_in_record.wb_dat_i;
wishbone_slot_12_in(27 downto 3) <= wishbone_slot_12_in_record.wb_adr_i;
wishbone_slot_12_in(2) <= wishbone_slot_12_in_record.wb_we_i;
wishbone_slot_12_in(1) <= wishbone_slot_12_in_record.wb_cyc_i;
wishbone_slot_12_in(0) <= wishbone_slot_12_in_record.wb_stb_i;
wishbone_slot_12_out_record.wb_dat_o <= wishbone_slot_12_out(33 downto 2);
wishbone_slot_12_out_record.wb_ack_o <= wishbone_slot_12_out(1);
wishbone_slot_12_out_record.wb_inta_o <= wishbone_slot_12_out(0);
wishbone_slot_13_in(61) <= wishbone_slot_13_in_record.wb_clk_i;
wishbone_slot_13_in(60) <= wishbone_slot_13_in_record.wb_rst_i;
wishbone_slot_13_in(59 downto 28) <= wishbone_slot_13_in_record.wb_dat_i;
wishbone_slot_13_in(27 downto 3) <= wishbone_slot_13_in_record.wb_adr_i;
wishbone_slot_13_in(2) <= wishbone_slot_13_in_record.wb_we_i;
wishbone_slot_13_in(1) <= wishbone_slot_13_in_record.wb_cyc_i;
wishbone_slot_13_in(0) <= wishbone_slot_13_in_record.wb_stb_i;
wishbone_slot_13_out_record.wb_dat_o <= wishbone_slot_13_out(33 downto 2);
wishbone_slot_13_out_record.wb_ack_o <= wishbone_slot_13_out(1);
wishbone_slot_13_out_record.wb_inta_o <= wishbone_slot_13_out(0);
wishbone_slot_14_in(61) <= wishbone_slot_14_in_record.wb_clk_i;
wishbone_slot_14_in(60) <= wishbone_slot_14_in_record.wb_rst_i;
wishbone_slot_14_in(59 downto 28) <= wishbone_slot_14_in_record.wb_dat_i;
wishbone_slot_14_in(27 downto 3) <= wishbone_slot_14_in_record.wb_adr_i;
wishbone_slot_14_in(2) <= wishbone_slot_14_in_record.wb_we_i;
wishbone_slot_14_in(1) <= wishbone_slot_14_in_record.wb_cyc_i;
wishbone_slot_14_in(0) <= wishbone_slot_14_in_record.wb_stb_i;
wishbone_slot_14_out_record.wb_dat_o <= wishbone_slot_14_out(33 downto 2);
wishbone_slot_14_out_record.wb_ack_o <= wishbone_slot_14_out(1);
wishbone_slot_14_out_record.wb_inta_o <= wishbone_slot_14_out(0);
wishbone_slot_15_in(61) <= wishbone_slot_15_in_record.wb_clk_i;
wishbone_slot_15_in(60) <= wishbone_slot_15_in_record.wb_rst_i;
wishbone_slot_15_in(59 downto 28) <= wishbone_slot_15_in_record.wb_dat_i;
wishbone_slot_15_in(27 downto 3) <= wishbone_slot_15_in_record.wb_adr_i;
wishbone_slot_15_in(2) <= wishbone_slot_15_in_record.wb_we_i;
wishbone_slot_15_in(1) <= wishbone_slot_15_in_record.wb_cyc_i;
wishbone_slot_15_in(0) <= wishbone_slot_15_in_record.wb_stb_i;
wishbone_slot_15_out_record.wb_dat_o <= wishbone_slot_15_out(33 downto 2);
wishbone_slot_15_out_record.wb_ack_o <= wishbone_slot_15_out(1);
wishbone_slot_15_out_record.wb_inta_o <= wishbone_slot_15_out(0);
gpio_bus_in_record.gpio_spp_data <= gpio_bus_in(97 downto 49);
gpio_bus_in_record.gpio_i <= gpio_bus_in(48 downto 0);
gpio_bus_out(147) <= gpio_bus_out_record.gpio_clk;
gpio_bus_out(146 downto 98) <= gpio_bus_out_record.gpio_o;
gpio_bus_out(97 downto 49) <= gpio_bus_out_record.gpio_t;
gpio_bus_out(48 downto 0) <= gpio_bus_out_record.gpio_spp_read;
gpio_bus_out_record.gpio_o <= gpio_o_reg;
gpio_bus_out_record.gpio_clk <= sysclk;
wb_clk_i <= sysclk;
wb_rst_i <= sysrst;
--Wishbone 5
wishbone_slot_5_in_record.wb_clk_i <= sysclk;
wishbone_slot_5_in_record.wb_rst_i <= sysrst;
slot_read(5) <= wishbone_slot_5_out_record.wb_dat_o;
wishbone_slot_5_in_record.wb_dat_i <= slot_write(5);
wishbone_slot_5_in_record.wb_adr_i <= slot_address(5);
wishbone_slot_5_in_record.wb_we_i <= slot_we(5);
wishbone_slot_5_in_record.wb_cyc_i <= slot_cyc(5);
wishbone_slot_5_in_record.wb_stb_i <= slot_stb(5);
slot_ack(5) <= wishbone_slot_5_out_record.wb_ack_o;
slot_interrupt(5) <= wishbone_slot_5_out_record.wb_inta_o;
--Wishbone 6
wishbone_slot_6_in_record.wb_clk_i <= sysclk;
wishbone_slot_6_in_record.wb_rst_i <= sysrst;
slot_read(6) <= wishbone_slot_6_out_record.wb_dat_o;
wishbone_slot_6_in_record.wb_dat_i <= slot_write(6);
wishbone_slot_6_in_record.wb_adr_i <= slot_address(6);
wishbone_slot_6_in_record.wb_we_i <= slot_we(6);
wishbone_slot_6_in_record.wb_cyc_i <= slot_cyc(6);
wishbone_slot_6_in_record.wb_stb_i <= slot_stb(6);
slot_ack(6) <= wishbone_slot_6_out_record.wb_ack_o;
slot_interrupt(6) <= wishbone_slot_6_out_record.wb_inta_o;
--Wishbone 8
wishbone_slot_8_in_record.wb_clk_i <= sysclk;
wishbone_slot_8_in_record.wb_rst_i <= sysrst;
slot_read(8) <= wishbone_slot_8_out_record.wb_dat_o;
wishbone_slot_8_in_record.wb_dat_i <= slot_write(8);
wishbone_slot_8_in_record.wb_adr_i <= slot_address(8);
wishbone_slot_8_in_record.wb_we_i <= slot_we(8);
wishbone_slot_8_in_record.wb_cyc_i <= slot_cyc(8);
wishbone_slot_8_in_record.wb_stb_i <= slot_stb(8);
slot_ack(8) <= wishbone_slot_8_out_record.wb_ack_o;
slot_interrupt(8) <= wishbone_slot_8_out_record.wb_inta_o;
--Wishbone 9
wishbone_slot_9_in_record.wb_clk_i <= sysclk;
wishbone_slot_9_in_record.wb_rst_i <= sysrst;
slot_read(9) <= wishbone_slot_9_out_record.wb_dat_o;
wishbone_slot_9_in_record.wb_dat_i <= slot_write(9);
wishbone_slot_9_in_record.wb_adr_i <= slot_address(9);
wishbone_slot_9_in_record.wb_we_i <= slot_we(9);
wishbone_slot_9_in_record.wb_cyc_i <= slot_cyc(9);
wishbone_slot_9_in_record.wb_stb_i <= slot_stb(9);
slot_ack(9) <= wishbone_slot_9_out_record.wb_ack_o;
slot_interrupt(9) <= wishbone_slot_9_out_record.wb_inta_o;
--Wishbone 10
wishbone_slot_10_in_record.wb_clk_i <= sysclk;
wishbone_slot_10_in_record.wb_rst_i <= sysrst;
slot_read(10) <= wishbone_slot_10_out_record.wb_dat_o;
wishbone_slot_10_in_record.wb_dat_i <= slot_write(10);
wishbone_slot_10_in_record.wb_adr_i <= slot_address(10);
wishbone_slot_10_in_record.wb_we_i <= slot_we(10);
wishbone_slot_10_in_record.wb_cyc_i <= slot_cyc(10);
wishbone_slot_10_in_record.wb_stb_i <= slot_stb(10);
slot_ack(10) <= wishbone_slot_10_out_record.wb_ack_o;
slot_interrupt(10) <= wishbone_slot_10_out_record.wb_inta_o;
--Wishbone 11
wishbone_slot_11_in_record.wb_clk_i <= sysclk;
wishbone_slot_11_in_record.wb_rst_i <= sysrst;
slot_read(11) <= wishbone_slot_11_out_record.wb_dat_o;
wishbone_slot_11_in_record.wb_dat_i <= slot_write(11);
wishbone_slot_11_in_record.wb_adr_i <= slot_address(11);
wishbone_slot_11_in_record.wb_we_i <= slot_we(11);
wishbone_slot_11_in_record.wb_cyc_i <= slot_cyc(11);
wishbone_slot_11_in_record.wb_stb_i <= slot_stb(11);
slot_ack(11) <= wishbone_slot_11_out_record.wb_ack_o;
slot_interrupt(11) <= wishbone_slot_11_out_record.wb_inta_o;
--Wishbone 12
wishbone_slot_12_in_record.wb_clk_i <= sysclk;
wishbone_slot_12_in_record.wb_rst_i <= sysrst;
slot_read(12) <= wishbone_slot_12_out_record.wb_dat_o;
wishbone_slot_12_in_record.wb_dat_i <= slot_write(12);
wishbone_slot_12_in_record.wb_adr_i <= slot_address(12);
wishbone_slot_12_in_record.wb_we_i <= slot_we(12);
wishbone_slot_12_in_record.wb_cyc_i <= slot_cyc(12);
wishbone_slot_12_in_record.wb_stb_i <= slot_stb(12);
slot_ack(12) <= wishbone_slot_12_out_record.wb_ack_o;
slot_interrupt(12) <= wishbone_slot_12_out_record.wb_inta_o;
--Wishbone 13
wishbone_slot_13_in_record.wb_clk_i <= sysclk;
wishbone_slot_13_in_record.wb_rst_i <= sysrst;
slot_read(13) <= wishbone_slot_13_out_record.wb_dat_o;
wishbone_slot_13_in_record.wb_dat_i <= slot_write(13);
wishbone_slot_13_in_record.wb_adr_i <= slot_address(13);
wishbone_slot_13_in_record.wb_we_i <= slot_we(13);
wishbone_slot_13_in_record.wb_cyc_i <= slot_cyc(13);
wishbone_slot_13_in_record.wb_stb_i <= slot_stb(13);
slot_ack(13) <= wishbone_slot_13_out_record.wb_ack_o;
slot_interrupt(13) <= wishbone_slot_13_out_record.wb_inta_o;
--Wishbone 14
wishbone_slot_14_in_record.wb_clk_i <= sysclk;
wishbone_slot_14_in_record.wb_rst_i <= sysrst;
slot_read(14) <= wishbone_slot_14_out_record.wb_dat_o;
wishbone_slot_14_in_record.wb_dat_i <= slot_write(14);
wishbone_slot_14_in_record.wb_adr_i <= slot_address(14);
wishbone_slot_14_in_record.wb_we_i <= slot_we(14);
wishbone_slot_14_in_record.wb_cyc_i <= slot_cyc(14);
wishbone_slot_14_in_record.wb_stb_i <= slot_stb(14);
slot_ack(14) <= wishbone_slot_14_out_record.wb_ack_o;
slot_interrupt(14) <= wishbone_slot_14_out_record.wb_inta_o;
--Wishbone 15
wishbone_slot_15_in_record.wb_clk_i <= sysclk;
wishbone_slot_15_in_record.wb_rst_i <= sysrst;
slot_read(15) <= wishbone_slot_15_out_record.wb_dat_o;
wishbone_slot_15_in_record.wb_dat_i <= slot_write(15);
wishbone_slot_15_in_record.wb_adr_i <= slot_address(15);
wishbone_slot_15_in_record.wb_we_i <= slot_we(15);
wishbone_slot_15_in_record.wb_cyc_i <= slot_cyc(15);
wishbone_slot_15_in_record.wb_stb_i <= slot_stb(15);
slot_ack(15) <= wishbone_slot_15_out_record.wb_ack_o;
slot_interrupt(15) <= wishbone_slot_15_out_record.wb_inta_o;
rstgen: zpuino_serialreset
generic map (
SYSTEM_CLOCK_MHZ => 96
)
port map (
clk => sysclk,
rx => rx,
rstin => clkgen_rst,
rstout => sysrst
);
--sysrst <= clkgen_rst;
clkgen_inst: clkgen
port map (
clkin => clk,
rstin => dbg_reset,
clkout => sysclk,
vgaclkout => vgaclkout,
clkout_1mhz => clk_1Mhz,
clk_osc_32Mhz => clk_osc_32Mhz,
rstout => clkgen_rst
);
clk_96Mhz <= sysclk;
zpuino:zpuino_top
port map (
clk => sysclk,
rst => sysrst,
slot_cyc => slot_cyc,
slot_we => slot_we,
slot_stb => slot_stb,
slot_read => slot_read,
slot_write => slot_write,
slot_address => slot_address,
slot_ack => slot_ack,
slot_interrupt=> slot_interrupt,
--Be careful the order for this is different then the other wishbone bus connections.
--The address array is bigger so we moved the single signals to the top of the array.
m_wb_dat_o => wishbone_slot_video_out(33 downto 2),
m_wb_dat_i => wishbone_slot_video_in(59 downto 28),
m_wb_adr_i => wishbone_slot_video_in(27 downto 0),
m_wb_we_i => wishbone_slot_video_in(62),
m_wb_cyc_i => wishbone_slot_video_in(61),
m_wb_stb_i => wishbone_slot_video_in(60),
m_wb_ack_o => wishbone_slot_video_out(1),
dbg_reset => dbg_reset,
jtag_data_chain_out => open,--jtag_data_chain_out,
jtag_ctrl_chain_in => (others=>'0')--jtag_ctrl_chain_in
);
--
--
-- ---------------- I/O connection to devices --------------------
--
--
--
-- IO SLOT 0 For SPI FLash
--
slot0: zpuino_spi
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(0),
wb_dat_i => slot_write(0),
wb_adr_i => slot_address(0),
wb_we_i => slot_we(0),
wb_cyc_i => slot_cyc(0),
wb_stb_i => slot_stb(0),
wb_ack_o => slot_ack(0),
wb_inta_o => slot_interrupt(0),
mosi => spi_pf_mosi,
miso => spi_pf_miso,
sck => spi_pf_sck,
enabled => spi_enabled
);
--
-- IO SLOT 1
--
uart_inst: zpuino_uart
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(1),
wb_dat_i => slot_write(1),
wb_adr_i => slot_address(1),
wb_we_i => slot_we(1),
wb_cyc_i => slot_cyc(1),
wb_stb_i => slot_stb(1),
wb_ack_o => slot_ack(1),
wb_inta_o => slot_interrupt(1),
enabled => uart_enabled,
tx => tx,
rx => rx
);
--
-- IO SLOT 2
--
gpio_inst: zpuino_gpio
generic map (
gpio_count => zpuino_gpio_count
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(2),
wb_dat_i => slot_write(2),
wb_adr_i => slot_address(2),
wb_we_i => slot_we(2),
wb_cyc_i => slot_cyc(2),
wb_stb_i => slot_stb(2),
wb_ack_o => slot_ack(2),
wb_inta_o => slot_interrupt(2),
spp_data => gpio_bus_in_record.gpio_spp_data,
spp_read => gpio_bus_out_record.gpio_spp_read,
gpio_i => gpio_bus_in_record.gpio_i,
gpio_t => gpio_bus_out_record.gpio_t,
gpio_o => gpio_o_reg,
spp_cap_in => spp_cap_in,
spp_cap_out => spp_cap_out
);
--
-- IO SLOT 3
--
timers_inst: zpuino_timers
generic map (
A_TSCENABLED => true,
A_PWMCOUNT => 1,
A_WIDTH => 16,
A_PRESCALER_ENABLED => true,
A_BUFFERS => true,
B_TSCENABLED => false,
B_PWMCOUNT => 1,
B_WIDTH => 8,
B_PRESCALER_ENABLED => false,
B_BUFFERS => false
)
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(3),
wb_dat_i => slot_write(3),
wb_adr_i => slot_address(3),
wb_we_i => slot_we(3),
wb_cyc_i => slot_cyc(3),
wb_stb_i => slot_stb(3),
wb_ack_o => slot_ack(3),
wb_inta_o => slot_interrupt(3), -- We use two interrupt lines
wb_intb_o => slot_interrupt(4), -- so we borrow intr line from slot 4
pwm_a_out => timers_pwm(0 downto 0),
pwm_b_out => timers_pwm(1 downto 1)
);
--
-- IO SLOT 4 - DO NOT USE (it's already mapped to Interrupt Controller)
--
--
-- IO SLOT 5
--
--
-- sigmadelta_inst: zpuino_sigmadelta
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(5),
-- wb_dat_i => slot_write(5),
-- wb_adr_i => slot_address(5),
-- wb_we_i => slot_we(5),
-- wb_cyc_i => slot_cyc(5),
-- wb_stb_i => slot_stb(5),
-- wb_ack_o => slot_ack(5),
-- wb_inta_o => slot_interrupt(5),
--
-- raw_out => sigmadelta_raw,
-- spp_data => sigmadelta_spp_data,
-- spp_en => sigmadelta_spp_en,
-- sync_in => '1'
-- );
--
-- IO SLOT 6
--
-- slot1: zpuino_spi
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(6),
-- wb_dat_i => slot_write(6),
-- wb_adr_i => slot_address(6),
-- wb_we_i => slot_we(6),
-- wb_cyc_i => slot_cyc(6),
-- wb_stb_i => slot_stb(6),
-- wb_ack_o => slot_ack(6),
-- wb_inta_o => slot_interrupt(6),
--
-- mosi => spi2_mosi,
-- miso => spi2_miso,
-- sck => spi2_sck,
-- enabled => open
-- );
--
--
--
--
-- IO SLOT 7
--
crc16_inst: zpuino_crc16
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_dat_o => slot_read(7),
wb_dat_i => slot_write(7),
wb_adr_i => slot_address(7),
wb_we_i => slot_we(7),
wb_cyc_i => slot_cyc(7),
wb_stb_i => slot_stb(7),
wb_ack_o => slot_ack(7),
wb_inta_o => slot_interrupt(7)
);
--
-- IO SLOT 8 (optional)
--
-- adc_inst: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(8),
-- wb_dat_i => slot_write(8),
-- wb_adr_i => slot_address(8),
-- wb_we_i => slot_we(8),
-- wb_cyc_i => slot_cyc(8),
-- wb_stb_i => slot_stb(8),
-- wb_ack_o => slot_ack(8),
-- wb_inta_o => slot_interrupt(8)
-- );
--
-- --
-- -- IO SLOT 9
-- --
--
-- slot9: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(9),
-- wb_dat_i => slot_write(9),
-- wb_adr_i => slot_address(9),
-- wb_we_i => slot_we(9),
-- wb_cyc_i => slot_cyc(9),
-- wb_stb_i => slot_stb(9),
-- wb_ack_o => slot_ack(9),
-- wb_inta_o => slot_interrupt(9)
-- );
--
-- --
-- -- IO SLOT 10
-- --
--
-- slot10: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(10),
-- wb_dat_i => slot_write(10),
-- wb_adr_i => slot_address(10),
-- wb_we_i => slot_we(10),
-- wb_cyc_i => slot_cyc(10),
-- wb_stb_i => slot_stb(10),
-- wb_ack_o => slot_ack(10),
-- wb_inta_o => slot_interrupt(10)
-- );
--
-- --
-- -- IO SLOT 11
-- --
--
-- slot11: zpuino_empty_device
---- generic map (
---- bits => 4
---- )
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(11),
-- wb_dat_i => slot_write(11),
-- wb_adr_i => slot_address(11),
-- wb_we_i => slot_we(11),
-- wb_cyc_i => slot_cyc(11),
-- wb_stb_i => slot_stb(11),
-- wb_ack_o => slot_ack(11),
--
-- wb_inta_o => slot_interrupt(11)
--
---- tx => uart2_tx,
---- rx => uart2_rx
-- );
--
-- --
-- -- IO SLOT 12
-- --
--
-- slot12: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(12),
-- wb_dat_i => slot_write(12),
-- wb_adr_i => slot_address(12),
-- wb_we_i => slot_we(12),
-- wb_cyc_i => slot_cyc(12),
-- wb_stb_i => slot_stb(12),
-- wb_ack_o => slot_ack(12),
-- wb_inta_o => slot_interrupt(12)
-- );
--
-- --
-- -- IO SLOT 13
-- --
--
-- slot13: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(13),
-- wb_dat_i => slot_write(13),
-- wb_adr_i => slot_address(13),
-- wb_we_i => slot_we(13),
-- wb_cyc_i => slot_cyc(13),
-- wb_stb_i => slot_stb(13),
-- wb_ack_o => slot_ack(13),
-- wb_inta_o => slot_interrupt(13)
--
---- data_out => ym2149_audio_data
-- );
--
-- --
-- -- IO SLOT 14
-- --
--
-- slot14: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(14),
-- wb_dat_i => slot_write(14),
-- wb_adr_i => slot_address(14),
-- wb_we_i => slot_we(14),
-- wb_cyc_i => slot_cyc(14),
-- wb_stb_i => slot_stb(14),
-- wb_ack_o => slot_ack(14),
-- wb_inta_o => slot_interrupt(14)
--
---- clk_1MHZ => sysclk_1mhz,
---- audio_data => sid_audio_data
--
-- );
--
-- --
-- -- IO SLOT 15
-- --
--
-- slot15: zpuino_empty_device
-- port map (
-- wb_clk_i => wb_clk_i,
-- wb_rst_i => wb_rst_i,
-- wb_dat_o => slot_read(15),
-- wb_dat_i => slot_write(15),
-- wb_adr_i => slot_address(15),
-- wb_we_i => slot_we(15),
-- wb_cyc_i => slot_cyc(15),
-- wb_stb_i => slot_stb(15),
-- wb_ack_o => slot_ack(15),
-- wb_inta_o => slot_interrupt(15)
-- );
-- -- Audio for SID
-- sid_sd: simple_sigmadelta
-- generic map (
-- BITS => 18
-- )
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- data_in => sid_audio_data,
-- data_out => sid_audio
-- );
-- Audio output for devices
-- ym2149_audio_dac <= ym2149_audio_data & "0000000000";
--
-- mixer: zpuino_io_audiomixer
-- port map (
-- clk => wb_clk_i,
-- rst => wb_rst_i,
-- ena => '1',
--
-- data_in1 => sid_audio_data,
-- data_in2 => ym2149_audio_dac,
-- data_in3 => sigmadelta_raw,
--
-- audio_out => platform_audio_sd
-- );
-- pin00: IOPAD port map(I => gpio_o(0), O => gpio_i(0), T => gpio_t(0), C => sysclk,PAD => WING_A(0) );
-- pin01: IOPAD port map(I => gpio_o(1), O => gpio_i(1), T => gpio_t(1), C => sysclk,PAD => WING_A(1) );
-- pin02: IOPAD port map(I => gpio_o(2), O => gpio_i(2), T => gpio_t(2), C => sysclk,PAD => WING_A(2) );
-- pin03: IOPAD port map(I => gpio_o(3), O => gpio_i(3), T => gpio_t(3), C => sysclk,PAD => WING_A(3) );
-- pin04: IOPAD port map(I => gpio_o(4), O => gpio_i(4), T => gpio_t(4), C => sysclk,PAD => WING_A(4) );
-- pin05: IOPAD port map(I => gpio_o(5), O => gpio_i(5), T => gpio_t(5), C => sysclk,PAD => WING_A(5) );
-- pin06: IOPAD port map(I => gpio_o(6), O => gpio_i(6), T => gpio_t(6), C => sysclk,PAD => WING_A(6) );
-- pin07: IOPAD port map(I => gpio_o(7), O => gpio_i(7), T => gpio_t(7), C => sysclk,PAD => WING_A(7) );
-- pin08: IOPAD port map(I => gpio_o(8), O => gpio_i(8), T => gpio_t(8), C => sysclk,PAD => WING_A(8) );
-- pin09: IOPAD port map(I => gpio_o(9), O => gpio_i(9), T => gpio_t(9), C => sysclk,PAD => WING_A(9) );
-- pin10: IOPAD port map(I => gpio_o(10),O => gpio_i(10),T => gpio_t(10),C => sysclk,PAD => WING_A(10) );
-- pin11: IOPAD port map(I => gpio_o(11),O => gpio_i(11),T => gpio_t(11),C => sysclk,PAD => WING_A(11) );
-- pin12: IOPAD port map(I => gpio_o(12),O => gpio_i(12),T => gpio_t(12),C => sysclk,PAD => WING_A(12) );
-- pin13: IOPAD port map(I => gpio_o(13),O => gpio_i(13),T => gpio_t(13),C => sysclk,PAD => WING_A(13) );
-- pin14: IOPAD port map(I => gpio_o(14),O => gpio_i(14),T => gpio_t(14),C => sysclk,PAD => WING_A(14) );
-- pin15: IOPAD port map(I => gpio_o(15),O => gpio_i(15),T => gpio_t(15),C => sysclk,PAD => WING_A(15) );
--
-- pin16: IOPAD port map(I => gpio_o(16),O => gpio_i(16),T => gpio_t(16),C => sysclk,PAD => WING_B(0) );
-- pin17: IOPAD port map(I => gpio_o(17),O => gpio_i(17),T => gpio_t(17),C => sysclk,PAD => WING_B(1) );
-- pin18: IOPAD port map(I => gpio_o(18),O => gpio_i(18),T => gpio_t(18),C => sysclk,PAD => WING_B(2) );
-- pin19: IOPAD port map(I => gpio_o(19),O => gpio_i(19),T => gpio_t(19),C => sysclk,PAD => WING_B(3) );
-- pin20: IOPAD port map(I => gpio_o(20),O => gpio_i(20),T => gpio_t(20),C => sysclk,PAD => WING_B(4) );
-- pin21: IOPAD port map(I => gpio_o(21),O => gpio_i(21),T => gpio_t(21),C => sysclk,PAD => WING_B(5) );
-- pin22: IOPAD port map(I => gpio_o(22),O => gpio_i(22),T => gpio_t(22),C => sysclk,PAD => WING_B(6) );
-- pin23: IOPAD port map(I => gpio_o(23),O => gpio_i(23),T => gpio_t(23),C => sysclk,PAD => WING_B(7) );
-- pin24: IOPAD port map(I => gpio_o(24),O => gpio_i(24),T => gpio_t(24),C => sysclk,PAD => WING_B(8) );
-- pin25: IOPAD port map(I => gpio_o(25),O => gpio_i(25),T => gpio_t(25),C => sysclk,PAD => WING_B(9) );
-- pin26: IOPAD port map(I => gpio_o(26),O => gpio_i(26),T => gpio_t(26),C => sysclk,PAD => WING_B(10) );
-- pin27: IOPAD port map(I => gpio_o(27),O => gpio_i(27),T => gpio_t(27),C => sysclk,PAD => WING_B(11) );
-- pin28: IOPAD port map(I => gpio_o(28),O => gpio_i(28),T => gpio_t(28),C => sysclk,PAD => WING_B(12) );
-- pin29: IOPAD port map(I => gpio_o(29),O => gpio_i(29),T => gpio_t(29),C => sysclk,PAD => WING_B(13) );
-- pin30: IOPAD port map(I => gpio_o(30),O => gpio_i(30),T => gpio_t(30),C => sysclk,PAD => WING_B(14) );
-- pin31: IOPAD port map(I => gpio_o(31),O => gpio_i(31),T => gpio_t(31),C => sysclk,PAD => WING_B(15) );
--
-- pin32: IOPAD port map(I => gpio_o(32),O => gpio_i(32),T => gpio_t(32),C => sysclk,PAD => WING_C(0) );
-- pin33: IOPAD port map(I => gpio_o(33),O => gpio_i(33),T => gpio_t(33),C => sysclk,PAD => WING_C(1) );
-- pin34: IOPAD port map(I => gpio_o(34),O => gpio_i(34),T => gpio_t(34),C => sysclk,PAD => WING_C(2) );
-- pin35: IOPAD port map(I => gpio_o(35),O => gpio_i(35),T => gpio_t(35),C => sysclk,PAD => WING_C(3) );
-- pin36: IOPAD port map(I => gpio_o(36),O => gpio_i(36),T => gpio_t(36),C => sysclk,PAD => WING_C(4) );
-- pin37: IOPAD port map(I => gpio_o(37),O => gpio_i(37),T => gpio_t(37),C => sysclk,PAD => WING_C(5) );
-- pin38: IOPAD port map(I => gpio_o(38),O => gpio_i(38),T => gpio_t(38),C => sysclk,PAD => WING_C(6) );
-- pin39: IOPAD port map(I => gpio_o(39),O => gpio_i(39),T => gpio_t(39),C => sysclk,PAD => WING_C(7) );
-- pin40: IOPAD port map(I => gpio_o(40),O => gpio_i(40),T => gpio_t(40),C => sysclk,PAD => WING_C(8) );
-- pin41: IOPAD port map(I => gpio_o(41),O => gpio_i(41),T => gpio_t(41),C => sysclk,PAD => WING_C(9) );
-- pin42: IOPAD port map(I => gpio_o(42),O => gpio_i(42),T => gpio_t(42),C => sysclk,PAD => WING_C(10) );
-- pin43: IOPAD port map(I => gpio_o(43),O => gpio_i(43),T => gpio_t(43),C => sysclk,PAD => WING_C(11) );
-- pin44: IOPAD port map(I => gpio_o(44),O => gpio_i(44),T => gpio_t(44),C => sysclk,PAD => WING_C(12) );
-- pin45: IOPAD port map(I => gpio_o(45),O => gpio_i(45),T => gpio_t(45),C => sysclk,PAD => WING_C(13) );
-- pin46: IOPAD port map(I => gpio_o(46),O => gpio_i(46),T => gpio_t(46),C => sysclk,PAD => WING_C(14) );
-- pin47: IOPAD port map(I => gpio_o(47),O => gpio_i(47),T => gpio_t(47),C => sysclk,PAD => WING_C(15) );
-- Other ports are special, we need to avoid outputs on input-only pins
ibufrx: IPAD port map ( PAD => RXD, O => rx, C => sysclk );
ibufmiso: IPAD port map ( PAD => SPI_FLASH_MISO, O => spi_pf_miso, C => sysclk );
obuftx: OPAD port map ( I => tx, PAD => TXD );
ospiclk: OPAD port map ( I => spi_pf_sck, PAD => SPI_FLASH_SCK );
ospics: OPAD port map ( I => gpio_o_reg(48), PAD => SPI_FLASH_CS );
ospimosi: OPAD port map ( I => spi_pf_mosi, PAD => SPI_FLASH_MOSI );
-- process(gpio_spp_read,
-- sigmadelta_spp_data,
-- timers_pwm,
-- spi2_mosi,spi2_sck)
-- begin
--
-- gpio_spp_data <= (others => DontCareValue);
--
---- gpio_spp_data(0) <= platform_audio_sd; -- PPS0 : SIGMADELTA DATA
-- gpio_spp_data(1) <= timers_pwm(0); -- PPS1 : TIMER0
-- gpio_spp_data(2) <= timers_pwm(1); -- PPS2 : TIMER1
-- gpio_spp_data(3) <= spi2_mosi; -- PPS3 : USPI MOSI
-- gpio_spp_data(4) <= spi2_sck; -- PPS4 : USPI SCK
---- gpio_spp_data(5) <= platform_audio_sd; -- PPS5 : SIGMADELTA1 DATA
-- gpio_spp_data(6) <= uart2_tx; -- PPS6 : UART2 DATA
---- gpio_spp_data(8) <= platform_audio_sd;
-- spi2_miso <= gpio_spp_read(0); -- PPS0 : USPI MISO
---- uart2_rx <= gpio_spp_read(1); -- PPS0 : USPI MISO
--
-- end process;
end behave;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68d
-- \ \ Application: netgen
-- / / Filename: bram_x64.vhd
-- /___/ /\ Timestamp: Fri Sep 6 17:21:24 2013
-- \ \ / \
-- \___\/\___\
--
-- Command : -w -sim -ofmt vhdl /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/bram_x64.ngc /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/bram_x64.vhd
-- Device : 6vlx240tff1156-1
-- Input file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/bram_x64.ngc
-- Output file : /home/adrian/praca/creotech/pcie_brazil/bpm-sw/hdl/ip_cores/pcie/ml605/tmp/_cg/bram_x64.vhd
-- # of Entities : 1
-- Design Name : bram_x64
-- Xilinx : /opt/Xilinx/14.6/ISE_DS/ISE/
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity bram_x64 is
port (
clka : in STD_LOGIC := 'X';
clkb : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
web : in STD_LOGIC_VECTOR ( 7 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 63 downto 0 );
douta : out STD_LOGIC_VECTOR ( 63 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
);
end bram_x64;
architecture STRUCTURE of bram_x64 is
signal N0 : STD_LOGIC;
signal N1 : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED : STD_LOGIC;
signal NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED : STD_LOGIC;
begin
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => N1
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(63),
DIADI(6) => dina(62),
DIADI(5) => dina(61),
DIADI(4) => dina(60),
DIADI(3) => dina(59),
DIADI(2) => dina(58),
DIADI(1) => dina(57),
DIADI(0) => dina(56),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(63),
DIBDI(6) => dinb(62),
DIBDI(5) => dinb(61),
DIBDI(4) => dinb(60),
DIBDI(3) => dinb(59),
DIBDI(2) => dinb(58),
DIBDI(1) => dinb(57),
DIBDI(0) => dinb(56),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(63),
DOADO(6) => douta(62),
DOADO(5) => douta(61),
DOADO(4) => douta(60),
DOADO(3) => douta(59),
DOADO(2) => douta(58),
DOADO(1) => douta(57),
DOADO(0) => douta(56),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(63),
DOBDO(6) => doutb(62),
DOBDO(5) => doutb(61),
DOBDO(4) => doutb(60),
DOBDO(3) => doutb(59),
DOBDO(2) => doutb(58),
DOBDO(1) => doutb(57),
DOBDO(0) => doutb(56),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_7_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(7),
WEA(2) => wea(7),
WEA(1) => wea(7),
WEA(0) => wea(7),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(7),
WEBWE(2) => web(7),
WEBWE(1) => web(7),
WEBWE(0) => web(7)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(55),
DIADI(6) => dina(54),
DIADI(5) => dina(53),
DIADI(4) => dina(52),
DIADI(3) => dina(51),
DIADI(2) => dina(50),
DIADI(1) => dina(49),
DIADI(0) => dina(48),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(55),
DIBDI(6) => dinb(54),
DIBDI(5) => dinb(53),
DIBDI(4) => dinb(52),
DIBDI(3) => dinb(51),
DIBDI(2) => dinb(50),
DIBDI(1) => dinb(49),
DIBDI(0) => dinb(48),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(55),
DOADO(6) => douta(54),
DOADO(5) => douta(53),
DOADO(4) => douta(52),
DOADO(3) => douta(51),
DOADO(2) => douta(50),
DOADO(1) => douta(49),
DOADO(0) => douta(48),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(55),
DOBDO(6) => doutb(54),
DOBDO(5) => doutb(53),
DOBDO(4) => doutb(52),
DOBDO(3) => doutb(51),
DOBDO(2) => doutb(50),
DOBDO(1) => doutb(49),
DOBDO(0) => doutb(48),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_6_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(6),
WEA(2) => wea(6),
WEA(1) => wea(6),
WEA(0) => wea(6),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(6),
WEBWE(2) => web(6),
WEBWE(1) => web(6),
WEBWE(0) => web(6)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(47),
DIADI(6) => dina(46),
DIADI(5) => dina(45),
DIADI(4) => dina(44),
DIADI(3) => dina(43),
DIADI(2) => dina(42),
DIADI(1) => dina(41),
DIADI(0) => dina(40),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(47),
DIBDI(6) => dinb(46),
DIBDI(5) => dinb(45),
DIBDI(4) => dinb(44),
DIBDI(3) => dinb(43),
DIBDI(2) => dinb(42),
DIBDI(1) => dinb(41),
DIBDI(0) => dinb(40),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(47),
DOADO(6) => douta(46),
DOADO(5) => douta(45),
DOADO(4) => douta(44),
DOADO(3) => douta(43),
DOADO(2) => douta(42),
DOADO(1) => douta(41),
DOADO(0) => douta(40),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(47),
DOBDO(6) => doutb(46),
DOBDO(5) => doutb(45),
DOBDO(4) => doutb(44),
DOBDO(3) => doutb(43),
DOBDO(2) => doutb(42),
DOBDO(1) => doutb(41),
DOBDO(0) => doutb(40),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_5_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(5),
WEA(2) => wea(5),
WEA(1) => wea(5),
WEA(0) => wea(5),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(5),
WEBWE(2) => web(5),
WEBWE(1) => web(5),
WEBWE(0) => web(5)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(39),
DIADI(6) => dina(38),
DIADI(5) => dina(37),
DIADI(4) => dina(36),
DIADI(3) => dina(35),
DIADI(2) => dina(34),
DIADI(1) => dina(33),
DIADI(0) => dina(32),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(39),
DIBDI(6) => dinb(38),
DIBDI(5) => dinb(37),
DIBDI(4) => dinb(36),
DIBDI(3) => dinb(35),
DIBDI(2) => dinb(34),
DIBDI(1) => dinb(33),
DIBDI(0) => dinb(32),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(39),
DOADO(6) => douta(38),
DOADO(5) => douta(37),
DOADO(4) => douta(36),
DOADO(3) => douta(35),
DOADO(2) => douta(34),
DOADO(1) => douta(33),
DOADO(0) => douta(32),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(39),
DOBDO(6) => doutb(38),
DOBDO(5) => doutb(37),
DOBDO(4) => doutb(36),
DOBDO(3) => doutb(35),
DOBDO(2) => doutb(34),
DOBDO(1) => doutb(33),
DOBDO(0) => doutb(32),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_4_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(4),
WEA(2) => wea(4),
WEA(1) => wea(4),
WEA(0) => wea(4),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(4),
WEBWE(2) => web(4),
WEBWE(1) => web(4),
WEBWE(0) => web(4)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(31),
DIADI(6) => dina(30),
DIADI(5) => dina(29),
DIADI(4) => dina(28),
DIADI(3) => dina(27),
DIADI(2) => dina(26),
DIADI(1) => dina(25),
DIADI(0) => dina(24),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(31),
DIBDI(6) => dinb(30),
DIBDI(5) => dinb(29),
DIBDI(4) => dinb(28),
DIBDI(3) => dinb(27),
DIBDI(2) => dinb(26),
DIBDI(1) => dinb(25),
DIBDI(0) => dinb(24),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(31),
DOADO(6) => douta(30),
DOADO(5) => douta(29),
DOADO(4) => douta(28),
DOADO(3) => douta(27),
DOADO(2) => douta(26),
DOADO(1) => douta(25),
DOADO(0) => douta(24),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(31),
DOBDO(6) => doutb(30),
DOBDO(5) => doutb(29),
DOBDO(4) => doutb(28),
DOBDO(3) => doutb(27),
DOBDO(2) => doutb(26),
DOBDO(1) => doutb(25),
DOBDO(0) => doutb(24),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_3_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(3),
WEA(2) => wea(3),
WEA(1) => wea(3),
WEA(0) => wea(3),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(3),
WEBWE(2) => web(3),
WEBWE(1) => web(3),
WEBWE(0) => web(3)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(23),
DIADI(6) => dina(22),
DIADI(5) => dina(21),
DIADI(4) => dina(20),
DIADI(3) => dina(19),
DIADI(2) => dina(18),
DIADI(1) => dina(17),
DIADI(0) => dina(16),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(23),
DIBDI(6) => dinb(22),
DIBDI(5) => dinb(21),
DIBDI(4) => dinb(20),
DIBDI(3) => dinb(19),
DIBDI(2) => dinb(18),
DIBDI(1) => dinb(17),
DIBDI(0) => dinb(16),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(23),
DOADO(6) => douta(22),
DOADO(5) => douta(21),
DOADO(4) => douta(20),
DOADO(3) => douta(19),
DOADO(2) => douta(18),
DOADO(1) => douta(17),
DOADO(0) => douta(16),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(23),
DOBDO(6) => doutb(22),
DOBDO(5) => doutb(21),
DOBDO(4) => doutb(20),
DOBDO(3) => doutb(19),
DOBDO(2) => doutb(18),
DOBDO(1) => doutb(17),
DOBDO(0) => doutb(16),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_2_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(2),
WEA(2) => wea(2),
WEA(1) => wea(2),
WEA(0) => wea(2),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(2),
WEBWE(2) => web(2),
WEBWE(1) => web(2),
WEBWE(0) => web(2)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(15),
DIADI(6) => dina(14),
DIADI(5) => dina(13),
DIADI(4) => dina(12),
DIADI(3) => dina(11),
DIADI(2) => dina(10),
DIADI(1) => dina(9),
DIADI(0) => dina(8),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(15),
DIBDI(6) => dinb(14),
DIBDI(5) => dinb(13),
DIBDI(4) => dinb(12),
DIBDI(3) => dinb(11),
DIBDI(2) => dinb(10),
DIBDI(1) => dinb(9),
DIBDI(0) => dinb(8),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(15),
DOADO(6) => douta(14),
DOADO(5) => douta(13),
DOADO(4) => douta(12),
DOADO(3) => douta(11),
DOADO(2) => douta(10),
DOADO(1) => douta(9),
DOADO(0) => douta(8),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(15),
DOBDO(6) => doutb(14),
DOBDO(5) => doutb(13),
DOBDO(4) => doutb(12),
DOBDO(3) => doutb(11),
DOBDO(2) => doutb(10),
DOBDO(1) => doutb(9),
DOBDO(0) => doutb(8),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_1_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(1),
WEA(2) => wea(1),
WEA(1) => wea(1),
WEA(0) => wea(1),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(1),
WEBWE(2) => web(1),
WEBWE(1) => web(1),
WEBWE(0) => web(1)
);
U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram : RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 1,
EN_ECC_READ => FALSE,
EN_ECC_WRITE => FALSE,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "VIRTEX6",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
CASCADEINA => N1,
CASCADEINB => N1,
CASCADEOUTA =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTA_UNCONNECTED
,
CASCADEOUTB =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_CASCADEOUTB_UNCONNECTED
,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DBITERR_UNCONNECTED
,
ENARDEN => N0,
ENBWREN => N0,
INJECTDBITERR => N1,
INJECTSBITERR => N1,
REGCEAREGCE => N1,
REGCEB => N0,
RSTRAMARSTRAM => N1,
RSTRAMB => N1,
RSTREGARSTREG => N1,
RSTREGB => N1,
SBITERR =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_SBITERR_UNCONNECTED
,
ADDRARDADDR(15) => N0,
ADDRARDADDR(14) => addra(11),
ADDRARDADDR(13) => addra(10),
ADDRARDADDR(12) => addra(9),
ADDRARDADDR(11) => addra(8),
ADDRARDADDR(10) => addra(7),
ADDRARDADDR(9) => addra(6),
ADDRARDADDR(8) => addra(5),
ADDRARDADDR(7) => addra(4),
ADDRARDADDR(6) => addra(3),
ADDRARDADDR(5) => addra(2),
ADDRARDADDR(4) => addra(1),
ADDRARDADDR(3) => addra(0),
ADDRARDADDR(2) => N1,
ADDRARDADDR(1) => N1,
ADDRARDADDR(0) => N1,
ADDRBWRADDR(15) => N0,
ADDRBWRADDR(14) => addrb(11),
ADDRBWRADDR(13) => addrb(10),
ADDRBWRADDR(12) => addrb(9),
ADDRBWRADDR(11) => addrb(8),
ADDRBWRADDR(10) => addrb(7),
ADDRBWRADDR(9) => addrb(6),
ADDRBWRADDR(8) => addrb(5),
ADDRBWRADDR(7) => addrb(4),
ADDRBWRADDR(6) => addrb(3),
ADDRBWRADDR(5) => addrb(2),
ADDRBWRADDR(4) => addrb(1),
ADDRBWRADDR(3) => addrb(0),
ADDRBWRADDR(2) => N1,
ADDRBWRADDR(1) => N1,
ADDRBWRADDR(0) => N1,
DIADI(31) => N1,
DIADI(30) => N1,
DIADI(29) => N1,
DIADI(28) => N1,
DIADI(27) => N1,
DIADI(26) => N1,
DIADI(25) => N1,
DIADI(24) => N1,
DIADI(23) => N1,
DIADI(22) => N1,
DIADI(21) => N1,
DIADI(20) => N1,
DIADI(19) => N1,
DIADI(18) => N1,
DIADI(17) => N1,
DIADI(16) => N1,
DIADI(15) => N1,
DIADI(14) => N1,
DIADI(13) => N1,
DIADI(12) => N1,
DIADI(11) => N1,
DIADI(10) => N1,
DIADI(9) => N1,
DIADI(8) => N1,
DIADI(7) => dina(7),
DIADI(6) => dina(6),
DIADI(5) => dina(5),
DIADI(4) => dina(4),
DIADI(3) => dina(3),
DIADI(2) => dina(2),
DIADI(1) => dina(1),
DIADI(0) => dina(0),
DIBDI(31) => N1,
DIBDI(30) => N1,
DIBDI(29) => N1,
DIBDI(28) => N1,
DIBDI(27) => N1,
DIBDI(26) => N1,
DIBDI(25) => N1,
DIBDI(24) => N1,
DIBDI(23) => N1,
DIBDI(22) => N1,
DIBDI(21) => N1,
DIBDI(20) => N1,
DIBDI(19) => N1,
DIBDI(18) => N1,
DIBDI(17) => N1,
DIBDI(16) => N1,
DIBDI(15) => N1,
DIBDI(14) => N1,
DIBDI(13) => N1,
DIBDI(12) => N1,
DIBDI(11) => N1,
DIBDI(10) => N1,
DIBDI(9) => N1,
DIBDI(8) => N1,
DIBDI(7) => dinb(7),
DIBDI(6) => dinb(6),
DIBDI(5) => dinb(5),
DIBDI(4) => dinb(4),
DIBDI(3) => dinb(3),
DIBDI(2) => dinb(2),
DIBDI(1) => dinb(1),
DIBDI(0) => dinb(0),
DIPADIP(3) => N1,
DIPADIP(2) => N1,
DIPADIP(1) => N1,
DIPADIP(0) => N1,
DIPBDIP(3) => N1,
DIPBDIP(2) => N1,
DIPBDIP(1) => N1,
DIPBDIP(0) => N1,
DOADO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_31_UNCONNECTED
,
DOADO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_30_UNCONNECTED
,
DOADO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_29_UNCONNECTED
,
DOADO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_28_UNCONNECTED
,
DOADO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_27_UNCONNECTED
,
DOADO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_26_UNCONNECTED
,
DOADO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_25_UNCONNECTED
,
DOADO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_24_UNCONNECTED
,
DOADO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_23_UNCONNECTED
,
DOADO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_22_UNCONNECTED
,
DOADO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_21_UNCONNECTED
,
DOADO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_20_UNCONNECTED
,
DOADO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_19_UNCONNECTED
,
DOADO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_18_UNCONNECTED
,
DOADO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_17_UNCONNECTED
,
DOADO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_16_UNCONNECTED
,
DOADO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_15_UNCONNECTED
,
DOADO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_14_UNCONNECTED
,
DOADO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_13_UNCONNECTED
,
DOADO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_12_UNCONNECTED
,
DOADO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_11_UNCONNECTED
,
DOADO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_10_UNCONNECTED
,
DOADO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_9_UNCONNECTED
,
DOADO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOADO_8_UNCONNECTED
,
DOADO(7) => douta(7),
DOADO(6) => douta(6),
DOADO(5) => douta(5),
DOADO(4) => douta(4),
DOADO(3) => douta(3),
DOADO(2) => douta(2),
DOADO(1) => douta(1),
DOADO(0) => douta(0),
DOBDO(31) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_31_UNCONNECTED
,
DOBDO(30) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_30_UNCONNECTED
,
DOBDO(29) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_29_UNCONNECTED
,
DOBDO(28) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_28_UNCONNECTED
,
DOBDO(27) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_27_UNCONNECTED
,
DOBDO(26) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_26_UNCONNECTED
,
DOBDO(25) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_25_UNCONNECTED
,
DOBDO(24) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_24_UNCONNECTED
,
DOBDO(23) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_23_UNCONNECTED
,
DOBDO(22) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_22_UNCONNECTED
,
DOBDO(21) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_21_UNCONNECTED
,
DOBDO(20) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_20_UNCONNECTED
,
DOBDO(19) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_19_UNCONNECTED
,
DOBDO(18) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_18_UNCONNECTED
,
DOBDO(17) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_17_UNCONNECTED
,
DOBDO(16) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_16_UNCONNECTED
,
DOBDO(15) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_15_UNCONNECTED
,
DOBDO(14) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_14_UNCONNECTED
,
DOBDO(13) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_13_UNCONNECTED
,
DOBDO(12) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_12_UNCONNECTED
,
DOBDO(11) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_11_UNCONNECTED
,
DOBDO(10) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_10_UNCONNECTED
,
DOBDO(9) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_9_UNCONNECTED
,
DOBDO(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOBDO_8_UNCONNECTED
,
DOBDO(7) => doutb(7),
DOBDO(6) => doutb(6),
DOBDO(5) => doutb(5),
DOBDO(4) => doutb(4),
DOBDO(3) => doutb(3),
DOBDO(2) => doutb(2),
DOBDO(1) => doutb(1),
DOBDO(0) => doutb(0),
DOPADOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_3_UNCONNECTED
,
DOPADOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_2_UNCONNECTED
,
DOPADOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_1_UNCONNECTED
,
DOPADOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPADOP_0_UNCONNECTED
,
DOPBDOP(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_3_UNCONNECTED
,
DOPBDOP(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_2_UNCONNECTED
,
DOPBDOP(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_1_UNCONNECTED
,
DOPBDOP(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_DOPBDOP_0_UNCONNECTED
,
ECCPARITY(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_7_UNCONNECTED
,
ECCPARITY(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_6_UNCONNECTED
,
ECCPARITY(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_5_UNCONNECTED
,
ECCPARITY(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_4_UNCONNECTED
,
ECCPARITY(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_3_UNCONNECTED
,
ECCPARITY(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_2_UNCONNECTED
,
ECCPARITY(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_1_UNCONNECTED
,
ECCPARITY(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_ECCPARITY_0_UNCONNECTED
,
RDADDRECC(8) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_8_UNCONNECTED
,
RDADDRECC(7) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_7_UNCONNECTED
,
RDADDRECC(6) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_6_UNCONNECTED
,
RDADDRECC(5) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_5_UNCONNECTED
,
RDADDRECC(4) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_4_UNCONNECTED
,
RDADDRECC(3) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_3_UNCONNECTED
,
RDADDRECC(2) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_2_UNCONNECTED
,
RDADDRECC(1) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_1_UNCONNECTED
,
RDADDRECC(0) =>
NLW_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_v6_noinit_ram_NO_BMM_INFO_TRUE_DP_SIMPLE_PRIM36_ram_RDADDRECC_0_UNCONNECTED
,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7) => N1,
WEBWE(6) => N1,
WEBWE(5) => N1,
WEBWE(4) => N1,
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
-- synthesis translate_on
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
-- Date : Sat Jan 21 14:43:34 2017
-- Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
-- Command : write_vhdl -force -mode funcsim
-- /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mult_17x16/mult_17x16_sim_netlist.vhdl
-- Design : mult_17x16
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xcku035-fbva676-3-e
-- --------------------------------------------------------------------------------
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`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`protect encoding = (enctype="base64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 460000)
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yja9697GlNeE1PEMMjXEm2kPdVdP5PMn1tud9174WiO9rYS18pfCA4GQQXtaFN4oXkoL1nO26ad1
eKwGx2Yv/cseY1li992bhJkujrWkxp1kF9DSBuSKU2fxgkN/WkgpvyNmtH4gUoY1LpIJVyeN2juz
MLKADnZ1Nw6XAW64sfHCcXIJBbKQ3OCLunw44oeTaScNqEl1sRuf1zsGA/sYeZLeR3gGQtTyg+K5
TyZy+nfS2VEkdQqxSZRjNVDXZc85GR8QNhu805rc0kBF3XffIZBKh6z2xZX1y/JQReImJ7BKKUTe
bhopvcusSZgbCfB7XeTUHVhTWSrQJAGQXtxcgjxz77H8wSXZP4xo7afm/wy+/poeRw0FUX55H6aX
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BOlPMKbcqG8wcQ==
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_17x16_mult_gen_v12_0_12 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 16 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
CE : in STD_LOGIC;
SCLR : in STD_LOGIC;
ZERO_DETECT : out STD_LOGIC_VECTOR ( 1 downto 0 );
P : out STD_LOGIC_VECTOR ( 24 downto 0 );
PCASC : out STD_LOGIC_VECTOR ( 47 downto 0 )
);
attribute C_A_TYPE : integer;
attribute C_A_TYPE of mult_17x16_mult_gen_v12_0_12 : entity is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of mult_17x16_mult_gen_v12_0_12 : entity is 17;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of mult_17x16_mult_gen_v12_0_12 : entity is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of mult_17x16_mult_gen_v12_0_12 : entity is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of mult_17x16_mult_gen_v12_0_12 : entity is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of mult_17x16_mult_gen_v12_0_12 : entity is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_OPTIMIZE_GOAL : integer;
attribute C_OPTIMIZE_GOAL of mult_17x16_mult_gen_v12_0_12 : entity is 1;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of mult_17x16_mult_gen_v12_0_12 : entity is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of mult_17x16_mult_gen_v12_0_12 : entity is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of mult_17x16_mult_gen_v12_0_12 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of mult_17x16_mult_gen_v12_0_12 : entity is "kintexu";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of mult_17x16_mult_gen_v12_0_12 : entity is "mult_gen_v12_0_12";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_17x16_mult_gen_v12_0_12 : entity is "yes";
end mult_17x16_mult_gen_v12_0_12;
architecture STRUCTURE of mult_17x16_mult_gen_v12_0_12 is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_mult_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_i_mult_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE of i_mult : label is 1;
attribute C_A_WIDTH of i_mult : label is 17;
attribute C_B_TYPE of i_mult : label is 1;
attribute C_B_VALUE of i_mult : label is "10000001";
attribute C_B_WIDTH of i_mult : label is 16;
attribute C_CCM_IMP of i_mult : label is 0;
attribute C_CE_OVERRIDES_SCLR of i_mult : label is 0;
attribute C_HAS_CE of i_mult : label is 0;
attribute C_HAS_SCLR of i_mult : label is 0;
attribute C_HAS_ZERO_DETECT of i_mult : label is 0;
attribute C_LATENCY of i_mult : label is 4;
attribute C_MODEL_TYPE of i_mult : label is 0;
attribute C_MULT_TYPE of i_mult : label is 0;
attribute C_OUT_HIGH of i_mult : label is 32;
attribute C_OUT_LOW of i_mult : label is 8;
attribute C_ROUND_OUTPUT of i_mult : label is 0;
attribute C_ROUND_PT of i_mult : label is 0;
attribute C_VERBOSITY of i_mult : label is 0;
attribute C_XDEVICEFAMILY of i_mult : label is "kintexu";
attribute c_optimize_goal of i_mult : label is 1;
attribute downgradeipidentifiedwarnings of i_mult : label is "yes";
begin
PCASC(47) <= \<const0>\;
PCASC(46) <= \<const0>\;
PCASC(45) <= \<const0>\;
PCASC(44) <= \<const0>\;
PCASC(43) <= \<const0>\;
PCASC(42) <= \<const0>\;
PCASC(41) <= \<const0>\;
PCASC(40) <= \<const0>\;
PCASC(39) <= \<const0>\;
PCASC(38) <= \<const0>\;
PCASC(37) <= \<const0>\;
PCASC(36) <= \<const0>\;
PCASC(35) <= \<const0>\;
PCASC(34) <= \<const0>\;
PCASC(33) <= \<const0>\;
PCASC(32) <= \<const0>\;
PCASC(31) <= \<const0>\;
PCASC(30) <= \<const0>\;
PCASC(29) <= \<const0>\;
PCASC(28) <= \<const0>\;
PCASC(27) <= \<const0>\;
PCASC(26) <= \<const0>\;
PCASC(25) <= \<const0>\;
PCASC(24) <= \<const0>\;
PCASC(23) <= \<const0>\;
PCASC(22) <= \<const0>\;
PCASC(21) <= \<const0>\;
PCASC(20) <= \<const0>\;
PCASC(19) <= \<const0>\;
PCASC(18) <= \<const0>\;
PCASC(17) <= \<const0>\;
PCASC(16) <= \<const0>\;
PCASC(15) <= \<const0>\;
PCASC(14) <= \<const0>\;
PCASC(13) <= \<const0>\;
PCASC(12) <= \<const0>\;
PCASC(11) <= \<const0>\;
PCASC(10) <= \<const0>\;
PCASC(9) <= \<const0>\;
PCASC(8) <= \<const0>\;
PCASC(7) <= \<const0>\;
PCASC(6) <= \<const0>\;
PCASC(5) <= \<const0>\;
PCASC(4) <= \<const0>\;
PCASC(3) <= \<const0>\;
PCASC(2) <= \<const0>\;
PCASC(1) <= \<const0>\;
PCASC(0) <= \<const0>\;
ZERO_DETECT(1) <= \<const0>\;
ZERO_DETECT(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_mult: entity work.mult_17x16_mult_gen_v12_0_12_viv
port map (
A(16 downto 0) => A(16 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '0',
CLK => CLK,
P(24 downto 0) => P(24 downto 0),
PCASC(47 downto 0) => NLW_i_mult_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_i_mult_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mult_17x16 is
port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 16 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 24 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of mult_17x16 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of mult_17x16 : entity is "mult_17x16,mult_gen_v12_0_12,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of mult_17x16 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of mult_17x16 : entity is "mult_gen_v12_0_12,Vivado 2016.4";
end mult_17x16;
architecture STRUCTURE of mult_17x16 is
signal NLW_U0_PCASC_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_U0_ZERO_DETECT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_A_TYPE : integer;
attribute C_A_TYPE of U0 : label is 1;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of U0 : label is 17;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of U0 : label is 1;
attribute C_B_VALUE : string;
attribute C_B_VALUE of U0 : label is "10000001";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of U0 : label is 16;
attribute C_CCM_IMP : integer;
attribute C_CCM_IMP of U0 : label is 0;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of U0 : label is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of U0 : label is 0;
attribute C_HAS_ZERO_DETECT : integer;
attribute C_HAS_ZERO_DETECT of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 4;
attribute C_MODEL_TYPE : integer;
attribute C_MODEL_TYPE of U0 : label is 0;
attribute C_MULT_TYPE : integer;
attribute C_MULT_TYPE of U0 : label is 0;
attribute C_OUT_HIGH : integer;
attribute C_OUT_HIGH of U0 : label is 32;
attribute C_OUT_LOW : integer;
attribute C_OUT_LOW of U0 : label is 8;
attribute C_ROUND_OUTPUT : integer;
attribute C_ROUND_OUTPUT of U0 : label is 0;
attribute C_ROUND_PT : integer;
attribute C_ROUND_PT of U0 : label is 0;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "kintexu";
attribute c_optimize_goal : integer;
attribute c_optimize_goal of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.mult_17x16_mult_gen_v12_0_12
port map (
A(16 downto 0) => A(16 downto 0),
B(15 downto 0) => B(15 downto 0),
CE => '1',
CLK => CLK,
P(24 downto 0) => P(24 downto 0),
PCASC(47 downto 0) => NLW_U0_PCASC_UNCONNECTED(47 downto 0),
SCLR => '0',
ZERO_DETECT(1 downto 0) => NLW_U0_ZERO_DETECT_UNCONNECTED(1 downto 0)
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2015 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : BusMonCore.vhd
-- /___/ /\ Timestamp : 30/05/2015
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomBusMon
--Device: XC3S250E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.OhoPack.all ;
entity BusMonCore is
generic (
num_comparators : integer := 8;
reg_width : integer := 46;
fifo_width : integer := 72;
avr_data_mem_size : integer := 1024 * 2; -- 2K is the mimimum
avr_prog_mem_size : integer := 1024 * 8 -- Default is 8K, 6809 amd Z80 need 9K
);
port (
clock_avr : in std_logic;
busmon_clk : in std_logic;
busmon_clken : in std_logic;
cpu_clk : in std_logic;
cpu_clken : in std_logic;
-- CPU Signals
Addr : in std_logic_vector(15 downto 0);
Data : in std_logic_vector(7 downto 0);
Rd_n : in std_logic;
Wr_n : in std_logic;
RdIO_n : in std_logic;
WrIO_n : in std_logic;
Sync : in std_logic;
Rdy : out std_logic;
nRSTin : in std_logic;
nRSTout : out std_logic;
CountCycle : in std_logic;
-- CPU Registers
-- unused in pure bus monitor mode
Regs : in std_logic_vector(255 downto 0);
-- CPI Specific data
PdcData : in std_logic_vector(7 downto 0) := x"00";
-- CPU Memory Read/Write
-- unused in pure bus monitor mode
RdMemOut : out std_logic;
WrMemOut : out std_logic;
RdIOOut : out std_logic;
WrIOOut : out std_logic;
ExecOut : out std_logic;
AddrOut : out std_logic_vector(15 downto 0);
DataOut : out std_logic_vector(7 downto 0);
DataIn : in std_logic_vector(7 downto 0);
Done : in std_logic;
-- Special outputs (function is CPU specific)
Special : out std_logic_vector(2 downto 0);
-- Single Step interface
SS_Single : out std_logic;
SS_Step : out std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- AVR Serial Port
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic
);
end BusMonCore;
architecture behavioral of BusMonCore is
signal cpu_reset_n : std_logic;
signal nrst_avr : std_logic;
signal nrst1 : std_logic;
signal nrst2 : std_logic;
signal nrst3 : std_logic;
-- debounce time is 2^17 / 16MHz = 8.192ms
signal nrst_counter : unsigned(17 downto 0);
signal dy_counter : std_logic_vector(31 downto 0);
signal dy_data : y2d_type ;
signal mux : std_logic_vector(7 downto 0);
signal muxsel : std_logic_vector(5 downto 0);
signal cmd_edge : std_logic;
signal cmd_edge1 : std_logic;
signal cmd_edge2 : std_logic;
signal cmd_ack : std_logic;
signal cmd_ack1 : std_logic;
signal cmd_ack2 : std_logic;
signal cmd : std_logic_vector(5 downto 0);
signal addr_sync : std_logic_vector(15 downto 0);
signal addr_inst : std_logic_vector(15 downto 0);
signal Addr1 : std_logic_vector(15 downto 0);
signal Data1 : std_logic_vector(7 downto 0);
signal ext_clk : std_logic;
signal timer0Count : std_logic_vector(23 downto 0);
signal timer1Count : std_logic_vector(23 downto 0);
signal cycleCount : std_logic_vector(23 downto 0);
signal instrCount : std_logic_vector(23 downto 0);
signal single : std_logic;
signal reset : std_logic;
signal step : std_logic;
signal bw_status : std_logic_vector(3 downto 0);
signal bw_status1 : std_logic_vector(3 downto 0);
signal auto_inc : std_logic;
signal brkpt_reg : std_logic_vector(num_comparators * reg_width - 1 downto 0);
signal brkpt_enable : std_logic;
signal brkpt_active : std_logic;
signal brkpt_active1 : std_logic;
signal watch_active : std_logic;
signal fifo_din : std_logic_vector(fifo_width - 1 downto 0);
signal fifo_dout : std_logic_vector(fifo_width - 1 downto 0);
signal fifo_empty : std_logic;
signal fifo_full : std_logic;
signal fifo_not_empty1 : std_logic;
signal fifo_not_empty2 : std_logic;
signal fifo_rd : std_logic;
signal fifo_rd_en : std_logic;
signal fifo_wr : std_logic;
signal fifo_wr_en : std_logic;
signal fifo_rst : std_logic;
signal memory_rd : std_logic;
signal memory_wr : std_logic;
signal io_rd : std_logic;
signal io_wr : std_logic;
signal exec : std_logic;
signal addr_dout_reg : std_logic_vector(23 downto 0);
signal din_reg : std_logic_vector(7 downto 0);
signal Rdy_int : std_logic;
signal unused_d6 : std_logic;
signal unused_d7 : std_logic;
signal last_done : std_logic;
signal cmd_done : std_logic;
signal reset_counter : std_logic_vector(9 downto 0);
signal dropped_counter : std_logic_vector(3 downto 0);
signal timer_mode : std_logic_vector(1 downto 0);
begin
inst_oho_dy1 : entity work.Oho_Dy1 port map (
dy_clock => clock_avr,
dy_rst_n => '1',
dy_data => dy_data,
dy_update => '1',
dy_frame => open,
dy_frameend => open,
dy_frameend_c => open,
dy_pwm => "1010",
dy_counter => dy_counter,
dy_sclk => tdin,
dy_ser => tcclk,
dy_rclk => tmosi
);
Inst_AVR8: entity work.AVR8
generic map(
CDATAMEMSIZE => avr_data_mem_size,
CPROGMEMSIZE => avr_prog_mem_size
)
port map(
clk16M => clock_avr,
nrst => nrst_avr,
portain => PdcData,
portaout => open,
-- Command Port
portbin(0) => '0',
portbin(1) => '0',
portbin(2) => '0',
portbin(3) => '0',
portbin(4) => '0',
portbin(5) => '0',
portbin(6) => '0',
portbin(7) => '0',
portbout(0) => cmd(0),
portbout(1) => cmd(1),
portbout(2) => cmd(2),
portbout(3) => cmd(3),
portbout(4) => cmd(4),
portbout(5) => cmd(5),
portbout(6) => cmd_edge,
portbout(7) => open,
-- Status Port
portdin(0) => '0',
portdin(1) => '0',
portdin(2) => '0',
portdin(3) => '0',
portdin(4) => '0',
portdin(5) => '0',
portdin(6) => cmd_ack2,
portdin(7) => fifo_not_empty2,
portdout(0) => muxsel(0),
portdout(1) => muxsel(1),
portdout(2) => muxsel(2),
portdout(3) => muxsel(3),
portdout(4) => muxsel(4),
portdout(5) => muxsel(5),
portdout(6) => unused_d6,
portdout(7) => unused_d7,
-- Mux Port
portein => mux,
porteout => open,
spi_mosio => open,
spi_scko => open,
spi_misoi => '0',
rxd => avr_RxD,
txd => avr_TxD
);
-- Syncronise signals crossing busmon_clk / clock_avr boundary
process (clock_avr)
begin
if rising_edge(clock_avr) then
fifo_not_empty1 <= not fifo_empty;
fifo_not_empty2 <= fifo_not_empty1;
cmd_ack1 <= cmd_ack;
cmd_ack2 <= cmd_ack1;
end if;
end process;
WatchEvents_inst : entity work.WatchEvents port map(
clk => busmon_clk,
srst => fifo_rst,
din => fifo_din,
wr_en => fifo_wr_en,
rd_en => fifo_rd_en,
dout => fifo_dout,
full => fifo_full,
empty => fifo_empty
);
fifo_wr_en <= fifo_wr and busmon_clken;
fifo_rd_en <= fifo_rd and busmon_clken;
-- The fifo is writen the cycle after the break point
-- Addr1 is the address bus delayed by 1 cycle
-- DataWr1 is the data being written delayed by 1 cycle
-- DataRd is the data being read, that is already one cycle late
-- bw_state1(1) is 1 for writes, and 0 for reads
fifo_din <= instrCount & dropped_counter & bw_status1 & Data1 & Addr1 & addr_inst;
-- Implement a 4-bit saturating counter of the number of dropped events
process (busmon_clk)
begin
if rising_edge(busmon_clk) then
if busmon_clken = '1' then
if fifo_rst = '1' then
dropped_counter <= x"0";
elsif fifo_wr_en = '1' then
if fifo_full = '1' then
if dropped_counter /= x"F" then
dropped_counter <= dropped_counter + 1;
end if;
else
dropped_counter <= x"0";
end if;
end if;
end if;
end if;
end process;
led_trig0 <= trig(0);
led_trig1 <= trig(1);
led_bkpt <= brkpt_active;
nrst_avr <= not sw_reset_avr;
-- OHO DY1 Display for Testing
dy_data(0) <= hex & "0000" & Addr(3 downto 0);
dy_data(1) <= hex & "0000" & Addr(7 downto 4);
dy_data(2) <= hex & "0000" & "00" & sw_reset_avr & sw_reset_cpu;
mux <= addr_inst(7 downto 0) when muxsel = 0 else
addr_inst(15 downto 8) when muxsel = 1 else
din_reg when muxsel = 2 else
instrCount(23 downto 16) when muxsel = 3 else
instrCount(7 downto 0) when muxsel = 4 else
instrCount(15 downto 8) when muxsel = 5 else
fifo_dout(7 downto 0) when muxsel = 6 else
fifo_dout(15 downto 8) when muxsel = 7 else
fifo_dout(23 downto 16) when muxsel = 8 else
fifo_dout(31 downto 24) when muxsel = 9 else
fifo_dout(39 downto 32) when muxsel = 10 else
fifo_dout(47 downto 40) when muxsel = 11 else
fifo_dout(55 downto 48) when muxsel = 12 else
fifo_dout(63 downto 56) when muxsel = 13 else
fifo_dout(71 downto 64) when muxsel = 14 else
Regs(8 * to_integer(unsigned(muxsel(4 downto 0))) + 7 downto 8 * to_integer(unsigned(muxsel(4 downto 0))));
-- Combinatorial set of comparators to decode breakpoint/watch addresses
brkpt_active_process: process (brkpt_reg, brkpt_enable, Addr, Sync, Rd_n, Wr_n, RdIO_n, WrIO_n, trig)
variable i : integer;
variable reg_addr : std_logic_vector(15 downto 0);
variable reg_mask : std_logic_vector(15 downto 0);
variable reg_mode_bmr : std_logic;
variable reg_mode_bmw : std_logic;
variable reg_mode_bir : std_logic;
variable reg_mode_biw : std_logic;
variable reg_mode_bx : std_logic;
variable reg_mode_wmr : std_logic;
variable reg_mode_wmw : std_logic;
variable reg_mode_wir : std_logic;
variable reg_mode_wiw : std_logic;
variable reg_mode_wx : std_logic;
variable reg_mode_all : std_logic_vector(9 downto 0);
variable bactive : std_logic;
variable wactive : std_logic;
variable status : std_logic_vector(3 downto 0);
variable trigval : std_logic;
begin
bactive := '0';
wactive := '0';
status := (others => '0');
if (brkpt_enable = '1') then
for i in 0 to num_comparators - 1 loop
reg_addr := brkpt_reg(i * reg_width + 15 downto i * reg_width);
reg_mask := brkpt_reg(i * reg_width + 31 downto i * reg_width + 16);
reg_mode_bmr := brkpt_reg(i * reg_width + 32);
reg_mode_wmr := brkpt_reg(i * reg_width + 33);
reg_mode_bmw := brkpt_reg(i * reg_width + 34);
reg_mode_wmw := brkpt_reg(i * reg_width + 35);
reg_mode_bir := brkpt_reg(i * reg_width + 36);
reg_mode_wir := brkpt_reg(i * reg_width + 37);
reg_mode_biw := brkpt_reg(i * reg_width + 38);
reg_mode_wiw := brkpt_reg(i * reg_width + 39);
reg_mode_bx := brkpt_reg(i * reg_width + 40);
reg_mode_wx := brkpt_reg(i * reg_width + 41);
reg_mode_all := brkpt_reg(i * reg_width + 41 downto i * reg_width + 32);
trigval := brkpt_reg(i * reg_width + 42 + to_integer(unsigned(trig)));
if (trigval = '1' and ((Addr and reg_mask) = reg_addr or (reg_mode_all = "0000000000"))) then
if (Sync = '1') then
if (reg_mode_bx = '1') then
bactive := '1';
status := "1000";
elsif (reg_mode_wx = '1') then
wactive := '1';
status := "1001";
end if;
elsif (Rd_n = '0') then
if (reg_mode_bmr = '1') then
bactive := '1';
status := "0000";
elsif (reg_mode_wmr = '1') then
wactive := '1';
status := "0001";
end if;
elsif (Wr_n = '0') then
if (reg_mode_bmw = '1') then
bactive := '1';
status := "0010";
elsif (reg_mode_wmw = '1') then
wactive := '1';
status := "0011";
end if;
elsif (RdIO_n = '0') then
if (reg_mode_bir = '1') then
bactive := '1';
status := "0100";
elsif (reg_mode_wir = '1') then
wactive := '1';
status := "0101";
end if;
elsif (WrIO_n = '0') then
if (reg_mode_biw = '1') then
bactive := '1';
status := "0110";
elsif (reg_mode_wiw = '1') then
wactive := '1';
status := "0111";
end if;
end if;
end if;
end loop;
end if;
watch_active <= wactive;
brkpt_active <= bactive;
bw_status <= status;
end process;
-- CPU Control Commands
-- 00000x Enable/Disable single stepping
-- 00001x Enable/Disable breakpoints / watches
-- 00010x Load breakpoint / watch register
-- 00011x Reset CPU
-- 001000 Singe Step CPU
-- 001001 Read FIFO
-- 001010 Reset FIFO
-- 001011 Unused
-- 00110x Load address/data register
-- 00111x Unused
-- 010000 Read Memory
-- 010001 Read Memory and Auto Inc Address
-- 010010 Write Memory
-- 010011 Write Memory and Auto Inc Address
-- 010100 Read IO
-- 010101 Read IO and Auto Inc Address
-- 010110 Write IO
-- 010111 Write IO and Auto Inc Address
-- 011000 Execute 6502 instruction
-- 0111xx Unused
-- 011x1x Unused
-- 011xx1 Unused
-- 100xxx Special
-- 1010xx Timer Mode
-- 00 - count cpu cycles where clken = 1 and CountCycle = 1
-- 01 - count cpu cycles where clken = 1 (ignoring CountCycle)
-- 10 - free running timer, using busmon_clk as the source
-- 11 - free running timer, using trig0 as the source
-- Use trig0 to drive a free running counter for absolute timings
ext_clk <= trig(0);
timer1Process: process (ext_clk)
begin
if rising_edge(ext_clk) then
timer1Count <= timer1Count + 1;
end if;
end process;
cpuProcess: process (busmon_clk)
begin
if rising_edge(busmon_clk) then
timer0Count <= timer0Count + 1;
if busmon_clken = '1' then
-- Cycle counter
if (cpu_reset_n = '0') then
cycleCount <= (others => '0');
elsif (CountCycle = '1' or timer_mode(0) = '1') then
cycleCount <= cycleCount + 1;
end if;
-- Command processing
cmd_edge1 <= cmd_edge;
cmd_edge2 <= cmd_edge1;
fifo_rd <= '0';
fifo_wr <= '0';
fifo_rst <= '0';
memory_rd <= '0';
memory_wr <= '0';
io_rd <= '0';
io_wr <= '0';
exec <= '0';
SS_Step <= '0';
if (cmd_edge2 /= cmd_edge1) then
if (cmd(5 downto 1) = "00000") then
single <= cmd(0);
end if;
if (cmd(5 downto 1) = "00001") then
brkpt_enable <= cmd(0);
end if;
if (cmd(5 downto 1) = "00010") then
brkpt_reg <= cmd(0) & brkpt_reg(brkpt_reg'length - 1 downto 1);
end if;
if (cmd(5 downto 1) = "00110") then
addr_dout_reg <= cmd(0) & addr_dout_reg(addr_dout_reg'length - 1 downto 1);
end if;
if (cmd(5 downto 1) = "00011") then
reset <= cmd(0);
end if;
if (cmd(5 downto 0) = "01001") then
fifo_rd <= '1';
end if;
if (cmd(5 downto 0) = "01010") then
fifo_rst <= '1';
end if;
if (cmd(5 downto 1) = "01000") then
memory_rd <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 1) = "01001") then
memory_wr <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 1) = "01010") then
io_rd <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 1) = "01011") then
io_wr <= '1';
auto_inc <= cmd(0);
end if;
if (cmd(5 downto 0) = "011000") then
exec <= '1';
end if;
if (cmd(5 downto 3) = "100") then
Special <= cmd(2 downto 0);
end if;
if (cmd(5 downto 2) = "1010") then
timer_mode <= cmd(1 downto 0);
end if;
-- Acknowlege certain commands immediately
if cmd(5 downto 4) /= "01" then
cmd_ack <= not cmd_ack;
end if;
end if;
if cmd_done = '1' then
-- Acknowlege memory access commands when thet complete
cmd_ack <= not cmd_ack;
-- Auto increment the memory address reg the cycle after a rd/wr
if auto_inc = '1' then
addr_dout_reg(23 downto 8) <= addr_dout_reg(23 downto 8) + 1;
end if;
end if;
-- Single Stepping
if (brkpt_active = '1') then
single <= '1';
end if;
if ((single = '0') or (cmd_edge2 /= cmd_edge1 and cmd = "001000")) then
Rdy_int <= (not brkpt_active);
SS_Step <= (not brkpt_active);
else
Rdy_int <= (not Sync);
end if;
-- Latch instruction address for the whole cycle
if (Sync = '1') then
addr_inst <= Addr;
if timer_mode = "10" then
instrCount <= timer0Count;
elsif timer_mode = "11" then
instrCount <= timer1Count;
else
instrCount <= cycleCount;
end if;
end if;
-- Breakpoints and Watches written to the FIFO
brkpt_active1 <= brkpt_active;
bw_status1 <= bw_status;
if watch_active = '1' or (brkpt_active = '1' and brkpt_active1 = '0') then
fifo_wr <= '1';
Addr1 <= Addr;
end if;
end if;
end if;
end process;
dataProcess: process (cpu_clk)
begin
if rising_edge(cpu_clk) then
if cpu_clken = '1' then
-- Latch the data bus for use in watches
Data1 <= Data;
-- Latch memory read in response to a read command
if (Done = '1') then
din_reg <= DataIn;
end if;
-- Delay the increnting of the address by one cycle
last_done <= Done;
if Done = '1' and last_done = '0' then
cmd_done <= '1';
else
cmd_done <= '0';
end if;
end if;
end if;
end process;
Rdy <= Rdy_int;
RdMemOut <= memory_rd;
WrMemOut <= memory_wr;
RdIOOut <= io_rd;
WrIOOut <= io_wr;
AddrOut <= addr_dout_reg(23 downto 8);
DataOut <= addr_dout_reg(7 downto 0);
SS_Single <= single;
ExecOut <= exec;
-- Reset Logic
-- Generate a short (~1ms @ 1MHz) power up reset pulse
--
-- This is in case FPGA configuration takes longer than
-- the length of the host system reset pulse.
--
-- Some 6502 cores (particularly the AlanD core) needs
-- reset to be asserted to start.
-- Debounce nRSTin using clock_avr as this is always 16MHz
-- nrst1 is the possibly glitchy input
-- nrst2 is the filtered output
process(clock_avr)
begin
if rising_edge(clock_avr) then
-- Syncronise nRSTin
nrst1 <= nRSTin and (not sw_reset_cpu);
-- De-glitch NRST
if nrst1 = '0' then
nrst_counter <= to_unsigned(0, nrst_counter'length);
nrst2 <= '0';
elsif nrst_counter(nrst_counter'high) = '0' then
nrst_counter <= nrst_counter + 1;
else
nrst2 <= '1';
end if;
end if;
end process;
process(cpu_clk)
begin
if rising_edge(cpu_clk) then
if cpu_clken = '1' then
if reset_counter(reset_counter'high) = '0' then
reset_counter <= reset_counter + 1;
end if;
nrst3 <= nrst2 and reset_counter(reset_counter'high) and (not reset);
cpu_reset_n <= nrst3;
end if;
end if;
end process;
nRSTout <= cpu_reset_n;
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity tb_and6 is
end tb_and6;
architecture behav of tb_and6 is
signal i0, i1, i2, i3, i4, i5 : std_logic;
signal o : std_logic;
begin
dut : entity work.and6
port map (i0 => i0, i1 => i1, i2 => i2, i3 => i4, i4 => i4,
i5 => i5, o => o);
process
constant v0 : std_logic_vector := b"1011";
constant v1 : std_logic_vector := b"1111";
constant v2 : std_logic_vector := b"1111";
constant v3 : std_logic_vector := b"1111";
constant v4 : std_logic_vector := b"1111";
constant v5 : std_logic_vector := b"1101";
constant ov : std_logic_vector := b"1001";
begin
for i in ov'range loop
i0 <= v0 (i);
i1 <= v1 (i);
i2 <= v2 (i);
i3 <= v3 (i);
i4 <= v4 (i);
i5 <= v5 (i);
wait for 1 ns;
assert o = ov(i) severity failure;
end loop;
wait;
end process;
end behav;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity prova is
port(
entrada : in std_logic_vector (6 downto 0) := "0000000";
display : out std_logic_vector (6 downto 0)
);
end prova;
architecture Behavioral of prova is
signal bcd : std_logic_vector (6 downto 0);
begin
-- BCD.
process (entrada)
begin
if (entrada = "0000000") then -- 0
bcd <= "1111110";
elsif (entrada = "0000001") then -- 1
bcd <= "0110000";
elsif (entrada = "0000010") then -- 2
bcd <= "1101101";
elsif (entrada = "0000100") then -- 3
bcd <= "1111001";
elsif (entrada = "0001000") then -- 4
bcd <= "0110010";
elsif (entrada = "0010000") then -- 5
bcd <= "1011010";
elsif (entrada = "0100000") then -- 6
bcd <= "1011111";
else
bcd <= "1110000";
end if;
end process;
display <= bcd;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY principal_tb IS
END principal_tb;
ARCHITECTURE behavior OF principal_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MODULOPRINCIPAL
PORT(
rst : IN std_logic;
CLK : IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MODULOPRINCIPAL PORT MAP (
rst => rst,
CLK => CLK,
ALURESULT => ALURESULT
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
wait for 700 ns;
rst<='1';
wait;
end process;
END;
|
-- NEED RESULT: ARCH00619: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00619: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00619.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00619.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00619: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00619: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00619: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00619: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00619: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00619: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00619
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00619(ARCH00619)
-- ENT00619_Test_Bench(ARCH00619_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00619 is
end ENT00619 ;
--
--
architecture ARCH00619 of ENT00619 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr3_vector_select : select_type := 1 ;
--
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
procedure P1
(signal s_st_arr2_vector : in st_arr2_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr2_vector(lowb)(highb,false) <= transport
-- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ;
--
when 4
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00619" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00619" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr2_vector_cnt + 1 ;
--
end ;
--
procedure P2
(signal s_st_arr3_vector : in st_arr3_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr3_vector_cnt is
when 0
=> null ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr3_vector(highb)(lowb,true) <= transport
-- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ;
--
when 4
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00619" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00619" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00619" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr3_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr3_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_arr2_vector ,
st_arr2_vector_select ,
s_st_arr2_vector_savt ,
chk_st_arr2_vector ,
s_st_arr2_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb)(highb,false) <= transport
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb)(highb,false) after 5 ns when 3 ;
--
CHG2 :
P2(
s_st_arr3_vector ,
st_arr3_vector_select ,
s_st_arr3_vector_savt ,
chk_st_arr3_vector ,
s_st_arr3_vector_cnt ) ;
--
PGEN_CHKP_2 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_arr3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_arr3_vector_select select
s_st_arr3_vector(highb)(lowb,true) <= transport
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns
when 1,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 2,
--
c_st_arr3_vector_1(highb)(lowb,true) after 5 ns when 3 ;
--
end ARCH00619 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00619_Test_Bench is
end ENT00619_Test_Bench ;
--
--
architecture ARCH00619_Test_Bench of ENT00619_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00619 ( ARCH00619 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00619_Test_Bench ;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
-- SW8 (GLOBAL RESET) resets LCD
ENTITY LCD_Display IS
-- Enter number of live Hex hardware data values to display
-- (do not count ASCII character constants)
GENERIC(Num_Hex_Digits: Integer:= 8);
-----------------------------------------------------------------------
-- LCD Displays 16 Characters on 2 lines
-- LCD_display string is an ASCII character string entered in hex for
-- the two lines of the LCD Display (See ASCII to hex table below)
-- Edit LCD_Display_String entries above to modify display
-- Enter the ASCII character's 2 hex digit equivalent value
-- (see table below for ASCII hex values)
-- To display character assign ASCII value to LCD_display_string(x)
-- To skip a character use X"20" (ASCII space)
-- To dislay "live" hex values from hardware on LCD use the following:
-- make array element for that character location X"0" & 4-bit field from Hex_Display_Data
-- state machine sees X"0" in high 4-bits & grabs the next lower 4-bits from Hex_Display_Data input
-- and performs 4-bit binary to ASCII conversion needed to print a hex digit
-- Num_Hex_Digits must be set to the count of hex data characters (ie. "00"s) in the display
-- Connect hardware bits to display to Hex_Display_Data input
-- To display less than 32 characters, terminate string with an entry of X"FE"
-- (fewer characters may slightly increase the LCD's data update rate)
-------------------------------------------------------------------
-- ASCII HEX TABLE
-- Hex Low Hex Digit
-- Value 0 1 2 3 4 5 6 7 8 9 A B C D E F
------\----------------------------------------------------------------
--H 2 | SP ! " # $ % & ' ( ) * + , - . /
--i 3 | 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
--g 4 | @ A B C D E F G H I J K L M N O
--h 5 | P Q R S T U V W X Y Z [ \ ] ^ _
-- 6 | ` a b c d e f g h i j k l m n o
-- 7 | p q r s t u v w x y z { | } ~ DEL
-----------------------------------------------------------------------
-- Example "A" is row 4 column 1, so hex value is X"41"
-- *see LCD Controller's Datasheet for other graphics characters available
--
PORT(reset, clk_48Mhz : IN STD_LOGIC;
Hex_Display_Data : IN STD_LOGIC_VECTOR((Num_Hex_Digits*4)-1 DOWNTO 0);
Display_Data : IN STD_LOGIC_VECTOR(((Num_Hex_Digits*4)*4)-1 DOWNTO 0);
LCD_RS, LCD_EN : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY LCD_Display;
ARCHITECTURE a OF LCD_Display IS
TYPE character_string IS ARRAY ( 0 TO 31 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 );
TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, Print_String,
LINE2, RETURN_HOME, DROP_LCD_EN, RESET1, RESET2,
RESET3, DISPLAY_OFF, DISPLAY_CLEAR);
SIGNAL state, next_command: STATE_TYPE;
SIGNAL LCD_display_string : character_string;
-- Enter new ASCII hex data above for LCD Display
SIGNAL DATA_BUS_VALUE, Next_Char: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CLK_COUNT_400HZ: STD_LOGIC_VECTOR(19 DOWNTO 0);
SIGNAL CHAR_COUNT: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL CLK_400HZ_Enable,LCD_RW_INT : STD_LOGIC;
SIGNAL Line1_chars, Line2_chars: STD_LOGIC_VECTOR(127 DOWNTO 0);
BEGIN
LCD_display_string <= (
-- ASCII hex values for LCD Display
-- Enter Live Hex Data Values from hardware here
-- LCD DISPLAYS THE FOLLOWING:
------------------------------
--| Count=XX |
--| Data =XXXXXXXX |
------------------------------
-- Line 1
X"43",X"6F",X"75",X"6E",X"74",X"3D",
X"0" & Hex_Display_Data(7 DOWNTO 4),X"0" & Hex_Display_Data(3 DOWNTO 0),
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 2
X"44",X"41",X"54",X"41",X"20",X"3D",
X"0" & Display_Data(31 DOWNTO 28),
X"0" & Display_Data(27 DOWNTO 24),
X"0" & Display_Data(23 DOWNTO 20),
X"0" & Display_Data(19 DOWNTO 16),
X"0" & Display_Data(15 DOWNTO 12),
X"0" & Display_Data(11 DOWNTO 8),
X"0" & Display_Data(7 DOWNTO 4),
X"0" & Display_Data(3 DOWNTO 0),
X"20",X"20");
-- BIDIRECTIONAL TRI STATE LCD DATA BUS
DATA_BUS <= DATA_BUS_VALUE WHEN LCD_RW_INT = '0' ELSE "ZZZZZZZZ";
-- get next character in display string
Next_Char <= LCD_display_string(CONV_INTEGER(CHAR_COUNT));
LCD_RW <= LCD_RW_INT;
PROCESS
BEGIN
WAIT UNTIL CLK_48MHZ'EVENT AND CLK_48MHZ = '1';
IF RESET = '0' THEN
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '0';
ELSE
IF CLK_COUNT_400HZ < X"0EA60" THEN
CLK_COUNT_400HZ <= CLK_COUNT_400HZ + 1;
CLK_400HZ_Enable <= '0';
ELSE
CLK_COUNT_400HZ <= X"00000";
CLK_400HZ_Enable <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (CLK_48MHZ, reset)
BEGIN
IF reset = '0' THEN
state <= RESET1;
DATA_BUS_VALUE <= X"38";
next_command <= RESET2;
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '1';
ELSIF CLK_48MHZ'EVENT AND CLK_48MHZ = '1' THEN
-- State Machine to send commands and data to LCD DISPLAY
IF CLK_400HZ_Enable = '1' THEN
CASE state IS
-- Set Function to 8-bit transfer and 2 line display with 5x8 Font size
-- see Hitachi HD44780 family data sheet for LCD command and timing details
WHEN RESET1 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= RESET2;
CHAR_COUNT <= "00000";
WHEN RESET2 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= RESET3;
WHEN RESET3 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= FUNC_SET;
-- EXTRA STATES ABOVE ARE NEEDED FOR RELIABLE PUSHBUTTON RESET OF LCD
WHEN FUNC_SET =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"38";
state <= DROP_LCD_EN;
next_command <= DISPLAY_OFF;
-- Turn off Display and Turn off cursor
WHEN DISPLAY_OFF =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"08";
state <= DROP_LCD_EN;
next_command <= DISPLAY_CLEAR;
-- Clear Display and Turn off cursor
WHEN DISPLAY_CLEAR =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"01";
state <= DROP_LCD_EN;
next_command <= DISPLAY_ON;
-- Turn on Display and Turn off cursor
WHEN DISPLAY_ON =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"0C";
state <= DROP_LCD_EN;
next_command <= MODE_SET;
-- Set write mode to auto increment address and move cursor to the right
WHEN MODE_SET =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"06";
state <= DROP_LCD_EN;
next_command <= Print_String;
-- Write ASCII hex character in first LCD character location
WHEN Print_String =>
state <= DROP_LCD_EN;
LCD_EN <= '1';
LCD_RS <= '1';
LCD_RW_INT <= '0';
-- ASCII character to output
IF Next_Char(7 DOWNTO 4) /= X"0" THEN
DATA_BUS_VALUE <= Next_Char;
ELSE
-- Convert 4-bit value to an ASCII hex digit
IF Next_Char(3 DOWNTO 0) >9 THEN
-- ASCII A...F
DATA_BUS_VALUE <= X"4" & (Next_Char(3 DOWNTO 0)-9);
ELSE
-- ASCII 0...9
DATA_BUS_VALUE <= X"3" & Next_Char(3 DOWNTO 0);
END IF;
END IF;
state <= DROP_LCD_EN;
-- Loop to send out 32 characters to LCD Display (16 by 2 lines)
IF (CHAR_COUNT < 31) AND (Next_Char /= X"FE") THEN
CHAR_COUNT <= CHAR_COUNT +1;
ELSE
CHAR_COUNT <= "00000";
END IF;
-- Jump to second line?
IF CHAR_COUNT = 15 THEN next_command <= line2;
-- Return to first line?
ELSIF (CHAR_COUNT = 31) OR (Next_Char = X"FE") THEN
next_command <= return_home;
ELSE next_command <= Print_String; END IF;
-- Set write address to line 2 character 1
WHEN LINE2 =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"C0";
state <= DROP_LCD_EN;
next_command <= Print_String;
-- Return write address to first character postion on line 1
WHEN RETURN_HOME =>
LCD_EN <= '1';
LCD_RS <= '0';
LCD_RW_INT <= '0';
DATA_BUS_VALUE <= X"80";
state <= DROP_LCD_EN;
next_command <= Print_String;
-- The next three states occur at the end of each command or data transfer to the LCD
-- Drop LCD E line - falling edge loads inst/data to LCD controller
WHEN DROP_LCD_EN =>
LCD_EN <= '0';
state <= HOLD;
-- Hold LCD inst/data valid after falling edge of E line
WHEN HOLD =>
state <= next_command;
END CASE;
END IF;
END IF;
END PROCESS;
END a;
|
library ieee;
use ieee.std_logic_1164.all;
entity theunit is
port (dout : out std_ulogic);
end;
architecture rtl of theunit is
subtype thenum_t is integer range 0 to 1;
type rec_t is record
-- NOTE: changing order of these members prevents crash
data0 : std_ulogic;
bankm : std_ulogic_vector(thenum_t);
end record;
signal r : rec_t;
begin
thecomb : process(r)
variable v : rec_t;
variable thenum : thenum_t := 1;
begin
v.data0 := '1';
v.bankm := (others => '1');
-- NOTE: removing any of the lines below prevents crash
v.bankm(thenum) := '0';
r <= v;
dout <= r.data0;
end process;
end;
|
architecture RTL of FIFO is
begin
block_label : block is begin end block BLOCK_LABEL;
BLOCK_LABEL : BLOCK IS BEGIN END BLOCK BLOCK_LABEL;
end architecture RTL;
|
------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------------------------------------
configuration WrapReconfModule_cfg of ADT7410_tb is
for behavior
for DUT : ADT7410
for WrapReconfModule
for MyReconfigLogic_0 : MyReconfigLogic
for struct
for all : ParamOutReg
use entity work.ParamOutReg(rtl)
port map (
Reset_n_i => '0',
Clk_i => '0',
Enable_i => '0',
ParamWrData_i => (others => '0'),
Param_o => open
);
end for;
end for;
end for;
end for;
end for;
end for;
end WrapReconfModule_cfg;
|
library ieee;
use ieee.std_logic_1164.all;
entity divider_2 is
port( data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector( 10 downto 0));
end divider_2;
architecture behavior of divider_2 is
begin
data_out(6 downto 0)<= data_in(7 downto 1);
data_out(10 downto 7)<=(others=>data_in(7));
end behavior; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:15:44 06/26/2017
-- Design Name:
-- Module Name: /media/sf_SistemiEmbedded/workbench/ISE/SE/complex_modulus/tb_complex_abs.vhd
-- Project Name: complex_modulus
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: complex_abs
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_complex_abs IS
END tb_complex_abs;
ARCHITECTURE behavior OF tb_complex_abs IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT complex_abs
GENERIC ( complex_width : natural := 32 );
PORT(
clock : IN std_logic;
reset_n : IN std_logic;
enable : IN std_logic;
complex_value : IN std_logic_vector(complex_width-1 downto 0);
abs_value : OUT std_logic_vector(complex_width-1 downto 0);
done : OUT std_logic
);
END COMPONENT;
constant complex_width : natural := 32;
--Inputs
signal clock : std_logic := '0';
signal reset_n : std_logic := '0';
signal enable : std_logic := '0';
signal complex_value : std_logic_vector(complex_width-1 downto 0) := (others => '0');
--Outputs
signal abs_value : std_logic_vector(complex_width-1 downto 0);
signal done : std_logic;
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: complex_abs PORT MAP (
clock => clock,
reset_n => reset_n,
enable => enable,
complex_value => complex_value,
abs_value => abs_value,
done => done
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
enable <= '1';
wait for 5 ns;
complex_value <= x"00050004"; -- 0x00000029
wait for 5 ns;
reset_n <= '1';
wait until done = '1';
complex_value <= x"00020003"; -- 0x0000000D
wait until done = '1';
complex_value <= x"FFFF0006"; -- 0x00000025
wait until done = '1';
complex_value <= x"00051000"; -- 0x01000019
wait;
end process;
END;
|
entity test is
type t is range 0 to 1.0E+2;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity exit02 is
port (val : std_logic_vector (3 downto 0);
res : out integer);
end exit02;
architecture behav of exit02 is
function ffs (v : std_logic_vector (3 downto 0)) return natural
is
variable r : natural;
begin
r := 4;
for i in v'reverse_range loop
if v (i) = '1' then
r := i;
exit;
end if;
end loop;
return r;
end ffs;
begin
res <= ffs (val);
end behav;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for INST_AB_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ab_e-e.vhd,v 1.1 2007/03/03 17:32:14 wig Exp $
-- $Date: 2007/03/03 17:32:14 $
-- $Log: inst_ab_e-e.vhd,v $
-- Revision 1.1 2007/03/03 17:32:14 wig
-- Fixed case in UNIX, too for testcase case
--
-- Revision 1.2 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity INST_AB_e
--
entity INST_AB_e is
-- Generics:
-- No Generated Generics for Entity INST_AB_e
-- Generated Port Declaration:
-- No Generated Port for Entity INST_AB_e
end INST_AB_e;
--
-- End of Generated Entity INST_AB_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity encrypt is
port( data_in: in std_logic_vector(0 to 63);
key: in std_logic_vector(0 to 63);
data_out: out std_logic_vector(0 to 63));
end encrypt;
architecture behavior of encrypt is
component initial_permutation
port( data_in: in std_logic_vector(0 to 63);
permuted_right_half: out std_logic_vector(0 to 31);
permuted_left_half: out std_logic_vector(0 to 31));
end component;
component key_permutation_1
port( key: in std_logic_vector(0 to 63);
permuted_left_key: out std_logic_vector(0 to 27);
permuted_right_key: out std_logic_vector(0 to 27));
end component;
component subkey_production
generic(shifting_parameter: std_logic_vector(0 to 1);
left_or_right: std_logic_vector(0 to 0));
port( left_key_in: in std_logic_vector(0 to 27);
right_key_in: in std_logic_vector(0 to 27);
subkey: out std_logic_vector(0 to 47);
left_key_out: out std_logic_vector(0 to 27);
right_key_out: out std_logic_vector(0 to 27));
end component;
component round
port( left_plain: in std_logic_vector(0 to 31);
right_plain: in std_logic_vector(0 to 31);
subkey: in std_logic_vector(0 to 47);
left_data_out: out std_logic_vector(0 to 31);
right_data_out: out std_logic_vector(0 to 31));
end component;
component swap_left_right_64_bits
port( data_in_left: in std_logic_vector(0 to 31);
data_in_right: in std_logic_vector(0 to 31);
data_out_left: out std_logic_vector(0 to 31);
data_out_right: out std_logic_vector(0 to 31));
end component;
component reverse_initial_permutation
port( permuted_left_half: in std_logic_vector(0 to 31);
permuted_right_half: in std_logic_vector(0 to 31);
data_out: out std_logic_vector(0 to 63));
end component;
signal permuted_right_plain_text: std_logic_vector(0 to 31);
signal permuted_left_plain_text: std_logic_vector(0 to 31);
signal left_key: std_logic_vector(0 to 27);
signal right_key: std_logic_vector(0 to 27);
signal subkey1,subkey2,subkey3,subkey4,subkey5,subkey6,subkey7,subkey8,subkey9,subkey10,subkey11,subkey12,subkey13,subkey14,subkey15,subkey16: std_logic_vector(0 to 47);
signal left_key_1,left_key_2,left_key_3,left_key_4,left_key_5,left_key_6,left_key_7,left_key_8,left_key_9,left_key_10,left_key_11,left_key_12,left_key_13,left_key_14,left_key_15,left_key_16: std_logic_vector(0 to 27);
signal right_key_1,right_key_2,right_key_3,right_key_4,right_key_5,right_key_6,right_key_7,right_key_8,right_key_9,right_key_10,right_key_11,right_key_12,right_key_13,right_key_14,right_key_15,right_key_16: std_logic_vector(0 to 27);
signal left_plain_1,left_plain_2,left_plain_3,left_plain_4,left_plain_5,left_plain_6,left_plain_7,left_plain_8,left_plain_9,left_plain_10,left_plain_11,left_plain_12,left_plain_13,left_plain_14,left_plain_15,left_plain_16: std_logic_vector(0 to 31);
signal right_plain_1,right_plain_2,right_plain_3,right_plain_4,right_plain_5,right_plain_6,right_plain_7,right_plain_8,right_plain_9,right_plain_10,right_plain_11,right_plain_12,right_plain_13,right_plain_14,right_plain_15,right_plain_16: std_logic_vector(0 to 31);
signal swaped_plain_text_left,swaped_plain_text_right: std_logic_vector(0 to 31);
begin
s1: initial_permutation port map(
data_in=>data_in,
permuted_right_half=>permuted_right_plain_text,
permuted_left_half=>permuted_left_plain_text);
s2: key_permutation_1 port map(
key=>key,
permuted_left_key=>left_key,
permuted_right_key=>right_key);
s3: subkey_production generic map(
shifting_parameter=>"01",
left_or_right=>"0")
port map( left_key_in=>left_key,
right_key_in=>right_key,
subkey=>subkey1,
left_key_out=>left_key_1,
right_key_out=>right_key_1);
s4: round port map(
left_plain=>permuted_left_plain_text,
right_plain=>permuted_right_plain_text,
subkey=>subkey1,
left_data_out=>left_plain_1,
right_data_out=>right_plain_1);
s5: subkey_production generic map(
shifting_parameter=>"01",
left_or_right=>"0")
port map( left_key_in=>left_key_1,
right_key_in=>right_key_1,
subkey=>subkey2,
left_key_out=>left_key_2,
right_key_out=>right_key_2);
s6: round port map(
left_plain=>left_plain_1,
right_plain=>right_plain_1,
subkey=>subkey2,
left_data_out=>left_plain_2,
right_data_out=>right_plain_2);
s7: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_2,
right_key_in=>right_key_2,
subkey=>subkey3,
left_key_out=>left_key_3,
right_key_out=>right_key_3);
s8: round port map(
left_plain=>left_plain_2,
right_plain=>right_plain_2,
subkey=>subkey3,
left_data_out=>left_plain_3,
right_data_out=>right_plain_3);
s9: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_3,
right_key_in=>right_key_3,
subkey=>subkey4,
left_key_out=>left_key_4,
right_key_out=>right_key_4);
s10: round port map(
left_plain=>left_plain_3,
right_plain=>right_plain_3,
subkey=>subkey4,
left_data_out=>left_plain_4,
right_data_out=>right_plain_4);
s11: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_4,
right_key_in=>right_key_4,
subkey=>subkey5,
left_key_out=>left_key_5,
right_key_out=>right_key_5);
s12: round port map(
left_plain=>left_plain_4,
right_plain=>right_plain_4,
subkey=>subkey5,
left_data_out=>left_plain_5,
right_data_out=>right_plain_5);
s13: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_5,
right_key_in=>right_key_5,
subkey=>subkey6,
left_key_out=>left_key_6,
right_key_out=>right_key_6);
s14: round port map(
left_plain=>left_plain_5,
right_plain=>right_plain_5,
subkey=>subkey6,
left_data_out=>left_plain_6,
right_data_out=>right_plain_6);
s15: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_6,
right_key_in=>right_key_6,
subkey=>subkey7,
left_key_out=>left_key_7,
right_key_out=>right_key_7);
s16: round port map(
left_plain=>left_plain_6,
right_plain=>right_plain_6,
subkey=>subkey7,
left_data_out=>left_plain_7,
right_data_out=>right_plain_7);
s17: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_7,
right_key_in=>right_key_7,
subkey=>subkey8,
left_key_out=>left_key_8,
right_key_out=>right_key_8);
s18: round port map(
left_plain=>left_plain_7,
right_plain=>right_plain_7,
subkey=>subkey8,
left_data_out=>left_plain_8,
right_data_out=>right_plain_8);
s19: subkey_production generic map(
shifting_parameter=>"01",
left_or_right=>"0")
port map( left_key_in=>left_key_8,
right_key_in=>right_key_8,
subkey=>subkey9,
left_key_out=>left_key_9,
right_key_out=>right_key_9);
s20: round port map(
left_plain=>left_plain_8,
right_plain=>right_plain_8,
subkey=>subkey9,
left_data_out=>left_plain_9,
right_data_out=>right_plain_9);
s21: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_9,
right_key_in=>right_key_9,
subkey=>subkey10,
left_key_out=>left_key_10,
right_key_out=>right_key_10);
s22: round port map(
left_plain=>left_plain_9,
right_plain=>right_plain_9,
subkey=>subkey10,
left_data_out=>left_plain_10,
right_data_out=>right_plain_10);
s23: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_10,
right_key_in=>right_key_10,
subkey=>subkey11,
left_key_out=>left_key_11,
right_key_out=>right_key_11);
s24: round port map(
left_plain=>left_plain_10,
right_plain=>right_plain_10,
subkey=>subkey11,
left_data_out=>left_plain_11,
right_data_out=>right_plain_11);
s25: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_11,
right_key_in=>right_key_11,
subkey=>subkey12,
left_key_out=>left_key_12,
right_key_out=>right_key_12);
s26: round port map(
left_plain=>left_plain_11,
right_plain=>right_plain_11,
subkey=>subkey12,
left_data_out=>left_plain_12,
right_data_out=>right_plain_12);
s27: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_12,
right_key_in=>right_key_12,
subkey=>subkey13,
left_key_out=>left_key_13,
right_key_out=>right_key_13);
s28: round port map(
left_plain=>left_plain_12,
right_plain=>right_plain_12,
subkey=>subkey13,
left_data_out=>left_plain_13,
right_data_out=>right_plain_13);
s29: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_13,
right_key_in=>right_key_13,
subkey=>subkey14,
left_key_out=>left_key_14,
right_key_out=>right_key_14);
s30: round port map(
left_plain=>left_plain_13,
right_plain=>right_plain_13,
subkey=>subkey14,
left_data_out=>left_plain_14,
right_data_out=>right_plain_14);
s31: subkey_production generic map(
shifting_parameter=>"10",
left_or_right=>"0")
port map( left_key_in=>left_key_14,
right_key_in=>right_key_14,
subkey=>subkey15,
left_key_out=>left_key_15,
right_key_out=>right_key_15);
s32: round port map(
left_plain=>left_plain_14,
right_plain=>right_plain_14,
subkey=>subkey15,
left_data_out=>left_plain_15,
right_data_out=>right_plain_15);
s33: subkey_production generic map(
shifting_parameter=>"01",
left_or_right=>"0")
port map( left_key_in=>left_key_15,
right_key_in=>right_key_15,
subkey=>subkey16,
left_key_out=>left_key_16,
right_key_out=>right_key_16);
s34: round port map(
left_plain=>left_plain_15,
right_plain=>right_plain_15,
subkey=>subkey16,
left_data_out=>left_plain_16,
right_data_out=>right_plain_16);
s35: swap_left_right_64_bits port map(
data_in_left=>left_plain_16,
data_in_right=>right_plain_16,
data_out_left=>swaped_plain_text_left,
data_out_right=>swaped_plain_text_right);
s36: reverse_initial_permutation port map(
permuted_left_half=>swaped_plain_text_left,
permuted_right_half=>swaped_plain_text_right,
data_out=>data_out);
end;
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
library proc_common_v4_0;
use proc_common_v4_0.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
|
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