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---------------------------------------------------------------------------
-- SRAM memory controller
---------------------------------------------------------------------------
-- This file is a part of "Aeon Lite" project
-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
-- [email protected]
-- Project homepage: www.speccyland.net
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY sram_statemachine IS
PORT (
CLK : in std_logic;
RESET_N : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
ADDRESS_IN : in std_logic_vector(22 downto 0);
WRITE_EN : in std_logic;
REQUEST : in std_logic;
BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
COMPLETE : out std_logic;
DATA_OUT : out std_logic_vector(31 downto 0);
SRAM_ADDR : out std_logic_vector(17 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE0_N : out std_logic;
SRAM_CE1_N : out std_logic );
END sram_statemachine;
ARCHITECTURE vhdl OF sram_statemachine IS
function REPEAT(N: natural; B: std_logic)
return std_logic_vector
is
variable RESULT: std_logic_vector(1 to N);
begin
for i in 1 to N loop
RESULT(i) := B;
end loop;
return RESULT;
end;
signal SRAM_DI : std_logic_vector(15 downto 0);
signal SRAM_DO : std_logic_vector(15 downto 0);
signal DATA_OUT_REG : std_logic_vector(31 downto 0);
signal MASK : std_logic_vector(3 downto 0);
type STATES is (ST_IDLE, ST_READ0, ST_READ1, ST_READ2, ST_WRITE0, ST_WRITE1, ST_WRITE2);
signal STATE : STATES;
BEGIN
SRAM_DQ <= SRAM_DI;
SRAM_DO <= SRAM_DQ;
DATA_OUT <= DATA_OUT_REG;
COMPLETE <= '1' when STATE = ST_IDLE and REQUEST = '0' else '0';
process(CLK, RESET_N)
begin
if RESET_N = '0' then
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE_N <= '1';
SRAM_OE_N <= '1';
SRAM_CE0_N <= '1';
SRAM_CE1_N <= '1';
SRAM_LB_N <= '1';
SRAM_UB_N <= '1';
STATE <= ST_IDLE;
else
if rising_edge(CLK) then
case STATE is
when ST_IDLE =>
SRAM_DI <= (OTHERS=>'Z');
SRAM_WE_N <= '1';
SRAM_OE_N <= '1';
SRAM_LB_N <= '1';
SRAM_UB_N <= '1';
if REQUEST = '1' then
MASK(0) <= (BYTE_ACCESS or WORD_ACCESS) and ADDRESS_IN(0); -- masked on misaligned byte or word
MASK(1) <= (BYTE_ACCESS) and not(address_in(0)); -- masked on aligned byte only
MASK(2) <= BYTE_ACCESS or (WORD_ACCESS and not(ADDRESS_IN(0))); -- masked on aligned word or byte
MASK(3) <= not(LONGWORD_ACCESS); -- masked for everything except long word access
SRAM_ADDR <= ADDRESS_IN(18 downto 1);
SRAM_CE0_N <= ADDRESS_IN(19);
SRAM_CE1_N <= not ADDRESS_IN(19);
if WRITE_EN = '1' then
STATE <= ST_WRITE0;
else
STATE <= ST_READ0;
end if;
end if;
when ST_WRITE0 =>
SRAM_LB_N <= MASK(0);
SRAM_UB_N <= MASK(1);
SRAM_DI(7 downto 0) <= DATA_IN(7 downto 0);
SRAM_DI(15 downto 8) <= (DATA_IN(15 downto 8) and not(repeat(8,MASK(0)))) or (DATA_IN(7 downto 0) and repeat(8,MASK(0)));
SRAM_WE_N <= '0';
STATE <= ST_WRITE1;
when ST_WRITE1 =>
SRAM_WE_N <= '1';
STATE <= ST_WRITE2;
when ST_WRITE2 =>
SRAM_ADDR <= std_logic_vector(unsigned(ADDRESS_IN(18 downto 1)) + 1);
SRAM_DI(7 downto 0) <= (DATA_IN(23 downto 16) and not(repeat(8,MASK(0)))) or (DATA_IN(15 downto 8) and repeat(8,MASK(0)));
SRAM_DI(15 downto 8) <= DATA_IN(31 downto 24);
SRAM_LB_N <= MASK(2);
SRAM_UB_N <= MASK(3);
SRAM_WE_N <= '0';
STATE <= ST_IDLE;
when ST_READ0 =>
SRAM_LB_N <= MASK(0);
SRAM_UB_N <= MASK(1);
SRAM_OE_N <= '0';
STATE <= ST_READ1;
when ST_READ1 =>
DATA_OUT_REG(7 downto 0) <= (SRAM_DO(7 downto 0) and not(repeat(8,MASK(0)))) or (SRAM_DO(15 downto 8) and repeat(8,MASK(0)));
DATA_OUT_REG(15 downto 8) <= SRAM_DO(15 downto 8);
SRAM_ADDR <= std_logic_vector(unsigned(ADDRESS_IN(18 downto 1)) + 1);
SRAM_LB_N <= MASK(2);
SRAM_UB_N <= MASK(3);
STATE <= ST_READ2;
when ST_READ2 =>
DATA_OUT_REG(15 downto 8 ) <= (SRAM_DO(7 downto 0) and repeat(8,MASK(0))) or (DATA_OUT_REG(15 downto 8) and not(repeat(8,MASK(0))));
DATA_OUT_REG(31 downto 16) <= SRAM_DO(15 downto 0);
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
end if;
end if;
end process;
END vhdl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zynq_design_1_axi_gpio_0_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END zynq_design_1_axi_gpio_0_1;
ARCHITECTURE zynq_design_1_axi_gpio_0_1_arch OF zynq_design_1_axi_gpio_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_gpio_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_design_1_axi_gpio_0_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_design_1_axi_gpio_0_1_arch : ARCHITECTURE IS "zynq_design_1_axi_gpio_0_1,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_design_1_axi_gpio_0_1_arch: ARCHITECTURE IS "zynq_design_1_axi_gpio_0_1,axi_gpio,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=8,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_design_1_axi_gpio_0_1_arch;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BcdSegDecoder is
Port ( clk : in std_logic;
bcd : in std_logic_vector(3 downto 0);
segment7 : out std_logic_vector(6 downto 0));
end BcdSegDecoder;
architecture Behavioral of BcdSegDecoder is
begin
process (clk,bcd)
begin
if (clk'event and clk='1') then
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
when others=> segment7 <="1111111";
end case;
end if;
end process;
end Behavioral; |
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := kintex7;
constant CFG_MEMTECH : integer := kintex7;
constant CFG_PADTECH : integer := kintex7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := kintex7;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (8);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 1 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 16;
constant CFG_DTLBNUM : integer := 16;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1;
constant CFG_ATBSZ : integer := 1;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 0;
constant CFG_MIG_RANKS : integer := 1;
constant CFG_MIG_COLBITS : integer := 10;
constant CFG_MIG_ROWBITS : integer := 13;
constant CFG_MIG_BANKBITS: integer := 2;
constant CFG_MIG_HMASK : integer := 16#F00#;
-- Xilinx MIG Series 7
constant CFG_MIG_SERIES7 : integer := 1;
constant CFG_MIG_SERIES7_MODEL : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 4;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 32;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (7);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
entity syntax_error is
end entity syntax_error
|
entity syntax_error is
end entity syntax_error
|
entity syntax_error is
end entity syntax_error
|
entity syntax_error is
end entity syntax_error
|
-------------------------------------------------------------------------------
--
-- Title : cl_lcd_data
-- Author : Alexander Kapitanov
-- Company : Instrumental Systems
-- E-mail : [email protected]
--
-- Version : 1.0
--
-------------------------------------------------------------------------------
--
-- Description : Data for testing LCD Display LCD1602
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cl_lcd_data is
generic (
TD : in time --! simulation time;
);
port(
reset : in std_logic; --! system reset
clk : in std_logic; --! clock 50 MHz
test_mode : in std_logic; --! select mode: test message or timer message
load_ena : in std_logic; --! load new data
load_dat : in std_logic_vector(7 downto 0); --! new data;
load_addr : in std_logic_vector(4 downto 0); --! new address;
disp_data : out std_logic_vector(7 downto 0); --! data to display
disp_ena : out std_logic; --! enable for data
disp_init : in std_logic; --! ready for data
disp_rdyt : in std_logic --! valid pulse for data
);
end cl_lcd_data;
architecture cl_lcd_data of cl_lcd_data is
signal cnt : std_logic_vector(4 downto 0):="00000";
--signal data : std_logic_vector(7 downto 0);
type ROM is array (integer range 0 to 31) of std_logic_vector(7 downto 0);
-- MEMORY for TIMER:
signal mem_test : ROM:=( x"21", x"21", x"A5", x"A5", x"A5", x"A5", x"A5", x"2F", x"A5", x"A5", x"2F", x"A5", x"A5", x"A5", x"A5", x"A5",
x"21", x"21", x"A5", x"A5", x"A5", x"A5", x"A5", x"2F", x"A5", x"A5", x"2F", x"A5", x"A5", x"A5", x"A5", x"A5");
-- HELLO HABR: www.habrahabr.ru
signal mem_habr : ROM:=( x"2A", x"2A", x"A5", x"A5", x"48", x"65", x"6C", x"6C", x"6F", x"A0", x"48", x"41", x"42", x"52", x"A5", x"A5",
x"2A", x"2A", x"46", x"72", x"6F", x"6D", x"A0", x"4B", x"61", x"70", x"69", x"74", x"61", x"6E", x"6F", x"76");
attribute RAM_STYLE : string;
attribute RAM_STYLE of mem_test: signal is "DISTRIBUTED";
attribute RAM_STYLE of mem_habr: signal is "DISTRIBUTED";
begin
pr_rom8x32: process(clk) is
begin
if(rising_edge(clk)) then
if (load_ena = '1') then
mem_test(conv_integer(unsigned(load_addr))) <= load_dat after td;
end if;
--data <= mem_test(conv_integer(unsigned(load_addr)));
end if;
end process;
-- display 2x16 on LCD
pr_2to8: process(clk, reset) is
begin
if (reset = '0') then
disp_data <= x"00";
disp_ena <= '0';
cnt <= "00000";
elsif (rising_edge(clk)) then
if (disp_init = '1') then
if (disp_rdyt = '1') then
disp_ena <= '1' after td;
if (test_mode = '0') then
disp_data <= mem_test(conv_integer(cnt)) after td;
else
disp_data <= mem_habr(conv_integer(cnt)) after td;
end if;
if (cnt = "11111") then
cnt <= "00000" after td;
else
cnt <= cnt + 1 after td;
end if;
end if;
else
disp_data <= x"00" after td;
disp_ena <= '0' after td;
end if;
end if;
end process;
end cl_lcd_data; |
-- This file handles the sampling and clock crossing from the incoming pixel
-- clock to the internal system clock.
-- This is done using a 2 port fifo generated by the altera mega wizard
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity VideoCapturer is
generic (
DataW : positive := 8
);
port (
PRstN : in bit1;
PClk : in bit1;
--
RstN : in bit1;
Clk : in bit1;
--
Vsync : in bit1;
Href : in bit1;
PixelData : in word(DataW-1 downto 0);
--
PixelOut : out word(DataW-1 downto 0);
PixelVal : out bit1;
FillLevel : out word(3-1 downto 0);
Vsync_Clk : out bit1
);
end entity;
architecture rtl of VideoCapturer is
signal ValData_N : bit1;
signal PixelData_N, PixelData_D : word(DataW-1 downto 0);
signal SeenVsync_N, SeenVsync_D : word(4-1 downto 0);
--
signal FifoEmpty : bit1;
signal RdFifo : bit1;
signal FifoRdVal_N, FifoRdVal_D : bit1;
signal RdData : word(DataW-1 downto 0);
signal PixelOut_D : word(DataW-1 downto 0);
signal PixelVal_D : bit1;
signal VSync_D : word(4-1 downto 0);
signal VSync_META, VSync_D_Clk : bit1;
begin
PClkSync : process (PCLK, PRstN)
begin
if PRstN = '0' then
PixelData_D <= (others => '0');
SeenVsync_D <= (others => '0');
Vsync_D <= (others => '0');
elsif rising_edge(PCLK) then
PixelData_D <= PixelData_N;
SeenVsync_D <= SeenVsync_N;
Vsync_D(0) <= Vsync;
for i in 1 to 3 loop
Vsync_D(i) <= Vsync_D(i-1);
end loop;
end if;
end process;
PClkAsync : process (PixelData, Href, Vsync_D, SeenVsync_D)
begin
PixelData_N <= PixelData;
ValData_N <= '0';
SeenVsync_N <= SeenVsync_D;
-- Initial gating to ensure that we start to capture at the start of a frame
if (RedAnd(SeenVsync_D) = '1') then
-- VSync observed
null;
elsif (RedAnd(Vsync_D) = '1') then
SeenVsync_N <= SeenVsync_D + 1;
else
-- Vsync tracking lost, go to start state
SeenVSync_N <= (others => '0');
end if;
if Href = '1' and RedAnd(SeenVsync_D) = '1' then
ValData_N <= '1';
end if;
end process;
ClkCrossingFifo : entity work.AsyncFifo
port map (
data => PixelData_D,
wrclk => PClk,
wrreq => ValData_N,
--
rdclk => Clk,
rdempty => FifoEmpty,
rdreq => RdFifo,
q => RdData,
--
rdusedw => FillLevel,
wrfull => open
);
RdFifo <= not FifoEmpty;
ClkAsync : process (RdFifo)
begin
FifoRdVal_N <= '0';
if RdFifo = '1' then
FifoRdVal_N <= '1';
end if;
end process;
ClkRstSync : process (RstN, Clk)
begin
if RstN = '0' then
PixelVal_D <= '0';
elsif rising_edge(Clk) then
PixelVal_D <= FifoRdVal_D;
end if;
end process;
ClkNoRstSync : process (Clk)
begin
if rising_edge(Clk) then
FifoRdVal_D <= FifoRdVal_N;
PixelOut_D <= RdData;
--
VSync_META <= RedAnd(VSync);
VSync_D_Clk <= VSync_META;
end if;
end process;
PixelFeed : PixelOut <= PixelOut_D;
PixelValFeed : PixelVal <= PixelVal_D;
VsyncFeed : Vsync_Clk <= Vsync_D_Clk;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc742.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00742pkg is
type arrtype is array (1 to 5) of integer;
type rectype is record
-- 'a',33,0.1234,TRUE
ch : character;
int : integer;
re : real;
bo : boolean;
end record;
end c01s01b01x01p04n01i00742pkg;
use work.c01s01b01x01p04n01i00742pkg.all;
entity c01s01b01x01p04n01i00742ent_a is
generic (
constant gc1 : arrtype;
constant gc2 : rectype;
constant gc3 : boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00742ent_a;
architecture c01s01b01x01p04n01i00742arch_a of c01s01b01x01p04n01i00742ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1=(1,2,3,4,5)) AND (gc2.ch='a') AND (gc2.int=33) AND (gc2.re=0.1234) AND (gc2.bo) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00742"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00742 - Generic association with type conversion in component instantiation failed."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00742arch_a;
use work.c01s01b01x01p04n01i00742pkg.all;
ENTITY c01s01b01x01p04n01i00742ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00742ent;
ARCHITECTURE c01s01b01x01p04n01i00742arch OF c01s01b01x01p04n01i00742ent IS
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : arrtype;
constant dgc2 : rectype;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00742ent_a(c01s01b01x01p04n01i00742arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
function BoolToArr(bin : boolean) return arrtype is
begin
if bin then
return (1,2,3,4,5);
else
return (9,8,7,6,5);
end if;
end;
function IntegerToRec(iin : integer) return rectype is
begin
return ('a',33,0.1234,TRUE);
end;
function BitToBool(bin : bit) return boolean is
begin
if (bin = '1') then
return TRUE;
else
return FALSE;
end if;
end;
BEGIN
u1 : comp1
generic map (BoolToArr(TRUE), IntegerToRec(1234), BitToBool('1'))
port map (ee1,ee2);
END c01s01b01x01p04n01i00742arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc742.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00742pkg is
type arrtype is array (1 to 5) of integer;
type rectype is record
-- 'a',33,0.1234,TRUE
ch : character;
int : integer;
re : real;
bo : boolean;
end record;
end c01s01b01x01p04n01i00742pkg;
use work.c01s01b01x01p04n01i00742pkg.all;
entity c01s01b01x01p04n01i00742ent_a is
generic (
constant gc1 : arrtype;
constant gc2 : rectype;
constant gc3 : boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00742ent_a;
architecture c01s01b01x01p04n01i00742arch_a of c01s01b01x01p04n01i00742ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1=(1,2,3,4,5)) AND (gc2.ch='a') AND (gc2.int=33) AND (gc2.re=0.1234) AND (gc2.bo) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00742"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00742 - Generic association with type conversion in component instantiation failed."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00742arch_a;
use work.c01s01b01x01p04n01i00742pkg.all;
ENTITY c01s01b01x01p04n01i00742ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00742ent;
ARCHITECTURE c01s01b01x01p04n01i00742arch OF c01s01b01x01p04n01i00742ent IS
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : arrtype;
constant dgc2 : rectype;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00742ent_a(c01s01b01x01p04n01i00742arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
function BoolToArr(bin : boolean) return arrtype is
begin
if bin then
return (1,2,3,4,5);
else
return (9,8,7,6,5);
end if;
end;
function IntegerToRec(iin : integer) return rectype is
begin
return ('a',33,0.1234,TRUE);
end;
function BitToBool(bin : bit) return boolean is
begin
if (bin = '1') then
return TRUE;
else
return FALSE;
end if;
end;
BEGIN
u1 : comp1
generic map (BoolToArr(TRUE), IntegerToRec(1234), BitToBool('1'))
port map (ee1,ee2);
END c01s01b01x01p04n01i00742arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc742.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s01b01x01p04n01i00742pkg is
type arrtype is array (1 to 5) of integer;
type rectype is record
-- 'a',33,0.1234,TRUE
ch : character;
int : integer;
re : real;
bo : boolean;
end record;
end c01s01b01x01p04n01i00742pkg;
use work.c01s01b01x01p04n01i00742pkg.all;
entity c01s01b01x01p04n01i00742ent_a is
generic (
constant gc1 : arrtype;
constant gc2 : rectype;
constant gc3 : boolean
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n01i00742ent_a;
architecture c01s01b01x01p04n01i00742arch_a of c01s01b01x01p04n01i00742ent_a is
begin
p0: process
begin
wait for 1 ns;
if (gc1=(1,2,3,4,5)) AND (gc2.ch='a') AND (gc2.int=33) AND (gc2.re=0.1234) AND (gc2.bo) AND (gc3) then
assert FALSE
report "***PASSED TEST: c01s01b01x01p04n01i00742"
severity NOTE;
else
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n01i00742 - Generic association with type conversion in component instantiation failed."
severity ERROR;
end if;
wait;
end process;
end c01s01b01x01p04n01i00742arch_a;
use work.c01s01b01x01p04n01i00742pkg.all;
ENTITY c01s01b01x01p04n01i00742ent IS
generic ( constant gen_con : integer := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n01i00742ent;
ARCHITECTURE c01s01b01x01p04n01i00742arch OF c01s01b01x01p04n01i00742ent IS
signal s1 : integer;
signal s2 : integer;
signal s3 : integer;
component comp1
generic (
constant dgc1 : arrtype;
constant dgc2 : rectype;
constant dgc3 : boolean
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use
entity work.c01s01b01x01p04n01i00742ent_a(c01s01b01x01p04n01i00742arch_a)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
function BoolToArr(bin : boolean) return arrtype is
begin
if bin then
return (1,2,3,4,5);
else
return (9,8,7,6,5);
end if;
end;
function IntegerToRec(iin : integer) return rectype is
begin
return ('a',33,0.1234,TRUE);
end;
function BitToBool(bin : bit) return boolean is
begin
if (bin = '1') then
return TRUE;
else
return FALSE;
end if;
end;
BEGIN
u1 : comp1
generic map (BoolToArr(TRUE), IntegerToRec(1234), BitToBool('1'))
port map (ee1,ee2);
END c01s01b01x01p04n01i00742arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 95536)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztB/h+4PvAs/N0XI0cN9OT8nV3gs0Dpd/RXDA4Vc3dmwziA
NwElhjRY3VJxDTskfz+mxWNFaf1+mPePrYVqlwPTMBAxpvGimC8dYYQqLJKeeN1ZgTT7hwUkM2z1
Qy84CcCZcArvoNTfBy0dkWCCscLO7FYjYdrltlJMSy8CDdjskSxeftCs1jkCE/tStmrqLGxjbT6f
C92mpUd5YCmVlDJSoyG1Rmk3H90KWuHUMBc4d/nTIqIeHq74s/5YZbg6Itq+omXbAlchsha/ae76
9FWmmOPV5pGgbO9pUb/MAoiGnE0LV3UxmCzxLGMR5z068+xQRaJogr8gIRx4YzXucEDuMm6kq+U/
DJ8q3+UroFofr/QazQtIkbprz4hnKB1pQ9WCRHlWqYPmrTOztTQ4ZG+pAcx0IYfnFhwKTspFW+7y
GVx0kYGoMrgq7RbxX18WgYUZLMUFfRe6xSzxKiK5kNCdSzOH1JhyEU9M4B2sCcF5xcT7K2tFVZhx
cOoGlhAsPEMuJPF65qYCcRfu6UC7PJuefitD/S7Rr62kMcVw6pREvkYzRs+qsbgNnfPabgzwOYLp
olR7zI8hlqAGIZzAnxQDewB8HIRF0Cgw+b9popHU1CVbEfrPyAP2H9rTagex/AtB726oU3NS/Hto
hL3uC69KGFYAENJTVq04Ff518xRZvbDhZk4t7/Zpna6SOSIzrODGUJSP0FvZZ09QlakBg3Wo50tY
pgmp4DoT7CrqwvHOwtpgiLSWvTFKDLrISVTMjwWznwzIhQ773VhYwUgBwfVumnYIA8G6jaBfBGLn
337ecvtYSoD2WCjY57N+HiWBgdUQDQ3NSmVXDdKaQQjU+G8lATwv+bAb0d2har2upRJoeMobJ656
sfolUjfmew0LyjHzcPgiiMXxmQ//k5PhQRSAt8ggHr1+QYtC5Fh8GgB8scvBnTUM1XAO6R+HNs1L
U27gBJbGILSvUpTBZUXNkyoi8+s03L5a+vlwiEGgNBCUxq83tbJM454XJo07BkuS08KsFVnKwFol
BUxHZ12vFrTlJEeYdgyh64SsThJH99ZA6uEJZTSV37DhOLcIz86Z/+PfhZiByqnY0gn+wYCvOaR9
ocdEJsAWit/14k2h20xNDsh7vHErwyFqka7Ply4vS69D1gzEs/cwndFSR1Rm4eG7Zx13Pb2eR91A
vsj2o/4d7k6a8tH+bI8oDZQ/Qik/iGzOxZd3OZ9GvU8W+nKFx374cVoWAVRDAULUwyeFSZ8E+i4q
dROg4VnjRV1scMxi2bcOCuRJbX6vzKu9ao2v6me0KWbJrYk6Pb9VqAXmSAuxX1soQOyX8RLsDiWu
87+V9QkKz3gnZoSnwvxHt1paDTyWjfL4QMWA7yN1HbAvNPVY1XzuiTaKKEsyf9tvN3B/JY124zWT
CwibACdVqWqVFnC6vA4TidGx3yPOC9UhqDqcnqK5yfS7XC/KBwTP61QDQmo+8oWydyiuC+/NKVvt
xxNgeNW5WZL+UPd4qQ4ztuHmm9pfbJYKiuOJ4PkE6fuWkYPIhlX5QNKRqmLlF3jI6g6q2jl/S9KF
osulJvpp9IreJsYUeJoAOUYKglzMoa4rbTolwNg1kaiUPo7l5mXLcK0SujbMFWWGBRaLCfleNqCt
zawyhYjxey/Hi6IAQNbpyV42kQw66RXAvkbnjvc1Q/4UJ5rUo3Y+BfUc/d6QtoQ/MM2DnzZSelhz
wuszJzcVPod7VaEeVJQoYhSX/X+K3VQKZs2qHjRAh3XGV9YuAF3++sWBmfFfgurXmByZIYDa8kG1
7ZqIxa03vBFzHPJOv6aVvwWhnLmhSlVPCIHJxHiCGClZqCwm4y91AzIrXc9bPQNFscMLSg18PeG+
DaO3k99xUA9pn0STbk95TsxkbAAjVNbWBxRf9UedMz2Sj3o8XoBTOQYO2J+U066n+tTbHFYav1rR
9+sxamPEgAx/m5VI7mTLxdi0W2dgRRA4XDWHFWifRPN1KzIxNPHcTykgw/Lm//RZxB8MPUoBtMTv
ZLGrbVtckg65yrTYytUXEVL0eEGX99q4F5ZD7HmggQj/TehQOqyJaeGRkF0iyLX3+6bJxTqZWTkM
E9InS3J5wzbPVE3Pnz95yL45bs7pjKcK5Wq97wYr2xOxkApeasVKwvVSnGdxZ3dD8J71KiH7xG4j
IiU8QzbswZSUR0PukpVOPr7GcqrqOww/EAwXmesEJh0iEamU/ApOkbw8VZz0DcNew0BtRSv4oJn0
YVzugB/ed+9BIWsevE4e4JWi9vIXmUBT/uxNTF4cIDVP8RoxUJyU49US+VYMX+h6zYO0wxW/e/3q
GGFfRTxrDEX4+kwKXlfTe0Ryfled6Hfe25WkbytJZsJO11a+oiZrrrxLilzx9YraiqOSOJ0leUdK
6f6LbYP28aPSZxITy7N37ClpKNEZAsfvjXjI+fU6WItoDfHlnRgUP8kk6pzNyr2cSv4Mlg8S7zvo
ctupzXJVB+2WWab3RwqY3O4WwctcKkE7Mu9IPJjczuTATT/gFi6qOIUy0IeuDBMu7yfxvapNVXUw
x/XHP7kpFa5xaFPZLGgEyZwXZaOFNJ8gpmEjnHVUV8Nhrix4J7xLYfZ6r0+AiYhRCMMbuV46k6ew
DJLx1p3eKNSDagcWjIFx0oFXKM1MYJkymZpAFr+eTGw2up4fXuKo/DLd7vUiZYlt18Xw78+btiEv
VZCl5PS6ecifRQUmuW7wUQLJ5xxXco2P9v96725mgey2TRdWYXLdZQ1V8zsnwpZhINsLIMM1wT2E
Z/4Jlan/b4Zsw+9yMPAEMlN26qzCpzctSH/z5OrlpY49tjCWSpkqPM1l1BpbaAbi5nfYEoXMFOeT
3jTzFbWQ2tmzc3FPkORk9SqZMGl0agAeyQagVZsLeL8FxdQFK3Y5MgwzIOVV9N4/ouRr9BMhJylB
pE47x6S6ncVe3PPCxE1R3CYSUJJWb14e6OnlbSfrR1jTCppWEFUstCgOAU8m+D5GCqWe8zdILdlj
YVMbKliRzjsBZYMiXuBCjZYpJ/hu4pdE+56Km5r72/sGlwpLh0Sp3qFx3/QY60or8+nqNxjRVqk6
9Pu3EvIRyKCuk1fExvo9V5Zs62RrE6CxOL0NpxrYwn7PSChgdL6XSH+DfuTLAaDxXlkaM7r3Sr5k
6FbBdl0Bn4I7rwYV1cA5kPU8rGxOt1WJao5O9kG/TbxPqNPdrG3ZlEwSzi7J4QWmqCjzjzewXt9X
zmletWZ+HZMYVcLf7BB0zap0EO5N0XBbpxu+e+h+OGrXmFH0vlVv6jXXgJVEZhVw/dV72W+J4QvQ
7N5/Y6Hr5kpPZZ01uoNwTFORiT/PwJLbPj2fBb5Gupszp4mlgz5O1srWhwUzJ4ykKwhtQ5tk3ftx
EncTUon2WC0cUTNxeAxJTSs9wFPwNskezNjJ0tnXdwNiJI8kUrRZ9oszqKoasW8PcDueaSwjb2PD
JavrQhmgEOCBAgCnkPTno9NGlcek7DcPaq6uhwb50gYY2l2UYPMAcfrREJFdP8i3XffmUArvDNEA
hAnZbc677LlBoxG39d509+AoCHpo8BYl1DjMsP2+nJqaY56Crq3mip+KpqU20a6GnkZtXvPh6DVO
YUd+d0dSZUBv5Jaf67F96NUK/ZHgjMitGyfJzi1QzZ58EBcqYFCtNnceVpAtoN4bL9dhrzCh0nHg
MIUuDgdLdZg56MsdvfuRWLF8b/1Vh+j0J0VBvAUlBNvU1cM2zvUBkKhgPplG/6+J4+BgY6F3zNs2
E8aTB3D8gLnt4PtbmDbg5tbe4C+2DVb86cTrTGw299kZM+ygqVuiJVLzkM3HoqyCTYi+CnYwTPK/
y/XPY2wobFm0hVk+oUY6bPKxJnrs78fSpKYCsvBkIpmD10jW/Nm01hhpmD0uM3axfPe/99ANehUH
7fpJUTnGpOTayowtnZOrndV6huw2x86n43VyZuL+FXzIcUPYKGIC33W3zZ5/zbGT9xlK1SpYxlnH
/ppFj9iNqzCviDzyau+llMtjcfT6n2bb4gi2xhl9FcFCC/+KvGdaUJbalCRsmC2nUFgVEASgt4y+
q992c+slBpmDw0taTdwawRL5BBzSYHPcW+59Vk5z3x6WPcpKOwhK9wp+yXxcID2zXmFeLpldmL0I
Y4vWB0IFu1Uo65b3V6dmSVgMHCaGvZQ6MJvS80iCf2/oDacpLNOZkqa3DFC4XV0NkQD2EHqS1Bd7
Noj7ZW4mBzeMessx5D/91heXx/RqOy7/pl+B0XfW5qN+QxiwZWFDjCF/5T8+qXxlUdetQuYt43Qt
AdGhtGnd35GYO2bFGES0k7Da0FhfXhFYvkTTKxxDOSQe+uo9iYZmrRVQdW8iYJbqjDWytxfXX0Kx
3y9tB1FTg4/oSo1meuQSvqFourhD62tW0W8CfImuVnMpmgx803NJ/ftSoVsfVaWsKjyLWxWfRl+r
/c9DfsPalq2CZJWdnxy7Co4PtLr1oeDoO6Fh9j7ij5BvsJqhp2dD2Q1Pp4jdcY7GRfx/s6qpYfjF
Qe+EpssNScsqF1DpODQxSWFlVnlkK+s/JobFp+IjSWFUKJ93ppkLcDIzymZQ1YKHLaJLD99JgfYX
RLXBjcqlicOhUntYoWbOq62SvBwrM3+r2JSKS1zfoCW7diS5rKJDairlH6b07Df6sARnHgdtyvvs
wzoA8/6IMp5M/54p1AUnVhHKh8oE9i6raHwMjr4vLijAGWPMOcBYj2eRL3nf8yEzeQu8XrFwSdnp
9soB6+nAGNVBfaYMJRgoINTHd/t80sdsnt0dnc7OfHM1iNWo/XxkeQLX1Z1xYKIz2XxkTQbfjTUE
xV+7BFWCJoboXsmxldrKomYpXCq6iDGhc4m3/x5J7mxNJkFWobhHchcGgjsed5wcsPCJtD3o/Qkf
mPnoh+6FPdiK/pHCChdbGItAyYAMzuGs9moowM0jahLcRGlgQSQbRtUc17x3Jt/JPcj59ROJM9iQ
aToEB1fFa5ALLIMO990eT5C8x/f0txA4cFc+gSDKCpOxA8DgX+Cn1tSto/VVhjpNE3vhpRdWgKDT
QCBO32bUWpGpNSZ2mALB79qTAf1gtX4oS4PW/yqjNkA7vJZ5W1Ep7LbaHT5Kd6K1KvFZ7K4zsCnD
bZB1asu0sCnXOGy4tGDNDu87/W9YKynMVtEDan1nNPZh2MnYo1+0HGnKETiQCPsk9SD0uhlPfGET
GzUd30zy2VdFsYvHIZyc/oc5ShZvVko9KdUkQ2wbUIH1VCvkk01EaWm7JrAVbpno3YzlDMAxcTFY
4iPcZJm/Q6fBXllaUXtqMfKn/cLnJTu8UPqveOFrYWbW++8K15jKnYwmwBFiM8u7V28cWF3vGiPX
JpR1mIcHPRnp7ywMrNWwxxz+LOcaLd0BDeaKUHmmd1mcr9QXopzJ9u0Is+EG6+Y+XqaElZzev470
SbvcF+pk1F9KhDjfJ09zIAdaAa18yWpo2n920VijmiK2Rntt/OXM3MA1/RLDKQWGd1E1akKmHZCQ
2f4+jnSPliZZl/6HNYXqLkaKU3oDEnHZEpIUZDWxPr4ABMHG4vDQHEM+4TRgbvC4eeIX9WdFj3V7
9JQ4FI/fTQtLGMHL3JO/PbRYkcJaCbLayzHV0XRRyrf9H1f293w6M6ssFbExIOMRmgFGwJDsURJb
FMvIjbQhgOCeKxQLnZ0+NHGpU2NmPTnPchyDzCA1H1/b+ZYRr7+gyTXbpvU7eC7ZMZJ2XRpVL012
oAMm+Ap+Oid5SwtFA7qpEsaHLlR/Wex9JmnUFKAj4Do2xCvHIm7+BXkOzQjzXNWYxFGZrU+xtA8B
cCpO4uRc56S2eDWb0JoXv0SKypg/JR99YVnETpC9ZFbb0odtnyYL9Lt+MB3YtqHFsamqAvpmUSJo
gpOupM24T7ED4SU7H5kcB4v3jLQ49hZEOTgafERRw3hazIZktU6bZqJHU8WeC4qMBJZ3OJ0S5wiJ
4sT1FewY4C+E8itTd80OUhYMa/5nUbBozYxNnBheUDfF1L/kfSUnXQstIpO9BTGF30LOPsxEoHrS
TKbn8sSq7YWKdUgNBFNFr7aBhrCkymIvB9YHF5ZDGvJ0zBLAeK5vC59vIKbjx3sO7YVubeSKs6Pv
K53T+7qkHuPULU8r6TksEIfIQwPf0P5WFf9LGqAxv+w5THHUMpAxc978FW0xJ+ATe7ey+rwWmvXi
EepaB1EwshLp45w2tYNzZoNEWKapASif/ojS2VCO8kuw1rLY1obQ9HVA6xPadqu48FBPHQ+74tuK
wOY37WuuyKxSp9ipLLYPtUem0F4B9H5QIGQoY056nz1XffujAGuqtlHOu/VU/egDi7ksi3T848K6
afVhRJVHwyROsV5zaIQgO7j7rOOJxjXj0AL7J6eTOyZQSfpg+lyY/5JL3OA3n67CyAaJPle8F2//
yXF1TMnDWGiz+LJ4/tpKAB+ep7+25zmewAzueWctvyDd81E/+vel/qf1DchiMed6N+zOnmr03lAW
/jH9UKkeDdz0B46MBKOJF3iHsGkeR9XNtMP7NsrBZx+GQSmbOKXxtRROPJZQnnh9TAgyfmvubEN2
oTdk+AYIOtJPiNDnb3/ShalJJowuygg2dCMgfPcFUWWJxYRGhfx1NK2pHz4G6MYl3FjqFI58V5Yu
P2jjlmTfiJM5gsFIMNm2fXyGp/3p/PIDACDrSqDTfza2lc6HsJyStW5rX0XjcMAazq3s0X7UGK35
njjab0JAtar2KvLn7iRtuSVpOHX5TVjSqVVZGLzTz55zM5rqgFmwRK7b1PGwxswDHKU46yj89va+
M72ncoJecdz14w9WaKoTOQSvkijxIYE9PUaSodR/URjiys7WRHYmMatapl/IrM366IouVihpw0gE
29Tqb6mKcaZDuCCkhpvjBlLz575PFUN2A/J/RwlRhTm7R/5cjoT+bZrLVuCdcr+pGea4K7U4LFEk
OW/Wd+DXpuSaOzO8zAttgjTxwnxuiY5yNn0nfCPigCczr2eG5zjBKRjapq5tKn59IX+Fy93RxHHd
niuH8uTMAyBxo3V1e6+6O4Qb3WsEiwGKM4KdCsLvMMOsLu1rQ9FUpJv/OuRdxyH8QleUiMl74kEx
Rdq//sCW5pWbKFrcNTDOzBCOEtzvwiu+ppCwDL3A5GBzzqSlS7Tj1F2nn7pYYQBFRSRVwS0c5Y2Y
xxWfniwfrPuP27l4JewCuzwmIKgAhAnVy5UOf7GTQzksgZrI4VTOXg74GzT8hUv6YYSekgJsLrdT
ADdqiVgdtysoOn0TarcxZemh60uYUE0Mz+X3d7CmPi+PV1oCpAjEgcZC//at+lTlksptnpW4w6Zl
geD1tbQWyTqm9051zQf4tqKTpqlOu9tadafn5+vmnICIty9v02HBRyOZ2uK+vIOEtGCKF78KEmhT
cX4+R2FpikbT6ELjUAR+Wr8nQbFSCirAhNWKx6lFhXLrPX58FL0/fr6iM5BG08HFIHdG1Ofy78Hr
T+khaBwOSxE1E7++jao/IfrYlC7Bj+PijA5ivaC4nBEJVvvBPcouiwTwyh3rO/fsV9BfSsN44Q89
uX8CsJA5/TF9O49W6PQ0+g0WNcC9hHYgqSnKpGF0AQzimofBQc3g0M2DS4+TUDCVQmAJxsIEc7S9
JG2YnesYAaLnR4cUUWcj2FxqFkUNCgEBJRKpjWPZmDbTDgwfRZx0H9NWUzksG4buj1ULbeP7/eCy
4QihsOnTftd6jV/1KZHhvqMKaMt2lkBqBnz9OPH8l+8i/1tscn7JjuFm0B2hlPeEln3ve8PTui0v
O1xoNfnmcvOYS1zXTEsMo946kMiP+XDahoVHYvR29Hz0lkm0dKsNqsIA7Fjh8dB3pMBQ3GPvxQht
1F5DhTR8jFQF15PXinIGZPg6VVjOOQlkA/0AzmC6RQwLvaLEB1ClayDzl3JNs3JR/I38ys2DtHas
KlTJUmJwSKpk20eOu0zG4QM1X10HoxmER4BThMGhF9XfzVetBzNpiDxcY5rypE93ly+JaMxL/YnI
er1AhHiOp+v9PL5+NZ5Irv+biqp1na/tAp+CroxH7jUiq/PkUtq8iajsIyI6x1jlE8QdLgqO21CQ
eAlW0oQd+z43dsOMBX4l9No69p0x5G74X+GtUwAX3QaWvogBeyT8qcPECATrLU66fZFTdW1mGydz
X7spXsQ9VrwMCAoEWk1eHyt/+W7lbd4+5o8o7kSI7V53f9MvWgE5essO4oaw2ODv9qrGsgM5JyVJ
54ZojqFg/b4rxWr9sxkfNeBf/LEPdG815RL/iy9yeZ+yqXxVoWyuV2WsUuFBNkiv0CDOtebdN2qC
PffE9o82SoaKCSilxjcKzfkHobBOOpulHY80AYxraMcq20BpaCpwVXcgkR99bdQcCJsQUhLY9/GW
aMAwob4oKVJ5ZQgMi5uLmP9KL2qSGZkYi/7tyPcsf7mJmDeSxp1GWzQX8E8ZjLtVsd+8Q1/NSRdl
rwypTMi0Cq4Lmu7KuI4P2BB2NHb9Rp0g171FEZwowk1IDQzj9OSqSxmuMrbwnHdMLky6q7FePkUS
+jkeOoXds+5L2mnTMSRsQEeFnCh+mAh3Gjh3JiHcUbSYHwXj9vDM7IvVH2432cDCUAeUnEMZe9BO
OVpC527TtY6WVxAgx2nIrdP5ocF4AFSFvjvGbVRXsBLie+/7wR3dpES4ekCj3PxlQzkU0SU52ega
BdPdlXwQH87nsro92CPzn7BUTmD0RhhSQIcw/ib/4XCo0LiDhBv9Yi8OmrEPgmFWPUB5agMU2fzb
RKYYoYKyXzh7WVEZF7C2R7ZV4XoPgBWa2e3DH2ShHLvFIYaEmmSB/YGkUCcYwEub9m40ly7Wfczs
GpxXHjKvx/U8wBjxvWCZ7FwSYQ/GWDYZGEbw6CJZyX+Y87fCiMdQqsXGLT7AJQufSy8XHvXlPnFA
p+9/v00bZhuRsskGcDf5NhEvaNdpQ54yUTmm8/j07XtybWTqTH13VCxgofciS+MVMx4sO1XJNMd5
Oq/bN0Fh1v2WMCRgTWBGCIGhbqMw/qv2O6UJPOUGtNk8qUCOtBxG8N6m6z14uk+qCzgQFv3zRm6U
017WWQxFl7OlKHe9iwCoRfXoyz4xpq2mWBoAzshnXfzGbBHMvDF/wh0gpcDPqB0iz3VeowRMqEHp
DxXfj17pWu/bFcH+dgWfIQMHwKfYL+6NdCSMgDBFadU0/lUm1CDzfrLa/NwNrBBpJTteKSPKi5sr
xMIK+T6OLB3+jlYBH1d5fjCY8KuUdV6PKCa0FWKOQbN1rByH4vWfFn9YI2vpqemVkNKlWxtw98t3
7YTmA++q9jiA0Y11M4BeLeI7KpVoZf6HglC7ohm3wiczIXAHPljhvVifkz/P0qE6EjTkTBtopYrf
mXeOcjkwpVSMNc3WmZViUiqDsyCdpkMZms+uJ5EqnA9Gtsg8OlyF4DgbaZhqfiffd5yx0UDRVAfv
nxGDfsP3Zdl8jLWG/4n8l/qaGZEhYhoPgFo0fYBs5Hkjp8JRO0t5WFQYdc7/YEhOvYxOCy8T2wOL
+rmoF9E3WWxuCDoIimuXfR2e3mdottzPBYpEu/lU6cqYnL+GLgj9//BFDj191Qb4EAobWzWIFMxX
WyqP1VvvhD8tBwpS07T6LnLV1W6FNjLDYFRFM/3a9c+6DcbGVgu/CaoU0V3W59W8PLgbgRP0H9H7
59xG9vn+JF6KVTemFMnaITTvfeM64HG4Kda0MQ0oItadwlwUuERJmu8nEtC4lHbxMt7h4LUQPkao
cHuVD9NJcuZ1rUWDah/RHB4cuow50hNjJOcxzcKez4u+02lmrx8cOlATOX2ulxG+R4L+EXmYP0GA
HyyCznR9Mjj137uWaYw2NwZ+MBcQuUlbIH2+ghW/NDL1CsnCF7HEwzdyTSBfKNLvouJuwSBksCy1
YQFzs+CwFBHX0+ZtkWBNRPqt/LhLLE/IFbR7L9J5Y+PaVmKrccVwlG6xp5NRMtewV0s4YL/ZTtHK
wjwCeV6zUiP7GjvU034OQwq21A7Ji+kTq8IXQFi+4OC5eE8g2wlftMLeP8MouoUjzqEcMRfxXXLE
xuvDuJedd1PYad79B+7Nf3r9wIH9BY6DAqiaV++QY4n2NVQo8Q2+E44vu5YVMolrgKSq+P1vW+17
JPjb23Dfi0czi7NPrN8JtHStk+QiQdZd0LjT6lVaSCmdI/Ag64PsANMCUvXqzuWHBv0BZkP2G1Qu
ea0eatg4Y/pudRt91Lusr2wHqLekSoIh6EXQzZWcY28O1W1PaE0FTPJ4aa1APknMcG2XrORCNHet
WnDE8a8vGidAe+fjWr/YexFGVYcyHud84wjEXZtYo3ZpGTdg5FplBM0bZqmbxOD0qqog+Df6e3LE
SH0BMCF9I+tMEO7I4rbcjw2cy8dzJuJQFDLI8Xavy+lU6FrkKRWNZjn7rwzZPkBNAsWkXK+Vo2MM
u/V30eXNhkCSnluY4kWdI9+ZAfeZyF/lJ0yVhUJJuY5z8KkD4O+w7wx4iVwLo+kJ+y9KVYkPm0sz
6/CLq+zdlqnkWPkqzuD+ZLQYs2FcRgcBbOd22ssoqOiM9E2MKxWGz8oNpXSQSeIS2RnO99COFBk3
FgwnITLdkaTpSa9R9J5gTwl5OlKDbitvZ/c3L9X5KnRj6x8BDKEtCOUzSH52dJxde7WZcBcJ4RWU
9Z9uuRaQYiDvAjYcQDFeMHtxsdaashYCp5J8HuLkXgB7GLGPKEmsXpUcn95GWavBX6d64jWQtv2O
JUfm1AdqsKL5CqGc9MSSl2mJiB6FhTkipc4NcognZup9LetL7eTaBwsFB7anGaPkQa78AgF7/HbQ
pRtl1jz3q5M5XccdiH9whn+ktL8iWXxRJmho4W+GfQkhrb0pCgjGvC3HMzGxJhPwDIe12kY3a7Zk
mO9hipTjbu8P4kmDQzvYQW+yXJKLgb9blX+SNyA3EUcEpDBzBQvtsH8NJ5RBsEfa7YZB3thUQJQg
csqAGoqHpP2rrUA8GFfNcB40v0BJauwvLrWl/96Z4LokYuAuXnfzQ2EA7pUvmVnf/bojv07qmizn
bIuSl6f4gPDJCCn2BDPJXhFJqFOjSYnWJdnvLauyqOZXMSRhfX33dTmILR6B8l8U+dVSrjDNPgG4
MxZg4hyDdYI1dxlKbAM+GCIN0nfxc0VYCBSC/c6B4/S99AqH6ECw/rHcWnKQHTe8O9KLvUz2LRfG
qLJK4tXxtknGVpqURD+Zmkic+mUwlYNwS3cxIOj0vR1B5RGELLVrwqf60f31TjCUMvRuuK5zrqr5
sQiVFkxkHZEd6IL7k1uX7PGzURaXHNJZAeO0J0iFbUrIivzZKVzOAYdr+WIB7XNF8PcyKHjuR32c
P1xIX65iIFPV+fqreLuGiUknt5rjofjjE8CN/A7yk9LUjptaRJT+Yg1VTwYfK4Ea/+oq7XtvmCTQ
Ch+Q7aw2rgMdw6rqmXwZwd1s00ro5RoE3uDn1RfTITdvEnzA0pq5G7Vi/t01sypXWtK6YuKx9hx2
YEbN0FZOITCdYyhv8epXrM081X1m5TURm46Uipe6HN0gheY9yu0Jr05CMhlSBisqqC7GuL0PaNLQ
IvMO7tfv6W7K8o6QYzK7/jy9LoC4XObLmWctsLRjBp43XRxOGkkrzQbcp1egIQtZHRZmywM7Vo0G
SqiYRP5hFjKfPO0vzN+lY12M0BQqSssj6MJAR85Jc/TtjXNpoR69NiD1JsSZosUi5iGj3lMTvw9o
NOlQIS6SdhvfJT5bebbpq1BNV1Q7pW21jky9my+vi6DXxyBfN8GBsoNeJuKy6FZFQbhyWNZSKegL
HKtEU/j8cSXEYeay7ZBBMUjr6B5Qfab+4ZawIoTbdFDJIJHF1iq+/UX6f6ubszhxRD/C8PgoFneq
ywtNsVsMAq3yuzIjVnHz7YECgy+m9RrEX0+7TtnA065G7wXCmurdOD002QuiBB2PoQJO2PnU3JnR
YYYaVfvvdGtiuJtymvW8cR5SY0BNB0UZC1ctY5YEMbCUAZNsLD/Ac4Va0iTiMA390XrINPp9PRA0
QRQ2BepR3rrbVTGmaqXMvDknGZ7pM2GVn3YNTdtcr7WMjOKv1+wOCtHdW7J1HicKNSJof3qN/YWQ
K3PzLzd+m/yNqRtz9zguRW5jhoiSzLfYFQITcED7NJAUQ9PCsQW7yAPzwUI1noeHUu5n0mWw8Io0
9jaDcg6VrtlcYMlREcGRjFJTFrucgDqwmYucwyT+CWGZp2R9rO6s9429d9IfVwTXJp+WFd7AS91o
jxWXzY5iIKjI6K292dJYoWFnmPN3duRdWa55ALezeowDBeMUk3j6B5B6pbj8L2AqIu689QYY8Z3Z
ofdaVS0NdSfXp3M2AFOcJ2Z8vq7qBWGflZYqVRC+UiAx+C5VTiapu79WXsjsPJSVzOPmpeGEGymE
okQ2azg9EaTHDqxkj/ZZwCFF1Ky2EUb0DNHOy6iTNp//5YBDgrHXWmDO1GNUQVlwf/K4xHIT6eJK
l/IiZ/Xe/cauv7n9NA1h43ZLRcRpFPjH8Y7eWncgOsQ0y6IqUdMQU+weo0nsOsV7oDd4vzf7CLrb
x1eugr1d0K2577CWnfqjA/Z890gmnrHZV8Q4gHTybwH+ux1nXq67J/QptDzg0n+m2XfCBROc7u4u
AJcm253a1ZdHD3nGV8dW2cgmw4o70t2y4yDy8MdhtstsLIVzBMJQrzRIxGykb2+sCFFcBLCpjAXH
bRfNBW6YfbfeO/W410LqEGkXtYphoB2XFPpsDw7ujy1+alnJ1gZPmessMdh5JteCLST7qXk9qpPE
WgKFuN0RIrrjpOAyZsOnLXqslB2qWBoRDiUtanoM1cHC0jEfDOBub0QN/9yVNO+x4hSC9+dvkH3X
hXlhVt3VmBfxAew5OWYwTEVaL3XCbuvp0wf0qTiK+j4FV7TBwxh74Lwfr80R9Dy1DDZ3ZnLX7OKN
G0Dw/f57NgWVcW03pDzQL9x+BUbEwIep3ANwzdROXWQcLZNGI/u/RDbA+qYqbl6CITAEqoESv35b
SCb/fp9dSp6H3oWYkcoX7X0EM/4lcRD+FF6902xyEDkQ3hdSpf5jHF+okafmXtOwdEcQrZY2nUIt
kLFTlriZ8axCnPj9lnoX0quERFQ4rmZMuBQyn/XZi+hhiblmeNz6pf60dPdzSYNqpuMHz2O4T0XO
Xd9gUrmyGndNKePb9jTY4yHnkyyegIplJeibFvFcMfCe2fuy4dK3+VjvH0C9PeHWUZGOn7noGT7L
8Cbegb0cv1PpV2E/yQNe1KpiY1IQZCu/nIv3uRpdNi0dlTIDs9Y3bya4xOeWhZQKwFJ3pAs01BRT
tlfgOyRkI6u7Vwrm2w/mEmOBli1HY3BDE5Hoyr2mr0GCxoBYVMLJZskeP4N3wER+jbIxHnu/A/dG
V3/iVT9shoKQzD77FqqGKuKxKAQjytefetnfPFZ6uZ2l/bWTU2mdCUGAlBLO2RKCjLHZthJjDuK1
LRO2AfxsCI57idVVcZIO8ESjFd77xQLkF6SGxvctCShdOTx8x++Ks4WFzJiMZaSTKl3MoSu4oFpq
4yWXpxCdTr7njznr96YNPLMnh85ENDod5Umc2dZHQdN6uHl2ygkxQQbvQ32AwL8WgcNRlIHfmwoI
TT8r0iYOIA/7baedkWVD6zeFBSqmxwcIqV4XgoidAR7LQs2jWKqJkqKKrPaey87DTyAOYVZFof/R
iiUUuFZWugr4d4MxxQAFrfbHzsqIGCJzhMSx1tLw5qqYWc6RFU5Oj0T7mxqztoDyNzah2eycBjam
LRog5XmaEL4doJDEiuboxnV85qElBk7yXMWLna4unRIAb+B9GrwZAMw0r27DdKjkb30RgMWPYyES
7mR/aaPKkrS356tD186vUPsBaM8kAHuV5vu10jBNCqi2drGjHjqNb4QsMsSXFJ4G1ziiKrQ6XTqT
XbisxDzNGxbM1KEjANG87/PLzHM2WCX5tzLwLX5CYj5Hv905an+K27tMzHj20xbe2ZmuJyobjjco
QbV0nJF/boxcJV8S3d+g8lS+ZhNBVp/szLMVfcoFyI3pUvstUiHJqZhmQfaSMZZgDAMreMa+2fkh
wj+Bv+xIg3RxeNIDX1z0SOYMdY35p9V4B4l7giji5RC9JmLvIHCzpDDL9T+Rak21uxeqE+f1Tuez
L6qmg451FDGGjbDiO4Xw19wWpJhL5Ngb0OVUIZcXpRWoZSvPzy5M/N+mBD7hednKcUee4ccim03U
0t2/Sp3DhFxkUf19m8PgjG48ScmNUBYCtnGVjP+QSVd/l6z9MLy6rDuIgJqu8lBjOu8FXnfvviHb
bvQVC4On3v6r9dz+SAymle622X5n4ZVfJKJz3tZnqdxyv68kck2PAf3cqLtfILzPd2u3ifvtn5Mj
DfTDeEeoG5OUBWD3ipre8R7Ekh5Ipn/IkuTcCzeNftm8iZfi/we+H+VC+PJdUc/tVPM9oxeDf5ph
zze8ZKuz0LXFJhqU5F/4CxH3i6q7mm61JjjUGb10RgQ2eJweaxR81eARI7OUwNJhqKHnk2g0lLlW
2i2ggKUi5MNbPSBX2PpaBveHXgX1sFXlKQqS6bfaWoa5SVADwAoFLrrmaVlzKvYhIcNPsCKKxJ/a
AqAtqS2IW8TPHnWJq9DF15N2EFGcaSJS83crcG0yQrsBe/sb9PxMv3WMH7TXgak77HxBoXP/QN3r
1u6c/tLSbp8JgmHfSSrRxeAgVLUh6SJy8mUqjbb/FZXLY/laoSYOCEvV9ZaOrk7QFsY8dqQJ7I5K
hB7HRrQYpgD3zcvcFiugtLP6p1EER5fJXWb3hPBFH56hKP0cD8GO3/TKgW31KLkyGByrN4Eae5F5
xUhQrKRN/RiwmwJzcG/rOjtci8aUH8JbR6fhxs3/EB7ndoJmC4odaG/43KNXIunlSYqgFIFrj8UL
jhacJwpk+VP2WA7/3ym703OXA7b1XmKdoSie7sX92LUhrgGGHk9Qeu7vn1tiBYCfK2Mt5WWnRCnn
+TPEN0RB/kSWgLPwz+5/rrLdNIcNQvb1GsGYnZv13j77u3jozl54S7yOX5cYZ/dJLhvasBb4LnIt
S7qObJR5xuXgRe6vCNGFlt3lqeoBoft+6EUCVFbBpeWm0qtZioS6l7KDmO3sPtMqZrWPPXp0xkSB
6RdXc81lfkMPciwxLgTFOez1Rbk3n3xUz8fAZGTaac76Ty3qqJVo37fwdGORDxQcyfLrCq4Nd6CP
8eALqcd1aSeJneV8uz06IcM35b0uFSL+WeQhTl5kdZAidKEcWtqkLa7dAcn/kDiG1kCcGmvGHfXa
qn1irjO9qhyO4CFY9s0nhe6/ksILBE6Z1quldWkTOG5DEdSyGFwVbM9GrFPgDgCUNezQiEhSHtYE
LiexJy9/HcUjg0YnUBsFgi0C+SKKzNT+o05GL2vJTD2tcuBlsYNddciBtr3aEHu+AYc6cZb8QTER
q9F7WXcZxWkR7AlktPochgdBrRUw9ZVfhdZHooGufJIbmNsRoXJ/32D9crK9dV8WYtry8PQ9amwL
NbEiYqd364+SCg6UqvHVw4u+QULqXq5jBERGKHcypm7czYPSL79KAzFdgVJFKJPCYvys4jHkbvQ0
7/KKvTwYY4nDkj+oDpsd7jhtA+Y4/bHcWf3CtXlvc9Hmm9OyOUv/6q8Noo+wPUxp3wjKA+xYiasT
fvepHfhPXUjFCDc2OYV/XA7CJnaoDag2POozp9ieok2OV0io2+j4WlYzMRT3YP7TrcUhv/4d818g
qkoO+VK7R4AWi1KTGpXsxAGK5Mk7D78d5hutfgGANT/WLYbShz2C4iy/LnJQPrhQxn9ovXkkwNCI
Glh9J0RZcV8o5e61W4xA79q03Zyw62LElDj/w67F22WeFbezMFrIT5JfKZsZd3DtIyrrslINdkoT
RV6hjgKROquC1vdpL1ZvvDiXbwQGWWjhYCWl3AoISvV72vxOyViceZW9p9eA4Fahu+p3rovuxPvl
SJ0LX0tOduZXw4r50nw4GsWijnpvVOtagdK19x0EEOxo1Lm0v84Qfgp+bamVmL2WGuc8MQ9Od3fa
yRWl/eZBLLqbsPT+BegFmyST6uDZNlkXpKCKL5SgOUKGD8g7Rz6so7i3djobhGWSlLkF9IdfQvfM
TlRsgF9GNvm622P7oafqzVkmSnGnc5OlQRWCPuyvhznoVvXrBU4FNliyB9WkAsQBTOWOxzgtH+jk
Kwlh+6ZYkDDQxuScWaX+cwQY+Tie55ati38u92QDnjhbt1WRfrla+Nl1SHn6m8MpUdqZ+zBL5A4v
e6WfvQcGpo1hFsiue0bwaRM69/8JnAg2pJPgQLuTklwmVXEuLf3p2ZgeNTrmAK/varOnuqkSg1k5
nfjKmUBaJBhFqHH0m4jrX0HFqiQFt8d9vcDFTM8plQeIY2u+S3UHIIeXhTH4xmvWWTo86zPJYY9F
VSb83LM1DDQUZH2G7Ei4bBRJr31tszLdzBX0aVMkdoyPIDoF1Ti36hxbij1O4z/femuvtjYMRXcT
F8XWzmraun5bau0YDtTolverTX1I9QXp7rX7wIl9A/ukg+6nJyGZAf8lMx8ygha4CO+SvP9U071J
ffE3Qdw60RgMINeYAegmAX8X3Eq19fs1r4/LJwa+RFCXRIw5teuDXIhenoFULdSKli4BT0DuPmiA
zVqI5D1+MboPitJQp2aWbpN25+gDGAULsDc786te4qw0+NcSUnqAqX9X7K7r7iSMtOPigPB3xXSi
LoPnagE6C770mM0okHieTZEA5OorsKU0+dhgPQXr31cc/yorByhjaTWmEFwLqY8g3Qug9LksD9+Z
2eEUkwjrR7q03nqpURquplM84th+7LdL1ac3PstmG230MNvWoCVXWu2Ttt/sKtzuk71KDFKH/Qtu
W13L3RO5O8Zd9AKsGGQsRJS6QebFhMb6qry1v9XWKaWfAQhC1D0A1TWWcnNaM/yQXf1TNxmzJm5U
ow/RvCduLwPt/Ax3RxDgGnIzBgr9CKVFjY2m9nJOFWZBtRrPAWtly3coyMcAM5uCbD9wn7DwDjbL
Byxg7J+yzg4qGP5Xs9Q/bpf4NvfoGZWgIPUbGm7Jo4JUvgmlDO89fZMR98Iznb4UIJNlcBkWZbCm
asmRTq3OFKMWzrZof8FYYI/IpzN3gTkJXkTVlWysbCNIoGMYCjDQs/AdmaF815MTOdnMvmXbh+Fc
ETXS5M0PSLdvkESbUpBP4FTMVZ0Y+fT8qpMDpxw9/Bjglxucl9IoTjezNfaYnvw8EJpERHem/ZNI
BXJybuy+BOmZS6Bue8kU7McvHm2BVed4IVhJreY1yawpggPmLj2X6RhXpC58fFRM7L4iN6LYkHFG
NNlFq2oGqiW7hp9JeD6i2BWwbJHAGPs348z5yn3wTxCqdcuGc/WzBINAs6VYY8qzZVdKQmfj5QM/
MnAwofN+QLWLlKbTYXmSdUW68AUp4lDnQFpgMpGPjKhM0B+YVzhNWhD54ByAssV3KU6eV8xaAk0G
8hzTmTEqiHjhSZIQBfez2hWop/aAhqWNLXqCLolQCQiP2hFJEcHeYwaS8coqQtJA5XQISimlBoWE
PMTeiogxyLM4OrZLz2WWyxQPr0ASEgBApawrlXmqo4RjkOqZO6kUYI84PCyqoxZz8xgAGkJ8mC6d
mITN96leA3ZLUz1ZivhAaAQu6wIvKav1k8fvVLAb2LC+5ZPqzZ3F+W3+n5at4iacUj+rImeRX9ky
4kHCWQnrBTuUL6kPCUPwbCGu1ZAlGPWE4lA8q7Lqb+d2+YNP/d/tZX4EhKOGXnZ/YbQITo5ehLU0
Ogu9PQK+gaNzABJ4tzWyzskESKfcb7pAenjAT3jMqJ3FQKm3lGdnsIPsyOwvBPmlG/k8orjGxRGo
Y1hQnS7RUz4wU3g5edgWBxXpJz+IMQZf5sMAJHSKHMZcPNhH57l3vO162ZURVJjzuBMjZ/AAl4U5
nEBa/6vh0C5f5a2o/1ZoTHk2gv2Izr4WyrRKUHIO76/C4H63JIrJiWHv+/K/lKXk+2Y0snXyeAYj
NqGa9Zo3goEbnf71kIvIsWTHW6mYxFD5qhzXXEMY6pPo3+QrMC5M0XQ+44O2v0C60RNhLCKib+qP
teFLxSdGXdtGWsBjlppRYKBriEBA2DjXamxVMFmtlG8hXQ+O3xirfZavSO/I21Kj0UyL/WaAFfW/
IUp4wk8J97pZLq9gvk0BjeOqCpXEhoMaco3L59ViwAjahDbTQOPSvWxQhaLQ14qXv0cVxuwf3aJM
6YvKpRL7xEeJMIyiiEh0AjUVk+ZfEeOTFXRmzPAv+l5m/hz0DFYAyh994gxzVeRqv/2y/SUobsB+
JYYyZaNviBTdvxw45TMs1tmADAQFulU3GIOW3XahXH/G6HlLlq9xSBAXUIj0O78F6nt9X88pr45o
75g1aqDooeplNaUHMwzcS05WxMHt/ohYXuyvHRqZhynnFgSBv5W06qBJqt2o03JTh5HAxPNOUS0M
t4WliZ7z1rSnQ7m88yG3nc/BdGEQR2Wo8219Tn/B4HEQWm74PChGCVNjpIT+ACUxgHf2W2MRcs4s
BcWhgNtAPcvqSHMeo8NE4n46Jy1sg3LxU5bJPb7w70Y5RzZ0EEV/tyUw2NIlGYZ5cKFwt3HVJycq
Jw7jt3kP3E5nxtqb43uYz/5mSxZInBBTIa8rhLgCAognLSnQSl+vC8uiDDh/gMDOldbbsCTrU1EY
y6E8MciYYgVaHFUjx7z1whjA0tBfQ+kRzbZwp4QfgDAHTQ/6KEg99ryM3lWqzRS+2Rmx8Zyse+9S
mY0Zz4vKpFGRm9X8kpFmjdvc+dTzr6CX6LsRmH1E6JawqDpbgIW7FG/u1qbr+V4HhtziOWVXw8vM
0f7b1hJnlEDSThrVDZiMbl9+tmY+XO0djeczofhHvTnLUUV+D2gfk7B8OoCFF2WOFTcUERmL080g
1eMs5FphXnDhoFRfYtAfxMPybnCm+GC09HMP8yoYeVTeyim69Jz7bGzwvhiRXaeJhdkPKJMQbgQN
6VdEQzcokO2jJ+XljpLe3H1ilAf2hU8dRaK7Fm3oj2TD6HCoQsvX2ahmR/2OalXSDNWjm9Sk2rn3
iJmu6KPEkvsn+uTdA3TkBnU9zjXXZnHZpebNMZMCSSk9uYd9IhxS+mGWSmDM3GCysE/GGgqFr4aY
wx9yv4ajCHERFojAlh4kiH9jFGSF5O3bEvwHvwny9yHOp1WiIgzwPg0bs/F4Fxw5Q9kj33WPmP+X
yq87ObIAEEgql6s2+hXVf7LTfMFgilqDKMjPil2jMs5rl4eSuP9mMRDV+BASz2cc82EtmnyzLOUG
1yfysW2M5EeF2gDOf8+3v4LhKhrHCDGZlvBLY/kaB8nWB68/Im5y7lK3UDafleHmsdNHuqj2tLhy
NR/pJ4NPMFkrFkrsxQWHBIyI5s/HqyFu2LfzqpgU5uwi3M/2kU0QLxQb/Jl6bHxKoD2zY0Ktlm9T
rKiuAK1izkUYH8D4b0GaSLJn6UbmCdXNb/lTeUYNfnjVr23dBBoz1ZYA+ebhHn3zaLCWHwzHezw1
Vl2/PewA70oFBLv49Puyf5A7cWasP0YFKFx98VlSaF4VcyVsahRh5dwqvt/djXq8vo5vg4I1DIB4
RIJyV0SQuKpqfu3EcYqQUcImt6Gvci9bP/FN0h/9HxAm0jNAtTKhx3Rsy3lHep2LcE1ecZn6ythE
URYdSWULA2Zn2LFytejdTokGiILfiQlJj/5PoUzD3D4okJmL3ku9Z1PZUwh7lyvY44IAUYjkDs01
FCIJsw2jEWvNseW2QvTrH0bMp8lSu4Hc5oFEEx0OcNaFFTFQjeUTzlsJJmlXUYkA83qVi3FEqpjo
NE7kOH9l3+oNoihe7EUykE91LcqHq7zoKdayUZnGNn8sxLjPDObACihFH4NNfrHQ8PqPKVTwOhXv
1Pw+uZvhYhek+QnKt3sa492iqeJg9h7nXJEsiAxMgzMd72IIoB9sOzBJr4Evgv8Gkg/DaGuiXYtl
ow4mmjFKKiYtgFWFkgkohhLxY6ZYOS1l4YguzAKfX2ngYidKEzY7fqLfI0G7YmgsX9R1LGUt6dxn
KTZP8bgV/mo5RAIoLxrNTVif7N6HhM3TplL0GXz7xvT2+WnwETz4wDCqcX+h4jsFk1WXRzF8j3gv
vAjBrEru3r5wVlETWeP3CUOGxmealEg0WMq7k2mtaUKhs3rr/1Vw02pesY4zbI9RuwcR8+rT9po+
RXYYL6AhMHxaRs2/ypQHd28tqLqNtyNSWm0rMBJxvWGvz2Rll0PlbgovxQ+FXxkhG7C7afChRYPU
1X/D3WeSR8myHzMGpyp2fu77qefl84jYxveOuJkX4uXQJApgX/pt7YqwnS/OPL8H0R6mbdRCwQtD
NQ10hRxOjuW7ZrWIXVQOMrDXS41GQAx19Bk6HTg3Za+HomJy0VUdWLRbD6dBAPhtVIBvgdQEGwoP
B/dmvpOPW+302WPLgKPEt6VFVHXDEFB9ysKr1u2J8w7TMzZzX2QprJczTHVFjeNKPxWr8rQSEB+d
y2vEYDMD6V6jaz2DHC8XLDqKOWjZOi8lywFK4Q3NENKEf1h8WBfJ+U6/9Fyo7HbRE5hRwPRyjulw
wCl7bs8H7NUXgjeAjFx+uc/D+KSqHXovAVlemXlVtCkJ/9fqhgHoyjUfA7T20RomzaTxP5x6iE6z
PleTecrIfWyk/DatK4TgJiVN4dp1DQYAuUk6jXSQcYNyZGfh31wuaLhwaU9n4txM0Paz6bpQAX/G
3wKuqibsKnJJi+CUJ2Idc//2N9sTUxAojsE/I9FgR7Tggyuox/TJrDzd4lyRb3K8kGIN3XqCZ3ph
B9dmIhR3ZiwbFy4MDR4/If5n6/9f9Zs+OCMaBJbL7w9lvU5dUV2uuahboEeShcanQzTpokBndB/4
4AZOerk4ZxiXM62YH5k9NRGt16tXMpNTli7QD20w7/xmY164qrmYktmzdTfIi8vG7Xd5ELVLyHaz
G7CGrllzN3SAARWxewBJT06iVxu9/WZ6yROpOuyAllWZwav1J/MgVcMx/O6LNV75ulgzTlytRHKx
jwhsAdZWpTsWRPpQRRfh0aswvAo4WecQsBilRxWLvwohXzILpp8kH4SXTJ0ZO27SxxFC0CT7guLD
uf/HzUE353GAvaRJpOulCxaWCWnWh22lrllunCqUzI/4M8pkNO67lSgqaZxfhQc88U6brozHv9xW
mmjhievqdVrR4YqTj9xPMATuxCPqQ1MOGw3EZmjO68IdCRZFGTVzEEEJa9SwH2QEzY6QPLpXv51g
1H/kw2M0O/99j7mIYK/H+G2RFshAtercaOnNKo8kU9oQk6d8V3VjBXbEYOzFO5d/hH1xpgwDsGcg
4OFa/tpzudXYAFNWEtlMnXYCrbmEir66UGLn1vrypeMJjaE9ZTfz49jOkso3oLc0kQsU8AVXOaRf
rp3n4W9FLPnL2+de/HYxZQqZZZ5da3NGf8xLp64lNUKykAj1Jh2z4glVrzJmcubSReq8vtYH966F
ouXBAZfNH7TL4lSvrDo9Jl6uePLb2k+TVhSbfOnnwsvPJ4hn1Hcz80LtUFZun9QkHeFigMfjMHGL
48RQ3tSN4nqUGcZiifE8gU1AK48aqleUi3G5CtvsFsS4HYiVRib/bKqxAwz0748UAGuvbeoqYv6x
rNjwxn28qaKzdGBmjlEp52kJg3sB0NsJPKuNf3doR33DpCKbs4bzasIT65sJQ8VetRLG3fatRY3v
gqR+Ir+pRfpNO6u69Du/QUbzsDK6/ojn5zKoNTag9Wr9uU77dUEZbyh4jwPgdLX9D5JcpxDzD7QA
QgLBcWMTsLQM4/6J6yA3U+jAEv27oeyt9QnSRB4DYx/azO8cSH2KNOIc4ygp4deDiFYuaTlkgxZB
FesVy+jIx7NUdzg1EBJNu89puuOkTBLwI2YKb+wja1z2zJ2gv/nJtG+jvQBTkxSMS2QLJ70mk+0F
jqKbHPZZLeWcVBWS3rBrR07xPqmYqyUZepaFdZsdUW+S+FUG7Pk7ANdC4D4KfbHHJkBgzi95iQ9h
L3JV8Ay12taEuWPVL2ui2WGn7D6qj5CBcT/rg3n3pkC/Qj3QgRMUf0isWwmQtKDP7PZ0Tt6DRLvf
fvS/PpuZ/NFgdfmLdlZhHV05uCMpxzwEtzgPD3afR/xa/tyMnaDQ5UZJzD0nujKNLpBDInwM5oJ6
vBH8xaI/GIbTTjGPjX4IttFrb54oVjr2XncVE49i2l1X3CCVtcFMQdFaz7ht0BC+Cn4CYUa+eo53
vDG1d57Dpya5PWslnpt0IydBf6qm65qS2Nmku7VqiJtkNVGk65aCseHMeEktFR96sKQR8WTRzWUe
d1QOFhnlado/cpUN7hBjblxcTM+XyQ3nUQrgYC6ima66ajqe+M+SlDQlBu2zodLJZh8Rh9+w7GTk
j7ec/PJxNlQS83Z8HkZgalUKU1SghFQB/l+AGoKWoiQx239U3DqYzadDqXKGUTMK+S68XFfLZzD5
Sv05IiptZORJzytAHhUY5td5O3QUljxjbLZdafCaFUlqN8/doZwK+sdbsKiYs+C98aBdRoXE1Z4Z
Sac/XeiiSW3xfNEZEVZKJgdjOeESgAnFQu31sgu0o1MdRxKAl1gHjFW8WTZVpiwEbHgLlegAIUlo
thf3OILjZqSqvbnzsntYvRIl5uG8Qd9sZyJhNomGZ9NrgssHhNof7bwj/3Xt0q98eoz1TpGY/tkG
x+1dleFof1NYAnvpstAr0tzdyk+YT3OGZoB1FSo0p0gVFmFil8bd82Ouv1xqKyLBSrWma4mrG6EU
nLcnoeyLRRdSAG+yqQXqyer1VDQB2C9JIQXCvSuqI4z4K7RAutCjKn1pgQKXUSEfkdRprG0XOhYS
920UicJIi4XB28P0Xt8s8+Mu08vGXz4ejtIbnuhXBKkxvjKMUib3Omm5ALKP0RJgRSfpf/zj1utV
Sx8iSwurlvK8ZKMhfkNCELecSFu3PWpe7JAQlyMKdXO7hOYfYXMH/uyXr5L8rJU3JZnR6vpfydJ5
z1WTADdtSBQV4WSch95apgpKPeCW//gb2RYbZ+la7ccKPclKISoiBhCV5DCp/UUClWumdf1CK+Kj
ruglGH8zD4TILPO5r4+WGF9EQA4Hbvh2Jkz1B5YCCr6/HCD1Id/pwVBwoUcU9ndZsjdNlWGHsUiS
uzQtXyowgks7lnYPmYWRad9b08d8U3eVs29icpzACSjz5KXy0noNDs9jU414y+KcSJNxZy1xEQ9b
YW7ZRQXjwlm3LWQydDfHXFd5s7LfzvISAPG9tffghCtkkZyqByxiASICB74TlEw5Dw5tNsmHAsy4
jfMnlOQbajXJN8zbaNBDSLVoU8/sgfTZhBmwXs4omNtAReXcY7zRchDDGAfqITGeUNshnpceMrwW
EK+EiPjMVJVyF+c4aBXHPUerI8dQNi07zkf40geMSbFUmbyedrmAUpDSQuf6RslkZpeY4HWDOm94
g3vQsgaqjNVOVIcLX6Bso63mHXd5KSLelIpUg2WmVb57vNZwRlB+e/bH7mAFOEv5iAWwxMGrtVsk
8zXZb5/NhIImCeH9Ny3FGQUncEfC8krQqWM0tJuyGg2AVCSh4spu8t3HlsO7JNAZ7UgUtMXsxAD+
QXF7zrkEnMhM/MXlmcBVLAeNDYZLewAp2I/t04TPKVHK5hgtSJxm85trqJ2SAHWTnNnXy2uGC0pv
soT/PYkMLOw/c4ri0p3zmQYaekPPHkB6PmvyYXvTOl0BaPbUPvaHwNyPNvFOyZYFYe5gDs0chr9V
SH+LRFdykhSkiJHlX3tR6rgfzC2reWwhpcAgSFcpX2AwU7mIGzAaONFTOyupp2iuFCVALZoXl2HP
dmSLe605TNUaAdBAqaWoRwv4e7RVlebbNP2F29qKCRAqJPwS82q0fNB8A1abxDtB0GfywhkyOdnK
B0bR/fD64+6qiSrxTO21lWmSldu+QEz2NEgtBoNnFxxZSnYQ+xOjpqSnFkfEK8CbNxoQZKFMTzbE
uy7h/eTG4fAAg7vadtXp8OJQVKmQblpZMna4cefnRHhoONX+AjqoYrcq7YJgqigZ+/Dh4z2xQLDS
/gJ/8XzETMukGDzCT3QsEW7oGeLKTiWWfZNJeWA6X39r9t0UsD8NR7eG3RjlrWHrYTcou3PO83Ul
b50JOj1RRWgRLpruQIdYLsb4KdCpEwq0RYTwjoEXezpWD+ySoSBVo6/9SjAIahMLPb9Tcouukgnz
mIAdtuRBYpmlsDRjtnRdSfeqlykiWhTSzYJFDUvNt402gXlFxBEzhwycR/ZiaDd7Lmu1/HMqnlgd
1xNEmmcBTaS3t9k0T1pgJuif/8aBmz9vRF6lgmc69vBbmYNlfUb8//PXE6FhY7S/t3Dgw4FuFvfk
SOn1cTlXw3wa0B19NlI734peWqmv7ZvOzikuslmuyd7psqUj6vmrqR7YcznAnRi0rwMX/A9vLqOL
uuYm/bZdbeqJ6gZGGkkUPaVVgRslis5kVfyR+FmzbN8u/Qao3Z5YY6rH6zaIm54Bj2kX3fRu7y+R
ZzqXtHeT3TXkL6V6R55WD0UD0obVL8UJiOtwuEkSAQp6EjjbCYARUW8N4udU7DowSQx2NJFDYO0e
mMftjxPfOTpAfuSMdfc1GNr+Ex60dfyaYJ2+2kI2zOJHmVHrxTKJY5ELd6Yk7SmnAIOvv1Z6/Ccp
SxaoP0LqWEP/8Oa0Qe08oyBk3w8cWHBa3dG8PB2JDnwkxIAko0sWARIw5BC8L8yTposE91z5vXyi
CbCEYHRdaB7G835eW/pumfz4Ry44wjx6ov2n7tyTBPsz8OzfySvWh7YQfATb5036+sbhxSbuRm2O
qbhUvd6mpDB4yM4t1fF/y8LCYEZy6P7QQXwW8JbT9e3l7TlKe+tFXU+AFO+UFOobATqzXFIOoZ60
qhlUBJ1kb52iKuhPwIGxMv/S4LScMqYyyExs8joi2SfBFHix1+5agrfTUqxmSxe/n83m31zbjMmA
V9spGFVmxXWyc1OF2CVcOTmRlYm9H6KB3CcacKpszLKM2qvul8M5hPfnj/anyWwWvozjFlnMvJL/
4RU0D41NNyL/ulPuK5L3obI/ot9GooPsfaQ9CKrN0xZHp+c4h07ARQxvJur36iZVn40RYxbdrZvQ
ij4S07wi+5UlMkG693DcmmajMI954uGIHYq3Lhm2y/SI+LlEL0xfTXoLyvhSy84H7hgMioxzm4mW
BrR7DhT42cNrU3NvuEVLQ+LuGpkPJFkwsHJvYNKpX4g7X20qeYqwEw+Me1zB918lKp00S3sXGK1a
r9xLXtVfquEsZ6x5xIoBDEm6nncI9Tp2TlzhPpbrt5kKZjTuTegLvqGgloDVK86fbcR+JkKl5AP0
e3jgJH1nbofeYmPb/b6hATHE+atppIf5ao/eXdTFl8o7ZPaFMB37IhIdak609Flegmgz8fJ2bbFM
pBQMFwImWWveifD9pnTEGsUm+oDpOt7+XVbUbla1jlST8BOSBtHffIEJTnLdt9tx7ulzIku/8UAL
T8TxGgjWaT6tZBzMcRDSa/cNG4UxWNnw9Z7YN9GOhO8a9rOjRZXFTca8vOGRDIn/UmPGYUSaWPzg
LFyEwdRNVnGkN5tQSzXVsBg1uax4umZ5qytHrpI1OQTjZESLOCNUkr8qd0nu6ErgIYE0Z/G0LB6+
NYBcinK1Z91fcMIdFdMYrdjNI93Pc0PuzjKQSoxkVEny0cg2KtPQmN+ZfIkE+YCOLQwG4rle5aFX
abxOhgCzTAtC4yt1nSt+8qkIsxlxayeyI8QNqmcCR88UinpVz7phPonyd2TjRzKb+cCDHnSHYM8J
tRDv9JYy9ePuR52bPZ/7PP7ElpM9lg5kA+tXe8aABGBhxQcT90gwHNswCZXFiOP89q6cYRmq/ZoN
AbHwLGxS554mtCUiUnDcK3KKW15PSwEOHYaGgxZfajgbTrJa48hGZ1oo7lI+nyVgJKIX4wA1wvkd
5gywogoh/ihqe91jRdaMHTyUrMgO+Cz1mu+knsWRsMTZ8RPhsS8FGEnPnCuXspOIbZgrAAxRIW+F
idyd8HkjryOGJaWie8L+s0dz1QWGp1tbTG1v26RAE2lO+GmZihf4tYQZfpUGM8/IVdSX7sqB7Xc1
oOqWuujjaN1baZq5984azUxIx9jMGQhbHF6F6G93u9Y7mZREz5h8Rm51spuJr8xNK9f411JudHUs
qpYIDytsEdsbgiIt7a00tkNlX9X6C9/vOFd1v9R2o5K5JjmevktjPM7iaYjZSnmRJA6XlWz4vca2
aUurxKPLECmAaJv5Rci+Y9vOIObgnySZhb7IyojdjqgenoyS4o6s4I0fL+W5vM7PgHybhxUa/tEx
649O0a/9ukZ9kt/Mswr2XT1jQEaemzaz/Vu7xC1dso0LOBEZJ9cDvbkmttpU3ZYI7rdVT8evbAXZ
jEknoZvE6A1gAg5JOq0VsiPtOJANqjCkAoBK4Zd7tWocfedPk/03XxMHsLL2FW192D73bSOJjhDk
Wldna0cHkmatqgYXFYqe+IEqSGa2JE7nqAjCRN9AqNYAYIiOu1aJiBq8cAwT+6HELs0Yg26N6EcE
eSMEifyusJljio+1TIks88DnawaciqpNBx2L6iv96j/rTp5DTvQxX5Lh6nk7eSVeWc4KHPQm2mBF
Nm49vF7kbUkiO1YORAlf36PefsOta3VHSk30HbwjWNXbzU3VSKXOaFCfnKWbl3yoFtJWbJAJWUG1
0GqbhRkCsCI0YkWaTH73atcVrYqYsd0qAkMqbc62kEGzYB1VJNBQ/guPh8J8vf4HY6zxVrxP0vFN
4AhrACpj0vPXMSd0e05j9fCVblog04GbHxBlc7MM0BKYWL7kh3fDCmNwMNQZM1mgpTW+uoTl/vAu
w05oY7I/e0z4mN8JhTJtIXTMqGyTvs4YKZNKksUh+Xdq0RDh6XsG7MCtT+1dNNgJdi3Lu+Ygf0JS
HBk/cx2sjN8iZpcZR/Xm8EdDQVEpRBPHm+bmHx3ddifbeB2yJReGs5ISAJUI5O2ZYGYKiokpol5r
zdHOIoq+TOUkLVEzBXeO3OIVdWS+3lz8tFm+beY9ezuCaO4+Ct0QiMfHybwnMiR182uv+aA2AycG
5W2tuNLkaV8a4nTCP9LszNUCw5TOaa1NfBQMLerqOjH3rOZGSnOOpR9mAE66jMIyceBpedc18P7h
tuXfKOWR1Z6tOE2eXMwH1SKBWCCLEa45LplJ2R2O1WRRi7Z4N4/xKLJbBWpG2lYAKHuuqPijNUMV
XA3ts5kzeYrySbq3m3/5VcB+tK7ZEtG1Zr8isv/eew61YdzGXE3IhKGsJMEf+aTKpXfb4G0DIVTn
k0NQR653uhgdFUoJMMsZuMkafVwfqBNEpwwPedSV6Rpj7WnjkhC6P5We7ib7C/CFo151HALBTj1p
hhDg5a1jEzdICU6v9GBdCDpTlM790rMEKzJIBWDv85llQDggTevOsROAQmfGC4ABH6TU2fVO6+sy
aj46W4zG1cbOIjZWoQHxRp6sqllyqkCqbYiBkjCskWeAl+ApIN42dyP5JiNQSWANyzPv2rrPaq9n
HE0v3n5Y4W0i+Vk8eBukOguqnkb5lkQMWUDg4EEgUjDYPIwoJa60w8uq4i5E/lqhMm2+aYCmca+s
p6MTAQdOQmBzU4oHj9+hdF8r4dNb0NR8gukaDgTO3bG5/2MfcY8vicPPMhA8Lbxiu/A9bH731Rvi
MygBLzeu9A39F+SSrxPVK+suWh5fyKAKbqWN0rxuKDULy/tO79RCjUHBqzlttbAD4+pgISygpFLx
EYd85cYrApg3vFuegn0E2Fp1N6UwKHA10+i/ENS2FqGgVT6rQhcTFAx5tSpntmHP33x4KIH61dfQ
UNjSN1VIncKhc/6uLVPzqvVKzJYuKMAhv+YXS2vNA9YddITgbzbWw783bR4FE/hNEpG/i5tANbIk
yg5qiacIfFsRNcb1kBnyJD9DW2NC4saO/K7sGLRJOKadmMWtUaFW00i6YBDg/4FWbzEQ20W8W0uo
ol7lGbnVRe71pZqBw3UrILBTHKgAxkVXeL4m16tUVA39kQ4G0wVNPVDBq62f9z5AZ9YDb4dXPJtW
1qrvl1nsrYjGz92QVNnuqsjCKqgC4dD2/Z1SL57vXYWuPYQ7rBzFXjdplEucFkYwTPUg36Swe6nG
KBp02Ch2pOj5q46nSQxqA6tMuVOd+Yq3U/KaR8UqN/irKEkn1px1XvDPYVxq3m2n0QaTfDPchkLI
BcNh8cQiAe7Nyl1PMEoRToIQ5Cf0eJfQ6vEpTIlnG91gahMri+Na6EvYWGHPvKfmBPcDI/dZZFBg
2amkrUf26SOAuxTp3sLs75HgZsEPwOGKnHwDyIV30+iwR8EOYLNob6MsF0LJnSDyU+l5PG+Alvj+
ccI7W3VATGRP3A0eSpa8UnBksvlcF1xdJKsLHrcjWlzC7RrkHiqH6nku4+fv3nELXz3zNvT6sB7l
1Dnfg2uHcIz6VWpZ0xG1zcFM+vwRkdZmYCYUqUhJCzNpLeHwf65nfSFJj/f0ucoJt8fY/gQ4yNqM
2y22KyY4va+6wldPidNsuucclcbv3l6cEeLFcT+hyxPCjKcityahJp5Fh/dCcLXZGqXfQseeDxeH
KE00e0rS/rdrKE4oNWo2PvhC5kJEFh+e/Adf1APIuwz1wha3rDRwxeRDIGx9zMDv38WN16gPzL+1
+2eYCFPIHsfQkHvg3E2ufnf20PriRS5LtbKpwxXoXbTb3eYyzsE3axdre3UQECH3AefVZR8v9g/7
95XmRP9IhB2KaGh96CPJIF5poL8XrJFofkOT4fGn9zoXq2IkPwyY+DJ9TLsBBWaDBNGrCnT1We21
kbbpadwVBL55t5EDFcLrn4zW2HihzUdWbUZaV0mY4BgMmZJY52cFhsBa0mawVtdBEayihOsDsUDw
hJWm24X+naDT6mkBx7hoOrETAgleduAyT9uzRPobC1M9zi+LpNQW1Kz0PJiZoja29MF+NiY1oTh7
cU0JXrtH6Y78CnuOWih3RXDNgSDYS52qpg9Rry8Hx+N+7A7dfR7bWLGIPG+/1FOrjSbSBq7q+BPP
ecEO3KDFQoKZHFdprqOSPV+GBNS+/2fFOZ4yiCqAY3qT4WjtKfE9P+je52YKfRC2fJcTf6GVSzSz
Ld4YNd8OtGkQ+btDfHJ12///vSnqiFAauRm6JquUGaoiknZCaPwFXmaKPZTeyiC35AqpGkhgSaTw
gAdoqZgQG7yVOV9NF+lRk06oQF7k7zWcDurXlONJeNZZNNwdkmHW15VjhCZIXQocfwjRtuWMH6ao
fy/9CdNQR5IuVgzAeIxKjwdmLrd1pxpvNTjJ64+GPVtld/595aec6vShsx8Ogui5+8UHE88WSuyE
wxyFqNMI8keEU68suDZE+xkepWycXY7Rn0GEPtRgdsLCoJkoRnT9ugAy4DyU+uriY0BkLYYYJ8Nk
/57Vkl9u20RwcQ38xECRXUm0VMzN74vjgWDBERuHkFZ1qUCxNroWJfnXbnx2aERif540Q93cdcG3
socQLOkKjD+CKGEYIb3fVLFmGp6o9DEgeBvwy+mSLp2J8abI4p7uTKQvwELgN2qWsDSUHiQFtG3c
FbVlVSz0EH8pfUt9bM4v108R2Tt6SSPKlgohTIVjHC/B9RTlA9wGDt9PBQIwlqrlSzVaWJJXOh5n
oGqripWHmnVDD2rg/AkVGIoW4K3DXm3QalDs/C5x+s6dBk8agHsY9PEs3jE0NqXdo1fiHxLlEpUY
oMED+igXZt7/8xxDPeLJpJpbjF/fExx60r4BZikp6XoXjkfQVLpCHyT4bi1NnrDWqC1NEHBMRd5x
nCeaYAxdgEhUft3v3sz9SyAFwQtG4UZpkpl993rN9pZ8I80e5TUEvMQSJ1IQsTwPSOpyhA81VAbi
26p7NqbkWMlXOuf0A2mLfw9xAHVQX250wGukHsMfTo0YVrSGkxXb2pQD6nu/G5ibFoaSSX2ld35P
D+vk1gqSC2i9d7bGmGv6j5fL9jO1lXPrtgTZeKoWvb4qs7yK5/WIx/qoIM65y5S+ZXBO78bpSoza
DABOoOnvSzRcQ3QNJM/URDXJm9J4wWdNJti7TOpDXzuJIg1PFKLTcMyBFIS70JNaU2rIm5wnqkBk
+IStkkqkDvIjAm5hcY/R365rSQOsIhI1b+lxjBd4YrmXh0H3MvuS2CKAICZ+Tc0gzl3GEV5tgnrm
gsuFopTlefOqu4EGt2zqlHrQZGz/y2v6S2EIH6TE3Y0fe/Z767A9lU5lvFj56I/+4SqQbyUtPZcT
FcyE4UxrvtvGg50LjWPi8q9SEhW2BK1kKAjjxW9o/WdcItcImhGsrS8L0cSriiEAKv5PVJHIJROg
huRjkhOcNufW3GSdPh3l207uXhGR7DGmFxxy9arEJJ7yleOky8d8CFhx4mejtL4pZXCRgzK8xXT9
mgAFvDTPM4e1dwGGGyL6Pep1w2nqyUCDd7PvBBiirTr2KBZvSvnxcu740uiSFiUs7UsicOF+QCoN
vntpeea7I1Kn9OTP+dsmE1Q+52lP27285/nFEBu4iyOvxLlwKcG9qIAE81U29Ah6TIQyt285z0LY
kQ91eVNjHGy6wIt2n+50dSDFb8f5PaMxaebOG/7cSr1OXlE3PVngB/96xpEMe4guLnGttwcIFsIB
gSCecvYsFvZIZVVi2gaWBQ5zmOaEkMsu4uDmTgXQGJ3u1Y0tygNwmDWdwyXYNDVTfVuThOvgWgr1
L5soEdK2SGo1l5XP35op0pqA2tZm/trbQEfnlwpenzLvZgUlz0xJTSsiWu6F0kXCPpTORNtjIO66
aAmDmZUUJLx5OpzFDq3cd6A0/iG9QmBZQhMQf1zSI4Ogw3SAYybQ84B/A3Mz/lCVG1UyfthpwM5k
55VfT/SbEdAbowbc+KVWaaK9yMPKEZUIEyYsfv63g4pJXVYlH2zhpmxmIqylS3ZpIz9GB3hy8nI0
M+JrGX3U7bBjQgYcx2/4V2mT9fB1yQbYR4UdY7ukfYCvRWc0omMc8xyGI0XBmgx+Uv5pihDChlHR
/WZgJyQSuAjHt9EpvGsQBEXLbpoEUuKHP7YOkSSvwyLNr9gZK+7JQLBycI2ya56jrdfo0u1zMOG7
RFl1S7xj8g/mfVlhpzw6hoRon1BpcXF9S7owhVEhpfNPzN2iVU+hNnhv+ByFLd69YE0FLoUU4dBi
mtWRf+WNHcFDJbuDok66AcX8d+m6vyzdpIpGaQqQSALkR6HGHbATs3jwYnQFKs684Nwn6TTWcChm
NKqFiUywRybgQ8s56vT9lN3OAVzHcj0vq4l9EwQ1gWc2kHlVpOXjBWFTCVmyqW/P88imwP8nndho
eCmnZzW6UzIrZv9WhUNit1RbHqyE0LaTkOhn6ELaPETrkYY+FA333Qr8enLts7E4DMCHvuk7dgA4
UWihqhNfoCh4bcohnTXc6sQs/CZzkfnznAlb6d3ci30Oq1MlUNteca86mGN4CUd4BPOkglRbKTMj
S6VFdRgdhCsrKvS1MxQswmsYt3NubqQyKCRRSqCPqumqTRG5nZ3TO8PQ5ux5DULpfR+sv5piA1Z+
moEV57Pzzbk3U+uNzmXC+8NU+DrqoyApe6Tj7hmvzBnOv/lg4C+KoomWjkOQZxdHbchTjYHwg2DI
AwjRapoTsijLLWOTyk6AnC83XhP0qFqikFmnypnYSELjCb4ayuz1iK3KYBKSuRofrKaDF3LqYypB
IjchI7u/ZvErFuMN66M6kAmqN0UtE0ZccNjlvmIwbny4FgcwUkbAwg34BeW1EO9EbfgW832gWMVT
X48quDOL6Mgb3/rasK+dITjrtA1XImndtTgUaM2kjYGxqmyxchz1z7+1TxB6UfdbmomO2vKqBYFY
i9JmVxf6EkgkzrPdR2VwVKOijy54AxAHW9fy+s2yXe5U3ZhPoe6W8Hml0zydrMQeAhvVWcDqBtdh
hyxIB69G6kEQeU9iL1DPDM6U5a17kq+6aW6+EQXEeNORUX5izGL0+gRz2jGMC3hJYa5zbSbES/Q8
WMfwlAGCQWxCOD3Fok+rYwVy4h9CaIS1+KTtpEyZ2H5TuWhItJWZ6hbh3D323U3ZWwxHDzJOiZSj
hkNlxyE/SdjE4lgodD2jlfHuAY7eMlRvxxehib5JqUux1iR31EC3/FOWHvpj97znx2ZO27NXJrWr
6ouxadOY3sxYJp1d2T/dNndKC2XhjpO0K/T/1leuip7bzfo2CxRRYUuD90ABnJuRCXmhGRpy2v9U
6dkyAWHMcpfixr2nRQFDEKpfN6NGvGa6gQjChcF1YJj3U3DIJ5tUj9I0NHJurFMLXYOIkvE61nuJ
fx6YNmYsBUbRmPdG3gMbzPlIdsbpBE0J4CGauV5eI9VKLZy8qhD85zco53XGqh7+/kAItnjY6dgd
4VZo+SW2BvlwGA++yefXNPAgNXF+AAUbQsmB/hMbstjEFyGKGrCvSYNPP/cQcxd03c46xg1vrQeZ
rNROJamJNhRGEbxD6gT2Sny1xea2Zv2ABjz5X0EebKCfxZZnU0OqQCpSG29Yv4aoFf8FdpMgdhA0
tt0uQufjuIwyGXk19jPz3Y9FAA/jexzJNZeNzhkCkIwwkxjD76Jr7ffjTJiz0dJ7aYV9N5FG71kN
1du0vDgPwc8jC/cF24KBbwZoD1kOK+dldfujwA35hgtdbd++7xlvPOUbNtpKnJXgUUrn8YeLsqwx
OqoK1YZi05vZn1sENSJ3M1NuIML4XS3l0FzjA4NY6QoMspA7Nd5StRXsIhpcAR2UNBAhJlX2zkxX
my+HVOczmKcb82+MbUK7XNs1UTNIz/zLR+AW7/ioPX0u/hNAbi5aL2nxOENfaQ9TLLqAQK7lS5IA
bYYN2DE6gfUdhkyGU74Yt4McJpS7EHeg5nHjySNJAmMfT2Fs9pER5gLileAHLwsqF3/96B9CIqxs
Bw7D1OZr+QGxUqPdWSuNqsV01ZdZC7D6IW76sruf63w44hbDPBVW87rywe6o0kpVMa1Ci/YqquZi
hXf47cgmZLrDOYpC8X5AB/pxhBGz3+RRvdvSkCWQWGOEGWzevhp+C7UmZhganxwAbCPT4OXIibu/
7vnGiTJXrEP/5tmty7VDDg8xnSpzv4vHkZGRcBRZlYdtFfr8NDVunTmBFYDNtvIICU6efe7FLObg
vfYEqiOkT+ziy9bg6gxtUe2lOlXDeZ2jc0G8ZzmUE7z8S9fsJL0oY6nySdgoDFJVzFKDzSVRpmeb
KJ7qmj5r8zWElIgIgKompvBm2rdHf/5zxlqYEnRNnkMVbi7ecVqpGM+f4aHAIO+kifeeLsryToPM
BRs+G+cFK8uwtKOjYAWtBYD7rV0/NwTny7b1fI7+HzMWxxJ2hlC7dcrQnLER/LlQADmZql7SGwjS
HEOahRB4JE0QP8X5Xp/0Q5C41i5FkKfznzyFKmTkDU8vf7ZuIGrmJ+SNPG29F6KkfxUxl4inu++c
7h4nY7zROQGR3dIt+ZUIHJJtdfEPNRsamWlV0NWm93tfFF//FPMIdI4ZPL56EOj1tFlLgyet31S2
HsRwv6HQbIAUHrN/VzhOIURru2cen/HR9jY4AzTa2XUssaynzYDFkU+Obil1JX/jHkH7mL0qGWdE
hnoU6kgXNjYAU58qGwobutF1g7xQAwMDwXzdprkbC9FozeReX4qRTWHC9rLEhrs0EOuwyDbM2+QE
uPHVUgUz38M4IPAa2xUKRwc28wLjnR7rCOcbmqu97al5pd7rFMWb1+6kPJtdTAoz3kTGpiCboLTu
W9+p19YZSmsNFR+EUO7ApUAXYJttR2ItIpyEd6RJDuGlAt0gZ19/dZsF95w1Zm6nuE+Pf4gNGB7+
jS0PBYMwUP8lMhxfL0JtqZINWeAO6ozv5PWkZbmibNVFXsphbiVyJ/klRo4r2es5jl+6eGj759ij
BHJTVlYJmpkSaEfbN+38VqDL2RdOqxUeUZian84cYiVtx4ZxEVc7/JgW4QNn/BQZYkzhj4jD/E3B
AgMnuDKK77/5oqS77e2iRuvso18BhLnLgAzauAjj6Lv0pQzISFz1DdGD7seSLBC0psm1B91kWqNx
a0AyXKup0Y6CI6NU2ac61wQHrZzbZ33Rmebnc4gIk5ni2JsTZZTDoa9z2fn6OrES4iYXVsaa+xmJ
IfQFTvWOtCRNxFhDXPIT0annNtHA9kxtahDqwGXZu3/PJozpKJPeyy/7u36x4JnP1zsh4ZHsokGk
pEOo4mUhKlR2L5TWz3rU/pCeYVyY/fps6WfgPgndvaVaOlpiZEXxQPtoJDRoJgfLymXVT1pIj1dX
crbvZiEo7nPMhvnoE6ai+8qmmIY+oo6QtsQmrbBk8wbITp+6+VkL1IyzyWccb7wstnUUHWyT9hPL
rbYcokhCGlMP2dU7fT8eihEnHvPRXvjafMzOyOXAX/zclcOwPPvPa3lcT8GCEGOQb9ij66ag8pLB
qljZzIiOtB5qANxGETQK2RyOOvmNs+N2yN+j1zq8NG+1syd7LyZyQ+xnXt4fFTkqD5t20sGQwkf1
qWmFovOSUDIw+Y85Wl5jvuwQtpRoQ46IsA+tsmpMC5E7yMYwe5O++rs1ANyINyxDpQwZAFk7BCc1
SGSU/YOY8TwuZ5hOmCEYzd/vsEC5zQzBm/U4VMUev7IC335qqDc98fFm3olQR91R/ocXbg1Zjs8Z
vf32a5LONVmphJduGAmD8AenJylu9cUttstftOHOQs8Cq9aylBAWWiV/kNeP85KfqEGAPgBJGHM2
2ta1A5Qsw1UuC59vHhZlcAlx32PWYlLJSGRib1mrM0o2r1Qcl/efPr6h1VNfd5LRBAJ2uN66Sq3L
TRuRtM17rSyTtQS5+k4jmdrGTCok7fnVuCFM2R36f8eEhos9HPDTh0pPTwlxzhFFGxJhgCgFcliM
Es/kyTxRK+QMqCH558jouuIbuUVM6Gs3ejUZbhDQ8rXI0ntG1pQKmXlPG7bt0DGl1XEpxegKXVXR
ZErVuMkJmuOse3kMOyUu/8B5ReMp/Gy5ntnNPJhicZhT57K2FpJXAaq3YcF8ZTmLPbfYa76SExoo
fZEx1O7ipEN98JUSUIsQ7AyPbzeQfLLxQax9+jHjCKroIfXStou0RIl8qy+xNr9p6IvbAhdvB/HX
TfYwQ3aicnWLx2YXzmfvEyXCuz1vqOU4+D8PbBVS7ogLWdh+Uor96nwgg1Sx1TN+M6MoZi6yhFqu
98to+5YCQ1AjeoWujWWN/rsKdENxKHtLynFoPaMNjXEanpXFEz04xa6hmwWn99VsOaJSCBz0QlO8
L67cdmnCD6I2zwCkGjIuBxuB7iMAS4Ou7+68rsl3nDDLPa8LIufZnZ5/TEdKcEn8/tzwQKTpDrL8
E71CsswFQ6iuuKcFijo08ixU27kZ9XBvZLZmXu5NMy7RvXHBFyeC8qgUhQBf7EZonwQgrB0p2YKX
j6TdwwkJ1t0VWAV0aQ1aJ2UD9dIctQGDwRBQd8CYcl0U3PV5hQ+a9PD/rtA3akR++mVdFjZuoHzy
rg9sMKvYHVE8xhQH5qfdej8KJEd6mEKmH1n8dr7ItB3hFAjELz+0BKmUnZ9j9IUYtFMEDj03/1Tv
wGyOTOw+pcp073oS02Hydb6CVpKdPz4UaHihUDs78uRxWNS5X4UgT5K2tWWvp6vuXpUiwbhsMeTE
f33P1g9q7P0foKdDOLdOc8Gy4jkEdbJOXevrW6LLZ1NskaILgXrcZKxDHMurnWl7xR6rp7oPjtY0
K7NuvMuFoDahbuWzbvZ4k2DExjE1QeTCVxFRNWuqO7KjOfUWkw6v/mIJ0snRHlY59KE1MMurPnBt
KfkmbUYmzDrrW5+sTxzd+O58QyX0cLeayUMvW42TvC3jpSWA8eTTrRT12q94QXExYtK7trSpM/7l
TMfR1TbI4Odl1Qmg1HbAb8NB3idfnRpO3PuLEp4fX1pnyI0iKPtmsSUSq6WCi7gJo+yYbRAQU3yW
FZUGxyJFAKTSFmzyRpXBy+rlqy3tL5z+nD9I+iRye35dKYYFQudzxTd9QyCrp/eAYKzi1OPgAG8W
UDSY39wMntDDYaGGtcqnyzRXo1MLHa9lMwEmlON+1Z7q5lAWD5U0QB3ro0i6KBr1Kw+CaiTn2gsT
c/sZGv+0tOHxvgtIUYTTCpJuTApGBrRHQmZVeB8t+QTDg5DLQ+G1P7Jhye6mvqwqxiQL3njHSvXB
AMt1VbwFpXsIM+vU7t90g0wnCplC2u7Wc2YBqTTt3kMxS2J39eW6K/MTmN9s+/bijKM09hpCm+X4
14IoWn0M71rtNcckqYKw2nMVNn7flDwuj8MBYRYZJFS1Wq8habQ8MignQHRtwRlaRwhejapiYhh2
amCbPEmCIaBf/D+5S1dQzMyyd/0JGx9CeV8Addu3lrc7v/8Oa+qIEDfQV1VN1dVJN6teLlgclQaW
vg5qfZ0ywnzSbTzNb/ayfy3iOJWd+6a2LTdBmu5xn2lBXSPfDatsy0TEURMZXcoX0oCXX9fpXVEi
VzN1S0/ErESJuXPZS4PHcob3m5YH7gUg8+Bco4ESfYizNaRX5hB6Ta++95zthr1FAIyJ87rRQQdw
9x+Wb5n9AAGT4IKjWfPM30mzy76e9wvEVgFPxZlZu7nrUk24Et3C9d5HeLpTEgyanHrw+0CUeCfB
kvFBnlUqNq2+pNCsqtMy1MNqLmMK9n9qdFnoD91+YoVsiSAk7D6HEzMWFBEw1Rj1EP71KI5T/6O7
qaLlxJ5OPgq1sRydOzA+Tlpmv47a1zsCE7vDbg96PgZVLSuVn8i1uRI1O423bVBOzuB0MCHIDD6V
bcd2EPDN7HTStohpEzIgz3UCsIJ+7xvccmiBkj4EW5jG78F0XiI1E1koBDqMnM1BI9LAvZDL3O04
9czanHzhdvX/8HnFX//BB7TGRnlXp2guELwfWqKbNYP+TMEjyIm6tBGAmJatm3MyvBcL+yi375mn
nMP4GztupOFWhJ4cLsXNdPV/b2HUJeRrawfwKVeJ/Sxq+rVsY++/dcfNCNwxWV0EWajUMs53VE1+
k0pas4olvyuP+lZmXwa96tAlCeX9xgVnV3QIvvvUZ8RBxvYtpCoJG1QWxnmgKrixBvGrmPZfuo/p
BHQ4PepPmqIVXftf5Oxy5RJbBbkm/XmSK21aC9TqSePFFkPTb4rBrYOwM+07IZsdJ8iDmjKLX4sL
1AqDpPrBNgZfcRCpmpqaMg4ypc0tDmN8lHGevShOVSlGZZ2x5ERvC1Wr6xrAHqRFeBipet9lJWZg
+M/OSlNvLgtnrzhXwMzUS9J0vsWJ2a0g/gSaJtWq7tIJaJOIxqMtXzF5SzyZxMvdNvM9xpv7uAVt
gTz6bwf6wu7+18ohLLcvogkybMBznUpLkHqAhmWrzapHzm/D+zAup8kv2cDQHlPTKdcTvF6NG+tK
bRrmahfF3BSsxVbV0bNU24UNVr1BH9pSYYbDSP2C9KxPtOg0Dkl24v7ix4XfneQj9UPVEDVZEEwY
kWthW+qdGlKAe3C1oV39WHdpB5/jtm6sggprWGxnYVMaWm6q8rWu4gGmp4XxCjmMyFBpoyjYm/8x
eHqKL82pE2ZjzxCkKMdAcaYHemiLJS73PAuexOtN2qCFRbzpHekOUfwyzXsZP8bpTX4T1tYKmRE8
vIsQcxew9jaOM//2qRoT82vpB9lZDFODozrgRw5kPJMyH69L3+fnQZHUoGyQKevPbEuCtO96X2nd
J7hZwJDTx98fCtvP6yMTfmlhaNV/pi4ytxYWi2gLL7By1+tayIiUY8hwvKnjmskoWy+62Jk8ip0m
in+K1JuoOknK3kEaIr2BhyWXbZW21jETTFDrafWpeURGQi/MSr5g3tpsH1oYYabdUu6xSBYoF1mT
sdKjqNGdRH4ziCxMLXyLUx+KrDbzzvaq33YBiV5jEN+VNn4dSE0RX5t62bgwrzlYQPQgOkzSlnsp
3Q1JbwLBkvJiAiwfD7Clh1PFOp2X8+yM3cWYJ6ybEq9+AUwZC+UcGU4cSUUVLvIftbkf99zf1QII
5Q43f89SUwyY2YEziMLiVrFyaHYJjIyXDuKM0d4JM9UYQAH2WyE6FA/4/fJvYWxyoU9zG80GtKHg
rghFbn2sfJrSNcRLipjP51Mj7Xf0VjccJKvJR5E1+8n0MaZk3qb/Kr6YsDJvMqqIox/yrn1YjyP8
GYtkYvt9rzUHULBp9eD4JRjepouRUSq4h1URjtrc8ZeWmOz8Vuy/o0/oZZ/N+bb6SCxmp+lv8oBS
D8x+YfE7Ep8MfW7SngI+QA3NnvymxKUhdH6CJkqY+/32OjFXhF/8iYKilBBYu6v1+Wq6re5kJgl3
36o7MBI1SUSydxtrVAtwHBnwbUHTRpwmXmMgYJCp0HrwmPujSXS/oHheUZAH4FXRWwhWyRNaCsr7
5c+ZRJgwVpZj3kgtIkdSfhbBz4nMFypgG7/lWvAX2UIuhBRPMVNHmKjnl7eTbjII/u/1PUJbdMlP
iz17Wxx8lYgUZ+ZSi1ajH+8sVYzKhzhgW0lnJmtY1x0wJtoMw0Qh2hblDkXl3EWtomJchm61UlRB
qmeEGrKuje5iHGHo6GjlKfyz3zsl0BGAzSaH9SKqhEqpNfgp6W9ddjLUnKgzIJN6pDs/4FD8Ej6o
JZiv0+FYJX0bALpFtRvvktcO+KIyMAmdZTl9uTBMI9b+LhT68Pxr3Fls2KX5Ygy9Kv6yVPEsFGJ3
n5VTgFYfIk9ehvN5xpcxmQnkQguHPQAkK5HaOm7TWZ7h7hP9kd/FyDY1oOvynYQyxuUxZhGALZHe
KVBwAUdu8rwtqY47Q6xLgeSHHhtdFQvCmnmUfMt0gSZ9btEtV6vjP+G5P4HxgS9npnkETEfBEYew
qsUJnQbRvk9ZedGw2MGQftN1AeUctv89URu7symUa6PisR9RRbw922tzFi0C6q4J4rPBVA232u9+
QdRmhH2Vo8LLxDZfO6DggYE0g65mn1QmBHXOEdKOHZqYuSZrqpxHKZ73MhkoCOJR2waNdGo2No6t
gwxk5z1rexFDBXPoX9AOa6anDMvMYWiPrQUGhD4lJZrt+Iv1r8GniQDePnOhrzCOKl5619RkfYHs
IxeqU36dmMZQNeZVL30uBd6BO4/8nBJJxbrH0kk4vKEOptIS8P8XwXpiDivW2NR6Dcu2OhzRSLmq
7sULpfYYCzZmgG6VNCC8oImAEyLYWkNEVac/EkYL7YIyf2gTPPmbfKBs1lRpxbcKOXj6PwY8RfWU
wai8x2RbkowaETPvPJGsvaQcSfBQDpPu8JG8c1RFwq0kWp/s1r6ifmIQsWvBg3PHpJJu61AH1XfL
y2BvSBXERnZJHCz4YxBpMTYhk+sG+KUPvoRYlaOt0iQTkxmsuBjaj3WebNUaMqOlYpvhfxHAbCT2
RfqLPOSKAnmiryCairwTDzWLTv75JnEDKYVXGzB7RBgyutuamV1j3b2CreKOwkqwRDjAlq7rcgqu
BS+mDT/Q9cpKXcfEJRjU7eUKgA710YfBLDuvHBNPT7iMhlnLJ8ayspf62mkRoKwBwzpFOA0doy7U
UhY3KLsDbJ+nTU9Cp6+oYQYxLaQd9jznICVyRNJUgEhkmZh6AwrodIR2bL3zDufwS0hRGPURQORb
l69FlG9c/BiCPjWcuqNsFbnTO0YSEI+1elRpJNTlG/CLlYo2oLfGUds4nQClEyDosalFea+TS+5X
4v7/hUobBdNCldrtvFIoZzNcC9CNExTe8+fkZ3ttWIxuk+CiymnZMA04a0dPz+j6Y+O+UFGhZdpV
fPlZ6BdegbV+ZEnXZiuojivU+aa2qTKYExKAIn1aE7NGU0k5wfCfnhHoAPFwqbMownezklXiYyWr
2/eP5e+39lkN5IP0GbUc2hZT7uVwwKfWuEG+l0oFl3i8hqXsRVNKqwQdN7TDBTSCA29Xh+OxLiJ4
WIgA+mzhsrX90IbPP89mWpqGNrTrK+VzxBZJP24hyuDwMRCQhAdNtbKgCB0iON4vvcAK+LLaoesh
MA6X8vFLZrNMkWFsai8DFfW8sdaRsHDoLUhZFKK6tBCkb04SdqdRjva423jKPtYVwVmaVnf8WdXt
NfQmhPu8qgR5JkxPEF91mEhK2sXwnMTGYtxHRtUcnihFxN00rQ49D/xZPD8CtEPxPwtztZoj5GeP
hFhDVvA/oen432znWAP2itRFZxQd5l55C88CP94l1b+V06oGWd/8RQyZ/E5L66ycZ80yhGnMCvev
Ve1AZYsAi0E22+bS0N2/qwlwkrpN+z+vI497q8INwTWkqHPtFu0hNwSYyf07KTVAMSccvzpJS4t0
qIlEj4gOd7MaJsaWRlhW5Hkx62bXxF6c6wUDSO1OvqHAvrWQym5M4l0vquT4KlpNbqLtxa/iJD3b
0DfPXsbpOGAS5HoMA50hn65ZmGKDJz+DsULuMhoQBCOvH4T5SXUUwTbSgCOpgPWWiZKAEg6kaw+G
IwU12885XsJtpeNAKTRewFgDGkBEzX8yyLgjf6FqaOqXJsc7X7vXX3f4MLuBhSsNY56oHALCMl4V
yJn0zu5ob+vGwooJKmCq0LMMIV+p6VgiU6VcQXVkgSR6kdKWLKNjUDSO2KZTwu6h+zxulLS8TQP4
+/uhVAjR01v7dNJRIorwoijR/oGLd22JkQha+qyb2bSYWkSqQ+SRsVWvwHnExkismrmU/SKQI7aJ
TqrLZF2B+Ry2p1aqwi0mMGmR3CVVXepEyrOMRnfZltd3D2wLO9gR2rJcYsoo2B1w+D8PYFDOYTQn
YJgJRQz31Hq+bMuGJ4JuLSHfK+d6N0PmB6q9Dc6jPfuKVfOBP+6kI7cN7N3E9SHBJ7VDuXCT7OVH
YC0z6bmI9nRW1+Z+u+NgZjyc7M3dI1MSGY4aPH6MeI29g5hS7rJnPLvRfP511RGO6gPNy1jA0QJV
vn/0UF/noafNlPud+kT+TnSk670OFSuHixsWHt5DMk63N11I6jr3/c3bX7hgCyq46UgxUbeb/7iD
Ggx1+TV/BIz+juJirHhCComVVklrj4PWYcPM5FhyjRPx4GqZ7uOQ3pTKNxFWc4hXPPdiKGAjz3Mf
UN28j/ryWPJZJRJ3/5Lk5QWRv8osMDFmmSYff9KxJ2H/C4sWhyDG5iX+O4JjGyvEiKFKz568Omfk
S6i5qIAHQ1pXkukrbtrt9rk6ntNDUlLWqc+bp8aJtNFjhvidh7/EVfuwGKU1ab2XCGHmDF8Q8Ibk
gn2b0owGkEJvIJ4QRx2JGhIzHG2KJo2fxXDYRBIgveOivM4HeO31aZgsjfc3POM+P4GEGVPk2+tD
+3aipEYICJGrlGTpBTw+Rgq2Zy0uRRXy9QFMfFl/dqr3y/PR7MAZw4ke+BSiTjpq77UcD+ZUHt/o
r5IThMyU9uwH6hetHqkcb1df8JuG3eFWuB/9lUJmgXl7jsvAACLazrXb4+XU3+SQ+L/u+FQtCesX
+lLV/nJzuVzfIIqIIPkKYOSm+SA3uZ3KQbreWCRfTQhoW6Kc1zyjL/JR6mxsQNp61z/SuaYBdAn9
Qz1X4oWyhtGloor+1kkSUr8NCZ2B7PIF+oElyQPGbeVlDE/0iRzvYRDoBbCxiEUb4MtjJkmS6h4b
geGMTVWGy36Tg7N4fL4qZt07qp2wawuEmyr80U5b+4gPGjpoZjTgBWINokTAEQweDvByx+DQrLP7
TkQGJVR8uS8jR0OMfuukcO+lsAgwhYFQwILHZFOlPRIJwtHtf3q5FWMdHGhm8IrQSHgcxY2lqIdu
es91AyqcDdXd9lfjY9Xfj9Zf5Uu61SGXRRzwyxDjEu3Lnt2oJSp8clbrgiclH6n6IXCYcWor+/gW
xdbWP+LYsgOlqiwmSDhtTO5OHVtdZzrgMhWq+gmFbrxrbCTS88aitOeaPqXgXULJgWjqMcRFxKr2
Mn8UYFUjLHBLrHNBMD10+++EquB6qAV+fEvUTWxUjvyqdboQkjCQAlSkkLwfljDXhVd6YrNvPFof
qJo94bmgfhKX6wolRW2ezoUU4Be3x/WiYKiWvEHkJHH2yw3yS6RBGwBfHIoVk2RtkyrZGHwSpjah
SlTJeBHM57pEUnYoa5Q4zTPfPY55tQZ0Qs/z3Uef0RnEB2heoWugWNUwf5Jx+ihciCxgUeIkVpyk
a6H/RqOxUfeTRgG80j8X5zeFobbEEOO+hGUqgCNkIQkCBR+awFK0qP1Fgj8+pazgEgU6KQ+PKM+V
nNrkB280dL0dPBb4nyDZun61IG7nxz46tryJmOtitDVboKADwHvMdfhPXhHA+2HHZOSwh608clrh
27cChwROmvp8kTGMk/PXaQrA2cAEfFEBeDCks30vcYvTesb7icGR9PmjlGamYm7tjSoynvfMiTgY
4eRlt9zReML0Ey9rARUfPTKHQT1y5QyCC9rtcut0dukTJDOXlN2hxk9nSdoryLjQ2/0UPB3BsLym
032qQZQGQuvUbpPvrB3I2shODi8djMcptvmwRQ4T25VWHIgicrDPwe5HVEy6I1gTB6e27eiuIfuy
T7/raNKZt8GjeiEgGXwsTvRw9qcRI8XuPTO7qjowfLSEZR32jQQy11HAolL9v+OB2vvVI28M9g5Q
Jf+E3z9p5mhqd4XEU6GaTS+srdsER+oVzOUcBsKWPYOyccCdRkqicS4QAmwm24Qlx6Do8QaBoQSk
+S+g2lJuDYfUSUZhrOJpEXiI4tq/q3ypx2azl9mgpSZzKKysFsyqBdjBqT2aAUx+dvK3VLsRZPE6
V/7RWJEkbliJz2suDnqHOhySLJQEu+V38UJSgdCr+5D4OTZAEwi+FT1t88B9tIXDQLHFMnQJOLd8
amCnOso5CctFtxiIozoJ/cyL+OQ9J26+MLFgvizEWLv8yagQJH1m6T94vktq8bAVV2fgviS8EUdd
fCeqh3ensVnOcZJpkHwNGd+d/eyT6MswQHJXHSI+xPT8HxTzmt9LL9/Ld4WpvmJzO2vxNOKY/VWx
/GuUpOkxS9K/s7nMaLl0EkjEeN1PcJAz7nNheXWcejP+ZHG4ZeyLJz9bYiLPc6DKjV86Ody6xu3O
CW4Rgc/US6rC8mOqStDUgMNk2ur+PU49mHfUAWp1F6aI0RTklPA6NKadoZkzt+mAtdhUMJyjkqu/
jLQZATbezuH4JdUih/8ex6PJ5UfA9ynSmpdgY5/9es7oRtBjrEWXok/znvEtrpI5Z1UciLrt2N6Q
FUpRXV9OGvBKGqhG+Qog+wOMCD99BIe6sCwwS5rpGkbXU51xiGeFZrBJVHvjS1lMZrGPFj1jI6vB
tbpmhRogeV1kjPGFf1OauxJ4SHbyaQNl88EFZnjQcHLl6rxe5E2IoGHng3AM0VH6ktm1FJySsNBU
vighP8F/VsWHcKQlWx5+yNwYWVMUkZV61awxTDgM1/B8ZfhrCPbqzDDU278P5Eu1oQCaEBvUW+cZ
d0RwGyyrWuph/5jH2gmOjXQ3SbsmE7QE+2kfg8xXmjAQBNOCHOBdOINHMWuaHjsfddk35IXxEue5
x/tCueJbLhLMcbspYq/7BrFll1CAFLjpgp5rwYfK/OQFbkqqhy2TsoXuRZv8zdCW+1kuayDBeQ8S
SyP6YnAwcvMK/xfHIPP+UiF3/FU9juboiIZBnv7dUfSs3w4LcbTeT6vDDhT8xv56uEQNB5RXSr6r
Z6TDx6HypWo4aaHe5zyk29DBVNfCwxm1/6N1mvoOUZGez+v4pG1vHMgLWKm6a5oFEiMLeuaYVCMg
p2AyTIRqnniVyIOfplOAKOf4D7wu14PhC8KquuYNwrEeRkfv2PjXMMrD9qkDmeRXTIlqS/rblubs
gB4di+qHHMLkL1uP0an9kJGeyQnmvp/J2ovcDo8+AAMz5bn5r/a6behg5rEKY53JAqmQifrrxpfO
8h94+k2fwEL02OEciBIxMsi75vPtr4YCX5odZRptEnVx91pjss7H2ehQ8MSOIUtW4cxri4qg/XmQ
wHcN9Y+XVneXxJHY5HryiwhThTvmcaoBKkNm67JlS4J9HgX/B29Xh0cXOPfDm7tXG1quV7OTHpXR
UrTZ1/jg96QnfSV/62VxU3lGz7tzldVFGZ0N+Vv2OgBeFwRlWMQ0sm5UzWlUPiKyzDPh/vIvkStz
/J/tP7y5C4wLoSwVaCnJflRHjpIW142RqHfPclObZBvvrcxH6BCCtIyEkPudpW2ja0n8C/M076M5
bJHotJga1L8kOfv5zOghPX+5SaWSLFFgCh1uZyTw5G6f2fhV/MZAvWfyNX2OjYL4QQfjSYmboSc8
AAoeQ6EXyu9cgekD6ASUhII/cu7ek/vSdbddSFGddkq6jeN3VAQmJvgxCLcqbwNH10mg38jxNa9y
ONRReWdM+6sKWBn6OWxpKVfLYbnHpw0/EN8rYD0Ku8GUuV5BesCDRAc63kJtRlw6WD3DYdqhHLg+
dUg1784xPjdWWsB+os8v2QGdNJ5odWlp9wHN75NME3k5OOTFjfcVBIh66O8FhSJazmWvCKEYfpWB
/DpZn2KOJyuWZxI7vag+rabK4R7q7dzdogrx1dQ+5EnXeCj+aEQ/pZlwO9Jw7wuDrB6PXcCVm5qJ
vEGSevHvGTpCwo6OM2Xz64DnPPPRXEcSjEbMfvv8tdQ8gEbHiaH1eh8Q/qFjaR4JnM95Gj3NbPEC
bJ6GzNdiKhKspVy6+qZrN5+xc7w4gNaSwn29Le7wtUy+HtDnD6BCgb8NNvx6Ca3DFLA5g5sEaG7h
1D+e2/9v8/A93D8KwMpvGBxEGUne6eXULjMyPnQuHKtltNsHAgxvYuXcpJPgC/pEPQLMhMeGHCry
bDVVLYWwQCHv957Jg6Fb9NRwdXMtCxTz/sFpocY/R1sytIul6L/1J5HmBssygExV69Vj6MtrG/r0
1LdUJwpifoUHdEEyJ7JIT7Kuo8qLJ3ugqVYXZ8wq47jXGcZUbF8ChSG/wOLRpbFUaPqjARQy6wUu
d/c4ZaJ364xin3HFqTwAPi/XlG8k2nQaMbHT2UCXk+Gxs/h4891FMhI82/HMGBdMVJ9q+k+MIoXa
lWJndlJ7W/8CrvYU9Z6GcfUPBytXdjbbva7laGsbej8OHEh690/0t0pzqZJKLyMP8yxOSuvZg0xX
NNlSfotAK7PRgQT1bY8yL6NBjfbmFm5+53TXpL8Fd+RXgCwZ6UM1LeUlHz5Jz+3nShx4uYodEdWm
nXPHGcWXpc/5VBRWrlQI2Rp2JN1Rk4zkHWqWeVY5xAMAfyxiu6zZTm31L9e9MzGZ6fHgBqeMhsKk
C//SHmpOta7bLsuGV8m0949o/k2VLhTAbGPy4Q6PGTf9f9u2a1hh1Dm4JQQDGqLq7At7UoxAImZL
5Nr3u6oy/+pLAQiWEtsmn8QFd5m7DzQ4ceAegW/m4sQPgTDSX5ZwMCrJ/0R+ZB5C9sPGF/Tsnn9z
YE7EWM+Yz3gePW2ChxId28d5VyWUpkgJIPRVjYuKxQ36VkrvgcV7H2h+A5KHJV/gP3NI7kjzic4O
7J/9xGOhTWFARFdHEMErK6Hn4W0v6kHgC+i+CVlIl9Vah4NxOmKlDVPngAHXHRk+09OaErSegfbZ
4WMLWgPQfNj0rfPosEOee5iF9MoSN8f3Gevz1/TLXQ75zU7M89mv8eg2/eSwxc8lFK2M72OK1Rb9
BgTlFK9Sp+xPUzVlcjPFkFK/mpTxOV8dnS6yQklC0H4nt6s+kqU1OK6eDEDHXn9TOto+w3fmU690
c59Ohos+3AP0eKtUU8uS9L9jrscYjQ8FuQU2REizq0EBlhh/D9dj8jLjrN4BzQEUAw9a0bgN4zxp
xymrCQzyfsyzOUkzg2H6gMmW7aY+Itwv0wFlPY+dv29UxriacV7Roa5x/9cF7EGetnvniK+U4FOG
XrYHGt2rC0Txn41o2TVDEHcPHrDjRQ4ZS6N0CsAPxWKsSy3XW3NxYcQaI9j9LoZxm5Up1hYiTuV4
E/gZeDQEHkR99BgrAMwFi853C552psEj0l5DInUwPST1X/j2wkaG1UujUkm7+tfUBaffmcnv2UNW
9K17arl2bKv6K8GpLTjo4p7BgcBxxcyqMPkR77gjTZjtuIE3J4iITTTHgeGD4CaYOU1QEJNurXsL
Mr9cQvS6n29qX/dvqNIc4i8BdHA3aylnVO/6cJH0ef+ab7JNdJ0ahKSjiljEFNqDPXpAEKwmZRWG
0G+IenMF+l94vFS+vJ82WQecLCu4JjLcacdtMy3yzjCmXneAqL9fHmLbL8DnvISCf53tJdHQ14/M
N0D0k+1uuE1cDYy0IIkOXRd4fiakh0crREjjbHZud1Sh0gNR8tlIp1B5hR8qQrqvjyLQM2cIYcTp
3BeCD0wz8MH41jcHeSLPNY8ni/Ia/wjEaf6ibNMlCvCoEPnqbtLvPZko5fN0YwKkzPlIzaTGLi4c
RgnssEGlayN6IC82ZQttghJhLmvlJwUsGIaoE9q3cx7sgb1wRmR/xQbcBac2dvlZG8b0aIjr6kYx
4Xz1/4Dq/pKbXLKpITsR0hkHKRC35aY/6EHcEtayv+FovvgqSL6b/6uY18MXQY7RN0HZ7jaAakf5
Yvl/bUd2wx4XEbnibR7ZIRVKRiqwCY/7gOYFIGv4+j0/L5e5RMDwhLaLg692oreEhIKh2hxPU051
18eiI6RlsYqhXbUT8kWiDtelU4L5Wfas5ETZVzAkATqqKVvNfxfup7Hk+71fK9okxLoU+qGd0yy8
bFXXW1WSPDv/CS+ia0OMBAI6ELLy8pgvgtgNuIWxEUPNa5IESYwznzlPplZY4DdQ3MRND/Meye+g
36w02QeINPz5KL80FjUUEnKEtNOCJZrsRlcaRNC4iMD60d35oaxDpWbhcv8Oury86+x+aAds1M1B
dvo4IKRP9GHPNY7HYezBsVyRGS6+GXyw9E147+pZbCyzUmOUBWUd0UQkRCCFoULQUcbbtRUtqk+w
dFf2L5iURZ/6DMaUeIwK9z76SzYmTt4JveDEgmhHg0bJTBRvBgbZrQNpIq/jGOuku0+gl/2Gv/Dl
AGzzaQniAM8fcYLP7gCM84FNZifXWVUunWqiCWMg4sRkJr0as2zdHHxIvoQ322t+dNEYKk5dbVST
j1jnWKp+U8uPvWxMK8MW96kd0VLRzLv97ii7K3IzxpQfYZjy+pO/IYIR9LnX8eGKM9oeQgMlEenx
JhkbpZWvj7owsFkxPfp4v3Otje0HVInulKgbHmXU7I3Jp62OQY/h6yTVzeoq68GLN/A8oe8T6Rz5
IJmYvhQ45OfF8/glNb46gAcjyDb8ghQyngTvC2KXq7DTesPshpdbkr5pfpGzVUltgWZiZDJvU+RX
lK2dzQMcwvqYl4v29KCu7tpFPUUSUwr+17osmRlOPr2zOWXCGWobAmqmNzdho7IjEa4QBRcIg/Vg
1g92Zaza+HOkrQ88X1gPMrE1/NKC8kdtd+L24ArQA+r9RnljTRpitVsegklnOH57NPjZe/vc/iTg
U513oyCA7s3aWn1U0oD3pLKeXM/uOZ7qkNSvMQ4vMPgJu4iH9rcVa9WVZ0tEU8TWioEAzo44JjH+
kiuf84jsrVNzw7qYwBUFz5PJXNG6yLvK/a60AqGd4aJ4hM9u1193+YrRPWEEo0a7QLwGZX5WSvK9
xNkvrHwxcSnFhrHGa1Tl94DNidk/hDQ5MC9+oevVX7v3HgvZ/IvdxHpYYfwMRjSvd+4ejE7hhJXm
qyD0LgHJIQ1aNYPRPC/2Wr/dNoBzs8BrNwTgqxzbhZ/WC+gkFSZ+s/IkUPY2B14zHbyzfj/oGL74
FdAVo0ewjDi3QSO0xuW3+sAsqAf31QDGxSa4UvxVlKUeteydmA1iFa9KE85TKj0xtCtgykHMj6ot
XMHvcAw5MDGbNtMsTkV96ychhkm12ITx2L3xz0zv2j4S3tlGB8bi+UimBnK2H41keKbT6vbhtdn3
sZQztrG3lZsBZ4RTAW29nD/FnoSNPjCLk2CSPP9zLvZSpwyBpvf0EjWa/ZqKRdHthhFh7XCNqlwZ
PCTlaqOig5GlsJ1enMqDyRFUj5GpOlS3XYRI5owSaS1PSK7K68OlGEsSNK5zZrk+RUby5TdptLrW
FrMFfw3URjPiAhiODWMXFMxxcEbxDbfLU8HlotEdjCNwkrMhRPyE/uUpxw4/uCEl4O06lteKGVYz
7WmPrbWj40Q4bmWPm4xLY0i2B4a4VGpW8LLwcU7d8x7kiQ+ZZfUmEXGaklVfoWZmSEFg3PUhLiUz
8xSMGeWAUIoJhuQAC7f+kClwIKaM4jGkdo/1Q/XWoJyEeNnuCjNWqTXmt+Bau7aU5RfbASuy5x4d
5FMYGbRhOTCNupajdrChShY1lzKd8VlmBOAYdKTOGzULqjJUPRqTnVVBxoExuuZ80Gh5egGPr6+9
5OLKsZXZlo0HcMc9DIKdLMMs2yhCRoVbnaRMnnZ+kQjUIk/y2ROyWDMb/cki+sidU2Y53OGbPYYg
z19DvO0DPsDLpuCWBqGyJ/LKBhVdvZfoTzgT0nCRb6SIHkro3jXILjFpZTHP0MXcOSlFWLuXUzz5
zgeMH5rA7MibTgmN9/q/KDwyZO6v5cWK5RQjSCZgYATw5Zp/RyDMNGB0ZmMIMClLku2ZrCg3Ae7K
PYvM562XtfthYRrJP2AvJW8Heg/DT4JHLKBwWKX+AgQBn8c6xbaAaAEDYpkBUcc1jf97r9eZWseG
ajou57OAHhvaVw+I1RYLZVXmo0IQjYx8bThSvFnXAIjVZ6loMlpo1KGGmF9CcXJ9IrYOvLwS4C8d
Il6KFkmQgP7lEsIbfygBQTiAG6YXD0hTNUfQoFBQGaIGs3ol8/bS6bZY3GM1fFrIhQ0opVdzSdYh
BbOrsoz0BTLUcpzmM3jdSnbi3q8fmje+cC1nRqCKQD7q37G2TwWcYUWnDHXy5gN5G7+KJg3nFYwC
K9+PJ/GVhdDe/zBH741HWM3t7D1G2jq+QCEGiBKqN6sXEc3a2TCCN/8ALEiUimxYNnW9ncFX+H9+
fl6VarD2RsT7LP58i/+zkA7zPGH9Cu3TFRmImt/jOo4f+ZMhHh/UfZuXt5YA+fnT5xTniIMjPl64
O+DSOYcBWvwHDwg7hRMaoIXByFmSC1ARim4CX/gnmlXrOi5brnt46d7oSlR80W5wJsqPE66gVmHk
0jbSCEBW2Kc4o/8NeBnH5XdtQbwtjJYdzoKNAbDWFZL0e41auQ3LM9v9QffLY7ILgHJn5nM1Mb+D
U6v/FvbohAhjO7Jmyxf3OzkpXmTZZ9mAV4NuYe6LCZ+3rU8i79126Z+WONJ8xh7Hb5o99QOzdy+J
wFo1To+blNSJWgGYX3mX2JydBMJuOiV3fxRa+Q9ZMJd7KFqmavtz+CHvS9c2ypjQW2BnfAZJ71if
PDiZ0peGC0QKPBRN3f9xOXfrA6lMGm3K6dDlX9ZCXs2TfpDlakIK2Zd5J4kEJAMsarwyyO4VK7BY
GJNAKq0iuAL3INXSzVncyKXYi7zix7TN7HXSWKgs5ZBpn2VAbUzdRIyImOu5GX9nYmj/SjLQURA2
9+6dHzJC+z67tNroCtoFSIJnBun8rfIOIvyRrupL9iCsoh0O317pFlWTOFSYy+czqlMoZ+fi+rAy
9VGA+PjgOFoXQKOO1h+RRauRHM16F4s4wNaI0uVJNPiSZj8eF6JjrYOvpn9fOU68u57DKQi50lgx
cm373KF3Nssl6uuzX9oZi6octDQArks53l0A9KgW3rn08JfyXdqN20wTGfoB1vZxCzAaGdxHuv1S
FDL8rWFBdrWv9h4mbMQoLnoj0Kt3nEnibVqQVVxnjBSTFKTJK4/FcSIHsVCeRoGZH4RHKQ0DVCa8
ef7NGEqZJtD9DvDErCUoLTE+Z/NT1td3rrOqWzL7fVXwywkyrhd7x9CwUHD/liV+uK+tsh22vlMG
OT7C9s0+hg+8cYN9YZPIgewQjiLJ8a4q+9Q7WWnlt+f1wCSGrfnQ9raxoSnfDFnaqN1X1R6Lp+DL
gBkqDvL7G8HX408TRkoAnAUO/AqIwJQzaU604eKG0I0/Rk4dQH0B7YMxm/Ar3sptS8/05aqvwFjf
Vvc+/LGz2NDiJ4ocqjjRigG6s6Dv4sfdNdTFy6UmRS2J8NEZYOKTpAoVeQJ3ynQkBXgjzRmpUiV4
SpsygJsZMXKoJrJ+wSKNWGs6Bmy9DcLGvBj8r1mkXTyVpGKfyqM06CN/zv1TsJEPem6RL49lA/fn
mpmGi9MI8eupmncNlexl2Ve5jtW+31OOzarStjsBZ/VHqRL+DCjBFykP1Wydc8ZoPlUUH4bTZk4p
ZT8RJR9DhFK0DcOXhcFikcWNrLaJ0RXN+3QoVn9zaV0axoNDVYnxB8b8llk+bdk26yUkBurKNuH1
/CetMpVAhAWbdTexIdHt1Lc2jm3QzIL5+BMdw6l9iHm3v8vqH8lI5QT2IPwhGji70iYgPYhaUyr0
ur1Eg+FVe4CksTjOTA99bdSnZa8+MfqqweQ37DFUg7sIpnUFe+rtkw5PpgbdVTriRQGgcVMJGHPE
w74yFW985inpN1J83e3eOHb9SKbpy4OCnBCde/4i0N1go0paQfT8CeePWEn+0ZwEkgAP/ot4VAYu
wDi3q28NS7qGYK4duxEHeCSAsdkdRn79dlDati2/Rj5QX4sD9+48OGTjM5Z7w7lIFCIeP2fbSFX+
HjM66UgmPXAwwReO/WrpziI3sbRFPHAI492uwkofC1aPtwRBpUG+nI9STYqavYmaDXjI01MIKPtl
kmmRS/80sORyrKODJ67tX965qlGyTXi32/K96jkmum1pB8bKQ40wKNdVTpnAzLm1Ogb7VNXelJ63
Rii8vlNtMlRqvmuMywX08QNzihF95/hlJAMtc99dpznM0kFJVPIebyvMaFZkIJOFDvoagpfA/6Nw
0LQoY3kdiqZsq2qqyzzEbXPG/2ZvnAevN4RJIdj4mUnPlMBe7oVvmNUQT0tADZ/yXYmfut6fV0Jg
EUcui3rELzeGYGvx3/sLeMqBsMb6wnuQVa3DGOQLQtIGxB8DYZ43mhjkQWMMzuHHRvrVbzccbSjm
idPutbcBBGdxr8jSE0vKEfQ5XteVnbU/Z7RcullHwmGkw0ur+DPimr9DGf9G+fkVdDiFKgGhNxlr
5CaFmZ65jDOEqCCvDOUu6nw9qrHCEI7v3RladEE/A6WeoljM+M61NafrEoWZ/6f6LU/dm1C9L4Lo
O7mPKXQe/Yp7AtyDeu29zV1K2F9WLQlNbb1Q3FdXFBBg4kj6nMjEqATX77BlHw6pi7FoZRt9kzkX
MAeacmrFBz+fpGQ3tR9028h5bhpo050v6JX2iLDEIbBz2kp6t9M75KKNg8hiKhbByCFuxWuxG/RI
I0YwvKOoX4eecJZn1aw52gotCNOYHurLu0Zt1NKq4DXv/5ECr4ZlQMTqwdhmEjcH0+ca3SUqhM3f
EoiN8iNCYKl37j9Wc83H34LGonf8loVWYeZf4uzoVTa2zNqGtF0++IQsfqIszO2dQ6m/GjWVez/r
nhFmuoqMCH01R7zAUNyy1gzfyZqOSV5p4aOA8dJIxE427BSQMs14EmvgBV7iCMzU7tDjhlBVJZjT
1Y0jT+gT2Y/6KQx18/xhUPGWvJADpin8p5YCtSCnz4iH+/BLQXvAC++RcszNLgvWSrwo7bykcrpY
Xy1SMYXCEqioKl4ZJunYeuoNM/QtbTc0QR732DT8+w6v2n2QwvwmMtIxViFoORhUIlNiQcgN1cVr
oueMn1868g4S5+b+hNFefYwkqK5IrBdy5BZg50NfHfWv0J6gxVAZvYyZWqOxcxXC55yTSdgaCiwI
1+uL4RDiMk/fTX65EYFtMg9N8VN92tFqvxUgnFPbkgDLjYNIgYIZK3NBFWZTkV2axZT+CCJ1Zul6
oiO47h5wNuZJCUVczqC58NwQb07OX0oZ4Ao3nIe6PNkiJlHOC5xCRrXKLu5ymoexbzgIH2E6CQpH
FW0nKeKZtwww0jeDW6jCdp3MMtWAnUGJZHvrYMeqkw7tP4QQPe7/+df3YeCeRyfJbUR7IyMLjKi6
u8QuvSdSq7IXg3KHAxfIwSldfsARomrdXDm9dCBmuCV29Hc7OEEAm0JiKGFq7Fe0c6bycCkx1lIV
P3fjBvhEJfvMCc1ZUSbAgPcQvtrr9+hZh9DQH+PE8eNvnqCedwTGKLcFKhWmA5PeLVSL9yIHP1QP
ok5VXHJkqBkZ9Dj8bsa/5FZWXlJyI7YhfDedSkRgOtM/hlJBjtIhkTQwAit0/aCyQFHKEU9H6rFS
LD5xZXfW7A0N9rLBVZzEvoo7TNGquCGa+Lqd7IuVFt+R/xhPAThNSltaKTfMJuvMOIyrfSpIGlq8
xkWbGqJhc2KV8G0Pu2HUQtznxj3gcBuiPg9ZIeOZrIDrsGJFu72Sd+/k4li4ZeCIMAZMocllcL+e
cmcxVMW1xXoCOQ5bnXZec4t2P0qWOQV27pcPmswok5yvh/m6k18JDPH9+4Az1F1eTEoZlyz8UxYA
38yh1NqIbKzDp6IS1Rhx5e3jQTCswNuNf/ViuaEDcvSImFJJ4s7KMZavy/bsv1OLAqQBhwGzph+0
NNI2lvSC0j53SqcVC0WE+rnaFo9xncLBYsIdt23S8e+6txqAK9FhBmYmmNX1WXeTPK/FQWaAkx0A
hkMiZ2v/D17ebg58MUWVnrmeezJWrVlBS7elSjnsXVxdkzA25y3yzQcCGVZBI5kgcqNpyms/9O8x
7Q37IlnZzmFw9NCICUDNWCfmLlsilw9I59pZhsdIGzUkF1KNoQQeLlPZfXQk+Uo5lnLU/9pnEisC
rrqol0sCwPMiR+nk+gB6WeO4APIHi1zcQwLnEsZv2OzQjY3oifCSOxWrynPwLvU6L133xEd4VXoO
rGrQYOeQrt8u8bhUMcNbu4GXRQ46L6DJ/MhfvFfQMK3cmRGCsZda5cOD+McAZqnhvXxiQl0L++G8
Uo1rWsPMoFxTGMLgfs+w3lSiMRVdr2TmraX7tlP/n85hitp6tHjSPAgZEH9OtmmpPJHe9B+vWht0
FfFy6BYMPl+HuPbL+Cg32A+lERTj4vsMGGlacNp15XtobZ3Jgr7BkdECRM1g5k/z7peM2L2W6mOx
mqgJEjqT5G9NdcVkVnwxiNdNNkc99yOrTgzw7/lhz4AAHxuzIzRAPkQvMHcrJT9CtDaHPEflIMTz
Xx8U+Jv6BPKs+hZ2FnhV7Eq7lOrK0JQj8bLVQiwxPo0o8yDzwVaMvUoQVAykqmHVnNVtRGGfnK4Q
tJyJBFYNI5gjuPD/XmdKky8qa5cczz321+VjNpj/RgcIA25rzmOqaRZ0KJsQoHOA/52PpUYX3T+J
g05voPwzSWlJktWJQIRCTcaTjDWUiDMDa4eATlWqQlySb3rINH61sEl+ZeIdNhW/X9Tf1FiMFh16
knYvSG5NXjwNJMyCzlyo/nHh/VmkO88Gr/dhuY0u3XMXJxNKh6ZH+hUUelCWLYWJnnjSF5JpkDYw
3gzfBQrxYRJ3gFNMIyoPKncXnMlZdvz1Kco8k17+m/AFLEPEobS16W1M+FwaztiUPqTwb/W3pUQ9
kqpvJZbRTeTsyV78Q764ovbVkKXlzLEXGN4tPej61SDVa2/P8AArRonfaqnbQIn9AEyCfTq9N0Vy
7fmVLJ3mLEZa5GeLg9haAz824IUJhKOUSTnMLNej1qVtyxjZ6M/rHjIYOVgRxl+Mwb3Go8z8dx/i
A0w2XKZ3omA6hPycDcwgk27sclK5khhy1geoy/N/ecwiTP93CrG20N+Cd+hN1uU03B0WCBfDOFS+
gd8N5xo7+VNLgJR1Dq88saDgncCSj+xDIvzkCumCiJtvgHDsMMKaNk6VtHieBDczCYLFUfPzogXn
pNyH+e3wLEkHjsxsa1wtY0HGD2c7e8dKLtJsDjiA7UfKhNs3agstoJvvyaCzbl6ys20tDLEaxt6c
DVJ/Ou5WOVk7NSTx5umvBbsF544R3YsINkBiQ7IVSPXgpjuw9KIvRdQloyIM7yJdiJ1G3pxszmCt
En70yj1gcvgNcgCXM3iKULl6IuCtf3bkSZdH6pHCU+YTD91zFaHLEqXfrPsMOFPyRC813MrOwaWK
CTQ66mM6qat7wKASrovjtJ0QQ3KHrWz2pjA5duxp1BAUYkQDvKUuAZsGFX9OBYUEV0qJDXNRFR+B
TuMpf6tCk8NCAE7F+g01EvudVeZExnVz0yPXmilZT+N0fbFdruWarhuXyOnN/OJnCNQAEN8L7kQc
oTlsdxSHdZYfeZnQssGjpiwmOWzyZpg7i98h+iH7WT6sIrvSdA8GoT0m3lC1epKkv0PJmiNbNoXx
R+ypWOKROx4dDrw28koHWSrm1fVZL/f4lkOzP0zZsXDhupiVLnpqEKvdB010ZY4lS3yvgaHkd/js
RSrUUFdqHWlajJBZ16EyJsP9xOJDC14vvJATJ7jJs/ImcUk2UqVbEJCZjE7MLf8ZxESiyqsVxl2i
bHQxyvVbEud7eVwyex2uvAzHdO3gE93X+R1HAUXnZpeSr8MSaX6A8SSjajW0PcHhj2SRBZW1jlcP
t9BAB9IqrdhuF3CP8xkKRXU8jrWzm5kSQ4iApjV66Wb6rCbYFvbgVaYiZjFp0CPMn4l9bPz3u5OM
0fco1Wnf1fiQudxH5wK8nria2Ly/n5qNVHjusBK1Co9Cgov82ZiLgKc/GHyTqSG+xCd4iCtjxUvv
3GKwjvBzaSFAkb9zye+2xkFv/ckCzThFkTTeoSkvIQEmpCHanEvVu22HfEtvWMQDvRn9jmWLfVN7
JHYnfzJyPxn8nI05BXxs9hGHUyw5t5CFZ6jxdHu62gUuXzfKQGGTYSRRHUx6aT8o/pbmpZd7t5Mm
n9WEoCDlVYjBk7+aJOWYcTfcDmG7Xtu5rVFOv8VaoDEZw9dd5KR/hwrr+ueVNQhnikOERfGQk2fl
aPpe87eDxFTq8IC/zVVQcVHMshnFkr7oqicMib832lAGypvZFN/Vh30ojYu0niEdreNdIdJaYbXt
ydPNW9SxJ5FDyXMtmc22EhkHvXzV8vTrKs417tZs4xL+MVq5mZ1E6JXdD7XTJkTeCiWl4K05nmIX
D01bBN6v0IcSdZlxapOjvvoKqfE8e140OzJxIBYMSbEd/ZGJxZMTdm82fSewB9xqxiwQsMwhfHwp
ZO7iyvF6aLrn7T/nXnsPyCXpOsb1yE9Z3WbFKQBvr2Pk4PM750CBY/uy/zF1+uo8VVmyL4RzjSJU
Bw09+p6xTt1LIAKLPLLEBZfVEN3n1uSMj/dpBMAFlWh5frAT/vtVf0oyLKqE37DMsx/2XHjJenqe
Dy3I5dxeyKLLGEu45N9suP0a9PtjCEkfg7nbLMnlpY4qMfrLxbBIhz5paT1SwgeBRbuHiC/daJzm
S8N6QyJaYTyhtCJ4OUWmYc8SCQmgHvKGjxgbqjBFpi1H7G+OSR8DE4afJmDixpFpC/g5douXxOLh
TzJAKpWbw2IxHfKtRl0I23a7dSS56SbLo5LPm4By7d5ZTiIKXG2v79mRvGJzYiTZZl7GJjDvH+lO
q/snZHqFP8ITcDOTEzPvK+MoG2ZvrUh+XZoPXb0UcIHEjUI/Z2S/VTYbOzaBcS9sQiXBnkU8DfIR
OjhJ6BtSiMXD2g93nh1tkt3e9EjKKNjN2e9v6ZAptKuMaeYPV5QoIkWAebleZjQmj0Yc/E+dQVaw
atsgyV6YOD+BopqYrZKe6kXka7y06pPzi8zs068XOA9HYWlzrjtr0oO7LRmB9Y7CuJWFYTUStzKE
JtVKHuqo1uhNvxWJ1foKIU1b75R0Wa6kamWKKPO3XtZwYzxnxePIJNi1O/lq+R/sc9CZFSjr+K4D
ZOCnAdCRrrzcLuikBX4A3XDZBcG06Kfm6WKbmVxGu43QFn/kZQXlshP7io9FHJzaMApleoX4NCxs
BgnkL1OStREMk85Iged5O+wK6jFDVlXyFRZjfU5UxTR912vMmvr3SSzcbKNUyqKmQ01LEqdhne7M
p6AARaYnmOS0j9qL9Ju5o5+jdbJBqrNY/CZ+xbLA52g8apmGYmZlYDNUxdlUKHm3j2N0jyh9ok+j
KHMDhzya+Tx7PHi+FBBBeeqoB6wm79YP01URJjZNAgo97R7kQTur338ib+O++gaCx4ytGwMXjxuz
pOGnpCmcMk7CkxiM6rBdyuTNm2W+Q1XPtaJZIYtw4K29S+QmAaMrZ0XOSzKT7SucToDWeo9+DpxJ
kMA2Afgd05olx+Qj45ngBB4PQ03MhIlS+Yader9aR85Ok8e9S7zUjgO3vJt5eyiajoBQZFMv1sz4
5efK4UPcF2jKv4IPl9T7uG2VfSXoXdAkCTUFjql6fZKNGDDRN7U7iaAL8Z2p/GHlsRh97GR8KfHE
iAa8rSVGqL/wC/yeUI61b7pvzN44v18QTTLa7ZOEByERO54YDaUFySNGDqCTmRz1XjRt7wY6UtRZ
Gg2vQoOIHOh2JkB9rbBXq+QHM9MI+6YIzs4mWj50yp8oO064+O5maOsGe770VhFB1c7N7Qc5r+v7
P7veUPnAgVUoDloe+dWWbKQpBGGk9IAGl8J2TDVlEiWdzLwOtmT4npuusHJDPZr59axilk0YxArq
1UeH8UWwdwOmAe7uvmfLLQI8EcAp5UjDtpG25Gx2zLtEXe9A+umTSacEfPbSS3mIpTDnM2vKzokd
QxGoJzHpyZz4YFQjwKC07+QRZiyXdQzOul/AiFCS8LQ+VBMKGaxmVSPgwC0UxkNfdSvqvyXj5P1c
Uth9jWACwHpNXK+mqmVANp5MhUtGSLoigqvBb+1JANvo/+CSKsANlyRGGhmhuif6CBikFM8B8Pgg
/khgFozYkGpxxvugswkvUP+vbFno3I+G2irrBg0iYxj5nMQHNGGNyIRixxfKLloGDPYDz7cR5JeU
N/T4bYmVHdVOUkH93P0Xza3gd3xNHBptQyYBSq25cMp4MueYPkGxbPOat9rVvoSzo5qq73cK0v80
L+qSbZ55qRQxWyiGNFUPFB/O1p7DvhIiOkVnQW4umjd/hXRPgSDIasMkkvJO6mQQnvtEsRXyxTJU
6zyIEl2CWyMta63JHB87DfeDNwRzyFYjcO2r8GwRDQqKAPSoRhDqZA3sb+0XyWRy8Q3IqtQGA7aZ
1kUE0eOZTY21qW3uIJB3CTDVzi+s8aNMvR3Q4feI/V70r87lox4SyFzAyb9gNWz6cBJkhX6dWOtD
9ffT7I1quGXVkBWVKjM3RVYq7Q7Bt9HXXpMr3bW5ghpwcbKiQvvVq8VCS+E6UDfTzukWstS/Wx3S
LwNbFd4hBfAW/ItxjivlL5SOxKfKHzGHdRZLOi9QIEJl/LO7TSr2r5UUXebsW7ACOipaMptoRZt/
3JrlsHMczZswvRKdOaoN++uoyyNEJ8RWZkpNN9iOoMtYMkAecaFFCcc1Qj8lpOQ/tkQP1vTQ000o
58UbURsdrZBSkmKgijUUFKwUMjnxzyj8ABABNHn9pNWbOBFMAaGtr1xgbeov7PIqzjncplrT2v11
EqulqKA8Ztb+LJlnnKYinDJCeMqI6mfI0xwdc5IQ4uaKUPyH5eR8DGpSb8Qp4e98FPzKJ5sI5tVl
C3r1SmqDey7/2vlLP4mFS8zFCnNYuyxIFBFX0YJbvTglkVMxjDzEG8GlEZvVEny12e4V4TQObngQ
k8TAIJhp5kfynVsIpNnCl/evn6vEyPy+M93qI0s5TrvDt6Jkfii3G4ix0Ma2iKUqtAKXYPAYCZV1
XkaUV92czRBS9v2zhJs3bzlYP/NLSgjCyeXP0MmFgTbFcri19DpeL+QeankxLYFG9mnD4CQKOlmb
Wyo/DJ1Rt5k0LHP6Kfu7IwJIKPTcyrPOvNZt8XPibCbjAdvqIy79AicnlhbSFr5kFqL2+Qd34fwG
GHVO8N4lFCr9LL5MZ7VkVCcWfGLp39p5b+P0n2bZo025Q4ZhmCMZNui9nHBu2n6sDIDG2E1VYX8a
5c99vb7gdsB1WVcgegbkMs5Jq/BfytjvG9FEASNjdLacPIdnP9NVz4fT/Ea9o2Syv76DqHfb+S2H
1Q94+LVV0/IjUxzy5hCdJG8aaf+dibn0bM9In/Z8B4Ns9/Jb6iGArAjuAQ/Gs0HeUhvoKrnPs5aP
sC+G4CwChQn1jdhlA2vlcumX+msCX+l63lrU39u3Aq2tyhlm3aAtrMTgjhpJrfuTMOYhp9Rkm/+e
JbqD5AAuuYw36//mA+y3e6YEL9gHSOAvIXcANZdxPKu8M1iCpSWfgWNtuRo3NjpVY8N99Qt+KFUd
6bH6V06ea1VzxDhgpvN2kQKbdiEDq/A/xDg1f30DCwzzIA4ZHg1C9ewrhlt3EX6YUkQPLlPRtY1E
cj19VWapJ4Ce9PT2l8CN45zNNXcNiNcees7w1HQg/avM1/Z3ZIqZgjorxiMoJq9PEjpTl8LN5mrD
2YW2M4/K/fmZuypSILzMWj55QXO0JDpTn9jIb7ByaWqzjgFE0j/Z8YFBAjUzbizguxz6oNQ2Bdqz
fpEXr01msf6gNgZG7SLFpm9QCKmxoSb/LmK4kJSL5iXSWf5AVLKMeNwmoqvprA4OsvQtGSS+6k+L
TWtqiFUov3RvyLspAteOcVImj2KLnjpuBN5N2TWPSwxChfFK6A5VW1XbyG0r+0xwLgOXBnP5rUgl
RuXqgLNR31hA91E7PbmYJea+Sr5mOWknC5j7HcwJdJuaZCW92PEQqSR/fDg41CAu7YC5mLdF2Dhj
zUlEpZDdp3ArHTOaqcxfOm0ctQ/vF+Q4eAYV263f/wShJsPt2vpf42ThKOFA83WX/HhiqxgYy3a3
hGp2FKS5eMod6mlL4Rf9OoWFKeOWHEhCjnIEdQQ22q5mzjQvMQn8wr26fnzU7Szcyt9nG/QhF+zU
tYlIrRN61SKOGBT1pDzNWxnfr4+ECArG3tNfDBZozm6Zpry/JY5smlYcYzdQAgozguL32ispBCpJ
rKihyMOexk6pnqZnwW2VYy7A/oeNggwl+ct5O4CCMEUfg5jxzkqfhL9fLKHRO2DcD4iA2cXCKyL9
+clpZZ32pnVAJ6NSW4dRYP/bPLOs85P0dXr8fBf5GLJqftdGA7XBF/QbUWc7yYsmdJ73a+3sIyD3
Qp7Wn0Qh5rk718CnY3xtCcItM5QQvDjI9AfkfJwapZT+1jv5V/IDlrtqJ/8rO68vS+HA7S27GKJ0
XMvFzZdaFMBdo1suaInwF5gwwiZuKYiymFj9pTaZnqAD/8DZfSxYUhzvq28cOnc7mZ1iqNubYEny
NlahiHYsMtVbvzzn61TRBiIkUIQlU+i90no7P+rwm9g3bBNXrfOxduiWB+iWsSEukEjKxNo3wmlX
NzynIz5J+7fS9HnIGU1KtC+nC1s1ijhWOMl92JUnKd20R6hidZynGwyJHcGlso0YITuSy2uoDrdT
W/50n6KLF9q2+fT6wqivO3bncGPRah1NxAIIwfBgZ4YqBL1DwCnDFzVG20zsUNePQ+o39BPaXK45
oiMTSBdEwUq7fE3WUgBaQtMQrolOBG+yJm1hgO6mpXzNS7XSQg0LwOF8nsj/luOhShC4UxD+KAvM
z71NBeRpi8IloSiIpQB1DOYa2lvLBxxv+0AhXO7/GWn8bEzKVV9lm3C8WtndrbLA7WNfP+Wo9Z1a
v1AUBLLePfEujr8nTbiwKxBypnMuVAhBNCeBbShEDdAOWkWw+g4hlSC9ivqsuKA1bKTJUjLh58BL
ivM5dQUjwJO2pamP/uBP6vAFRHDsdltBGy3FurfMHbEOQ9nXmLl4oEdCVTVqdKZtDLt2IKISbSaL
0rOuPJF+hnXUrnR9uPRzpmx51xYw7hZKhHUgOgttd6qKcbaRRr1cI+6Znmz0usr53yX0nAX9yLmD
6fZ4U2YFxS4ZFA5+c+ZW8jCycFkz6Z2exTklD4gh0xLYBYaxrPBckueKtC+4meHuR/yNx7RD2QNu
IPaPT1mBtG0OwLtEiIwzXrxWbg+nvEkAK2/659+xtcDrfIMwtScQSxOqcMNhVUA2xvOyg5FLOMjJ
IMgKORZPu++mzguB08qMVvQiPUNnU2rqY7sZWUDBhdVyYu4HS22UU6NBllX3O7y/OSekHUZ3WI/H
wktDRmvKy1vF5AAR7C6J1tueYITdzdhMynaNM6/TRhHuKP0f2XgFOQmsV+973RKQe160s25ZR5AH
XiVjL13+E8vz8sf84qLo5eLtUVBnVYClCW6nWuOC8H5GcLmVDE7izcZnrBeoX/uByciZhnXbAfm8
HDoDIyx6uGlG80uzJXj+IK2Cled3/rvIlnI9tyjMDYX3wzzrMX5oY6ccWDU4oFNcDiAtnnFa5xBG
X+gMh8DqQN2i8im37ripIBJ4b9uXHoAveZvtAr7goIIImYk34DPBdOONnDFQzT22ce4+2SgTutcR
N2ngS9bLrY1CL8mZ1GWh9XHDZrVO7zuKYPMmxEgCmA8uIoBfscRITAfmlFLfdaKg+bmvPruPCnBC
ZSa2Ss/OHE7F5fZ8jiu1VdfrRQovpY7ii1mYX2lY5PNhtMSE2VbXqFVt/s4hh3CvdDqWerg9GE80
veIlXfHX5mxs3W7A7cjrcCmhIO57EGgIdN2T/YoYQYytCICaieka/5MlG2qK7bIkn5ngkNsrjUYv
qjCMleA32PrkZhbdlQGmm6VlCeszFE4zPX4ui2AlNohkxb5GTJRxv8hRGMj1UEPk7TnacE+VBRmu
dK/ZIHE1cOytw83Z9lOzeEwTP50LSTTKFGSQmBd1KSvMeGpg3gZa39zawQyzbizL4fj9S3O1CCfs
D8Q6vizOIhzlwx/QpBTXta5Pao+L1AfThO5sJjifSobhS+5ivuIMDhmAdN5ZCm6K3X2fN+nZHeE/
Z4EB12O+9qYbJzzM87xveBFqfhsuY0erTn86JjcwA+f5pLC2LkQ5nRSjBUdM1lGArG52ZeS8jeHP
WowFDa2c4Ahn4ejsemZ5puMHLsV4BhvQxCYdda4qSW285A4cPFb/9yiMZDrRIa7YJqVbEnuzXh8Y
W+pMG+1K9ix/+9aF2k+HJ4fb7b0VCcGrhzLq0+OrDmUOijesQhW3Nmym/uZFohgIVMDLN6jkZhzW
PA7hUWxjMlWXs008U3JV9ZCBo3OhF4ZJB1thuB+VI2CGVNASMdzet9g08F72Hed4H1yVsP5H41ry
Cmx7nn0abV0F5I+twKSqCg66Rthmu3itnOQoP5uyCHhTbtgoNReG23nsND3zQtHIKyUWG80esjUG
GgJCv4kG882Ax0jkAbxNsLUTZZNNzXqi7cZygKuZz7cAXDh5+p+r1g3IJvvfAaDhvXK5I98iNfRT
9FEj2Am9vlbnC5BZUCe48zTAT+cPRxODH6lpWjN1HRx2K8A4DdqP9wWnianOnmluB0VjMgNH2tlQ
WVkYpQrSz/Ar5XsvFDeLbxJxZ7FbWEgq2SgaNp1A5hugupTcZnzfwco7EsD9Su9oq/PZNXks2s7Y
NjVxYWq5ma3s84IaInhtqevwCZ557m83zcj/r/WI3aJxzJGjeft7IdA7OKwxQDhmOD160ByL5lO3
mFgb0aNMCYRnR0+xfhC6pWjN2nawyjWjRzPbkcfQZD8az3kMLLQ2UNh2Zw+J12ElsF75BNiW++/7
TM2E+b/KlewQTr0XGVAOEDbPPaMiwVKPAG6SmQ2/sBeFoaMwkNYvA+oj6UTIdFrmSr0qKNRsflNT
AARbkNgRzJY0XBDqGWf2JN+qQ3xr3aO/EfsVw8Rwu4qfQ+q9yc0XqO6In8k1r7ka2GRLKh63/ZQM
42sOWQMUwv+pXGUHZ1U+8ctKQyN2oSf6WpA0ikQZklsKfrUelk2cNS6gaoTf/PO/nO2/8Ck7RYuR
j8ZEO1xAZac9poTxSQVfVDb2oZUqGmDJ4B4AadyEB73BIRqqruyOw3ZWlB+StXEY7l90rp5onA0I
FRuQyhlJ21E5i/XOKy8ZSs6OS5hDu53PxC+x8wYHuJGFMkPzL/T6ldia+eQWAdFNDJkAuh3aUpPW
mTKDiEKruwulrUPj8SIdXGym0WDIX56rM5aktjgHCBxlS7A4nEMMqhnqF3dBQL7Hh68Lvz+LlFw6
wFJC96fMyCfqlcaY3r3fblXymS9/iaHAAUbyG1lXYN9IzGsZMJA25Ded3E5EGs9BsHLe2PAP6K6w
h6UFNODAscV8YH6UaORCB607lxOkXbXPvh+vdTTWyaT7m6u9z51NqcO7/JW5KyGr5IXzSHo8KbUH
upVTG3dHDTBnoUv0YBBakmD0u00BmPuCBc9qkP3pigyhAp7r83c7t6RgcZQL2M5gTeD0pqiIr6D2
HYpGm34lX6/kj67p+X+NifHyDWwA8OTmNV442wMidfSkfcL/9ttz4aAPeYPp+pXYCAhgl4u7cnSn
/fp+izpsNAoSMxgZKnAwB3pOQtS5jL7TrdXWMnKT5GIUKj0Q5/U1TnhRo6TU50rpHjiAC3H4Tmp6
tV5lt7d5EOGRF2tEEVY8e7AiNtbwnuErY2co8iwPDGNohe2hW2znCc7WynTsEP7Emd5UXNoDMDKT
psKsoPnUvPEk1rT9rKb9wMTOtsNAPj0MRQML5p1Xis1uwDPWf8elZy+LVnaJ5SgEFun8ozukCbLB
CyIGvSYtZBXknA1Xrck83rs7lo1O4V/uBVL7BTslwQrj0sShw3AyYQB4fXtfwv75fk/aewAD2Pfj
GaAh3crUJzO1o/pWFB61XI32WLNnp7Q0P6mRGNYvAjd1w3ymIGwgHWmDzYEKsEvSrAsA4gPJ1Jp3
AMJwYOIgzJJYnSzUxzRpa/l4IshtrfM8dahtoFHU/exiTtAPvs7tnhU0vZY5yflnxx+S5K3K6R64
1UHli5uEHLjWQCacj8Cl66eYeUSYy86JE7+K8knkLXEz0NErGww7Uk7DgFP7ZbfX7Xax4aMBCapb
wyaABgCQ7BB/eHnLPN9tJUEBZ7joCD5a/yVHdJ442IEavKZvfYvW3ZNpXuzuCUDWPlPPZSS9MwKC
BhQTKClrFKRv5pmgXIRQo/TftFewFW7eUKTvkVFRQnySocfIwMMy0MyYwBwIFwLjdICtGZ4uhp0t
3hcvApBiUqzkq2/6czI/m2iybgqVZw8Bc3sN3KPDKKrZpbRNK1Tsy08AG+mX/1PnyGx54KLkyHOd
KPm38xJID9Pf+csFEK3heHRCIMFHY/HoRYCWBP9Kshb1kTgi1yYhHN7ApjLr9OaRjc36MHRsmlz/
RZ5USNytHDPFagT9xW526ye9cKcOiuQuiEDhDk6BNgMSOWXU7/iJDHhQXw+V0evnEt83JqC4XloJ
whMsXfZXXL8bsGofCu61XJY8/MPmYhVMmli/687K8rGA5syRrF3gmi6kOok9zYCKHJw/mHBC2/Ej
nbKf58aAlNhQsiViTP0WIBlpaoKRZZ/Mv2LUr55/RclO10IqPmfQ72RPLdHt2HdtfZcCq7Tu1XpS
7wmQmBGu88xeVP65ys+lDeM9GPFReGq6S1gnWhKTRwkzZUz6Y8jR+MNIK5Qh9XvxXA1qsICz6K0O
SomwKcIwToBGkZZSwJNMDGU0orai9Bqd3WXHe8uVjlaJyC/Z9bLapt7r0/PWypjblsaxq75LGtRs
TNrFY4ryoAyYualnLDWaNokUpD9VuuBTGyPr5PwdtPlUd4Dqp8riS/bWwKYTdJhQjV9vDwSgs+Ez
Esj6h9vsedaaQf/mwPI0vC+Nu7zXcwlesDK+aGZ6ulyhmuYHlrW0NMlmdZN28ct59OPlQkJ7mVH9
MRX9U9A6km4XUwjheKOJux8FDmWeG39EIMvzvPDVwo3yomh8F/+xj8hqd8luiW8gIJDYZAzq1CKo
6ypbKmrwr+icHTuLiNj2lbd4vOzVDNMz/4rW5lNjg4NvWPuyvzR7wLTNaXqeHKi8kWXCS6BeSIeI
X1tJDc8DSCV9qCcb1AJGuAC2gHjbKtbupJC7Jtsu1PhR7IR4ZX4rF5UJKsqCiUf78eex9gg8oYGz
8xjkyEexGVy9+uyk1M3FxmCOOGXHFjYOPQvHeADICMRxnW5fJ/P4tF78uK+rbW2iwicqlDgdzuMg
3Ydc35PP95jv32Wigw7uZx3z+hxGa1H3AYEW9i+ZXSKiQZ7+x71+K7eqhv+h0JXRgbHFSxoqPEFf
DxenyKsU1dFtbQCGX52r5DAV3hJB0///ZOcIWNfZuyhvgmV6zn0mYyhlLn9H3cZPOJEzLHxhJU23
QSZTmVxQNtx9DxI9SdKo2KBcqaRcbtk44Qp+Zy5/2zZ+M8FS1Y50QUFuCyR33amrtdw++oo3aHvJ
dKyhtNBgaBkzihpGOBRU5oVS4PQUc+uQd/FqKcGN/hhJf1Kma2VcVYNtYAr3TMcrz2P4SVRI70ds
Ea0c7YXLCJHdbxIHNRDCytljR3CmMv0kKLXMSyqet7qvFDMCOXfjAmOS2JMman7ziQ+4OPOWSBlM
jycwcnJ+vdQ1tQdcLRVdHi5PdGa2rJFWCqoVPEye4rqYT1QA1JnD8IrBXGeuN+SrLICE8/L9YuX4
E+yV95sTNEQM7TPxm6LXyLNE2cL5n5W/IBl7Rq9IqqUGM1eJyKXEzHJxZUrpOUN42LG70ViVmUGp
3mZ98F6ThaZxRNN06GtfKGcKS+SPjUDWIdUmyWC2mPCbJH8aO+CBnV0W3Sy9pKqPJTo9duYIgFyU
BY81bJc/oDi6eERxAkrQ5OzvIgASGvF2b74HMuHVKUH4kceFJAviFJHFoDJo/+ZDsf4tyunLd3vA
dlBd0zlDzkGnUul65+7DPa2YaDbIY2tQF2ZOMDEwQG29kXLNQen7pQmm91agINK8xxIt7Z6MDXfk
rIcnoV1IbCkf0FmVnbNPcQLCwABHPF8/SL0Loq8xS7VoKXxhaiWAfrua+XOzslpdFoa+6BlBThRS
pqZ/A9ZI0ggN8JeGfmlYVYulUFhIOmHmRTYqInRI8CY8JeHYDlVmSyhdCkC3M4g+/JYt+GCPC143
hJ48cfgtZ+UN7qwQl72ECEvSaqUEZu22NmzPpTU+l3thTgvvOxYOkG69lBkRF4n0ds7agp74g6WJ
9lt4SRFt8Gv1MouKPu6mXtATjdL7/OZukTw7DHj511uPk9BkW9rV49ZyzObfTwLRMO72b2o3JJTO
DCfbqcJgedYQkPNPTK/5E9KvJv5Gf6eX/oWduYG/LVlNYb7fXcp+U1P9DQDvFtKKBUUa6NzSZpDU
ERL89p7VT6+9FfSDq8niVErrCK475XEBs04ZQ/UMxEZOVbkdx03we9QArVFhpUU8QDayHlFpKlb5
4uB917WwI8rvs90H4HhFUidzaP650NUhhx6P3RGkdvajee8XcpW33QznKbRnS1uRlup1KcSw6G42
JnFEgXGimUubFFdW4mGQvGqEe5Az/c9qryfiieDxYAPNaOWrLnB1LVX9zhtESd/t6bkV5ZAcR3Ft
ZA1oXF6dlgX5SQr6QZR9u7s8O+UeVkQ+EsnZnJCzq7NhkO0U/e8Xq5NBweghtsHNx7HGDrRzf/En
Pio+J/yOUBrmOk9yepVE1SU+jC7sVfatkoR57FKxk1aDB8A64yN7RSmcvFE6Cmxfp3q4sziN0uvk
yIlOJAt8BbHP/8Cs2L6Urtk9hV9MIKffx9LFg4wp1Oszu40X38PasESXhN7/N+sPcVbvpwqRhEzk
/o71uxRxRio4q+yBlPj/hnMYV437i5fNqwxXtWUBt19bVl3WxrM9ChCEpopmH7LsbjksTkCxvCey
dG1t27GqiPeYzgWHV1/lM07n/KtOLDckPTwoGA95xrf8zjZ9ZoHlDiIb7OPNnwc7jWg+UtMX1cW1
OPeiJTCgGIWBIy1R6/dVIoGrZlxrjj1Bzd89fzU8D0SPCZCXTxOm+h3g7ffhm3ZUkO2TnVJuqdPC
oB9C9Rd/W8awsymopeP5AD/EsNyya2ZrmJSeiAfCRIZPGstsKHwrQJ7EzZ1grTfC/YaRiOPoONwf
aq/3miqNNOtlf9wXQ/B/7dWe+dVBghPAXqufacR/vND+gUKr33MeMy8xEJOWqMFLldEYeRMK2ksI
e/WxvljLCgol2peL7L/2BHH8zA4oHmGN3CnoCBO16WNwkMprkW0v2xPOkKxLQ2m9bwxgVL+h98mR
xuHbOKooXsaOWGQnOxJhSM5VtS4P8svQU/DRgJf9JGPn1th9Jqbp30doL9ArftsNhmMk0qnCqSvZ
t+OIO+JOC5CaU2sAi1av6DyJjGx7db4Exgk90qRJKgcj9/cwIjYHgPLnwlaG7jlCBqx/PNen6hBA
Z0hTyat2cLISWuNgZw+zcbzepI9RWEj3K5ZuR2HMfiWVd1/K/msMBlxda555z8bWIX2nJIKBOoXS
DeZiDbxNafIlozIjEaNJdAUyBT3H7FXRWVO4qwoSgOG5YseVMuokdPXsqZ30wRHI1kXl5/pFc9f4
o6XpaxK7EP5vstXOKPVh1pwSqSCYtJS+JkQ2TzEkC7Hr3VBzQfkjOgaHtcOQe92XW43Bm2zIslDz
dNZuRaJY4cgXQ6raAbhXzmDs6z3YGgaqUtNH4lfm/QsFO39IZ1NYWKW3CjbV7OxTSfrfjLn2R4St
27iIMQh1aWHlxQpbtOXbCO4nZfr6rEhLPUT1CgRzHnlSaUyqFuCqn0e6IRWsY9rt683gGLE/6BKv
QJaFcnbECHZ5Lu02gIE3efOHJ5syGcbbmKpAfLLJLmPzjQIuQyDi3ggIx4JKRT3XjygHF3WjL65P
gCFjLBacQk/6rv3uEpQ+nl99f3rLek4a/DSnC89HW9sIJqMJ+a6fwjHG16fEu7ymasu2vMX0cxGW
lhmkvsujbL6Fr4P4DcIJU43XTcUSgojF5a4wh/AKgUw2J5IpoTHAjuHc/ZIB8yK1vaLOxDTd9eyo
yIz2zHKcJYTtmt7oDWvpDVKP9uOOq7Zi+cOE6wiB053UTbsT+YLY9ccmP1KMzICrEehQOpcQ8o30
E/8eWLLpJr0u85qGPs+AxeMOApWkFe50XUE+BE7J6TH7HOO8mHabocRlUb9MCLm1KLuVHXHdrL8L
5ON36hXLo+b5R7vAvbMk+ESNu4l+QZoHX6QE0S0ZI5LAobXpUU1VUESLSeJiZJ+xYsxXdT1wyBRz
TC10LJJcqQ67U5UdwC15UExEDuCOKoKA3kE2xSVVjyzIUDrKZlFEdAcSQRpbQP38fqNaxT/2JSw7
UN6gWY6CNWhuPJab+pZ+d4AyWEGLpndATthH04p9q55Y8gZJM7ivCQlKPQSjSTUv4u6HytQXSH1L
EjIWvXMtQiRI1bsgnOyzm/Rqb7KRwjcrHF3162VnGD/kTVDFUv6HRla5dNtZDzmPLBf4PiWZ2vLy
W1pRl4Rjv/IORqlHbTuQwbcZgbx8bkKMN5yGs8IyiHJ1tt92Sc4UZBque7/DvFUtvBMuHAuObouB
qSLGE/qr2iu48ot/sSez8623cSdBes6lHzZL0m8uuDrDti6QNeaeRQgqOOTJQS9Rr3LRt7feh0qp
nViijbrTPvUkkseWgUMadF+SmkiR8wpmRHCQbOZdXsxxRsybgqeqXIqBvcvFg6Huh+7oUaEgS/Mn
e3P8Ug9CJyme67MJSi4OIWhSj18dhyogysqfnX5dtTmAjkcTC4yIU5VXZdSMmqkR8wB2S6imR7UW
1jtfJaXR9Mx142afQIokdzn0UYWQTgO3NEqJxqoZG0PminbWwG6JhxnhRlpS7TOrR5a25xz8vFYk
K92l2pRV6cWhkTfU+9nQFfm0KjgRxNObnfW/K8hxF7VL2opc500xFlCjpHnXwIpgzHhbsoWgXA37
wKiFj/yKPcxBX12+VxMgOs8DxPLrGhUZsLnDzF0cTU+QgCkwpMDVTTkRf1aIUqfC0Zc+SsSIC5qZ
DJBv6u9QeFORzXKmxumw8SWI9EnPhiOpPlabMXgVR66JTazGd1a3VQfhaWdDEM9373nP2TXYB3CN
+x4fsUi6tmiPgi84I5CHWEMQLEiWHUMTjd8qR2ND1owxJtALXmzSCcdhuDTegrJYArpcAEZcgKwJ
OsZwneo+vIzy+Y6W3Pr79H/y2zdUKELHlGQZEcooGwba8FNJnPkQTaAiai2XoVVVvuhkN135e3I1
veL1Fnni/HmYh1ytA8g2fVYgs3r7ZyZpqGD7aMxRg5whME3XjBBSbB6iej9VoRxOeaYRpJK680mM
JJeh5TzROV+SIPAF5gvEd6DOjj0+lDec82/W9AXNtHsHZQHPuc0/9f7e5Es+NyNj7vyqBNcSxZ8+
Hg+8XGsUG3hyCoqxbl6/eXd4rRExHhhtDGRZjlZzuEyCPx6adsqbTAZEcvdubsSw4xZLUtgmK8EU
i5XsjvFJ5AzDdggh0DMIBChPjDbES9ehjCJJcZVxQiwjrXywuZjBfeR1ltcdPItDDsYCPYCQ1bbv
0cbwzKsgQa1Tkg6vkUY3ZSBEemyZOz3FpmWxQ5pvd49en9uolIzffoOmXFnpeGggN5uhwq1D+Cbq
0XaiYBtOmCakYJi4/mGFv5UHjUnj1pvU5rrxly9c/EgxAM5LF4tYByshDnVD9U0m9u+LtL/799lS
CkB0ELlHdOohl4kBKiIKXfKzrDWQeGIYhOYd617jNPCn8iqpfNkwYKFrNacR5ngMrgdHRLq7QsU0
mkXx+ktNcTMcxelWVNxl8aeelA/ypxyRStfXyr7sjSoyJKjX+UQajui+ODN9PmoLGW1wEb/S/Kxl
qGXFEfOX7aXST9aV0NScs0LlSYAenxSHJyTHqZO0QVSqj6GuzNw+4973UWXTqMlrGLxAdG+rUit9
nbEMPL2lfQ4OVkXa+or9n7n8eDgM0acJLUP9OUyIZYHWT+3aPsD5Ehfr4t+Y5Wep8BCuc2vGCsNy
bNcPDHk85qjkZHMrvkAjWCNLN9O5x46XACXSkymr9yJRaefhpTUQFvCeVTqo27PHttWT7I7SVyPs
4QKEW/0hVsFZOpnFPR5nVHjzj+rxLRP57fm4Ijpvp3rJz7yNHf8A/vzqKBX0TmouDw57IRKeZos6
U6nQXb8uWG5yBIBUmy3tFOLQBm6gJT99VuxHK3S99eLZfklCuyI+kTieSq1iUffYR6byfEA2KXKm
kphHGbVjSHjySzN5k1d/weJmRpFug+kvnAPgxcjHeKaVFLIBtks14/xshXp1Xwssraei8PdkEVd6
9Pmy8lIrBOx4vD1IdZ/x579wPinmmqQlPnlQSwBpmfV5yJas6k6vrspfKqRZENL40xdJpFnxSdd1
uiav11FtrziuzpmAoEB5DIVl56ElOM5hEXPPjYvUlv0sR2mUpAvKRu332VCfCxbNm06oqmD7BOP7
1x9DipEvCHHXV/kbmV0qjRLcBftLtUBux0UoGPqEfxlg2Txs7nFcOci/RReVKZxn0YuFatBmfv6Y
9AYahekvpCkXNbm8+JWIqlt6+GmqbpdBqzGQPt0yu28cMqj0vAW+UFXPEFmYO+t+cCXcPpCMbVbV
fwHKpUld6hORx84vGzQuIMbvJcwKlEqxMcf4bQ+qkkn3kqqbptVvSeJ1Ipl3fqbaj4ct1oPB9bkD
jGcrqxza8HQDPXeDpNRLxx6nxKkOFmraU2YpW4WhS/PEERVZBuzCcqpKXQ3ZlZ2uHGwim8dKHwV1
+n/RjZOIkYcVoOlhcHx0qTo6xTi6J6g+e2wLSw95mRfvEq1BxNuTB85O9Q+EkRtq0TRU+LoSqSGe
h+AvUbJUft7/M2zeVqYM5vo25Ue1KqH0P6igo+6YUPYuMq47plii1u5061yDJfdaXoa1Sd8uLtX5
bYhdliTozCdxFtu+7GERoMnYaThw5suqcs0QcT66SOm8qO9fnhLNPWoch1JVzELscCIvwTvg74Or
UvLQU+h6ilmHs4LkROIRbTBNLEuzXgTR3LrTNAAaz3tv06cTdHRg1hYPaoAF+OvzBnzXxuwpmDfT
dpJC3hb7RlAcCO8WKYJhuMvmLCqumLusMg6y0KDRhdG/JRcYUtIblFjhNEtqXsElGmn0ZCRC8YPu
CUDGQzTWABcKfSM21+YiK7QApwzIoDPZy2dfJjMAbqukjgp/QfLV1h4oOJJHvU51BhTJ2UIbvVc5
Sw79eQ/5gd1ZNSLMvwChOqXzEnFWIRM2T5z8kWuwAh4ncwPQJpAKSCEycoawQwx/pk3LuN0Ebtrf
8c9HjwVWjUV+aT5tklMH42OOFS+f4rLJE930gDPUN9yaez/z7DCqPKNFSQHVKMedMjpkBkGoEm7Y
zKOCqlfFj+GALcs6SO2NCN9VFUiV7h1oZI88O7PESuXjaL3Y1Cx2k4q55c57tcC+WT0PuWkP/f75
B0oWiFPFG3b1oY95nG2cVfWwgB/rY4zA9HlSa0dMnrp73bULNiPFQCiiFo6bfhjmdqp9GCTFDSUv
Qgwu6aqiYqC6IHNwHXuzk0Ad5UnbvqVZ1DuENbtRA2sr2Ubu5qxtJGR1kWnVsRFp+pK4z9KUjPb6
96+jq2hawBXminz0i4qdG/99/BeMS1Pj/k6KNQnSycMy+ASnF1/GwWWL8I/6CiDD2ng5L3ec0bWo
VPiiiOh8vdSx5UTHdBG3ithW61HHGZtmgzZhF6oXpJNPE5cjN9Fd6lpMGjzYfGE0E8EV/LOm6YyM
j6PxRPom0FoBNYGzkplcQk/3VvnXlYjPgdED7Qutn3Km6uIb29su8ULb8GAey2laLEAZDwUbD1M5
yHvxJ+klboxRtIdYz+tkVjUw0MfWCcuYzGotMsvKDJATc7jE9fJRb5ttDyRB45f+5KOsZTu5DoOy
12B5a947bRJdilSN9drC9qb9hABf9vR28tfgnHPF0AWopkhQac6xDuuGYqxRFc2K5+5TROY/9lL9
j00qIumGrPul/kNWDoZPYgEmm3Abti5klUjKhznWRGobawjBBHIrcMgCv/zrG3JyhpE2Mh8eBkqb
BPzJ1oOcxUiN6HPRUXf+WJD7n4bKRu8hjyMF864ebX55ZWcdIzQvHoxAIQ61grcNvyFxHaIzyUqj
2cYimYZqPAo6hCdyirWf4z13n/durv1uVxgFh+5/kWazWevRD1RDOzJYDWrwptyaM7cS6q22XTVp
jyYqBCq35rlCf0VrY4N3XSc/v7T43t2/n21C3DZuSb3MbCb2U5XdSph8QDVxIbV4xn5kwTyQ2JER
ApD2BcZVYGW/lgROyi14Mm8Q3ufvXbIDUBLabuuIdXT1/b5MMRWpSLX6OW8uHISl+urVDgbVHP40
jf+caJCX3Hn07Wl4QhemVu2uyit87LQ2OmFHyrLgMy+cdHWv8iIYqFrrgizruo3A0jOZuw7qdBH7
Vzyv9pW8uKy0NTH5T57rzHxO88+6Zt5+RgVbVjAZwErgS3d6O7OyuW86NWVgqc0N2PLRHmZh5Nhf
lsz5yqyH67Fx30CCxk6zO61nwB+wBWmAdW66uV7N4GS/W72aR98557W7dp0z3RfsO4G2PzgG3ttk
j7Tg1jLMD/HyfiR8WvRiXPUhlqsvvrzRPo397k8mitOgcGJ5eFLXMbu589amOJMt05kDIFEQUvIl
jEB3dxE1hu3HOiy3LXWmI7a7vuTtsnK1mU9EUfAcryOGKKbMaeR6U6QdjPC+XO4RdhJ/juC2YsjQ
pWoEHLOgveA0z46D0Ju5IHDUfd/KtQPtzi1EnID0meEXhfVdY0rfT2WhwOf/PWcWPSrR39tqGGlY
Cp+ex7FTI8m0ASRwzvQwzJGxpeyW2O9twgFttn62XrxJjWvsHjHQjeFsvbsYumRGiuJATvVTj53d
N4LRssbGNiLJ8JUZdudc5w664V0IUYktB9kcykedzCPPb0SJbbqqVD9Q7wyU0gTzHsAEcQEDQTg4
4HDZm/NsmxPyz7+aM3FJHPCzdQcfEDCFlLfSxUK4qqggmddrmRNwhC2ef6rpH/NnuloY08S5r2cP
toJzP08Bq2iXzuptbNbDP+h7QII6FkHrKvEbGeFFEsEKtjwi1hLnQhHU2lFmeAKEZFpo2Q4ShF6q
g7FqeeLXNs5ZkCNfXTBA53ccv9dXRSxU8CaoqoJ13kmwPszZqV7RKxs32rsNJOqVISx3lZzPhlxG
FxzuOEEyr8cGdIBxe21OHG2T5pCNyWNXNTGNxPFX8O8lfa4jj0JeiN5rUwsis1a7W5r2QJSbPMy6
UTcvYQo8rmOwHlr1y94dFKogN3U4BZbV3fhXitjT3yhD/xF3MM6gjOARFs19GgZVyOXOQqJyF2ja
+rOkguJo81MgePpiEIiwBPWMMBa2PBLx+1PazhhxK4V55QztCqd0ErfgvLvl5HXlCmFdcntRhY18
xBElfErrtBPROdFI3SjXp6/e9/zJpFfQG+FFhpdh6bdiu5l2utxxxgB0BWvdnmmEsUPEjLmN1SvP
anxw4ut4apAE/dtOPPwqmQfqeiyI3tkKxNCSzz2fhM/hUaNoEs/xLIfG54XfVGmQcRmKgpkNLyMQ
xBoBbqNU918A3sgbMmKSQmPQqdfxnqBDJMoke72BKmfdEBU6ku/Cck19OJBzRi/RWeMsoMTPX44/
pSXuh4UG4BOXmxzN939ZwyJv+9hYE6cP8KzkaHC6yLiak38OKWYUkWWmc/YnHWsGYbpTHQpAUZ9t
VCF/vyhNL6HamPQBOlbj7do/T5lWbWw42dUB9HiiWBkNIMfxdBWu5vUF+2uFjaZ0GkUBT7RFgzX2
y5DWNlG0ycJomogXcmG7EP8h+m6kD8EB4pzdn1cLnp8QSEI2rblzi3j8D+aIRI1HSXRmitZYJPHQ
zRiQK7ZL0fob3w/Crr2FHVHZswRo59+3nN83fpX+CaqJMvXsD/hnSR0250g4AAraJ+5upl1qqVRl
A9+UAfyhII32M3RU6gl6SOE4CLtXly809Ru4iGnw4V0XXMBNQTXAQRE4mZ8GXZqexGyPZudjUqZq
VnEKOOrVRlV6oJ0S9xZQfofi7XHo/nZdmrdw6ab4diXkAU/8eIEdNxCDvSVDhpzZ39tZEfaesPVU
mkahrRm4bB4/Nm6s3ijedMe1HU2wOa9DoxxtyCAb6xON/XVJhwwKZFHYaW0HdUgpU+eWjBIQ+QYQ
MaF8D+RU8frutZb3/xNhm1cN5PPoxiBYKAIpjtcSxnKn5HKlp8LYYlu/99htMNHmAs8VlPlErO3H
xethceVqvUbx4iH0k+Zp7lAsBBvOJn8LtZJXCQ2FJlSOhjAmVxoKD6KMsz5v4Cb6WNqlBBUjiXRw
+0LYSyQ2OnPdMlx37AeUTDM3W2UfUUzdqj1PCPRV6XD7OdlbiN/hp+IdVLbHUMu0+oGAO82wcJQB
jJk6cTdvAdiEjmfA27kK02nsAlOsxufLDlasJQF2IOQo6Mp2Z60kfnAnlgFq1LVBgl2rH5yrOZAy
mvNMgQZK4RPelu7IW9la/gni7CTBl03pCajBwPdJ8UjgU+KblJABA0l9J36Qr4tMxgLkYBRyYnUn
iaVKP3eTH/+2hRCBC4ZJmp4ICTnvKuf43rT6tEBKZ4bkDvJWPcRJ00lA7iGLYza91crEFKChBSH6
QrJFEq2ceWuynjv0TRE2hhbJksBqK4CdQJhoCoUzrJ64X/7o6VGWRH5GlPaUEBu2QLdbt2YydG/r
7DgJT4dG+ngmxGaTwn8WS8lKbBGAXy5Li9dhdugiOaqPJT2nlNDRu0L/z8W3Zd3ZZHQaWTHiGUIh
Vfnm1UfCJSkCaQ+cyBpe8cO1qCNOtqKG7ey52RLR3mS4yNr7kJqfriOMntv0hBIXlYhQLMwdgzxT
GCjgw+yaDoVG5qT8/tHtlNDIV6t27+MCDMFcea/wW7us9VEDW1Wm2vURid6PcMdLwybmv0gpGICq
1r+tUGuKQ6R05NPk48TwWsTNW2T2b/Iw0Swa1w9BqcaHPGWnu90KdZYI1L3kw7k8vt2KjzvDKDlT
da/yZqmNikKv5vO9yGJPfcoHPd2L0Al8P9KeUKyROFQuvHdqSwN7d2kDni9umxY5xx+ErFNHWFcM
UGFIzdtu5rkyQKNtFWMe95UjiVEwjr+TD0IjLZwdH2HR9k0KvJcDBqb9P8+3dDCZUStERkkKXAIx
yTiWuliC5QP3FH/dVC9QkX/s1GAYB+IS6VZVEtaQV3OZjJNJ2x1x7XcDPTeNuU4OZQ2YeuNa18eg
Lc7ro6SaYuxkdaE/T0zkXzlMuVm6lERh1kkc4kstZKBIfoL51N4Nvoatj94OAjCgB3T+c34r7dA3
XeNZryjYAYazSdvy3wXz+I1A/FyGZLMwqjXygFpg1LlG3AVJQtibTYVwltx/nSqPwqnA0uKkc9QO
FY+pA1F3IjYfaBklApF/jmi/1NqVvv+B6GONANRt17Cb57kKPevQin4W+HtFwMWJn53B+ph5ioFy
QEB/QWHPw0iX+cnTUyNzQZ/wdKxM3PvGnn38rvme/x/wtqL74vmkYOdsJBmzZa+O9y8MbeG2E30v
+9jts6ruud4qFJ0Lb7VEIB6ZefOt7qSZyB3aiAHpqJx4F13pzGMUwaXJooTGi+dHMH0rq7WW2GnU
2tyYpwkNlK78JWIU3ABtsyMHIJ/eLrMd6FkDr0lBhBHNr0ZMCb30814pa2HBtMgsdElEWZacDh7c
nTGGA4K8qaoND7ZJd6KJptgwvNXeGESaqdZoSJuGB68kgBWY4iQYSIWbMiyTkkGqhtBBpU68CRkm
sKYJC2kEmWWC7JVZL4fBkF1Hzn6KtRHEEBkJpVD4XzsskiFeBhNKH4R66IE73drZu52Z1xIq+Ix4
LfGspCNVT0ulF7YSMaZRKrMCdXx9TWVwRUv1zRfil6seigvfz9+NZ+1u7r1fOJiipk9eekB/6ZK5
iigkIkPcIO5fGL53+r2k4QY/gx8336YlBn5sk9NNxxL8DZ/UwrHjy8HX5ASID/qG4/nccjH63qUY
UoNZiItos1pdcrwUldPD0dMC2VB3ttygqcd9BAywfNFjB4vLtr3B3WmTEPNo5uMJHmsZIEhvv72Y
63eBGjNjC+aU5VPvGHJPMpWi9DTfgUkLHQv4gZ0wQ2ncFeYaahXYZbV38A4pf/n7SjE7NHsaQo/B
tUKwOkOKiyN3YEhzwF2QPbE4QngR2tTfuZ8NBnfouXLr6jZkMFNc3ByOEU8OuVb3BI2VnHT6cyO9
IPEd5ZiL9LAKpG2NTWUmCXupOn+CBEepyzbWc9o5ZT/pT4deYkI2hzfRwlPttj+oo3l9/eh9MUAE
o7ODpombkYx+1AnJgc5AAlIYgUqffCnCftaBumolKH4QBuEnneyVo3vp102T51woa3AaMIbtV2u0
3KwOHH3IlW42lcy3fvBo5RqjX0d2VuNtS1M22S0+RdBXCC1H2eTJXIFa+EOxRPs6NT/hfYEEfk8A
StN7SLJ/3Hbx0M31dqbnfmcJoemVjReFVRo+PFllO5Ba+eoQHvFBHEuCLry8Stx8+riI3e50y9wJ
BfjivWpx1wjdJ72+V1XUlXSA0KhRWm05ex/Yh2aAizrqsNOzVK3hW/jVWvxWWhLQEyp48WxQPYCo
SZfHLf3CaMMor/EPSo0yEbL4k5nRUm9SnH9w76Zqm4L1EXkdil/3pyR4X2eEtUu8s1uTdEyqFdzB
i3i/tJgKgU4up5XALaYqmqPwTmJnndZFCCmSaouyssKjquS02x+5gsyrOu0bLj6ydNSDExB0HnnU
POI1mL8nOkag9KXf7EvEqrFwnicySpCGzjZjNXKNV2Ao4S1d4+BXgB9nS5ObchtigdMFsYWaOqUJ
PYbIqgTObTHVqKk/QFXHfyx/xR3EXwDIUs8+F4Q6cKOJwYCCiTiQkq/h9+zD70YsRvpGJFUgec0c
nVFxry6QHbM6v3bJmBsNCCt3VhPgqNO8wTE7ijVEsEOCkYKunXCaT3XjNI3yd7PiIa0NM8av86le
wx/Sx+89GR1KhGvIgSNjbJACk8tQqFQX6Gz7fCAupOJnfDj1+1GVWXm3rTVZ6WT69ubak9coMNjU
XlabHK0tdOQRU+Cy3Xo0ILSUfBGJwpYyfZDZcTmoBNK5l3WANoGwCc+vyQ+VJgQiuT0u9Ynd+Ztw
lJ+JAsH8rLCsNC2hkVPuo1Bw7Nn/K5eZp8Eboow1S0D7m7cxBltSt8Z2ZsvnolW97svNeZg1fsZD
LixWUVSaFKqjmfomfutOrqbkXYBFpRrsD/c8UGq5s3FWxp2/jwU4DKaaLSqMeQgnsrdirF9Iwtr9
w/6xO0QY/UiNvGjwqQTIXd1jhUCl6A4IVB3EDzWG8PbaPxTANodtsCgAgPSDXHtNebvgr/5/67VY
2sY0Fxi68MbuYPttSU0ehM0KmDGkcSrILUrqWdp/y49NSfD2t4cGmm5VRVeg4yySD85uXKJ/HugV
UjFDeTrSr5Cbg+hcsF/M3TRvYcuW6MmHzPUz+V9dj3V71yHjqSgW7c9zhGJA9Sr36RLHdEqYYhLc
ewl60CdOzx2+TsI7ooPfFE02lkbRCsJYtQw0WqkWdBb2+zkaa6EWlbMPNTyf8RYkIYYNMiS1v8b0
Ol+ZutYaEjQiU0mei/7HompWbK6p+HNh0/NpruYRaUepbHknD/1QYkm9nZtZHDz6voZGIsryQRka
z1ItTDmi2CHDfCX1tdsqBV7vPw34VuJx1E/YEWuzsiavozFMih+w0pdegOkJLm6+u3GvsBxz1V6g
A+QYzJwzi/cqwQrO80UWKTsoLo0sdZHb2P7aqq95kgTvdC9IeT9jMQR72R9aDh9RaLiYDj8oYRkO
X3Tkm1nUl7M8+65i95k1yCMHnb3qZpikChaktLS3QW3WBGJ6gqM1My4GX/Fy9snnpUVtWLnXxIjF
jJ/o5RLaoCP5zOha4etHOOjvTz6Fp7TnnHW1kXBKLnEER/dc8B7JPd57zCDqmHofL373r6VNv1Vt
lgKQ5vZT++YKDrhFT+HACeu1R28j55Vs9OtXUWJffcGL3mUNmMtPvenuTmgb5EeEOy4DBhH0R4fR
LSRdw4+V56OBIFvWaspqKevbqynN0pMwRaoVFtTD6/nkz3XOL8fnHHDhcj9Sg4IhJWwOmwyRWp/U
nimUyTqMS+gfyrTzHZhc3pYuEIgD4GpPmR3jI0YVlpWaLbny1p/oLKS1YrVEJ3ILUYb8f8u0BTRb
A11Eb2NEJhyqH6Ifzo3l7c5r12c3hC3K/9lPLLVQG5K+51ZfhgF6D+ct+7MW/z+VwrlLk09qbR6Z
bJ8Ug9CbL3E4R7S5m1+4UrM/b/l5mbPhN1nuv6rFL6s8ztKJELIMBjuKdmTse+q547cQ7p1QQnhZ
Gb8nYRaIArIVEYqOHxUWPKgmabq4KG7yw8EArzdk20Mxje7zOwWrPjBRUHi7p+UWVbfKM/DhKTxI
jC9/ywV/DuvMZ7GFY0ylKpK4ds3dpEsyL0MpkV4gvMvHrcME1As+XaQo+eML+gwDk+D2rgb/9iPC
gR6RHHL+h4OW8uRUDuGVHXKlWDvInj7dr3ZnDPpsUYoo1scsPb4EaeMXeSvgnrAwYivKzm54b5dp
Kss3zirqI+mAYGtN6I2fFxZ4W1fx+KQv/oGRz/8scfimL6ebAGZi0A2TUxbt+bI4+Guv9LZ9Gwlj
AunXkQ5VSvQjlYJugn7JihUk/sYH+VdcPmvDSq23bRYA8apgYsMc+hCvAl6qU5c8GLAAWwAo815U
RSoVQl9xJKG3GnPUfwN19uhuczSDZIG5fr0ovH6Cc3idOdp1IXGuz0ehgsH+tlYk3B55TLFb4X3h
qv5IG3q2PiYuKewEy0Dp9PeEE5s+rpi/AAc9zF6vssSjH07+xx0uC9S276A4jRJWt277cFq118Xk
VELQGb+4CVyULbZE55Vv2uZRjt2WTaQP/gz6prqWU9PoV3jmOa6N+Mnh/7kQ3c9Ahd8qdwn9fz/a
HD9eftuYgcFqgtres2AEaCdTYA1EiccGuu01ct9q+nfCqRVpe8T+bN3i+dyEbUioZLwG+FxjXf3m
2YnSeROIK6A6nB6hiW+oPu8mVUCsL5FvpwsSSmcMGACkhkmUSa7m7yHnv4r3yrO8hNqC9Qr0OGrd
wiC04LrjO3lXIx9coZi3o9A+Xe8WuyP52MacAcQqrMALC01sgT1QIsSEl3PcIGIdYBXiOoPNZnoq
yLrsrUJOst6aUf6M/6KX/L94QPNqNYwKRfDQ+ExphSLYXlWzN60eGoTHNSiYWehYWeSLNKAenKMM
hJrLC2boMRsfqIbP/sjjxOGoSOy+YTEQ+6/fF9UtG90wy+KBCFd855C0p7qA+8igvG0/6NN4D147
TzN9jIh6TmB7mrGsBLOvpReDl7FAIgNwgeVBMiTFvu9h4V/Z4rQZQa0gpR2IkSB1lpRlG9DyZU1M
rn2NdjoP8sl9S6nKBJpcu1QYucstkNxS1yFuKasYDrr2oGEuQ2Cqf6zJ55vZxfCVOdhygfZSFBAo
z6hq3SNY8/uNhSlLPn0Oy4/o6jAP/qVRbXLRlYbttGUfGRIcq+zpkG0VFjUh3dv/EEVxiCIpFSCX
uxgpkRs2ClzDhfTQ0l5Jr4EtVFaNXCe5Ileynj7Aylt1b6brK7nH3Wc9mrs2ZWOshq++LhCGHlmR
VzSPdF5k2bDABw8ZNsy7zJXwYm+Z1wGaN+C3Bt7eiyVTsKOX4u8qGLSQsgXnGDcmDE3B4QCV6RoF
Dhowztc4Ky8BzUM1KzU7sfaMw36ml9xikmnkhVVhRNlNBKrRd+88VL4GWz+dpMe95y7vRZ4nWiN6
kv3+n3jFb5GXzglGipS/RtGA51Vt5rVUcZngLozrjKTPL0cmgbQCKFXw/wmJpuzUMnzuwTtJq1h6
fZhB9FJmE+hn8+NBs4PMtVKgpjKQe1RxTBDptIpLrB+8KRdvJLluZ8A1C/5qFNifGNkDCd1M4Wkz
ya5Az9IK1vDnOE3USbST+DqZpbQ7BczR1V3itKUyoT2YrpNakSVrYJC4quevaeTocHodhJEIi9aN
oRdhyW9MoCZXDVdrQ3neFOotPiP6aBm40YN/9oc0xAwLLMOkpI7EBnQ3piZOep+oRFMi/RYldxEB
3TIIUp1tGPa2z3/f7ETN54SPaqCMCBp1m3wsD1AO6l/O1Q+fRpoMOZHUmt3cbuZm9wXDkedF1gJK
ROXs8xHcnn92X/5LmGkWccRw86CeUmAjPNW26fml2gA5kHA2uwbuzvcCx+2BVVRLiqpY5vIv9Y8c
rKj2+yBPo7E/+sv5NxhdiahAatIlmPm+2tGRaR3t0BL+XzJ4NuS8m53I9Yfi0ZpJcMu2s8Umykhx
WMK+NNbv59QNQoOjWhIRc7I3cVko3OuyJt05pB4OxVxQ1ikpc1DJsZgKEO3CVNs1rFdEsL3vg1s6
KpCjijqDMA32K5OWe/1DvfwhlGVX7Vq+PuF0BhFzf0bJ+S0bHx4nw4bpcIjN/v3keWt71Bbmz/OR
JeQ9Qtbx3glx+rlEhRyAHzWR1VSI2X5A1Qixq7hfqS91Q+GdJHMAKqUwgi6C5m0GkCkx7lrREQAc
BYn4y7rcUXynj1wN5QWzbe+yhBJ+ks49I57HCZnNSIExqNaStE35RBdXS/0YsZbV5mySBm2mG1bM
4jObjV4mOuDgFMmB8dr/PfXgp43tt7ZWZsTdSOxLRQpFlKrdkpx2Saofy8ezcwQ3QWyyXbZPAjAP
vR2nqMx3HbtwDV0g3nSoEjy7TT6H8oPCkZQ8BjZDDTWHeY+Q5L5sE0K2smiPnyeiiqCL2coRXlct
ZNFLP/nzDzwh1mlzJ15p2sBas/uttC0OGCFsqxsEg3+v8zeY9WYrB8nj+m9klrkdGhVHqxgtabPy
iLlulUMprVFzW8sRZo+X6SzMqHmkOT8590bLWIoRagVzbchwNX7IFvbcprQJNMPUiv2mXdTW70Tx
PkBJ6rZeSEi09LCG4Bd7XqtrVZm6hn8UNl7C4IQpGP9frJZA3uW046fKuJP56KrmMHSZQF9ne25e
W4oWBM1mFphMO9fgh9c5SXpndZ/uOAbcYVM4WSIe+3cOWQOLgz/c5aCN39Uahsaq+zdOCYiRzkgh
4LAsjTYWb/l4DZ1fqya1YTKuc3MwcY7hLUuBzDaQty5BwHN7ZwzcG+QELxIgKA+l7dBiqGfHRmIT
SWkiv+R2fJ0Tm0HcOdYVigTzz2N5unN7BlAymOjG+ZFILimEtJyFeSeZGYvmiMdjAHQPouUG1xYp
mo6hfBaza9gEa3RR4xiMMAp9jlpXrnjcSRNeCACyLj0GJia0rsSFVZAxG/fEuQFTkEVeJliIa/1X
VhmWDilZmXLCcHM2K3OD98VqKhMeI2/nypDDsOD4FkyCWr0TpdQ+cVep2yf1HLZhAQtSz5UdMAkO
SxHkpkMObsPG9AnDbNpRfAoTq15hN66kjqXHh1vXuD1jhlqqTqEqCVs6mwmim6jb5GtgwAkZENJF
CyTODBsW5zP3Ex02qfRUHA0r23lOPKR3gnqUkrQf5IRTz/FWA78X2Y2GBxK2wmCCvEDhI1fgzolx
6yIRgu4JUsgTWckUTSCceRKFX6oBwvDUQyiI1Habhx/a+jKN2IwcUDd+iYyoU+m9HxLq9z4AThqt
4DNL0moU01Wn2SLRzjNCgUFNd9Nh8W7jGR2cWfNRumEOSUDVaJC/2H889qht4ZSVfruVTj3BKkmA
6ET8qMoDcNsJDIZaUlk0+MfiTcDPb+JglPFKCPNKEuXgbujuZAPUFa2+QoA1eWXeSK4XOquNtxKX
qOCedBI+qCiyG5n+JLAmo+mCKlGLL4ksHauzCoJUjFbox9a1kHHY3PvFMZhElk24nCi2CstyneGT
0D/4JyR2fd7nB0uujj9Pvd6UY1p1zaL1Obe6pOS0Y4efxuDRTVXx+7VBYxgNhlG4Z2mYXx7U0Ge9
0jiEYzamlcfRVHLVzbjriAmZUfhVxdw0bTiY67VFXJan5tJ7h/f8CT9jVPo/3MinWFp1ICeIkodK
Ucxq10VV8qgFXEtSq9zLeAjGWy53GEb78GGPsx8+4Z9YToN7JLjMlefcZaV0KLM1ASPQ+GB28K9V
us6jphIkZfL5iIUv4hgo5qiO5ksFKgRd7M2VQrP4Vx3bGOjvWwk/Wtxri2xokDAm3KujC5J/PjKc
dCUcpazCHKegW5DcVUJIeZguaXleLwAbIe2Dm/Rsr+qNVzMeiO5rSXO8PKQSu24YAPvnpAhQFKEd
c2CCDDtpPdIcVUVJQBk8km3gzGKHq6RH1YS9ax4TLFeq62vw+teLUlzViFybM/qkXRhmFMnblxwT
xjYushKjB3fDGKgDSgp34KoN88SPgnZdGDmbgfLw8cD8sFS/5SbAINR+xoWF6xbVA3QPl9qeobDb
O3fnrA4ELM91a/fUIs4aWxmyZ8An18YSR+AwsGZCsajXu96vMwHwEq0qPcbNglkJ+kYhaGmDYSTl
R3lkx31s99EP9tVbb5m3ypbJbI+Zagjb9umKbJorkTH/4fpAGs3qPh2CPmcmcgFAEAW48QT+y8DE
31SgTJNf6XI42hYexAXvSUq70KQiociEoFBR1/15om6yWKPtGKVR/aEtoHMNiOtaSatTr9HGyoTQ
t/Yb09gkbswaoJmtEcbZPyyUfUH0X8GY6h9gMa36jtSzzCx4d70DY6oUCOTsbLZY3XwJK8qhaQ8C
k/Sv9uujYpfGfOuiwl+a5yYUzpnAe40KU4nwIIKqRtCriZiwFRD7b6KdpUzj3NYQx2GZIdso10nY
I/vJUVupq5nhWjBE3W0eQCRkhrCUPBZ4CJbsji0NskGvInD2Rd7DyreUQK+ry/tQnt8Sq2kC7AQX
JmSiKyjXyyU987Ro6C55E6y45Xber2SlI0rKrNk7B/JG45XRagzufl55OlrD1HQSdy2P8kQ95dib
U2oVR8scvJGlf7+GlQNsQvqzvuGbECG+46t0Pvzi8ujzy4IAV3IXLOLrHthnM/gAXwKsRrOKn0kO
gWZzv7sxIB51eodkBeRsU0IFKdpfJbe+rHXY9zjCBO3rGxCviVsOlQhP20R72NYx7EhrF2cUP2PD
ZfO8icyP7z9gIN7kAB8+GiiPTgRQw7wqX9dIVE6ax3Cc6UhJ7uKgzirlTrIVg5h0pwBADkbH6sSZ
9p+WeGRczAlXmJOI395TCAHK4koxfALn2M3e1RqJ0WiGJblUUNQbpZuc1c3pxFs7kH6FzU5WbmZ2
lDCj+We6b4Q24E+T85W2U+zg8c2dtwfC2hsx6IwRhpqGjcuVHxvWHyUFhRwqJT68UsqhR85454xd
pDqxq1AyJGxr2/8PS5bdKmRQA+xV6HxyNHnMA0ZQs4q9AeQ1q9Z/CEtDFegC0z0d22cYMw4lQncv
URUhiGKUzwO9t10+jL98f4152TN/VGZPs9+tHlN6EVqksSuc/wjtNZkpAJivOHVQd1U4q6P5a0Bl
IkL95LSN77wcpQtol3FahE5hEHcpkLwmtuJWI44ie170OfQ8P6Kpoc90lvTG9py1pY41rtAIZLm1
xI4ptWCDkvt9P4Y/y54v2/k0xvdlMFbuKWIGQUGGDw68F78NAgW81+qvqXPg9CHHxEX0c31KOShQ
wONoFqQYkNzREoD+2gU1rH85pMYtV5Ggvk4Yt+9cifxka7iD4jnuTzolu5G4sciLFLuKrFP/zajd
HcRRE86ea56qMZMRzJ2k9hgB8SqT8Ll1tJ3y4EwUCf/Xegxihmqhr4+grBZpXs/Yf1zvYyfE4Z5G
xUD8WfLJER//MPMq0yF3OVkTBhkA3MTfR/TK7WWz3T4D6sJlrX4Vj5/dBxrhe9ycnNc5VrfK8K/y
5HwkRCdo4u0imwvmesygiTJfLfIskwzOmX//tBV2g2rtBNqKHk9CuIsmi22V5PCAB8busQ6Fozq2
jkfQmvbukxML8Xt39QgYJpYxa47X785Iz/wX9hD5hf/+kNOfrHnXmffr+Up2sQHwC7D54zcn6WLW
qYIQ6Q2JJcemYPPPIRECMgNleVv1ISQEhIA6K8u9GZxvqGwzoRSm6EpwC1Q8qsvj6hkYsEAp55jy
hCAYpDcovqXAik+e7TPd0mceXINXJRP72Ppfjh1l9YmiNVOclcWCTQB82nYDnfFC0ZDBrxg72Ov8
rch6CxlNPG7js8U7c5R1oXgCxS6qvrXPg17Qj6E1ICfVpe90jylPcN+FpdJYm2HUySP8d5bYgesg
KKkV1qwupC+WV/qD7imznvwwL6wfSEDB0GzodVp08+CdgoOh++NuHi/3iobuQ1l2Jlv905m26wnv
7TvrioAk6YJaBZrw++2ZzhXl+TbYTd8Up68QJDe8CdSdARBdheiFzD5ZdfsRowTvF5GvlbyYyyFW
9hJfAQBjrrc13lpvMCfEhEnhzCkM+ZhC6ZjHxyaEB8qnv3SGJ180jWFYsBZORO2CLp4hZO7lgAVW
j2rKqSOAPuS4DPhdSvzWCidf9rUf9qPj05AIBmtWvuZIuX6pduuvj0F9cu7ZN9462h6CgYMbLSu+
Oi788EwXwjtchoy42EyTPoe/g/CJV92XoxRWlDToyX/k1HmCS2yK2Gum6zeG/ln6s+TOmgi0e0qO
IkQPGvPqvyH0KqZufVeQLWB33ugRw19SC61p2pn6pVjVN+iDvhpINYgAaunlA0XsE35XdE/91w63
+OfVbOFXsDE2+nB4azfHJbkUqs8HYO+z3t8uNSBXX+mX/fx9LOmWfR3pBzHMRAP1q0QP+D7CSUMw
YhBCNI9sHIAqANYcdn2FzewPv1jU1RKfiv85GNx64768bNj7urg0PwyOkiYgEgMMKPTzZUr971WO
QC7zVvsydXVXZyWSePZMuxTDeVTOldxCc1zftOlUkEmGXss9PRcvz0oJFd0tXS0AYTHL2Zy0eqjo
DEb4C6eHbeq6dX2o6fbSFdTz72u6FhYRZt6fSvNnPVduqHyxOZ2AVjWdXa7AR+y/F065fgeS748H
9cFYEye0Qqw27zpW5BL7I9Mti3i2ya52EqQRrHIbezv2enE+IBSMdektyTcMRHV07wCWF0Ch19Tf
MQ700rhmWVPSrWzwainmUyGnmB/pMLS1iYePRhXBycAYqilZqCnu4kfYNVdxnlShdxeU1/z5f6GA
b/A25BS8w6FUsgACY3TZXnvUXMzo6vNiYhVDp0opOgX6dNNKlXe3oOHrbYS6hkDuZFfouenKnF4A
h2VKXa69l9d7931pBPsw4pyPCiqP9PSV/yBuEgznTccfKOHjWiCuOClj29o8Lfs+62MsbuUiNa28
MPxEIL2oN5iQiglzRmXpkb97YHrafndOgl1fnEyDrg9vNe2YujnmmyONnjWyzhY5JJ/PLzlAZKJv
A9/wTMRea57NpyxHOsu9iAdnRGPAX/xBFRegUUOY8487tjB+wmET7mw8vHNWPup9h0xkiK7/r1uw
5wBPQ/g+/0skhhCBCeF8SEhIv4Kqv54zN+HPvBq/7rOfs+CW7wd7eI9AEDuLwEOlFhLQvXn6z2+S
0Ij4jD2k3X/oANV0RedZoPLor3WdbPVEJQMvucaIEWi3Q6DKKxDWpHxgNUE78/BIK0Sc3TxLyrZM
UUA5SKGvJJ41DbYJ4fDtqI0HIDgTPbj0CRgbWqRWY/omGdES+aWp90kspaMR8vnTf/X3Y027qBbN
mhEtPTpYOnn6nVwEau6eicycn3EdXBQxkHl7CS/lveUJAWMNi7fn3d6mRqlRdst1k3NpkZoEJjzX
xHSFipxRFnps4v0ePE/TxUDdXRB9ZvWLqyQEaKekemE3iLCjctvp0sCPu/+Jw09zA2k8/nNshv6h
8FF4tsAivvijhocxan0Crr8j5InoPp0DtNCaBMhfAFUU545ifEcgI94KkSvMMBELViWvmjaajK8Q
OwQFau/qLIlWMnQXs6t76aal66zC2o7xqPv+06cVBIifEnOiTjbhYS+sOtoPAbrOVGMns5GRo9wG
js7V0w6MXNme/Kk2zB8mQ8GVxei1kBylH3OVVwP4Xe/JC7s5C9L5iA17YM9cu4x6gmeC5EZ5Mn8i
/ZYd8mdRXaFKdHKIkt0gNHsIFROtcstepjonJ9uPY6S6JP5YCHpw9pU586OJUIy7WO0eDy8NbDew
FQ1Rq5QM3okVbDFrxTeYcxDGoanV6oI8nuGxFJjqBB+ysHXyl4MoLkv8WFCZYtFznb8w3Wr696+j
/2nDVjRIuRaGRVFKln75/OJ9V6SOJN9w4bYdb2hklugyT4GmR7AkJTgZhAZuqnYW4oPfH6jKU01h
XwSwRkeZFyF4cqQObwwehcLCMHeBgC5AqZwRFl5RFoP6lMEzTEpC0ZzgxSnDgjCmNhcGr4S8rU42
asm7NlfGJuVuLg9FFZu3+5gBm13qD7yABfaDPXMdgv3wNYGSE0AMbtI0etqypMiviHv5tT6usq+i
91R6dhAf1oM1TOsPH9L8mKumnLHl0Ma7GWnq3Mqfamr6DZYTEKn9v0Zo4n9ZUh/HoJKhclgvwW3h
tQW+L7GZ6np2LUka99v/6TVVE0yX6fFjHA8aYX49OqqQvdxkF6IAdJ10b5t56FWWFVMDdWjYXJIe
aWwxhxu0zQt+c3d/jCeu0M+uWfez4AUGj8zZfqWV7VFAfxIuUVTC1m/uUcb6OKnALAYpPj1VS73N
m+ajBmr0uv0I3AUC4ZNzozi2lprOiBCaTNj0IZlFj2LAF37a44aktYSmL+qybabFi628P3+Pyc+B
lAbAVKvbN0XIy0XEIXm5+2UX4ItagK2STNIIy8b/BnryVRL5ZF289AlY2ShIO8S24I4sjWhR6/iW
ToI/3EBeb3Tt5Kn2la/oBFfRR/z+lAeD8jwBh0Qi/UjQj8IsJStXq0RtO8dQmHYKF3yu6BjYkmrE
LKGkJK/KogH5vNIK8eDKtPG7s9pZKv7N7KY0t2BilDsTGD9bKRLgLakT+PdCMOuxJd5VS4wrAMo2
FMxUz+3m9ZDZIqZb3H355+mfeLjXRXi/L/0cm3zW+ecfm66kqo2lQmEFa5CdZTiA1MCV662jaQ3c
oId+dtWDOJMrd6ZBtsej1xGwfrZdHm3TRwYAW/TzPrvGAeKs5Jsu/9tPyH1ZzwztPZcksglM6v3S
92QuLIoUyq5TZw5K62o3nI1Jc5JgjXzl8JYhtsdbM1201v/mliNyL3DH3uWFuPvQH38QgN7IHrVw
ZYTvp+jWVH2ykDMl0Mxa8NCODvAoKi9nWY7m28x85Ye0t5LvnRD1pymCdkGmswtcP4FPfe3GYCHa
GHsPBJD3vx26MuqyTdFDLHZ/Q0yw1196sEKLkpMvtugA7VNMa9KUJxIoqLgwrCNIzd7Nme4pjilj
XFWqZxa3EAWyEh5N3gIEF//6s0Zl2ncAavd1YWzy0Dq+RlPXJ16FP3ENkDh5JXWntfzAoRdbM6v6
ayd3U0OgxE9adKnRw8PoSoun0jhRwpUayUY0yxQNeypSIG/2ZauLJXE7nhXwK+Lo8ABngEA4Ktzw
v7Fj16UHq1KTMf5R5SQlNBAKosdp3B4XWmJjjSi9V71TmVXSla0Qum9G3wNMchGiBv/7mtoJmwyn
GYEnoFF84G8yY5Qq56uG5CZeeyRTZ8zCMtJ18atBqWEDG0FbLxsS01fZ5jHM4mrncVDobYhcc3M9
oTQJxJcHk6lp8oPqfZu3Lyk7hShMIqoM5FdfLnjOJUe25LF8lmCYim814R255LQYgdIb6Y7ancEL
is1S3VDTvsZoXNtL2E2S3ZCwvWekfVMVNI1HfouMLBo2vQ610jeJUq8RQ6dZBkHHOpb0KjkqCm97
MhUubQkvNVfp+of0APHf+4888jAyTFrDOHOTof1JokSwfhEKGMyu2nIZR3BVImJAD3uq78Fa8TUn
owZWl25qy88aE3GOtUexLMVv0zsVjUHE5IEJL7/EiYjIBlaxEyoJuxtMizveJq6Cnlr1Tw/anOH3
btbBvWqbSFlWv1VZKvnUx95B1frbN37IW7Le3KWB81Wemo7gm0omI7A3ZaQ4oh3mMsytV7lCYfhW
xblBxsuNp2ImeiBCuuBmSKXxnWw93jGUCbrkSXstB/rV8xBC5tJaP5jteQDSgt2fgIfHEoe0M3uZ
XmMy6qwweoYufzpAQ96GSK6AdckKaVKa13kWis+IQ/uZQyxtvKbo+g+CoRBqdNlaksYwsdxN7dB/
plnr+MxCi+KMonz9RF+Lf3KsIuyfzkItQSmlOEYWcPTXPxCy05VmftjrxF8NCt8Oq9bIPvTHSKQ/
eoFvnxi0N8mdUI9HoI2V7QGCI7vlkSNNIYuxTbTjFMmUI7Dv81RhNfrMw5OqMsbrQwcJxxj3wvba
h09th0pwYdkH5WlJonHJuRDGcfZtVkFO9tcBcktRGtVyHRqPKW3WPOhlJ1CRxT1q3rm7nTuHdaoX
JS3SZn+f9LusJGZDFrs0vUkwYu03wlvWGu4Lr5L79L/o6X5kRfqYFAZvyz0XxWQ1kq6NSLndu7D4
Uwg9IrpKT9QfYsuyhGiyV9PtOAJNGcM9stxR+ksXcyL3SPGKSRl4/XsXUFWui4SUMm1NnPkEfmF2
mDT9U54uhlXtb8cqLB6ZwBLfgdgT7PPFNlxKvEs5CL6SwqLxuUNn5QkUgtwjLghZi8TwbE3TWX4B
yfSAsI95TtQh6m0kh/LlHxCqOO4GclfJcpvqY33il5VgQkP7BLkYD2wTHK8RZkqXUq8nrCCTKlBK
L+e1bPyerXJ4H87S4mCtuUkbtEJOT2gY4LFg8CBK8FR/bk6gWWC5na5obQ4te+9eQhbqoiBs07rS
iu8RkQKgc3cdknhM7hgZmOPoFgOvEv/FmQHpMbU3yfEmJyJC3mGsFTapvqFOTZx1nhPsZe2/oxOz
1M2D49Fs7UncbHZ6e/0o0gK946eMVsGYbOoB3/jLKLFf0D2rhlsfeRbiBR396WlR9QXHV7z+og22
wLB0thgMpS0TMvermjBmkPUPl3n3Q8868avqZxyA5uJRvPAASHvXty4IedETyOtMs7JrtoQc6jFm
2//LfKacx/IuxFwAk01NFbrpCakSjJ327TRGKxXhpfvntTVC6MaCGg7s9DOKpusxorl+LDB1jLdy
mdLb2JFIULscvpy3iCLyOXcFfA9q+wgtxEzGwPJlBmFT5buocW4DO9Jq16ugtduAXqc1hExZLxth
LdvnrkIOHMX80VWka3+fNclFj+HBeH6nsa1Lxkjzw946N6KTIrzWFMhjezNrpPaAsd4uhSt/Do5v
6Xzcr7IdPtsn3sS04cvcRQ/2s7db3zFV6yv3jizVcLCiyLSKFb2wrMjvnS2WguhRjn3KMGrOzgjb
Oajtu1nISPL6Kd2bGUjPoQS/rG/HJDtXVWJm1er89Vu5Pss8MoZQoojZuuqkUlCEhJ/DDQbOxkJ3
Ggfl9rS++kVqLX6YQGbVTSxayDOxW9x7uuAFjZYurUcCtAxHk5fHUd5pXLXB6CynvNdFI20KTLZ3
eHIFRyoTT92uJ+APkMQeroomwYcFDkxlgkHmbordW1RPkre1rwlJbHrWXJ7KDfNIvfKAqVF9s1n8
38RbocQcUcDSiHpnwuMUCbQwe4Aic/TWKDjeEidYZCBuX9u5RcKnuOhwjuUALmk0NtzrxOSQBkDx
Tx9OzYhGGOYsxoOLzaM4B64D7HZ0yFan6QvHZQgO52PQqWjubcnw9NQNKRxcPB/qr2CuUY4Np6g6
QghAVZL5c0xIh+DASQ81xGHcYYO+xFxsbDdJNRrtAWifyLyx3WLHJm1xSxajTQRIH7eXkeklk8N6
2j88OUvFe0WgEMUMCAgS14w4n2zybnWnRA0Y0615RLenrQmiVU3icpTtEPNZ9/x/TiWlzej58Go3
H80HJw50YzvhUaIx8EjgdQtN6CarZ01EGxdN+PKMABW6WXU44FmAJJPcYMlAMT7CjAv3QNHTL9T1
rnoIu6FjdqHvfVGvtphzVjcncBfqyhe1uPaBV+E1M8cUI3e9QqmaRMbg+yeH9u+qqKhEOtqtUCOR
LkoP8AV2/cXyrPlaT5XVaiE1JrjED+t7wLjtixTtPKeCZaDsBpUEHGgDcQig4yNAaXtWimGECJal
JbXLyDsajDcQkHAq1LlVFlJhFXGkcOIWgoU7fUIvtec2S5/dqrCkhc2Kq2NNVtFGyN4x/xstugGg
1kiFaOb91c2aximvRO1bePnejRcf2AR2OMbqI17ynv+MjteTWTQds71AwTjo9gnDa6RKtadafMjk
jtHgEKS9XCl+s05E1UpzFTKROXnKqaDCrO0cb1MT0qITNyvH18Z4Cvfs4lvY93AE09NSB8a4YqHQ
knRgsgQxH8Eeb92E0ivqEBUHm3crV0Ih7hqXOdvd/K3WhNre2aEeQqc9beXyK+UL8s8VOjfT74Gm
mxWqdu4TJbTCj6Qu2KAtVzoGVcZIE2R65QCpJHz5zBQvL5rdxwRqPH3pcgO3nQJj7S1xLn0AB4Mq
ppJgH2XUoIT1QTJr2Qvx+Syp8p47KRLWPRkJ7vKKIj6rb1nm0foUY3OBrsgOlM8qzWr3oBXAC73u
gEYY4a4ZH6kakTbn04TmgP3bID+RiUjFTHo7ti5m7E7btSqury0Y056QgnGbJfzo3O4MDwm73f2u
4o6zGq+ESmk1z9YstONZKsonCixcQoIQdz7AGX3EGfasLzM33kOxhdasoPozwL7L9xTBK20Ct3dj
I9QvngBJusMf2ZV8J8o8BGUZLgol7ylzKm1icaA55KCb3LdXapQCyoTJs5hYTVRf0QVZSLsIHieV
iqkJUpjFJ4cfWh3GxiSxFz3D1CK32d0OCWia/vLobNMfZw28cG2nJoYLm3Q1OkrTVIqzkrC0yMUs
W+ZpUy7rgYwBB9pza+wSNkQh0gfg1F0IX9zdRvAr1bZ9IXeN+MmjJJTVVxDx+tbbA9/ZeU0jYmTM
DZstOiwUUv3PJruQb8uLyfYP8UL/e+RiGsFBs6K0Wi8HpE6VSM52TcnGje534PjzBVhvYKZzvidl
FGIArU+gXPzsbm3hYC2VeFZRrlWAKHVialDyksqfdg1VggPm700VOaHDGo1TN96ssIGCyOMTpteB
GlA8huY5aP/o6/hpF6bI4CqTKtBLIzms0Eaw/robm/7zvuh7YE4TU8comcxuqHjpXyWFXy87SViL
xiwfYGqFPAUWurrSFpa8/cGLdEtaVewIK9J9a6pU1VNfOnaYH6SHBidja3INJ3QW0aPs2VdMgNPk
XxYJUoqV24EZ1NsJRsRv2ITECd3tCG/YgJ2ce/uilKywLj0FDGduQ2d+k0AsEqN734tfUyzdu+yH
WUtxG3gu42rk+Wv4t5zWpfsxEJRIsVLZYKUvGJC2RgTKXbhCEJ9gE9Kn1OUlGZo95cl66MDk3bhz
NaJukrJzOPZL8yhGQNZnMQkhdeKVrleaNdq3nRebA6sPKTwCftqCwCibYjalf7xr8Vc2s+Xo5who
00RZUi45LrW3jpmPBlhNoAxHr3BwmvYYaRHdnwGZVWCufh78eda3IyYN5q2H65tRoQIY28ZoWmxz
Th17PGMS3mdOro6bAiMmdXTXdeL+vnDTZXiI0pxq0ywtS0xbEMh8N7Gi6ylQNwRpXPBIt9O/LCek
le++PeCG5EktTJMeLFdRB0pwfAGmIFy5cLgXE4MsHvo8rOyFtBfxSg1tWGLZE+BYy3XBD9vGX2qb
48EKbsLi4WPfugppR+J7lrt070wastWyykZy+tAMrFc5Y8N4mN6cd7mhA1GvhS/lOfgJnhSntoMV
9r1oRPug28FHjAvlpOt/Q29TsVM2d648fW626eUc0A6479nkQr2zIsKrTY9AjSXO2kCnNqV1N999
Q57q2Y0OFut9w5YzlZMFAS306EaJgFWmDSU7lq6WHeKT04XXfAm5QENSFOocSZ6ogHEwDAZmOZ4q
3ufBJcxX45ZduUS6tJFhJYkvQbYGXpYF38KxVhnwVY/Sz1OpMfrL4w+0lI/6oCXuAzSa0HMVw+t0
wGxC6Grk1nIH8tHrMlA41OQeIsAOCKI6hcDt6DbRlm57yQNTcf+c2baRSwnsr2InbpQ0nHoLTxsr
zqFmWDj/QjOru6QWnqaOvLHJpbmLh9P65BxVL52Kg6u/MU9ZuPsnM7jMejay2q0kuZ+th+2RzyJc
OW2T/GYoZdlYZjAG/NvLWUdBraRVs3t4ErLxDFoVSQkAD8dJ+HRSPrQwmtYHpllB/42m/oVhYmos
DbCyx3vH3cX0+zI0vpGAH4Zo5NKrLtuG4w//dbUNFCVWLt3H2mtWdHW5ygGudIz6T0nwqFPj6ZBk
fojgF0OjrXVuCA1wnhoK7MC8QbG0Afdfi5imwyKnXuZ7BnZ5BPcj88JFlcHM/wRVIIZ7CR4eqna5
crJqZVj2GOgMfx+nq7gMPM12U0VyfjGaLs3FKyle62+F5s8wNpopTrgoj1wFqr+ZwxVEmL6Mxwd/
LkmusnbZr7WhvGGuHWXpUmD27/awDBzVyvtkccVZ5VDFl1Tslk2j89YvyxZOZkFPxq5sk83sxlXk
ov0JqanH14Nr+y+snIzBQ3kVrl4RcfSgj9wjS6WJucRRaXw2/aax8/UhV5Pu4vqitzJevGChi69f
pBEJ2q6+rxQvZfSf20XA6DfoD48/m4V3ofTuT9UqHykiGMBmLPxkyVsyeeuosrmw2Zkd1GrORvlp
4S2x+0IHfzBp28Ykd7I8b6vjLp1MkLLGuPLJ5IYL8C5/S4rAyXsuTRfnUkMQ0GPnPS5O/EyK2hci
qZ1JlIJww7ePu9aA32fznjZMWZHSAV2NbTrHqijeUz7kMpV6Xtqz2ZCWsqv/qKf7tZRNdAOMb/58
JIncMUCfKJrGNyh00xs3y/TY4uiuedjkW4ylNArTBM6OmwZBYDWqVV1qhjR02+82DHk+LOHAZrSe
wpIXxCvN7o/gGKT0zTmlfLOL11u3jZNMP8fBkzWlbMHwspfnwJ2zqb9t71xSNiVHTLpMcEKMODbJ
LcvW7CO0tDpzTooRPHl4REDILA46OuuJAORPsrHxb7mH5uPShllVcQNyPyvZRVQFbfOhNdoZ7L0Q
9QvrWSrhFdG6iYMgSL3n/EVjjoaeoa2XMPDf3ST+1BSiDsUjFUOlC4M1jBsJHo56fQ4kqE7Wubf+
TaguNyLF3dvnmClE5X7Prb+tBhgSctmFYndul++uMZSoXSZZQ5hjeBOuUKhWGses/ikMpWSE6Sq8
94GMHHVUJXngWohLXO6z+UDOIM6D6SLMaiuhPtvRCWdz7Iq84mfYSonBejK4FEbpwVRglYJ1dsVg
KundW3wa0RV8tr5GOpgoMmgY52kUN/+cX050tM6JT09UcmA5adLlUaXNlxrb6VIZ3SWwpBs/kgyz
3Oa2OC9bgWDYVcKdIR2XL0HJQfv/UWZSEge+trNk59dzslrdVVqD8Jv32GD3HXKuKRH1Ly1Qo59z
kJNAyMl6fyT4PDwR067ctq5Vv/PvNgTunIFadz2gYvUQyBEc3K7xpaYRoszK19gAZt5tyBTDQ9yZ
t5UuiK77eaD+6X08oCrD37DbdtF8RaKjEZ6zf0Py1Ps7k4eQAuaf7yWK++Vb3Bos4j70PUyU2gZE
hbtwzXujeLyT1vlP5Wt/s7Pq+5ZKaR9Lbv2MUpUkClsTjUr/J9/tMyYl6flV1wkeb8kPBTMPMFEu
oFwfCA+lwxMke0mjzEvEpHDSWBGzdvYRTLP1L42p9l4jLQapJyOUf9iLfccJdYBzkTn7wqQuL8XE
l2Cxdsx6vd2V6Fvye8dsBI4En7WKPcKQDxIh9cw2XAqxrZbiOhLXdlLD2emT1RwqrBHsq/GC+NQ2
TZUeGT/zCkTlpDKJ7PuQtr2/kzmNZxKiR5pTszHGZAvsHK43V3Mdv2V9PKAxqg8x0YBYfdDgAsbc
EZvJowZc6D/lM1XQuu8VM41cx+0Gjz1He9yT3PhI9XWRJoMlR9BH8YvExcTxbx3udS1ETj6kLWPO
AFcMthZafr8BAD+83j3U6Iego540tGOCFn2u/OyEXiZwc5HE2pyF94HtGSDQiSctA/wblhAYK4s0
53YmdKiCaDB3xEs7QgPlx24u4iUNqjIsvhQgQf2qsOAVSjjR4kpvFXyiJVhAZcw3yH8xZKJI3fng
gGYI5b1HNJCt1gErtUz7TXcLCACn58DpNPvDDwU2JMcEHrga0gcLeI9nzu+L0o3PjwkQjZmP403/
R+rB8IVLLUWCVvAa16VPJOH2rhfpwS5V9mO0Yv5Y2er5GcH23uyflDl6A4U8Fh2L71vGXktyQjSp
nmLzBL0citpx+iCmeZxXlE6J0/rDiogXyaY3n32+P0OengrY+u7oineUx4SqEhDg6rOnkUGT+0mc
SosYZs3gtMYjewh2PuXH+5IBiVrL7dZ3Neh9lF3T0hWQBovdONqE4uipGiE3JeC5q7BgnJQqcOtr
LI25CpwvRaRDncougFAXq0ren7mc5ZJNzB7NtIt6Ehlrf2K0tjFYfFVNUDlQgIIutD07wneF2QJ0
LKCcQfFbXLm74HW1HiyG4tCn19R26/L37UoFiKqlnuWrZgXM/IMDFJulf7qmiT7dMaU8489s1qQN
rWewfTtrMNvA76ob0ruzk/23XDMiddLKPoWSfnidALD+KGd1z5Wzc0ux9E5Zy23cZylMhowOEGWK
6zh3ONVT+ozYy6sIdeA6hg4/QGyPyFT6mP7ZxkX8vS2Mn7WKx4nQ0hZspVC6YitRsERnmuRtjkXD
g3BPWKPWyqqTTSlxshji4mN9GwNLJy0EZONchEN2gq8WoCzgDQA6PDSgjDwsUBVVuwCsSh8RBYfa
CLKywyCC5Q9ipXpQmf0rP9iNlZeHRwWBtmvUalewzQPARjrZ01aKlHELUNsV8JNa9nKL+2wYeuxE
zPNUt2NOoPWeOuvlq+0js35DHES0s3ltRt9OTHcF7Gruh/63nzZVn/bUGEKZ/NcObfXJAzCUB98F
eK+c/TViwz0bhMePPejI9sfMH457YpSDGTvKlLsvmYhINeD0Hnr1yL9Ouet2A8LFCRwL0AWAByPO
4M4tjPYHWFYmNnaXSoJo32Ejn0DpEMYXHE4+3MIyNytAyUh/ZnmGBTG1VDNVtDA93q5xGW0sDZc+
gvlKDNHr4dBVEp6xsYQiOhH4reUOsao+Y9FPxBwJQAA6KfO4f/stybMO56RbnEHOm+kxbOCj4Qzn
xvQNd/RNTmR/um5gnw1GIQ0VYUsGmELk6x93B28ieQp3g+hNUtDz2Vu/NDA4/jqU8Y4RgOJgcOdJ
mPfwDmkWFfsJ0z6gIHmhVmfJQeIAalovckxvV9jY8gbt16C0hqKJuv1UynIHVSqmH8rWOVKx0oPT
iBTzC66elVwYvhQxYbu5Dt4Zah4KWDcCfzNHeYAXEhOXH2ohUo/8KIMllS4AtVmRBeHtbPcY1ugt
DFc/CDlfB5F5IQJIFnkVhfggnktmqFT2tJRyLmJUs8lDxg0dnFXoNB+k/1FGyBBS6Ha5C/q2QOSv
WgepisVsb7Bvhb5oW62CSaYyYo9a/SFCcvsXaMWobDyI9YaZfMlEs4OVWBhMSQMkxgCM/LlV9Mxj
k82WDI/vz36XHunorORJ880rUvMxZp64XvrNtOEa02+7ct2FkNzbFSEDEyVDQ/EzXzC/KA8JFssl
8A1S77hWbZHw5LPNGBHBAQByK4OCMZuRghjAg37C4fGNV674ZMldBY5JMIcF92+jgbFLYPrcLeTp
482tDy/zU3X3Lp0i8P8BppIn/rfloLjeeH8XtMGfpNDhF5b78SclrWCgGuEuKcU41m0osWWnXVFG
dnQSlAysC8KIODKl87TL/eNW7twd39JFzKuqQcDkIeVy7HjV4pP2wV/0x59YCccAiD6DOp8ZGsUf
Go4wTefcte0qm0v08rVYObJ+dLBfDtwZlPhUTvwrm7l1WoOX1OG+q0VuNLo6PF3KYx5X8prgBlNp
HZUhy5/vj5vKxufEdiUAPXldUWtNAwpdgwoMM0dMeAc0ZVgKLwscNYxHYgpPAahXhuTIme59NfY2
s4ktLA7E2UY+rypEXA+qNFmEiRe2lh4jDSt/H5N+VLp1NQD/+1SziqmTX2DKXO84XJTRa1UUMQTE
BGyd1f/FjFePoR3y/rD+IBsuzsQfq7cgWHpStOjs7X/xLOh0HfHGaTiTElY08EhzuQzhDiBx7fOw
QfT4JJmyRMMq1sWHQB5fYOAV9Tkhbo9ECtGYAHBSy86iLKOIIyD2rji5gxGht1etwkPmxyenTYCz
Xmq6HSc35+KUg9vJTY4tzDz0KchPrAlBzII1zLxAatDkdpGRJPmziYZCtXelcchuTH/1YuTThoJ7
f0ZdD1ox1jMXJFFYZFIQFYyHZz8hsLvcdeI7D0QANYRmRT89K3N3KOAP8Jd7Y96RTXjiO+PApl38
RxIn8V5M4+wfc+a4MkbwBEsuqXqTtH2jVvQTOYBTa6oYf4cshW0/mMkppFXndHW2X74Q2Dc2OljZ
gyLQ31M1p5dSkbTvmi+Rr1SQ42oaSRFQ8qDzzlQ97+gQP1/q141X17jvR4VdkZwo9g23xKgQlvM0
3AGJB9r5kXGzXqOHqco0//NS6T4ZtlSBQ8vUzhTcd8AM3dBkn23eQS+7hSlW14p/h5uYAlpGA13j
q7O+04S6Myp+mbmJoG2SDjQ/zUHjFfahgKHCaQdU6LYzZ8/7UD7eRnJCMVCy4vL1BaJHW5ONTlv4
uBXjW/mYtcEC1kcu1QRXiMaSIOMW7H0C94hBcbexUwLLjz2ZNFIlKHD8iMK/ad5EJ/TXb6kbrId1
pOEY/2JCcWJsLBMxZhv6VcFui7YJ0F9zKGNb23L2JFI2Z0fTkgqs/UOGTQlZzx07Cc4pw4ZHg+4x
krw0EYgD+P6qE8VGoGkh9HTGW6oplcRrwtrtSpctPU9cy8TAOe8Zf9XLkfgyELOWNBviANFkFKj1
zVSb8HHUOSdMlVHdSyBR33SEvb90CSFVTQWgfVIwdH+NtAx2rp0ri8w9Nq07lCDkZz5+CMCJlYfZ
6jTQbeu/uWGKZvH/BaNLF0viSZSGWIAHgMaUA/LVK+//cJlmU674vMGAmBCC0qO6AEIP9Ouaq8+j
u3rwUxlBF7HSXAtxoO6fwWXm4vm7d9X7V4vyv5TejMU4X+kDxlo4jMQrjvUEgRfeEH41DPQfKuoU
XHEbEzJSqb3MwPly1m8QT6xHOsfd6MYiTJU6qxyQlbz2rk4RH/Zp5s+pFq8e3k27KiaddXtbs0Jh
ny5ymV7LV6znxPlh/8XrgYa7samye6vRgFHK3rlXRq9FirxvKyz53BaA3WQmy4VR2ijnw46DawgJ
Wc4zPg6BFdX/L0OeCudvWsItz6WngnhFvYx6aCFxxL78trzIeMhbxJsB19UujB1bXKgaxcx5EZh3
wW8DuEhloPSLiN1ovvYeX+mC/Z+ZlZXrWDLFcV7Q9aB8X0TFcJAPJvdHNxO1v4cnqWpjqKL0AFzD
zhjDdFXNdOX61qLUJX8qCfHfKZraDlgqNXHQCMFNElA8+RzrA2dwJUR2gffd5xvrhha2/AwssbK+
FWyxeA9K4kdyJoP/AXJbczOIKMRq/IgHpt0PIIdQYXwLisJ+ZvN7FNdAh3G1xQ2nl/8snhm6gw1O
k4cgsj30cj/D6Lbg+OzM7ocJGDnT1Qo0sYErs+c/KW5GPXRLycskB6xnAoIFq1JLLvXN1AVhsUhl
DJEvt0eWCwvVtRQ5OFcarNIO+OBaO23SqyKWKeBhqcWmTAaPMpzE2PBldrl6VzXl8G8UUtdEKaNg
C5DzRGgSQbnZR+zmG+/iVVtOsW9or6rWetSzyanp2gEG39MgGmtOKuhPsMKVEC2b6iiva+6BAm1z
ijb6MVLhsTEHU+U5A+kkXlh7tgF4qsWR8S5jIuTRxsm47QFdFBccR/isNkJiilRGmZw4N/iX3Urs
hzgvS6twm0cF+WGsoebwfb6j0gQIYZxluHZZQKtPb8ulROsGFLVLSrl8VnYZSHSaRnFag3gzVg7m
Mm1N2i49m8+rJ+wU53r+GS7bFVlbthgMe4QWhjuOl2b3rMSxUB3211K9cyLC4lKr1V7njLqSnGLS
95RI0YnxVJnKfb8c/l23xDtvvnIuQ/NrwtzPrYGq7F5zedIiUbF/9rAmeR5uCSccKtYGzHukW9F6
RUSICthZ6p3SeQzfMsxcu5s2BQfZlPpX+2b98lsgZG305dv9MTEyZgv3tdpxpsR5C6fj5P3eO2Gg
eprpbQe3GFMRKfxhoJBFj525EUCXPqIUV029/p2xC8ZAodQA3pol5Qx7VQNpsbOLCWZ4VPECGuZb
LnnKS4TKaxkazcxhlHwpsUNrXFhbnQ+iMxR2hp3b+poeFUUciCjeJer2WyXYFPf6EAIMa7KXAwyN
3y3kNgu1jnxHE2wNUVX9D/CTlZjJKDLoL9jcH7T4eSSoVZYzWd10ki5gXbzYVLutAbjj6YijzVhS
flQI/083/izwu/mDHVKALIggPl99cyxdg/EmWP7y+PFdo+d5EIgIwQFPFfcUILb4CeeOELjyENaM
SUHAdYCt81FCad874yBdH0GG+OJbx/ClcEhfD4+ZKvnGfoHeSvKO0PUqEU5DheipXz23RQIZZz9C
BRIH+i0LPAFuu4h5IZaCBzWxL5S6Jz2k3ndzXmIu4USenPGbKmQ14QafdQqMZYPdScOfO09+YODY
DOAYpJN8p88r9P2ZW4zOhrHw0WS8mmfYpJQvJZVqy/FPzpDpYP6EifgvG4raLEvwCSql94+pFi4A
11ZWAOL2dfInu8ROS59jutFXNDoguYZNiY9gP4iQSt0R8b+Unok0+eyWp8x4DUGSAXROwku8embZ
7clF6sOUZ51SAA0yDB2Bj7BO7ZMBU4GEIs5dFgfsgfYUO+RmSvKxHx3LurT0v2CSQ0GQ6Y/26iYT
KlAkafSyTDAC4G0xX0ekxrAZmx2wDVrFRuu1TRy4S5JHz7QuReP6r74UHpXh5W9ZVDW75Sd0b9tp
/7CgsdoaNnYogv4xmbPUKBSgQj0xT6eF2DfOTejm7J2qR085aXPr8uafAvF6hiIBLSbwZpEwzSS7
UHBQG1cl1Zz659U+fMS/kbq2pFUL+iZulafjfxVNjVu1q8Cw1h1dqzpoIkdNJ+qlaDW9Q4GB17XR
kz9eXJ6fogV84GOhBWhw7nCbhI9pAdcVukq3X+e77LhbxHRjdC3vs4wVbe1Pl2M+35sccXENUaHX
w3MtQ+8z6/TlY0RWObw45BgpiSH5xWuY9VirGjP1aoSUNajuGiPd3zuaHkwb7ud8LNyITz49t1M4
M0QO2JoajemH/WaieCFjmnv5yKBTdGie+jkCKqg3wsQSGd1H7tL9yeq/mET428mGha3xZbK6SS2y
/W07hT/0iaDavW4bo6LZ6AuOhjy2V6yJM3u52evZCDKlTZ8SnadgX1MnQGkQy2lz0QYJbJUfPbO2
1ktzsPlDAQSLP09eW+o+Xb/lzZg0OMIsoPjwjjUvcvsYbRwVVPlVFjmB5u4rbbpVryJdIvwHg04M
WgdYSEDryIEjYx18dDNFV8/grdhB2KfH6p4NS78wKdlE3VMe6/TashF0XsBmYhRcfcy/gDnRaMO+
kbO5lbr8LlVXp4sOn3YJRhKGw+eL+RI+D+WIUGQ/oMJ2wswCIqO6EGRlMo8JOlT3bLWOsGZ9oZDx
hJWNvEkM74f3rtVIc9v8mEXcdIOX6zulLtl5GyenA0hWuobOVLkxyK/R4Jzegl0ePh5wzKPBXmS6
h94Pqddn/xFEOlOK9ztpoa7EE0vomtrtqKmvDqGZ7+gLYVduztjNL+PYoB36Cyr6IK2u1dVwK/52
JDBtROIThDZPj/tJ6WF5t6q2+I8QiufP94Ji8CmXoM4aIgkDhq033FAILKemv8E3lWb29nQwg6U5
CI7737rOlmxlo43tf9aDouzrbRO+KtNDr2S6L9a3W1g6TRZ41ezQLoi1GGZ7r3lTcWw5XpIcc7nX
kxfNthyGCvTjUKM1vrBpOhh0FAWn3P3gTZmgVILx9xvg1HlzZ3PwKCYZdBhxvVKwNTpOsLtjML0f
aCVXxxL1Uufd0XahCPI8BFlKE5zNc3YF8OIC6QzeGenbLCuxVBIno0tCYKvUisFWmOFNXJ+ydEOc
o6MfZXLX0YyP1pMDT9YBmoa0RMFg0MNWiGqzv7mTgYqXADbEFz1tnQF0u9Y4NCPboC2nasuXJGA7
87xdwv9IauY8ZULgxchNOPp8NCZ9GDFJwwEzpHfwIE3v+VKW1Rn++7bPkU1oKn8Z8x+pg3za2q/0
YF5b/24/hspJk3S8Ll5qTczSrZd/4285K1SOwRICbz5G7jIzXy1bxcq6Xr3TrNpk9YXhklQa/EPd
nCpSTSPPH7sHy+WmiO9cSJpviAiK9o3pbPJ6rqBGgHsXRoJQvFP+3ib2cx1aRdHVEPclapXwxue0
b1O0hgs1BcD3lRbWVlIugtWwgUnB819JkoD1YpzHLdJgQ2UNsPe28mZeBEZbGUDS7VIYUefbog+y
M9Gi+lNOY9tTvRCb6eghS17kT/UTg06tckdd+BlKwHmTFdcNcWotTiNABf1pFahZBbe4sfzWKpFe
l0gqxmcVnWTOqBXq0vsywnphG/20fCKrVs5pAQWMxFJzY2+QEqioWnhRT7vR3CXRode9YO1iAte6
gG3hDEGUywCHyNJ9/6TtSp2LUealLvqo/R3m8NjVXofixzwvMJcX7o8+P0q6IzqGWh282n0JEGYI
4h0ZwASUL7ij/6zNxWlLIPFbtcqDuNeLLkUCe6ddKcgmjG7JBFmGh05E26le4ZkTm+QJsiRDmnzN
xCLstMYFXN/GNzec8go5cWrnXX/zYL7oBNkt5y6x6zqwPw1kiDlIQInajTyZHWFehLZaTrY8uJUJ
6vXl2CVRfW3c1GKsMq//i6Ie1D/gblyE+YmF1Q+YlSNVPEsgYVKah+tcpk6waZogzRSdbNtTZIYF
pxbKkw0KjWSCSgbnmrGrgBod3K0PrN3cMgQzplcygC97wwQHD+TkIQWNEFadO+ridDuI/NnTS+k5
FXc0/9S3aCsYU78J6xSFYoaDhXe4RenYu4gChs3gCZM+2gAXZ24ttGAyVnkabi765pO+Z/ix5dS+
jd90wgg6K5BtndBelrmU/2aWLJ5Udi2oZlQiJ2lrqy/gCvyFGcwjHp0zIbhHCky9Szc/h8LTS+Yf
+rNh5TAEj3JBLOYlPD+95JUKR0l1oBvvLoc3XK3QvDLXjpYr6EteHlhmv/txjYpx6ER9U5FHCWFT
bGSov4fvZsEEH6N0HDN6PrXRkfv9Y86CLXyyZN4hYIMN6qcZ4hI4N3SmPHMEfN7k26csa7TuZMsj
Qf3vB+jelmQBPzN3ts6dQRn+CPqg6jbQA6lR3xgPhV0eQbwJ5wUvwKJAsYOZImowl2lwyVgrZ9Rr
ekOMI9iPxATz+nNCV5taFhdVxHnrfWZFIdGkTXjEh4jMLrfEvZPEgQE3eL/ypSm0a3EX8n3I0jWx
7tamnH0x60ij40xVQzHMHxQXrpjYtVwEM8mjWwEG4Q3EwLBw9R+nChIl7AB4qFoFt3WiJjtsG2yW
j0MyOJa8JUWteMN3Rx/2W8CZIw2TL6hzZ474nYoYlvjBAsp3Mwi5MMJR8/jPl7a+xzvOtXMI4h7M
8JltU6qZ3DYLfJfD7WUSVeMQ7Ae3bRxhnq6lSUhzUGr1sTDpikDEpraxUwekgdGoeg1wau/L0Lh/
iEVbP72uDuLawQR/rDXNmTUDQTXC57llyVvPqZzam3k8dKpLiO5b296rw5+M3/4RzGAmkyeBEi8s
yVOVwxbdXMwqZmjGmNVNj5Tm/RLoPEIqnp9p+M3wTwDqetBCucS2No38YhkV5wXRlwHl6s8l489U
2YnYaPhiIzfQ0kfTVjwPlJjE8e0BVlGfQyKTyccnt/I0dY+VTVbKrPE5OSiOssajWNoJ25xoB+Hv
5EQv7Z5rVhmIMpx9gsZYpk8fzs+VYKIwbSOOxaLmUiS2D4pacYpCPDRC+5XsRbCZb0d+I+PFLiXm
mv9XOzD1tHNbZpjMnRGyGCStqjXuALtGHX7NUdQ17zovs+ppm6tE2kkYfMAkkRJ8M2HeP45UCMxo
MZS3mCsbl6TjZBoNSqBBIMHCE5INNhctAcDzl+AaRkXpmYxgLm5Dm0ih9flZCe0RvVVnW0Iyb+dP
QUUrTUuXtK5ZXDmlZeXoen1/Egp8S8xTl+OFsdwq6RVPBP8poEkqj8DYvgCVpcnUQXYd3SimxGs3
0IYSLEHWxGGwtFT2bY5QyDOTETVJVtWODwkTyPxQsp2mFsAoPexXGgtaMj7CdBodAlvYmjQUhcaW
RT2cXQmgMwFp62xzRG7ir2IDYA0CJYnN87IegOKa9BVPjin1Y5Rxbnrs3a0UONix4fSTn49OTnil
7ZwWmcJmMo6MBC1XpviF9q5Q+3zBdWF01ALxh7OQeI0hxMtNci7OeXj6/RvZQa/3z0Y4SijmUpfb
N18dDI4iyK+4ercMRndSeqGFlx69R0+qXwBsbE3saYY5KNTIDNg2PZORCv3KbgrGSigDxxZsf3J1
FPGwb1jOMSQtAhnBwjGuWrjhb9QJttWZ3boIkWFGMOrnWde0DzCMH5CSLecUCDfOwZYb5e3GvlXV
bfBXx6AT+zPalB5Mo6F6Fx/7RgMB+Eycs1kdwotah5lChq3ErqUi5Sl3kNWE0BC1t/ofHisntgPD
Zfv9rrg5XY/ChS5SmNKf7iJzdV2eCGsE0zvcmf3Rt19DYnJzyFUeUIvT5OICyhjLjFpzu0O0YVNO
GxqLcQ4dKDQ0774qV2UAmn7BHUkG9FNdc9QfiPRRiRkZHhmEfpp+THrEEQXOjPlVVfER9aF8Tg0q
vWcC/jV0rpqLu+kB98F19SASUm2k41UJRRbdu7TvygjTthZajuhIys1REHHhLB84XwnNX2zLEt3Q
TiO+AKs80zmHJC4PczFvstaBgq42vuv/zkRPuD84VNcRL94zzdVCXSI2EAdMTsAF4b/F5s7i6H8Z
fAlCZGo3nJJ7yZ89b4UO0D8E7X4n2dFmLRtXqji3Ex9KFPSu8LCJCvzgx6xSlgMLmEovlM/C2OEz
CTLAjOUou6JCPF++VF1kKJsDumMQ2yr7KRztVgAzimyubfQT/UufNy3Ayw9uQIW/5Xg0idA75D0V
En7B5HSNaVBezOs14xtIdCavSUoZxEoT0mt8v7BfRIz2UDCj9P/sUnfAFQe7UJvIjMnAyaJ2yiJI
trnq2wktx4kzaZHaeJrQX9nMCKyCINjedlW7aUNEw7s+xzbq4MyOwBo7tnQ6XUeL1yGMUk7uSQ5d
pYgQq/pXP34E7AueoDd1KmvcH0tGYBeSMro/WZX4xOaLJGpyqoEXrT1NmZUfbslkYpWU+3aWVakn
KyEAAWtToBttGVLibmWOVSDwH0N1jB2fKuZ6TdFLvfq8fe2WSBUdTyzKlHad4Bk/xeX4ywSdC7X7
pGgmkKVjKqqsvSoXv/C6pUPeQeYQhpJhjj5XhCXywNe8V/Lfz1eOetoRno6YK5yid/fAq8cy1Ka1
OXUoT/8oDt3LK5n6rVBB9l6hpCPKKfNc9u1jXIB5Sgg9soyT82f7IcJ5lOxmjsP9phMkTVXBIoUT
KgwnL+H6MCD/lPdPBpHKU1wv8dHzKEkLiMJYZCiPWKGx1eLtc0rrQZmpu2dZS1ANiYONENpD0tFD
NXkA0KF+hZkHIWVi2rrwO9MPjGeir0D+LRrpplP/pCF9Gk5Fa/qZR+KXa19cjz8Icw/ksv1UJETe
i2oyfk6n7wIzPhKW+URhdmFh1uS9dQZs7bTJ3UtCO0zIUcgwKkmEAw+neAu4bR4L2N5t3Iu3PxRH
8IfJF6ISyW+qjvXU5mxxZUZkd43Ib+UXcQJTpFTJ+YlPCwRw5HU7bOJofc5FiGvJsrZt+dUTJnnR
5rX4P9yQBO/0me1IC9FtOBRuQs4sMDAnSEQ9UcUErP/Iq7YykqMb0uC+Kj1KEnj39/oOSfYHTsf0
6Mq4FzemajCmeSZvXthLnVy1NiDBCpM2xRBixSg33ds0CZeFxe207+9nCB+0QOo0tBc0hf7PR59P
WGbzihR9FnnzKU5psrqa8HDYf5G4dEMZHNwYQwfLyYSaO2BTnudVNGJsCrxLnbURV/likQtFwhaj
U+p51h6sZpNq/wybWyxG3ZtyvsGdqdXcB8+jC3iKbPPC9qQPKjfOKL8+xMdeym2dlhF+hXfra0W6
0GOUmbI+xURWUHP4aj6Rn1XH1b7Rg6iLSJsrxIO2u3p+uvZa/+hvm0xFVQHZfan3DHkDlufZdOC9
v4tD32T+frV9YFAFI3EzylHjqNfyLE/xURRVBrDPL3pfZU0SrCLuCRERJwM0/ZKjIdyi+oxzcJZ6
7Vh3J6yMra/vklguZQRk9bCaABrHqwW2duEvQom190fHn4+73kESPZ95rGvxPWyLngnEgkzlJAIy
od5N4MNBKqEjFRg2PrLxuI5vw338gRI6DipGpw1vZ08/rbN5InnemcFcUMPVrF9SrB510ofiqvFP
qi9qc15sqHd/uX4rxoj/y802uc4uI5H1JWqvQ2GxSTt/mc++hC4aJL7DvWMiigyfziPKGGBV4+VV
v4YU8QrpObsm023tgrtpbZI4ZYNZgAFkF7D7Fr5tisLp8C0t1ohKYVeOnJmaeXI7w0XV+rodWOkS
7o96SSZbjEimiU2jEc5K3TB6uNStRZ4ey/49SZaP5Q2rL2N+7NfrSbSJUoeVjgCeaM8tpeNZTSfE
ZekeG4qH/utVte3QZWQe3qKpM/DqJi5aL6/1zTdgiVgEoN7b9Z8Qkq3sYNCag6Qg48i0Zzh/Zgco
V2GKi5o8eND1s6H/HhkFhONsLlMiHpMRI1fNMO73lyVkD3KLplhdAxS9JWMpRbSMbWuYeb9defGn
hEu+oQp9yQO3og7FDE+MsvCv/sK+CBXP6Nem816WWc9H5fT+HSXsGBYEQYamsmXBv2c/8A4kFFFp
cwCENmoWdeL6YlO9IcRU6XCpEasiEjSLPhjz0gHdDt5W9nGHWoB0Gceo8aG9wFKIlWBuTUPpq11X
E9nGkzGBlfN8de9lf21sYyAHOsEw++LoUYpuUzdHwkcKBWI2sxRMs1DWizlbS7cY1uYUZWSrdw6f
QVA+OAnym+LL0F+q6p/Wy29lhgGGB5625rUyengieb+hxQVXhB/MGIyId6WNYrUshPNnI2EHpppX
29kLUGTHdsmbbYRuLeL0MvaAx3vXyzeNChRDcQkeNghTPfdGV8czGbtwH6PtCRaTP/lAlraVez4s
pwup8kifVmfl2QCajEoigH8VLlwL1a+SyvsItcven2M+Z1M5DsobgmwCZ5vc5ocUQNO6vw37bDrW
vyz67biR5Kc1pBKU+WubLMSxW7djEW46TMxa2FDOyGB7Yy5RY4bSnQ4n74F6TDdIPjJBgh3+ZcZz
9PZ7DERVKLSQhItbYjhHm2EVRvR9s7qAqeNcq4K/9qUcZ0a/PZYv17mTJLnE3RU5Uv1F1x2HMqZL
oZNZSsKN3sWbAmM2LuI9XBE8IzdbCBnz6JZGFW28zLHU28SZNcwFP+WJe2TWv5uFasnjuNTm39qj
bDTBxRGezMZGqL3QT+YnE40/DxahKpUb95lUIsF6AKsS/ptHc2bSw/Jv/AzxoNAnKYbsmFJVvaZP
W3k5or9u9pZg6V01z5Puztpl8vp1KkIRr6vDYKqXzudLcM29XLHXQXcC2TLDsyYm/A082fCXdUi0
9yJzSmMXaGG5tCk6iTEXj6vz/xi/2lK3Ay1WTwSHBFQ2Mwt0TNpxdSa/9+pS3YsPkpPBWXthu/8J
nXp5ucTb8I+H2Q+rabTCRTW/AcZss5swjQ35EvBXU3R6Xk1ZHWxTptgnKpgeW2ruiuQ4UD/QqPGd
7KGLWl3XZr6FnAROw0XOe6C2BlsM8aGp+Xjt4TomTdAzg6EaVQfh0V/BWpPE6vA9dNYvi6fQ+4YT
9rmL6CggE6RiagYrgzGRP7ay2VeMBXoGH7r/Yzsg/vA27n8YH13VXg7EBHFFppREoelNpXFD4zjN
PI0M2ov0py4wHtoRT3oXQ7EprzJ7i3sC71INRxhhSfENDIqeHaR6xxxEiWQo9kZ0BuJQiNT64y5i
fx6Syq2RS5+6wDVVqgSfeEJkUYSxA/Vz+WBJFRHqTfxfpuqvD2N0UHiRovPN0iDII9wouvgxkQu1
7j8hqdNjmIALmRU+NNAyoDRW9G0irvoJyEuk5tcZzlz5Z6imeMbeVs0BjoDdaWU8eaha49HCYq9b
YCexYtMcf7DbZC+sO7+tDeMJgPDxN5p8wpyN3LAYmXKA/8G1Q3p0GPTNyKXMGGl4SGIfWdJudNv0
v70D+JM8URiuu0cXcihjkggGHfzmlxS047AXUktcgufIG9UXFjfiQLlaPATIRsHO/bIIrZoTXsnd
OVZf3pcUZ4hgjCX3QMSmpJQQXkmqupMgvMUEw4BGgXE5vTU9flyna6MYp8+YGVm2c+t/cKqS7dQl
avjDgv1eQZBfxdASOy4lQPfsonTnWkI4Jufp6Yxnu1WXk/eveMNkt3QZM5FRR/dogtFLq6lXSqDe
m0DeNRVOgR5dO6aYXC5mt7jvzcJOyw4GnLXN+BfqkubJYiUNACIXQx5yZHxmHrL4otf3B9lE1KQf
Tv5xugyKrzFIIH10uOZToWCPSJ/7ZNDQYUzw9vYxXU7h+/qLEgoylXhoqNe7iCWUuC+WCKD7qdM8
rKztcJN5ZCFhFaJzDwZaAyugjxkotaQKUbDrpk9XsezcBqXo3mhs6F9oS3vxNN5QN4Cc5/TPBJno
zLZrPs9pW7MLxsTbCI6XhXf1piqizdbXQclRm4ZnC/5gHeG4jxLH2o1+CjaEdjDFz3MY728CxBDx
BlJHjeLF23mZPqyi7Ecc3rOFnEwdzzbFni8XXBDswyEPeyAvtfBrqZccReAXN7kNe1ljqU/H1kpy
DF7/qZYXUEIZpEoqo6DFkjEz8psthwPH67D0jQu5HlRc6myaeZ0epG97CzUuzRKy8aqjW544h9Zu
0yw4B0cLXC3+DB5c5jPR19Ix1NeSIoymbRmq5a+61lM85oZ7+l18yt9E4ZarQTlM8lrcBPyF3v3m
uHQwp+gPEHwSBUlutkRaX1P66blJxF0EHo78DPqMLjL9TrR89gSSPOCwp7+QQBHtgOzGYUDGxPQp
zk7VKQUMOSyarIYZJAru253mR+GDUHwvfKIs6UQ1m1ohV0CeC06bbhGBKRll7l5X2r4+7s6Prb/x
PYzmRgvVdMx3qU4O1OpF7xU1o26FEjLbRufYYRoTCqxo6Ohb8Uw1mfRpmueFV9W6RDnIi4pqUl8K
BFNPNPerj0nSPrEEHO0qXqE3/XF4Bcoav4/hl9QWsUV+sb+HlRin7FjXcKD0zH7vQA7gPwuzlvMT
iObmKWY3ZSyBkbRX32pbd7Uq+H+5OYMCIRMlzFCmcYmSSpA8gzyPuLCV5kPa0/Z0olnGFyZQusO4
7VHqT6W/Edc/C2HjRYW8mYBC3FPRpiCIcTa7o/oZYVdGDBKEdVb0Vj6P1RJwRykQ4ZMhYzD9aPHk
xQcRaf606NiWPEe71+r8WJ2WWQidPezR8P+jzqrMMEmm5cxgsT/R7lD8SrDyG1qbW4pTVhzjBrri
Jyy4JaGLkv2Eo5KbvvE1vq0SJkObEY4nMsfZH64cUgGRBkghceooq92Qw/Ny9I2PVuFDUU+zuMgT
y3w9QLRcLWHg9JME9F8yYA/qqnt57rbsYiS9s6xRwMQKYNX6h4P2g81ncchfe0mOyFh78glvRcvO
DMcm7KRE1yq0Vxspam+QhQ7WuWg0H7ZU/LTmeyt5TJvDRz6cUROy3Ifbw5IPJOZrLMkUNEZ1zioj
Ahr9kbS/R91lfGkflhSq7xOTEmcxpCrAd7dWYwjxYFCumkcRMVCr5iTBnYSq8AbVaUAq2JnMDPKW
H2QvYpeyuaUKWKQUtMzmM906KWBiKil2/RjdfrxXWCrdPmq+uKx3lUIeZzOeqo7ZvNGv5crOi1AF
QwPvXJUTOMtjGnOD7aOKHnCi/0375mHKHSxW7+TlLZDrWmduwXlj0++eUjN8LFjkV0TRjY6i/Uqz
/HPNBWT/5g4NjaFC9rAQWtOC2ZuFAhuYjfXQiU8qwjiYL8WSDTfNTGTSGF+lKoo+CXkZgz91YlBh
bd7xdJMLvZ2MZZHRXvMz4spMXUTujk7jOQLeT9EocFIDOyi9ms2wDJ/cboltWOh63q4uAh3LTLNj
OLii97JLTUaXHENXOaZCoBO6PgdLxJjKSpAyJSaI5UQn5J2V0iULdAKIVIhcd4nzjhzYqpcyxmWZ
t/mcVuzF7nsTbVo7E3mi3Jm0v0ldvnWHCvyZwC+dURAFeDKmt3l5sEgwuEAgdqr3ND5Xc/1SWwKa
v/woJzZciNJydD7xz2AFuysUGgkSmSbdnElI2/mBZXMtIH6PUIJIYjQBjegM3SFZTliuQ0iL/DMc
vgDA0N94WmPj5iUYLcqtAYFWCoxYcAid8rwk7w5NYmv0AAh0Z2xvQQWrzp4od7W1twj0WFAFS7uo
FNlsjvKF2vJIt0akt/WvYyDnm9oFCxB2tUzvRJ8g90dWeWC6VI52Ogo6NuA/A9e+IDZjcLSu5sUe
NZG52aoXDTSqnkrK1ytdXb/w200Fqc3WodpYDst3KjBEw+Qdy/4Bs2L4IGsJ2bwUjnaCWNTQZyXX
UfJrLR6fI5JHvhiuhIWNz7U6/lh6SAARwSR/voxMfpsLrXh7cfnVi54nEi+Si2IgnIHGztWcvPfx
xfrrdHZLK+qWPkeMlIInP1fs1yta8VgOTKxg2YN5eH55Rf60PBEYRfAncdYnDHxx5yIAvlHoyzZo
lvYof905cboO9jKWUU+K5df28En615nzATsH2P52lsfCSelHblLBIvrSZI0R8BTup8HhZthceRbL
AYPWLArcbzruxpmrvPNwZCwYetmyf65RZiCEKbwMPEbvpGyKwbI6fjUP3mOJWExGBCAvcOd3m+Wm
QWusy6AL5ZXGtX1/Wp+rD8nDnFxMDwptd3O01cef8YESfGIwjC9FINptr3Lm1U05CfZn4/udSO3m
o4VLm0VbgaiggSqjHb7BN302axy/uJib19iqNYmmgDuus++FlqWHdDFZMGVfav5BHebckIElWEp+
8ZB4nfMRKlBbp7xXy7T6BtPd9j5XPACuXoOA3vXcnFxTWod1eq3AXAR8cxmqDg/2Me8lWtVm20ms
fXdCSdM7DAbPp3tx28LVEJA7Fw6wMqiGMAm0LDeI8hckosuB63rqbcNlCk0sKYUjf5zh2trzVi76
6qzDbC9YbXfb6vydU0gdBQ2AalCDlodBtI6z0c41wAecE3A/h23y/+jfDI6huMPBtVy/dj8e58b7
/Bt5dQoFgQNF7gnFS2uhuLJ/U9qjkbkQ2F8OqnNf4CgqvxucaLLPtm+8BA3c9FAe1/BoaNnw2jBO
UAieRKyAX2JDo/+X+8tVvEbb9Hnsz7bmSnQi1M+yjGvUtbIH+S2vBReyBc7A5SAfucM34UvI/2oF
SxrJ9KPeu0mo/QWu/DOoLo+fAf8+K7mlFY2St4kZPwM3shqy+znpN3USLkbdOpD2A69N6w1qcB01
zZ0wgHA8wXLXDzABWcBDY3tplV47wUHiyvaRmBxsr0nA0IRf2BYOkSbGJ9e4vBP5oI3Q7B2EeMzR
1SmMJBlnv8mR1ImXLxsjk+iSnTNh0BMd+IPYBNUjmgCU+FVK3cOmbYHh9JBhsBq6HZNUWosUjzxt
HGJF7axx1la1E91UVpaJZWkHTJFyqhbwkU5/NFCdMJ7V9goznULUb/rBOPCv34R+i0+u4+XGru7A
G+7VQiP5KHYiggDRxdif2UXfWkpTC0jNwp9NZBp8RntmAM4gqg2fXPCWQyZ0WeYsY2ieWJaYtxta
4s0aBMYEbfajofZ/FTErnp0BHZiugCEy4O+MneldY1E2oAwVcDEhAULO321t8H50SViMStAYghid
aLYhiwjkg448SxxTTQKdyUMgzwnI0G/5k3f88NY0ESA4COLTTHxKHuGWrWqCCM5zn3OBEoCroU9o
A65bIMkn/GtaCXhF8nv/d766uPw/WS1TNGOO8BrgpIiWPYiL8LqI97qKJ+PQQZPUzAFXYja30VI6
uSkZdHt1JWyznHFvmHPjzxILGlZMphibnDpsG/9Gxl9mfHbLBgbwkVE83U6aztzKd8sN80U3qa61
JeYH7Mm2TxcZN8yAXyjF+yJtRXxV1uWPr41MV2+hANzu6W1LcPEtnxbtCuXtyEQ3Fl0VSmq9jAKl
coub1g/1SeEb384AT0HYWb5fYa+1gcoWD1jGLQGKh2DH3KaNijZGKsj8r44p63O6PwAgurtt2zB3
mhTfvRHqnXkYCOHZ7pe91bbncgvki5UEDg1xi/ffwYYF7Qp/ICkU53zs/VxhsB6d8hzRfBQS/Zmv
D0tcn9jSpxLICyGCGyW8QuPO0T5URQV6TIpKqUtyBvlybvOLJ3lcQN9LJLaGKp+41jdIU0NsabnJ
UoOvpB/qqOZ9Vcmj4yzJ0s0EQSFtGsKYpPnwz3ZIV3fIwIfyvCY6Pvs+74VPTri2/EMdsCaVik3u
HbQ5N4EE6xxIkXECoOgteX1qyeOiSlIBHuLQy/SHN7LRhEaUV+U+6usTiUG9RIVcQiMbuPFwxN4T
B2aKBnmTVZo/xXsgJ+vmX/6Dxy0SaGZIi2Urkj+P6B4tNsOxfkCPfGjjTwn48/kUm78UABMxWT3K
gvuDTqHuZtsmz+4wN/MuFIp4Y/nTV8ss1b/zWrnSge8UYXGlZt0yHVjTbaZYyJSQZ7vsBBXbNImC
lnAfrNqWgB3pCwEpShzYCuVjGOj59ro6R4/bEnBcypbPR9zNHGOAu/e2LIQL1/gAgHX+ftDek/EO
p73byY405gsXFaIYsdGQkMgO8Mqa0jK/pQDcM0az0NT9ZP4bi6I3sNM7+vCnGGInMiuBooDu+8JJ
CHhVCQRYdR/B5SF7W8IBsNNGITxFUgxzGL/WAugL0vBUepvXcCezBzCv8fcLwf3EKjI8r6RHrPvk
AOfnMyJ97CmIZL4x69fO5ICzzB7egnJv7+FHFrl9p4StuLXYMbBEaky+8oseLe6le/k2Ho4ohuTi
O42DUwGUS5fOmxWUvu0totPVZjC4lLxHHo+eZsRZRnRMqEtrVnW1bz1MAWwCe/B90+puT8dYLJNc
COIdvypPMHzan1VqBxchtR7exj+CTkLg7tZZAHU9hdnaEgjRQMzAC9VCAl+QhzGAnyj17t83iz5R
JY1udenja2Z9WshBJ6GYUR74dU04EaxjqDg0m/oz33nIaLFjAH411ynVRML7vPV8tq2CX2dHH6An
7olbI+mIXMT09UJ6vcOJqXG7Ln8sVxBYD67nOL6PPrNjBUDoFlvl4ehAmSUquwfrDrjztC4/xVWv
y0hvtuAlFVOZA4SgJHzA1K7jolhFZBc5eANZFmY30DT1OQ72TUrAnUqvLZSM9LKPwOFefjBbcT9Q
LwpfI3L6hE5B/rDskfK43jjGQLGY/gQayFTfbZGg2uKhJ7lxpeEWB5505GKfSispBGj+CHpG8B30
rRxb13lxai9d5OCCD6uc+VTh5JRk5hFVZlfYkNTXz0CXovhbZrxzWAncRM7yxpbR/o7+d3cP6iL5
MB8rhC0C56V4K4dGl3/NdQaLp5isj+tj6KRqAw9FWNYFreTw7KCBmXyNkRsHmODzxOXxpq6YJE71
XLDfRy9wUbw+g1VpP3mcBSeV8A0mx5TUzXIXx1yG6X9N6Ir+jzzwWxA3PFasI6+lQd6Mvs1YNbb/
T/mdrCW9yLGxDpcpsQENQsYO4p5vCDAv+JDQjQztfgQTpSWicVCVYBm+GOROfFNYy9f65jNfin0W
+SPXjeC9pktegecdWDIGIL7OuCEOPpAdStz0fL+vdgFOjdfVr+y/65+QO6mxdpnxsTrNiUlW22Ti
6VhPpeKXEt18hR8BpwYwMnd7PxtOeIxPqdFxXgk6uH0xbmcqnfQ07VgdiwGdcn2Q+YJD9gBjZo1l
RJhiX+9sx/okF1CLGxnLC3DWlPwYLZYLOgfeOc5Eqv+Y1+l2yNv5033xI0FUKL75NraUVce4gYG4
9+lpDVqzhDOifH4oZt4O1t6U/TR+yIqoNMbZBb4vv5/bfxeK8CzdxgKYnSDEgGFH5dXZ2qJNVWnP
t6atx7BdHFoQstCn3IM1Qzx5xZ52tqch01gkVN5SvP7BTr6HXBabooumd/WMZ7sV4EezoMxxYIq9
pbUMXoiDREqbfG5CsnbS64fli6UKTm3s5z3ivj2VZKMgicVhY3K3+NczeDK6TIoDSOCJXpd+f24M
UAGanpQdS7WH5a8R4aKKtfdLiS3kc32Pmkh5Tnl90VMzDqw4CiHs1q1bkXcXdxCah7EcU8mZmsd2
6Ou9FsQLIMJplrBAl+wyKGSgbJUX/wqZgPyOwKtDxpcgmQUga4SUUW3A7LeeFmh9/jUUik/w1fg5
Qe+aaRLCHdC5UQW5FgS1sumRjusk0XK6moMTSZsFQAxmmSO/wr+DBL3WhzW+ls//q5DVFIqQWG3w
B32eO5Ie2W8u6Eu9Yp1Z9Ql9+DbojehqDfGtcneN6B0s3cTjpb2bcFzhqTCcPuZXsLIUipFcgKOr
CbHcPqRjhLO3VRAzOTVyAWp9MA2+xcl38J3ofRrj/balgszy0yg0ywjIUeKJIITK62LfgrizYqAL
JAox/SkQNBMllO3SetlBXMDo/+r6u3e5r+bFDogl7eN4hc5PWfhzdzg9Yui7qD8guSa/PadVOFKc
cxrzP9EfdkIu6pP1hXW2qcsdwBTIkk2Nok5RoJ2FmEWLAKMHm/3NPkQQeWwwWr75UaHG/sDwjPv3
6AbAv5fmvPys17BDd9uDnuiMd8gechR8vG3pcXHTF1MhYHMa/fN9rXnqSg2hzzoDxjWXUo7BZtyg
3jbi06JCdIUQkfzaITVwPpBDRSeD8PchDIUfXU4iRyUlWogQjyvVPSsywEm5Tr10iRHeSberw2GX
0WPcovs5JnrXD7Jl15S3bnouNgc4ujw4aEkNzkh36cr/270tN+Gl4JFdc7v/JZtfyr4z63BtHwpZ
hVrNPdriEwMfGaWkjXLA4Z1q2P+rvFdmdJB4eKNxQSwe8A1NAoJZdA7wYTbWPE7zcenlXdwz5PNx
nmSTJ6kqtFmcWvcKFhnFsuOj3XgQym2Z8qpVB8FoA5ozh8neAaBi7leWCrN9k04K/v/T8QMhGRWi
zyiy7OntAF2S2SdLHPHChdLeZYZfs6xJsa5Yp0+Lh7mw8sQmkXNEW4steimAHZG4QDTXBHVm7E6n
Zg6bfX84mZBqM4YoTk+nZJvY0sl2tOTddepsSLOEfdjKFKgF5uRl58mzT3tQedogk/iygjIqerui
/nIUvVuKHbs/+UoLSLv9/T77JwRHSWOIcEeudE5AQ+LmQqIKTdfheaAMek2iRynJuA4rfRjb9QqO
J7ni0Hdt1dad5VoOql4W6EzZp9sTXIB1BWUbciNv1a5n4NEOcGrhgH0MLXeyxqb+jnCK9/cgH1Ua
3M7P0A8S/tHqhNVXXjvYknpwB5wrq9O3PYr+AuwVVYw5NmoxcucHyjDRmb43IGlh6IpRZeJYlJKm
jVxsZZctj1qzNvt77Kae+e5GIARhIL9LXzTzaxhaDfh56hEZ6gfMYlTmM60b4ICC2zrmCDGMxRfJ
RU5a/1KzgwenUIwLCU4rvfJYNwS3VpynsVij7Y2bzejLBP9i17veylTdesJu/N1xd7UkYZjildee
W+WuUYrXMygpTUtekKRsZKRwin5WdhRda4C+k7yVZmfifcl2Kyzc8Jq97LOeAEzZ4A5PBjE4rAI8
V9xWyoISTStX+LQPaMS0euFnD+F0z957yep/FjoP9XhAUk9WbA8dmYoEKoTIMwT9yOJUzxN7eQWf
JqxYaUG0ZuYDpG/jF2AniZKHc8+UFIi1eSEm1g5tFslANBstNANzRZkZ9Y4+XzUc4+NHCuNPCK2v
tf7/w4JDMCVd3K6Z2iyh+ioWWSGK+iYQrMsXt8yDjRCx64XjxAIvurh4PEuvlhb3MaykkAOkSGeI
GDgmI+Kz5zrjbibo29L807lJ6TnpSKvKqLeYZ5Gd488kOkq0itVugNOIiMYnBGpGqNWz5tPHG94x
eUPusIvIlKHeZkdibYpDOsRElC7f+DvsPosO1OEmPUena0SwvMr+DjRnOOGC3VnRxC2C8p/rjNQb
Cfh0Qh9LuhwxOdl2tbb1sU2K57bK5mcxDhWvaX8FZx+EfX78vfa+UJmii80R6DGKBk1lmEEvVqHw
AJ3kOOecMNh8lV1Zxb6vqLFiRBrUJYkAAn4L8Xo7bzosgvd2xu6A6WvgbxouHBJNUwn256H+ovw3
hYYWcNINYG5hBrD3VUxKzLILtpQL24br1Vmrdp74fwhW3aqwGNQOxODt2mPLeXib12Kk7boC2E7G
oP0bYc5HTqfWuCOj/jW4CslVPKmDIO5GHkdisOtUNQA7W9o5cy6v/hnETYldHn9g38sxYPAD7YId
Uz+EQD4VekPvZvS8oIpFm+zC/FYxt1fpJW/HKyb5I8DkRuCfkRAmxgIZPiT4c/HR15qX5uzhytRy
+vbD3t3qu6YJl8xVRQC/l61ngfgpKLBADQlMFGo1znNGmD++jun8TMZE0OzH3N0WSqeX+wlu3fik
UZHVTQym2XGt9ugKGwIBGcxMTwfI6WBSlg5+UqwCw3W8upF0bx+abUmYuOdtYk6bXc7DoqLc99yw
aXhlJEGnc25rTEn7G76xoWm0gRJVluAlQ7Ob1e2mVboBHtoccMbiHIK8idMMb7QLg4GTCDLMboWB
cn/0E5Vo99LywxDKX3VVBNXDbCRyLY8xe1LbM+VxpS0eYBAGdFSkSQCqXXnVWYC4TwAIV/Lepg+q
83zvJSAFpk1854U83A04sjZEJ5Be3au/nknkMFC3xNbraR4ABvf0h0zACZe84KkRFaXCUrd2GAFH
04IZHdKrj6xwOCgYPMbw3h6ZLSvNLvUiBPtwRJLYFv3qs0/0bSf7k2Sify3l/xfkuKtquACYxN7t
y13MDJrvlqQMbQdb7jpyqqUpFx1+Y2ObpRHVjlAAJTEZ227EettLtgtHundbAynd9HZijH/XviwE
VbwuRZ1g1ifS3PHVNYDYoPJ7eb8tBfNLponWjHNSWNtoJ2KYW0/AkVd6an2RjrpJQE1ymzMaK22I
kz4WEDDQjV+EGjZbcCurNJut+xacQ/qcWGBFjWPPR8YBjnMu0+nEEhRc1nJy0mzXvzWm/8FR3TjO
CKffvhq7g+MkX5y1GsdwG4sSa8AOIcxcJ68fEUUdo2rlZFfefj2IH1+fUfTgYeUxo71wHY2QrF1y
h/bkI++2qKAXOA0pdQQDNeAvxT0Vz+4UNypJkjSKhvpq2vR6ZhX3cMUA14755oq7tSE2L1OT/sC3
dTToOvuKyZIz7/Jnlo4qNtdI7Gq/yJ1Z7LlrZYxQnY998hxCPqrTpr3FnipATnimOvtQPHT7IeL3
FcIAHPMX/4a5+zSWlLGRRTF+j8wYVMnDhy9xb6wTEbrfL7pmiCwlMIS+suVSkHcF2NpLhbRg60qw
d0QDO1kd6WvPtoU3uFkjVrVETnhAJhdTYoGPjySFhCYaApTyU/xJny/dhn9ok49U0+rfQluSVe4Q
QT8nEStW/Bhd+zmOvsKDD1ORMA9m+aqLMEGbpIliV0hmAfKmoabDjn0OAhjUw+0aG89KZoMALbUp
XUQAuDcmQiK3qVtjl0fj0F7eTFiXbCwqTtOab6eEnEgDJfRsgWKc0/+AszEtD0P2P3p5cv8LdCZx
8D0/ZCzuBnB9fb0/vSNhtX6nKExEgnc4OXmgXo+op4R6bFrbB2MyYL80hi+EP6nne9Ar552PhTh2
VT1FZ6Rqw6auq9BHuz9ZeIpqZc4a1GcrnkFZTF1nXx5/1K1Ly0RYF2hfSiF5Zd+r2mh7ujrtrcVW
1hwDUNIqt/XShMP0CBABP58Hd6mhrQK/TOsbgoubm3zk1te/TNQLbh3YrwJu8rv9MvvPtmE8FiKH
UGTOL419z3rvyzesnfVXumExNMXyw/ePmy/oPrAuP6pDin13AgxwmbWmLD2BhOEv2vQnKU+2FHf6
A0dLw/dpuWesMLFUrSE139jh4PuJFCUK+gzXeKxdMO1Rx4SLohyW+dg2quuobWfmT/AZWM4y4u6n
di/UVmLXMCwDjJnQMiB72os8/NK4D7WZ2drQvlhbmRu1HqaKhIXz/mP+QlGq79B3fTCoWC+swtnz
U5L5LzCMNS5vr9GIbY/HytveGuR6ouclgElKgARJWKwtQiSyf7AdbXhEgfIiUCiKdf/b/sLXRFkm
i/Nat8s56nMbY6wWLocf3BOADWOy2cZRbchY5YSTgNPobW4lw02zDAgJ+plL7fwIOao9fudU6yx0
vTSBJ0Zx5z4CtRypHkJYBDF+0ilZ3JYq3PFZbq6EA97g0zSbKzVdjQegGMIBKgrJiSvvtIZjhcQd
C7d1S6pe6fct64H7WtWy8TpOY1ZPWwHPT/ydd4a/q9YsVEPwT2/ZQ7sKEXqSzyZWrzEyQKhOwwnp
UhJiKANmhg7V1WP28GT5qYhQiJzxPbHJsmsgT9XyMNO6XXfRs35CsiDUTI3HQl7eNi0LHpf4czhQ
c7k09WwIBBolq6qYvxu9GrgwCV2KEbkh8jLLJzMxA9goOa0eFKBdtU4RytFGOv3galcRi4d/SWHQ
PMiv6dTTTq0drS1P6Fp6Uwa8HUUo5OmnVNZckahzs3Byzy3cnlme3GSJR15mDdmc+eVAT2ayjJiv
lx1qcxfgyjgSf9RjWC6sserQgjG2TY1s83SQ+tVxGcbGXCkLIZXDSvf2MPtmyHYJ3IcjTmiscvOy
jBmcYmBCCO8L4pPNHnVeCMKHjoteTBEdRpDCebKEYx+Yt6nthL/qKLSyEFlTsCEyNGVg6KP2LQVH
O+ZYeHAp9DIHDuHN4ygkGW9172dz7dbqyo73wPLIh4tqs2n0jy0YFgYQ80Jz0ac1ETrvBfMZPmjq
/S4Pm8DGgsP4Ow7hR/jhqmzwVQ8PfRJeDKDN3Tt8Dp1HfqM1Qt1Zv00nSqWG8wvQN9YbyI7byZR9
pCF976qzcoyXj3aVe8Q0/SWeCh4aDMq5w1ByL57lsng2aYlCUVnA79VfHDCXeFEo/fBRGcTKvpiq
0ihUCW+4PdIYx9Y/NVT1AsWTc8uNHq2tFJHXSRKIRt/DJihrgnhiLcxx769fYVS02k9riMClc5f8
2/4orbqpKyRt7A3/5lB/fjJxfVxZQtha2qMSNvMDBkSJ7UGVc7LOPvhRi7noFJo7tdakeXQM4hA1
Bs2sHoP+BMevk5Clo/db5mOk6ZBEGqy2iBAGP+P6JLB4gWY6CFWwWvGRNNNIKjz1MFaUCfaqEWyp
exJJbwsat/b0YJ6MqfVZr9nHiRgkjWuc8VfKEv/+FvCY1eL2KV+FYBoVStc9dgbJ2gZkqRcx4r+B
4dAV2golNnHrDrUuRYflFEsNP4Lmv72+pIWnbJDcaRi8BtWrzi6oltnQ/kXeftcFHC18GbqTvPEB
C3ZoD/DUWgSYu1FCb5GjpItXsh/EOjCls0fUNnjaX9oEFmBh2pePWjAO/6TwlwfLGI1JFybwE6Bi
tRrhMLiMxLMDE44e4OYiqOxNssY0az2B0SKzK4mx9q7Ms+/jkYPYv2XRfo3CBtjT1bD0b4jGXGV1
e1F1BDVrmNIdBb1IeK6+T0VlUgmjsRclvNo/fIhsUwdEvivjes3fyqWh59JBXTfp4cpOL/vox2BP
xHndo/LB57bjnv/P107CM5AC9gJ2X/Abw/5gCPP0kLYSbXvCnxMSIi6tSygTVxW9yfw7fLB+uIeY
JNC76jtsP/Tj5+93wCqp3DCTt53PYGuH+qgZsR40b9NgL9N4N8dLALjUpz9kOgbuNbqapTKtwNkj
Id/egu5Z45VKnPK74wGO+t9Z5NeaCz4PJJeU63Vdy51kQ0ZrMUwyAFESpGzKFESJgRDrssBM19ZD
nvh+25zVXmzOYhC1753VLyGQV/Rs6LOGtWjzKnQUlTKQ0fiAXkg5aIJyFRoHloA724GNHtyJxB57
j+8FPJhGMVlKH0fBHTyIgKJUY+C7DvzWJOnZzb/6I+AYyYFV5Wj/3jNDAJvsmg6h2imji6RASgjG
/+RFl5/rvFCOzHLwAkEL4k8sksMsOGgnJ9PrkNrXB3bzSKnnWppWgkJgSkLqspcaG9eluFTrTqJk
5coKRv8D/RTcP32xXs83CQ3/9QC5BScHRd+NaPaWI+JN4195nUIdYG05YXbF9BsZwSqnZIZSe1YN
btSshAnWEpmzln1f73cGeElVajbiQ7YDTz+KwmklM+YzgV0ceXO/OprAB1dv5IEssp/0juWUsFa4
fn9Ftpq+nJI9qhm1RAxQV7OqSMrfyUAhFgjIw9PNxbtz3LvJb90d1tAzQAbdozDjLPDjlD037d4C
ZimRZb3XuZU9Jp862rWLrWXXubhIWYchxYJ/Q/CEKNRKMEvJZUg/AFX76XZnXr2JjO1BPPrjfsXB
tQ/mn7vu5hjW7LYX5RcF/He3exSHSSF1Eo/Qc6n6AtOexGnv42xHwCx7BE84rat3kJmju1seZJTu
+tpic64w+a7sgSzdccMpUEsA981/20Q6wDqNXGZGOT8DbBAt//l621EQ6Ae0KaD9gDJIqoDs28M7
Rdp5wbNSialJ3TG1fwVSukaelnE4S/YQCGbH3JtirUIuaKww0k+BhB1YPYeUjno9JNtky2GncPMH
EqlBj2aVXlWns2olHTU+wRzpEokj0oNTQZ8QDscrPrCTYpKeNCJP/byfCLJNAhHF/JsWBLCtJO6M
wWWpDMLkPTuXq9BzG+VvtflHaBxci2135593zt6X2i+CRVbYPH9bypwCRenVZC4TYf+OEWUlfn4A
Bz6N0WHmziIFu08DuXLVz8Lm9NA8aXwa6tugWYMJ3vmH1h1kdfRqMAGzzzRLa6xXWt7Vk9ZaqSWU
kmsQ89gl1bvKDqzv6Rqncja3/FmxOOPJcEeA4kSmyLZ8UFiDDc/apSgdpjIZR7G0qFUiIi0X4tst
TmBE9yL0Rbwx9WumO5YISse4q8QVjkD7DbfWUMd01An3A+6rjuQg75XReZ8WSfSOT1h/tKuaSf7o
8u1PObmMb81bYuceuGCV7M9oDmDrqF7sCci8oBXKcQbzjoAehpPvQQaiZU8Uv2Dya4vlz90D5plX
87ZqDPP9zounC97RB83AqzWEx7r8NdBN3r2NDAgFI0DYm8dbQn16Dfr0lFVnx3VT26dBuwRdx6P8
svaVVpTg7mfVcaWi3FaFzLSI4dT5Muf9Wx0g3HXw3QThJWe65XtGnSGP6sMW2s7OfZVwjWFLI77+
Op74HIEkffSqFR/W3Tn4p2suaS5/XNNoKsth8RxHe/66AXTIPXgp1n7GrYD+SvB42YALD6a76ice
YpopwFknrQmGSGDmeFDB9GAs5aJZqxbr3Br9JmjbWEFrWV6ytMnpauZBaqeFJYUgv6S6tdHrPOkw
afFvuDoe4sZdu9tMkf6Qy0AiWzkVeYIhLj1H0DPzRv2mYvqCa6d5Jq8B8puYLx6VizVolzLPhk+W
TA0qtBmTfHzRNLbID3hrYV7yik5QeECQssNTI24fktXNHYNfZDAhvFGsFg4UML9aUiI3n/FVqDxp
LPVNDa8rGdV3l634r5YwxiIxhVSeWn6JmcbQvMUrITQco9/IN0bMWStBSqbWB0LuizwlScGrb25U
J26jWfFjJR+K0ahtY8EkCDhkMC/Cb41iPLG+LkczcmUWZ6K3l4eUwkleDI65hWkkwlz9PKgK0FU0
8++AiFIOBxP+z3wEnzd5bml1F8PZQPMBoRQKDyxXkOdAHW/kkZDWvqJiqfftIH0jl4u2zAa7HP4y
8X8mhXG28BY6ooyF7Q5cPp9MV5RdSKRvxtoDnl2btTdA97AkGoL4p3TkJISDN5d4ff8g/c98PmY4
iBONXaMrLLL0O4ubqKSgdwWd0WrCs2QhuPxo8bj9Y73uy1pOCSVGB69HeN1LCb0d3i98cTcGAMoO
20wxWurJSKaQq5jA5gRnclJCBwEXY118m1I//BCLoBzhtXOKz1DbC6+9wZnk7B9itLT6vN76QUxJ
IOfQex+6EfpYTI5mIjiBO6+0eAM3EYixfGsxv1ZY++MuncIfqC+JwuD9PN5pd8EzJleEh2oDcGx0
ODIPLfMn7DYxneVP+SpNTwFH3XT468kN+RnrVVs6isIiaq4H6Uxqkd/kUvB1XOgipxOsn+qu855n
x+/875GvlDpuveihya1YX9rf8Pic8AGp3LALS4xxspVA6d9+YAW4bmJKgkM8qOu4QTqqP+aBVJcZ
8jAkS7LsXryauXlbfTzK3Di85jROhx+OlmNqrs8dljOm6RIerAiHEXk/Q59g89uuoattoIgPl434
FVq/4WtoftJxfohfBNvtN50QCa9/kiTaeg2b1QQjzbaVLzgwK3WDGTaAoevp4F4wdEoHs9B5CbKO
fIvALUryO8sWvH9d/H3uTtmcmqYN4Sfk7ciH0Fcox8cY/EeBThcyEaPC0g19bDzf3sN+VihGu8iW
MfS4opWYONbTp5x5Fm3L6Ddh5TDRTuCfkaCzB3oL4e9jyJeqG44Tc1YmIEq2TSLvxIrXTSvNCRp7
Da+sf6H5XxNj9Ud7SVXT34XGFyskhIBhh5TUNGAe8hqOFNmqzDMXHrSut8ghGCsbHzfiOa5SRWgE
yQ41uh9GiyIzyvgsliaFX8BtZnNTTb68zuY3j+AQaLzXzhdhpZf3dYUcA/LJ8AUdmWBz2KEPm9me
iDfvvhYupEnLOxWGhGi3y3GtIIKsGG7M31xUoAEi88g2Jlpo2xnn9b7iee368Wa8i7nqga95K1UC
+9AjhPfidvgBN9jgVwxXMM3ziO+GubbHG9g9lz0/uw/+ts//9jQwSD6zHxhKGrY5e7u3uZrSuYwV
sd1hQDXCuSqmWurrD2oqGHpE+JGuG829WUgvHLJAs/Pv+HhwkwQ52SgVCpUbdQ8zz6o8Y+EK2X+4
2mrXJXpcz2EI9BxawG8epAPaYh2/2iHEnq1fHkx1ty4ytC6iPC3MLx+Z/5N+I+vZLQkpdZWjjPIB
24prBtpll76glntVVdC1fHl9C0j+72AkPEmKHQQPto4n0rU+yKSlfL7sMpxH3ljoAsamZy7KAZH2
0zhgMNMT9eADmPVT+bo77WCW/QmGW1zY0iLk/lZb0/gvrodmvGkKdAiHKXjLtaxp//tY+iI4wSsq
ut8Bo2HZDORmaeZTToXdi6snZHBIrFAeX90kAvi8D39BiAvd1KKfEvsSS19jmbprIop9mNf1+h16
GrVje++ZcJKQ66V7cH1Bktp3kHYobVpqjarfRK1XAG38Va+cniiRLBhdhErCAYrCW/Mw0GFF6cbk
1OoMFkZwTbIunNAYubkjy7k9tXF6yyHx7d06g4fSouGKZyUU81qCq8bYhVBrjFv9q8eIVfK6J1bl
MLsW7xshsOFPjrqlvp1bxMGVLAGQeaYMCOobjc6kEuoF2Gd4ILc0AbgYPQXzLJTKLnpiCKcDOD/6
wHvvgEzaAcjWIsEhPG5QKiwKkAnVUprsIYeMKFfsZsshscOwmPzYwPRENaK8EF+O/cJS1B+zoD0y
O34XSY+R+gafV7lo4k3et2LzmgHEU5VwwLbHFjzA168yybYpn0ccNxbGN3SjSW1ATOQMoPghsAEE
CN9Iv/gy9ZWPccfi83NuVEnJsvOXwgmpyeYALEVJUdpVflCUErSf3I9cgcn0muWbC9tSgNJt6tzN
BHanahzy5qNT/PzwbUIembrQmOLQeH8PSrorDGWit/eFKNyooVlsPBo3GjnPLEXVtA9WCIWw7iI6
Ku8noelk9ALpQ5wMYyrlN336Wozr1yudxynJMj2SxA850wMjyW8ONwLKXAhI2I+DK7G8B2LsadIJ
exyn0LnDPO/enq54EbccEXXqjZCzM6r5Xek9RZl6OSeBYAPvTGiaWAh5cpSCJEIhTZ0sovD4Fizb
fTFBaaSzsoyfzcz/wasMjz6aUQRAWpRw41W3qkYutosl1iGtGaWLmkPF3rDibfcA7avsnvxfxwpY
KDx37xEhyTktSjy38VB3+E1YWebmvz6Dv0HauGBNp3/UocdYOM13L2mAIRm5pkGyr9+acSg9pssy
0+bm7Q+ZOUY9v+uA6XbwScM0DUmXf3oJ8XdLTfQL0wqxXaC/MaecOZPRk+BM6Q0EPod/6TTbmc6L
uj7tW1tK2eCfUILAWWXWFu9x9DWGZ5g+AQXrHPNiSWUBETVlALqJczupg6m5nVFFrS8+tqUhr6g3
yOvq0iYv0UIVRl0/syjDPWp48koZzETKrFHT59gtGO38wwXQwu6O3/+f2mdmZZt75Z/Qt2oM/CpP
f6C/mwwyeHLNhGn3MicF42toHnmF2AtLtY92nxE9XUl4ujdRYNIPZ/fS5dU3aUjtWDcbW7VvvYBw
/s59mJBrcja9cNmvtQWKeu0YIlcIF9sDln3ZM9dDV+zdo5E9Vk7vsLViYdnvdd5mImMWg2zT7+ht
fxvNR4yH7jwx14mj+4Llu5SHzNCqxHLE7EujCdbmmfMyZWntA7XWKAzaqjrJXm+EteKThFSM+KGn
IHccgGhdBlA+25k8Kq4nyXN6e4mmISCGvvaGs4kg63V+BhdOFmE8GUiIxrNRuzwsbssr+apDole5
SGLBLi6zHhOy189d48FNPZKRnsXtEvZ+nSEh17qLoy3UiKPXxvmKGGSskHhoTPH/rC35vGfMMSvQ
R7jLStXE/Gvaw2OB83jAxmGnyxjEV4rxhR24xpHJlCU5TUF0gS1MtvYWvtZPvPpxumCgO2Sl4Pmo
trv21TeFP7Eg6PbxljmSVwSQ8lSxIAYHbk5LmZ6AetUA4ZpE9rSk/Amghqi646aVRIVm4lg81niN
HQ1UJPZwZc882A/3be12xZwcrCs6LEHbfiFmlVycFTNNbBalVCmOpNTDMgg4XSExPfjgG2x8lB4m
v4iCzHuPUaHduaeHtumJQ1WxIrfqBE0bYTcjppIj+kvjzu5+ePij6B8ZSWACOCH+OjPxU3e/Bq9U
PhC8D3l81egTqcg6IxVyNk2HukVSy8R5fLNeJD+BfM/KqinQE4LPzk2mqoxiEnaM1wxNwoCLUQJ4
hRs9UxKOy+2rQLVokRu0auwhwoUrmK3mrM2I0+ReNk5eKdKQSfBjE6uP/oUCuZbYlMQjvJzOrxlA
Y8VAuJsZ9dZyVyy6UqaluypC/Ah3DJKizzafQB7j0L7dT/FDQM/IxuWvpywy963fGCF7yBo0I5v8
3j4QeRVN2Rcfl8tdoAeMl+UA83Df5k9ccVSHWEg07HmN+kdYprNuJGOgK21Zb0DtXeUKYPcuip5X
wzeZS70aTO2mjZClMq/JruSN/97kYg+8zXss6HQmY1vzKVYPqeBRXOQ37199Fn81/P5hEBpuWyqE
Bt3fsfYVD2s6Bh/0OPzCm/1i1AIdSNjNlAN0K04gSengA/bWEfQT7KddMPLrdgvkUwhLZVJgouYg
PvzdbcA4xcNRRyR5qzJQhZbzxEiF5VP/HeknOM8k/pyzsGmMC/aflg1DyEzCRfWnwnM2JYp1AXGu
mwyr8RQ6RqOpsE0bGLaAaK3Zf9tngpe3UiuMBkBCiYSnMrYl1GGLGCr6Q+hFEpLCYNF5iXy/MpzA
3S2OYqqpSG8PbCWZ/ZJ5Wgbmr9Eh/fDelNzeE2Dmfyjuy7oBkax0w85PTasEcNiGWolNUV2AGC/7
xiDCzZHY91O6kU9sVGIco3d4K6BcuvPxgnne7CHqIoCyiAX29XdRUaqGoDhpd7GbSH70FMcaROkd
tLx+7be6BOPSaSpiybnoscDyHiEoUaeRY8Ykm5WMFYV1XZZVbGDJ9MA8Pshh1TVqPRqvSTXE4fp5
RWJ2KVdAtDbOQW0OSe1gBWsIiNEoFrOebnUyq/VkQiOOSiA2dElai7WRlRrpIB81gnG7gI8Qo+A+
BDigF6/KuMgtdFWHjVSJIdOgfFo1Eog+susPa2BFWl4RP3MmYcPmxRIYWv/wLrLphubcTKVKbRVm
KNELe0FhfCRj4F4rOHO4GVP4jcUZl7J5qMGPfuRkCckakp8m79NadNzu/gnHSgxFSe/QnTqFtDZ3
TDZlBjb90MK+m8tC4hyNUG1M+1mtDYuBom2u0R7BRa6RD8Ksyv6OC61IyGdAmVbLKNer78rcSLaX
onmK5l0WL2BZdvzZ1sKZAkqCLDn1QwqNSmwJdL1Lum3FHJKQldxlTMIUhzkf7XkPfowaABvDGWuC
WUwroxnrQOi16i0brEUS4Yh8+yUydwPy3GSIh538wMWqGkd14t6lrAw2SL0KHWEAC2VhdLUV3Vp+
Xc/8IaO5rjGQ+/IsDNXQ1B7IRYm3UU1aN/cKm6lIyBubgetqFsds+zYigaUaxtE1Bj7PSTebAC94
nyeOY+hRF3hvmEtLqCRJCu3VH/8CWsYiu40UP/kerIVio5tDond2Xeo4cD/ZsSWUfZWC0gn2T8Lp
OFmkAY6HB9W/sfZHkxBHCYXvHaOVU0H7a41WnII4tZ6LhNegdmPxA7UGQH7JlPp19IWQMRAQPT7A
TEjkTherPvpjQO1Ty4ytQ1XtrlqhIyvTdldG96anhzm70W2Qe3xclNsW7HqcoZlBmiUghaRY2jOh
RvWNrrPycFkU+3dKJRsQxYbleJrzXm/saUW+KK6vJhmy673K7I3ko5qM+kTR09GoPk1Wdaz963tS
THHvm0jLsK7cgFIg5sCiMMdVyjDXIrROYXCLT/a8Kq7ouXOG3pEKCBXM/fqOQHpeBwLwjj/na4Y+
DT7SvHMPSRHY68xknnSZjZhO6X6L9D/Lw50XymwsKmGvKpg8hwMhwH1ovN8DVWmUfVcLY8RV5fPu
cvYrJ8G9XNy2d7u95sznubRil751Cp9pDSwVZ8JW/oOGxA4zkJB8iQ8eL6h5uwbhvB4u4auZ4NJX
1CPX1Ta1AtTIKhZUKloT5YjwKsNU2svZKlolI1K/g9yI5Azjfq6jUKz0VZ1rzK1rFtcRU95UXR13
bSVs0QDQtTkcwb2U6bmVrQDindiNJCJSVB01lkn7uVxnbFkwlucFZ4gJDKzhpKc4rmtfQ5tvLK87
c/pXijgEDoDb+V8jWAx3hvnFNXAL2PrMqiImcKRU9aEs8NvMzaaFdIESPU43ZPYLhmgibKNHTyRP
dw9BUv07GidQsWY5Jfz9BR1zlrdPdOyii97Z3U50q41ZCQzQBUZLMbSp4T2pzluN37YRGkXuIgvk
CdHSYUR1w6YAF9NpD2V6WFskVZw2U3TBMYZPPJo+lOZKXbtBFYiSuxEXmV/O1JreTfwY39qV8d5+
zG+SLmAcj/tw9eQS7fpcdQUKwtpvUS4yO56tsNObxnq/T99zU0ew04gN7cfTr8cAzYwAmZTcQyB9
Wp/J1Fa5BzKejIPZLdrtvjofqW7QOEX88IeSEJTabmLMksBHo9CY23hvoI4670G+PdVMc61TV7mu
t2+qfCoOrbFiqg7G/jwFGIB5Sx2pUTUqfa2UpJ/fJ6lnDzoY/+TboF32ovWfEHC31GoJL1EqmW+5
aWMq41HFe7vQq/sUvx26qPvSPXxGUgJbi0vaVN2axpvm+nz010BhG7dDQKIL/22Nis8rqb0qcBv8
VgVImfuY2RDDrQHvF8k3Wshklu472cSq8AF16izb0g+6dX8G/A/tl9pdehzkkF2WJrJJNzFMwUSy
Z6gf5jS+r4AW4q/jFvjRK30zyYwIWahHru0vC+VfdsPgmUw6CybX/uwcCkqfbSPqC34dmKHD6lpK
SsyFZSG1z5x6/J4QyWbB6GO9GrTykNXnI4LX50vbdR465MAYMgAc0PW+s1wd7KCMt6VYaIcQwlNB
Nh/oSXczkU75rcP0Ng6UyaS6dD+kv1IrX/4ym5lgO0Mq90fn8RMaIMHrh02KTOPin/UqcV/BLwb7
SGbJTEicfVwda/665scUTP+PomIgN4XDksEmd1lJ7QPPKRauOib4MPQJ2ADZcaCfbT3rfMYDqLuV
YuLS1AaWoMimrbe1t+SSfyjzlBnbD0xSadQ0HDe8Gy3yQ5iamTurznixXKXH+gOGX1kqVUOM6TIV
89feDfSSx0qfujK6lFBwmooJHDpdlhnr61u5N9nROjNI7Vj+zwhsQ+LYW133wuAYEUxfC21OY8E3
pEOJYeX3YpTIsnsZ/Sn0Ow9q9dIsdvL4W96BleBwE3G0p3WLyGYjgBRdV19LWYARQQQRkYxPOyBo
NcTlh5MOzHqcw0cgKpTXur5F3q5Tx1/SwIhwNTWoMOIv+XFjsovcGwSkfZTRHsb0STi2fOk5Pkpa
UdgDn061fUWEG5rTPv2Pi/IHzPXVGcGEHXSQaiJK4lhk1RNYfoLv7gSRPiaXXPeZo44PWZSseUjk
4pJTAUaZtvC8hR7/PchbsIG/8jZV/7bz6JkQ7Q6yy31lrsHXOhNFino9tLnleBZJjPERTW8M/Myh
DC/UlCjPwoWe/VdE0rizjYYVkEswn5CFXuvIzSnuhAD+yngs0e0NUK1lh2Cu8CS5rNO7E0J1JNZq
gnnS4OheJv36ODWV/H1PP0LJM4/x3BWdTNpewMjPAz93n+XoW02ZsTz+foYV8ur7ZQgOwAkNgMmn
wXv9CQvFIkyOTEDdeUMQw0UfxhWz+xBs4m2ffD6p2XARKB7E+osVd/WsQgXhYxOm8cEqn2z87tGk
LZ2X4rZPFtq9oXX7FV1wQwmnc0znfOzef9GA3xuuSebp5O3rmHho9+mfj5JNyKXlQBizcYAn2SQE
bPyWokHR5vlkdQMwmP1kWAYlf5qokDnir2lPWNIVu3sUSYqNNaqlGULrCau2/Eec55l5n1GwF3bf
Yb9aCEOWA5DRtLdqFNgdRctMIcFHxyOitXraVs8Bl9Xe4j+rlW/sakBPV90oQ8cVf0o35nLQF9kN
66Tuzrtcfu697MVteMVKcBas3ZTYte9ua8ryzbZ0w3sIMZ8IHjpjfVIZtidHFNX1tJhohcAcCRdj
vwF+zjD/6dgo55cZoNtoPxjMhrZ6+T83ArBK/UYPyX+Y+hTIrF1B80T2x63aeP7Rj5ENp7nDono1
Bf88Ly5cPgWuT6aR3bSsvS2VlB0Ay4Du7iHl3gB7PVSRfuwOPIsZo+P1K24UmyZdVgq6Mtad1RnG
EUUySbapAZJpfYzHdk9NJ8dU9fbdIjeU+JVM2totfpWMBY4zjfqLomOIC9XInObLBkoQ5W7qfpwo
W2U3/h2hnlK3COtSch+mH0VdsIfA80WkSdKFtXebZcqnxGucgNWIMu97Zq5tr1MmNomtLTOekkfr
pcyIyeygDJJ+RUwfV4gk7NNObJj84CGqasd5c0AGoJytttLQQRYj97vFyvQ3750uuNu6LultdMQ4
tl4WHtLsnysf7jyTfjuCmUGHOB3M57yGei/8C3eHMZaGabC+/vCMl1pJ9+pXW66iNk3qLiya3Gss
qH8dtw2wIOYRRZNAuD5p31gwV84i55q6RCXZmBOjwqtTFIEXn/w/SCChROaaCRVYjfBkqZ6JwS2U
xma72dRL1h7rF1hufkCF3EkdLALj4ByrYlQmM9c0tZCUHoVlrjGKg/n+TOmBfbyhS68naUvDehz8
rwnMDGSNG/pH2Gi4FXyBoFgz1A4rXInu5oG7jtBtBKZkKvMAtUC5MhM2afLKuZ8umxNI1CxYSbfd
MAM1uLqs6LSmWV4ENx/WbjkfZQJl96/ufYJ13E6aPgmn4oZ16VYl8HL3JU5+486nypD5ns0yzsEm
9T1FQUuj9+J8akJDHA8Ts/rhcpnxceb2OZ+TFq4UEV1UkWUIm+GCP0cFzf8A4ub5I+CYA6jxV+Ks
IU1UnCearq0xZAK6SWhiBs/ltjUX/Ac/oQ497t73oafmMieb9fWI3O6cHX1+nZpKRwQUtG1e2VKz
oKhcYgyYeGn7TzvD8KuE8bLjgaj7tyBM/Sd2U9dRtfUiov5q6qvLGnw8YJuvgfbqMKJZXlWVJBIB
7GJRtflfQs1Nr2tVEAylU0QnXKYubwxW+sjGg9/j8NOrDU6Uc5x4r3ZSuy21ts90PrxDS6Ug87C4
9WmfEs81lLMNAXXrYgbpA4ZoWVusEOrYzZNT1vAOICJtxOuRc5Qcn40jpezenTtAb9PvBtu3SkU4
MuAKi9GEjEDvbuhoQUp4QYlyJ6PxmuqKrnqeBm7gGHl6P5k3b24AH4rje9zGBeKRWawIiC40W+vQ
lDuiB4PgEzAKCj608jfcKq43IIcdB98ZpObTm7EVCy8FljuJal/U0R/pE0IPwHQJQrDZ8cTRsLRb
87RLMw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 95536)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztB/h+4PvAs/N0XI0cN9OT8nV3gs0Dpd/RXDA4Vc3dmwziA
NwElhjRY3VJxDTskfz+mxWNFaf1+mPePrYVqlwPTMBAxpvGimC8dYYQqLJKeeN1ZgTT7hwUkM2z1
Qy84CcCZcArvoNTfBy0dkWCCscLO7FYjYdrltlJMSy8CDdjskSxeftCs1jkCE/tStmrqLGxjbT6f
C92mpUd5YCmVlDJSoyG1Rmk3H90KWuHUMBc4d/nTIqIeHq74s/5YZbg6Itq+omXbAlchsha/ae76
9FWmmOPV5pGgbO9pUb/MAoiGnE0LV3UxmCzxLGMR5z068+xQRaJogr8gIRx4YzXucEDuMm6kq+U/
DJ8q3+UroFofr/QazQtIkbprz4hnKB1pQ9WCRHlWqYPmrTOztTQ4ZG+pAcx0IYfnFhwKTspFW+7y
GVx0kYGoMrgq7RbxX18WgYUZLMUFfRe6xSzxKiK5kNCdSzOH1JhyEU9M4B2sCcF5xcT7K2tFVZhx
cOoGlhAsPEMuJPF65qYCcRfu6UC7PJuefitD/S7Rr62kMcVw6pREvkYzRs+qsbgNnfPabgzwOYLp
olR7zI8hlqAGIZzAnxQDewB8HIRF0Cgw+b9popHU1CVbEfrPyAP2H9rTagex/AtB726oU3NS/Hto
hL3uC69KGFYAENJTVq04Ff518xRZvbDhZk4t7/Zpna6SOSIzrODGUJSP0FvZZ09QlakBg3Wo50tY
pgmp4DoT7CrqwvHOwtpgiLSWvTFKDLrISVTMjwWznwzIhQ773VhYwUgBwfVumnYIA8G6jaBfBGLn
337ecvtYSoD2WCjY57N+HiWBgdUQDQ3NSmVXDdKaQQjU+G8lATwv+bAb0d2har2upRJoeMobJ656
sfolUjfmew0LyjHzcPgiiMXxmQ//k5PhQRSAt8ggHr1+QYtC5Fh8GgB8scvBnTUM1XAO6R+HNs1L
U27gBJbGILSvUpTBZUXNkyoi8+s03L5a+vlwiEGgNBCUxq83tbJM454XJo07BkuS08KsFVnKwFol
BUxHZ12vFrTlJEeYdgyh64SsThJH99ZA6uEJZTSV37DhOLcIz86Z/+PfhZiByqnY0gn+wYCvOaR9
ocdEJsAWit/14k2h20xNDsh7vHErwyFqka7Ply4vS69D1gzEs/cwndFSR1Rm4eG7Zx13Pb2eR91A
vsj2o/4d7k6a8tH+bI8oDZQ/Qik/iGzOxZd3OZ9GvU8W+nKFx374cVoWAVRDAULUwyeFSZ8E+i4q
dROg4VnjRV1scMxi2bcOCuRJbX6vzKu9ao2v6me0KWbJrYk6Pb9VqAXmSAuxX1soQOyX8RLsDiWu
87+V9QkKz3gnZoSnwvxHt1paDTyWjfL4QMWA7yN1HbAvNPVY1XzuiTaKKEsyf9tvN3B/JY124zWT
CwibACdVqWqVFnC6vA4TidGx3yPOC9UhqDqcnqK5yfS7XC/KBwTP61QDQmo+8oWydyiuC+/NKVvt
xxNgeNW5WZL+UPd4qQ4ztuHmm9pfbJYKiuOJ4PkE6fuWkYPIhlX5QNKRqmLlF3jI6g6q2jl/S9KF
osulJvpp9IreJsYUeJoAOUYKglzMoa4rbTolwNg1kaiUPo7l5mXLcK0SujbMFWWGBRaLCfleNqCt
zawyhYjxey/Hi6IAQNbpyV42kQw66RXAvkbnjvc1Q/4UJ5rUo3Y+BfUc/d6QtoQ/MM2DnzZSelhz
wuszJzcVPod7VaEeVJQoYhSX/X+K3VQKZs2qHjRAh3XGV9YuAF3++sWBmfFfgurXmByZIYDa8kG1
7ZqIxa03vBFzHPJOv6aVvwWhnLmhSlVPCIHJxHiCGClZqCwm4y91AzIrXc9bPQNFscMLSg18PeG+
DaO3k99xUA9pn0STbk95TsxkbAAjVNbWBxRf9UedMz2Sj3o8XoBTOQYO2J+U066n+tTbHFYav1rR
9+sxamPEgAx/m5VI7mTLxdi0W2dgRRA4XDWHFWifRPN1KzIxNPHcTykgw/Lm//RZxB8MPUoBtMTv
ZLGrbVtckg65yrTYytUXEVL0eEGX99q4F5ZD7HmggQj/TehQOqyJaeGRkF0iyLX3+6bJxTqZWTkM
E9InS3J5wzbPVE3Pnz95yL45bs7pjKcK5Wq97wYr2xOxkApeasVKwvVSnGdxZ3dD8J71KiH7xG4j
IiU8QzbswZSUR0PukpVOPr7GcqrqOww/EAwXmesEJh0iEamU/ApOkbw8VZz0DcNew0BtRSv4oJn0
YVzugB/ed+9BIWsevE4e4JWi9vIXmUBT/uxNTF4cIDVP8RoxUJyU49US+VYMX+h6zYO0wxW/e/3q
GGFfRTxrDEX4+kwKXlfTe0Ryfled6Hfe25WkbytJZsJO11a+oiZrrrxLilzx9YraiqOSOJ0leUdK
6f6LbYP28aPSZxITy7N37ClpKNEZAsfvjXjI+fU6WItoDfHlnRgUP8kk6pzNyr2cSv4Mlg8S7zvo
ctupzXJVB+2WWab3RwqY3O4WwctcKkE7Mu9IPJjczuTATT/gFi6qOIUy0IeuDBMu7yfxvapNVXUw
x/XHP7kpFa5xaFPZLGgEyZwXZaOFNJ8gpmEjnHVUV8Nhrix4J7xLYfZ6r0+AiYhRCMMbuV46k6ew
DJLx1p3eKNSDagcWjIFx0oFXKM1MYJkymZpAFr+eTGw2up4fXuKo/DLd7vUiZYlt18Xw78+btiEv
VZCl5PS6ecifRQUmuW7wUQLJ5xxXco2P9v96725mgey2TRdWYXLdZQ1V8zsnwpZhINsLIMM1wT2E
Z/4Jlan/b4Zsw+9yMPAEMlN26qzCpzctSH/z5OrlpY49tjCWSpkqPM1l1BpbaAbi5nfYEoXMFOeT
3jTzFbWQ2tmzc3FPkORk9SqZMGl0agAeyQagVZsLeL8FxdQFK3Y5MgwzIOVV9N4/ouRr9BMhJylB
pE47x6S6ncVe3PPCxE1R3CYSUJJWb14e6OnlbSfrR1jTCppWEFUstCgOAU8m+D5GCqWe8zdILdlj
YVMbKliRzjsBZYMiXuBCjZYpJ/hu4pdE+56Km5r72/sGlwpLh0Sp3qFx3/QY60or8+nqNxjRVqk6
9Pu3EvIRyKCuk1fExvo9V5Zs62RrE6CxOL0NpxrYwn7PSChgdL6XSH+DfuTLAaDxXlkaM7r3Sr5k
6FbBdl0Bn4I7rwYV1cA5kPU8rGxOt1WJao5O9kG/TbxPqNPdrG3ZlEwSzi7J4QWmqCjzjzewXt9X
zmletWZ+HZMYVcLf7BB0zap0EO5N0XBbpxu+e+h+OGrXmFH0vlVv6jXXgJVEZhVw/dV72W+J4QvQ
7N5/Y6Hr5kpPZZ01uoNwTFORiT/PwJLbPj2fBb5Gupszp4mlgz5O1srWhwUzJ4ykKwhtQ5tk3ftx
EncTUon2WC0cUTNxeAxJTSs9wFPwNskezNjJ0tnXdwNiJI8kUrRZ9oszqKoasW8PcDueaSwjb2PD
JavrQhmgEOCBAgCnkPTno9NGlcek7DcPaq6uhwb50gYY2l2UYPMAcfrREJFdP8i3XffmUArvDNEA
hAnZbc677LlBoxG39d509+AoCHpo8BYl1DjMsP2+nJqaY56Crq3mip+KpqU20a6GnkZtXvPh6DVO
YUd+d0dSZUBv5Jaf67F96NUK/ZHgjMitGyfJzi1QzZ58EBcqYFCtNnceVpAtoN4bL9dhrzCh0nHg
MIUuDgdLdZg56MsdvfuRWLF8b/1Vh+j0J0VBvAUlBNvU1cM2zvUBkKhgPplG/6+J4+BgY6F3zNs2
E8aTB3D8gLnt4PtbmDbg5tbe4C+2DVb86cTrTGw299kZM+ygqVuiJVLzkM3HoqyCTYi+CnYwTPK/
y/XPY2wobFm0hVk+oUY6bPKxJnrs78fSpKYCsvBkIpmD10jW/Nm01hhpmD0uM3axfPe/99ANehUH
7fpJUTnGpOTayowtnZOrndV6huw2x86n43VyZuL+FXzIcUPYKGIC33W3zZ5/zbGT9xlK1SpYxlnH
/ppFj9iNqzCviDzyau+llMtjcfT6n2bb4gi2xhl9FcFCC/+KvGdaUJbalCRsmC2nUFgVEASgt4y+
q992c+slBpmDw0taTdwawRL5BBzSYHPcW+59Vk5z3x6WPcpKOwhK9wp+yXxcID2zXmFeLpldmL0I
Y4vWB0IFu1Uo65b3V6dmSVgMHCaGvZQ6MJvS80iCf2/oDacpLNOZkqa3DFC4XV0NkQD2EHqS1Bd7
Noj7ZW4mBzeMessx5D/91heXx/RqOy7/pl+B0XfW5qN+QxiwZWFDjCF/5T8+qXxlUdetQuYt43Qt
AdGhtGnd35GYO2bFGES0k7Da0FhfXhFYvkTTKxxDOSQe+uo9iYZmrRVQdW8iYJbqjDWytxfXX0Kx
3y9tB1FTg4/oSo1meuQSvqFourhD62tW0W8CfImuVnMpmgx803NJ/ftSoVsfVaWsKjyLWxWfRl+r
/c9DfsPalq2CZJWdnxy7Co4PtLr1oeDoO6Fh9j7ij5BvsJqhp2dD2Q1Pp4jdcY7GRfx/s6qpYfjF
Qe+EpssNScsqF1DpODQxSWFlVnlkK+s/JobFp+IjSWFUKJ93ppkLcDIzymZQ1YKHLaJLD99JgfYX
RLXBjcqlicOhUntYoWbOq62SvBwrM3+r2JSKS1zfoCW7diS5rKJDairlH6b07Df6sARnHgdtyvvs
wzoA8/6IMp5M/54p1AUnVhHKh8oE9i6raHwMjr4vLijAGWPMOcBYj2eRL3nf8yEzeQu8XrFwSdnp
9soB6+nAGNVBfaYMJRgoINTHd/t80sdsnt0dnc7OfHM1iNWo/XxkeQLX1Z1xYKIz2XxkTQbfjTUE
xV+7BFWCJoboXsmxldrKomYpXCq6iDGhc4m3/x5J7mxNJkFWobhHchcGgjsed5wcsPCJtD3o/Qkf
mPnoh+6FPdiK/pHCChdbGItAyYAMzuGs9moowM0jahLcRGlgQSQbRtUc17x3Jt/JPcj59ROJM9iQ
aToEB1fFa5ALLIMO990eT5C8x/f0txA4cFc+gSDKCpOxA8DgX+Cn1tSto/VVhjpNE3vhpRdWgKDT
QCBO32bUWpGpNSZ2mALB79qTAf1gtX4oS4PW/yqjNkA7vJZ5W1Ep7LbaHT5Kd6K1KvFZ7K4zsCnD
bZB1asu0sCnXOGy4tGDNDu87/W9YKynMVtEDan1nNPZh2MnYo1+0HGnKETiQCPsk9SD0uhlPfGET
GzUd30zy2VdFsYvHIZyc/oc5ShZvVko9KdUkQ2wbUIH1VCvkk01EaWm7JrAVbpno3YzlDMAxcTFY
4iPcZJm/Q6fBXllaUXtqMfKn/cLnJTu8UPqveOFrYWbW++8K15jKnYwmwBFiM8u7V28cWF3vGiPX
JpR1mIcHPRnp7ywMrNWwxxz+LOcaLd0BDeaKUHmmd1mcr9QXopzJ9u0Is+EG6+Y+XqaElZzev470
SbvcF+pk1F9KhDjfJ09zIAdaAa18yWpo2n920VijmiK2Rntt/OXM3MA1/RLDKQWGd1E1akKmHZCQ
2f4+jnSPliZZl/6HNYXqLkaKU3oDEnHZEpIUZDWxPr4ABMHG4vDQHEM+4TRgbvC4eeIX9WdFj3V7
9JQ4FI/fTQtLGMHL3JO/PbRYkcJaCbLayzHV0XRRyrf9H1f293w6M6ssFbExIOMRmgFGwJDsURJb
FMvIjbQhgOCeKxQLnZ0+NHGpU2NmPTnPchyDzCA1H1/b+ZYRr7+gyTXbpvU7eC7ZMZJ2XRpVL012
oAMm+Ap+Oid5SwtFA7qpEsaHLlR/Wex9JmnUFKAj4Do2xCvHIm7+BXkOzQjzXNWYxFGZrU+xtA8B
cCpO4uRc56S2eDWb0JoXv0SKypg/JR99YVnETpC9ZFbb0odtnyYL9Lt+MB3YtqHFsamqAvpmUSJo
gpOupM24T7ED4SU7H5kcB4v3jLQ49hZEOTgafERRw3hazIZktU6bZqJHU8WeC4qMBJZ3OJ0S5wiJ
4sT1FewY4C+E8itTd80OUhYMa/5nUbBozYxNnBheUDfF1L/kfSUnXQstIpO9BTGF30LOPsxEoHrS
TKbn8sSq7YWKdUgNBFNFr7aBhrCkymIvB9YHF5ZDGvJ0zBLAeK5vC59vIKbjx3sO7YVubeSKs6Pv
K53T+7qkHuPULU8r6TksEIfIQwPf0P5WFf9LGqAxv+w5THHUMpAxc978FW0xJ+ATe7ey+rwWmvXi
EepaB1EwshLp45w2tYNzZoNEWKapASif/ojS2VCO8kuw1rLY1obQ9HVA6xPadqu48FBPHQ+74tuK
wOY37WuuyKxSp9ipLLYPtUem0F4B9H5QIGQoY056nz1XffujAGuqtlHOu/VU/egDi7ksi3T848K6
afVhRJVHwyROsV5zaIQgO7j7rOOJxjXj0AL7J6eTOyZQSfpg+lyY/5JL3OA3n67CyAaJPle8F2//
yXF1TMnDWGiz+LJ4/tpKAB+ep7+25zmewAzueWctvyDd81E/+vel/qf1DchiMed6N+zOnmr03lAW
/jH9UKkeDdz0B46MBKOJF3iHsGkeR9XNtMP7NsrBZx+GQSmbOKXxtRROPJZQnnh9TAgyfmvubEN2
oTdk+AYIOtJPiNDnb3/ShalJJowuygg2dCMgfPcFUWWJxYRGhfx1NK2pHz4G6MYl3FjqFI58V5Yu
P2jjlmTfiJM5gsFIMNm2fXyGp/3p/PIDACDrSqDTfza2lc6HsJyStW5rX0XjcMAazq3s0X7UGK35
njjab0JAtar2KvLn7iRtuSVpOHX5TVjSqVVZGLzTz55zM5rqgFmwRK7b1PGwxswDHKU46yj89va+
M72ncoJecdz14w9WaKoTOQSvkijxIYE9PUaSodR/URjiys7WRHYmMatapl/IrM366IouVihpw0gE
29Tqb6mKcaZDuCCkhpvjBlLz575PFUN2A/J/RwlRhTm7R/5cjoT+bZrLVuCdcr+pGea4K7U4LFEk
OW/Wd+DXpuSaOzO8zAttgjTxwnxuiY5yNn0nfCPigCczr2eG5zjBKRjapq5tKn59IX+Fy93RxHHd
niuH8uTMAyBxo3V1e6+6O4Qb3WsEiwGKM4KdCsLvMMOsLu1rQ9FUpJv/OuRdxyH8QleUiMl74kEx
Rdq//sCW5pWbKFrcNTDOzBCOEtzvwiu+ppCwDL3A5GBzzqSlS7Tj1F2nn7pYYQBFRSRVwS0c5Y2Y
xxWfniwfrPuP27l4JewCuzwmIKgAhAnVy5UOf7GTQzksgZrI4VTOXg74GzT8hUv6YYSekgJsLrdT
ADdqiVgdtysoOn0TarcxZemh60uYUE0Mz+X3d7CmPi+PV1oCpAjEgcZC//at+lTlksptnpW4w6Zl
geD1tbQWyTqm9051zQf4tqKTpqlOu9tadafn5+vmnICIty9v02HBRyOZ2uK+vIOEtGCKF78KEmhT
cX4+R2FpikbT6ELjUAR+Wr8nQbFSCirAhNWKx6lFhXLrPX58FL0/fr6iM5BG08HFIHdG1Ofy78Hr
T+khaBwOSxE1E7++jao/IfrYlC7Bj+PijA5ivaC4nBEJVvvBPcouiwTwyh3rO/fsV9BfSsN44Q89
uX8CsJA5/TF9O49W6PQ0+g0WNcC9hHYgqSnKpGF0AQzimofBQc3g0M2DS4+TUDCVQmAJxsIEc7S9
JG2YnesYAaLnR4cUUWcj2FxqFkUNCgEBJRKpjWPZmDbTDgwfRZx0H9NWUzksG4buj1ULbeP7/eCy
4QihsOnTftd6jV/1KZHhvqMKaMt2lkBqBnz9OPH8l+8i/1tscn7JjuFm0B2hlPeEln3ve8PTui0v
O1xoNfnmcvOYS1zXTEsMo946kMiP+XDahoVHYvR29Hz0lkm0dKsNqsIA7Fjh8dB3pMBQ3GPvxQht
1F5DhTR8jFQF15PXinIGZPg6VVjOOQlkA/0AzmC6RQwLvaLEB1ClayDzl3JNs3JR/I38ys2DtHas
KlTJUmJwSKpk20eOu0zG4QM1X10HoxmER4BThMGhF9XfzVetBzNpiDxcY5rypE93ly+JaMxL/YnI
er1AhHiOp+v9PL5+NZ5Irv+biqp1na/tAp+CroxH7jUiq/PkUtq8iajsIyI6x1jlE8QdLgqO21CQ
eAlW0oQd+z43dsOMBX4l9No69p0x5G74X+GtUwAX3QaWvogBeyT8qcPECATrLU66fZFTdW1mGydz
X7spXsQ9VrwMCAoEWk1eHyt/+W7lbd4+5o8o7kSI7V53f9MvWgE5essO4oaw2ODv9qrGsgM5JyVJ
54ZojqFg/b4rxWr9sxkfNeBf/LEPdG815RL/iy9yeZ+yqXxVoWyuV2WsUuFBNkiv0CDOtebdN2qC
PffE9o82SoaKCSilxjcKzfkHobBOOpulHY80AYxraMcq20BpaCpwVXcgkR99bdQcCJsQUhLY9/GW
aMAwob4oKVJ5ZQgMi5uLmP9KL2qSGZkYi/7tyPcsf7mJmDeSxp1GWzQX8E8ZjLtVsd+8Q1/NSRdl
rwypTMi0Cq4Lmu7KuI4P2BB2NHb9Rp0g171FEZwowk1IDQzj9OSqSxmuMrbwnHdMLky6q7FePkUS
+jkeOoXds+5L2mnTMSRsQEeFnCh+mAh3Gjh3JiHcUbSYHwXj9vDM7IvVH2432cDCUAeUnEMZe9BO
OVpC527TtY6WVxAgx2nIrdP5ocF4AFSFvjvGbVRXsBLie+/7wR3dpES4ekCj3PxlQzkU0SU52ega
BdPdlXwQH87nsro92CPzn7BUTmD0RhhSQIcw/ib/4XCo0LiDhBv9Yi8OmrEPgmFWPUB5agMU2fzb
RKYYoYKyXzh7WVEZF7C2R7ZV4XoPgBWa2e3DH2ShHLvFIYaEmmSB/YGkUCcYwEub9m40ly7Wfczs
GpxXHjKvx/U8wBjxvWCZ7FwSYQ/GWDYZGEbw6CJZyX+Y87fCiMdQqsXGLT7AJQufSy8XHvXlPnFA
p+9/v00bZhuRsskGcDf5NhEvaNdpQ54yUTmm8/j07XtybWTqTH13VCxgofciS+MVMx4sO1XJNMd5
Oq/bN0Fh1v2WMCRgTWBGCIGhbqMw/qv2O6UJPOUGtNk8qUCOtBxG8N6m6z14uk+qCzgQFv3zRm6U
017WWQxFl7OlKHe9iwCoRfXoyz4xpq2mWBoAzshnXfzGbBHMvDF/wh0gpcDPqB0iz3VeowRMqEHp
DxXfj17pWu/bFcH+dgWfIQMHwKfYL+6NdCSMgDBFadU0/lUm1CDzfrLa/NwNrBBpJTteKSPKi5sr
xMIK+T6OLB3+jlYBH1d5fjCY8KuUdV6PKCa0FWKOQbN1rByH4vWfFn9YI2vpqemVkNKlWxtw98t3
7YTmA++q9jiA0Y11M4BeLeI7KpVoZf6HglC7ohm3wiczIXAHPljhvVifkz/P0qE6EjTkTBtopYrf
mXeOcjkwpVSMNc3WmZViUiqDsyCdpkMZms+uJ5EqnA9Gtsg8OlyF4DgbaZhqfiffd5yx0UDRVAfv
nxGDfsP3Zdl8jLWG/4n8l/qaGZEhYhoPgFo0fYBs5Hkjp8JRO0t5WFQYdc7/YEhOvYxOCy8T2wOL
+rmoF9E3WWxuCDoIimuXfR2e3mdottzPBYpEu/lU6cqYnL+GLgj9//BFDj191Qb4EAobWzWIFMxX
WyqP1VvvhD8tBwpS07T6LnLV1W6FNjLDYFRFM/3a9c+6DcbGVgu/CaoU0V3W59W8PLgbgRP0H9H7
59xG9vn+JF6KVTemFMnaITTvfeM64HG4Kda0MQ0oItadwlwUuERJmu8nEtC4lHbxMt7h4LUQPkao
cHuVD9NJcuZ1rUWDah/RHB4cuow50hNjJOcxzcKez4u+02lmrx8cOlATOX2ulxG+R4L+EXmYP0GA
HyyCznR9Mjj137uWaYw2NwZ+MBcQuUlbIH2+ghW/NDL1CsnCF7HEwzdyTSBfKNLvouJuwSBksCy1
YQFzs+CwFBHX0+ZtkWBNRPqt/LhLLE/IFbR7L9J5Y+PaVmKrccVwlG6xp5NRMtewV0s4YL/ZTtHK
wjwCeV6zUiP7GjvU034OQwq21A7Ji+kTq8IXQFi+4OC5eE8g2wlftMLeP8MouoUjzqEcMRfxXXLE
xuvDuJedd1PYad79B+7Nf3r9wIH9BY6DAqiaV++QY4n2NVQo8Q2+E44vu5YVMolrgKSq+P1vW+17
JPjb23Dfi0czi7NPrN8JtHStk+QiQdZd0LjT6lVaSCmdI/Ag64PsANMCUvXqzuWHBv0BZkP2G1Qu
ea0eatg4Y/pudRt91Lusr2wHqLekSoIh6EXQzZWcY28O1W1PaE0FTPJ4aa1APknMcG2XrORCNHet
WnDE8a8vGidAe+fjWr/YexFGVYcyHud84wjEXZtYo3ZpGTdg5FplBM0bZqmbxOD0qqog+Df6e3LE
SH0BMCF9I+tMEO7I4rbcjw2cy8dzJuJQFDLI8Xavy+lU6FrkKRWNZjn7rwzZPkBNAsWkXK+Vo2MM
u/V30eXNhkCSnluY4kWdI9+ZAfeZyF/lJ0yVhUJJuY5z8KkD4O+w7wx4iVwLo+kJ+y9KVYkPm0sz
6/CLq+zdlqnkWPkqzuD+ZLQYs2FcRgcBbOd22ssoqOiM9E2MKxWGz8oNpXSQSeIS2RnO99COFBk3
FgwnITLdkaTpSa9R9J5gTwl5OlKDbitvZ/c3L9X5KnRj6x8BDKEtCOUzSH52dJxde7WZcBcJ4RWU
9Z9uuRaQYiDvAjYcQDFeMHtxsdaashYCp5J8HuLkXgB7GLGPKEmsXpUcn95GWavBX6d64jWQtv2O
JUfm1AdqsKL5CqGc9MSSl2mJiB6FhTkipc4NcognZup9LetL7eTaBwsFB7anGaPkQa78AgF7/HbQ
pRtl1jz3q5M5XccdiH9whn+ktL8iWXxRJmho4W+GfQkhrb0pCgjGvC3HMzGxJhPwDIe12kY3a7Zk
mO9hipTjbu8P4kmDQzvYQW+yXJKLgb9blX+SNyA3EUcEpDBzBQvtsH8NJ5RBsEfa7YZB3thUQJQg
csqAGoqHpP2rrUA8GFfNcB40v0BJauwvLrWl/96Z4LokYuAuXnfzQ2EA7pUvmVnf/bojv07qmizn
bIuSl6f4gPDJCCn2BDPJXhFJqFOjSYnWJdnvLauyqOZXMSRhfX33dTmILR6B8l8U+dVSrjDNPgG4
MxZg4hyDdYI1dxlKbAM+GCIN0nfxc0VYCBSC/c6B4/S99AqH6ECw/rHcWnKQHTe8O9KLvUz2LRfG
qLJK4tXxtknGVpqURD+Zmkic+mUwlYNwS3cxIOj0vR1B5RGELLVrwqf60f31TjCUMvRuuK5zrqr5
sQiVFkxkHZEd6IL7k1uX7PGzURaXHNJZAeO0J0iFbUrIivzZKVzOAYdr+WIB7XNF8PcyKHjuR32c
P1xIX65iIFPV+fqreLuGiUknt5rjofjjE8CN/A7yk9LUjptaRJT+Yg1VTwYfK4Ea/+oq7XtvmCTQ
Ch+Q7aw2rgMdw6rqmXwZwd1s00ro5RoE3uDn1RfTITdvEnzA0pq5G7Vi/t01sypXWtK6YuKx9hx2
YEbN0FZOITCdYyhv8epXrM081X1m5TURm46Uipe6HN0gheY9yu0Jr05CMhlSBisqqC7GuL0PaNLQ
IvMO7tfv6W7K8o6QYzK7/jy9LoC4XObLmWctsLRjBp43XRxOGkkrzQbcp1egIQtZHRZmywM7Vo0G
SqiYRP5hFjKfPO0vzN+lY12M0BQqSssj6MJAR85Jc/TtjXNpoR69NiD1JsSZosUi5iGj3lMTvw9o
NOlQIS6SdhvfJT5bebbpq1BNV1Q7pW21jky9my+vi6DXxyBfN8GBsoNeJuKy6FZFQbhyWNZSKegL
HKtEU/j8cSXEYeay7ZBBMUjr6B5Qfab+4ZawIoTbdFDJIJHF1iq+/UX6f6ubszhxRD/C8PgoFneq
ywtNsVsMAq3yuzIjVnHz7YECgy+m9RrEX0+7TtnA065G7wXCmurdOD002QuiBB2PoQJO2PnU3JnR
YYYaVfvvdGtiuJtymvW8cR5SY0BNB0UZC1ctY5YEMbCUAZNsLD/Ac4Va0iTiMA390XrINPp9PRA0
QRQ2BepR3rrbVTGmaqXMvDknGZ7pM2GVn3YNTdtcr7WMjOKv1+wOCtHdW7J1HicKNSJof3qN/YWQ
K3PzLzd+m/yNqRtz9zguRW5jhoiSzLfYFQITcED7NJAUQ9PCsQW7yAPzwUI1noeHUu5n0mWw8Io0
9jaDcg6VrtlcYMlREcGRjFJTFrucgDqwmYucwyT+CWGZp2R9rO6s9429d9IfVwTXJp+WFd7AS91o
jxWXzY5iIKjI6K292dJYoWFnmPN3duRdWa55ALezeowDBeMUk3j6B5B6pbj8L2AqIu689QYY8Z3Z
ofdaVS0NdSfXp3M2AFOcJ2Z8vq7qBWGflZYqVRC+UiAx+C5VTiapu79WXsjsPJSVzOPmpeGEGymE
okQ2azg9EaTHDqxkj/ZZwCFF1Ky2EUb0DNHOy6iTNp//5YBDgrHXWmDO1GNUQVlwf/K4xHIT6eJK
l/IiZ/Xe/cauv7n9NA1h43ZLRcRpFPjH8Y7eWncgOsQ0y6IqUdMQU+weo0nsOsV7oDd4vzf7CLrb
x1eugr1d0K2577CWnfqjA/Z890gmnrHZV8Q4gHTybwH+ux1nXq67J/QptDzg0n+m2XfCBROc7u4u
AJcm253a1ZdHD3nGV8dW2cgmw4o70t2y4yDy8MdhtstsLIVzBMJQrzRIxGykb2+sCFFcBLCpjAXH
bRfNBW6YfbfeO/W410LqEGkXtYphoB2XFPpsDw7ujy1+alnJ1gZPmessMdh5JteCLST7qXk9qpPE
WgKFuN0RIrrjpOAyZsOnLXqslB2qWBoRDiUtanoM1cHC0jEfDOBub0QN/9yVNO+x4hSC9+dvkH3X
hXlhVt3VmBfxAew5OWYwTEVaL3XCbuvp0wf0qTiK+j4FV7TBwxh74Lwfr80R9Dy1DDZ3ZnLX7OKN
G0Dw/f57NgWVcW03pDzQL9x+BUbEwIep3ANwzdROXWQcLZNGI/u/RDbA+qYqbl6CITAEqoESv35b
SCb/fp9dSp6H3oWYkcoX7X0EM/4lcRD+FF6902xyEDkQ3hdSpf5jHF+okafmXtOwdEcQrZY2nUIt
kLFTlriZ8axCnPj9lnoX0quERFQ4rmZMuBQyn/XZi+hhiblmeNz6pf60dPdzSYNqpuMHz2O4T0XO
Xd9gUrmyGndNKePb9jTY4yHnkyyegIplJeibFvFcMfCe2fuy4dK3+VjvH0C9PeHWUZGOn7noGT7L
8Cbegb0cv1PpV2E/yQNe1KpiY1IQZCu/nIv3uRpdNi0dlTIDs9Y3bya4xOeWhZQKwFJ3pAs01BRT
tlfgOyRkI6u7Vwrm2w/mEmOBli1HY3BDE5Hoyr2mr0GCxoBYVMLJZskeP4N3wER+jbIxHnu/A/dG
V3/iVT9shoKQzD77FqqGKuKxKAQjytefetnfPFZ6uZ2l/bWTU2mdCUGAlBLO2RKCjLHZthJjDuK1
LRO2AfxsCI57idVVcZIO8ESjFd77xQLkF6SGxvctCShdOTx8x++Ks4WFzJiMZaSTKl3MoSu4oFpq
4yWXpxCdTr7njznr96YNPLMnh85ENDod5Umc2dZHQdN6uHl2ygkxQQbvQ32AwL8WgcNRlIHfmwoI
TT8r0iYOIA/7baedkWVD6zeFBSqmxwcIqV4XgoidAR7LQs2jWKqJkqKKrPaey87DTyAOYVZFof/R
iiUUuFZWugr4d4MxxQAFrfbHzsqIGCJzhMSx1tLw5qqYWc6RFU5Oj0T7mxqztoDyNzah2eycBjam
LRog5XmaEL4doJDEiuboxnV85qElBk7yXMWLna4unRIAb+B9GrwZAMw0r27DdKjkb30RgMWPYyES
7mR/aaPKkrS356tD186vUPsBaM8kAHuV5vu10jBNCqi2drGjHjqNb4QsMsSXFJ4G1ziiKrQ6XTqT
XbisxDzNGxbM1KEjANG87/PLzHM2WCX5tzLwLX5CYj5Hv905an+K27tMzHj20xbe2ZmuJyobjjco
QbV0nJF/boxcJV8S3d+g8lS+ZhNBVp/szLMVfcoFyI3pUvstUiHJqZhmQfaSMZZgDAMreMa+2fkh
wj+Bv+xIg3RxeNIDX1z0SOYMdY35p9V4B4l7giji5RC9JmLvIHCzpDDL9T+Rak21uxeqE+f1Tuez
L6qmg451FDGGjbDiO4Xw19wWpJhL5Ngb0OVUIZcXpRWoZSvPzy5M/N+mBD7hednKcUee4ccim03U
0t2/Sp3DhFxkUf19m8PgjG48ScmNUBYCtnGVjP+QSVd/l6z9MLy6rDuIgJqu8lBjOu8FXnfvviHb
bvQVC4On3v6r9dz+SAymle622X5n4ZVfJKJz3tZnqdxyv68kck2PAf3cqLtfILzPd2u3ifvtn5Mj
DfTDeEeoG5OUBWD3ipre8R7Ekh5Ipn/IkuTcCzeNftm8iZfi/we+H+VC+PJdUc/tVPM9oxeDf5ph
zze8ZKuz0LXFJhqU5F/4CxH3i6q7mm61JjjUGb10RgQ2eJweaxR81eARI7OUwNJhqKHnk2g0lLlW
2i2ggKUi5MNbPSBX2PpaBveHXgX1sFXlKQqS6bfaWoa5SVADwAoFLrrmaVlzKvYhIcNPsCKKxJ/a
AqAtqS2IW8TPHnWJq9DF15N2EFGcaSJS83crcG0yQrsBe/sb9PxMv3WMH7TXgak77HxBoXP/QN3r
1u6c/tLSbp8JgmHfSSrRxeAgVLUh6SJy8mUqjbb/FZXLY/laoSYOCEvV9ZaOrk7QFsY8dqQJ7I5K
hB7HRrQYpgD3zcvcFiugtLP6p1EER5fJXWb3hPBFH56hKP0cD8GO3/TKgW31KLkyGByrN4Eae5F5
xUhQrKRN/RiwmwJzcG/rOjtci8aUH8JbR6fhxs3/EB7ndoJmC4odaG/43KNXIunlSYqgFIFrj8UL
jhacJwpk+VP2WA7/3ym703OXA7b1XmKdoSie7sX92LUhrgGGHk9Qeu7vn1tiBYCfK2Mt5WWnRCnn
+TPEN0RB/kSWgLPwz+5/rrLdNIcNQvb1GsGYnZv13j77u3jozl54S7yOX5cYZ/dJLhvasBb4LnIt
S7qObJR5xuXgRe6vCNGFlt3lqeoBoft+6EUCVFbBpeWm0qtZioS6l7KDmO3sPtMqZrWPPXp0xkSB
6RdXc81lfkMPciwxLgTFOez1Rbk3n3xUz8fAZGTaac76Ty3qqJVo37fwdGORDxQcyfLrCq4Nd6CP
8eALqcd1aSeJneV8uz06IcM35b0uFSL+WeQhTl5kdZAidKEcWtqkLa7dAcn/kDiG1kCcGmvGHfXa
qn1irjO9qhyO4CFY9s0nhe6/ksILBE6Z1quldWkTOG5DEdSyGFwVbM9GrFPgDgCUNezQiEhSHtYE
LiexJy9/HcUjg0YnUBsFgi0C+SKKzNT+o05GL2vJTD2tcuBlsYNddciBtr3aEHu+AYc6cZb8QTER
q9F7WXcZxWkR7AlktPochgdBrRUw9ZVfhdZHooGufJIbmNsRoXJ/32D9crK9dV8WYtry8PQ9amwL
NbEiYqd364+SCg6UqvHVw4u+QULqXq5jBERGKHcypm7czYPSL79KAzFdgVJFKJPCYvys4jHkbvQ0
7/KKvTwYY4nDkj+oDpsd7jhtA+Y4/bHcWf3CtXlvc9Hmm9OyOUv/6q8Noo+wPUxp3wjKA+xYiasT
fvepHfhPXUjFCDc2OYV/XA7CJnaoDag2POozp9ieok2OV0io2+j4WlYzMRT3YP7TrcUhv/4d818g
qkoO+VK7R4AWi1KTGpXsxAGK5Mk7D78d5hutfgGANT/WLYbShz2C4iy/LnJQPrhQxn9ovXkkwNCI
Glh9J0RZcV8o5e61W4xA79q03Zyw62LElDj/w67F22WeFbezMFrIT5JfKZsZd3DtIyrrslINdkoT
RV6hjgKROquC1vdpL1ZvvDiXbwQGWWjhYCWl3AoISvV72vxOyViceZW9p9eA4Fahu+p3rovuxPvl
SJ0LX0tOduZXw4r50nw4GsWijnpvVOtagdK19x0EEOxo1Lm0v84Qfgp+bamVmL2WGuc8MQ9Od3fa
yRWl/eZBLLqbsPT+BegFmyST6uDZNlkXpKCKL5SgOUKGD8g7Rz6so7i3djobhGWSlLkF9IdfQvfM
TlRsgF9GNvm622P7oafqzVkmSnGnc5OlQRWCPuyvhznoVvXrBU4FNliyB9WkAsQBTOWOxzgtH+jk
Kwlh+6ZYkDDQxuScWaX+cwQY+Tie55ati38u92QDnjhbt1WRfrla+Nl1SHn6m8MpUdqZ+zBL5A4v
e6WfvQcGpo1hFsiue0bwaRM69/8JnAg2pJPgQLuTklwmVXEuLf3p2ZgeNTrmAK/varOnuqkSg1k5
nfjKmUBaJBhFqHH0m4jrX0HFqiQFt8d9vcDFTM8plQeIY2u+S3UHIIeXhTH4xmvWWTo86zPJYY9F
VSb83LM1DDQUZH2G7Ei4bBRJr31tszLdzBX0aVMkdoyPIDoF1Ti36hxbij1O4z/femuvtjYMRXcT
F8XWzmraun5bau0YDtTolverTX1I9QXp7rX7wIl9A/ukg+6nJyGZAf8lMx8ygha4CO+SvP9U071J
ffE3Qdw60RgMINeYAegmAX8X3Eq19fs1r4/LJwa+RFCXRIw5teuDXIhenoFULdSKli4BT0DuPmiA
zVqI5D1+MboPitJQp2aWbpN25+gDGAULsDc786te4qw0+NcSUnqAqX9X7K7r7iSMtOPigPB3xXSi
LoPnagE6C770mM0okHieTZEA5OorsKU0+dhgPQXr31cc/yorByhjaTWmEFwLqY8g3Qug9LksD9+Z
2eEUkwjrR7q03nqpURquplM84th+7LdL1ac3PstmG230MNvWoCVXWu2Ttt/sKtzuk71KDFKH/Qtu
W13L3RO5O8Zd9AKsGGQsRJS6QebFhMb6qry1v9XWKaWfAQhC1D0A1TWWcnNaM/yQXf1TNxmzJm5U
ow/RvCduLwPt/Ax3RxDgGnIzBgr9CKVFjY2m9nJOFWZBtRrPAWtly3coyMcAM5uCbD9wn7DwDjbL
Byxg7J+yzg4qGP5Xs9Q/bpf4NvfoGZWgIPUbGm7Jo4JUvgmlDO89fZMR98Iznb4UIJNlcBkWZbCm
asmRTq3OFKMWzrZof8FYYI/IpzN3gTkJXkTVlWysbCNIoGMYCjDQs/AdmaF815MTOdnMvmXbh+Fc
ETXS5M0PSLdvkESbUpBP4FTMVZ0Y+fT8qpMDpxw9/Bjglxucl9IoTjezNfaYnvw8EJpERHem/ZNI
BXJybuy+BOmZS6Bue8kU7McvHm2BVed4IVhJreY1yawpggPmLj2X6RhXpC58fFRM7L4iN6LYkHFG
NNlFq2oGqiW7hp9JeD6i2BWwbJHAGPs348z5yn3wTxCqdcuGc/WzBINAs6VYY8qzZVdKQmfj5QM/
MnAwofN+QLWLlKbTYXmSdUW68AUp4lDnQFpgMpGPjKhM0B+YVzhNWhD54ByAssV3KU6eV8xaAk0G
8hzTmTEqiHjhSZIQBfez2hWop/aAhqWNLXqCLolQCQiP2hFJEcHeYwaS8coqQtJA5XQISimlBoWE
PMTeiogxyLM4OrZLz2WWyxQPr0ASEgBApawrlXmqo4RjkOqZO6kUYI84PCyqoxZz8xgAGkJ8mC6d
mITN96leA3ZLUz1ZivhAaAQu6wIvKav1k8fvVLAb2LC+5ZPqzZ3F+W3+n5at4iacUj+rImeRX9ky
4kHCWQnrBTuUL6kPCUPwbCGu1ZAlGPWE4lA8q7Lqb+d2+YNP/d/tZX4EhKOGXnZ/YbQITo5ehLU0
Ogu9PQK+gaNzABJ4tzWyzskESKfcb7pAenjAT3jMqJ3FQKm3lGdnsIPsyOwvBPmlG/k8orjGxRGo
Y1hQnS7RUz4wU3g5edgWBxXpJz+IMQZf5sMAJHSKHMZcPNhH57l3vO162ZURVJjzuBMjZ/AAl4U5
nEBa/6vh0C5f5a2o/1ZoTHk2gv2Izr4WyrRKUHIO76/C4H63JIrJiWHv+/K/lKXk+2Y0snXyeAYj
NqGa9Zo3goEbnf71kIvIsWTHW6mYxFD5qhzXXEMY6pPo3+QrMC5M0XQ+44O2v0C60RNhLCKib+qP
teFLxSdGXdtGWsBjlppRYKBriEBA2DjXamxVMFmtlG8hXQ+O3xirfZavSO/I21Kj0UyL/WaAFfW/
IUp4wk8J97pZLq9gvk0BjeOqCpXEhoMaco3L59ViwAjahDbTQOPSvWxQhaLQ14qXv0cVxuwf3aJM
6YvKpRL7xEeJMIyiiEh0AjUVk+ZfEeOTFXRmzPAv+l5m/hz0DFYAyh994gxzVeRqv/2y/SUobsB+
JYYyZaNviBTdvxw45TMs1tmADAQFulU3GIOW3XahXH/G6HlLlq9xSBAXUIj0O78F6nt9X88pr45o
75g1aqDooeplNaUHMwzcS05WxMHt/ohYXuyvHRqZhynnFgSBv5W06qBJqt2o03JTh5HAxPNOUS0M
t4WliZ7z1rSnQ7m88yG3nc/BdGEQR2Wo8219Tn/B4HEQWm74PChGCVNjpIT+ACUxgHf2W2MRcs4s
BcWhgNtAPcvqSHMeo8NE4n46Jy1sg3LxU5bJPb7w70Y5RzZ0EEV/tyUw2NIlGYZ5cKFwt3HVJycq
Jw7jt3kP3E5nxtqb43uYz/5mSxZInBBTIa8rhLgCAognLSnQSl+vC8uiDDh/gMDOldbbsCTrU1EY
y6E8MciYYgVaHFUjx7z1whjA0tBfQ+kRzbZwp4QfgDAHTQ/6KEg99ryM3lWqzRS+2Rmx8Zyse+9S
mY0Zz4vKpFGRm9X8kpFmjdvc+dTzr6CX6LsRmH1E6JawqDpbgIW7FG/u1qbr+V4HhtziOWVXw8vM
0f7b1hJnlEDSThrVDZiMbl9+tmY+XO0djeczofhHvTnLUUV+D2gfk7B8OoCFF2WOFTcUERmL080g
1eMs5FphXnDhoFRfYtAfxMPybnCm+GC09HMP8yoYeVTeyim69Jz7bGzwvhiRXaeJhdkPKJMQbgQN
6VdEQzcokO2jJ+XljpLe3H1ilAf2hU8dRaK7Fm3oj2TD6HCoQsvX2ahmR/2OalXSDNWjm9Sk2rn3
iJmu6KPEkvsn+uTdA3TkBnU9zjXXZnHZpebNMZMCSSk9uYd9IhxS+mGWSmDM3GCysE/GGgqFr4aY
wx9yv4ajCHERFojAlh4kiH9jFGSF5O3bEvwHvwny9yHOp1WiIgzwPg0bs/F4Fxw5Q9kj33WPmP+X
yq87ObIAEEgql6s2+hXVf7LTfMFgilqDKMjPil2jMs5rl4eSuP9mMRDV+BASz2cc82EtmnyzLOUG
1yfysW2M5EeF2gDOf8+3v4LhKhrHCDGZlvBLY/kaB8nWB68/Im5y7lK3UDafleHmsdNHuqj2tLhy
NR/pJ4NPMFkrFkrsxQWHBIyI5s/HqyFu2LfzqpgU5uwi3M/2kU0QLxQb/Jl6bHxKoD2zY0Ktlm9T
rKiuAK1izkUYH8D4b0GaSLJn6UbmCdXNb/lTeUYNfnjVr23dBBoz1ZYA+ebhHn3zaLCWHwzHezw1
Vl2/PewA70oFBLv49Puyf5A7cWasP0YFKFx98VlSaF4VcyVsahRh5dwqvt/djXq8vo5vg4I1DIB4
RIJyV0SQuKpqfu3EcYqQUcImt6Gvci9bP/FN0h/9HxAm0jNAtTKhx3Rsy3lHep2LcE1ecZn6ythE
URYdSWULA2Zn2LFytejdTokGiILfiQlJj/5PoUzD3D4okJmL3ku9Z1PZUwh7lyvY44IAUYjkDs01
FCIJsw2jEWvNseW2QvTrH0bMp8lSu4Hc5oFEEx0OcNaFFTFQjeUTzlsJJmlXUYkA83qVi3FEqpjo
NE7kOH9l3+oNoihe7EUykE91LcqHq7zoKdayUZnGNn8sxLjPDObACihFH4NNfrHQ8PqPKVTwOhXv
1Pw+uZvhYhek+QnKt3sa492iqeJg9h7nXJEsiAxMgzMd72IIoB9sOzBJr4Evgv8Gkg/DaGuiXYtl
ow4mmjFKKiYtgFWFkgkohhLxY6ZYOS1l4YguzAKfX2ngYidKEzY7fqLfI0G7YmgsX9R1LGUt6dxn
KTZP8bgV/mo5RAIoLxrNTVif7N6HhM3TplL0GXz7xvT2+WnwETz4wDCqcX+h4jsFk1WXRzF8j3gv
vAjBrEru3r5wVlETWeP3CUOGxmealEg0WMq7k2mtaUKhs3rr/1Vw02pesY4zbI9RuwcR8+rT9po+
RXYYL6AhMHxaRs2/ypQHd28tqLqNtyNSWm0rMBJxvWGvz2Rll0PlbgovxQ+FXxkhG7C7afChRYPU
1X/D3WeSR8myHzMGpyp2fu77qefl84jYxveOuJkX4uXQJApgX/pt7YqwnS/OPL8H0R6mbdRCwQtD
NQ10hRxOjuW7ZrWIXVQOMrDXS41GQAx19Bk6HTg3Za+HomJy0VUdWLRbD6dBAPhtVIBvgdQEGwoP
B/dmvpOPW+302WPLgKPEt6VFVHXDEFB9ysKr1u2J8w7TMzZzX2QprJczTHVFjeNKPxWr8rQSEB+d
y2vEYDMD6V6jaz2DHC8XLDqKOWjZOi8lywFK4Q3NENKEf1h8WBfJ+U6/9Fyo7HbRE5hRwPRyjulw
wCl7bs8H7NUXgjeAjFx+uc/D+KSqHXovAVlemXlVtCkJ/9fqhgHoyjUfA7T20RomzaTxP5x6iE6z
PleTecrIfWyk/DatK4TgJiVN4dp1DQYAuUk6jXSQcYNyZGfh31wuaLhwaU9n4txM0Paz6bpQAX/G
3wKuqibsKnJJi+CUJ2Idc//2N9sTUxAojsE/I9FgR7Tggyuox/TJrDzd4lyRb3K8kGIN3XqCZ3ph
B9dmIhR3ZiwbFy4MDR4/If5n6/9f9Zs+OCMaBJbL7w9lvU5dUV2uuahboEeShcanQzTpokBndB/4
4AZOerk4ZxiXM62YH5k9NRGt16tXMpNTli7QD20w7/xmY164qrmYktmzdTfIi8vG7Xd5ELVLyHaz
G7CGrllzN3SAARWxewBJT06iVxu9/WZ6yROpOuyAllWZwav1J/MgVcMx/O6LNV75ulgzTlytRHKx
jwhsAdZWpTsWRPpQRRfh0aswvAo4WecQsBilRxWLvwohXzILpp8kH4SXTJ0ZO27SxxFC0CT7guLD
uf/HzUE353GAvaRJpOulCxaWCWnWh22lrllunCqUzI/4M8pkNO67lSgqaZxfhQc88U6brozHv9xW
mmjhievqdVrR4YqTj9xPMATuxCPqQ1MOGw3EZmjO68IdCRZFGTVzEEEJa9SwH2QEzY6QPLpXv51g
1H/kw2M0O/99j7mIYK/H+G2RFshAtercaOnNKo8kU9oQk6d8V3VjBXbEYOzFO5d/hH1xpgwDsGcg
4OFa/tpzudXYAFNWEtlMnXYCrbmEir66UGLn1vrypeMJjaE9ZTfz49jOkso3oLc0kQsU8AVXOaRf
rp3n4W9FLPnL2+de/HYxZQqZZZ5da3NGf8xLp64lNUKykAj1Jh2z4glVrzJmcubSReq8vtYH966F
ouXBAZfNH7TL4lSvrDo9Jl6uePLb2k+TVhSbfOnnwsvPJ4hn1Hcz80LtUFZun9QkHeFigMfjMHGL
48RQ3tSN4nqUGcZiifE8gU1AK48aqleUi3G5CtvsFsS4HYiVRib/bKqxAwz0748UAGuvbeoqYv6x
rNjwxn28qaKzdGBmjlEp52kJg3sB0NsJPKuNf3doR33DpCKbs4bzasIT65sJQ8VetRLG3fatRY3v
gqR+Ir+pRfpNO6u69Du/QUbzsDK6/ojn5zKoNTag9Wr9uU77dUEZbyh4jwPgdLX9D5JcpxDzD7QA
QgLBcWMTsLQM4/6J6yA3U+jAEv27oeyt9QnSRB4DYx/azO8cSH2KNOIc4ygp4deDiFYuaTlkgxZB
FesVy+jIx7NUdzg1EBJNu89puuOkTBLwI2YKb+wja1z2zJ2gv/nJtG+jvQBTkxSMS2QLJ70mk+0F
jqKbHPZZLeWcVBWS3rBrR07xPqmYqyUZepaFdZsdUW+S+FUG7Pk7ANdC4D4KfbHHJkBgzi95iQ9h
L3JV8Ay12taEuWPVL2ui2WGn7D6qj5CBcT/rg3n3pkC/Qj3QgRMUf0isWwmQtKDP7PZ0Tt6DRLvf
fvS/PpuZ/NFgdfmLdlZhHV05uCMpxzwEtzgPD3afR/xa/tyMnaDQ5UZJzD0nujKNLpBDInwM5oJ6
vBH8xaI/GIbTTjGPjX4IttFrb54oVjr2XncVE49i2l1X3CCVtcFMQdFaz7ht0BC+Cn4CYUa+eo53
vDG1d57Dpya5PWslnpt0IydBf6qm65qS2Nmku7VqiJtkNVGk65aCseHMeEktFR96sKQR8WTRzWUe
d1QOFhnlado/cpUN7hBjblxcTM+XyQ3nUQrgYC6ima66ajqe+M+SlDQlBu2zodLJZh8Rh9+w7GTk
j7ec/PJxNlQS83Z8HkZgalUKU1SghFQB/l+AGoKWoiQx239U3DqYzadDqXKGUTMK+S68XFfLZzD5
Sv05IiptZORJzytAHhUY5td5O3QUljxjbLZdafCaFUlqN8/doZwK+sdbsKiYs+C98aBdRoXE1Z4Z
Sac/XeiiSW3xfNEZEVZKJgdjOeESgAnFQu31sgu0o1MdRxKAl1gHjFW8WTZVpiwEbHgLlegAIUlo
thf3OILjZqSqvbnzsntYvRIl5uG8Qd9sZyJhNomGZ9NrgssHhNof7bwj/3Xt0q98eoz1TpGY/tkG
x+1dleFof1NYAnvpstAr0tzdyk+YT3OGZoB1FSo0p0gVFmFil8bd82Ouv1xqKyLBSrWma4mrG6EU
nLcnoeyLRRdSAG+yqQXqyer1VDQB2C9JIQXCvSuqI4z4K7RAutCjKn1pgQKXUSEfkdRprG0XOhYS
920UicJIi4XB28P0Xt8s8+Mu08vGXz4ejtIbnuhXBKkxvjKMUib3Omm5ALKP0RJgRSfpf/zj1utV
Sx8iSwurlvK8ZKMhfkNCELecSFu3PWpe7JAQlyMKdXO7hOYfYXMH/uyXr5L8rJU3JZnR6vpfydJ5
z1WTADdtSBQV4WSch95apgpKPeCW//gb2RYbZ+la7ccKPclKISoiBhCV5DCp/UUClWumdf1CK+Kj
ruglGH8zD4TILPO5r4+WGF9EQA4Hbvh2Jkz1B5YCCr6/HCD1Id/pwVBwoUcU9ndZsjdNlWGHsUiS
uzQtXyowgks7lnYPmYWRad9b08d8U3eVs29icpzACSjz5KXy0noNDs9jU414y+KcSJNxZy1xEQ9b
YW7ZRQXjwlm3LWQydDfHXFd5s7LfzvISAPG9tffghCtkkZyqByxiASICB74TlEw5Dw5tNsmHAsy4
jfMnlOQbajXJN8zbaNBDSLVoU8/sgfTZhBmwXs4omNtAReXcY7zRchDDGAfqITGeUNshnpceMrwW
EK+EiPjMVJVyF+c4aBXHPUerI8dQNi07zkf40geMSbFUmbyedrmAUpDSQuf6RslkZpeY4HWDOm94
g3vQsgaqjNVOVIcLX6Bso63mHXd5KSLelIpUg2WmVb57vNZwRlB+e/bH7mAFOEv5iAWwxMGrtVsk
8zXZb5/NhIImCeH9Ny3FGQUncEfC8krQqWM0tJuyGg2AVCSh4spu8t3HlsO7JNAZ7UgUtMXsxAD+
QXF7zrkEnMhM/MXlmcBVLAeNDYZLewAp2I/t04TPKVHK5hgtSJxm85trqJ2SAHWTnNnXy2uGC0pv
soT/PYkMLOw/c4ri0p3zmQYaekPPHkB6PmvyYXvTOl0BaPbUPvaHwNyPNvFOyZYFYe5gDs0chr9V
SH+LRFdykhSkiJHlX3tR6rgfzC2reWwhpcAgSFcpX2AwU7mIGzAaONFTOyupp2iuFCVALZoXl2HP
dmSLe605TNUaAdBAqaWoRwv4e7RVlebbNP2F29qKCRAqJPwS82q0fNB8A1abxDtB0GfywhkyOdnK
B0bR/fD64+6qiSrxTO21lWmSldu+QEz2NEgtBoNnFxxZSnYQ+xOjpqSnFkfEK8CbNxoQZKFMTzbE
uy7h/eTG4fAAg7vadtXp8OJQVKmQblpZMna4cefnRHhoONX+AjqoYrcq7YJgqigZ+/Dh4z2xQLDS
/gJ/8XzETMukGDzCT3QsEW7oGeLKTiWWfZNJeWA6X39r9t0UsD8NR7eG3RjlrWHrYTcou3PO83Ul
b50JOj1RRWgRLpruQIdYLsb4KdCpEwq0RYTwjoEXezpWD+ySoSBVo6/9SjAIahMLPb9Tcouukgnz
mIAdtuRBYpmlsDRjtnRdSfeqlykiWhTSzYJFDUvNt402gXlFxBEzhwycR/ZiaDd7Lmu1/HMqnlgd
1xNEmmcBTaS3t9k0T1pgJuif/8aBmz9vRF6lgmc69vBbmYNlfUb8//PXE6FhY7S/t3Dgw4FuFvfk
SOn1cTlXw3wa0B19NlI734peWqmv7ZvOzikuslmuyd7psqUj6vmrqR7YcznAnRi0rwMX/A9vLqOL
uuYm/bZdbeqJ6gZGGkkUPaVVgRslis5kVfyR+FmzbN8u/Qao3Z5YY6rH6zaIm54Bj2kX3fRu7y+R
ZzqXtHeT3TXkL6V6R55WD0UD0obVL8UJiOtwuEkSAQp6EjjbCYARUW8N4udU7DowSQx2NJFDYO0e
mMftjxPfOTpAfuSMdfc1GNr+Ex60dfyaYJ2+2kI2zOJHmVHrxTKJY5ELd6Yk7SmnAIOvv1Z6/Ccp
SxaoP0LqWEP/8Oa0Qe08oyBk3w8cWHBa3dG8PB2JDnwkxIAko0sWARIw5BC8L8yTposE91z5vXyi
CbCEYHRdaB7G835eW/pumfz4Ry44wjx6ov2n7tyTBPsz8OzfySvWh7YQfATb5036+sbhxSbuRm2O
qbhUvd6mpDB4yM4t1fF/y8LCYEZy6P7QQXwW8JbT9e3l7TlKe+tFXU+AFO+UFOobATqzXFIOoZ60
qhlUBJ1kb52iKuhPwIGxMv/S4LScMqYyyExs8joi2SfBFHix1+5agrfTUqxmSxe/n83m31zbjMmA
V9spGFVmxXWyc1OF2CVcOTmRlYm9H6KB3CcacKpszLKM2qvul8M5hPfnj/anyWwWvozjFlnMvJL/
4RU0D41NNyL/ulPuK5L3obI/ot9GooPsfaQ9CKrN0xZHp+c4h07ARQxvJur36iZVn40RYxbdrZvQ
ij4S07wi+5UlMkG693DcmmajMI954uGIHYq3Lhm2y/SI+LlEL0xfTXoLyvhSy84H7hgMioxzm4mW
BrR7DhT42cNrU3NvuEVLQ+LuGpkPJFkwsHJvYNKpX4g7X20qeYqwEw+Me1zB918lKp00S3sXGK1a
r9xLXtVfquEsZ6x5xIoBDEm6nncI9Tp2TlzhPpbrt5kKZjTuTegLvqGgloDVK86fbcR+JkKl5AP0
e3jgJH1nbofeYmPb/b6hATHE+atppIf5ao/eXdTFl8o7ZPaFMB37IhIdak609Flegmgz8fJ2bbFM
pBQMFwImWWveifD9pnTEGsUm+oDpOt7+XVbUbla1jlST8BOSBtHffIEJTnLdt9tx7ulzIku/8UAL
T8TxGgjWaT6tZBzMcRDSa/cNG4UxWNnw9Z7YN9GOhO8a9rOjRZXFTca8vOGRDIn/UmPGYUSaWPzg
LFyEwdRNVnGkN5tQSzXVsBg1uax4umZ5qytHrpI1OQTjZESLOCNUkr8qd0nu6ErgIYE0Z/G0LB6+
NYBcinK1Z91fcMIdFdMYrdjNI93Pc0PuzjKQSoxkVEny0cg2KtPQmN+ZfIkE+YCOLQwG4rle5aFX
abxOhgCzTAtC4yt1nSt+8qkIsxlxayeyI8QNqmcCR88UinpVz7phPonyd2TjRzKb+cCDHnSHYM8J
tRDv9JYy9ePuR52bPZ/7PP7ElpM9lg5kA+tXe8aABGBhxQcT90gwHNswCZXFiOP89q6cYRmq/ZoN
AbHwLGxS554mtCUiUnDcK3KKW15PSwEOHYaGgxZfajgbTrJa48hGZ1oo7lI+nyVgJKIX4wA1wvkd
5gywogoh/ihqe91jRdaMHTyUrMgO+Cz1mu+knsWRsMTZ8RPhsS8FGEnPnCuXspOIbZgrAAxRIW+F
idyd8HkjryOGJaWie8L+s0dz1QWGp1tbTG1v26RAE2lO+GmZihf4tYQZfpUGM8/IVdSX7sqB7Xc1
oOqWuujjaN1baZq5984azUxIx9jMGQhbHF6F6G93u9Y7mZREz5h8Rm51spuJr8xNK9f411JudHUs
qpYIDytsEdsbgiIt7a00tkNlX9X6C9/vOFd1v9R2o5K5JjmevktjPM7iaYjZSnmRJA6XlWz4vca2
aUurxKPLECmAaJv5Rci+Y9vOIObgnySZhb7IyojdjqgenoyS4o6s4I0fL+W5vM7PgHybhxUa/tEx
649O0a/9ukZ9kt/Mswr2XT1jQEaemzaz/Vu7xC1dso0LOBEZJ9cDvbkmttpU3ZYI7rdVT8evbAXZ
jEknoZvE6A1gAg5JOq0VsiPtOJANqjCkAoBK4Zd7tWocfedPk/03XxMHsLL2FW192D73bSOJjhDk
Wldna0cHkmatqgYXFYqe+IEqSGa2JE7nqAjCRN9AqNYAYIiOu1aJiBq8cAwT+6HELs0Yg26N6EcE
eSMEifyusJljio+1TIks88DnawaciqpNBx2L6iv96j/rTp5DTvQxX5Lh6nk7eSVeWc4KHPQm2mBF
Nm49vF7kbUkiO1YORAlf36PefsOta3VHSk30HbwjWNXbzU3VSKXOaFCfnKWbl3yoFtJWbJAJWUG1
0GqbhRkCsCI0YkWaTH73atcVrYqYsd0qAkMqbc62kEGzYB1VJNBQ/guPh8J8vf4HY6zxVrxP0vFN
4AhrACpj0vPXMSd0e05j9fCVblog04GbHxBlc7MM0BKYWL7kh3fDCmNwMNQZM1mgpTW+uoTl/vAu
w05oY7I/e0z4mN8JhTJtIXTMqGyTvs4YKZNKksUh+Xdq0RDh6XsG7MCtT+1dNNgJdi3Lu+Ygf0JS
HBk/cx2sjN8iZpcZR/Xm8EdDQVEpRBPHm+bmHx3ddifbeB2yJReGs5ISAJUI5O2ZYGYKiokpol5r
zdHOIoq+TOUkLVEzBXeO3OIVdWS+3lz8tFm+beY9ezuCaO4+Ct0QiMfHybwnMiR182uv+aA2AycG
5W2tuNLkaV8a4nTCP9LszNUCw5TOaa1NfBQMLerqOjH3rOZGSnOOpR9mAE66jMIyceBpedc18P7h
tuXfKOWR1Z6tOE2eXMwH1SKBWCCLEa45LplJ2R2O1WRRi7Z4N4/xKLJbBWpG2lYAKHuuqPijNUMV
XA3ts5kzeYrySbq3m3/5VcB+tK7ZEtG1Zr8isv/eew61YdzGXE3IhKGsJMEf+aTKpXfb4G0DIVTn
k0NQR653uhgdFUoJMMsZuMkafVwfqBNEpwwPedSV6Rpj7WnjkhC6P5We7ib7C/CFo151HALBTj1p
hhDg5a1jEzdICU6v9GBdCDpTlM790rMEKzJIBWDv85llQDggTevOsROAQmfGC4ABH6TU2fVO6+sy
aj46W4zG1cbOIjZWoQHxRp6sqllyqkCqbYiBkjCskWeAl+ApIN42dyP5JiNQSWANyzPv2rrPaq9n
HE0v3n5Y4W0i+Vk8eBukOguqnkb5lkQMWUDg4EEgUjDYPIwoJa60w8uq4i5E/lqhMm2+aYCmca+s
p6MTAQdOQmBzU4oHj9+hdF8r4dNb0NR8gukaDgTO3bG5/2MfcY8vicPPMhA8Lbxiu/A9bH731Rvi
MygBLzeu9A39F+SSrxPVK+suWh5fyKAKbqWN0rxuKDULy/tO79RCjUHBqzlttbAD4+pgISygpFLx
EYd85cYrApg3vFuegn0E2Fp1N6UwKHA10+i/ENS2FqGgVT6rQhcTFAx5tSpntmHP33x4KIH61dfQ
UNjSN1VIncKhc/6uLVPzqvVKzJYuKMAhv+YXS2vNA9YddITgbzbWw783bR4FE/hNEpG/i5tANbIk
yg5qiacIfFsRNcb1kBnyJD9DW2NC4saO/K7sGLRJOKadmMWtUaFW00i6YBDg/4FWbzEQ20W8W0uo
ol7lGbnVRe71pZqBw3UrILBTHKgAxkVXeL4m16tUVA39kQ4G0wVNPVDBq62f9z5AZ9YDb4dXPJtW
1qrvl1nsrYjGz92QVNnuqsjCKqgC4dD2/Z1SL57vXYWuPYQ7rBzFXjdplEucFkYwTPUg36Swe6nG
KBp02Ch2pOj5q46nSQxqA6tMuVOd+Yq3U/KaR8UqN/irKEkn1px1XvDPYVxq3m2n0QaTfDPchkLI
BcNh8cQiAe7Nyl1PMEoRToIQ5Cf0eJfQ6vEpTIlnG91gahMri+Na6EvYWGHPvKfmBPcDI/dZZFBg
2amkrUf26SOAuxTp3sLs75HgZsEPwOGKnHwDyIV30+iwR8EOYLNob6MsF0LJnSDyU+l5PG+Alvj+
ccI7W3VATGRP3A0eSpa8UnBksvlcF1xdJKsLHrcjWlzC7RrkHiqH6nku4+fv3nELXz3zNvT6sB7l
1Dnfg2uHcIz6VWpZ0xG1zcFM+vwRkdZmYCYUqUhJCzNpLeHwf65nfSFJj/f0ucoJt8fY/gQ4yNqM
2y22KyY4va+6wldPidNsuucclcbv3l6cEeLFcT+hyxPCjKcityahJp5Fh/dCcLXZGqXfQseeDxeH
KE00e0rS/rdrKE4oNWo2PvhC5kJEFh+e/Adf1APIuwz1wha3rDRwxeRDIGx9zMDv38WN16gPzL+1
+2eYCFPIHsfQkHvg3E2ufnf20PriRS5LtbKpwxXoXbTb3eYyzsE3axdre3UQECH3AefVZR8v9g/7
95XmRP9IhB2KaGh96CPJIF5poL8XrJFofkOT4fGn9zoXq2IkPwyY+DJ9TLsBBWaDBNGrCnT1We21
kbbpadwVBL55t5EDFcLrn4zW2HihzUdWbUZaV0mY4BgMmZJY52cFhsBa0mawVtdBEayihOsDsUDw
hJWm24X+naDT6mkBx7hoOrETAgleduAyT9uzRPobC1M9zi+LpNQW1Kz0PJiZoja29MF+NiY1oTh7
cU0JXrtH6Y78CnuOWih3RXDNgSDYS52qpg9Rry8Hx+N+7A7dfR7bWLGIPG+/1FOrjSbSBq7q+BPP
ecEO3KDFQoKZHFdprqOSPV+GBNS+/2fFOZ4yiCqAY3qT4WjtKfE9P+je52YKfRC2fJcTf6GVSzSz
Ld4YNd8OtGkQ+btDfHJ12///vSnqiFAauRm6JquUGaoiknZCaPwFXmaKPZTeyiC35AqpGkhgSaTw
gAdoqZgQG7yVOV9NF+lRk06oQF7k7zWcDurXlONJeNZZNNwdkmHW15VjhCZIXQocfwjRtuWMH6ao
fy/9CdNQR5IuVgzAeIxKjwdmLrd1pxpvNTjJ64+GPVtld/595aec6vShsx8Ogui5+8UHE88WSuyE
wxyFqNMI8keEU68suDZE+xkepWycXY7Rn0GEPtRgdsLCoJkoRnT9ugAy4DyU+uriY0BkLYYYJ8Nk
/57Vkl9u20RwcQ38xECRXUm0VMzN74vjgWDBERuHkFZ1qUCxNroWJfnXbnx2aERif540Q93cdcG3
socQLOkKjD+CKGEYIb3fVLFmGp6o9DEgeBvwy+mSLp2J8abI4p7uTKQvwELgN2qWsDSUHiQFtG3c
FbVlVSz0EH8pfUt9bM4v108R2Tt6SSPKlgohTIVjHC/B9RTlA9wGDt9PBQIwlqrlSzVaWJJXOh5n
oGqripWHmnVDD2rg/AkVGIoW4K3DXm3QalDs/C5x+s6dBk8agHsY9PEs3jE0NqXdo1fiHxLlEpUY
oMED+igXZt7/8xxDPeLJpJpbjF/fExx60r4BZikp6XoXjkfQVLpCHyT4bi1NnrDWqC1NEHBMRd5x
nCeaYAxdgEhUft3v3sz9SyAFwQtG4UZpkpl993rN9pZ8I80e5TUEvMQSJ1IQsTwPSOpyhA81VAbi
26p7NqbkWMlXOuf0A2mLfw9xAHVQX250wGukHsMfTo0YVrSGkxXb2pQD6nu/G5ibFoaSSX2ld35P
D+vk1gqSC2i9d7bGmGv6j5fL9jO1lXPrtgTZeKoWvb4qs7yK5/WIx/qoIM65y5S+ZXBO78bpSoza
DABOoOnvSzRcQ3QNJM/URDXJm9J4wWdNJti7TOpDXzuJIg1PFKLTcMyBFIS70JNaU2rIm5wnqkBk
+IStkkqkDvIjAm5hcY/R365rSQOsIhI1b+lxjBd4YrmXh0H3MvuS2CKAICZ+Tc0gzl3GEV5tgnrm
gsuFopTlefOqu4EGt2zqlHrQZGz/y2v6S2EIH6TE3Y0fe/Z767A9lU5lvFj56I/+4SqQbyUtPZcT
FcyE4UxrvtvGg50LjWPi8q9SEhW2BK1kKAjjxW9o/WdcItcImhGsrS8L0cSriiEAKv5PVJHIJROg
huRjkhOcNufW3GSdPh3l207uXhGR7DGmFxxy9arEJJ7yleOky8d8CFhx4mejtL4pZXCRgzK8xXT9
mgAFvDTPM4e1dwGGGyL6Pep1w2nqyUCDd7PvBBiirTr2KBZvSvnxcu740uiSFiUs7UsicOF+QCoN
vntpeea7I1Kn9OTP+dsmE1Q+52lP27285/nFEBu4iyOvxLlwKcG9qIAE81U29Ah6TIQyt285z0LY
kQ91eVNjHGy6wIt2n+50dSDFb8f5PaMxaebOG/7cSr1OXlE3PVngB/96xpEMe4guLnGttwcIFsIB
gSCecvYsFvZIZVVi2gaWBQ5zmOaEkMsu4uDmTgXQGJ3u1Y0tygNwmDWdwyXYNDVTfVuThOvgWgr1
L5soEdK2SGo1l5XP35op0pqA2tZm/trbQEfnlwpenzLvZgUlz0xJTSsiWu6F0kXCPpTORNtjIO66
aAmDmZUUJLx5OpzFDq3cd6A0/iG9QmBZQhMQf1zSI4Ogw3SAYybQ84B/A3Mz/lCVG1UyfthpwM5k
55VfT/SbEdAbowbc+KVWaaK9yMPKEZUIEyYsfv63g4pJXVYlH2zhpmxmIqylS3ZpIz9GB3hy8nI0
M+JrGX3U7bBjQgYcx2/4V2mT9fB1yQbYR4UdY7ukfYCvRWc0omMc8xyGI0XBmgx+Uv5pihDChlHR
/WZgJyQSuAjHt9EpvGsQBEXLbpoEUuKHP7YOkSSvwyLNr9gZK+7JQLBycI2ya56jrdfo0u1zMOG7
RFl1S7xj8g/mfVlhpzw6hoRon1BpcXF9S7owhVEhpfNPzN2iVU+hNnhv+ByFLd69YE0FLoUU4dBi
mtWRf+WNHcFDJbuDok66AcX8d+m6vyzdpIpGaQqQSALkR6HGHbATs3jwYnQFKs684Nwn6TTWcChm
NKqFiUywRybgQ8s56vT9lN3OAVzHcj0vq4l9EwQ1gWc2kHlVpOXjBWFTCVmyqW/P88imwP8nndho
eCmnZzW6UzIrZv9WhUNit1RbHqyE0LaTkOhn6ELaPETrkYY+FA333Qr8enLts7E4DMCHvuk7dgA4
UWihqhNfoCh4bcohnTXc6sQs/CZzkfnznAlb6d3ci30Oq1MlUNteca86mGN4CUd4BPOkglRbKTMj
S6VFdRgdhCsrKvS1MxQswmsYt3NubqQyKCRRSqCPqumqTRG5nZ3TO8PQ5ux5DULpfR+sv5piA1Z+
moEV57Pzzbk3U+uNzmXC+8NU+DrqoyApe6Tj7hmvzBnOv/lg4C+KoomWjkOQZxdHbchTjYHwg2DI
AwjRapoTsijLLWOTyk6AnC83XhP0qFqikFmnypnYSELjCb4ayuz1iK3KYBKSuRofrKaDF3LqYypB
IjchI7u/ZvErFuMN66M6kAmqN0UtE0ZccNjlvmIwbny4FgcwUkbAwg34BeW1EO9EbfgW832gWMVT
X48quDOL6Mgb3/rasK+dITjrtA1XImndtTgUaM2kjYGxqmyxchz1z7+1TxB6UfdbmomO2vKqBYFY
i9JmVxf6EkgkzrPdR2VwVKOijy54AxAHW9fy+s2yXe5U3ZhPoe6W8Hml0zydrMQeAhvVWcDqBtdh
hyxIB69G6kEQeU9iL1DPDM6U5a17kq+6aW6+EQXEeNORUX5izGL0+gRz2jGMC3hJYa5zbSbES/Q8
WMfwlAGCQWxCOD3Fok+rYwVy4h9CaIS1+KTtpEyZ2H5TuWhItJWZ6hbh3D323U3ZWwxHDzJOiZSj
hkNlxyE/SdjE4lgodD2jlfHuAY7eMlRvxxehib5JqUux1iR31EC3/FOWHvpj97znx2ZO27NXJrWr
6ouxadOY3sxYJp1d2T/dNndKC2XhjpO0K/T/1leuip7bzfo2CxRRYUuD90ABnJuRCXmhGRpy2v9U
6dkyAWHMcpfixr2nRQFDEKpfN6NGvGa6gQjChcF1YJj3U3DIJ5tUj9I0NHJurFMLXYOIkvE61nuJ
fx6YNmYsBUbRmPdG3gMbzPlIdsbpBE0J4CGauV5eI9VKLZy8qhD85zco53XGqh7+/kAItnjY6dgd
4VZo+SW2BvlwGA++yefXNPAgNXF+AAUbQsmB/hMbstjEFyGKGrCvSYNPP/cQcxd03c46xg1vrQeZ
rNROJamJNhRGEbxD6gT2Sny1xea2Zv2ABjz5X0EebKCfxZZnU0OqQCpSG29Yv4aoFf8FdpMgdhA0
tt0uQufjuIwyGXk19jPz3Y9FAA/jexzJNZeNzhkCkIwwkxjD76Jr7ffjTJiz0dJ7aYV9N5FG71kN
1du0vDgPwc8jC/cF24KBbwZoD1kOK+dldfujwA35hgtdbd++7xlvPOUbNtpKnJXgUUrn8YeLsqwx
OqoK1YZi05vZn1sENSJ3M1NuIML4XS3l0FzjA4NY6QoMspA7Nd5StRXsIhpcAR2UNBAhJlX2zkxX
my+HVOczmKcb82+MbUK7XNs1UTNIz/zLR+AW7/ioPX0u/hNAbi5aL2nxOENfaQ9TLLqAQK7lS5IA
bYYN2DE6gfUdhkyGU74Yt4McJpS7EHeg5nHjySNJAmMfT2Fs9pER5gLileAHLwsqF3/96B9CIqxs
Bw7D1OZr+QGxUqPdWSuNqsV01ZdZC7D6IW76sruf63w44hbDPBVW87rywe6o0kpVMa1Ci/YqquZi
hXf47cgmZLrDOYpC8X5AB/pxhBGz3+RRvdvSkCWQWGOEGWzevhp+C7UmZhganxwAbCPT4OXIibu/
7vnGiTJXrEP/5tmty7VDDg8xnSpzv4vHkZGRcBRZlYdtFfr8NDVunTmBFYDNtvIICU6efe7FLObg
vfYEqiOkT+ziy9bg6gxtUe2lOlXDeZ2jc0G8ZzmUE7z8S9fsJL0oY6nySdgoDFJVzFKDzSVRpmeb
KJ7qmj5r8zWElIgIgKompvBm2rdHf/5zxlqYEnRNnkMVbi7ecVqpGM+f4aHAIO+kifeeLsryToPM
BRs+G+cFK8uwtKOjYAWtBYD7rV0/NwTny7b1fI7+HzMWxxJ2hlC7dcrQnLER/LlQADmZql7SGwjS
HEOahRB4JE0QP8X5Xp/0Q5C41i5FkKfznzyFKmTkDU8vf7ZuIGrmJ+SNPG29F6KkfxUxl4inu++c
7h4nY7zROQGR3dIt+ZUIHJJtdfEPNRsamWlV0NWm93tfFF//FPMIdI4ZPL56EOj1tFlLgyet31S2
HsRwv6HQbIAUHrN/VzhOIURru2cen/HR9jY4AzTa2XUssaynzYDFkU+Obil1JX/jHkH7mL0qGWdE
hnoU6kgXNjYAU58qGwobutF1g7xQAwMDwXzdprkbC9FozeReX4qRTWHC9rLEhrs0EOuwyDbM2+QE
uPHVUgUz38M4IPAa2xUKRwc28wLjnR7rCOcbmqu97al5pd7rFMWb1+6kPJtdTAoz3kTGpiCboLTu
W9+p19YZSmsNFR+EUO7ApUAXYJttR2ItIpyEd6RJDuGlAt0gZ19/dZsF95w1Zm6nuE+Pf4gNGB7+
jS0PBYMwUP8lMhxfL0JtqZINWeAO6ozv5PWkZbmibNVFXsphbiVyJ/klRo4r2es5jl+6eGj759ij
BHJTVlYJmpkSaEfbN+38VqDL2RdOqxUeUZian84cYiVtx4ZxEVc7/JgW4QNn/BQZYkzhj4jD/E3B
AgMnuDKK77/5oqS77e2iRuvso18BhLnLgAzauAjj6Lv0pQzISFz1DdGD7seSLBC0psm1B91kWqNx
a0AyXKup0Y6CI6NU2ac61wQHrZzbZ33Rmebnc4gIk5ni2JsTZZTDoa9z2fn6OrES4iYXVsaa+xmJ
IfQFTvWOtCRNxFhDXPIT0annNtHA9kxtahDqwGXZu3/PJozpKJPeyy/7u36x4JnP1zsh4ZHsokGk
pEOo4mUhKlR2L5TWz3rU/pCeYVyY/fps6WfgPgndvaVaOlpiZEXxQPtoJDRoJgfLymXVT1pIj1dX
crbvZiEo7nPMhvnoE6ai+8qmmIY+oo6QtsQmrbBk8wbITp+6+VkL1IyzyWccb7wstnUUHWyT9hPL
rbYcokhCGlMP2dU7fT8eihEnHvPRXvjafMzOyOXAX/zclcOwPPvPa3lcT8GCEGOQb9ij66ag8pLB
qljZzIiOtB5qANxGETQK2RyOOvmNs+N2yN+j1zq8NG+1syd7LyZyQ+xnXt4fFTkqD5t20sGQwkf1
qWmFovOSUDIw+Y85Wl5jvuwQtpRoQ46IsA+tsmpMC5E7yMYwe5O++rs1ANyINyxDpQwZAFk7BCc1
SGSU/YOY8TwuZ5hOmCEYzd/vsEC5zQzBm/U4VMUev7IC335qqDc98fFm3olQR91R/ocXbg1Zjs8Z
vf32a5LONVmphJduGAmD8AenJylu9cUttstftOHOQs8Cq9aylBAWWiV/kNeP85KfqEGAPgBJGHM2
2ta1A5Qsw1UuC59vHhZlcAlx32PWYlLJSGRib1mrM0o2r1Qcl/efPr6h1VNfd5LRBAJ2uN66Sq3L
TRuRtM17rSyTtQS5+k4jmdrGTCok7fnVuCFM2R36f8eEhos9HPDTh0pPTwlxzhFFGxJhgCgFcliM
Es/kyTxRK+QMqCH558jouuIbuUVM6Gs3ejUZbhDQ8rXI0ntG1pQKmXlPG7bt0DGl1XEpxegKXVXR
ZErVuMkJmuOse3kMOyUu/8B5ReMp/Gy5ntnNPJhicZhT57K2FpJXAaq3YcF8ZTmLPbfYa76SExoo
fZEx1O7ipEN98JUSUIsQ7AyPbzeQfLLxQax9+jHjCKroIfXStou0RIl8qy+xNr9p6IvbAhdvB/HX
TfYwQ3aicnWLx2YXzmfvEyXCuz1vqOU4+D8PbBVS7ogLWdh+Uor96nwgg1Sx1TN+M6MoZi6yhFqu
98to+5YCQ1AjeoWujWWN/rsKdENxKHtLynFoPaMNjXEanpXFEz04xa6hmwWn99VsOaJSCBz0QlO8
L67cdmnCD6I2zwCkGjIuBxuB7iMAS4Ou7+68rsl3nDDLPa8LIufZnZ5/TEdKcEn8/tzwQKTpDrL8
E71CsswFQ6iuuKcFijo08ixU27kZ9XBvZLZmXu5NMy7RvXHBFyeC8qgUhQBf7EZonwQgrB0p2YKX
j6TdwwkJ1t0VWAV0aQ1aJ2UD9dIctQGDwRBQd8CYcl0U3PV5hQ+a9PD/rtA3akR++mVdFjZuoHzy
rg9sMKvYHVE8xhQH5qfdej8KJEd6mEKmH1n8dr7ItB3hFAjELz+0BKmUnZ9j9IUYtFMEDj03/1Tv
wGyOTOw+pcp073oS02Hydb6CVpKdPz4UaHihUDs78uRxWNS5X4UgT5K2tWWvp6vuXpUiwbhsMeTE
f33P1g9q7P0foKdDOLdOc8Gy4jkEdbJOXevrW6LLZ1NskaILgXrcZKxDHMurnWl7xR6rp7oPjtY0
K7NuvMuFoDahbuWzbvZ4k2DExjE1QeTCVxFRNWuqO7KjOfUWkw6v/mIJ0snRHlY59KE1MMurPnBt
KfkmbUYmzDrrW5+sTxzd+O58QyX0cLeayUMvW42TvC3jpSWA8eTTrRT12q94QXExYtK7trSpM/7l
TMfR1TbI4Odl1Qmg1HbAb8NB3idfnRpO3PuLEp4fX1pnyI0iKPtmsSUSq6WCi7gJo+yYbRAQU3yW
FZUGxyJFAKTSFmzyRpXBy+rlqy3tL5z+nD9I+iRye35dKYYFQudzxTd9QyCrp/eAYKzi1OPgAG8W
UDSY39wMntDDYaGGtcqnyzRXo1MLHa9lMwEmlON+1Z7q5lAWD5U0QB3ro0i6KBr1Kw+CaiTn2gsT
c/sZGv+0tOHxvgtIUYTTCpJuTApGBrRHQmZVeB8t+QTDg5DLQ+G1P7Jhye6mvqwqxiQL3njHSvXB
AMt1VbwFpXsIM+vU7t90g0wnCplC2u7Wc2YBqTTt3kMxS2J39eW6K/MTmN9s+/bijKM09hpCm+X4
14IoWn0M71rtNcckqYKw2nMVNn7flDwuj8MBYRYZJFS1Wq8habQ8MignQHRtwRlaRwhejapiYhh2
amCbPEmCIaBf/D+5S1dQzMyyd/0JGx9CeV8Addu3lrc7v/8Oa+qIEDfQV1VN1dVJN6teLlgclQaW
vg5qfZ0ywnzSbTzNb/ayfy3iOJWd+6a2LTdBmu5xn2lBXSPfDatsy0TEURMZXcoX0oCXX9fpXVEi
VzN1S0/ErESJuXPZS4PHcob3m5YH7gUg8+Bco4ESfYizNaRX5hB6Ta++95zthr1FAIyJ87rRQQdw
9x+Wb5n9AAGT4IKjWfPM30mzy76e9wvEVgFPxZlZu7nrUk24Et3C9d5HeLpTEgyanHrw+0CUeCfB
kvFBnlUqNq2+pNCsqtMy1MNqLmMK9n9qdFnoD91+YoVsiSAk7D6HEzMWFBEw1Rj1EP71KI5T/6O7
qaLlxJ5OPgq1sRydOzA+Tlpmv47a1zsCE7vDbg96PgZVLSuVn8i1uRI1O423bVBOzuB0MCHIDD6V
bcd2EPDN7HTStohpEzIgz3UCsIJ+7xvccmiBkj4EW5jG78F0XiI1E1koBDqMnM1BI9LAvZDL3O04
9czanHzhdvX/8HnFX//BB7TGRnlXp2guELwfWqKbNYP+TMEjyIm6tBGAmJatm3MyvBcL+yi375mn
nMP4GztupOFWhJ4cLsXNdPV/b2HUJeRrawfwKVeJ/Sxq+rVsY++/dcfNCNwxWV0EWajUMs53VE1+
k0pas4olvyuP+lZmXwa96tAlCeX9xgVnV3QIvvvUZ8RBxvYtpCoJG1QWxnmgKrixBvGrmPZfuo/p
BHQ4PepPmqIVXftf5Oxy5RJbBbkm/XmSK21aC9TqSePFFkPTb4rBrYOwM+07IZsdJ8iDmjKLX4sL
1AqDpPrBNgZfcRCpmpqaMg4ypc0tDmN8lHGevShOVSlGZZ2x5ERvC1Wr6xrAHqRFeBipet9lJWZg
+M/OSlNvLgtnrzhXwMzUS9J0vsWJ2a0g/gSaJtWq7tIJaJOIxqMtXzF5SzyZxMvdNvM9xpv7uAVt
gTz6bwf6wu7+18ohLLcvogkybMBznUpLkHqAhmWrzapHzm/D+zAup8kv2cDQHlPTKdcTvF6NG+tK
bRrmahfF3BSsxVbV0bNU24UNVr1BH9pSYYbDSP2C9KxPtOg0Dkl24v7ix4XfneQj9UPVEDVZEEwY
kWthW+qdGlKAe3C1oV39WHdpB5/jtm6sggprWGxnYVMaWm6q8rWu4gGmp4XxCjmMyFBpoyjYm/8x
eHqKL82pE2ZjzxCkKMdAcaYHemiLJS73PAuexOtN2qCFRbzpHekOUfwyzXsZP8bpTX4T1tYKmRE8
vIsQcxew9jaOM//2qRoT82vpB9lZDFODozrgRw5kPJMyH69L3+fnQZHUoGyQKevPbEuCtO96X2nd
J7hZwJDTx98fCtvP6yMTfmlhaNV/pi4ytxYWi2gLL7By1+tayIiUY8hwvKnjmskoWy+62Jk8ip0m
in+K1JuoOknK3kEaIr2BhyWXbZW21jETTFDrafWpeURGQi/MSr5g3tpsH1oYYabdUu6xSBYoF1mT
sdKjqNGdRH4ziCxMLXyLUx+KrDbzzvaq33YBiV5jEN+VNn4dSE0RX5t62bgwrzlYQPQgOkzSlnsp
3Q1JbwLBkvJiAiwfD7Clh1PFOp2X8+yM3cWYJ6ybEq9+AUwZC+UcGU4cSUUVLvIftbkf99zf1QII
5Q43f89SUwyY2YEziMLiVrFyaHYJjIyXDuKM0d4JM9UYQAH2WyE6FA/4/fJvYWxyoU9zG80GtKHg
rghFbn2sfJrSNcRLipjP51Mj7Xf0VjccJKvJR5E1+8n0MaZk3qb/Kr6YsDJvMqqIox/yrn1YjyP8
GYtkYvt9rzUHULBp9eD4JRjepouRUSq4h1URjtrc8ZeWmOz8Vuy/o0/oZZ/N+bb6SCxmp+lv8oBS
D8x+YfE7Ep8MfW7SngI+QA3NnvymxKUhdH6CJkqY+/32OjFXhF/8iYKilBBYu6v1+Wq6re5kJgl3
36o7MBI1SUSydxtrVAtwHBnwbUHTRpwmXmMgYJCp0HrwmPujSXS/oHheUZAH4FXRWwhWyRNaCsr7
5c+ZRJgwVpZj3kgtIkdSfhbBz4nMFypgG7/lWvAX2UIuhBRPMVNHmKjnl7eTbjII/u/1PUJbdMlP
iz17Wxx8lYgUZ+ZSi1ajH+8sVYzKhzhgW0lnJmtY1x0wJtoMw0Qh2hblDkXl3EWtomJchm61UlRB
qmeEGrKuje5iHGHo6GjlKfyz3zsl0BGAzSaH9SKqhEqpNfgp6W9ddjLUnKgzIJN6pDs/4FD8Ej6o
JZiv0+FYJX0bALpFtRvvktcO+KIyMAmdZTl9uTBMI9b+LhT68Pxr3Fls2KX5Ygy9Kv6yVPEsFGJ3
n5VTgFYfIk9ehvN5xpcxmQnkQguHPQAkK5HaOm7TWZ7h7hP9kd/FyDY1oOvynYQyxuUxZhGALZHe
KVBwAUdu8rwtqY47Q6xLgeSHHhtdFQvCmnmUfMt0gSZ9btEtV6vjP+G5P4HxgS9npnkETEfBEYew
qsUJnQbRvk9ZedGw2MGQftN1AeUctv89URu7symUa6PisR9RRbw922tzFi0C6q4J4rPBVA232u9+
QdRmhH2Vo8LLxDZfO6DggYE0g65mn1QmBHXOEdKOHZqYuSZrqpxHKZ73MhkoCOJR2waNdGo2No6t
gwxk5z1rexFDBXPoX9AOa6anDMvMYWiPrQUGhD4lJZrt+Iv1r8GniQDePnOhrzCOKl5619RkfYHs
IxeqU36dmMZQNeZVL30uBd6BO4/8nBJJxbrH0kk4vKEOptIS8P8XwXpiDivW2NR6Dcu2OhzRSLmq
7sULpfYYCzZmgG6VNCC8oImAEyLYWkNEVac/EkYL7YIyf2gTPPmbfKBs1lRpxbcKOXj6PwY8RfWU
wai8x2RbkowaETPvPJGsvaQcSfBQDpPu8JG8c1RFwq0kWp/s1r6ifmIQsWvBg3PHpJJu61AH1XfL
y2BvSBXERnZJHCz4YxBpMTYhk+sG+KUPvoRYlaOt0iQTkxmsuBjaj3WebNUaMqOlYpvhfxHAbCT2
RfqLPOSKAnmiryCairwTDzWLTv75JnEDKYVXGzB7RBgyutuamV1j3b2CreKOwkqwRDjAlq7rcgqu
BS+mDT/Q9cpKXcfEJRjU7eUKgA710YfBLDuvHBNPT7iMhlnLJ8ayspf62mkRoKwBwzpFOA0doy7U
UhY3KLsDbJ+nTU9Cp6+oYQYxLaQd9jznICVyRNJUgEhkmZh6AwrodIR2bL3zDufwS0hRGPURQORb
l69FlG9c/BiCPjWcuqNsFbnTO0YSEI+1elRpJNTlG/CLlYo2oLfGUds4nQClEyDosalFea+TS+5X
4v7/hUobBdNCldrtvFIoZzNcC9CNExTe8+fkZ3ttWIxuk+CiymnZMA04a0dPz+j6Y+O+UFGhZdpV
fPlZ6BdegbV+ZEnXZiuojivU+aa2qTKYExKAIn1aE7NGU0k5wfCfnhHoAPFwqbMownezklXiYyWr
2/eP5e+39lkN5IP0GbUc2hZT7uVwwKfWuEG+l0oFl3i8hqXsRVNKqwQdN7TDBTSCA29Xh+OxLiJ4
WIgA+mzhsrX90IbPP89mWpqGNrTrK+VzxBZJP24hyuDwMRCQhAdNtbKgCB0iON4vvcAK+LLaoesh
MA6X8vFLZrNMkWFsai8DFfW8sdaRsHDoLUhZFKK6tBCkb04SdqdRjva423jKPtYVwVmaVnf8WdXt
NfQmhPu8qgR5JkxPEF91mEhK2sXwnMTGYtxHRtUcnihFxN00rQ49D/xZPD8CtEPxPwtztZoj5GeP
hFhDVvA/oen432znWAP2itRFZxQd5l55C88CP94l1b+V06oGWd/8RQyZ/E5L66ycZ80yhGnMCvev
Ve1AZYsAi0E22+bS0N2/qwlwkrpN+z+vI497q8INwTWkqHPtFu0hNwSYyf07KTVAMSccvzpJS4t0
qIlEj4gOd7MaJsaWRlhW5Hkx62bXxF6c6wUDSO1OvqHAvrWQym5M4l0vquT4KlpNbqLtxa/iJD3b
0DfPXsbpOGAS5HoMA50hn65ZmGKDJz+DsULuMhoQBCOvH4T5SXUUwTbSgCOpgPWWiZKAEg6kaw+G
IwU12885XsJtpeNAKTRewFgDGkBEzX8yyLgjf6FqaOqXJsc7X7vXX3f4MLuBhSsNY56oHALCMl4V
yJn0zu5ob+vGwooJKmCq0LMMIV+p6VgiU6VcQXVkgSR6kdKWLKNjUDSO2KZTwu6h+zxulLS8TQP4
+/uhVAjR01v7dNJRIorwoijR/oGLd22JkQha+qyb2bSYWkSqQ+SRsVWvwHnExkismrmU/SKQI7aJ
TqrLZF2B+Ry2p1aqwi0mMGmR3CVVXepEyrOMRnfZltd3D2wLO9gR2rJcYsoo2B1w+D8PYFDOYTQn
YJgJRQz31Hq+bMuGJ4JuLSHfK+d6N0PmB6q9Dc6jPfuKVfOBP+6kI7cN7N3E9SHBJ7VDuXCT7OVH
YC0z6bmI9nRW1+Z+u+NgZjyc7M3dI1MSGY4aPH6MeI29g5hS7rJnPLvRfP511RGO6gPNy1jA0QJV
vn/0UF/noafNlPud+kT+TnSk670OFSuHixsWHt5DMk63N11I6jr3/c3bX7hgCyq46UgxUbeb/7iD
Ggx1+TV/BIz+juJirHhCComVVklrj4PWYcPM5FhyjRPx4GqZ7uOQ3pTKNxFWc4hXPPdiKGAjz3Mf
UN28j/ryWPJZJRJ3/5Lk5QWRv8osMDFmmSYff9KxJ2H/C4sWhyDG5iX+O4JjGyvEiKFKz568Omfk
S6i5qIAHQ1pXkukrbtrt9rk6ntNDUlLWqc+bp8aJtNFjhvidh7/EVfuwGKU1ab2XCGHmDF8Q8Ibk
gn2b0owGkEJvIJ4QRx2JGhIzHG2KJo2fxXDYRBIgveOivM4HeO31aZgsjfc3POM+P4GEGVPk2+tD
+3aipEYICJGrlGTpBTw+Rgq2Zy0uRRXy9QFMfFl/dqr3y/PR7MAZw4ke+BSiTjpq77UcD+ZUHt/o
r5IThMyU9uwH6hetHqkcb1df8JuG3eFWuB/9lUJmgXl7jsvAACLazrXb4+XU3+SQ+L/u+FQtCesX
+lLV/nJzuVzfIIqIIPkKYOSm+SA3uZ3KQbreWCRfTQhoW6Kc1zyjL/JR6mxsQNp61z/SuaYBdAn9
Qz1X4oWyhtGloor+1kkSUr8NCZ2B7PIF+oElyQPGbeVlDE/0iRzvYRDoBbCxiEUb4MtjJkmS6h4b
geGMTVWGy36Tg7N4fL4qZt07qp2wawuEmyr80U5b+4gPGjpoZjTgBWINokTAEQweDvByx+DQrLP7
TkQGJVR8uS8jR0OMfuukcO+lsAgwhYFQwILHZFOlPRIJwtHtf3q5FWMdHGhm8IrQSHgcxY2lqIdu
es91AyqcDdXd9lfjY9Xfj9Zf5Uu61SGXRRzwyxDjEu3Lnt2oJSp8clbrgiclH6n6IXCYcWor+/gW
xdbWP+LYsgOlqiwmSDhtTO5OHVtdZzrgMhWq+gmFbrxrbCTS88aitOeaPqXgXULJgWjqMcRFxKr2
Mn8UYFUjLHBLrHNBMD10+++EquB6qAV+fEvUTWxUjvyqdboQkjCQAlSkkLwfljDXhVd6YrNvPFof
qJo94bmgfhKX6wolRW2ezoUU4Be3x/WiYKiWvEHkJHH2yw3yS6RBGwBfHIoVk2RtkyrZGHwSpjah
SlTJeBHM57pEUnYoa5Q4zTPfPY55tQZ0Qs/z3Uef0RnEB2heoWugWNUwf5Jx+ihciCxgUeIkVpyk
a6H/RqOxUfeTRgG80j8X5zeFobbEEOO+hGUqgCNkIQkCBR+awFK0qP1Fgj8+pazgEgU6KQ+PKM+V
nNrkB280dL0dPBb4nyDZun61IG7nxz46tryJmOtitDVboKADwHvMdfhPXhHA+2HHZOSwh608clrh
27cChwROmvp8kTGMk/PXaQrA2cAEfFEBeDCks30vcYvTesb7icGR9PmjlGamYm7tjSoynvfMiTgY
4eRlt9zReML0Ey9rARUfPTKHQT1y5QyCC9rtcut0dukTJDOXlN2hxk9nSdoryLjQ2/0UPB3BsLym
032qQZQGQuvUbpPvrB3I2shODi8djMcptvmwRQ4T25VWHIgicrDPwe5HVEy6I1gTB6e27eiuIfuy
T7/raNKZt8GjeiEgGXwsTvRw9qcRI8XuPTO7qjowfLSEZR32jQQy11HAolL9v+OB2vvVI28M9g5Q
Jf+E3z9p5mhqd4XEU6GaTS+srdsER+oVzOUcBsKWPYOyccCdRkqicS4QAmwm24Qlx6Do8QaBoQSk
+S+g2lJuDYfUSUZhrOJpEXiI4tq/q3ypx2azl9mgpSZzKKysFsyqBdjBqT2aAUx+dvK3VLsRZPE6
V/7RWJEkbliJz2suDnqHOhySLJQEu+V38UJSgdCr+5D4OTZAEwi+FT1t88B9tIXDQLHFMnQJOLd8
amCnOso5CctFtxiIozoJ/cyL+OQ9J26+MLFgvizEWLv8yagQJH1m6T94vktq8bAVV2fgviS8EUdd
fCeqh3ensVnOcZJpkHwNGd+d/eyT6MswQHJXHSI+xPT8HxTzmt9LL9/Ld4WpvmJzO2vxNOKY/VWx
/GuUpOkxS9K/s7nMaLl0EkjEeN1PcJAz7nNheXWcejP+ZHG4ZeyLJz9bYiLPc6DKjV86Ody6xu3O
CW4Rgc/US6rC8mOqStDUgMNk2ur+PU49mHfUAWp1F6aI0RTklPA6NKadoZkzt+mAtdhUMJyjkqu/
jLQZATbezuH4JdUih/8ex6PJ5UfA9ynSmpdgY5/9es7oRtBjrEWXok/znvEtrpI5Z1UciLrt2N6Q
FUpRXV9OGvBKGqhG+Qog+wOMCD99BIe6sCwwS5rpGkbXU51xiGeFZrBJVHvjS1lMZrGPFj1jI6vB
tbpmhRogeV1kjPGFf1OauxJ4SHbyaQNl88EFZnjQcHLl6rxe5E2IoGHng3AM0VH6ktm1FJySsNBU
vighP8F/VsWHcKQlWx5+yNwYWVMUkZV61awxTDgM1/B8ZfhrCPbqzDDU278P5Eu1oQCaEBvUW+cZ
d0RwGyyrWuph/5jH2gmOjXQ3SbsmE7QE+2kfg8xXmjAQBNOCHOBdOINHMWuaHjsfddk35IXxEue5
x/tCueJbLhLMcbspYq/7BrFll1CAFLjpgp5rwYfK/OQFbkqqhy2TsoXuRZv8zdCW+1kuayDBeQ8S
SyP6YnAwcvMK/xfHIPP+UiF3/FU9juboiIZBnv7dUfSs3w4LcbTeT6vDDhT8xv56uEQNB5RXSr6r
Z6TDx6HypWo4aaHe5zyk29DBVNfCwxm1/6N1mvoOUZGez+v4pG1vHMgLWKm6a5oFEiMLeuaYVCMg
p2AyTIRqnniVyIOfplOAKOf4D7wu14PhC8KquuYNwrEeRkfv2PjXMMrD9qkDmeRXTIlqS/rblubs
gB4di+qHHMLkL1uP0an9kJGeyQnmvp/J2ovcDo8+AAMz5bn5r/a6behg5rEKY53JAqmQifrrxpfO
8h94+k2fwEL02OEciBIxMsi75vPtr4YCX5odZRptEnVx91pjss7H2ehQ8MSOIUtW4cxri4qg/XmQ
wHcN9Y+XVneXxJHY5HryiwhThTvmcaoBKkNm67JlS4J9HgX/B29Xh0cXOPfDm7tXG1quV7OTHpXR
UrTZ1/jg96QnfSV/62VxU3lGz7tzldVFGZ0N+Vv2OgBeFwRlWMQ0sm5UzWlUPiKyzDPh/vIvkStz
/J/tP7y5C4wLoSwVaCnJflRHjpIW142RqHfPclObZBvvrcxH6BCCtIyEkPudpW2ja0n8C/M076M5
bJHotJga1L8kOfv5zOghPX+5SaWSLFFgCh1uZyTw5G6f2fhV/MZAvWfyNX2OjYL4QQfjSYmboSc8
AAoeQ6EXyu9cgekD6ASUhII/cu7ek/vSdbddSFGddkq6jeN3VAQmJvgxCLcqbwNH10mg38jxNa9y
ONRReWdM+6sKWBn6OWxpKVfLYbnHpw0/EN8rYD0Ku8GUuV5BesCDRAc63kJtRlw6WD3DYdqhHLg+
dUg1784xPjdWWsB+os8v2QGdNJ5odWlp9wHN75NME3k5OOTFjfcVBIh66O8FhSJazmWvCKEYfpWB
/DpZn2KOJyuWZxI7vag+rabK4R7q7dzdogrx1dQ+5EnXeCj+aEQ/pZlwO9Jw7wuDrB6PXcCVm5qJ
vEGSevHvGTpCwo6OM2Xz64DnPPPRXEcSjEbMfvv8tdQ8gEbHiaH1eh8Q/qFjaR4JnM95Gj3NbPEC
bJ6GzNdiKhKspVy6+qZrN5+xc7w4gNaSwn29Le7wtUy+HtDnD6BCgb8NNvx6Ca3DFLA5g5sEaG7h
1D+e2/9v8/A93D8KwMpvGBxEGUne6eXULjMyPnQuHKtltNsHAgxvYuXcpJPgC/pEPQLMhMeGHCry
bDVVLYWwQCHv957Jg6Fb9NRwdXMtCxTz/sFpocY/R1sytIul6L/1J5HmBssygExV69Vj6MtrG/r0
1LdUJwpifoUHdEEyJ7JIT7Kuo8qLJ3ugqVYXZ8wq47jXGcZUbF8ChSG/wOLRpbFUaPqjARQy6wUu
d/c4ZaJ364xin3HFqTwAPi/XlG8k2nQaMbHT2UCXk+Gxs/h4891FMhI82/HMGBdMVJ9q+k+MIoXa
lWJndlJ7W/8CrvYU9Z6GcfUPBytXdjbbva7laGsbej8OHEh690/0t0pzqZJKLyMP8yxOSuvZg0xX
NNlSfotAK7PRgQT1bY8yL6NBjfbmFm5+53TXpL8Fd+RXgCwZ6UM1LeUlHz5Jz+3nShx4uYodEdWm
nXPHGcWXpc/5VBRWrlQI2Rp2JN1Rk4zkHWqWeVY5xAMAfyxiu6zZTm31L9e9MzGZ6fHgBqeMhsKk
C//SHmpOta7bLsuGV8m0949o/k2VLhTAbGPy4Q6PGTf9f9u2a1hh1Dm4JQQDGqLq7At7UoxAImZL
5Nr3u6oy/+pLAQiWEtsmn8QFd5m7DzQ4ceAegW/m4sQPgTDSX5ZwMCrJ/0R+ZB5C9sPGF/Tsnn9z
YE7EWM+Yz3gePW2ChxId28d5VyWUpkgJIPRVjYuKxQ36VkrvgcV7H2h+A5KHJV/gP3NI7kjzic4O
7J/9xGOhTWFARFdHEMErK6Hn4W0v6kHgC+i+CVlIl9Vah4NxOmKlDVPngAHXHRk+09OaErSegfbZ
4WMLWgPQfNj0rfPosEOee5iF9MoSN8f3Gevz1/TLXQ75zU7M89mv8eg2/eSwxc8lFK2M72OK1Rb9
BgTlFK9Sp+xPUzVlcjPFkFK/mpTxOV8dnS6yQklC0H4nt6s+kqU1OK6eDEDHXn9TOto+w3fmU690
c59Ohos+3AP0eKtUU8uS9L9jrscYjQ8FuQU2REizq0EBlhh/D9dj8jLjrN4BzQEUAw9a0bgN4zxp
xymrCQzyfsyzOUkzg2H6gMmW7aY+Itwv0wFlPY+dv29UxriacV7Roa5x/9cF7EGetnvniK+U4FOG
XrYHGt2rC0Txn41o2TVDEHcPHrDjRQ4ZS6N0CsAPxWKsSy3XW3NxYcQaI9j9LoZxm5Up1hYiTuV4
E/gZeDQEHkR99BgrAMwFi853C552psEj0l5DInUwPST1X/j2wkaG1UujUkm7+tfUBaffmcnv2UNW
9K17arl2bKv6K8GpLTjo4p7BgcBxxcyqMPkR77gjTZjtuIE3J4iITTTHgeGD4CaYOU1QEJNurXsL
Mr9cQvS6n29qX/dvqNIc4i8BdHA3aylnVO/6cJH0ef+ab7JNdJ0ahKSjiljEFNqDPXpAEKwmZRWG
0G+IenMF+l94vFS+vJ82WQecLCu4JjLcacdtMy3yzjCmXneAqL9fHmLbL8DnvISCf53tJdHQ14/M
N0D0k+1uuE1cDYy0IIkOXRd4fiakh0crREjjbHZud1Sh0gNR8tlIp1B5hR8qQrqvjyLQM2cIYcTp
3BeCD0wz8MH41jcHeSLPNY8ni/Ia/wjEaf6ibNMlCvCoEPnqbtLvPZko5fN0YwKkzPlIzaTGLi4c
RgnssEGlayN6IC82ZQttghJhLmvlJwUsGIaoE9q3cx7sgb1wRmR/xQbcBac2dvlZG8b0aIjr6kYx
4Xz1/4Dq/pKbXLKpITsR0hkHKRC35aY/6EHcEtayv+FovvgqSL6b/6uY18MXQY7RN0HZ7jaAakf5
Yvl/bUd2wx4XEbnibR7ZIRVKRiqwCY/7gOYFIGv4+j0/L5e5RMDwhLaLg692oreEhIKh2hxPU051
18eiI6RlsYqhXbUT8kWiDtelU4L5Wfas5ETZVzAkATqqKVvNfxfup7Hk+71fK9okxLoU+qGd0yy8
bFXXW1WSPDv/CS+ia0OMBAI6ELLy8pgvgtgNuIWxEUPNa5IESYwznzlPplZY4DdQ3MRND/Meye+g
36w02QeINPz5KL80FjUUEnKEtNOCJZrsRlcaRNC4iMD60d35oaxDpWbhcv8Oury86+x+aAds1M1B
dvo4IKRP9GHPNY7HYezBsVyRGS6+GXyw9E147+pZbCyzUmOUBWUd0UQkRCCFoULQUcbbtRUtqk+w
dFf2L5iURZ/6DMaUeIwK9z76SzYmTt4JveDEgmhHg0bJTBRvBgbZrQNpIq/jGOuku0+gl/2Gv/Dl
AGzzaQniAM8fcYLP7gCM84FNZifXWVUunWqiCWMg4sRkJr0as2zdHHxIvoQ322t+dNEYKk5dbVST
j1jnWKp+U8uPvWxMK8MW96kd0VLRzLv97ii7K3IzxpQfYZjy+pO/IYIR9LnX8eGKM9oeQgMlEenx
JhkbpZWvj7owsFkxPfp4v3Otje0HVInulKgbHmXU7I3Jp62OQY/h6yTVzeoq68GLN/A8oe8T6Rz5
IJmYvhQ45OfF8/glNb46gAcjyDb8ghQyngTvC2KXq7DTesPshpdbkr5pfpGzVUltgWZiZDJvU+RX
lK2dzQMcwvqYl4v29KCu7tpFPUUSUwr+17osmRlOPr2zOWXCGWobAmqmNzdho7IjEa4QBRcIg/Vg
1g92Zaza+HOkrQ88X1gPMrE1/NKC8kdtd+L24ArQA+r9RnljTRpitVsegklnOH57NPjZe/vc/iTg
U513oyCA7s3aWn1U0oD3pLKeXM/uOZ7qkNSvMQ4vMPgJu4iH9rcVa9WVZ0tEU8TWioEAzo44JjH+
kiuf84jsrVNzw7qYwBUFz5PJXNG6yLvK/a60AqGd4aJ4hM9u1193+YrRPWEEo0a7QLwGZX5WSvK9
xNkvrHwxcSnFhrHGa1Tl94DNidk/hDQ5MC9+oevVX7v3HgvZ/IvdxHpYYfwMRjSvd+4ejE7hhJXm
qyD0LgHJIQ1aNYPRPC/2Wr/dNoBzs8BrNwTgqxzbhZ/WC+gkFSZ+s/IkUPY2B14zHbyzfj/oGL74
FdAVo0ewjDi3QSO0xuW3+sAsqAf31QDGxSa4UvxVlKUeteydmA1iFa9KE85TKj0xtCtgykHMj6ot
XMHvcAw5MDGbNtMsTkV96ychhkm12ITx2L3xz0zv2j4S3tlGB8bi+UimBnK2H41keKbT6vbhtdn3
sZQztrG3lZsBZ4RTAW29nD/FnoSNPjCLk2CSPP9zLvZSpwyBpvf0EjWa/ZqKRdHthhFh7XCNqlwZ
PCTlaqOig5GlsJ1enMqDyRFUj5GpOlS3XYRI5owSaS1PSK7K68OlGEsSNK5zZrk+RUby5TdptLrW
FrMFfw3URjPiAhiODWMXFMxxcEbxDbfLU8HlotEdjCNwkrMhRPyE/uUpxw4/uCEl4O06lteKGVYz
7WmPrbWj40Q4bmWPm4xLY0i2B4a4VGpW8LLwcU7d8x7kiQ+ZZfUmEXGaklVfoWZmSEFg3PUhLiUz
8xSMGeWAUIoJhuQAC7f+kClwIKaM4jGkdo/1Q/XWoJyEeNnuCjNWqTXmt+Bau7aU5RfbASuy5x4d
5FMYGbRhOTCNupajdrChShY1lzKd8VlmBOAYdKTOGzULqjJUPRqTnVVBxoExuuZ80Gh5egGPr6+9
5OLKsZXZlo0HcMc9DIKdLMMs2yhCRoVbnaRMnnZ+kQjUIk/y2ROyWDMb/cki+sidU2Y53OGbPYYg
z19DvO0DPsDLpuCWBqGyJ/LKBhVdvZfoTzgT0nCRb6SIHkro3jXILjFpZTHP0MXcOSlFWLuXUzz5
zgeMH5rA7MibTgmN9/q/KDwyZO6v5cWK5RQjSCZgYATw5Zp/RyDMNGB0ZmMIMClLku2ZrCg3Ae7K
PYvM562XtfthYRrJP2AvJW8Heg/DT4JHLKBwWKX+AgQBn8c6xbaAaAEDYpkBUcc1jf97r9eZWseG
ajou57OAHhvaVw+I1RYLZVXmo0IQjYx8bThSvFnXAIjVZ6loMlpo1KGGmF9CcXJ9IrYOvLwS4C8d
Il6KFkmQgP7lEsIbfygBQTiAG6YXD0hTNUfQoFBQGaIGs3ol8/bS6bZY3GM1fFrIhQ0opVdzSdYh
BbOrsoz0BTLUcpzmM3jdSnbi3q8fmje+cC1nRqCKQD7q37G2TwWcYUWnDHXy5gN5G7+KJg3nFYwC
K9+PJ/GVhdDe/zBH741HWM3t7D1G2jq+QCEGiBKqN6sXEc3a2TCCN/8ALEiUimxYNnW9ncFX+H9+
fl6VarD2RsT7LP58i/+zkA7zPGH9Cu3TFRmImt/jOo4f+ZMhHh/UfZuXt5YA+fnT5xTniIMjPl64
O+DSOYcBWvwHDwg7hRMaoIXByFmSC1ARim4CX/gnmlXrOi5brnt46d7oSlR80W5wJsqPE66gVmHk
0jbSCEBW2Kc4o/8NeBnH5XdtQbwtjJYdzoKNAbDWFZL0e41auQ3LM9v9QffLY7ILgHJn5nM1Mb+D
U6v/FvbohAhjO7Jmyxf3OzkpXmTZZ9mAV4NuYe6LCZ+3rU8i79126Z+WONJ8xh7Hb5o99QOzdy+J
wFo1To+blNSJWgGYX3mX2JydBMJuOiV3fxRa+Q9ZMJd7KFqmavtz+CHvS9c2ypjQW2BnfAZJ71if
PDiZ0peGC0QKPBRN3f9xOXfrA6lMGm3K6dDlX9ZCXs2TfpDlakIK2Zd5J4kEJAMsarwyyO4VK7BY
GJNAKq0iuAL3INXSzVncyKXYi7zix7TN7HXSWKgs5ZBpn2VAbUzdRIyImOu5GX9nYmj/SjLQURA2
9+6dHzJC+z67tNroCtoFSIJnBun8rfIOIvyRrupL9iCsoh0O317pFlWTOFSYy+czqlMoZ+fi+rAy
9VGA+PjgOFoXQKOO1h+RRauRHM16F4s4wNaI0uVJNPiSZj8eF6JjrYOvpn9fOU68u57DKQi50lgx
cm373KF3Nssl6uuzX9oZi6octDQArks53l0A9KgW3rn08JfyXdqN20wTGfoB1vZxCzAaGdxHuv1S
FDL8rWFBdrWv9h4mbMQoLnoj0Kt3nEnibVqQVVxnjBSTFKTJK4/FcSIHsVCeRoGZH4RHKQ0DVCa8
ef7NGEqZJtD9DvDErCUoLTE+Z/NT1td3rrOqWzL7fVXwywkyrhd7x9CwUHD/liV+uK+tsh22vlMG
OT7C9s0+hg+8cYN9YZPIgewQjiLJ8a4q+9Q7WWnlt+f1wCSGrfnQ9raxoSnfDFnaqN1X1R6Lp+DL
gBkqDvL7G8HX408TRkoAnAUO/AqIwJQzaU604eKG0I0/Rk4dQH0B7YMxm/Ar3sptS8/05aqvwFjf
Vvc+/LGz2NDiJ4ocqjjRigG6s6Dv4sfdNdTFy6UmRS2J8NEZYOKTpAoVeQJ3ynQkBXgjzRmpUiV4
SpsygJsZMXKoJrJ+wSKNWGs6Bmy9DcLGvBj8r1mkXTyVpGKfyqM06CN/zv1TsJEPem6RL49lA/fn
mpmGi9MI8eupmncNlexl2Ve5jtW+31OOzarStjsBZ/VHqRL+DCjBFykP1Wydc8ZoPlUUH4bTZk4p
ZT8RJR9DhFK0DcOXhcFikcWNrLaJ0RXN+3QoVn9zaV0axoNDVYnxB8b8llk+bdk26yUkBurKNuH1
/CetMpVAhAWbdTexIdHt1Lc2jm3QzIL5+BMdw6l9iHm3v8vqH8lI5QT2IPwhGji70iYgPYhaUyr0
ur1Eg+FVe4CksTjOTA99bdSnZa8+MfqqweQ37DFUg7sIpnUFe+rtkw5PpgbdVTriRQGgcVMJGHPE
w74yFW985inpN1J83e3eOHb9SKbpy4OCnBCde/4i0N1go0paQfT8CeePWEn+0ZwEkgAP/ot4VAYu
wDi3q28NS7qGYK4duxEHeCSAsdkdRn79dlDati2/Rj5QX4sD9+48OGTjM5Z7w7lIFCIeP2fbSFX+
HjM66UgmPXAwwReO/WrpziI3sbRFPHAI492uwkofC1aPtwRBpUG+nI9STYqavYmaDXjI01MIKPtl
kmmRS/80sORyrKODJ67tX965qlGyTXi32/K96jkmum1pB8bKQ40wKNdVTpnAzLm1Ogb7VNXelJ63
Rii8vlNtMlRqvmuMywX08QNzihF95/hlJAMtc99dpznM0kFJVPIebyvMaFZkIJOFDvoagpfA/6Nw
0LQoY3kdiqZsq2qqyzzEbXPG/2ZvnAevN4RJIdj4mUnPlMBe7oVvmNUQT0tADZ/yXYmfut6fV0Jg
EUcui3rELzeGYGvx3/sLeMqBsMb6wnuQVa3DGOQLQtIGxB8DYZ43mhjkQWMMzuHHRvrVbzccbSjm
idPutbcBBGdxr8jSE0vKEfQ5XteVnbU/Z7RcullHwmGkw0ur+DPimr9DGf9G+fkVdDiFKgGhNxlr
5CaFmZ65jDOEqCCvDOUu6nw9qrHCEI7v3RladEE/A6WeoljM+M61NafrEoWZ/6f6LU/dm1C9L4Lo
O7mPKXQe/Yp7AtyDeu29zV1K2F9WLQlNbb1Q3FdXFBBg4kj6nMjEqATX77BlHw6pi7FoZRt9kzkX
MAeacmrFBz+fpGQ3tR9028h5bhpo050v6JX2iLDEIbBz2kp6t9M75KKNg8hiKhbByCFuxWuxG/RI
I0YwvKOoX4eecJZn1aw52gotCNOYHurLu0Zt1NKq4DXv/5ECr4ZlQMTqwdhmEjcH0+ca3SUqhM3f
EoiN8iNCYKl37j9Wc83H34LGonf8loVWYeZf4uzoVTa2zNqGtF0++IQsfqIszO2dQ6m/GjWVez/r
nhFmuoqMCH01R7zAUNyy1gzfyZqOSV5p4aOA8dJIxE427BSQMs14EmvgBV7iCMzU7tDjhlBVJZjT
1Y0jT+gT2Y/6KQx18/xhUPGWvJADpin8p5YCtSCnz4iH+/BLQXvAC++RcszNLgvWSrwo7bykcrpY
Xy1SMYXCEqioKl4ZJunYeuoNM/QtbTc0QR732DT8+w6v2n2QwvwmMtIxViFoORhUIlNiQcgN1cVr
oueMn1868g4S5+b+hNFefYwkqK5IrBdy5BZg50NfHfWv0J6gxVAZvYyZWqOxcxXC55yTSdgaCiwI
1+uL4RDiMk/fTX65EYFtMg9N8VN92tFqvxUgnFPbkgDLjYNIgYIZK3NBFWZTkV2axZT+CCJ1Zul6
oiO47h5wNuZJCUVczqC58NwQb07OX0oZ4Ao3nIe6PNkiJlHOC5xCRrXKLu5ymoexbzgIH2E6CQpH
FW0nKeKZtwww0jeDW6jCdp3MMtWAnUGJZHvrYMeqkw7tP4QQPe7/+df3YeCeRyfJbUR7IyMLjKi6
u8QuvSdSq7IXg3KHAxfIwSldfsARomrdXDm9dCBmuCV29Hc7OEEAm0JiKGFq7Fe0c6bycCkx1lIV
P3fjBvhEJfvMCc1ZUSbAgPcQvtrr9+hZh9DQH+PE8eNvnqCedwTGKLcFKhWmA5PeLVSL9yIHP1QP
ok5VXHJkqBkZ9Dj8bsa/5FZWXlJyI7YhfDedSkRgOtM/hlJBjtIhkTQwAit0/aCyQFHKEU9H6rFS
LD5xZXfW7A0N9rLBVZzEvoo7TNGquCGa+Lqd7IuVFt+R/xhPAThNSltaKTfMJuvMOIyrfSpIGlq8
xkWbGqJhc2KV8G0Pu2HUQtznxj3gcBuiPg9ZIeOZrIDrsGJFu72Sd+/k4li4ZeCIMAZMocllcL+e
cmcxVMW1xXoCOQ5bnXZec4t2P0qWOQV27pcPmswok5yvh/m6k18JDPH9+4Az1F1eTEoZlyz8UxYA
38yh1NqIbKzDp6IS1Rhx5e3jQTCswNuNf/ViuaEDcvSImFJJ4s7KMZavy/bsv1OLAqQBhwGzph+0
NNI2lvSC0j53SqcVC0WE+rnaFo9xncLBYsIdt23S8e+6txqAK9FhBmYmmNX1WXeTPK/FQWaAkx0A
hkMiZ2v/D17ebg58MUWVnrmeezJWrVlBS7elSjnsXVxdkzA25y3yzQcCGVZBI5kgcqNpyms/9O8x
7Q37IlnZzmFw9NCICUDNWCfmLlsilw9I59pZhsdIGzUkF1KNoQQeLlPZfXQk+Uo5lnLU/9pnEisC
rrqol0sCwPMiR+nk+gB6WeO4APIHi1zcQwLnEsZv2OzQjY3oifCSOxWrynPwLvU6L133xEd4VXoO
rGrQYOeQrt8u8bhUMcNbu4GXRQ46L6DJ/MhfvFfQMK3cmRGCsZda5cOD+McAZqnhvXxiQl0L++G8
Uo1rWsPMoFxTGMLgfs+w3lSiMRVdr2TmraX7tlP/n85hitp6tHjSPAgZEH9OtmmpPJHe9B+vWht0
FfFy6BYMPl+HuPbL+Cg32A+lERTj4vsMGGlacNp15XtobZ3Jgr7BkdECRM1g5k/z7peM2L2W6mOx
mqgJEjqT5G9NdcVkVnwxiNdNNkc99yOrTgzw7/lhz4AAHxuzIzRAPkQvMHcrJT9CtDaHPEflIMTz
Xx8U+Jv6BPKs+hZ2FnhV7Eq7lOrK0JQj8bLVQiwxPo0o8yDzwVaMvUoQVAykqmHVnNVtRGGfnK4Q
tJyJBFYNI5gjuPD/XmdKky8qa5cczz321+VjNpj/RgcIA25rzmOqaRZ0KJsQoHOA/52PpUYX3T+J
g05voPwzSWlJktWJQIRCTcaTjDWUiDMDa4eATlWqQlySb3rINH61sEl+ZeIdNhW/X9Tf1FiMFh16
knYvSG5NXjwNJMyCzlyo/nHh/VmkO88Gr/dhuY0u3XMXJxNKh6ZH+hUUelCWLYWJnnjSF5JpkDYw
3gzfBQrxYRJ3gFNMIyoPKncXnMlZdvz1Kco8k17+m/AFLEPEobS16W1M+FwaztiUPqTwb/W3pUQ9
kqpvJZbRTeTsyV78Q764ovbVkKXlzLEXGN4tPej61SDVa2/P8AArRonfaqnbQIn9AEyCfTq9N0Vy
7fmVLJ3mLEZa5GeLg9haAz824IUJhKOUSTnMLNej1qVtyxjZ6M/rHjIYOVgRxl+Mwb3Go8z8dx/i
A0w2XKZ3omA6hPycDcwgk27sclK5khhy1geoy/N/ecwiTP93CrG20N+Cd+hN1uU03B0WCBfDOFS+
gd8N5xo7+VNLgJR1Dq88saDgncCSj+xDIvzkCumCiJtvgHDsMMKaNk6VtHieBDczCYLFUfPzogXn
pNyH+e3wLEkHjsxsa1wtY0HGD2c7e8dKLtJsDjiA7UfKhNs3agstoJvvyaCzbl6ys20tDLEaxt6c
DVJ/Ou5WOVk7NSTx5umvBbsF544R3YsINkBiQ7IVSPXgpjuw9KIvRdQloyIM7yJdiJ1G3pxszmCt
En70yj1gcvgNcgCXM3iKULl6IuCtf3bkSZdH6pHCU+YTD91zFaHLEqXfrPsMOFPyRC813MrOwaWK
CTQ66mM6qat7wKASrovjtJ0QQ3KHrWz2pjA5duxp1BAUYkQDvKUuAZsGFX9OBYUEV0qJDXNRFR+B
TuMpf6tCk8NCAE7F+g01EvudVeZExnVz0yPXmilZT+N0fbFdruWarhuXyOnN/OJnCNQAEN8L7kQc
oTlsdxSHdZYfeZnQssGjpiwmOWzyZpg7i98h+iH7WT6sIrvSdA8GoT0m3lC1epKkv0PJmiNbNoXx
R+ypWOKROx4dDrw28koHWSrm1fVZL/f4lkOzP0zZsXDhupiVLnpqEKvdB010ZY4lS3yvgaHkd/js
RSrUUFdqHWlajJBZ16EyJsP9xOJDC14vvJATJ7jJs/ImcUk2UqVbEJCZjE7MLf8ZxESiyqsVxl2i
bHQxyvVbEud7eVwyex2uvAzHdO3gE93X+R1HAUXnZpeSr8MSaX6A8SSjajW0PcHhj2SRBZW1jlcP
t9BAB9IqrdhuF3CP8xkKRXU8jrWzm5kSQ4iApjV66Wb6rCbYFvbgVaYiZjFp0CPMn4l9bPz3u5OM
0fco1Wnf1fiQudxH5wK8nria2Ly/n5qNVHjusBK1Co9Cgov82ZiLgKc/GHyTqSG+xCd4iCtjxUvv
3GKwjvBzaSFAkb9zye+2xkFv/ckCzThFkTTeoSkvIQEmpCHanEvVu22HfEtvWMQDvRn9jmWLfVN7
JHYnfzJyPxn8nI05BXxs9hGHUyw5t5CFZ6jxdHu62gUuXzfKQGGTYSRRHUx6aT8o/pbmpZd7t5Mm
n9WEoCDlVYjBk7+aJOWYcTfcDmG7Xtu5rVFOv8VaoDEZw9dd5KR/hwrr+ueVNQhnikOERfGQk2fl
aPpe87eDxFTq8IC/zVVQcVHMshnFkr7oqicMib832lAGypvZFN/Vh30ojYu0niEdreNdIdJaYbXt
ydPNW9SxJ5FDyXMtmc22EhkHvXzV8vTrKs417tZs4xL+MVq5mZ1E6JXdD7XTJkTeCiWl4K05nmIX
D01bBN6v0IcSdZlxapOjvvoKqfE8e140OzJxIBYMSbEd/ZGJxZMTdm82fSewB9xqxiwQsMwhfHwp
ZO7iyvF6aLrn7T/nXnsPyCXpOsb1yE9Z3WbFKQBvr2Pk4PM750CBY/uy/zF1+uo8VVmyL4RzjSJU
Bw09+p6xTt1LIAKLPLLEBZfVEN3n1uSMj/dpBMAFlWh5frAT/vtVf0oyLKqE37DMsx/2XHjJenqe
Dy3I5dxeyKLLGEu45N9suP0a9PtjCEkfg7nbLMnlpY4qMfrLxbBIhz5paT1SwgeBRbuHiC/daJzm
S8N6QyJaYTyhtCJ4OUWmYc8SCQmgHvKGjxgbqjBFpi1H7G+OSR8DE4afJmDixpFpC/g5douXxOLh
TzJAKpWbw2IxHfKtRl0I23a7dSS56SbLo5LPm4By7d5ZTiIKXG2v79mRvGJzYiTZZl7GJjDvH+lO
q/snZHqFP8ITcDOTEzPvK+MoG2ZvrUh+XZoPXb0UcIHEjUI/Z2S/VTYbOzaBcS9sQiXBnkU8DfIR
OjhJ6BtSiMXD2g93nh1tkt3e9EjKKNjN2e9v6ZAptKuMaeYPV5QoIkWAebleZjQmj0Yc/E+dQVaw
atsgyV6YOD+BopqYrZKe6kXka7y06pPzi8zs068XOA9HYWlzrjtr0oO7LRmB9Y7CuJWFYTUStzKE
JtVKHuqo1uhNvxWJ1foKIU1b75R0Wa6kamWKKPO3XtZwYzxnxePIJNi1O/lq+R/sc9CZFSjr+K4D
ZOCnAdCRrrzcLuikBX4A3XDZBcG06Kfm6WKbmVxGu43QFn/kZQXlshP7io9FHJzaMApleoX4NCxs
BgnkL1OStREMk85Iged5O+wK6jFDVlXyFRZjfU5UxTR912vMmvr3SSzcbKNUyqKmQ01LEqdhne7M
p6AARaYnmOS0j9qL9Ju5o5+jdbJBqrNY/CZ+xbLA52g8apmGYmZlYDNUxdlUKHm3j2N0jyh9ok+j
KHMDhzya+Tx7PHi+FBBBeeqoB6wm79YP01URJjZNAgo97R7kQTur338ib+O++gaCx4ytGwMXjxuz
pOGnpCmcMk7CkxiM6rBdyuTNm2W+Q1XPtaJZIYtw4K29S+QmAaMrZ0XOSzKT7SucToDWeo9+DpxJ
kMA2Afgd05olx+Qj45ngBB4PQ03MhIlS+Yader9aR85Ok8e9S7zUjgO3vJt5eyiajoBQZFMv1sz4
5efK4UPcF2jKv4IPl9T7uG2VfSXoXdAkCTUFjql6fZKNGDDRN7U7iaAL8Z2p/GHlsRh97GR8KfHE
iAa8rSVGqL/wC/yeUI61b7pvzN44v18QTTLa7ZOEByERO54YDaUFySNGDqCTmRz1XjRt7wY6UtRZ
Gg2vQoOIHOh2JkB9rbBXq+QHM9MI+6YIzs4mWj50yp8oO064+O5maOsGe770VhFB1c7N7Qc5r+v7
P7veUPnAgVUoDloe+dWWbKQpBGGk9IAGl8J2TDVlEiWdzLwOtmT4npuusHJDPZr59axilk0YxArq
1UeH8UWwdwOmAe7uvmfLLQI8EcAp5UjDtpG25Gx2zLtEXe9A+umTSacEfPbSS3mIpTDnM2vKzokd
QxGoJzHpyZz4YFQjwKC07+QRZiyXdQzOul/AiFCS8LQ+VBMKGaxmVSPgwC0UxkNfdSvqvyXj5P1c
Uth9jWACwHpNXK+mqmVANp5MhUtGSLoigqvBb+1JANvo/+CSKsANlyRGGhmhuif6CBikFM8B8Pgg
/khgFozYkGpxxvugswkvUP+vbFno3I+G2irrBg0iYxj5nMQHNGGNyIRixxfKLloGDPYDz7cR5JeU
N/T4bYmVHdVOUkH93P0Xza3gd3xNHBptQyYBSq25cMp4MueYPkGxbPOat9rVvoSzo5qq73cK0v80
L+qSbZ55qRQxWyiGNFUPFB/O1p7DvhIiOkVnQW4umjd/hXRPgSDIasMkkvJO6mQQnvtEsRXyxTJU
6zyIEl2CWyMta63JHB87DfeDNwRzyFYjcO2r8GwRDQqKAPSoRhDqZA3sb+0XyWRy8Q3IqtQGA7aZ
1kUE0eOZTY21qW3uIJB3CTDVzi+s8aNMvR3Q4feI/V70r87lox4SyFzAyb9gNWz6cBJkhX6dWOtD
9ffT7I1quGXVkBWVKjM3RVYq7Q7Bt9HXXpMr3bW5ghpwcbKiQvvVq8VCS+E6UDfTzukWstS/Wx3S
LwNbFd4hBfAW/ItxjivlL5SOxKfKHzGHdRZLOi9QIEJl/LO7TSr2r5UUXebsW7ACOipaMptoRZt/
3JrlsHMczZswvRKdOaoN++uoyyNEJ8RWZkpNN9iOoMtYMkAecaFFCcc1Qj8lpOQ/tkQP1vTQ000o
58UbURsdrZBSkmKgijUUFKwUMjnxzyj8ABABNHn9pNWbOBFMAaGtr1xgbeov7PIqzjncplrT2v11
EqulqKA8Ztb+LJlnnKYinDJCeMqI6mfI0xwdc5IQ4uaKUPyH5eR8DGpSb8Qp4e98FPzKJ5sI5tVl
C3r1SmqDey7/2vlLP4mFS8zFCnNYuyxIFBFX0YJbvTglkVMxjDzEG8GlEZvVEny12e4V4TQObngQ
k8TAIJhp5kfynVsIpNnCl/evn6vEyPy+M93qI0s5TrvDt6Jkfii3G4ix0Ma2iKUqtAKXYPAYCZV1
XkaUV92czRBS9v2zhJs3bzlYP/NLSgjCyeXP0MmFgTbFcri19DpeL+QeankxLYFG9mnD4CQKOlmb
Wyo/DJ1Rt5k0LHP6Kfu7IwJIKPTcyrPOvNZt8XPibCbjAdvqIy79AicnlhbSFr5kFqL2+Qd34fwG
GHVO8N4lFCr9LL5MZ7VkVCcWfGLp39p5b+P0n2bZo025Q4ZhmCMZNui9nHBu2n6sDIDG2E1VYX8a
5c99vb7gdsB1WVcgegbkMs5Jq/BfytjvG9FEASNjdLacPIdnP9NVz4fT/Ea9o2Syv76DqHfb+S2H
1Q94+LVV0/IjUxzy5hCdJG8aaf+dibn0bM9In/Z8B4Ns9/Jb6iGArAjuAQ/Gs0HeUhvoKrnPs5aP
sC+G4CwChQn1jdhlA2vlcumX+msCX+l63lrU39u3Aq2tyhlm3aAtrMTgjhpJrfuTMOYhp9Rkm/+e
JbqD5AAuuYw36//mA+y3e6YEL9gHSOAvIXcANZdxPKu8M1iCpSWfgWNtuRo3NjpVY8N99Qt+KFUd
6bH6V06ea1VzxDhgpvN2kQKbdiEDq/A/xDg1f30DCwzzIA4ZHg1C9ewrhlt3EX6YUkQPLlPRtY1E
cj19VWapJ4Ce9PT2l8CN45zNNXcNiNcees7w1HQg/avM1/Z3ZIqZgjorxiMoJq9PEjpTl8LN5mrD
2YW2M4/K/fmZuypSILzMWj55QXO0JDpTn9jIb7ByaWqzjgFE0j/Z8YFBAjUzbizguxz6oNQ2Bdqz
fpEXr01msf6gNgZG7SLFpm9QCKmxoSb/LmK4kJSL5iXSWf5AVLKMeNwmoqvprA4OsvQtGSS+6k+L
TWtqiFUov3RvyLspAteOcVImj2KLnjpuBN5N2TWPSwxChfFK6A5VW1XbyG0r+0xwLgOXBnP5rUgl
RuXqgLNR31hA91E7PbmYJea+Sr5mOWknC5j7HcwJdJuaZCW92PEQqSR/fDg41CAu7YC5mLdF2Dhj
zUlEpZDdp3ArHTOaqcxfOm0ctQ/vF+Q4eAYV263f/wShJsPt2vpf42ThKOFA83WX/HhiqxgYy3a3
hGp2FKS5eMod6mlL4Rf9OoWFKeOWHEhCjnIEdQQ22q5mzjQvMQn8wr26fnzU7Szcyt9nG/QhF+zU
tYlIrRN61SKOGBT1pDzNWxnfr4+ECArG3tNfDBZozm6Zpry/JY5smlYcYzdQAgozguL32ispBCpJ
rKihyMOexk6pnqZnwW2VYy7A/oeNggwl+ct5O4CCMEUfg5jxzkqfhL9fLKHRO2DcD4iA2cXCKyL9
+clpZZ32pnVAJ6NSW4dRYP/bPLOs85P0dXr8fBf5GLJqftdGA7XBF/QbUWc7yYsmdJ73a+3sIyD3
Qp7Wn0Qh5rk718CnY3xtCcItM5QQvDjI9AfkfJwapZT+1jv5V/IDlrtqJ/8rO68vS+HA7S27GKJ0
XMvFzZdaFMBdo1suaInwF5gwwiZuKYiymFj9pTaZnqAD/8DZfSxYUhzvq28cOnc7mZ1iqNubYEny
NlahiHYsMtVbvzzn61TRBiIkUIQlU+i90no7P+rwm9g3bBNXrfOxduiWB+iWsSEukEjKxNo3wmlX
NzynIz5J+7fS9HnIGU1KtC+nC1s1ijhWOMl92JUnKd20R6hidZynGwyJHcGlso0YITuSy2uoDrdT
W/50n6KLF9q2+fT6wqivO3bncGPRah1NxAIIwfBgZ4YqBL1DwCnDFzVG20zsUNePQ+o39BPaXK45
oiMTSBdEwUq7fE3WUgBaQtMQrolOBG+yJm1hgO6mpXzNS7XSQg0LwOF8nsj/luOhShC4UxD+KAvM
z71NBeRpi8IloSiIpQB1DOYa2lvLBxxv+0AhXO7/GWn8bEzKVV9lm3C8WtndrbLA7WNfP+Wo9Z1a
v1AUBLLePfEujr8nTbiwKxBypnMuVAhBNCeBbShEDdAOWkWw+g4hlSC9ivqsuKA1bKTJUjLh58BL
ivM5dQUjwJO2pamP/uBP6vAFRHDsdltBGy3FurfMHbEOQ9nXmLl4oEdCVTVqdKZtDLt2IKISbSaL
0rOuPJF+hnXUrnR9uPRzpmx51xYw7hZKhHUgOgttd6qKcbaRRr1cI+6Znmz0usr53yX0nAX9yLmD
6fZ4U2YFxS4ZFA5+c+ZW8jCycFkz6Z2exTklD4gh0xLYBYaxrPBckueKtC+4meHuR/yNx7RD2QNu
IPaPT1mBtG0OwLtEiIwzXrxWbg+nvEkAK2/659+xtcDrfIMwtScQSxOqcMNhVUA2xvOyg5FLOMjJ
IMgKORZPu++mzguB08qMVvQiPUNnU2rqY7sZWUDBhdVyYu4HS22UU6NBllX3O7y/OSekHUZ3WI/H
wktDRmvKy1vF5AAR7C6J1tueYITdzdhMynaNM6/TRhHuKP0f2XgFOQmsV+973RKQe160s25ZR5AH
XiVjL13+E8vz8sf84qLo5eLtUVBnVYClCW6nWuOC8H5GcLmVDE7izcZnrBeoX/uByciZhnXbAfm8
HDoDIyx6uGlG80uzJXj+IK2Cled3/rvIlnI9tyjMDYX3wzzrMX5oY6ccWDU4oFNcDiAtnnFa5xBG
X+gMh8DqQN2i8im37ripIBJ4b9uXHoAveZvtAr7goIIImYk34DPBdOONnDFQzT22ce4+2SgTutcR
N2ngS9bLrY1CL8mZ1GWh9XHDZrVO7zuKYPMmxEgCmA8uIoBfscRITAfmlFLfdaKg+bmvPruPCnBC
ZSa2Ss/OHE7F5fZ8jiu1VdfrRQovpY7ii1mYX2lY5PNhtMSE2VbXqFVt/s4hh3CvdDqWerg9GE80
veIlXfHX5mxs3W7A7cjrcCmhIO57EGgIdN2T/YoYQYytCICaieka/5MlG2qK7bIkn5ngkNsrjUYv
qjCMleA32PrkZhbdlQGmm6VlCeszFE4zPX4ui2AlNohkxb5GTJRxv8hRGMj1UEPk7TnacE+VBRmu
dK/ZIHE1cOytw83Z9lOzeEwTP50LSTTKFGSQmBd1KSvMeGpg3gZa39zawQyzbizL4fj9S3O1CCfs
D8Q6vizOIhzlwx/QpBTXta5Pao+L1AfThO5sJjifSobhS+5ivuIMDhmAdN5ZCm6K3X2fN+nZHeE/
Z4EB12O+9qYbJzzM87xveBFqfhsuY0erTn86JjcwA+f5pLC2LkQ5nRSjBUdM1lGArG52ZeS8jeHP
WowFDa2c4Ahn4ejsemZ5puMHLsV4BhvQxCYdda4qSW285A4cPFb/9yiMZDrRIa7YJqVbEnuzXh8Y
W+pMG+1K9ix/+9aF2k+HJ4fb7b0VCcGrhzLq0+OrDmUOijesQhW3Nmym/uZFohgIVMDLN6jkZhzW
PA7hUWxjMlWXs008U3JV9ZCBo3OhF4ZJB1thuB+VI2CGVNASMdzet9g08F72Hed4H1yVsP5H41ry
Cmx7nn0abV0F5I+twKSqCg66Rthmu3itnOQoP5uyCHhTbtgoNReG23nsND3zQtHIKyUWG80esjUG
GgJCv4kG882Ax0jkAbxNsLUTZZNNzXqi7cZygKuZz7cAXDh5+p+r1g3IJvvfAaDhvXK5I98iNfRT
9FEj2Am9vlbnC5BZUCe48zTAT+cPRxODH6lpWjN1HRx2K8A4DdqP9wWnianOnmluB0VjMgNH2tlQ
WVkYpQrSz/Ar5XsvFDeLbxJxZ7FbWEgq2SgaNp1A5hugupTcZnzfwco7EsD9Su9oq/PZNXks2s7Y
NjVxYWq5ma3s84IaInhtqevwCZ557m83zcj/r/WI3aJxzJGjeft7IdA7OKwxQDhmOD160ByL5lO3
mFgb0aNMCYRnR0+xfhC6pWjN2nawyjWjRzPbkcfQZD8az3kMLLQ2UNh2Zw+J12ElsF75BNiW++/7
TM2E+b/KlewQTr0XGVAOEDbPPaMiwVKPAG6SmQ2/sBeFoaMwkNYvA+oj6UTIdFrmSr0qKNRsflNT
AARbkNgRzJY0XBDqGWf2JN+qQ3xr3aO/EfsVw8Rwu4qfQ+q9yc0XqO6In8k1r7ka2GRLKh63/ZQM
42sOWQMUwv+pXGUHZ1U+8ctKQyN2oSf6WpA0ikQZklsKfrUelk2cNS6gaoTf/PO/nO2/8Ck7RYuR
j8ZEO1xAZac9poTxSQVfVDb2oZUqGmDJ4B4AadyEB73BIRqqruyOw3ZWlB+StXEY7l90rp5onA0I
FRuQyhlJ21E5i/XOKy8ZSs6OS5hDu53PxC+x8wYHuJGFMkPzL/T6ldia+eQWAdFNDJkAuh3aUpPW
mTKDiEKruwulrUPj8SIdXGym0WDIX56rM5aktjgHCBxlS7A4nEMMqhnqF3dBQL7Hh68Lvz+LlFw6
wFJC96fMyCfqlcaY3r3fblXymS9/iaHAAUbyG1lXYN9IzGsZMJA25Ded3E5EGs9BsHLe2PAP6K6w
h6UFNODAscV8YH6UaORCB607lxOkXbXPvh+vdTTWyaT7m6u9z51NqcO7/JW5KyGr5IXzSHo8KbUH
upVTG3dHDTBnoUv0YBBakmD0u00BmPuCBc9qkP3pigyhAp7r83c7t6RgcZQL2M5gTeD0pqiIr6D2
HYpGm34lX6/kj67p+X+NifHyDWwA8OTmNV442wMidfSkfcL/9ttz4aAPeYPp+pXYCAhgl4u7cnSn
/fp+izpsNAoSMxgZKnAwB3pOQtS5jL7TrdXWMnKT5GIUKj0Q5/U1TnhRo6TU50rpHjiAC3H4Tmp6
tV5lt7d5EOGRF2tEEVY8e7AiNtbwnuErY2co8iwPDGNohe2hW2znCc7WynTsEP7Emd5UXNoDMDKT
psKsoPnUvPEk1rT9rKb9wMTOtsNAPj0MRQML5p1Xis1uwDPWf8elZy+LVnaJ5SgEFun8ozukCbLB
CyIGvSYtZBXknA1Xrck83rs7lo1O4V/uBVL7BTslwQrj0sShw3AyYQB4fXtfwv75fk/aewAD2Pfj
GaAh3crUJzO1o/pWFB61XI32WLNnp7Q0P6mRGNYvAjd1w3ymIGwgHWmDzYEKsEvSrAsA4gPJ1Jp3
AMJwYOIgzJJYnSzUxzRpa/l4IshtrfM8dahtoFHU/exiTtAPvs7tnhU0vZY5yflnxx+S5K3K6R64
1UHli5uEHLjWQCacj8Cl66eYeUSYy86JE7+K8knkLXEz0NErGww7Uk7DgFP7ZbfX7Xax4aMBCapb
wyaABgCQ7BB/eHnLPN9tJUEBZ7joCD5a/yVHdJ442IEavKZvfYvW3ZNpXuzuCUDWPlPPZSS9MwKC
BhQTKClrFKRv5pmgXIRQo/TftFewFW7eUKTvkVFRQnySocfIwMMy0MyYwBwIFwLjdICtGZ4uhp0t
3hcvApBiUqzkq2/6czI/m2iybgqVZw8Bc3sN3KPDKKrZpbRNK1Tsy08AG+mX/1PnyGx54KLkyHOd
KPm38xJID9Pf+csFEK3heHRCIMFHY/HoRYCWBP9Kshb1kTgi1yYhHN7ApjLr9OaRjc36MHRsmlz/
RZ5USNytHDPFagT9xW526ye9cKcOiuQuiEDhDk6BNgMSOWXU7/iJDHhQXw+V0evnEt83JqC4XloJ
whMsXfZXXL8bsGofCu61XJY8/MPmYhVMmli/687K8rGA5syRrF3gmi6kOok9zYCKHJw/mHBC2/Ej
nbKf58aAlNhQsiViTP0WIBlpaoKRZZ/Mv2LUr55/RclO10IqPmfQ72RPLdHt2HdtfZcCq7Tu1XpS
7wmQmBGu88xeVP65ys+lDeM9GPFReGq6S1gnWhKTRwkzZUz6Y8jR+MNIK5Qh9XvxXA1qsICz6K0O
SomwKcIwToBGkZZSwJNMDGU0orai9Bqd3WXHe8uVjlaJyC/Z9bLapt7r0/PWypjblsaxq75LGtRs
TNrFY4ryoAyYualnLDWaNokUpD9VuuBTGyPr5PwdtPlUd4Dqp8riS/bWwKYTdJhQjV9vDwSgs+Ez
Esj6h9vsedaaQf/mwPI0vC+Nu7zXcwlesDK+aGZ6ulyhmuYHlrW0NMlmdZN28ct59OPlQkJ7mVH9
MRX9U9A6km4XUwjheKOJux8FDmWeG39EIMvzvPDVwo3yomh8F/+xj8hqd8luiW8gIJDYZAzq1CKo
6ypbKmrwr+icHTuLiNj2lbd4vOzVDNMz/4rW5lNjg4NvWPuyvzR7wLTNaXqeHKi8kWXCS6BeSIeI
X1tJDc8DSCV9qCcb1AJGuAC2gHjbKtbupJC7Jtsu1PhR7IR4ZX4rF5UJKsqCiUf78eex9gg8oYGz
8xjkyEexGVy9+uyk1M3FxmCOOGXHFjYOPQvHeADICMRxnW5fJ/P4tF78uK+rbW2iwicqlDgdzuMg
3Ydc35PP95jv32Wigw7uZx3z+hxGa1H3AYEW9i+ZXSKiQZ7+x71+K7eqhv+h0JXRgbHFSxoqPEFf
DxenyKsU1dFtbQCGX52r5DAV3hJB0///ZOcIWNfZuyhvgmV6zn0mYyhlLn9H3cZPOJEzLHxhJU23
QSZTmVxQNtx9DxI9SdKo2KBcqaRcbtk44Qp+Zy5/2zZ+M8FS1Y50QUFuCyR33amrtdw++oo3aHvJ
dKyhtNBgaBkzihpGOBRU5oVS4PQUc+uQd/FqKcGN/hhJf1Kma2VcVYNtYAr3TMcrz2P4SVRI70ds
Ea0c7YXLCJHdbxIHNRDCytljR3CmMv0kKLXMSyqet7qvFDMCOXfjAmOS2JMman7ziQ+4OPOWSBlM
jycwcnJ+vdQ1tQdcLRVdHi5PdGa2rJFWCqoVPEye4rqYT1QA1JnD8IrBXGeuN+SrLICE8/L9YuX4
E+yV95sTNEQM7TPxm6LXyLNE2cL5n5W/IBl7Rq9IqqUGM1eJyKXEzHJxZUrpOUN42LG70ViVmUGp
3mZ98F6ThaZxRNN06GtfKGcKS+SPjUDWIdUmyWC2mPCbJH8aO+CBnV0W3Sy9pKqPJTo9duYIgFyU
BY81bJc/oDi6eERxAkrQ5OzvIgASGvF2b74HMuHVKUH4kceFJAviFJHFoDJo/+ZDsf4tyunLd3vA
dlBd0zlDzkGnUul65+7DPa2YaDbIY2tQF2ZOMDEwQG29kXLNQen7pQmm91agINK8xxIt7Z6MDXfk
rIcnoV1IbCkf0FmVnbNPcQLCwABHPF8/SL0Loq8xS7VoKXxhaiWAfrua+XOzslpdFoa+6BlBThRS
pqZ/A9ZI0ggN8JeGfmlYVYulUFhIOmHmRTYqInRI8CY8JeHYDlVmSyhdCkC3M4g+/JYt+GCPC143
hJ48cfgtZ+UN7qwQl72ECEvSaqUEZu22NmzPpTU+l3thTgvvOxYOkG69lBkRF4n0ds7agp74g6WJ
9lt4SRFt8Gv1MouKPu6mXtATjdL7/OZukTw7DHj511uPk9BkW9rV49ZyzObfTwLRMO72b2o3JJTO
DCfbqcJgedYQkPNPTK/5E9KvJv5Gf6eX/oWduYG/LVlNYb7fXcp+U1P9DQDvFtKKBUUa6NzSZpDU
ERL89p7VT6+9FfSDq8niVErrCK475XEBs04ZQ/UMxEZOVbkdx03we9QArVFhpUU8QDayHlFpKlb5
4uB917WwI8rvs90H4HhFUidzaP650NUhhx6P3RGkdvajee8XcpW33QznKbRnS1uRlup1KcSw6G42
JnFEgXGimUubFFdW4mGQvGqEe5Az/c9qryfiieDxYAPNaOWrLnB1LVX9zhtESd/t6bkV5ZAcR3Ft
ZA1oXF6dlgX5SQr6QZR9u7s8O+UeVkQ+EsnZnJCzq7NhkO0U/e8Xq5NBweghtsHNx7HGDrRzf/En
Pio+J/yOUBrmOk9yepVE1SU+jC7sVfatkoR57FKxk1aDB8A64yN7RSmcvFE6Cmxfp3q4sziN0uvk
yIlOJAt8BbHP/8Cs2L6Urtk9hV9MIKffx9LFg4wp1Oszu40X38PasESXhN7/N+sPcVbvpwqRhEzk
/o71uxRxRio4q+yBlPj/hnMYV437i5fNqwxXtWUBt19bVl3WxrM9ChCEpopmH7LsbjksTkCxvCey
dG1t27GqiPeYzgWHV1/lM07n/KtOLDckPTwoGA95xrf8zjZ9ZoHlDiIb7OPNnwc7jWg+UtMX1cW1
OPeiJTCgGIWBIy1R6/dVIoGrZlxrjj1Bzd89fzU8D0SPCZCXTxOm+h3g7ffhm3ZUkO2TnVJuqdPC
oB9C9Rd/W8awsymopeP5AD/EsNyya2ZrmJSeiAfCRIZPGstsKHwrQJ7EzZ1grTfC/YaRiOPoONwf
aq/3miqNNOtlf9wXQ/B/7dWe+dVBghPAXqufacR/vND+gUKr33MeMy8xEJOWqMFLldEYeRMK2ksI
e/WxvljLCgol2peL7L/2BHH8zA4oHmGN3CnoCBO16WNwkMprkW0v2xPOkKxLQ2m9bwxgVL+h98mR
xuHbOKooXsaOWGQnOxJhSM5VtS4P8svQU/DRgJf9JGPn1th9Jqbp30doL9ArftsNhmMk0qnCqSvZ
t+OIO+JOC5CaU2sAi1av6DyJjGx7db4Exgk90qRJKgcj9/cwIjYHgPLnwlaG7jlCBqx/PNen6hBA
Z0hTyat2cLISWuNgZw+zcbzepI9RWEj3K5ZuR2HMfiWVd1/K/msMBlxda555z8bWIX2nJIKBOoXS
DeZiDbxNafIlozIjEaNJdAUyBT3H7FXRWVO4qwoSgOG5YseVMuokdPXsqZ30wRHI1kXl5/pFc9f4
o6XpaxK7EP5vstXOKPVh1pwSqSCYtJS+JkQ2TzEkC7Hr3VBzQfkjOgaHtcOQe92XW43Bm2zIslDz
dNZuRaJY4cgXQ6raAbhXzmDs6z3YGgaqUtNH4lfm/QsFO39IZ1NYWKW3CjbV7OxTSfrfjLn2R4St
27iIMQh1aWHlxQpbtOXbCO4nZfr6rEhLPUT1CgRzHnlSaUyqFuCqn0e6IRWsY9rt683gGLE/6BKv
QJaFcnbECHZ5Lu02gIE3efOHJ5syGcbbmKpAfLLJLmPzjQIuQyDi3ggIx4JKRT3XjygHF3WjL65P
gCFjLBacQk/6rv3uEpQ+nl99f3rLek4a/DSnC89HW9sIJqMJ+a6fwjHG16fEu7ymasu2vMX0cxGW
lhmkvsujbL6Fr4P4DcIJU43XTcUSgojF5a4wh/AKgUw2J5IpoTHAjuHc/ZIB8yK1vaLOxDTd9eyo
yIz2zHKcJYTtmt7oDWvpDVKP9uOOq7Zi+cOE6wiB053UTbsT+YLY9ccmP1KMzICrEehQOpcQ8o30
E/8eWLLpJr0u85qGPs+AxeMOApWkFe50XUE+BE7J6TH7HOO8mHabocRlUb9MCLm1KLuVHXHdrL8L
5ON36hXLo+b5R7vAvbMk+ESNu4l+QZoHX6QE0S0ZI5LAobXpUU1VUESLSeJiZJ+xYsxXdT1wyBRz
TC10LJJcqQ67U5UdwC15UExEDuCOKoKA3kE2xSVVjyzIUDrKZlFEdAcSQRpbQP38fqNaxT/2JSw7
UN6gWY6CNWhuPJab+pZ+d4AyWEGLpndATthH04p9q55Y8gZJM7ivCQlKPQSjSTUv4u6HytQXSH1L
EjIWvXMtQiRI1bsgnOyzm/Rqb7KRwjcrHF3162VnGD/kTVDFUv6HRla5dNtZDzmPLBf4PiWZ2vLy
W1pRl4Rjv/IORqlHbTuQwbcZgbx8bkKMN5yGs8IyiHJ1tt92Sc4UZBque7/DvFUtvBMuHAuObouB
qSLGE/qr2iu48ot/sSez8623cSdBes6lHzZL0m8uuDrDti6QNeaeRQgqOOTJQS9Rr3LRt7feh0qp
nViijbrTPvUkkseWgUMadF+SmkiR8wpmRHCQbOZdXsxxRsybgqeqXIqBvcvFg6Huh+7oUaEgS/Mn
e3P8Ug9CJyme67MJSi4OIWhSj18dhyogysqfnX5dtTmAjkcTC4yIU5VXZdSMmqkR8wB2S6imR7UW
1jtfJaXR9Mx142afQIokdzn0UYWQTgO3NEqJxqoZG0PminbWwG6JhxnhRlpS7TOrR5a25xz8vFYk
K92l2pRV6cWhkTfU+9nQFfm0KjgRxNObnfW/K8hxF7VL2opc500xFlCjpHnXwIpgzHhbsoWgXA37
wKiFj/yKPcxBX12+VxMgOs8DxPLrGhUZsLnDzF0cTU+QgCkwpMDVTTkRf1aIUqfC0Zc+SsSIC5qZ
DJBv6u9QeFORzXKmxumw8SWI9EnPhiOpPlabMXgVR66JTazGd1a3VQfhaWdDEM9373nP2TXYB3CN
+x4fsUi6tmiPgi84I5CHWEMQLEiWHUMTjd8qR2ND1owxJtALXmzSCcdhuDTegrJYArpcAEZcgKwJ
OsZwneo+vIzy+Y6W3Pr79H/y2zdUKELHlGQZEcooGwba8FNJnPkQTaAiai2XoVVVvuhkN135e3I1
veL1Fnni/HmYh1ytA8g2fVYgs3r7ZyZpqGD7aMxRg5whME3XjBBSbB6iej9VoRxOeaYRpJK680mM
JJeh5TzROV+SIPAF5gvEd6DOjj0+lDec82/W9AXNtHsHZQHPuc0/9f7e5Es+NyNj7vyqBNcSxZ8+
Hg+8XGsUG3hyCoqxbl6/eXd4rRExHhhtDGRZjlZzuEyCPx6adsqbTAZEcvdubsSw4xZLUtgmK8EU
i5XsjvFJ5AzDdggh0DMIBChPjDbES9ehjCJJcZVxQiwjrXywuZjBfeR1ltcdPItDDsYCPYCQ1bbv
0cbwzKsgQa1Tkg6vkUY3ZSBEemyZOz3FpmWxQ5pvd49en9uolIzffoOmXFnpeGggN5uhwq1D+Cbq
0XaiYBtOmCakYJi4/mGFv5UHjUnj1pvU5rrxly9c/EgxAM5LF4tYByshDnVD9U0m9u+LtL/799lS
CkB0ELlHdOohl4kBKiIKXfKzrDWQeGIYhOYd617jNPCn8iqpfNkwYKFrNacR5ngMrgdHRLq7QsU0
mkXx+ktNcTMcxelWVNxl8aeelA/ypxyRStfXyr7sjSoyJKjX+UQajui+ODN9PmoLGW1wEb/S/Kxl
qGXFEfOX7aXST9aV0NScs0LlSYAenxSHJyTHqZO0QVSqj6GuzNw+4973UWXTqMlrGLxAdG+rUit9
nbEMPL2lfQ4OVkXa+or9n7n8eDgM0acJLUP9OUyIZYHWT+3aPsD5Ehfr4t+Y5Wep8BCuc2vGCsNy
bNcPDHk85qjkZHMrvkAjWCNLN9O5x46XACXSkymr9yJRaefhpTUQFvCeVTqo27PHttWT7I7SVyPs
4QKEW/0hVsFZOpnFPR5nVHjzj+rxLRP57fm4Ijpvp3rJz7yNHf8A/vzqKBX0TmouDw57IRKeZos6
U6nQXb8uWG5yBIBUmy3tFOLQBm6gJT99VuxHK3S99eLZfklCuyI+kTieSq1iUffYR6byfEA2KXKm
kphHGbVjSHjySzN5k1d/weJmRpFug+kvnAPgxcjHeKaVFLIBtks14/xshXp1Xwssraei8PdkEVd6
9Pmy8lIrBOx4vD1IdZ/x579wPinmmqQlPnlQSwBpmfV5yJas6k6vrspfKqRZENL40xdJpFnxSdd1
uiav11FtrziuzpmAoEB5DIVl56ElOM5hEXPPjYvUlv0sR2mUpAvKRu332VCfCxbNm06oqmD7BOP7
1x9DipEvCHHXV/kbmV0qjRLcBftLtUBux0UoGPqEfxlg2Txs7nFcOci/RReVKZxn0YuFatBmfv6Y
9AYahekvpCkXNbm8+JWIqlt6+GmqbpdBqzGQPt0yu28cMqj0vAW+UFXPEFmYO+t+cCXcPpCMbVbV
fwHKpUld6hORx84vGzQuIMbvJcwKlEqxMcf4bQ+qkkn3kqqbptVvSeJ1Ipl3fqbaj4ct1oPB9bkD
jGcrqxza8HQDPXeDpNRLxx6nxKkOFmraU2YpW4WhS/PEERVZBuzCcqpKXQ3ZlZ2uHGwim8dKHwV1
+n/RjZOIkYcVoOlhcHx0qTo6xTi6J6g+e2wLSw95mRfvEq1BxNuTB85O9Q+EkRtq0TRU+LoSqSGe
h+AvUbJUft7/M2zeVqYM5vo25Ue1KqH0P6igo+6YUPYuMq47plii1u5061yDJfdaXoa1Sd8uLtX5
bYhdliTozCdxFtu+7GERoMnYaThw5suqcs0QcT66SOm8qO9fnhLNPWoch1JVzELscCIvwTvg74Or
UvLQU+h6ilmHs4LkROIRbTBNLEuzXgTR3LrTNAAaz3tv06cTdHRg1hYPaoAF+OvzBnzXxuwpmDfT
dpJC3hb7RlAcCO8WKYJhuMvmLCqumLusMg6y0KDRhdG/JRcYUtIblFjhNEtqXsElGmn0ZCRC8YPu
CUDGQzTWABcKfSM21+YiK7QApwzIoDPZy2dfJjMAbqukjgp/QfLV1h4oOJJHvU51BhTJ2UIbvVc5
Sw79eQ/5gd1ZNSLMvwChOqXzEnFWIRM2T5z8kWuwAh4ncwPQJpAKSCEycoawQwx/pk3LuN0Ebtrf
8c9HjwVWjUV+aT5tklMH42OOFS+f4rLJE930gDPUN9yaez/z7DCqPKNFSQHVKMedMjpkBkGoEm7Y
zKOCqlfFj+GALcs6SO2NCN9VFUiV7h1oZI88O7PESuXjaL3Y1Cx2k4q55c57tcC+WT0PuWkP/f75
B0oWiFPFG3b1oY95nG2cVfWwgB/rY4zA9HlSa0dMnrp73bULNiPFQCiiFo6bfhjmdqp9GCTFDSUv
Qgwu6aqiYqC6IHNwHXuzk0Ad5UnbvqVZ1DuENbtRA2sr2Ubu5qxtJGR1kWnVsRFp+pK4z9KUjPb6
96+jq2hawBXminz0i4qdG/99/BeMS1Pj/k6KNQnSycMy+ASnF1/GwWWL8I/6CiDD2ng5L3ec0bWo
VPiiiOh8vdSx5UTHdBG3ithW61HHGZtmgzZhF6oXpJNPE5cjN9Fd6lpMGjzYfGE0E8EV/LOm6YyM
j6PxRPom0FoBNYGzkplcQk/3VvnXlYjPgdED7Qutn3Km6uIb29su8ULb8GAey2laLEAZDwUbD1M5
yHvxJ+klboxRtIdYz+tkVjUw0MfWCcuYzGotMsvKDJATc7jE9fJRb5ttDyRB45f+5KOsZTu5DoOy
12B5a947bRJdilSN9drC9qb9hABf9vR28tfgnHPF0AWopkhQac6xDuuGYqxRFc2K5+5TROY/9lL9
j00qIumGrPul/kNWDoZPYgEmm3Abti5klUjKhznWRGobawjBBHIrcMgCv/zrG3JyhpE2Mh8eBkqb
BPzJ1oOcxUiN6HPRUXf+WJD7n4bKRu8hjyMF864ebX55ZWcdIzQvHoxAIQ61grcNvyFxHaIzyUqj
2cYimYZqPAo6hCdyirWf4z13n/durv1uVxgFh+5/kWazWevRD1RDOzJYDWrwptyaM7cS6q22XTVp
jyYqBCq35rlCf0VrY4N3XSc/v7T43t2/n21C3DZuSb3MbCb2U5XdSph8QDVxIbV4xn5kwTyQ2JER
ApD2BcZVYGW/lgROyi14Mm8Q3ufvXbIDUBLabuuIdXT1/b5MMRWpSLX6OW8uHISl+urVDgbVHP40
jf+caJCX3Hn07Wl4QhemVu2uyit87LQ2OmFHyrLgMy+cdHWv8iIYqFrrgizruo3A0jOZuw7qdBH7
Vzyv9pW8uKy0NTH5T57rzHxO88+6Zt5+RgVbVjAZwErgS3d6O7OyuW86NWVgqc0N2PLRHmZh5Nhf
lsz5yqyH67Fx30CCxk6zO61nwB+wBWmAdW66uV7N4GS/W72aR98557W7dp0z3RfsO4G2PzgG3ttk
j7Tg1jLMD/HyfiR8WvRiXPUhlqsvvrzRPo397k8mitOgcGJ5eFLXMbu589amOJMt05kDIFEQUvIl
jEB3dxE1hu3HOiy3LXWmI7a7vuTtsnK1mU9EUfAcryOGKKbMaeR6U6QdjPC+XO4RdhJ/juC2YsjQ
pWoEHLOgveA0z46D0Ju5IHDUfd/KtQPtzi1EnID0meEXhfVdY0rfT2WhwOf/PWcWPSrR39tqGGlY
Cp+ex7FTI8m0ASRwzvQwzJGxpeyW2O9twgFttn62XrxJjWvsHjHQjeFsvbsYumRGiuJATvVTj53d
N4LRssbGNiLJ8JUZdudc5w664V0IUYktB9kcykedzCPPb0SJbbqqVD9Q7wyU0gTzHsAEcQEDQTg4
4HDZm/NsmxPyz7+aM3FJHPCzdQcfEDCFlLfSxUK4qqggmddrmRNwhC2ef6rpH/NnuloY08S5r2cP
toJzP08Bq2iXzuptbNbDP+h7QII6FkHrKvEbGeFFEsEKtjwi1hLnQhHU2lFmeAKEZFpo2Q4ShF6q
g7FqeeLXNs5ZkCNfXTBA53ccv9dXRSxU8CaoqoJ13kmwPszZqV7RKxs32rsNJOqVISx3lZzPhlxG
FxzuOEEyr8cGdIBxe21OHG2T5pCNyWNXNTGNxPFX8O8lfa4jj0JeiN5rUwsis1a7W5r2QJSbPMy6
UTcvYQo8rmOwHlr1y94dFKogN3U4BZbV3fhXitjT3yhD/xF3MM6gjOARFs19GgZVyOXOQqJyF2ja
+rOkguJo81MgePpiEIiwBPWMMBa2PBLx+1PazhhxK4V55QztCqd0ErfgvLvl5HXlCmFdcntRhY18
xBElfErrtBPROdFI3SjXp6/e9/zJpFfQG+FFhpdh6bdiu5l2utxxxgB0BWvdnmmEsUPEjLmN1SvP
anxw4ut4apAE/dtOPPwqmQfqeiyI3tkKxNCSzz2fhM/hUaNoEs/xLIfG54XfVGmQcRmKgpkNLyMQ
xBoBbqNU918A3sgbMmKSQmPQqdfxnqBDJMoke72BKmfdEBU6ku/Cck19OJBzRi/RWeMsoMTPX44/
pSXuh4UG4BOXmxzN939ZwyJv+9hYE6cP8KzkaHC6yLiak38OKWYUkWWmc/YnHWsGYbpTHQpAUZ9t
VCF/vyhNL6HamPQBOlbj7do/T5lWbWw42dUB9HiiWBkNIMfxdBWu5vUF+2uFjaZ0GkUBT7RFgzX2
y5DWNlG0ycJomogXcmG7EP8h+m6kD8EB4pzdn1cLnp8QSEI2rblzi3j8D+aIRI1HSXRmitZYJPHQ
zRiQK7ZL0fob3w/Crr2FHVHZswRo59+3nN83fpX+CaqJMvXsD/hnSR0250g4AAraJ+5upl1qqVRl
A9+UAfyhII32M3RU6gl6SOE4CLtXly809Ru4iGnw4V0XXMBNQTXAQRE4mZ8GXZqexGyPZudjUqZq
VnEKOOrVRlV6oJ0S9xZQfofi7XHo/nZdmrdw6ab4diXkAU/8eIEdNxCDvSVDhpzZ39tZEfaesPVU
mkahrRm4bB4/Nm6s3ijedMe1HU2wOa9DoxxtyCAb6xON/XVJhwwKZFHYaW0HdUgpU+eWjBIQ+QYQ
MaF8D+RU8frutZb3/xNhm1cN5PPoxiBYKAIpjtcSxnKn5HKlp8LYYlu/99htMNHmAs8VlPlErO3H
xethceVqvUbx4iH0k+Zp7lAsBBvOJn8LtZJXCQ2FJlSOhjAmVxoKD6KMsz5v4Cb6WNqlBBUjiXRw
+0LYSyQ2OnPdMlx37AeUTDM3W2UfUUzdqj1PCPRV6XD7OdlbiN/hp+IdVLbHUMu0+oGAO82wcJQB
jJk6cTdvAdiEjmfA27kK02nsAlOsxufLDlasJQF2IOQo6Mp2Z60kfnAnlgFq1LVBgl2rH5yrOZAy
mvNMgQZK4RPelu7IW9la/gni7CTBl03pCajBwPdJ8UjgU+KblJABA0l9J36Qr4tMxgLkYBRyYnUn
iaVKP3eTH/+2hRCBC4ZJmp4ICTnvKuf43rT6tEBKZ4bkDvJWPcRJ00lA7iGLYza91crEFKChBSH6
QrJFEq2ceWuynjv0TRE2hhbJksBqK4CdQJhoCoUzrJ64X/7o6VGWRH5GlPaUEBu2QLdbt2YydG/r
7DgJT4dG+ngmxGaTwn8WS8lKbBGAXy5Li9dhdugiOaqPJT2nlNDRu0L/z8W3Zd3ZZHQaWTHiGUIh
Vfnm1UfCJSkCaQ+cyBpe8cO1qCNOtqKG7ey52RLR3mS4yNr7kJqfriOMntv0hBIXlYhQLMwdgzxT
GCjgw+yaDoVG5qT8/tHtlNDIV6t27+MCDMFcea/wW7us9VEDW1Wm2vURid6PcMdLwybmv0gpGICq
1r+tUGuKQ6R05NPk48TwWsTNW2T2b/Iw0Swa1w9BqcaHPGWnu90KdZYI1L3kw7k8vt2KjzvDKDlT
da/yZqmNikKv5vO9yGJPfcoHPd2L0Al8P9KeUKyROFQuvHdqSwN7d2kDni9umxY5xx+ErFNHWFcM
UGFIzdtu5rkyQKNtFWMe95UjiVEwjr+TD0IjLZwdH2HR9k0KvJcDBqb9P8+3dDCZUStERkkKXAIx
yTiWuliC5QP3FH/dVC9QkX/s1GAYB+IS6VZVEtaQV3OZjJNJ2x1x7XcDPTeNuU4OZQ2YeuNa18eg
Lc7ro6SaYuxkdaE/T0zkXzlMuVm6lERh1kkc4kstZKBIfoL51N4Nvoatj94OAjCgB3T+c34r7dA3
XeNZryjYAYazSdvy3wXz+I1A/FyGZLMwqjXygFpg1LlG3AVJQtibTYVwltx/nSqPwqnA0uKkc9QO
FY+pA1F3IjYfaBklApF/jmi/1NqVvv+B6GONANRt17Cb57kKPevQin4W+HtFwMWJn53B+ph5ioFy
QEB/QWHPw0iX+cnTUyNzQZ/wdKxM3PvGnn38rvme/x/wtqL74vmkYOdsJBmzZa+O9y8MbeG2E30v
+9jts6ruud4qFJ0Lb7VEIB6ZefOt7qSZyB3aiAHpqJx4F13pzGMUwaXJooTGi+dHMH0rq7WW2GnU
2tyYpwkNlK78JWIU3ABtsyMHIJ/eLrMd6FkDr0lBhBHNr0ZMCb30814pa2HBtMgsdElEWZacDh7c
nTGGA4K8qaoND7ZJd6KJptgwvNXeGESaqdZoSJuGB68kgBWY4iQYSIWbMiyTkkGqhtBBpU68CRkm
sKYJC2kEmWWC7JVZL4fBkF1Hzn6KtRHEEBkJpVD4XzsskiFeBhNKH4R66IE73drZu52Z1xIq+Ix4
LfGspCNVT0ulF7YSMaZRKrMCdXx9TWVwRUv1zRfil6seigvfz9+NZ+1u7r1fOJiipk9eekB/6ZK5
iigkIkPcIO5fGL53+r2k4QY/gx8336YlBn5sk9NNxxL8DZ/UwrHjy8HX5ASID/qG4/nccjH63qUY
UoNZiItos1pdcrwUldPD0dMC2VB3ttygqcd9BAywfNFjB4vLtr3B3WmTEPNo5uMJHmsZIEhvv72Y
63eBGjNjC+aU5VPvGHJPMpWi9DTfgUkLHQv4gZ0wQ2ncFeYaahXYZbV38A4pf/n7SjE7NHsaQo/B
tUKwOkOKiyN3YEhzwF2QPbE4QngR2tTfuZ8NBnfouXLr6jZkMFNc3ByOEU8OuVb3BI2VnHT6cyO9
IPEd5ZiL9LAKpG2NTWUmCXupOn+CBEepyzbWc9o5ZT/pT4deYkI2hzfRwlPttj+oo3l9/eh9MUAE
o7ODpombkYx+1AnJgc5AAlIYgUqffCnCftaBumolKH4QBuEnneyVo3vp102T51woa3AaMIbtV2u0
3KwOHH3IlW42lcy3fvBo5RqjX0d2VuNtS1M22S0+RdBXCC1H2eTJXIFa+EOxRPs6NT/hfYEEfk8A
StN7SLJ/3Hbx0M31dqbnfmcJoemVjReFVRo+PFllO5Ba+eoQHvFBHEuCLry8Stx8+riI3e50y9wJ
BfjivWpx1wjdJ72+V1XUlXSA0KhRWm05ex/Yh2aAizrqsNOzVK3hW/jVWvxWWhLQEyp48WxQPYCo
SZfHLf3CaMMor/EPSo0yEbL4k5nRUm9SnH9w76Zqm4L1EXkdil/3pyR4X2eEtUu8s1uTdEyqFdzB
i3i/tJgKgU4up5XALaYqmqPwTmJnndZFCCmSaouyssKjquS02x+5gsyrOu0bLj6ydNSDExB0HnnU
POI1mL8nOkag9KXf7EvEqrFwnicySpCGzjZjNXKNV2Ao4S1d4+BXgB9nS5ObchtigdMFsYWaOqUJ
PYbIqgTObTHVqKk/QFXHfyx/xR3EXwDIUs8+F4Q6cKOJwYCCiTiQkq/h9+zD70YsRvpGJFUgec0c
nVFxry6QHbM6v3bJmBsNCCt3VhPgqNO8wTE7ijVEsEOCkYKunXCaT3XjNI3yd7PiIa0NM8av86le
wx/Sx+89GR1KhGvIgSNjbJACk8tQqFQX6Gz7fCAupOJnfDj1+1GVWXm3rTVZ6WT69ubak9coMNjU
XlabHK0tdOQRU+Cy3Xo0ILSUfBGJwpYyfZDZcTmoBNK5l3WANoGwCc+vyQ+VJgQiuT0u9Ynd+Ztw
lJ+JAsH8rLCsNC2hkVPuo1Bw7Nn/K5eZp8Eboow1S0D7m7cxBltSt8Z2ZsvnolW97svNeZg1fsZD
LixWUVSaFKqjmfomfutOrqbkXYBFpRrsD/c8UGq5s3FWxp2/jwU4DKaaLSqMeQgnsrdirF9Iwtr9
w/6xO0QY/UiNvGjwqQTIXd1jhUCl6A4IVB3EDzWG8PbaPxTANodtsCgAgPSDXHtNebvgr/5/67VY
2sY0Fxi68MbuYPttSU0ehM0KmDGkcSrILUrqWdp/y49NSfD2t4cGmm5VRVeg4yySD85uXKJ/HugV
UjFDeTrSr5Cbg+hcsF/M3TRvYcuW6MmHzPUz+V9dj3V71yHjqSgW7c9zhGJA9Sr36RLHdEqYYhLc
ewl60CdOzx2+TsI7ooPfFE02lkbRCsJYtQw0WqkWdBb2+zkaa6EWlbMPNTyf8RYkIYYNMiS1v8b0
Ol+ZutYaEjQiU0mei/7HompWbK6p+HNh0/NpruYRaUepbHknD/1QYkm9nZtZHDz6voZGIsryQRka
z1ItTDmi2CHDfCX1tdsqBV7vPw34VuJx1E/YEWuzsiavozFMih+w0pdegOkJLm6+u3GvsBxz1V6g
A+QYzJwzi/cqwQrO80UWKTsoLo0sdZHb2P7aqq95kgTvdC9IeT9jMQR72R9aDh9RaLiYDj8oYRkO
X3Tkm1nUl7M8+65i95k1yCMHnb3qZpikChaktLS3QW3WBGJ6gqM1My4GX/Fy9snnpUVtWLnXxIjF
jJ/o5RLaoCP5zOha4etHOOjvTz6Fp7TnnHW1kXBKLnEER/dc8B7JPd57zCDqmHofL373r6VNv1Vt
lgKQ5vZT++YKDrhFT+HACeu1R28j55Vs9OtXUWJffcGL3mUNmMtPvenuTmgb5EeEOy4DBhH0R4fR
LSRdw4+V56OBIFvWaspqKevbqynN0pMwRaoVFtTD6/nkz3XOL8fnHHDhcj9Sg4IhJWwOmwyRWp/U
nimUyTqMS+gfyrTzHZhc3pYuEIgD4GpPmR3jI0YVlpWaLbny1p/oLKS1YrVEJ3ILUYb8f8u0BTRb
A11Eb2NEJhyqH6Ifzo3l7c5r12c3hC3K/9lPLLVQG5K+51ZfhgF6D+ct+7MW/z+VwrlLk09qbR6Z
bJ8Ug9CbL3E4R7S5m1+4UrM/b/l5mbPhN1nuv6rFL6s8ztKJELIMBjuKdmTse+q547cQ7p1QQnhZ
Gb8nYRaIArIVEYqOHxUWPKgmabq4KG7yw8EArzdk20Mxje7zOwWrPjBRUHi7p+UWVbfKM/DhKTxI
jC9/ywV/DuvMZ7GFY0ylKpK4ds3dpEsyL0MpkV4gvMvHrcME1As+XaQo+eML+gwDk+D2rgb/9iPC
gR6RHHL+h4OW8uRUDuGVHXKlWDvInj7dr3ZnDPpsUYoo1scsPb4EaeMXeSvgnrAwYivKzm54b5dp
Kss3zirqI+mAYGtN6I2fFxZ4W1fx+KQv/oGRz/8scfimL6ebAGZi0A2TUxbt+bI4+Guv9LZ9Gwlj
AunXkQ5VSvQjlYJugn7JihUk/sYH+VdcPmvDSq23bRYA8apgYsMc+hCvAl6qU5c8GLAAWwAo815U
RSoVQl9xJKG3GnPUfwN19uhuczSDZIG5fr0ovH6Cc3idOdp1IXGuz0ehgsH+tlYk3B55TLFb4X3h
qv5IG3q2PiYuKewEy0Dp9PeEE5s+rpi/AAc9zF6vssSjH07+xx0uC9S276A4jRJWt277cFq118Xk
VELQGb+4CVyULbZE55Vv2uZRjt2WTaQP/gz6prqWU9PoV3jmOa6N+Mnh/7kQ3c9Ahd8qdwn9fz/a
HD9eftuYgcFqgtres2AEaCdTYA1EiccGuu01ct9q+nfCqRVpe8T+bN3i+dyEbUioZLwG+FxjXf3m
2YnSeROIK6A6nB6hiW+oPu8mVUCsL5FvpwsSSmcMGACkhkmUSa7m7yHnv4r3yrO8hNqC9Qr0OGrd
wiC04LrjO3lXIx9coZi3o9A+Xe8WuyP52MacAcQqrMALC01sgT1QIsSEl3PcIGIdYBXiOoPNZnoq
yLrsrUJOst6aUf6M/6KX/L94QPNqNYwKRfDQ+ExphSLYXlWzN60eGoTHNSiYWehYWeSLNKAenKMM
hJrLC2boMRsfqIbP/sjjxOGoSOy+YTEQ+6/fF9UtG90wy+KBCFd855C0p7qA+8igvG0/6NN4D147
TzN9jIh6TmB7mrGsBLOvpReDl7FAIgNwgeVBMiTFvu9h4V/Z4rQZQa0gpR2IkSB1lpRlG9DyZU1M
rn2NdjoP8sl9S6nKBJpcu1QYucstkNxS1yFuKasYDrr2oGEuQ2Cqf6zJ55vZxfCVOdhygfZSFBAo
z6hq3SNY8/uNhSlLPn0Oy4/o6jAP/qVRbXLRlYbttGUfGRIcq+zpkG0VFjUh3dv/EEVxiCIpFSCX
uxgpkRs2ClzDhfTQ0l5Jr4EtVFaNXCe5Ileynj7Aylt1b6brK7nH3Wc9mrs2ZWOshq++LhCGHlmR
VzSPdF5k2bDABw8ZNsy7zJXwYm+Z1wGaN+C3Bt7eiyVTsKOX4u8qGLSQsgXnGDcmDE3B4QCV6RoF
Dhowztc4Ky8BzUM1KzU7sfaMw36ml9xikmnkhVVhRNlNBKrRd+88VL4GWz+dpMe95y7vRZ4nWiN6
kv3+n3jFb5GXzglGipS/RtGA51Vt5rVUcZngLozrjKTPL0cmgbQCKFXw/wmJpuzUMnzuwTtJq1h6
fZhB9FJmE+hn8+NBs4PMtVKgpjKQe1RxTBDptIpLrB+8KRdvJLluZ8A1C/5qFNifGNkDCd1M4Wkz
ya5Az9IK1vDnOE3USbST+DqZpbQ7BczR1V3itKUyoT2YrpNakSVrYJC4quevaeTocHodhJEIi9aN
oRdhyW9MoCZXDVdrQ3neFOotPiP6aBm40YN/9oc0xAwLLMOkpI7EBnQ3piZOep+oRFMi/RYldxEB
3TIIUp1tGPa2z3/f7ETN54SPaqCMCBp1m3wsD1AO6l/O1Q+fRpoMOZHUmt3cbuZm9wXDkedF1gJK
ROXs8xHcnn92X/5LmGkWccRw86CeUmAjPNW26fml2gA5kHA2uwbuzvcCx+2BVVRLiqpY5vIv9Y8c
rKj2+yBPo7E/+sv5NxhdiahAatIlmPm+2tGRaR3t0BL+XzJ4NuS8m53I9Yfi0ZpJcMu2s8Umykhx
WMK+NNbv59QNQoOjWhIRc7I3cVko3OuyJt05pB4OxVxQ1ikpc1DJsZgKEO3CVNs1rFdEsL3vg1s6
KpCjijqDMA32K5OWe/1DvfwhlGVX7Vq+PuF0BhFzf0bJ+S0bHx4nw4bpcIjN/v3keWt71Bbmz/OR
JeQ9Qtbx3glx+rlEhRyAHzWR1VSI2X5A1Qixq7hfqS91Q+GdJHMAKqUwgi6C5m0GkCkx7lrREQAc
BYn4y7rcUXynj1wN5QWzbe+yhBJ+ks49I57HCZnNSIExqNaStE35RBdXS/0YsZbV5mySBm2mG1bM
4jObjV4mOuDgFMmB8dr/PfXgp43tt7ZWZsTdSOxLRQpFlKrdkpx2Saofy8ezcwQ3QWyyXbZPAjAP
vR2nqMx3HbtwDV0g3nSoEjy7TT6H8oPCkZQ8BjZDDTWHeY+Q5L5sE0K2smiPnyeiiqCL2coRXlct
ZNFLP/nzDzwh1mlzJ15p2sBas/uttC0OGCFsqxsEg3+v8zeY9WYrB8nj+m9klrkdGhVHqxgtabPy
iLlulUMprVFzW8sRZo+X6SzMqHmkOT8590bLWIoRagVzbchwNX7IFvbcprQJNMPUiv2mXdTW70Tx
PkBJ6rZeSEi09LCG4Bd7XqtrVZm6hn8UNl7C4IQpGP9frJZA3uW046fKuJP56KrmMHSZQF9ne25e
W4oWBM1mFphMO9fgh9c5SXpndZ/uOAbcYVM4WSIe+3cOWQOLgz/c5aCN39Uahsaq+zdOCYiRzkgh
4LAsjTYWb/l4DZ1fqya1YTKuc3MwcY7hLUuBzDaQty5BwHN7ZwzcG+QELxIgKA+l7dBiqGfHRmIT
SWkiv+R2fJ0Tm0HcOdYVigTzz2N5unN7BlAymOjG+ZFILimEtJyFeSeZGYvmiMdjAHQPouUG1xYp
mo6hfBaza9gEa3RR4xiMMAp9jlpXrnjcSRNeCACyLj0GJia0rsSFVZAxG/fEuQFTkEVeJliIa/1X
VhmWDilZmXLCcHM2K3OD98VqKhMeI2/nypDDsOD4FkyCWr0TpdQ+cVep2yf1HLZhAQtSz5UdMAkO
SxHkpkMObsPG9AnDbNpRfAoTq15hN66kjqXHh1vXuD1jhlqqTqEqCVs6mwmim6jb5GtgwAkZENJF
CyTODBsW5zP3Ex02qfRUHA0r23lOPKR3gnqUkrQf5IRTz/FWA78X2Y2GBxK2wmCCvEDhI1fgzolx
6yIRgu4JUsgTWckUTSCceRKFX6oBwvDUQyiI1Habhx/a+jKN2IwcUDd+iYyoU+m9HxLq9z4AThqt
4DNL0moU01Wn2SLRzjNCgUFNd9Nh8W7jGR2cWfNRumEOSUDVaJC/2H889qht4ZSVfruVTj3BKkmA
6ET8qMoDcNsJDIZaUlk0+MfiTcDPb+JglPFKCPNKEuXgbujuZAPUFa2+QoA1eWXeSK4XOquNtxKX
qOCedBI+qCiyG5n+JLAmo+mCKlGLL4ksHauzCoJUjFbox9a1kHHY3PvFMZhElk24nCi2CstyneGT
0D/4JyR2fd7nB0uujj9Pvd6UY1p1zaL1Obe6pOS0Y4efxuDRTVXx+7VBYxgNhlG4Z2mYXx7U0Ge9
0jiEYzamlcfRVHLVzbjriAmZUfhVxdw0bTiY67VFXJan5tJ7h/f8CT9jVPo/3MinWFp1ICeIkodK
Ucxq10VV8qgFXEtSq9zLeAjGWy53GEb78GGPsx8+4Z9YToN7JLjMlefcZaV0KLM1ASPQ+GB28K9V
us6jphIkZfL5iIUv4hgo5qiO5ksFKgRd7M2VQrP4Vx3bGOjvWwk/Wtxri2xokDAm3KujC5J/PjKc
dCUcpazCHKegW5DcVUJIeZguaXleLwAbIe2Dm/Rsr+qNVzMeiO5rSXO8PKQSu24YAPvnpAhQFKEd
c2CCDDtpPdIcVUVJQBk8km3gzGKHq6RH1YS9ax4TLFeq62vw+teLUlzViFybM/qkXRhmFMnblxwT
xjYushKjB3fDGKgDSgp34KoN88SPgnZdGDmbgfLw8cD8sFS/5SbAINR+xoWF6xbVA3QPl9qeobDb
O3fnrA4ELM91a/fUIs4aWxmyZ8An18YSR+AwsGZCsajXu96vMwHwEq0qPcbNglkJ+kYhaGmDYSTl
R3lkx31s99EP9tVbb5m3ypbJbI+Zagjb9umKbJorkTH/4fpAGs3qPh2CPmcmcgFAEAW48QT+y8DE
31SgTJNf6XI42hYexAXvSUq70KQiociEoFBR1/15om6yWKPtGKVR/aEtoHMNiOtaSatTr9HGyoTQ
t/Yb09gkbswaoJmtEcbZPyyUfUH0X8GY6h9gMa36jtSzzCx4d70DY6oUCOTsbLZY3XwJK8qhaQ8C
k/Sv9uujYpfGfOuiwl+a5yYUzpnAe40KU4nwIIKqRtCriZiwFRD7b6KdpUzj3NYQx2GZIdso10nY
I/vJUVupq5nhWjBE3W0eQCRkhrCUPBZ4CJbsji0NskGvInD2Rd7DyreUQK+ry/tQnt8Sq2kC7AQX
JmSiKyjXyyU987Ro6C55E6y45Xber2SlI0rKrNk7B/JG45XRagzufl55OlrD1HQSdy2P8kQ95dib
U2oVR8scvJGlf7+GlQNsQvqzvuGbECG+46t0Pvzi8ujzy4IAV3IXLOLrHthnM/gAXwKsRrOKn0kO
gWZzv7sxIB51eodkBeRsU0IFKdpfJbe+rHXY9zjCBO3rGxCviVsOlQhP20R72NYx7EhrF2cUP2PD
ZfO8icyP7z9gIN7kAB8+GiiPTgRQw7wqX9dIVE6ax3Cc6UhJ7uKgzirlTrIVg5h0pwBADkbH6sSZ
9p+WeGRczAlXmJOI395TCAHK4koxfALn2M3e1RqJ0WiGJblUUNQbpZuc1c3pxFs7kH6FzU5WbmZ2
lDCj+We6b4Q24E+T85W2U+zg8c2dtwfC2hsx6IwRhpqGjcuVHxvWHyUFhRwqJT68UsqhR85454xd
pDqxq1AyJGxr2/8PS5bdKmRQA+xV6HxyNHnMA0ZQs4q9AeQ1q9Z/CEtDFegC0z0d22cYMw4lQncv
URUhiGKUzwO9t10+jL98f4152TN/VGZPs9+tHlN6EVqksSuc/wjtNZkpAJivOHVQd1U4q6P5a0Bl
IkL95LSN77wcpQtol3FahE5hEHcpkLwmtuJWI44ie170OfQ8P6Kpoc90lvTG9py1pY41rtAIZLm1
xI4ptWCDkvt9P4Y/y54v2/k0xvdlMFbuKWIGQUGGDw68F78NAgW81+qvqXPg9CHHxEX0c31KOShQ
wONoFqQYkNzREoD+2gU1rH85pMYtV5Ggvk4Yt+9cifxka7iD4jnuTzolu5G4sciLFLuKrFP/zajd
HcRRE86ea56qMZMRzJ2k9hgB8SqT8Ll1tJ3y4EwUCf/Xegxihmqhr4+grBZpXs/Yf1zvYyfE4Z5G
xUD8WfLJER//MPMq0yF3OVkTBhkA3MTfR/TK7WWz3T4D6sJlrX4Vj5/dBxrhe9ycnNc5VrfK8K/y
5HwkRCdo4u0imwvmesygiTJfLfIskwzOmX//tBV2g2rtBNqKHk9CuIsmi22V5PCAB8busQ6Fozq2
jkfQmvbukxML8Xt39QgYJpYxa47X785Iz/wX9hD5hf/+kNOfrHnXmffr+Up2sQHwC7D54zcn6WLW
qYIQ6Q2JJcemYPPPIRECMgNleVv1ISQEhIA6K8u9GZxvqGwzoRSm6EpwC1Q8qsvj6hkYsEAp55jy
hCAYpDcovqXAik+e7TPd0mceXINXJRP72Ppfjh1l9YmiNVOclcWCTQB82nYDnfFC0ZDBrxg72Ov8
rch6CxlNPG7js8U7c5R1oXgCxS6qvrXPg17Qj6E1ICfVpe90jylPcN+FpdJYm2HUySP8d5bYgesg
KKkV1qwupC+WV/qD7imznvwwL6wfSEDB0GzodVp08+CdgoOh++NuHi/3iobuQ1l2Jlv905m26wnv
7TvrioAk6YJaBZrw++2ZzhXl+TbYTd8Up68QJDe8CdSdARBdheiFzD5ZdfsRowTvF5GvlbyYyyFW
9hJfAQBjrrc13lpvMCfEhEnhzCkM+ZhC6ZjHxyaEB8qnv3SGJ180jWFYsBZORO2CLp4hZO7lgAVW
j2rKqSOAPuS4DPhdSvzWCidf9rUf9qPj05AIBmtWvuZIuX6pduuvj0F9cu7ZN9462h6CgYMbLSu+
Oi788EwXwjtchoy42EyTPoe/g/CJV92XoxRWlDToyX/k1HmCS2yK2Gum6zeG/ln6s+TOmgi0e0qO
IkQPGvPqvyH0KqZufVeQLWB33ugRw19SC61p2pn6pVjVN+iDvhpINYgAaunlA0XsE35XdE/91w63
+OfVbOFXsDE2+nB4azfHJbkUqs8HYO+z3t8uNSBXX+mX/fx9LOmWfR3pBzHMRAP1q0QP+D7CSUMw
YhBCNI9sHIAqANYcdn2FzewPv1jU1RKfiv85GNx64768bNj7urg0PwyOkiYgEgMMKPTzZUr971WO
QC7zVvsydXVXZyWSePZMuxTDeVTOldxCc1zftOlUkEmGXss9PRcvz0oJFd0tXS0AYTHL2Zy0eqjo
DEb4C6eHbeq6dX2o6fbSFdTz72u6FhYRZt6fSvNnPVduqHyxOZ2AVjWdXa7AR+y/F065fgeS748H
9cFYEye0Qqw27zpW5BL7I9Mti3i2ya52EqQRrHIbezv2enE+IBSMdektyTcMRHV07wCWF0Ch19Tf
MQ700rhmWVPSrWzwainmUyGnmB/pMLS1iYePRhXBycAYqilZqCnu4kfYNVdxnlShdxeU1/z5f6GA
b/A25BS8w6FUsgACY3TZXnvUXMzo6vNiYhVDp0opOgX6dNNKlXe3oOHrbYS6hkDuZFfouenKnF4A
h2VKXa69l9d7931pBPsw4pyPCiqP9PSV/yBuEgznTccfKOHjWiCuOClj29o8Lfs+62MsbuUiNa28
MPxEIL2oN5iQiglzRmXpkb97YHrafndOgl1fnEyDrg9vNe2YujnmmyONnjWyzhY5JJ/PLzlAZKJv
A9/wTMRea57NpyxHOsu9iAdnRGPAX/xBFRegUUOY8487tjB+wmET7mw8vHNWPup9h0xkiK7/r1uw
5wBPQ/g+/0skhhCBCeF8SEhIv4Kqv54zN+HPvBq/7rOfs+CW7wd7eI9AEDuLwEOlFhLQvXn6z2+S
0Ij4jD2k3X/oANV0RedZoPLor3WdbPVEJQMvucaIEWi3Q6DKKxDWpHxgNUE78/BIK0Sc3TxLyrZM
UUA5SKGvJJ41DbYJ4fDtqI0HIDgTPbj0CRgbWqRWY/omGdES+aWp90kspaMR8vnTf/X3Y027qBbN
mhEtPTpYOnn6nVwEau6eicycn3EdXBQxkHl7CS/lveUJAWMNi7fn3d6mRqlRdst1k3NpkZoEJjzX
xHSFipxRFnps4v0ePE/TxUDdXRB9ZvWLqyQEaKekemE3iLCjctvp0sCPu/+Jw09zA2k8/nNshv6h
8FF4tsAivvijhocxan0Crr8j5InoPp0DtNCaBMhfAFUU545ifEcgI94KkSvMMBELViWvmjaajK8Q
OwQFau/qLIlWMnQXs6t76aal66zC2o7xqPv+06cVBIifEnOiTjbhYS+sOtoPAbrOVGMns5GRo9wG
js7V0w6MXNme/Kk2zB8mQ8GVxei1kBylH3OVVwP4Xe/JC7s5C9L5iA17YM9cu4x6gmeC5EZ5Mn8i
/ZYd8mdRXaFKdHKIkt0gNHsIFROtcstepjonJ9uPY6S6JP5YCHpw9pU586OJUIy7WO0eDy8NbDew
FQ1Rq5QM3okVbDFrxTeYcxDGoanV6oI8nuGxFJjqBB+ysHXyl4MoLkv8WFCZYtFznb8w3Wr696+j
/2nDVjRIuRaGRVFKln75/OJ9V6SOJN9w4bYdb2hklugyT4GmR7AkJTgZhAZuqnYW4oPfH6jKU01h
XwSwRkeZFyF4cqQObwwehcLCMHeBgC5AqZwRFl5RFoP6lMEzTEpC0ZzgxSnDgjCmNhcGr4S8rU42
asm7NlfGJuVuLg9FFZu3+5gBm13qD7yABfaDPXMdgv3wNYGSE0AMbtI0etqypMiviHv5tT6usq+i
91R6dhAf1oM1TOsPH9L8mKumnLHl0Ma7GWnq3Mqfamr6DZYTEKn9v0Zo4n9ZUh/HoJKhclgvwW3h
tQW+L7GZ6np2LUka99v/6TVVE0yX6fFjHA8aYX49OqqQvdxkF6IAdJ10b5t56FWWFVMDdWjYXJIe
aWwxhxu0zQt+c3d/jCeu0M+uWfez4AUGj8zZfqWV7VFAfxIuUVTC1m/uUcb6OKnALAYpPj1VS73N
m+ajBmr0uv0I3AUC4ZNzozi2lprOiBCaTNj0IZlFj2LAF37a44aktYSmL+qybabFi628P3+Pyc+B
lAbAVKvbN0XIy0XEIXm5+2UX4ItagK2STNIIy8b/BnryVRL5ZF289AlY2ShIO8S24I4sjWhR6/iW
ToI/3EBeb3Tt5Kn2la/oBFfRR/z+lAeD8jwBh0Qi/UjQj8IsJStXq0RtO8dQmHYKF3yu6BjYkmrE
LKGkJK/KogH5vNIK8eDKtPG7s9pZKv7N7KY0t2BilDsTGD9bKRLgLakT+PdCMOuxJd5VS4wrAMo2
FMxUz+3m9ZDZIqZb3H355+mfeLjXRXi/L/0cm3zW+ecfm66kqo2lQmEFa5CdZTiA1MCV662jaQ3c
oId+dtWDOJMrd6ZBtsej1xGwfrZdHm3TRwYAW/TzPrvGAeKs5Jsu/9tPyH1ZzwztPZcksglM6v3S
92QuLIoUyq5TZw5K62o3nI1Jc5JgjXzl8JYhtsdbM1201v/mliNyL3DH3uWFuPvQH38QgN7IHrVw
ZYTvp+jWVH2ykDMl0Mxa8NCODvAoKi9nWY7m28x85Ye0t5LvnRD1pymCdkGmswtcP4FPfe3GYCHa
GHsPBJD3vx26MuqyTdFDLHZ/Q0yw1196sEKLkpMvtugA7VNMa9KUJxIoqLgwrCNIzd7Nme4pjilj
XFWqZxa3EAWyEh5N3gIEF//6s0Zl2ncAavd1YWzy0Dq+RlPXJ16FP3ENkDh5JXWntfzAoRdbM6v6
ayd3U0OgxE9adKnRw8PoSoun0jhRwpUayUY0yxQNeypSIG/2ZauLJXE7nhXwK+Lo8ABngEA4Ktzw
v7Fj16UHq1KTMf5R5SQlNBAKosdp3B4XWmJjjSi9V71TmVXSla0Qum9G3wNMchGiBv/7mtoJmwyn
GYEnoFF84G8yY5Qq56uG5CZeeyRTZ8zCMtJ18atBqWEDG0FbLxsS01fZ5jHM4mrncVDobYhcc3M9
oTQJxJcHk6lp8oPqfZu3Lyk7hShMIqoM5FdfLnjOJUe25LF8lmCYim814R255LQYgdIb6Y7ancEL
is1S3VDTvsZoXNtL2E2S3ZCwvWekfVMVNI1HfouMLBo2vQ610jeJUq8RQ6dZBkHHOpb0KjkqCm97
MhUubQkvNVfp+of0APHf+4888jAyTFrDOHOTof1JokSwfhEKGMyu2nIZR3BVImJAD3uq78Fa8TUn
owZWl25qy88aE3GOtUexLMVv0zsVjUHE5IEJL7/EiYjIBlaxEyoJuxtMizveJq6Cnlr1Tw/anOH3
btbBvWqbSFlWv1VZKvnUx95B1frbN37IW7Le3KWB81Wemo7gm0omI7A3ZaQ4oh3mMsytV7lCYfhW
xblBxsuNp2ImeiBCuuBmSKXxnWw93jGUCbrkSXstB/rV8xBC5tJaP5jteQDSgt2fgIfHEoe0M3uZ
XmMy6qwweoYufzpAQ96GSK6AdckKaVKa13kWis+IQ/uZQyxtvKbo+g+CoRBqdNlaksYwsdxN7dB/
plnr+MxCi+KMonz9RF+Lf3KsIuyfzkItQSmlOEYWcPTXPxCy05VmftjrxF8NCt8Oq9bIPvTHSKQ/
eoFvnxi0N8mdUI9HoI2V7QGCI7vlkSNNIYuxTbTjFMmUI7Dv81RhNfrMw5OqMsbrQwcJxxj3wvba
h09th0pwYdkH5WlJonHJuRDGcfZtVkFO9tcBcktRGtVyHRqPKW3WPOhlJ1CRxT1q3rm7nTuHdaoX
JS3SZn+f9LusJGZDFrs0vUkwYu03wlvWGu4Lr5L79L/o6X5kRfqYFAZvyz0XxWQ1kq6NSLndu7D4
Uwg9IrpKT9QfYsuyhGiyV9PtOAJNGcM9stxR+ksXcyL3SPGKSRl4/XsXUFWui4SUMm1NnPkEfmF2
mDT9U54uhlXtb8cqLB6ZwBLfgdgT7PPFNlxKvEs5CL6SwqLxuUNn5QkUgtwjLghZi8TwbE3TWX4B
yfSAsI95TtQh6m0kh/LlHxCqOO4GclfJcpvqY33il5VgQkP7BLkYD2wTHK8RZkqXUq8nrCCTKlBK
L+e1bPyerXJ4H87S4mCtuUkbtEJOT2gY4LFg8CBK8FR/bk6gWWC5na5obQ4te+9eQhbqoiBs07rS
iu8RkQKgc3cdknhM7hgZmOPoFgOvEv/FmQHpMbU3yfEmJyJC3mGsFTapvqFOTZx1nhPsZe2/oxOz
1M2D49Fs7UncbHZ6e/0o0gK946eMVsGYbOoB3/jLKLFf0D2rhlsfeRbiBR396WlR9QXHV7z+og22
wLB0thgMpS0TMvermjBmkPUPl3n3Q8868avqZxyA5uJRvPAASHvXty4IedETyOtMs7JrtoQc6jFm
2//LfKacx/IuxFwAk01NFbrpCakSjJ327TRGKxXhpfvntTVC6MaCGg7s9DOKpusxorl+LDB1jLdy
mdLb2JFIULscvpy3iCLyOXcFfA9q+wgtxEzGwPJlBmFT5buocW4DO9Jq16ugtduAXqc1hExZLxth
LdvnrkIOHMX80VWka3+fNclFj+HBeH6nsa1Lxkjzw946N6KTIrzWFMhjezNrpPaAsd4uhSt/Do5v
6Xzcr7IdPtsn3sS04cvcRQ/2s7db3zFV6yv3jizVcLCiyLSKFb2wrMjvnS2WguhRjn3KMGrOzgjb
Oajtu1nISPL6Kd2bGUjPoQS/rG/HJDtXVWJm1er89Vu5Pss8MoZQoojZuuqkUlCEhJ/DDQbOxkJ3
Ggfl9rS++kVqLX6YQGbVTSxayDOxW9x7uuAFjZYurUcCtAxHk5fHUd5pXLXB6CynvNdFI20KTLZ3
eHIFRyoTT92uJ+APkMQeroomwYcFDkxlgkHmbordW1RPkre1rwlJbHrWXJ7KDfNIvfKAqVF9s1n8
38RbocQcUcDSiHpnwuMUCbQwe4Aic/TWKDjeEidYZCBuX9u5RcKnuOhwjuUALmk0NtzrxOSQBkDx
Tx9OzYhGGOYsxoOLzaM4B64D7HZ0yFan6QvHZQgO52PQqWjubcnw9NQNKRxcPB/qr2CuUY4Np6g6
QghAVZL5c0xIh+DASQ81xGHcYYO+xFxsbDdJNRrtAWifyLyx3WLHJm1xSxajTQRIH7eXkeklk8N6
2j88OUvFe0WgEMUMCAgS14w4n2zybnWnRA0Y0615RLenrQmiVU3icpTtEPNZ9/x/TiWlzej58Go3
H80HJw50YzvhUaIx8EjgdQtN6CarZ01EGxdN+PKMABW6WXU44FmAJJPcYMlAMT7CjAv3QNHTL9T1
rnoIu6FjdqHvfVGvtphzVjcncBfqyhe1uPaBV+E1M8cUI3e9QqmaRMbg+yeH9u+qqKhEOtqtUCOR
LkoP8AV2/cXyrPlaT5XVaiE1JrjED+t7wLjtixTtPKeCZaDsBpUEHGgDcQig4yNAaXtWimGECJal
JbXLyDsajDcQkHAq1LlVFlJhFXGkcOIWgoU7fUIvtec2S5/dqrCkhc2Kq2NNVtFGyN4x/xstugGg
1kiFaOb91c2aximvRO1bePnejRcf2AR2OMbqI17ynv+MjteTWTQds71AwTjo9gnDa6RKtadafMjk
jtHgEKS9XCl+s05E1UpzFTKROXnKqaDCrO0cb1MT0qITNyvH18Z4Cvfs4lvY93AE09NSB8a4YqHQ
knRgsgQxH8Eeb92E0ivqEBUHm3crV0Ih7hqXOdvd/K3WhNre2aEeQqc9beXyK+UL8s8VOjfT74Gm
mxWqdu4TJbTCj6Qu2KAtVzoGVcZIE2R65QCpJHz5zBQvL5rdxwRqPH3pcgO3nQJj7S1xLn0AB4Mq
ppJgH2XUoIT1QTJr2Qvx+Syp8p47KRLWPRkJ7vKKIj6rb1nm0foUY3OBrsgOlM8qzWr3oBXAC73u
gEYY4a4ZH6kakTbn04TmgP3bID+RiUjFTHo7ti5m7E7btSqury0Y056QgnGbJfzo3O4MDwm73f2u
4o6zGq+ESmk1z9YstONZKsonCixcQoIQdz7AGX3EGfasLzM33kOxhdasoPozwL7L9xTBK20Ct3dj
I9QvngBJusMf2ZV8J8o8BGUZLgol7ylzKm1icaA55KCb3LdXapQCyoTJs5hYTVRf0QVZSLsIHieV
iqkJUpjFJ4cfWh3GxiSxFz3D1CK32d0OCWia/vLobNMfZw28cG2nJoYLm3Q1OkrTVIqzkrC0yMUs
W+ZpUy7rgYwBB9pza+wSNkQh0gfg1F0IX9zdRvAr1bZ9IXeN+MmjJJTVVxDx+tbbA9/ZeU0jYmTM
DZstOiwUUv3PJruQb8uLyfYP8UL/e+RiGsFBs6K0Wi8HpE6VSM52TcnGje534PjzBVhvYKZzvidl
FGIArU+gXPzsbm3hYC2VeFZRrlWAKHVialDyksqfdg1VggPm700VOaHDGo1TN96ssIGCyOMTpteB
GlA8huY5aP/o6/hpF6bI4CqTKtBLIzms0Eaw/robm/7zvuh7YE4TU8comcxuqHjpXyWFXy87SViL
xiwfYGqFPAUWurrSFpa8/cGLdEtaVewIK9J9a6pU1VNfOnaYH6SHBidja3INJ3QW0aPs2VdMgNPk
XxYJUoqV24EZ1NsJRsRv2ITECd3tCG/YgJ2ce/uilKywLj0FDGduQ2d+k0AsEqN734tfUyzdu+yH
WUtxG3gu42rk+Wv4t5zWpfsxEJRIsVLZYKUvGJC2RgTKXbhCEJ9gE9Kn1OUlGZo95cl66MDk3bhz
NaJukrJzOPZL8yhGQNZnMQkhdeKVrleaNdq3nRebA6sPKTwCftqCwCibYjalf7xr8Vc2s+Xo5who
00RZUi45LrW3jpmPBlhNoAxHr3BwmvYYaRHdnwGZVWCufh78eda3IyYN5q2H65tRoQIY28ZoWmxz
Th17PGMS3mdOro6bAiMmdXTXdeL+vnDTZXiI0pxq0ywtS0xbEMh8N7Gi6ylQNwRpXPBIt9O/LCek
le++PeCG5EktTJMeLFdRB0pwfAGmIFy5cLgXE4MsHvo8rOyFtBfxSg1tWGLZE+BYy3XBD9vGX2qb
48EKbsLi4WPfugppR+J7lrt070wastWyykZy+tAMrFc5Y8N4mN6cd7mhA1GvhS/lOfgJnhSntoMV
9r1oRPug28FHjAvlpOt/Q29TsVM2d648fW626eUc0A6479nkQr2zIsKrTY9AjSXO2kCnNqV1N999
Q57q2Y0OFut9w5YzlZMFAS306EaJgFWmDSU7lq6WHeKT04XXfAm5QENSFOocSZ6ogHEwDAZmOZ4q
3ufBJcxX45ZduUS6tJFhJYkvQbYGXpYF38KxVhnwVY/Sz1OpMfrL4w+0lI/6oCXuAzSa0HMVw+t0
wGxC6Grk1nIH8tHrMlA41OQeIsAOCKI6hcDt6DbRlm57yQNTcf+c2baRSwnsr2InbpQ0nHoLTxsr
zqFmWDj/QjOru6QWnqaOvLHJpbmLh9P65BxVL52Kg6u/MU9ZuPsnM7jMejay2q0kuZ+th+2RzyJc
OW2T/GYoZdlYZjAG/NvLWUdBraRVs3t4ErLxDFoVSQkAD8dJ+HRSPrQwmtYHpllB/42m/oVhYmos
DbCyx3vH3cX0+zI0vpGAH4Zo5NKrLtuG4w//dbUNFCVWLt3H2mtWdHW5ygGudIz6T0nwqFPj6ZBk
fojgF0OjrXVuCA1wnhoK7MC8QbG0Afdfi5imwyKnXuZ7BnZ5BPcj88JFlcHM/wRVIIZ7CR4eqna5
crJqZVj2GOgMfx+nq7gMPM12U0VyfjGaLs3FKyle62+F5s8wNpopTrgoj1wFqr+ZwxVEmL6Mxwd/
LkmusnbZr7WhvGGuHWXpUmD27/awDBzVyvtkccVZ5VDFl1Tslk2j89YvyxZOZkFPxq5sk83sxlXk
ov0JqanH14Nr+y+snIzBQ3kVrl4RcfSgj9wjS6WJucRRaXw2/aax8/UhV5Pu4vqitzJevGChi69f
pBEJ2q6+rxQvZfSf20XA6DfoD48/m4V3ofTuT9UqHykiGMBmLPxkyVsyeeuosrmw2Zkd1GrORvlp
4S2x+0IHfzBp28Ykd7I8b6vjLp1MkLLGuPLJ5IYL8C5/S4rAyXsuTRfnUkMQ0GPnPS5O/EyK2hci
qZ1JlIJww7ePu9aA32fznjZMWZHSAV2NbTrHqijeUz7kMpV6Xtqz2ZCWsqv/qKf7tZRNdAOMb/58
JIncMUCfKJrGNyh00xs3y/TY4uiuedjkW4ylNArTBM6OmwZBYDWqVV1qhjR02+82DHk+LOHAZrSe
wpIXxCvN7o/gGKT0zTmlfLOL11u3jZNMP8fBkzWlbMHwspfnwJ2zqb9t71xSNiVHTLpMcEKMODbJ
LcvW7CO0tDpzTooRPHl4REDILA46OuuJAORPsrHxb7mH5uPShllVcQNyPyvZRVQFbfOhNdoZ7L0Q
9QvrWSrhFdG6iYMgSL3n/EVjjoaeoa2XMPDf3ST+1BSiDsUjFUOlC4M1jBsJHo56fQ4kqE7Wubf+
TaguNyLF3dvnmClE5X7Prb+tBhgSctmFYndul++uMZSoXSZZQ5hjeBOuUKhWGses/ikMpWSE6Sq8
94GMHHVUJXngWohLXO6z+UDOIM6D6SLMaiuhPtvRCWdz7Iq84mfYSonBejK4FEbpwVRglYJ1dsVg
KundW3wa0RV8tr5GOpgoMmgY52kUN/+cX050tM6JT09UcmA5adLlUaXNlxrb6VIZ3SWwpBs/kgyz
3Oa2OC9bgWDYVcKdIR2XL0HJQfv/UWZSEge+trNk59dzslrdVVqD8Jv32GD3HXKuKRH1Ly1Qo59z
kJNAyMl6fyT4PDwR067ctq5Vv/PvNgTunIFadz2gYvUQyBEc3K7xpaYRoszK19gAZt5tyBTDQ9yZ
t5UuiK77eaD+6X08oCrD37DbdtF8RaKjEZ6zf0Py1Ps7k4eQAuaf7yWK++Vb3Bos4j70PUyU2gZE
hbtwzXujeLyT1vlP5Wt/s7Pq+5ZKaR9Lbv2MUpUkClsTjUr/J9/tMyYl6flV1wkeb8kPBTMPMFEu
oFwfCA+lwxMke0mjzEvEpHDSWBGzdvYRTLP1L42p9l4jLQapJyOUf9iLfccJdYBzkTn7wqQuL8XE
l2Cxdsx6vd2V6Fvye8dsBI4En7WKPcKQDxIh9cw2XAqxrZbiOhLXdlLD2emT1RwqrBHsq/GC+NQ2
TZUeGT/zCkTlpDKJ7PuQtr2/kzmNZxKiR5pTszHGZAvsHK43V3Mdv2V9PKAxqg8x0YBYfdDgAsbc
EZvJowZc6D/lM1XQuu8VM41cx+0Gjz1He9yT3PhI9XWRJoMlR9BH8YvExcTxbx3udS1ETj6kLWPO
AFcMthZafr8BAD+83j3U6Iego540tGOCFn2u/OyEXiZwc5HE2pyF94HtGSDQiSctA/wblhAYK4s0
53YmdKiCaDB3xEs7QgPlx24u4iUNqjIsvhQgQf2qsOAVSjjR4kpvFXyiJVhAZcw3yH8xZKJI3fng
gGYI5b1HNJCt1gErtUz7TXcLCACn58DpNPvDDwU2JMcEHrga0gcLeI9nzu+L0o3PjwkQjZmP403/
R+rB8IVLLUWCVvAa16VPJOH2rhfpwS5V9mO0Yv5Y2er5GcH23uyflDl6A4U8Fh2L71vGXktyQjSp
nmLzBL0citpx+iCmeZxXlE6J0/rDiogXyaY3n32+P0OengrY+u7oineUx4SqEhDg6rOnkUGT+0mc
SosYZs3gtMYjewh2PuXH+5IBiVrL7dZ3Neh9lF3T0hWQBovdONqE4uipGiE3JeC5q7BgnJQqcOtr
LI25CpwvRaRDncougFAXq0ren7mc5ZJNzB7NtIt6Ehlrf2K0tjFYfFVNUDlQgIIutD07wneF2QJ0
LKCcQfFbXLm74HW1HiyG4tCn19R26/L37UoFiKqlnuWrZgXM/IMDFJulf7qmiT7dMaU8489s1qQN
rWewfTtrMNvA76ob0ruzk/23XDMiddLKPoWSfnidALD+KGd1z5Wzc0ux9E5Zy23cZylMhowOEGWK
6zh3ONVT+ozYy6sIdeA6hg4/QGyPyFT6mP7ZxkX8vS2Mn7WKx4nQ0hZspVC6YitRsERnmuRtjkXD
g3BPWKPWyqqTTSlxshji4mN9GwNLJy0EZONchEN2gq8WoCzgDQA6PDSgjDwsUBVVuwCsSh8RBYfa
CLKywyCC5Q9ipXpQmf0rP9iNlZeHRwWBtmvUalewzQPARjrZ01aKlHELUNsV8JNa9nKL+2wYeuxE
zPNUt2NOoPWeOuvlq+0js35DHES0s3ltRt9OTHcF7Gruh/63nzZVn/bUGEKZ/NcObfXJAzCUB98F
eK+c/TViwz0bhMePPejI9sfMH457YpSDGTvKlLsvmYhINeD0Hnr1yL9Ouet2A8LFCRwL0AWAByPO
4M4tjPYHWFYmNnaXSoJo32Ejn0DpEMYXHE4+3MIyNytAyUh/ZnmGBTG1VDNVtDA93q5xGW0sDZc+
gvlKDNHr4dBVEp6xsYQiOhH4reUOsao+Y9FPxBwJQAA6KfO4f/stybMO56RbnEHOm+kxbOCj4Qzn
xvQNd/RNTmR/um5gnw1GIQ0VYUsGmELk6x93B28ieQp3g+hNUtDz2Vu/NDA4/jqU8Y4RgOJgcOdJ
mPfwDmkWFfsJ0z6gIHmhVmfJQeIAalovckxvV9jY8gbt16C0hqKJuv1UynIHVSqmH8rWOVKx0oPT
iBTzC66elVwYvhQxYbu5Dt4Zah4KWDcCfzNHeYAXEhOXH2ohUo/8KIMllS4AtVmRBeHtbPcY1ugt
DFc/CDlfB5F5IQJIFnkVhfggnktmqFT2tJRyLmJUs8lDxg0dnFXoNB+k/1FGyBBS6Ha5C/q2QOSv
WgepisVsb7Bvhb5oW62CSaYyYo9a/SFCcvsXaMWobDyI9YaZfMlEs4OVWBhMSQMkxgCM/LlV9Mxj
k82WDI/vz36XHunorORJ880rUvMxZp64XvrNtOEa02+7ct2FkNzbFSEDEyVDQ/EzXzC/KA8JFssl
8A1S77hWbZHw5LPNGBHBAQByK4OCMZuRghjAg37C4fGNV674ZMldBY5JMIcF92+jgbFLYPrcLeTp
482tDy/zU3X3Lp0i8P8BppIn/rfloLjeeH8XtMGfpNDhF5b78SclrWCgGuEuKcU41m0osWWnXVFG
dnQSlAysC8KIODKl87TL/eNW7twd39JFzKuqQcDkIeVy7HjV4pP2wV/0x59YCccAiD6DOp8ZGsUf
Go4wTefcte0qm0v08rVYObJ+dLBfDtwZlPhUTvwrm7l1WoOX1OG+q0VuNLo6PF3KYx5X8prgBlNp
HZUhy5/vj5vKxufEdiUAPXldUWtNAwpdgwoMM0dMeAc0ZVgKLwscNYxHYgpPAahXhuTIme59NfY2
s4ktLA7E2UY+rypEXA+qNFmEiRe2lh4jDSt/H5N+VLp1NQD/+1SziqmTX2DKXO84XJTRa1UUMQTE
BGyd1f/FjFePoR3y/rD+IBsuzsQfq7cgWHpStOjs7X/xLOh0HfHGaTiTElY08EhzuQzhDiBx7fOw
QfT4JJmyRMMq1sWHQB5fYOAV9Tkhbo9ECtGYAHBSy86iLKOIIyD2rji5gxGht1etwkPmxyenTYCz
Xmq6HSc35+KUg9vJTY4tzDz0KchPrAlBzII1zLxAatDkdpGRJPmziYZCtXelcchuTH/1YuTThoJ7
f0ZdD1ox1jMXJFFYZFIQFYyHZz8hsLvcdeI7D0QANYRmRT89K3N3KOAP8Jd7Y96RTXjiO+PApl38
RxIn8V5M4+wfc+a4MkbwBEsuqXqTtH2jVvQTOYBTa6oYf4cshW0/mMkppFXndHW2X74Q2Dc2OljZ
gyLQ31M1p5dSkbTvmi+Rr1SQ42oaSRFQ8qDzzlQ97+gQP1/q141X17jvR4VdkZwo9g23xKgQlvM0
3AGJB9r5kXGzXqOHqco0//NS6T4ZtlSBQ8vUzhTcd8AM3dBkn23eQS+7hSlW14p/h5uYAlpGA13j
q7O+04S6Myp+mbmJoG2SDjQ/zUHjFfahgKHCaQdU6LYzZ8/7UD7eRnJCMVCy4vL1BaJHW5ONTlv4
uBXjW/mYtcEC1kcu1QRXiMaSIOMW7H0C94hBcbexUwLLjz2ZNFIlKHD8iMK/ad5EJ/TXb6kbrId1
pOEY/2JCcWJsLBMxZhv6VcFui7YJ0F9zKGNb23L2JFI2Z0fTkgqs/UOGTQlZzx07Cc4pw4ZHg+4x
krw0EYgD+P6qE8VGoGkh9HTGW6oplcRrwtrtSpctPU9cy8TAOe8Zf9XLkfgyELOWNBviANFkFKj1
zVSb8HHUOSdMlVHdSyBR33SEvb90CSFVTQWgfVIwdH+NtAx2rp0ri8w9Nq07lCDkZz5+CMCJlYfZ
6jTQbeu/uWGKZvH/BaNLF0viSZSGWIAHgMaUA/LVK+//cJlmU674vMGAmBCC0qO6AEIP9Ouaq8+j
u3rwUxlBF7HSXAtxoO6fwWXm4vm7d9X7V4vyv5TejMU4X+kDxlo4jMQrjvUEgRfeEH41DPQfKuoU
XHEbEzJSqb3MwPly1m8QT6xHOsfd6MYiTJU6qxyQlbz2rk4RH/Zp5s+pFq8e3k27KiaddXtbs0Jh
ny5ymV7LV6znxPlh/8XrgYa7samye6vRgFHK3rlXRq9FirxvKyz53BaA3WQmy4VR2ijnw46DawgJ
Wc4zPg6BFdX/L0OeCudvWsItz6WngnhFvYx6aCFxxL78trzIeMhbxJsB19UujB1bXKgaxcx5EZh3
wW8DuEhloPSLiN1ovvYeX+mC/Z+ZlZXrWDLFcV7Q9aB8X0TFcJAPJvdHNxO1v4cnqWpjqKL0AFzD
zhjDdFXNdOX61qLUJX8qCfHfKZraDlgqNXHQCMFNElA8+RzrA2dwJUR2gffd5xvrhha2/AwssbK+
FWyxeA9K4kdyJoP/AXJbczOIKMRq/IgHpt0PIIdQYXwLisJ+ZvN7FNdAh3G1xQ2nl/8snhm6gw1O
k4cgsj30cj/D6Lbg+OzM7ocJGDnT1Qo0sYErs+c/KW5GPXRLycskB6xnAoIFq1JLLvXN1AVhsUhl
DJEvt0eWCwvVtRQ5OFcarNIO+OBaO23SqyKWKeBhqcWmTAaPMpzE2PBldrl6VzXl8G8UUtdEKaNg
C5DzRGgSQbnZR+zmG+/iVVtOsW9or6rWetSzyanp2gEG39MgGmtOKuhPsMKVEC2b6iiva+6BAm1z
ijb6MVLhsTEHU+U5A+kkXlh7tgF4qsWR8S5jIuTRxsm47QFdFBccR/isNkJiilRGmZw4N/iX3Urs
hzgvS6twm0cF+WGsoebwfb6j0gQIYZxluHZZQKtPb8ulROsGFLVLSrl8VnYZSHSaRnFag3gzVg7m
Mm1N2i49m8+rJ+wU53r+GS7bFVlbthgMe4QWhjuOl2b3rMSxUB3211K9cyLC4lKr1V7njLqSnGLS
95RI0YnxVJnKfb8c/l23xDtvvnIuQ/NrwtzPrYGq7F5zedIiUbF/9rAmeR5uCSccKtYGzHukW9F6
RUSICthZ6p3SeQzfMsxcu5s2BQfZlPpX+2b98lsgZG305dv9MTEyZgv3tdpxpsR5C6fj5P3eO2Gg
eprpbQe3GFMRKfxhoJBFj525EUCXPqIUV029/p2xC8ZAodQA3pol5Qx7VQNpsbOLCWZ4VPECGuZb
LnnKS4TKaxkazcxhlHwpsUNrXFhbnQ+iMxR2hp3b+poeFUUciCjeJer2WyXYFPf6EAIMa7KXAwyN
3y3kNgu1jnxHE2wNUVX9D/CTlZjJKDLoL9jcH7T4eSSoVZYzWd10ki5gXbzYVLutAbjj6YijzVhS
flQI/083/izwu/mDHVKALIggPl99cyxdg/EmWP7y+PFdo+d5EIgIwQFPFfcUILb4CeeOELjyENaM
SUHAdYCt81FCad874yBdH0GG+OJbx/ClcEhfD4+ZKvnGfoHeSvKO0PUqEU5DheipXz23RQIZZz9C
BRIH+i0LPAFuu4h5IZaCBzWxL5S6Jz2k3ndzXmIu4USenPGbKmQ14QafdQqMZYPdScOfO09+YODY
DOAYpJN8p88r9P2ZW4zOhrHw0WS8mmfYpJQvJZVqy/FPzpDpYP6EifgvG4raLEvwCSql94+pFi4A
11ZWAOL2dfInu8ROS59jutFXNDoguYZNiY9gP4iQSt0R8b+Unok0+eyWp8x4DUGSAXROwku8embZ
7clF6sOUZ51SAA0yDB2Bj7BO7ZMBU4GEIs5dFgfsgfYUO+RmSvKxHx3LurT0v2CSQ0GQ6Y/26iYT
KlAkafSyTDAC4G0xX0ekxrAZmx2wDVrFRuu1TRy4S5JHz7QuReP6r74UHpXh5W9ZVDW75Sd0b9tp
/7CgsdoaNnYogv4xmbPUKBSgQj0xT6eF2DfOTejm7J2qR085aXPr8uafAvF6hiIBLSbwZpEwzSS7
UHBQG1cl1Zz659U+fMS/kbq2pFUL+iZulafjfxVNjVu1q8Cw1h1dqzpoIkdNJ+qlaDW9Q4GB17XR
kz9eXJ6fogV84GOhBWhw7nCbhI9pAdcVukq3X+e77LhbxHRjdC3vs4wVbe1Pl2M+35sccXENUaHX
w3MtQ+8z6/TlY0RWObw45BgpiSH5xWuY9VirGjP1aoSUNajuGiPd3zuaHkwb7ud8LNyITz49t1M4
M0QO2JoajemH/WaieCFjmnv5yKBTdGie+jkCKqg3wsQSGd1H7tL9yeq/mET428mGha3xZbK6SS2y
/W07hT/0iaDavW4bo6LZ6AuOhjy2V6yJM3u52evZCDKlTZ8SnadgX1MnQGkQy2lz0QYJbJUfPbO2
1ktzsPlDAQSLP09eW+o+Xb/lzZg0OMIsoPjwjjUvcvsYbRwVVPlVFjmB5u4rbbpVryJdIvwHg04M
WgdYSEDryIEjYx18dDNFV8/grdhB2KfH6p4NS78wKdlE3VMe6/TashF0XsBmYhRcfcy/gDnRaMO+
kbO5lbr8LlVXp4sOn3YJRhKGw+eL+RI+D+WIUGQ/oMJ2wswCIqO6EGRlMo8JOlT3bLWOsGZ9oZDx
hJWNvEkM74f3rtVIc9v8mEXcdIOX6zulLtl5GyenA0hWuobOVLkxyK/R4Jzegl0ePh5wzKPBXmS6
h94Pqddn/xFEOlOK9ztpoa7EE0vomtrtqKmvDqGZ7+gLYVduztjNL+PYoB36Cyr6IK2u1dVwK/52
JDBtROIThDZPj/tJ6WF5t6q2+I8QiufP94Ji8CmXoM4aIgkDhq033FAILKemv8E3lWb29nQwg6U5
CI7737rOlmxlo43tf9aDouzrbRO+KtNDr2S6L9a3W1g6TRZ41ezQLoi1GGZ7r3lTcWw5XpIcc7nX
kxfNthyGCvTjUKM1vrBpOhh0FAWn3P3gTZmgVILx9xvg1HlzZ3PwKCYZdBhxvVKwNTpOsLtjML0f
aCVXxxL1Uufd0XahCPI8BFlKE5zNc3YF8OIC6QzeGenbLCuxVBIno0tCYKvUisFWmOFNXJ+ydEOc
o6MfZXLX0YyP1pMDT9YBmoa0RMFg0MNWiGqzv7mTgYqXADbEFz1tnQF0u9Y4NCPboC2nasuXJGA7
87xdwv9IauY8ZULgxchNOPp8NCZ9GDFJwwEzpHfwIE3v+VKW1Rn++7bPkU1oKn8Z8x+pg3za2q/0
YF5b/24/hspJk3S8Ll5qTczSrZd/4285K1SOwRICbz5G7jIzXy1bxcq6Xr3TrNpk9YXhklQa/EPd
nCpSTSPPH7sHy+WmiO9cSJpviAiK9o3pbPJ6rqBGgHsXRoJQvFP+3ib2cx1aRdHVEPclapXwxue0
b1O0hgs1BcD3lRbWVlIugtWwgUnB819JkoD1YpzHLdJgQ2UNsPe28mZeBEZbGUDS7VIYUefbog+y
M9Gi+lNOY9tTvRCb6eghS17kT/UTg06tckdd+BlKwHmTFdcNcWotTiNABf1pFahZBbe4sfzWKpFe
l0gqxmcVnWTOqBXq0vsywnphG/20fCKrVs5pAQWMxFJzY2+QEqioWnhRT7vR3CXRode9YO1iAte6
gG3hDEGUywCHyNJ9/6TtSp2LUealLvqo/R3m8NjVXofixzwvMJcX7o8+P0q6IzqGWh282n0JEGYI
4h0ZwASUL7ij/6zNxWlLIPFbtcqDuNeLLkUCe6ddKcgmjG7JBFmGh05E26le4ZkTm+QJsiRDmnzN
xCLstMYFXN/GNzec8go5cWrnXX/zYL7oBNkt5y6x6zqwPw1kiDlIQInajTyZHWFehLZaTrY8uJUJ
6vXl2CVRfW3c1GKsMq//i6Ie1D/gblyE+YmF1Q+YlSNVPEsgYVKah+tcpk6waZogzRSdbNtTZIYF
pxbKkw0KjWSCSgbnmrGrgBod3K0PrN3cMgQzplcygC97wwQHD+TkIQWNEFadO+ridDuI/NnTS+k5
FXc0/9S3aCsYU78J6xSFYoaDhXe4RenYu4gChs3gCZM+2gAXZ24ttGAyVnkabi765pO+Z/ix5dS+
jd90wgg6K5BtndBelrmU/2aWLJ5Udi2oZlQiJ2lrqy/gCvyFGcwjHp0zIbhHCky9Szc/h8LTS+Yf
+rNh5TAEj3JBLOYlPD+95JUKR0l1oBvvLoc3XK3QvDLXjpYr6EteHlhmv/txjYpx6ER9U5FHCWFT
bGSov4fvZsEEH6N0HDN6PrXRkfv9Y86CLXyyZN4hYIMN6qcZ4hI4N3SmPHMEfN7k26csa7TuZMsj
Qf3vB+jelmQBPzN3ts6dQRn+CPqg6jbQA6lR3xgPhV0eQbwJ5wUvwKJAsYOZImowl2lwyVgrZ9Rr
ekOMI9iPxATz+nNCV5taFhdVxHnrfWZFIdGkTXjEh4jMLrfEvZPEgQE3eL/ypSm0a3EX8n3I0jWx
7tamnH0x60ij40xVQzHMHxQXrpjYtVwEM8mjWwEG4Q3EwLBw9R+nChIl7AB4qFoFt3WiJjtsG2yW
j0MyOJa8JUWteMN3Rx/2W8CZIw2TL6hzZ474nYoYlvjBAsp3Mwi5MMJR8/jPl7a+xzvOtXMI4h7M
8JltU6qZ3DYLfJfD7WUSVeMQ7Ae3bRxhnq6lSUhzUGr1sTDpikDEpraxUwekgdGoeg1wau/L0Lh/
iEVbP72uDuLawQR/rDXNmTUDQTXC57llyVvPqZzam3k8dKpLiO5b296rw5+M3/4RzGAmkyeBEi8s
yVOVwxbdXMwqZmjGmNVNj5Tm/RLoPEIqnp9p+M3wTwDqetBCucS2No38YhkV5wXRlwHl6s8l489U
2YnYaPhiIzfQ0kfTVjwPlJjE8e0BVlGfQyKTyccnt/I0dY+VTVbKrPE5OSiOssajWNoJ25xoB+Hv
5EQv7Z5rVhmIMpx9gsZYpk8fzs+VYKIwbSOOxaLmUiS2D4pacYpCPDRC+5XsRbCZb0d+I+PFLiXm
mv9XOzD1tHNbZpjMnRGyGCStqjXuALtGHX7NUdQ17zovs+ppm6tE2kkYfMAkkRJ8M2HeP45UCMxo
MZS3mCsbl6TjZBoNSqBBIMHCE5INNhctAcDzl+AaRkXpmYxgLm5Dm0ih9flZCe0RvVVnW0Iyb+dP
QUUrTUuXtK5ZXDmlZeXoen1/Egp8S8xTl+OFsdwq6RVPBP8poEkqj8DYvgCVpcnUQXYd3SimxGs3
0IYSLEHWxGGwtFT2bY5QyDOTETVJVtWODwkTyPxQsp2mFsAoPexXGgtaMj7CdBodAlvYmjQUhcaW
RT2cXQmgMwFp62xzRG7ir2IDYA0CJYnN87IegOKa9BVPjin1Y5Rxbnrs3a0UONix4fSTn49OTnil
7ZwWmcJmMo6MBC1XpviF9q5Q+3zBdWF01ALxh7OQeI0hxMtNci7OeXj6/RvZQa/3z0Y4SijmUpfb
N18dDI4iyK+4ercMRndSeqGFlx69R0+qXwBsbE3saYY5KNTIDNg2PZORCv3KbgrGSigDxxZsf3J1
FPGwb1jOMSQtAhnBwjGuWrjhb9QJttWZ3boIkWFGMOrnWde0DzCMH5CSLecUCDfOwZYb5e3GvlXV
bfBXx6AT+zPalB5Mo6F6Fx/7RgMB+Eycs1kdwotah5lChq3ErqUi5Sl3kNWE0BC1t/ofHisntgPD
Zfv9rrg5XY/ChS5SmNKf7iJzdV2eCGsE0zvcmf3Rt19DYnJzyFUeUIvT5OICyhjLjFpzu0O0YVNO
GxqLcQ4dKDQ0774qV2UAmn7BHUkG9FNdc9QfiPRRiRkZHhmEfpp+THrEEQXOjPlVVfER9aF8Tg0q
vWcC/jV0rpqLu+kB98F19SASUm2k41UJRRbdu7TvygjTthZajuhIys1REHHhLB84XwnNX2zLEt3Q
TiO+AKs80zmHJC4PczFvstaBgq42vuv/zkRPuD84VNcRL94zzdVCXSI2EAdMTsAF4b/F5s7i6H8Z
fAlCZGo3nJJ7yZ89b4UO0D8E7X4n2dFmLRtXqji3Ex9KFPSu8LCJCvzgx6xSlgMLmEovlM/C2OEz
CTLAjOUou6JCPF++VF1kKJsDumMQ2yr7KRztVgAzimyubfQT/UufNy3Ayw9uQIW/5Xg0idA75D0V
En7B5HSNaVBezOs14xtIdCavSUoZxEoT0mt8v7BfRIz2UDCj9P/sUnfAFQe7UJvIjMnAyaJ2yiJI
trnq2wktx4kzaZHaeJrQX9nMCKyCINjedlW7aUNEw7s+xzbq4MyOwBo7tnQ6XUeL1yGMUk7uSQ5d
pYgQq/pXP34E7AueoDd1KmvcH0tGYBeSMro/WZX4xOaLJGpyqoEXrT1NmZUfbslkYpWU+3aWVakn
KyEAAWtToBttGVLibmWOVSDwH0N1jB2fKuZ6TdFLvfq8fe2WSBUdTyzKlHad4Bk/xeX4ywSdC7X7
pGgmkKVjKqqsvSoXv/C6pUPeQeYQhpJhjj5XhCXywNe8V/Lfz1eOetoRno6YK5yid/fAq8cy1Ka1
OXUoT/8oDt3LK5n6rVBB9l6hpCPKKfNc9u1jXIB5Sgg9soyT82f7IcJ5lOxmjsP9phMkTVXBIoUT
KgwnL+H6MCD/lPdPBpHKU1wv8dHzKEkLiMJYZCiPWKGx1eLtc0rrQZmpu2dZS1ANiYONENpD0tFD
NXkA0KF+hZkHIWVi2rrwO9MPjGeir0D+LRrpplP/pCF9Gk5Fa/qZR+KXa19cjz8Icw/ksv1UJETe
i2oyfk6n7wIzPhKW+URhdmFh1uS9dQZs7bTJ3UtCO0zIUcgwKkmEAw+neAu4bR4L2N5t3Iu3PxRH
8IfJF6ISyW+qjvXU5mxxZUZkd43Ib+UXcQJTpFTJ+YlPCwRw5HU7bOJofc5FiGvJsrZt+dUTJnnR
5rX4P9yQBO/0me1IC9FtOBRuQs4sMDAnSEQ9UcUErP/Iq7YykqMb0uC+Kj1KEnj39/oOSfYHTsf0
6Mq4FzemajCmeSZvXthLnVy1NiDBCpM2xRBixSg33ds0CZeFxe207+9nCB+0QOo0tBc0hf7PR59P
WGbzihR9FnnzKU5psrqa8HDYf5G4dEMZHNwYQwfLyYSaO2BTnudVNGJsCrxLnbURV/likQtFwhaj
U+p51h6sZpNq/wybWyxG3ZtyvsGdqdXcB8+jC3iKbPPC9qQPKjfOKL8+xMdeym2dlhF+hXfra0W6
0GOUmbI+xURWUHP4aj6Rn1XH1b7Rg6iLSJsrxIO2u3p+uvZa/+hvm0xFVQHZfan3DHkDlufZdOC9
v4tD32T+frV9YFAFI3EzylHjqNfyLE/xURRVBrDPL3pfZU0SrCLuCRERJwM0/ZKjIdyi+oxzcJZ6
7Vh3J6yMra/vklguZQRk9bCaABrHqwW2duEvQom190fHn4+73kESPZ95rGvxPWyLngnEgkzlJAIy
od5N4MNBKqEjFRg2PrLxuI5vw338gRI6DipGpw1vZ08/rbN5InnemcFcUMPVrF9SrB510ofiqvFP
qi9qc15sqHd/uX4rxoj/y802uc4uI5H1JWqvQ2GxSTt/mc++hC4aJL7DvWMiigyfziPKGGBV4+VV
v4YU8QrpObsm023tgrtpbZI4ZYNZgAFkF7D7Fr5tisLp8C0t1ohKYVeOnJmaeXI7w0XV+rodWOkS
7o96SSZbjEimiU2jEc5K3TB6uNStRZ4ey/49SZaP5Q2rL2N+7NfrSbSJUoeVjgCeaM8tpeNZTSfE
ZekeG4qH/utVte3QZWQe3qKpM/DqJi5aL6/1zTdgiVgEoN7b9Z8Qkq3sYNCag6Qg48i0Zzh/Zgco
V2GKi5o8eND1s6H/HhkFhONsLlMiHpMRI1fNMO73lyVkD3KLplhdAxS9JWMpRbSMbWuYeb9defGn
hEu+oQp9yQO3og7FDE+MsvCv/sK+CBXP6Nem816WWc9H5fT+HSXsGBYEQYamsmXBv2c/8A4kFFFp
cwCENmoWdeL6YlO9IcRU6XCpEasiEjSLPhjz0gHdDt5W9nGHWoB0Gceo8aG9wFKIlWBuTUPpq11X
E9nGkzGBlfN8de9lf21sYyAHOsEw++LoUYpuUzdHwkcKBWI2sxRMs1DWizlbS7cY1uYUZWSrdw6f
QVA+OAnym+LL0F+q6p/Wy29lhgGGB5625rUyengieb+hxQVXhB/MGIyId6WNYrUshPNnI2EHpppX
29kLUGTHdsmbbYRuLeL0MvaAx3vXyzeNChRDcQkeNghTPfdGV8czGbtwH6PtCRaTP/lAlraVez4s
pwup8kifVmfl2QCajEoigH8VLlwL1a+SyvsItcven2M+Z1M5DsobgmwCZ5vc5ocUQNO6vw37bDrW
vyz67biR5Kc1pBKU+WubLMSxW7djEW46TMxa2FDOyGB7Yy5RY4bSnQ4n74F6TDdIPjJBgh3+ZcZz
9PZ7DERVKLSQhItbYjhHm2EVRvR9s7qAqeNcq4K/9qUcZ0a/PZYv17mTJLnE3RU5Uv1F1x2HMqZL
oZNZSsKN3sWbAmM2LuI9XBE8IzdbCBnz6JZGFW28zLHU28SZNcwFP+WJe2TWv5uFasnjuNTm39qj
bDTBxRGezMZGqL3QT+YnE40/DxahKpUb95lUIsF6AKsS/ptHc2bSw/Jv/AzxoNAnKYbsmFJVvaZP
W3k5or9u9pZg6V01z5Puztpl8vp1KkIRr6vDYKqXzudLcM29XLHXQXcC2TLDsyYm/A082fCXdUi0
9yJzSmMXaGG5tCk6iTEXj6vz/xi/2lK3Ay1WTwSHBFQ2Mwt0TNpxdSa/9+pS3YsPkpPBWXthu/8J
nXp5ucTb8I+H2Q+rabTCRTW/AcZss5swjQ35EvBXU3R6Xk1ZHWxTptgnKpgeW2ruiuQ4UD/QqPGd
7KGLWl3XZr6FnAROw0XOe6C2BlsM8aGp+Xjt4TomTdAzg6EaVQfh0V/BWpPE6vA9dNYvi6fQ+4YT
9rmL6CggE6RiagYrgzGRP7ay2VeMBXoGH7r/Yzsg/vA27n8YH13VXg7EBHFFppREoelNpXFD4zjN
PI0M2ov0py4wHtoRT3oXQ7EprzJ7i3sC71INRxhhSfENDIqeHaR6xxxEiWQo9kZ0BuJQiNT64y5i
fx6Syq2RS5+6wDVVqgSfeEJkUYSxA/Vz+WBJFRHqTfxfpuqvD2N0UHiRovPN0iDII9wouvgxkQu1
7j8hqdNjmIALmRU+NNAyoDRW9G0irvoJyEuk5tcZzlz5Z6imeMbeVs0BjoDdaWU8eaha49HCYq9b
YCexYtMcf7DbZC+sO7+tDeMJgPDxN5p8wpyN3LAYmXKA/8G1Q3p0GPTNyKXMGGl4SGIfWdJudNv0
v70D+JM8URiuu0cXcihjkggGHfzmlxS047AXUktcgufIG9UXFjfiQLlaPATIRsHO/bIIrZoTXsnd
OVZf3pcUZ4hgjCX3QMSmpJQQXkmqupMgvMUEw4BGgXE5vTU9flyna6MYp8+YGVm2c+t/cKqS7dQl
avjDgv1eQZBfxdASOy4lQPfsonTnWkI4Jufp6Yxnu1WXk/eveMNkt3QZM5FRR/dogtFLq6lXSqDe
m0DeNRVOgR5dO6aYXC5mt7jvzcJOyw4GnLXN+BfqkubJYiUNACIXQx5yZHxmHrL4otf3B9lE1KQf
Tv5xugyKrzFIIH10uOZToWCPSJ/7ZNDQYUzw9vYxXU7h+/qLEgoylXhoqNe7iCWUuC+WCKD7qdM8
rKztcJN5ZCFhFaJzDwZaAyugjxkotaQKUbDrpk9XsezcBqXo3mhs6F9oS3vxNN5QN4Cc5/TPBJno
zLZrPs9pW7MLxsTbCI6XhXf1piqizdbXQclRm4ZnC/5gHeG4jxLH2o1+CjaEdjDFz3MY728CxBDx
BlJHjeLF23mZPqyi7Ecc3rOFnEwdzzbFni8XXBDswyEPeyAvtfBrqZccReAXN7kNe1ljqU/H1kpy
DF7/qZYXUEIZpEoqo6DFkjEz8psthwPH67D0jQu5HlRc6myaeZ0epG97CzUuzRKy8aqjW544h9Zu
0yw4B0cLXC3+DB5c5jPR19Ix1NeSIoymbRmq5a+61lM85oZ7+l18yt9E4ZarQTlM8lrcBPyF3v3m
uHQwp+gPEHwSBUlutkRaX1P66blJxF0EHo78DPqMLjL9TrR89gSSPOCwp7+QQBHtgOzGYUDGxPQp
zk7VKQUMOSyarIYZJAru253mR+GDUHwvfKIs6UQ1m1ohV0CeC06bbhGBKRll7l5X2r4+7s6Prb/x
PYzmRgvVdMx3qU4O1OpF7xU1o26FEjLbRufYYRoTCqxo6Ohb8Uw1mfRpmueFV9W6RDnIi4pqUl8K
BFNPNPerj0nSPrEEHO0qXqE3/XF4Bcoav4/hl9QWsUV+sb+HlRin7FjXcKD0zH7vQA7gPwuzlvMT
iObmKWY3ZSyBkbRX32pbd7Uq+H+5OYMCIRMlzFCmcYmSSpA8gzyPuLCV5kPa0/Z0olnGFyZQusO4
7VHqT6W/Edc/C2HjRYW8mYBC3FPRpiCIcTa7o/oZYVdGDBKEdVb0Vj6P1RJwRykQ4ZMhYzD9aPHk
xQcRaf606NiWPEe71+r8WJ2WWQidPezR8P+jzqrMMEmm5cxgsT/R7lD8SrDyG1qbW4pTVhzjBrri
Jyy4JaGLkv2Eo5KbvvE1vq0SJkObEY4nMsfZH64cUgGRBkghceooq92Qw/Ny9I2PVuFDUU+zuMgT
y3w9QLRcLWHg9JME9F8yYA/qqnt57rbsYiS9s6xRwMQKYNX6h4P2g81ncchfe0mOyFh78glvRcvO
DMcm7KRE1yq0Vxspam+QhQ7WuWg0H7ZU/LTmeyt5TJvDRz6cUROy3Ifbw5IPJOZrLMkUNEZ1zioj
Ahr9kbS/R91lfGkflhSq7xOTEmcxpCrAd7dWYwjxYFCumkcRMVCr5iTBnYSq8AbVaUAq2JnMDPKW
H2QvYpeyuaUKWKQUtMzmM906KWBiKil2/RjdfrxXWCrdPmq+uKx3lUIeZzOeqo7ZvNGv5crOi1AF
QwPvXJUTOMtjGnOD7aOKHnCi/0375mHKHSxW7+TlLZDrWmduwXlj0++eUjN8LFjkV0TRjY6i/Uqz
/HPNBWT/5g4NjaFC9rAQWtOC2ZuFAhuYjfXQiU8qwjiYL8WSDTfNTGTSGF+lKoo+CXkZgz91YlBh
bd7xdJMLvZ2MZZHRXvMz4spMXUTujk7jOQLeT9EocFIDOyi9ms2wDJ/cboltWOh63q4uAh3LTLNj
OLii97JLTUaXHENXOaZCoBO6PgdLxJjKSpAyJSaI5UQn5J2V0iULdAKIVIhcd4nzjhzYqpcyxmWZ
t/mcVuzF7nsTbVo7E3mi3Jm0v0ldvnWHCvyZwC+dURAFeDKmt3l5sEgwuEAgdqr3ND5Xc/1SWwKa
v/woJzZciNJydD7xz2AFuysUGgkSmSbdnElI2/mBZXMtIH6PUIJIYjQBjegM3SFZTliuQ0iL/DMc
vgDA0N94WmPj5iUYLcqtAYFWCoxYcAid8rwk7w5NYmv0AAh0Z2xvQQWrzp4od7W1twj0WFAFS7uo
FNlsjvKF2vJIt0akt/WvYyDnm9oFCxB2tUzvRJ8g90dWeWC6VI52Ogo6NuA/A9e+IDZjcLSu5sUe
NZG52aoXDTSqnkrK1ytdXb/w200Fqc3WodpYDst3KjBEw+Qdy/4Bs2L4IGsJ2bwUjnaCWNTQZyXX
UfJrLR6fI5JHvhiuhIWNz7U6/lh6SAARwSR/voxMfpsLrXh7cfnVi54nEi+Si2IgnIHGztWcvPfx
xfrrdHZLK+qWPkeMlIInP1fs1yta8VgOTKxg2YN5eH55Rf60PBEYRfAncdYnDHxx5yIAvlHoyzZo
lvYof905cboO9jKWUU+K5df28En615nzATsH2P52lsfCSelHblLBIvrSZI0R8BTup8HhZthceRbL
AYPWLArcbzruxpmrvPNwZCwYetmyf65RZiCEKbwMPEbvpGyKwbI6fjUP3mOJWExGBCAvcOd3m+Wm
QWusy6AL5ZXGtX1/Wp+rD8nDnFxMDwptd3O01cef8YESfGIwjC9FINptr3Lm1U05CfZn4/udSO3m
o4VLm0VbgaiggSqjHb7BN302axy/uJib19iqNYmmgDuus++FlqWHdDFZMGVfav5BHebckIElWEp+
8ZB4nfMRKlBbp7xXy7T6BtPd9j5XPACuXoOA3vXcnFxTWod1eq3AXAR8cxmqDg/2Me8lWtVm20ms
fXdCSdM7DAbPp3tx28LVEJA7Fw6wMqiGMAm0LDeI8hckosuB63rqbcNlCk0sKYUjf5zh2trzVi76
6qzDbC9YbXfb6vydU0gdBQ2AalCDlodBtI6z0c41wAecE3A/h23y/+jfDI6huMPBtVy/dj8e58b7
/Bt5dQoFgQNF7gnFS2uhuLJ/U9qjkbkQ2F8OqnNf4CgqvxucaLLPtm+8BA3c9FAe1/BoaNnw2jBO
UAieRKyAX2JDo/+X+8tVvEbb9Hnsz7bmSnQi1M+yjGvUtbIH+S2vBReyBc7A5SAfucM34UvI/2oF
SxrJ9KPeu0mo/QWu/DOoLo+fAf8+K7mlFY2St4kZPwM3shqy+znpN3USLkbdOpD2A69N6w1qcB01
zZ0wgHA8wXLXDzABWcBDY3tplV47wUHiyvaRmBxsr0nA0IRf2BYOkSbGJ9e4vBP5oI3Q7B2EeMzR
1SmMJBlnv8mR1ImXLxsjk+iSnTNh0BMd+IPYBNUjmgCU+FVK3cOmbYHh9JBhsBq6HZNUWosUjzxt
HGJF7axx1la1E91UVpaJZWkHTJFyqhbwkU5/NFCdMJ7V9goznULUb/rBOPCv34R+i0+u4+XGru7A
G+7VQiP5KHYiggDRxdif2UXfWkpTC0jNwp9NZBp8RntmAM4gqg2fXPCWQyZ0WeYsY2ieWJaYtxta
4s0aBMYEbfajofZ/FTErnp0BHZiugCEy4O+MneldY1E2oAwVcDEhAULO321t8H50SViMStAYghid
aLYhiwjkg448SxxTTQKdyUMgzwnI0G/5k3f88NY0ESA4COLTTHxKHuGWrWqCCM5zn3OBEoCroU9o
A65bIMkn/GtaCXhF8nv/d766uPw/WS1TNGOO8BrgpIiWPYiL8LqI97qKJ+PQQZPUzAFXYja30VI6
uSkZdHt1JWyznHFvmHPjzxILGlZMphibnDpsG/9Gxl9mfHbLBgbwkVE83U6aztzKd8sN80U3qa61
JeYH7Mm2TxcZN8yAXyjF+yJtRXxV1uWPr41MV2+hANzu6W1LcPEtnxbtCuXtyEQ3Fl0VSmq9jAKl
coub1g/1SeEb384AT0HYWb5fYa+1gcoWD1jGLQGKh2DH3KaNijZGKsj8r44p63O6PwAgurtt2zB3
mhTfvRHqnXkYCOHZ7pe91bbncgvki5UEDg1xi/ffwYYF7Qp/ICkU53zs/VxhsB6d8hzRfBQS/Zmv
D0tcn9jSpxLICyGCGyW8QuPO0T5URQV6TIpKqUtyBvlybvOLJ3lcQN9LJLaGKp+41jdIU0NsabnJ
UoOvpB/qqOZ9Vcmj4yzJ0s0EQSFtGsKYpPnwz3ZIV3fIwIfyvCY6Pvs+74VPTri2/EMdsCaVik3u
HbQ5N4EE6xxIkXECoOgteX1qyeOiSlIBHuLQy/SHN7LRhEaUV+U+6usTiUG9RIVcQiMbuPFwxN4T
B2aKBnmTVZo/xXsgJ+vmX/6Dxy0SaGZIi2Urkj+P6B4tNsOxfkCPfGjjTwn48/kUm78UABMxWT3K
gvuDTqHuZtsmz+4wN/MuFIp4Y/nTV8ss1b/zWrnSge8UYXGlZt0yHVjTbaZYyJSQZ7vsBBXbNImC
lnAfrNqWgB3pCwEpShzYCuVjGOj59ro6R4/bEnBcypbPR9zNHGOAu/e2LIQL1/gAgHX+ftDek/EO
p73byY405gsXFaIYsdGQkMgO8Mqa0jK/pQDcM0az0NT9ZP4bi6I3sNM7+vCnGGInMiuBooDu+8JJ
CHhVCQRYdR/B5SF7W8IBsNNGITxFUgxzGL/WAugL0vBUepvXcCezBzCv8fcLwf3EKjI8r6RHrPvk
AOfnMyJ97CmIZL4x69fO5ICzzB7egnJv7+FHFrl9p4StuLXYMbBEaky+8oseLe6le/k2Ho4ohuTi
O42DUwGUS5fOmxWUvu0totPVZjC4lLxHHo+eZsRZRnRMqEtrVnW1bz1MAWwCe/B90+puT8dYLJNc
COIdvypPMHzan1VqBxchtR7exj+CTkLg7tZZAHU9hdnaEgjRQMzAC9VCAl+QhzGAnyj17t83iz5R
JY1udenja2Z9WshBJ6GYUR74dU04EaxjqDg0m/oz33nIaLFjAH411ynVRML7vPV8tq2CX2dHH6An
7olbI+mIXMT09UJ6vcOJqXG7Ln8sVxBYD67nOL6PPrNjBUDoFlvl4ehAmSUquwfrDrjztC4/xVWv
y0hvtuAlFVOZA4SgJHzA1K7jolhFZBc5eANZFmY30DT1OQ72TUrAnUqvLZSM9LKPwOFefjBbcT9Q
LwpfI3L6hE5B/rDskfK43jjGQLGY/gQayFTfbZGg2uKhJ7lxpeEWB5505GKfSispBGj+CHpG8B30
rRxb13lxai9d5OCCD6uc+VTh5JRk5hFVZlfYkNTXz0CXovhbZrxzWAncRM7yxpbR/o7+d3cP6iL5
MB8rhC0C56V4K4dGl3/NdQaLp5isj+tj6KRqAw9FWNYFreTw7KCBmXyNkRsHmODzxOXxpq6YJE71
XLDfRy9wUbw+g1VpP3mcBSeV8A0mx5TUzXIXx1yG6X9N6Ir+jzzwWxA3PFasI6+lQd6Mvs1YNbb/
T/mdrCW9yLGxDpcpsQENQsYO4p5vCDAv+JDQjQztfgQTpSWicVCVYBm+GOROfFNYy9f65jNfin0W
+SPXjeC9pktegecdWDIGIL7OuCEOPpAdStz0fL+vdgFOjdfVr+y/65+QO6mxdpnxsTrNiUlW22Ti
6VhPpeKXEt18hR8BpwYwMnd7PxtOeIxPqdFxXgk6uH0xbmcqnfQ07VgdiwGdcn2Q+YJD9gBjZo1l
RJhiX+9sx/okF1CLGxnLC3DWlPwYLZYLOgfeOc5Eqv+Y1+l2yNv5033xI0FUKL75NraUVce4gYG4
9+lpDVqzhDOifH4oZt4O1t6U/TR+yIqoNMbZBb4vv5/bfxeK8CzdxgKYnSDEgGFH5dXZ2qJNVWnP
t6atx7BdHFoQstCn3IM1Qzx5xZ52tqch01gkVN5SvP7BTr6HXBabooumd/WMZ7sV4EezoMxxYIq9
pbUMXoiDREqbfG5CsnbS64fli6UKTm3s5z3ivj2VZKMgicVhY3K3+NczeDK6TIoDSOCJXpd+f24M
UAGanpQdS7WH5a8R4aKKtfdLiS3kc32Pmkh5Tnl90VMzDqw4CiHs1q1bkXcXdxCah7EcU8mZmsd2
6Ou9FsQLIMJplrBAl+wyKGSgbJUX/wqZgPyOwKtDxpcgmQUga4SUUW3A7LeeFmh9/jUUik/w1fg5
Qe+aaRLCHdC5UQW5FgS1sumRjusk0XK6moMTSZsFQAxmmSO/wr+DBL3WhzW+ls//q5DVFIqQWG3w
B32eO5Ie2W8u6Eu9Yp1Z9Ql9+DbojehqDfGtcneN6B0s3cTjpb2bcFzhqTCcPuZXsLIUipFcgKOr
CbHcPqRjhLO3VRAzOTVyAWp9MA2+xcl38J3ofRrj/balgszy0yg0ywjIUeKJIITK62LfgrizYqAL
JAox/SkQNBMllO3SetlBXMDo/+r6u3e5r+bFDogl7eN4hc5PWfhzdzg9Yui7qD8guSa/PadVOFKc
cxrzP9EfdkIu6pP1hXW2qcsdwBTIkk2Nok5RoJ2FmEWLAKMHm/3NPkQQeWwwWr75UaHG/sDwjPv3
6AbAv5fmvPys17BDd9uDnuiMd8gechR8vG3pcXHTF1MhYHMa/fN9rXnqSg2hzzoDxjWXUo7BZtyg
3jbi06JCdIUQkfzaITVwPpBDRSeD8PchDIUfXU4iRyUlWogQjyvVPSsywEm5Tr10iRHeSberw2GX
0WPcovs5JnrXD7Jl15S3bnouNgc4ujw4aEkNzkh36cr/270tN+Gl4JFdc7v/JZtfyr4z63BtHwpZ
hVrNPdriEwMfGaWkjXLA4Z1q2P+rvFdmdJB4eKNxQSwe8A1NAoJZdA7wYTbWPE7zcenlXdwz5PNx
nmSTJ6kqtFmcWvcKFhnFsuOj3XgQym2Z8qpVB8FoA5ozh8neAaBi7leWCrN9k04K/v/T8QMhGRWi
zyiy7OntAF2S2SdLHPHChdLeZYZfs6xJsa5Yp0+Lh7mw8sQmkXNEW4steimAHZG4QDTXBHVm7E6n
Zg6bfX84mZBqM4YoTk+nZJvY0sl2tOTddepsSLOEfdjKFKgF5uRl58mzT3tQedogk/iygjIqerui
/nIUvVuKHbs/+UoLSLv9/T77JwRHSWOIcEeudE5AQ+LmQqIKTdfheaAMek2iRynJuA4rfRjb9QqO
J7ni0Hdt1dad5VoOql4W6EzZp9sTXIB1BWUbciNv1a5n4NEOcGrhgH0MLXeyxqb+jnCK9/cgH1Ua
3M7P0A8S/tHqhNVXXjvYknpwB5wrq9O3PYr+AuwVVYw5NmoxcucHyjDRmb43IGlh6IpRZeJYlJKm
jVxsZZctj1qzNvt77Kae+e5GIARhIL9LXzTzaxhaDfh56hEZ6gfMYlTmM60b4ICC2zrmCDGMxRfJ
RU5a/1KzgwenUIwLCU4rvfJYNwS3VpynsVij7Y2bzejLBP9i17veylTdesJu/N1xd7UkYZjildee
W+WuUYrXMygpTUtekKRsZKRwin5WdhRda4C+k7yVZmfifcl2Kyzc8Jq97LOeAEzZ4A5PBjE4rAI8
V9xWyoISTStX+LQPaMS0euFnD+F0z957yep/FjoP9XhAUk9WbA8dmYoEKoTIMwT9yOJUzxN7eQWf
JqxYaUG0ZuYDpG/jF2AniZKHc8+UFIi1eSEm1g5tFslANBstNANzRZkZ9Y4+XzUc4+NHCuNPCK2v
tf7/w4JDMCVd3K6Z2iyh+ioWWSGK+iYQrMsXt8yDjRCx64XjxAIvurh4PEuvlhb3MaykkAOkSGeI
GDgmI+Kz5zrjbibo29L807lJ6TnpSKvKqLeYZ5Gd488kOkq0itVugNOIiMYnBGpGqNWz5tPHG94x
eUPusIvIlKHeZkdibYpDOsRElC7f+DvsPosO1OEmPUena0SwvMr+DjRnOOGC3VnRxC2C8p/rjNQb
Cfh0Qh9LuhwxOdl2tbb1sU2K57bK5mcxDhWvaX8FZx+EfX78vfa+UJmii80R6DGKBk1lmEEvVqHw
AJ3kOOecMNh8lV1Zxb6vqLFiRBrUJYkAAn4L8Xo7bzosgvd2xu6A6WvgbxouHBJNUwn256H+ovw3
hYYWcNINYG5hBrD3VUxKzLILtpQL24br1Vmrdp74fwhW3aqwGNQOxODt2mPLeXib12Kk7boC2E7G
oP0bYc5HTqfWuCOj/jW4CslVPKmDIO5GHkdisOtUNQA7W9o5cy6v/hnETYldHn9g38sxYPAD7YId
Uz+EQD4VekPvZvS8oIpFm+zC/FYxt1fpJW/HKyb5I8DkRuCfkRAmxgIZPiT4c/HR15qX5uzhytRy
+vbD3t3qu6YJl8xVRQC/l61ngfgpKLBADQlMFGo1znNGmD++jun8TMZE0OzH3N0WSqeX+wlu3fik
UZHVTQym2XGt9ugKGwIBGcxMTwfI6WBSlg5+UqwCw3W8upF0bx+abUmYuOdtYk6bXc7DoqLc99yw
aXhlJEGnc25rTEn7G76xoWm0gRJVluAlQ7Ob1e2mVboBHtoccMbiHIK8idMMb7QLg4GTCDLMboWB
cn/0E5Vo99LywxDKX3VVBNXDbCRyLY8xe1LbM+VxpS0eYBAGdFSkSQCqXXnVWYC4TwAIV/Lepg+q
83zvJSAFpk1854U83A04sjZEJ5Be3au/nknkMFC3xNbraR4ABvf0h0zACZe84KkRFaXCUrd2GAFH
04IZHdKrj6xwOCgYPMbw3h6ZLSvNLvUiBPtwRJLYFv3qs0/0bSf7k2Sify3l/xfkuKtquACYxN7t
y13MDJrvlqQMbQdb7jpyqqUpFx1+Y2ObpRHVjlAAJTEZ227EettLtgtHundbAynd9HZijH/XviwE
VbwuRZ1g1ifS3PHVNYDYoPJ7eb8tBfNLponWjHNSWNtoJ2KYW0/AkVd6an2RjrpJQE1ymzMaK22I
kz4WEDDQjV+EGjZbcCurNJut+xacQ/qcWGBFjWPPR8YBjnMu0+nEEhRc1nJy0mzXvzWm/8FR3TjO
CKffvhq7g+MkX5y1GsdwG4sSa8AOIcxcJ68fEUUdo2rlZFfefj2IH1+fUfTgYeUxo71wHY2QrF1y
h/bkI++2qKAXOA0pdQQDNeAvxT0Vz+4UNypJkjSKhvpq2vR6ZhX3cMUA14755oq7tSE2L1OT/sC3
dTToOvuKyZIz7/Jnlo4qNtdI7Gq/yJ1Z7LlrZYxQnY998hxCPqrTpr3FnipATnimOvtQPHT7IeL3
FcIAHPMX/4a5+zSWlLGRRTF+j8wYVMnDhy9xb6wTEbrfL7pmiCwlMIS+suVSkHcF2NpLhbRg60qw
d0QDO1kd6WvPtoU3uFkjVrVETnhAJhdTYoGPjySFhCYaApTyU/xJny/dhn9ok49U0+rfQluSVe4Q
QT8nEStW/Bhd+zmOvsKDD1ORMA9m+aqLMEGbpIliV0hmAfKmoabDjn0OAhjUw+0aG89KZoMALbUp
XUQAuDcmQiK3qVtjl0fj0F7eTFiXbCwqTtOab6eEnEgDJfRsgWKc0/+AszEtD0P2P3p5cv8LdCZx
8D0/ZCzuBnB9fb0/vSNhtX6nKExEgnc4OXmgXo+op4R6bFrbB2MyYL80hi+EP6nne9Ar552PhTh2
VT1FZ6Rqw6auq9BHuz9ZeIpqZc4a1GcrnkFZTF1nXx5/1K1Ly0RYF2hfSiF5Zd+r2mh7ujrtrcVW
1hwDUNIqt/XShMP0CBABP58Hd6mhrQK/TOsbgoubm3zk1te/TNQLbh3YrwJu8rv9MvvPtmE8FiKH
UGTOL419z3rvyzesnfVXumExNMXyw/ePmy/oPrAuP6pDin13AgxwmbWmLD2BhOEv2vQnKU+2FHf6
A0dLw/dpuWesMLFUrSE139jh4PuJFCUK+gzXeKxdMO1Rx4SLohyW+dg2quuobWfmT/AZWM4y4u6n
di/UVmLXMCwDjJnQMiB72os8/NK4D7WZ2drQvlhbmRu1HqaKhIXz/mP+QlGq79B3fTCoWC+swtnz
U5L5LzCMNS5vr9GIbY/HytveGuR6ouclgElKgARJWKwtQiSyf7AdbXhEgfIiUCiKdf/b/sLXRFkm
i/Nat8s56nMbY6wWLocf3BOADWOy2cZRbchY5YSTgNPobW4lw02zDAgJ+plL7fwIOao9fudU6yx0
vTSBJ0Zx5z4CtRypHkJYBDF+0ilZ3JYq3PFZbq6EA97g0zSbKzVdjQegGMIBKgrJiSvvtIZjhcQd
C7d1S6pe6fct64H7WtWy8TpOY1ZPWwHPT/ydd4a/q9YsVEPwT2/ZQ7sKEXqSzyZWrzEyQKhOwwnp
UhJiKANmhg7V1WP28GT5qYhQiJzxPbHJsmsgT9XyMNO6XXfRs35CsiDUTI3HQl7eNi0LHpf4czhQ
c7k09WwIBBolq6qYvxu9GrgwCV2KEbkh8jLLJzMxA9goOa0eFKBdtU4RytFGOv3galcRi4d/SWHQ
PMiv6dTTTq0drS1P6Fp6Uwa8HUUo5OmnVNZckahzs3Byzy3cnlme3GSJR15mDdmc+eVAT2ayjJiv
lx1qcxfgyjgSf9RjWC6sserQgjG2TY1s83SQ+tVxGcbGXCkLIZXDSvf2MPtmyHYJ3IcjTmiscvOy
jBmcYmBCCO8L4pPNHnVeCMKHjoteTBEdRpDCebKEYx+Yt6nthL/qKLSyEFlTsCEyNGVg6KP2LQVH
O+ZYeHAp9DIHDuHN4ygkGW9172dz7dbqyo73wPLIh4tqs2n0jy0YFgYQ80Jz0ac1ETrvBfMZPmjq
/S4Pm8DGgsP4Ow7hR/jhqmzwVQ8PfRJeDKDN3Tt8Dp1HfqM1Qt1Zv00nSqWG8wvQN9YbyI7byZR9
pCF976qzcoyXj3aVe8Q0/SWeCh4aDMq5w1ByL57lsng2aYlCUVnA79VfHDCXeFEo/fBRGcTKvpiq
0ihUCW+4PdIYx9Y/NVT1AsWTc8uNHq2tFJHXSRKIRt/DJihrgnhiLcxx769fYVS02k9riMClc5f8
2/4orbqpKyRt7A3/5lB/fjJxfVxZQtha2qMSNvMDBkSJ7UGVc7LOPvhRi7noFJo7tdakeXQM4hA1
Bs2sHoP+BMevk5Clo/db5mOk6ZBEGqy2iBAGP+P6JLB4gWY6CFWwWvGRNNNIKjz1MFaUCfaqEWyp
exJJbwsat/b0YJ6MqfVZr9nHiRgkjWuc8VfKEv/+FvCY1eL2KV+FYBoVStc9dgbJ2gZkqRcx4r+B
4dAV2golNnHrDrUuRYflFEsNP4Lmv72+pIWnbJDcaRi8BtWrzi6oltnQ/kXeftcFHC18GbqTvPEB
C3ZoD/DUWgSYu1FCb5GjpItXsh/EOjCls0fUNnjaX9oEFmBh2pePWjAO/6TwlwfLGI1JFybwE6Bi
tRrhMLiMxLMDE44e4OYiqOxNssY0az2B0SKzK4mx9q7Ms+/jkYPYv2XRfo3CBtjT1bD0b4jGXGV1
e1F1BDVrmNIdBb1IeK6+T0VlUgmjsRclvNo/fIhsUwdEvivjes3fyqWh59JBXTfp4cpOL/vox2BP
xHndo/LB57bjnv/P107CM5AC9gJ2X/Abw/5gCPP0kLYSbXvCnxMSIi6tSygTVxW9yfw7fLB+uIeY
JNC76jtsP/Tj5+93wCqp3DCTt53PYGuH+qgZsR40b9NgL9N4N8dLALjUpz9kOgbuNbqapTKtwNkj
Id/egu5Z45VKnPK74wGO+t9Z5NeaCz4PJJeU63Vdy51kQ0ZrMUwyAFESpGzKFESJgRDrssBM19ZD
nvh+25zVXmzOYhC1753VLyGQV/Rs6LOGtWjzKnQUlTKQ0fiAXkg5aIJyFRoHloA724GNHtyJxB57
j+8FPJhGMVlKH0fBHTyIgKJUY+C7DvzWJOnZzb/6I+AYyYFV5Wj/3jNDAJvsmg6h2imji6RASgjG
/+RFl5/rvFCOzHLwAkEL4k8sksMsOGgnJ9PrkNrXB3bzSKnnWppWgkJgSkLqspcaG9eluFTrTqJk
5coKRv8D/RTcP32xXs83CQ3/9QC5BScHRd+NaPaWI+JN4195nUIdYG05YXbF9BsZwSqnZIZSe1YN
btSshAnWEpmzln1f73cGeElVajbiQ7YDTz+KwmklM+YzgV0ceXO/OprAB1dv5IEssp/0juWUsFa4
fn9Ftpq+nJI9qhm1RAxQV7OqSMrfyUAhFgjIw9PNxbtz3LvJb90d1tAzQAbdozDjLPDjlD037d4C
ZimRZb3XuZU9Jp862rWLrWXXubhIWYchxYJ/Q/CEKNRKMEvJZUg/AFX76XZnXr2JjO1BPPrjfsXB
tQ/mn7vu5hjW7LYX5RcF/He3exSHSSF1Eo/Qc6n6AtOexGnv42xHwCx7BE84rat3kJmju1seZJTu
+tpic64w+a7sgSzdccMpUEsA981/20Q6wDqNXGZGOT8DbBAt//l621EQ6Ae0KaD9gDJIqoDs28M7
Rdp5wbNSialJ3TG1fwVSukaelnE4S/YQCGbH3JtirUIuaKww0k+BhB1YPYeUjno9JNtky2GncPMH
EqlBj2aVXlWns2olHTU+wRzpEokj0oNTQZ8QDscrPrCTYpKeNCJP/byfCLJNAhHF/JsWBLCtJO6M
wWWpDMLkPTuXq9BzG+VvtflHaBxci2135593zt6X2i+CRVbYPH9bypwCRenVZC4TYf+OEWUlfn4A
Bz6N0WHmziIFu08DuXLVz8Lm9NA8aXwa6tugWYMJ3vmH1h1kdfRqMAGzzzRLa6xXWt7Vk9ZaqSWU
kmsQ89gl1bvKDqzv6Rqncja3/FmxOOPJcEeA4kSmyLZ8UFiDDc/apSgdpjIZR7G0qFUiIi0X4tst
TmBE9yL0Rbwx9WumO5YISse4q8QVjkD7DbfWUMd01An3A+6rjuQg75XReZ8WSfSOT1h/tKuaSf7o
8u1PObmMb81bYuceuGCV7M9oDmDrqF7sCci8oBXKcQbzjoAehpPvQQaiZU8Uv2Dya4vlz90D5plX
87ZqDPP9zounC97RB83AqzWEx7r8NdBN3r2NDAgFI0DYm8dbQn16Dfr0lFVnx3VT26dBuwRdx6P8
svaVVpTg7mfVcaWi3FaFzLSI4dT5Muf9Wx0g3HXw3QThJWe65XtGnSGP6sMW2s7OfZVwjWFLI77+
Op74HIEkffSqFR/W3Tn4p2suaS5/XNNoKsth8RxHe/66AXTIPXgp1n7GrYD+SvB42YALD6a76ice
YpopwFknrQmGSGDmeFDB9GAs5aJZqxbr3Br9JmjbWEFrWV6ytMnpauZBaqeFJYUgv6S6tdHrPOkw
afFvuDoe4sZdu9tMkf6Qy0AiWzkVeYIhLj1H0DPzRv2mYvqCa6d5Jq8B8puYLx6VizVolzLPhk+W
TA0qtBmTfHzRNLbID3hrYV7yik5QeECQssNTI24fktXNHYNfZDAhvFGsFg4UML9aUiI3n/FVqDxp
LPVNDa8rGdV3l634r5YwxiIxhVSeWn6JmcbQvMUrITQco9/IN0bMWStBSqbWB0LuizwlScGrb25U
J26jWfFjJR+K0ahtY8EkCDhkMC/Cb41iPLG+LkczcmUWZ6K3l4eUwkleDI65hWkkwlz9PKgK0FU0
8++AiFIOBxP+z3wEnzd5bml1F8PZQPMBoRQKDyxXkOdAHW/kkZDWvqJiqfftIH0jl4u2zAa7HP4y
8X8mhXG28BY6ooyF7Q5cPp9MV5RdSKRvxtoDnl2btTdA97AkGoL4p3TkJISDN5d4ff8g/c98PmY4
iBONXaMrLLL0O4ubqKSgdwWd0WrCs2QhuPxo8bj9Y73uy1pOCSVGB69HeN1LCb0d3i98cTcGAMoO
20wxWurJSKaQq5jA5gRnclJCBwEXY118m1I//BCLoBzhtXOKz1DbC6+9wZnk7B9itLT6vN76QUxJ
IOfQex+6EfpYTI5mIjiBO6+0eAM3EYixfGsxv1ZY++MuncIfqC+JwuD9PN5pd8EzJleEh2oDcGx0
ODIPLfMn7DYxneVP+SpNTwFH3XT468kN+RnrVVs6isIiaq4H6Uxqkd/kUvB1XOgipxOsn+qu855n
x+/875GvlDpuveihya1YX9rf8Pic8AGp3LALS4xxspVA6d9+YAW4bmJKgkM8qOu4QTqqP+aBVJcZ
8jAkS7LsXryauXlbfTzK3Di85jROhx+OlmNqrs8dljOm6RIerAiHEXk/Q59g89uuoattoIgPl434
FVq/4WtoftJxfohfBNvtN50QCa9/kiTaeg2b1QQjzbaVLzgwK3WDGTaAoevp4F4wdEoHs9B5CbKO
fIvALUryO8sWvH9d/H3uTtmcmqYN4Sfk7ciH0Fcox8cY/EeBThcyEaPC0g19bDzf3sN+VihGu8iW
MfS4opWYONbTp5x5Fm3L6Ddh5TDRTuCfkaCzB3oL4e9jyJeqG44Tc1YmIEq2TSLvxIrXTSvNCRp7
Da+sf6H5XxNj9Ud7SVXT34XGFyskhIBhh5TUNGAe8hqOFNmqzDMXHrSut8ghGCsbHzfiOa5SRWgE
yQ41uh9GiyIzyvgsliaFX8BtZnNTTb68zuY3j+AQaLzXzhdhpZf3dYUcA/LJ8AUdmWBz2KEPm9me
iDfvvhYupEnLOxWGhGi3y3GtIIKsGG7M31xUoAEi88g2Jlpo2xnn9b7iee368Wa8i7nqga95K1UC
+9AjhPfidvgBN9jgVwxXMM3ziO+GubbHG9g9lz0/uw/+ts//9jQwSD6zHxhKGrY5e7u3uZrSuYwV
sd1hQDXCuSqmWurrD2oqGHpE+JGuG829WUgvHLJAs/Pv+HhwkwQ52SgVCpUbdQ8zz6o8Y+EK2X+4
2mrXJXpcz2EI9BxawG8epAPaYh2/2iHEnq1fHkx1ty4ytC6iPC3MLx+Z/5N+I+vZLQkpdZWjjPIB
24prBtpll76glntVVdC1fHl9C0j+72AkPEmKHQQPto4n0rU+yKSlfL7sMpxH3ljoAsamZy7KAZH2
0zhgMNMT9eADmPVT+bo77WCW/QmGW1zY0iLk/lZb0/gvrodmvGkKdAiHKXjLtaxp//tY+iI4wSsq
ut8Bo2HZDORmaeZTToXdi6snZHBIrFAeX90kAvi8D39BiAvd1KKfEvsSS19jmbprIop9mNf1+h16
GrVje++ZcJKQ66V7cH1Bktp3kHYobVpqjarfRK1XAG38Va+cniiRLBhdhErCAYrCW/Mw0GFF6cbk
1OoMFkZwTbIunNAYubkjy7k9tXF6yyHx7d06g4fSouGKZyUU81qCq8bYhVBrjFv9q8eIVfK6J1bl
MLsW7xshsOFPjrqlvp1bxMGVLAGQeaYMCOobjc6kEuoF2Gd4ILc0AbgYPQXzLJTKLnpiCKcDOD/6
wHvvgEzaAcjWIsEhPG5QKiwKkAnVUprsIYeMKFfsZsshscOwmPzYwPRENaK8EF+O/cJS1B+zoD0y
O34XSY+R+gafV7lo4k3et2LzmgHEU5VwwLbHFjzA168yybYpn0ccNxbGN3SjSW1ATOQMoPghsAEE
CN9Iv/gy9ZWPccfi83NuVEnJsvOXwgmpyeYALEVJUdpVflCUErSf3I9cgcn0muWbC9tSgNJt6tzN
BHanahzy5qNT/PzwbUIembrQmOLQeH8PSrorDGWit/eFKNyooVlsPBo3GjnPLEXVtA9WCIWw7iI6
Ku8noelk9ALpQ5wMYyrlN336Wozr1yudxynJMj2SxA850wMjyW8ONwLKXAhI2I+DK7G8B2LsadIJ
exyn0LnDPO/enq54EbccEXXqjZCzM6r5Xek9RZl6OSeBYAPvTGiaWAh5cpSCJEIhTZ0sovD4Fizb
fTFBaaSzsoyfzcz/wasMjz6aUQRAWpRw41W3qkYutosl1iGtGaWLmkPF3rDibfcA7avsnvxfxwpY
KDx37xEhyTktSjy38VB3+E1YWebmvz6Dv0HauGBNp3/UocdYOM13L2mAIRm5pkGyr9+acSg9pssy
0+bm7Q+ZOUY9v+uA6XbwScM0DUmXf3oJ8XdLTfQL0wqxXaC/MaecOZPRk+BM6Q0EPod/6TTbmc6L
uj7tW1tK2eCfUILAWWXWFu9x9DWGZ5g+AQXrHPNiSWUBETVlALqJczupg6m5nVFFrS8+tqUhr6g3
yOvq0iYv0UIVRl0/syjDPWp48koZzETKrFHT59gtGO38wwXQwu6O3/+f2mdmZZt75Z/Qt2oM/CpP
f6C/mwwyeHLNhGn3MicF42toHnmF2AtLtY92nxE9XUl4ujdRYNIPZ/fS5dU3aUjtWDcbW7VvvYBw
/s59mJBrcja9cNmvtQWKeu0YIlcIF9sDln3ZM9dDV+zdo5E9Vk7vsLViYdnvdd5mImMWg2zT7+ht
fxvNR4yH7jwx14mj+4Llu5SHzNCqxHLE7EujCdbmmfMyZWntA7XWKAzaqjrJXm+EteKThFSM+KGn
IHccgGhdBlA+25k8Kq4nyXN6e4mmISCGvvaGs4kg63V+BhdOFmE8GUiIxrNRuzwsbssr+apDole5
SGLBLi6zHhOy189d48FNPZKRnsXtEvZ+nSEh17qLoy3UiKPXxvmKGGSskHhoTPH/rC35vGfMMSvQ
R7jLStXE/Gvaw2OB83jAxmGnyxjEV4rxhR24xpHJlCU5TUF0gS1MtvYWvtZPvPpxumCgO2Sl4Pmo
trv21TeFP7Eg6PbxljmSVwSQ8lSxIAYHbk5LmZ6AetUA4ZpE9rSk/Amghqi646aVRIVm4lg81niN
HQ1UJPZwZc882A/3be12xZwcrCs6LEHbfiFmlVycFTNNbBalVCmOpNTDMgg4XSExPfjgG2x8lB4m
v4iCzHuPUaHduaeHtumJQ1WxIrfqBE0bYTcjppIj+kvjzu5+ePij6B8ZSWACOCH+OjPxU3e/Bq9U
PhC8D3l81egTqcg6IxVyNk2HukVSy8R5fLNeJD+BfM/KqinQE4LPzk2mqoxiEnaM1wxNwoCLUQJ4
hRs9UxKOy+2rQLVokRu0auwhwoUrmK3mrM2I0+ReNk5eKdKQSfBjE6uP/oUCuZbYlMQjvJzOrxlA
Y8VAuJsZ9dZyVyy6UqaluypC/Ah3DJKizzafQB7j0L7dT/FDQM/IxuWvpywy963fGCF7yBo0I5v8
3j4QeRVN2Rcfl8tdoAeMl+UA83Df5k9ccVSHWEg07HmN+kdYprNuJGOgK21Zb0DtXeUKYPcuip5X
wzeZS70aTO2mjZClMq/JruSN/97kYg+8zXss6HQmY1vzKVYPqeBRXOQ37199Fn81/P5hEBpuWyqE
Bt3fsfYVD2s6Bh/0OPzCm/1i1AIdSNjNlAN0K04gSengA/bWEfQT7KddMPLrdgvkUwhLZVJgouYg
PvzdbcA4xcNRRyR5qzJQhZbzxEiF5VP/HeknOM8k/pyzsGmMC/aflg1DyEzCRfWnwnM2JYp1AXGu
mwyr8RQ6RqOpsE0bGLaAaK3Zf9tngpe3UiuMBkBCiYSnMrYl1GGLGCr6Q+hFEpLCYNF5iXy/MpzA
3S2OYqqpSG8PbCWZ/ZJ5Wgbmr9Eh/fDelNzeE2Dmfyjuy7oBkax0w85PTasEcNiGWolNUV2AGC/7
xiDCzZHY91O6kU9sVGIco3d4K6BcuvPxgnne7CHqIoCyiAX29XdRUaqGoDhpd7GbSH70FMcaROkd
tLx+7be6BOPSaSpiybnoscDyHiEoUaeRY8Ykm5WMFYV1XZZVbGDJ9MA8Pshh1TVqPRqvSTXE4fp5
RWJ2KVdAtDbOQW0OSe1gBWsIiNEoFrOebnUyq/VkQiOOSiA2dElai7WRlRrpIB81gnG7gI8Qo+A+
BDigF6/KuMgtdFWHjVSJIdOgfFo1Eog+susPa2BFWl4RP3MmYcPmxRIYWv/wLrLphubcTKVKbRVm
KNELe0FhfCRj4F4rOHO4GVP4jcUZl7J5qMGPfuRkCckakp8m79NadNzu/gnHSgxFSe/QnTqFtDZ3
TDZlBjb90MK+m8tC4hyNUG1M+1mtDYuBom2u0R7BRa6RD8Ksyv6OC61IyGdAmVbLKNer78rcSLaX
onmK5l0WL2BZdvzZ1sKZAkqCLDn1QwqNSmwJdL1Lum3FHJKQldxlTMIUhzkf7XkPfowaABvDGWuC
WUwroxnrQOi16i0brEUS4Yh8+yUydwPy3GSIh538wMWqGkd14t6lrAw2SL0KHWEAC2VhdLUV3Vp+
Xc/8IaO5rjGQ+/IsDNXQ1B7IRYm3UU1aN/cKm6lIyBubgetqFsds+zYigaUaxtE1Bj7PSTebAC94
nyeOY+hRF3hvmEtLqCRJCu3VH/8CWsYiu40UP/kerIVio5tDond2Xeo4cD/ZsSWUfZWC0gn2T8Lp
OFmkAY6HB9W/sfZHkxBHCYXvHaOVU0H7a41WnII4tZ6LhNegdmPxA7UGQH7JlPp19IWQMRAQPT7A
TEjkTherPvpjQO1Ty4ytQ1XtrlqhIyvTdldG96anhzm70W2Qe3xclNsW7HqcoZlBmiUghaRY2jOh
RvWNrrPycFkU+3dKJRsQxYbleJrzXm/saUW+KK6vJhmy673K7I3ko5qM+kTR09GoPk1Wdaz963tS
THHvm0jLsK7cgFIg5sCiMMdVyjDXIrROYXCLT/a8Kq7ouXOG3pEKCBXM/fqOQHpeBwLwjj/na4Y+
DT7SvHMPSRHY68xknnSZjZhO6X6L9D/Lw50XymwsKmGvKpg8hwMhwH1ovN8DVWmUfVcLY8RV5fPu
cvYrJ8G9XNy2d7u95sznubRil751Cp9pDSwVZ8JW/oOGxA4zkJB8iQ8eL6h5uwbhvB4u4auZ4NJX
1CPX1Ta1AtTIKhZUKloT5YjwKsNU2svZKlolI1K/g9yI5Azjfq6jUKz0VZ1rzK1rFtcRU95UXR13
bSVs0QDQtTkcwb2U6bmVrQDindiNJCJSVB01lkn7uVxnbFkwlucFZ4gJDKzhpKc4rmtfQ5tvLK87
c/pXijgEDoDb+V8jWAx3hvnFNXAL2PrMqiImcKRU9aEs8NvMzaaFdIESPU43ZPYLhmgibKNHTyRP
dw9BUv07GidQsWY5Jfz9BR1zlrdPdOyii97Z3U50q41ZCQzQBUZLMbSp4T2pzluN37YRGkXuIgvk
CdHSYUR1w6YAF9NpD2V6WFskVZw2U3TBMYZPPJo+lOZKXbtBFYiSuxEXmV/O1JreTfwY39qV8d5+
zG+SLmAcj/tw9eQS7fpcdQUKwtpvUS4yO56tsNObxnq/T99zU0ew04gN7cfTr8cAzYwAmZTcQyB9
Wp/J1Fa5BzKejIPZLdrtvjofqW7QOEX88IeSEJTabmLMksBHo9CY23hvoI4670G+PdVMc61TV7mu
t2+qfCoOrbFiqg7G/jwFGIB5Sx2pUTUqfa2UpJ/fJ6lnDzoY/+TboF32ovWfEHC31GoJL1EqmW+5
aWMq41HFe7vQq/sUvx26qPvSPXxGUgJbi0vaVN2axpvm+nz010BhG7dDQKIL/22Nis8rqb0qcBv8
VgVImfuY2RDDrQHvF8k3Wshklu472cSq8AF16izb0g+6dX8G/A/tl9pdehzkkF2WJrJJNzFMwUSy
Z6gf5jS+r4AW4q/jFvjRK30zyYwIWahHru0vC+VfdsPgmUw6CybX/uwcCkqfbSPqC34dmKHD6lpK
SsyFZSG1z5x6/J4QyWbB6GO9GrTykNXnI4LX50vbdR465MAYMgAc0PW+s1wd7KCMt6VYaIcQwlNB
Nh/oSXczkU75rcP0Ng6UyaS6dD+kv1IrX/4ym5lgO0Mq90fn8RMaIMHrh02KTOPin/UqcV/BLwb7
SGbJTEicfVwda/665scUTP+PomIgN4XDksEmd1lJ7QPPKRauOib4MPQJ2ADZcaCfbT3rfMYDqLuV
YuLS1AaWoMimrbe1t+SSfyjzlBnbD0xSadQ0HDe8Gy3yQ5iamTurznixXKXH+gOGX1kqVUOM6TIV
89feDfSSx0qfujK6lFBwmooJHDpdlhnr61u5N9nROjNI7Vj+zwhsQ+LYW133wuAYEUxfC21OY8E3
pEOJYeX3YpTIsnsZ/Sn0Ow9q9dIsdvL4W96BleBwE3G0p3WLyGYjgBRdV19LWYARQQQRkYxPOyBo
NcTlh5MOzHqcw0cgKpTXur5F3q5Tx1/SwIhwNTWoMOIv+XFjsovcGwSkfZTRHsb0STi2fOk5Pkpa
UdgDn061fUWEG5rTPv2Pi/IHzPXVGcGEHXSQaiJK4lhk1RNYfoLv7gSRPiaXXPeZo44PWZSseUjk
4pJTAUaZtvC8hR7/PchbsIG/8jZV/7bz6JkQ7Q6yy31lrsHXOhNFino9tLnleBZJjPERTW8M/Myh
DC/UlCjPwoWe/VdE0rizjYYVkEswn5CFXuvIzSnuhAD+yngs0e0NUK1lh2Cu8CS5rNO7E0J1JNZq
gnnS4OheJv36ODWV/H1PP0LJM4/x3BWdTNpewMjPAz93n+XoW02ZsTz+foYV8ur7ZQgOwAkNgMmn
wXv9CQvFIkyOTEDdeUMQw0UfxhWz+xBs4m2ffD6p2XARKB7E+osVd/WsQgXhYxOm8cEqn2z87tGk
LZ2X4rZPFtq9oXX7FV1wQwmnc0znfOzef9GA3xuuSebp5O3rmHho9+mfj5JNyKXlQBizcYAn2SQE
bPyWokHR5vlkdQMwmP1kWAYlf5qokDnir2lPWNIVu3sUSYqNNaqlGULrCau2/Eec55l5n1GwF3bf
Yb9aCEOWA5DRtLdqFNgdRctMIcFHxyOitXraVs8Bl9Xe4j+rlW/sakBPV90oQ8cVf0o35nLQF9kN
66Tuzrtcfu697MVteMVKcBas3ZTYte9ua8ryzbZ0w3sIMZ8IHjpjfVIZtidHFNX1tJhohcAcCRdj
vwF+zjD/6dgo55cZoNtoPxjMhrZ6+T83ArBK/UYPyX+Y+hTIrF1B80T2x63aeP7Rj5ENp7nDono1
Bf88Ly5cPgWuT6aR3bSsvS2VlB0Ay4Du7iHl3gB7PVSRfuwOPIsZo+P1K24UmyZdVgq6Mtad1RnG
EUUySbapAZJpfYzHdk9NJ8dU9fbdIjeU+JVM2totfpWMBY4zjfqLomOIC9XInObLBkoQ5W7qfpwo
W2U3/h2hnlK3COtSch+mH0VdsIfA80WkSdKFtXebZcqnxGucgNWIMu97Zq5tr1MmNomtLTOekkfr
pcyIyeygDJJ+RUwfV4gk7NNObJj84CGqasd5c0AGoJytttLQQRYj97vFyvQ3750uuNu6LultdMQ4
tl4WHtLsnysf7jyTfjuCmUGHOB3M57yGei/8C3eHMZaGabC+/vCMl1pJ9+pXW66iNk3qLiya3Gss
qH8dtw2wIOYRRZNAuD5p31gwV84i55q6RCXZmBOjwqtTFIEXn/w/SCChROaaCRVYjfBkqZ6JwS2U
xma72dRL1h7rF1hufkCF3EkdLALj4ByrYlQmM9c0tZCUHoVlrjGKg/n+TOmBfbyhS68naUvDehz8
rwnMDGSNG/pH2Gi4FXyBoFgz1A4rXInu5oG7jtBtBKZkKvMAtUC5MhM2afLKuZ8umxNI1CxYSbfd
MAM1uLqs6LSmWV4ENx/WbjkfZQJl96/ufYJ13E6aPgmn4oZ16VYl8HL3JU5+486nypD5ns0yzsEm
9T1FQUuj9+J8akJDHA8Ts/rhcpnxceb2OZ+TFq4UEV1UkWUIm+GCP0cFzf8A4ub5I+CYA6jxV+Ks
IU1UnCearq0xZAK6SWhiBs/ltjUX/Ac/oQ497t73oafmMieb9fWI3O6cHX1+nZpKRwQUtG1e2VKz
oKhcYgyYeGn7TzvD8KuE8bLjgaj7tyBM/Sd2U9dRtfUiov5q6qvLGnw8YJuvgfbqMKJZXlWVJBIB
7GJRtflfQs1Nr2tVEAylU0QnXKYubwxW+sjGg9/j8NOrDU6Uc5x4r3ZSuy21ts90PrxDS6Ug87C4
9WmfEs81lLMNAXXrYgbpA4ZoWVusEOrYzZNT1vAOICJtxOuRc5Qcn40jpezenTtAb9PvBtu3SkU4
MuAKi9GEjEDvbuhoQUp4QYlyJ6PxmuqKrnqeBm7gGHl6P5k3b24AH4rje9zGBeKRWawIiC40W+vQ
lDuiB4PgEzAKCj608jfcKq43IIcdB98ZpObTm7EVCy8FljuJal/U0R/pE0IPwHQJQrDZ8cTRsLRb
87RLMw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 95536)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztB/h+4PvAs/N0XI0cN9OT8nV3gs0Dpd/RXDA4Vc3dmwziA
NwElhjRY3VJxDTskfz+mxWNFaf1+mPePrYVqlwPTMBAxpvGimC8dYYQqLJKeeN1ZgTT7hwUkM2z1
Qy84CcCZcArvoNTfBy0dkWCCscLO7FYjYdrltlJMSy8CDdjskSxeftCs1jkCE/tStmrqLGxjbT6f
C92mpUd5YCmVlDJSoyG1Rmk3H90KWuHUMBc4d/nTIqIeHq74s/5YZbg6Itq+omXbAlchsha/ae76
9FWmmOPV5pGgbO9pUb/MAoiGnE0LV3UxmCzxLGMR5z068+xQRaJogr8gIRx4YzXucEDuMm6kq+U/
DJ8q3+UroFofr/QazQtIkbprz4hnKB1pQ9WCRHlWqYPmrTOztTQ4ZG+pAcx0IYfnFhwKTspFW+7y
GVx0kYGoMrgq7RbxX18WgYUZLMUFfRe6xSzxKiK5kNCdSzOH1JhyEU9M4B2sCcF5xcT7K2tFVZhx
cOoGlhAsPEMuJPF65qYCcRfu6UC7PJuefitD/S7Rr62kMcVw6pREvkYzRs+qsbgNnfPabgzwOYLp
olR7zI8hlqAGIZzAnxQDewB8HIRF0Cgw+b9popHU1CVbEfrPyAP2H9rTagex/AtB726oU3NS/Hto
hL3uC69KGFYAENJTVq04Ff518xRZvbDhZk4t7/Zpna6SOSIzrODGUJSP0FvZZ09QlakBg3Wo50tY
pgmp4DoT7CrqwvHOwtpgiLSWvTFKDLrISVTMjwWznwzIhQ773VhYwUgBwfVumnYIA8G6jaBfBGLn
337ecvtYSoD2WCjY57N+HiWBgdUQDQ3NSmVXDdKaQQjU+G8lATwv+bAb0d2har2upRJoeMobJ656
sfolUjfmew0LyjHzcPgiiMXxmQ//k5PhQRSAt8ggHr1+QYtC5Fh8GgB8scvBnTUM1XAO6R+HNs1L
U27gBJbGILSvUpTBZUXNkyoi8+s03L5a+vlwiEGgNBCUxq83tbJM454XJo07BkuS08KsFVnKwFol
BUxHZ12vFrTlJEeYdgyh64SsThJH99ZA6uEJZTSV37DhOLcIz86Z/+PfhZiByqnY0gn+wYCvOaR9
ocdEJsAWit/14k2h20xNDsh7vHErwyFqka7Ply4vS69D1gzEs/cwndFSR1Rm4eG7Zx13Pb2eR91A
vsj2o/4d7k6a8tH+bI8oDZQ/Qik/iGzOxZd3OZ9GvU8W+nKFx374cVoWAVRDAULUwyeFSZ8E+i4q
dROg4VnjRV1scMxi2bcOCuRJbX6vzKu9ao2v6me0KWbJrYk6Pb9VqAXmSAuxX1soQOyX8RLsDiWu
87+V9QkKz3gnZoSnwvxHt1paDTyWjfL4QMWA7yN1HbAvNPVY1XzuiTaKKEsyf9tvN3B/JY124zWT
CwibACdVqWqVFnC6vA4TidGx3yPOC9UhqDqcnqK5yfS7XC/KBwTP61QDQmo+8oWydyiuC+/NKVvt
xxNgeNW5WZL+UPd4qQ4ztuHmm9pfbJYKiuOJ4PkE6fuWkYPIhlX5QNKRqmLlF3jI6g6q2jl/S9KF
osulJvpp9IreJsYUeJoAOUYKglzMoa4rbTolwNg1kaiUPo7l5mXLcK0SujbMFWWGBRaLCfleNqCt
zawyhYjxey/Hi6IAQNbpyV42kQw66RXAvkbnjvc1Q/4UJ5rUo3Y+BfUc/d6QtoQ/MM2DnzZSelhz
wuszJzcVPod7VaEeVJQoYhSX/X+K3VQKZs2qHjRAh3XGV9YuAF3++sWBmfFfgurXmByZIYDa8kG1
7ZqIxa03vBFzHPJOv6aVvwWhnLmhSlVPCIHJxHiCGClZqCwm4y91AzIrXc9bPQNFscMLSg18PeG+
DaO3k99xUA9pn0STbk95TsxkbAAjVNbWBxRf9UedMz2Sj3o8XoBTOQYO2J+U066n+tTbHFYav1rR
9+sxamPEgAx/m5VI7mTLxdi0W2dgRRA4XDWHFWifRPN1KzIxNPHcTykgw/Lm//RZxB8MPUoBtMTv
ZLGrbVtckg65yrTYytUXEVL0eEGX99q4F5ZD7HmggQj/TehQOqyJaeGRkF0iyLX3+6bJxTqZWTkM
E9InS3J5wzbPVE3Pnz95yL45bs7pjKcK5Wq97wYr2xOxkApeasVKwvVSnGdxZ3dD8J71KiH7xG4j
IiU8QzbswZSUR0PukpVOPr7GcqrqOww/EAwXmesEJh0iEamU/ApOkbw8VZz0DcNew0BtRSv4oJn0
YVzugB/ed+9BIWsevE4e4JWi9vIXmUBT/uxNTF4cIDVP8RoxUJyU49US+VYMX+h6zYO0wxW/e/3q
GGFfRTxrDEX4+kwKXlfTe0Ryfled6Hfe25WkbytJZsJO11a+oiZrrrxLilzx9YraiqOSOJ0leUdK
6f6LbYP28aPSZxITy7N37ClpKNEZAsfvjXjI+fU6WItoDfHlnRgUP8kk6pzNyr2cSv4Mlg8S7zvo
ctupzXJVB+2WWab3RwqY3O4WwctcKkE7Mu9IPJjczuTATT/gFi6qOIUy0IeuDBMu7yfxvapNVXUw
x/XHP7kpFa5xaFPZLGgEyZwXZaOFNJ8gpmEjnHVUV8Nhrix4J7xLYfZ6r0+AiYhRCMMbuV46k6ew
DJLx1p3eKNSDagcWjIFx0oFXKM1MYJkymZpAFr+eTGw2up4fXuKo/DLd7vUiZYlt18Xw78+btiEv
VZCl5PS6ecifRQUmuW7wUQLJ5xxXco2P9v96725mgey2TRdWYXLdZQ1V8zsnwpZhINsLIMM1wT2E
Z/4Jlan/b4Zsw+9yMPAEMlN26qzCpzctSH/z5OrlpY49tjCWSpkqPM1l1BpbaAbi5nfYEoXMFOeT
3jTzFbWQ2tmzc3FPkORk9SqZMGl0agAeyQagVZsLeL8FxdQFK3Y5MgwzIOVV9N4/ouRr9BMhJylB
pE47x6S6ncVe3PPCxE1R3CYSUJJWb14e6OnlbSfrR1jTCppWEFUstCgOAU8m+D5GCqWe8zdILdlj
YVMbKliRzjsBZYMiXuBCjZYpJ/hu4pdE+56Km5r72/sGlwpLh0Sp3qFx3/QY60or8+nqNxjRVqk6
9Pu3EvIRyKCuk1fExvo9V5Zs62RrE6CxOL0NpxrYwn7PSChgdL6XSH+DfuTLAaDxXlkaM7r3Sr5k
6FbBdl0Bn4I7rwYV1cA5kPU8rGxOt1WJao5O9kG/TbxPqNPdrG3ZlEwSzi7J4QWmqCjzjzewXt9X
zmletWZ+HZMYVcLf7BB0zap0EO5N0XBbpxu+e+h+OGrXmFH0vlVv6jXXgJVEZhVw/dV72W+J4QvQ
7N5/Y6Hr5kpPZZ01uoNwTFORiT/PwJLbPj2fBb5Gupszp4mlgz5O1srWhwUzJ4ykKwhtQ5tk3ftx
EncTUon2WC0cUTNxeAxJTSs9wFPwNskezNjJ0tnXdwNiJI8kUrRZ9oszqKoasW8PcDueaSwjb2PD
JavrQhmgEOCBAgCnkPTno9NGlcek7DcPaq6uhwb50gYY2l2UYPMAcfrREJFdP8i3XffmUArvDNEA
hAnZbc677LlBoxG39d509+AoCHpo8BYl1DjMsP2+nJqaY56Crq3mip+KpqU20a6GnkZtXvPh6DVO
YUd+d0dSZUBv5Jaf67F96NUK/ZHgjMitGyfJzi1QzZ58EBcqYFCtNnceVpAtoN4bL9dhrzCh0nHg
MIUuDgdLdZg56MsdvfuRWLF8b/1Vh+j0J0VBvAUlBNvU1cM2zvUBkKhgPplG/6+J4+BgY6F3zNs2
E8aTB3D8gLnt4PtbmDbg5tbe4C+2DVb86cTrTGw299kZM+ygqVuiJVLzkM3HoqyCTYi+CnYwTPK/
y/XPY2wobFm0hVk+oUY6bPKxJnrs78fSpKYCsvBkIpmD10jW/Nm01hhpmD0uM3axfPe/99ANehUH
7fpJUTnGpOTayowtnZOrndV6huw2x86n43VyZuL+FXzIcUPYKGIC33W3zZ5/zbGT9xlK1SpYxlnH
/ppFj9iNqzCviDzyau+llMtjcfT6n2bb4gi2xhl9FcFCC/+KvGdaUJbalCRsmC2nUFgVEASgt4y+
q992c+slBpmDw0taTdwawRL5BBzSYHPcW+59Vk5z3x6WPcpKOwhK9wp+yXxcID2zXmFeLpldmL0I
Y4vWB0IFu1Uo65b3V6dmSVgMHCaGvZQ6MJvS80iCf2/oDacpLNOZkqa3DFC4XV0NkQD2EHqS1Bd7
Noj7ZW4mBzeMessx5D/91heXx/RqOy7/pl+B0XfW5qN+QxiwZWFDjCF/5T8+qXxlUdetQuYt43Qt
AdGhtGnd35GYO2bFGES0k7Da0FhfXhFYvkTTKxxDOSQe+uo9iYZmrRVQdW8iYJbqjDWytxfXX0Kx
3y9tB1FTg4/oSo1meuQSvqFourhD62tW0W8CfImuVnMpmgx803NJ/ftSoVsfVaWsKjyLWxWfRl+r
/c9DfsPalq2CZJWdnxy7Co4PtLr1oeDoO6Fh9j7ij5BvsJqhp2dD2Q1Pp4jdcY7GRfx/s6qpYfjF
Qe+EpssNScsqF1DpODQxSWFlVnlkK+s/JobFp+IjSWFUKJ93ppkLcDIzymZQ1YKHLaJLD99JgfYX
RLXBjcqlicOhUntYoWbOq62SvBwrM3+r2JSKS1zfoCW7diS5rKJDairlH6b07Df6sARnHgdtyvvs
wzoA8/6IMp5M/54p1AUnVhHKh8oE9i6raHwMjr4vLijAGWPMOcBYj2eRL3nf8yEzeQu8XrFwSdnp
9soB6+nAGNVBfaYMJRgoINTHd/t80sdsnt0dnc7OfHM1iNWo/XxkeQLX1Z1xYKIz2XxkTQbfjTUE
xV+7BFWCJoboXsmxldrKomYpXCq6iDGhc4m3/x5J7mxNJkFWobhHchcGgjsed5wcsPCJtD3o/Qkf
mPnoh+6FPdiK/pHCChdbGItAyYAMzuGs9moowM0jahLcRGlgQSQbRtUc17x3Jt/JPcj59ROJM9iQ
aToEB1fFa5ALLIMO990eT5C8x/f0txA4cFc+gSDKCpOxA8DgX+Cn1tSto/VVhjpNE3vhpRdWgKDT
QCBO32bUWpGpNSZ2mALB79qTAf1gtX4oS4PW/yqjNkA7vJZ5W1Ep7LbaHT5Kd6K1KvFZ7K4zsCnD
bZB1asu0sCnXOGy4tGDNDu87/W9YKynMVtEDan1nNPZh2MnYo1+0HGnKETiQCPsk9SD0uhlPfGET
GzUd30zy2VdFsYvHIZyc/oc5ShZvVko9KdUkQ2wbUIH1VCvkk01EaWm7JrAVbpno3YzlDMAxcTFY
4iPcZJm/Q6fBXllaUXtqMfKn/cLnJTu8UPqveOFrYWbW++8K15jKnYwmwBFiM8u7V28cWF3vGiPX
JpR1mIcHPRnp7ywMrNWwxxz+LOcaLd0BDeaKUHmmd1mcr9QXopzJ9u0Is+EG6+Y+XqaElZzev470
SbvcF+pk1F9KhDjfJ09zIAdaAa18yWpo2n920VijmiK2Rntt/OXM3MA1/RLDKQWGd1E1akKmHZCQ
2f4+jnSPliZZl/6HNYXqLkaKU3oDEnHZEpIUZDWxPr4ABMHG4vDQHEM+4TRgbvC4eeIX9WdFj3V7
9JQ4FI/fTQtLGMHL3JO/PbRYkcJaCbLayzHV0XRRyrf9H1f293w6M6ssFbExIOMRmgFGwJDsURJb
FMvIjbQhgOCeKxQLnZ0+NHGpU2NmPTnPchyDzCA1H1/b+ZYRr7+gyTXbpvU7eC7ZMZJ2XRpVL012
oAMm+Ap+Oid5SwtFA7qpEsaHLlR/Wex9JmnUFKAj4Do2xCvHIm7+BXkOzQjzXNWYxFGZrU+xtA8B
cCpO4uRc56S2eDWb0JoXv0SKypg/JR99YVnETpC9ZFbb0odtnyYL9Lt+MB3YtqHFsamqAvpmUSJo
gpOupM24T7ED4SU7H5kcB4v3jLQ49hZEOTgafERRw3hazIZktU6bZqJHU8WeC4qMBJZ3OJ0S5wiJ
4sT1FewY4C+E8itTd80OUhYMa/5nUbBozYxNnBheUDfF1L/kfSUnXQstIpO9BTGF30LOPsxEoHrS
TKbn8sSq7YWKdUgNBFNFr7aBhrCkymIvB9YHF5ZDGvJ0zBLAeK5vC59vIKbjx3sO7YVubeSKs6Pv
K53T+7qkHuPULU8r6TksEIfIQwPf0P5WFf9LGqAxv+w5THHUMpAxc978FW0xJ+ATe7ey+rwWmvXi
EepaB1EwshLp45w2tYNzZoNEWKapASif/ojS2VCO8kuw1rLY1obQ9HVA6xPadqu48FBPHQ+74tuK
wOY37WuuyKxSp9ipLLYPtUem0F4B9H5QIGQoY056nz1XffujAGuqtlHOu/VU/egDi7ksi3T848K6
afVhRJVHwyROsV5zaIQgO7j7rOOJxjXj0AL7J6eTOyZQSfpg+lyY/5JL3OA3n67CyAaJPle8F2//
yXF1TMnDWGiz+LJ4/tpKAB+ep7+25zmewAzueWctvyDd81E/+vel/qf1DchiMed6N+zOnmr03lAW
/jH9UKkeDdz0B46MBKOJF3iHsGkeR9XNtMP7NsrBZx+GQSmbOKXxtRROPJZQnnh9TAgyfmvubEN2
oTdk+AYIOtJPiNDnb3/ShalJJowuygg2dCMgfPcFUWWJxYRGhfx1NK2pHz4G6MYl3FjqFI58V5Yu
P2jjlmTfiJM5gsFIMNm2fXyGp/3p/PIDACDrSqDTfza2lc6HsJyStW5rX0XjcMAazq3s0X7UGK35
njjab0JAtar2KvLn7iRtuSVpOHX5TVjSqVVZGLzTz55zM5rqgFmwRK7b1PGwxswDHKU46yj89va+
M72ncoJecdz14w9WaKoTOQSvkijxIYE9PUaSodR/URjiys7WRHYmMatapl/IrM366IouVihpw0gE
29Tqb6mKcaZDuCCkhpvjBlLz575PFUN2A/J/RwlRhTm7R/5cjoT+bZrLVuCdcr+pGea4K7U4LFEk
OW/Wd+DXpuSaOzO8zAttgjTxwnxuiY5yNn0nfCPigCczr2eG5zjBKRjapq5tKn59IX+Fy93RxHHd
niuH8uTMAyBxo3V1e6+6O4Qb3WsEiwGKM4KdCsLvMMOsLu1rQ9FUpJv/OuRdxyH8QleUiMl74kEx
Rdq//sCW5pWbKFrcNTDOzBCOEtzvwiu+ppCwDL3A5GBzzqSlS7Tj1F2nn7pYYQBFRSRVwS0c5Y2Y
xxWfniwfrPuP27l4JewCuzwmIKgAhAnVy5UOf7GTQzksgZrI4VTOXg74GzT8hUv6YYSekgJsLrdT
ADdqiVgdtysoOn0TarcxZemh60uYUE0Mz+X3d7CmPi+PV1oCpAjEgcZC//at+lTlksptnpW4w6Zl
geD1tbQWyTqm9051zQf4tqKTpqlOu9tadafn5+vmnICIty9v02HBRyOZ2uK+vIOEtGCKF78KEmhT
cX4+R2FpikbT6ELjUAR+Wr8nQbFSCirAhNWKx6lFhXLrPX58FL0/fr6iM5BG08HFIHdG1Ofy78Hr
T+khaBwOSxE1E7++jao/IfrYlC7Bj+PijA5ivaC4nBEJVvvBPcouiwTwyh3rO/fsV9BfSsN44Q89
uX8CsJA5/TF9O49W6PQ0+g0WNcC9hHYgqSnKpGF0AQzimofBQc3g0M2DS4+TUDCVQmAJxsIEc7S9
JG2YnesYAaLnR4cUUWcj2FxqFkUNCgEBJRKpjWPZmDbTDgwfRZx0H9NWUzksG4buj1ULbeP7/eCy
4QihsOnTftd6jV/1KZHhvqMKaMt2lkBqBnz9OPH8l+8i/1tscn7JjuFm0B2hlPeEln3ve8PTui0v
O1xoNfnmcvOYS1zXTEsMo946kMiP+XDahoVHYvR29Hz0lkm0dKsNqsIA7Fjh8dB3pMBQ3GPvxQht
1F5DhTR8jFQF15PXinIGZPg6VVjOOQlkA/0AzmC6RQwLvaLEB1ClayDzl3JNs3JR/I38ys2DtHas
KlTJUmJwSKpk20eOu0zG4QM1X10HoxmER4BThMGhF9XfzVetBzNpiDxcY5rypE93ly+JaMxL/YnI
er1AhHiOp+v9PL5+NZ5Irv+biqp1na/tAp+CroxH7jUiq/PkUtq8iajsIyI6x1jlE8QdLgqO21CQ
eAlW0oQd+z43dsOMBX4l9No69p0x5G74X+GtUwAX3QaWvogBeyT8qcPECATrLU66fZFTdW1mGydz
X7spXsQ9VrwMCAoEWk1eHyt/+W7lbd4+5o8o7kSI7V53f9MvWgE5essO4oaw2ODv9qrGsgM5JyVJ
54ZojqFg/b4rxWr9sxkfNeBf/LEPdG815RL/iy9yeZ+yqXxVoWyuV2WsUuFBNkiv0CDOtebdN2qC
PffE9o82SoaKCSilxjcKzfkHobBOOpulHY80AYxraMcq20BpaCpwVXcgkR99bdQcCJsQUhLY9/GW
aMAwob4oKVJ5ZQgMi5uLmP9KL2qSGZkYi/7tyPcsf7mJmDeSxp1GWzQX8E8ZjLtVsd+8Q1/NSRdl
rwypTMi0Cq4Lmu7KuI4P2BB2NHb9Rp0g171FEZwowk1IDQzj9OSqSxmuMrbwnHdMLky6q7FePkUS
+jkeOoXds+5L2mnTMSRsQEeFnCh+mAh3Gjh3JiHcUbSYHwXj9vDM7IvVH2432cDCUAeUnEMZe9BO
OVpC527TtY6WVxAgx2nIrdP5ocF4AFSFvjvGbVRXsBLie+/7wR3dpES4ekCj3PxlQzkU0SU52ega
BdPdlXwQH87nsro92CPzn7BUTmD0RhhSQIcw/ib/4XCo0LiDhBv9Yi8OmrEPgmFWPUB5agMU2fzb
RKYYoYKyXzh7WVEZF7C2R7ZV4XoPgBWa2e3DH2ShHLvFIYaEmmSB/YGkUCcYwEub9m40ly7Wfczs
GpxXHjKvx/U8wBjxvWCZ7FwSYQ/GWDYZGEbw6CJZyX+Y87fCiMdQqsXGLT7AJQufSy8XHvXlPnFA
p+9/v00bZhuRsskGcDf5NhEvaNdpQ54yUTmm8/j07XtybWTqTH13VCxgofciS+MVMx4sO1XJNMd5
Oq/bN0Fh1v2WMCRgTWBGCIGhbqMw/qv2O6UJPOUGtNk8qUCOtBxG8N6m6z14uk+qCzgQFv3zRm6U
017WWQxFl7OlKHe9iwCoRfXoyz4xpq2mWBoAzshnXfzGbBHMvDF/wh0gpcDPqB0iz3VeowRMqEHp
DxXfj17pWu/bFcH+dgWfIQMHwKfYL+6NdCSMgDBFadU0/lUm1CDzfrLa/NwNrBBpJTteKSPKi5sr
xMIK+T6OLB3+jlYBH1d5fjCY8KuUdV6PKCa0FWKOQbN1rByH4vWfFn9YI2vpqemVkNKlWxtw98t3
7YTmA++q9jiA0Y11M4BeLeI7KpVoZf6HglC7ohm3wiczIXAHPljhvVifkz/P0qE6EjTkTBtopYrf
mXeOcjkwpVSMNc3WmZViUiqDsyCdpkMZms+uJ5EqnA9Gtsg8OlyF4DgbaZhqfiffd5yx0UDRVAfv
nxGDfsP3Zdl8jLWG/4n8l/qaGZEhYhoPgFo0fYBs5Hkjp8JRO0t5WFQYdc7/YEhOvYxOCy8T2wOL
+rmoF9E3WWxuCDoIimuXfR2e3mdottzPBYpEu/lU6cqYnL+GLgj9//BFDj191Qb4EAobWzWIFMxX
WyqP1VvvhD8tBwpS07T6LnLV1W6FNjLDYFRFM/3a9c+6DcbGVgu/CaoU0V3W59W8PLgbgRP0H9H7
59xG9vn+JF6KVTemFMnaITTvfeM64HG4Kda0MQ0oItadwlwUuERJmu8nEtC4lHbxMt7h4LUQPkao
cHuVD9NJcuZ1rUWDah/RHB4cuow50hNjJOcxzcKez4u+02lmrx8cOlATOX2ulxG+R4L+EXmYP0GA
HyyCznR9Mjj137uWaYw2NwZ+MBcQuUlbIH2+ghW/NDL1CsnCF7HEwzdyTSBfKNLvouJuwSBksCy1
YQFzs+CwFBHX0+ZtkWBNRPqt/LhLLE/IFbR7L9J5Y+PaVmKrccVwlG6xp5NRMtewV0s4YL/ZTtHK
wjwCeV6zUiP7GjvU034OQwq21A7Ji+kTq8IXQFi+4OC5eE8g2wlftMLeP8MouoUjzqEcMRfxXXLE
xuvDuJedd1PYad79B+7Nf3r9wIH9BY6DAqiaV++QY4n2NVQo8Q2+E44vu5YVMolrgKSq+P1vW+17
JPjb23Dfi0czi7NPrN8JtHStk+QiQdZd0LjT6lVaSCmdI/Ag64PsANMCUvXqzuWHBv0BZkP2G1Qu
ea0eatg4Y/pudRt91Lusr2wHqLekSoIh6EXQzZWcY28O1W1PaE0FTPJ4aa1APknMcG2XrORCNHet
WnDE8a8vGidAe+fjWr/YexFGVYcyHud84wjEXZtYo3ZpGTdg5FplBM0bZqmbxOD0qqog+Df6e3LE
SH0BMCF9I+tMEO7I4rbcjw2cy8dzJuJQFDLI8Xavy+lU6FrkKRWNZjn7rwzZPkBNAsWkXK+Vo2MM
u/V30eXNhkCSnluY4kWdI9+ZAfeZyF/lJ0yVhUJJuY5z8KkD4O+w7wx4iVwLo+kJ+y9KVYkPm0sz
6/CLq+zdlqnkWPkqzuD+ZLQYs2FcRgcBbOd22ssoqOiM9E2MKxWGz8oNpXSQSeIS2RnO99COFBk3
FgwnITLdkaTpSa9R9J5gTwl5OlKDbitvZ/c3L9X5KnRj6x8BDKEtCOUzSH52dJxde7WZcBcJ4RWU
9Z9uuRaQYiDvAjYcQDFeMHtxsdaashYCp5J8HuLkXgB7GLGPKEmsXpUcn95GWavBX6d64jWQtv2O
JUfm1AdqsKL5CqGc9MSSl2mJiB6FhTkipc4NcognZup9LetL7eTaBwsFB7anGaPkQa78AgF7/HbQ
pRtl1jz3q5M5XccdiH9whn+ktL8iWXxRJmho4W+GfQkhrb0pCgjGvC3HMzGxJhPwDIe12kY3a7Zk
mO9hipTjbu8P4kmDQzvYQW+yXJKLgb9blX+SNyA3EUcEpDBzBQvtsH8NJ5RBsEfa7YZB3thUQJQg
csqAGoqHpP2rrUA8GFfNcB40v0BJauwvLrWl/96Z4LokYuAuXnfzQ2EA7pUvmVnf/bojv07qmizn
bIuSl6f4gPDJCCn2BDPJXhFJqFOjSYnWJdnvLauyqOZXMSRhfX33dTmILR6B8l8U+dVSrjDNPgG4
MxZg4hyDdYI1dxlKbAM+GCIN0nfxc0VYCBSC/c6B4/S99AqH6ECw/rHcWnKQHTe8O9KLvUz2LRfG
qLJK4tXxtknGVpqURD+Zmkic+mUwlYNwS3cxIOj0vR1B5RGELLVrwqf60f31TjCUMvRuuK5zrqr5
sQiVFkxkHZEd6IL7k1uX7PGzURaXHNJZAeO0J0iFbUrIivzZKVzOAYdr+WIB7XNF8PcyKHjuR32c
P1xIX65iIFPV+fqreLuGiUknt5rjofjjE8CN/A7yk9LUjptaRJT+Yg1VTwYfK4Ea/+oq7XtvmCTQ
Ch+Q7aw2rgMdw6rqmXwZwd1s00ro5RoE3uDn1RfTITdvEnzA0pq5G7Vi/t01sypXWtK6YuKx9hx2
YEbN0FZOITCdYyhv8epXrM081X1m5TURm46Uipe6HN0gheY9yu0Jr05CMhlSBisqqC7GuL0PaNLQ
IvMO7tfv6W7K8o6QYzK7/jy9LoC4XObLmWctsLRjBp43XRxOGkkrzQbcp1egIQtZHRZmywM7Vo0G
SqiYRP5hFjKfPO0vzN+lY12M0BQqSssj6MJAR85Jc/TtjXNpoR69NiD1JsSZosUi5iGj3lMTvw9o
NOlQIS6SdhvfJT5bebbpq1BNV1Q7pW21jky9my+vi6DXxyBfN8GBsoNeJuKy6FZFQbhyWNZSKegL
HKtEU/j8cSXEYeay7ZBBMUjr6B5Qfab+4ZawIoTbdFDJIJHF1iq+/UX6f6ubszhxRD/C8PgoFneq
ywtNsVsMAq3yuzIjVnHz7YECgy+m9RrEX0+7TtnA065G7wXCmurdOD002QuiBB2PoQJO2PnU3JnR
YYYaVfvvdGtiuJtymvW8cR5SY0BNB0UZC1ctY5YEMbCUAZNsLD/Ac4Va0iTiMA390XrINPp9PRA0
QRQ2BepR3rrbVTGmaqXMvDknGZ7pM2GVn3YNTdtcr7WMjOKv1+wOCtHdW7J1HicKNSJof3qN/YWQ
K3PzLzd+m/yNqRtz9zguRW5jhoiSzLfYFQITcED7NJAUQ9PCsQW7yAPzwUI1noeHUu5n0mWw8Io0
9jaDcg6VrtlcYMlREcGRjFJTFrucgDqwmYucwyT+CWGZp2R9rO6s9429d9IfVwTXJp+WFd7AS91o
jxWXzY5iIKjI6K292dJYoWFnmPN3duRdWa55ALezeowDBeMUk3j6B5B6pbj8L2AqIu689QYY8Z3Z
ofdaVS0NdSfXp3M2AFOcJ2Z8vq7qBWGflZYqVRC+UiAx+C5VTiapu79WXsjsPJSVzOPmpeGEGymE
okQ2azg9EaTHDqxkj/ZZwCFF1Ky2EUb0DNHOy6iTNp//5YBDgrHXWmDO1GNUQVlwf/K4xHIT6eJK
l/IiZ/Xe/cauv7n9NA1h43ZLRcRpFPjH8Y7eWncgOsQ0y6IqUdMQU+weo0nsOsV7oDd4vzf7CLrb
x1eugr1d0K2577CWnfqjA/Z890gmnrHZV8Q4gHTybwH+ux1nXq67J/QptDzg0n+m2XfCBROc7u4u
AJcm253a1ZdHD3nGV8dW2cgmw4o70t2y4yDy8MdhtstsLIVzBMJQrzRIxGykb2+sCFFcBLCpjAXH
bRfNBW6YfbfeO/W410LqEGkXtYphoB2XFPpsDw7ujy1+alnJ1gZPmessMdh5JteCLST7qXk9qpPE
WgKFuN0RIrrjpOAyZsOnLXqslB2qWBoRDiUtanoM1cHC0jEfDOBub0QN/9yVNO+x4hSC9+dvkH3X
hXlhVt3VmBfxAew5OWYwTEVaL3XCbuvp0wf0qTiK+j4FV7TBwxh74Lwfr80R9Dy1DDZ3ZnLX7OKN
G0Dw/f57NgWVcW03pDzQL9x+BUbEwIep3ANwzdROXWQcLZNGI/u/RDbA+qYqbl6CITAEqoESv35b
SCb/fp9dSp6H3oWYkcoX7X0EM/4lcRD+FF6902xyEDkQ3hdSpf5jHF+okafmXtOwdEcQrZY2nUIt
kLFTlriZ8axCnPj9lnoX0quERFQ4rmZMuBQyn/XZi+hhiblmeNz6pf60dPdzSYNqpuMHz2O4T0XO
Xd9gUrmyGndNKePb9jTY4yHnkyyegIplJeibFvFcMfCe2fuy4dK3+VjvH0C9PeHWUZGOn7noGT7L
8Cbegb0cv1PpV2E/yQNe1KpiY1IQZCu/nIv3uRpdNi0dlTIDs9Y3bya4xOeWhZQKwFJ3pAs01BRT
tlfgOyRkI6u7Vwrm2w/mEmOBli1HY3BDE5Hoyr2mr0GCxoBYVMLJZskeP4N3wER+jbIxHnu/A/dG
V3/iVT9shoKQzD77FqqGKuKxKAQjytefetnfPFZ6uZ2l/bWTU2mdCUGAlBLO2RKCjLHZthJjDuK1
LRO2AfxsCI57idVVcZIO8ESjFd77xQLkF6SGxvctCShdOTx8x++Ks4WFzJiMZaSTKl3MoSu4oFpq
4yWXpxCdTr7njznr96YNPLMnh85ENDod5Umc2dZHQdN6uHl2ygkxQQbvQ32AwL8WgcNRlIHfmwoI
TT8r0iYOIA/7baedkWVD6zeFBSqmxwcIqV4XgoidAR7LQs2jWKqJkqKKrPaey87DTyAOYVZFof/R
iiUUuFZWugr4d4MxxQAFrfbHzsqIGCJzhMSx1tLw5qqYWc6RFU5Oj0T7mxqztoDyNzah2eycBjam
LRog5XmaEL4doJDEiuboxnV85qElBk7yXMWLna4unRIAb+B9GrwZAMw0r27DdKjkb30RgMWPYyES
7mR/aaPKkrS356tD186vUPsBaM8kAHuV5vu10jBNCqi2drGjHjqNb4QsMsSXFJ4G1ziiKrQ6XTqT
XbisxDzNGxbM1KEjANG87/PLzHM2WCX5tzLwLX5CYj5Hv905an+K27tMzHj20xbe2ZmuJyobjjco
QbV0nJF/boxcJV8S3d+g8lS+ZhNBVp/szLMVfcoFyI3pUvstUiHJqZhmQfaSMZZgDAMreMa+2fkh
wj+Bv+xIg3RxeNIDX1z0SOYMdY35p9V4B4l7giji5RC9JmLvIHCzpDDL9T+Rak21uxeqE+f1Tuez
L6qmg451FDGGjbDiO4Xw19wWpJhL5Ngb0OVUIZcXpRWoZSvPzy5M/N+mBD7hednKcUee4ccim03U
0t2/Sp3DhFxkUf19m8PgjG48ScmNUBYCtnGVjP+QSVd/l6z9MLy6rDuIgJqu8lBjOu8FXnfvviHb
bvQVC4On3v6r9dz+SAymle622X5n4ZVfJKJz3tZnqdxyv68kck2PAf3cqLtfILzPd2u3ifvtn5Mj
DfTDeEeoG5OUBWD3ipre8R7Ekh5Ipn/IkuTcCzeNftm8iZfi/we+H+VC+PJdUc/tVPM9oxeDf5ph
zze8ZKuz0LXFJhqU5F/4CxH3i6q7mm61JjjUGb10RgQ2eJweaxR81eARI7OUwNJhqKHnk2g0lLlW
2i2ggKUi5MNbPSBX2PpaBveHXgX1sFXlKQqS6bfaWoa5SVADwAoFLrrmaVlzKvYhIcNPsCKKxJ/a
AqAtqS2IW8TPHnWJq9DF15N2EFGcaSJS83crcG0yQrsBe/sb9PxMv3WMH7TXgak77HxBoXP/QN3r
1u6c/tLSbp8JgmHfSSrRxeAgVLUh6SJy8mUqjbb/FZXLY/laoSYOCEvV9ZaOrk7QFsY8dqQJ7I5K
hB7HRrQYpgD3zcvcFiugtLP6p1EER5fJXWb3hPBFH56hKP0cD8GO3/TKgW31KLkyGByrN4Eae5F5
xUhQrKRN/RiwmwJzcG/rOjtci8aUH8JbR6fhxs3/EB7ndoJmC4odaG/43KNXIunlSYqgFIFrj8UL
jhacJwpk+VP2WA7/3ym703OXA7b1XmKdoSie7sX92LUhrgGGHk9Qeu7vn1tiBYCfK2Mt5WWnRCnn
+TPEN0RB/kSWgLPwz+5/rrLdNIcNQvb1GsGYnZv13j77u3jozl54S7yOX5cYZ/dJLhvasBb4LnIt
S7qObJR5xuXgRe6vCNGFlt3lqeoBoft+6EUCVFbBpeWm0qtZioS6l7KDmO3sPtMqZrWPPXp0xkSB
6RdXc81lfkMPciwxLgTFOez1Rbk3n3xUz8fAZGTaac76Ty3qqJVo37fwdGORDxQcyfLrCq4Nd6CP
8eALqcd1aSeJneV8uz06IcM35b0uFSL+WeQhTl5kdZAidKEcWtqkLa7dAcn/kDiG1kCcGmvGHfXa
qn1irjO9qhyO4CFY9s0nhe6/ksILBE6Z1quldWkTOG5DEdSyGFwVbM9GrFPgDgCUNezQiEhSHtYE
LiexJy9/HcUjg0YnUBsFgi0C+SKKzNT+o05GL2vJTD2tcuBlsYNddciBtr3aEHu+AYc6cZb8QTER
q9F7WXcZxWkR7AlktPochgdBrRUw9ZVfhdZHooGufJIbmNsRoXJ/32D9crK9dV8WYtry8PQ9amwL
NbEiYqd364+SCg6UqvHVw4u+QULqXq5jBERGKHcypm7czYPSL79KAzFdgVJFKJPCYvys4jHkbvQ0
7/KKvTwYY4nDkj+oDpsd7jhtA+Y4/bHcWf3CtXlvc9Hmm9OyOUv/6q8Noo+wPUxp3wjKA+xYiasT
fvepHfhPXUjFCDc2OYV/XA7CJnaoDag2POozp9ieok2OV0io2+j4WlYzMRT3YP7TrcUhv/4d818g
qkoO+VK7R4AWi1KTGpXsxAGK5Mk7D78d5hutfgGANT/WLYbShz2C4iy/LnJQPrhQxn9ovXkkwNCI
Glh9J0RZcV8o5e61W4xA79q03Zyw62LElDj/w67F22WeFbezMFrIT5JfKZsZd3DtIyrrslINdkoT
RV6hjgKROquC1vdpL1ZvvDiXbwQGWWjhYCWl3AoISvV72vxOyViceZW9p9eA4Fahu+p3rovuxPvl
SJ0LX0tOduZXw4r50nw4GsWijnpvVOtagdK19x0EEOxo1Lm0v84Qfgp+bamVmL2WGuc8MQ9Od3fa
yRWl/eZBLLqbsPT+BegFmyST6uDZNlkXpKCKL5SgOUKGD8g7Rz6so7i3djobhGWSlLkF9IdfQvfM
TlRsgF9GNvm622P7oafqzVkmSnGnc5OlQRWCPuyvhznoVvXrBU4FNliyB9WkAsQBTOWOxzgtH+jk
Kwlh+6ZYkDDQxuScWaX+cwQY+Tie55ati38u92QDnjhbt1WRfrla+Nl1SHn6m8MpUdqZ+zBL5A4v
e6WfvQcGpo1hFsiue0bwaRM69/8JnAg2pJPgQLuTklwmVXEuLf3p2ZgeNTrmAK/varOnuqkSg1k5
nfjKmUBaJBhFqHH0m4jrX0HFqiQFt8d9vcDFTM8plQeIY2u+S3UHIIeXhTH4xmvWWTo86zPJYY9F
VSb83LM1DDQUZH2G7Ei4bBRJr31tszLdzBX0aVMkdoyPIDoF1Ti36hxbij1O4z/femuvtjYMRXcT
F8XWzmraun5bau0YDtTolverTX1I9QXp7rX7wIl9A/ukg+6nJyGZAf8lMx8ygha4CO+SvP9U071J
ffE3Qdw60RgMINeYAegmAX8X3Eq19fs1r4/LJwa+RFCXRIw5teuDXIhenoFULdSKli4BT0DuPmiA
zVqI5D1+MboPitJQp2aWbpN25+gDGAULsDc786te4qw0+NcSUnqAqX9X7K7r7iSMtOPigPB3xXSi
LoPnagE6C770mM0okHieTZEA5OorsKU0+dhgPQXr31cc/yorByhjaTWmEFwLqY8g3Qug9LksD9+Z
2eEUkwjrR7q03nqpURquplM84th+7LdL1ac3PstmG230MNvWoCVXWu2Ttt/sKtzuk71KDFKH/Qtu
W13L3RO5O8Zd9AKsGGQsRJS6QebFhMb6qry1v9XWKaWfAQhC1D0A1TWWcnNaM/yQXf1TNxmzJm5U
ow/RvCduLwPt/Ax3RxDgGnIzBgr9CKVFjY2m9nJOFWZBtRrPAWtly3coyMcAM5uCbD9wn7DwDjbL
Byxg7J+yzg4qGP5Xs9Q/bpf4NvfoGZWgIPUbGm7Jo4JUvgmlDO89fZMR98Iznb4UIJNlcBkWZbCm
asmRTq3OFKMWzrZof8FYYI/IpzN3gTkJXkTVlWysbCNIoGMYCjDQs/AdmaF815MTOdnMvmXbh+Fc
ETXS5M0PSLdvkESbUpBP4FTMVZ0Y+fT8qpMDpxw9/Bjglxucl9IoTjezNfaYnvw8EJpERHem/ZNI
BXJybuy+BOmZS6Bue8kU7McvHm2BVed4IVhJreY1yawpggPmLj2X6RhXpC58fFRM7L4iN6LYkHFG
NNlFq2oGqiW7hp9JeD6i2BWwbJHAGPs348z5yn3wTxCqdcuGc/WzBINAs6VYY8qzZVdKQmfj5QM/
MnAwofN+QLWLlKbTYXmSdUW68AUp4lDnQFpgMpGPjKhM0B+YVzhNWhD54ByAssV3KU6eV8xaAk0G
8hzTmTEqiHjhSZIQBfez2hWop/aAhqWNLXqCLolQCQiP2hFJEcHeYwaS8coqQtJA5XQISimlBoWE
PMTeiogxyLM4OrZLz2WWyxQPr0ASEgBApawrlXmqo4RjkOqZO6kUYI84PCyqoxZz8xgAGkJ8mC6d
mITN96leA3ZLUz1ZivhAaAQu6wIvKav1k8fvVLAb2LC+5ZPqzZ3F+W3+n5at4iacUj+rImeRX9ky
4kHCWQnrBTuUL6kPCUPwbCGu1ZAlGPWE4lA8q7Lqb+d2+YNP/d/tZX4EhKOGXnZ/YbQITo5ehLU0
Ogu9PQK+gaNzABJ4tzWyzskESKfcb7pAenjAT3jMqJ3FQKm3lGdnsIPsyOwvBPmlG/k8orjGxRGo
Y1hQnS7RUz4wU3g5edgWBxXpJz+IMQZf5sMAJHSKHMZcPNhH57l3vO162ZURVJjzuBMjZ/AAl4U5
nEBa/6vh0C5f5a2o/1ZoTHk2gv2Izr4WyrRKUHIO76/C4H63JIrJiWHv+/K/lKXk+2Y0snXyeAYj
NqGa9Zo3goEbnf71kIvIsWTHW6mYxFD5qhzXXEMY6pPo3+QrMC5M0XQ+44O2v0C60RNhLCKib+qP
teFLxSdGXdtGWsBjlppRYKBriEBA2DjXamxVMFmtlG8hXQ+O3xirfZavSO/I21Kj0UyL/WaAFfW/
IUp4wk8J97pZLq9gvk0BjeOqCpXEhoMaco3L59ViwAjahDbTQOPSvWxQhaLQ14qXv0cVxuwf3aJM
6YvKpRL7xEeJMIyiiEh0AjUVk+ZfEeOTFXRmzPAv+l5m/hz0DFYAyh994gxzVeRqv/2y/SUobsB+
JYYyZaNviBTdvxw45TMs1tmADAQFulU3GIOW3XahXH/G6HlLlq9xSBAXUIj0O78F6nt9X88pr45o
75g1aqDooeplNaUHMwzcS05WxMHt/ohYXuyvHRqZhynnFgSBv5W06qBJqt2o03JTh5HAxPNOUS0M
t4WliZ7z1rSnQ7m88yG3nc/BdGEQR2Wo8219Tn/B4HEQWm74PChGCVNjpIT+ACUxgHf2W2MRcs4s
BcWhgNtAPcvqSHMeo8NE4n46Jy1sg3LxU5bJPb7w70Y5RzZ0EEV/tyUw2NIlGYZ5cKFwt3HVJycq
Jw7jt3kP3E5nxtqb43uYz/5mSxZInBBTIa8rhLgCAognLSnQSl+vC8uiDDh/gMDOldbbsCTrU1EY
y6E8MciYYgVaHFUjx7z1whjA0tBfQ+kRzbZwp4QfgDAHTQ/6KEg99ryM3lWqzRS+2Rmx8Zyse+9S
mY0Zz4vKpFGRm9X8kpFmjdvc+dTzr6CX6LsRmH1E6JawqDpbgIW7FG/u1qbr+V4HhtziOWVXw8vM
0f7b1hJnlEDSThrVDZiMbl9+tmY+XO0djeczofhHvTnLUUV+D2gfk7B8OoCFF2WOFTcUERmL080g
1eMs5FphXnDhoFRfYtAfxMPybnCm+GC09HMP8yoYeVTeyim69Jz7bGzwvhiRXaeJhdkPKJMQbgQN
6VdEQzcokO2jJ+XljpLe3H1ilAf2hU8dRaK7Fm3oj2TD6HCoQsvX2ahmR/2OalXSDNWjm9Sk2rn3
iJmu6KPEkvsn+uTdA3TkBnU9zjXXZnHZpebNMZMCSSk9uYd9IhxS+mGWSmDM3GCysE/GGgqFr4aY
wx9yv4ajCHERFojAlh4kiH9jFGSF5O3bEvwHvwny9yHOp1WiIgzwPg0bs/F4Fxw5Q9kj33WPmP+X
yq87ObIAEEgql6s2+hXVf7LTfMFgilqDKMjPil2jMs5rl4eSuP9mMRDV+BASz2cc82EtmnyzLOUG
1yfysW2M5EeF2gDOf8+3v4LhKhrHCDGZlvBLY/kaB8nWB68/Im5y7lK3UDafleHmsdNHuqj2tLhy
NR/pJ4NPMFkrFkrsxQWHBIyI5s/HqyFu2LfzqpgU5uwi3M/2kU0QLxQb/Jl6bHxKoD2zY0Ktlm9T
rKiuAK1izkUYH8D4b0GaSLJn6UbmCdXNb/lTeUYNfnjVr23dBBoz1ZYA+ebhHn3zaLCWHwzHezw1
Vl2/PewA70oFBLv49Puyf5A7cWasP0YFKFx98VlSaF4VcyVsahRh5dwqvt/djXq8vo5vg4I1DIB4
RIJyV0SQuKpqfu3EcYqQUcImt6Gvci9bP/FN0h/9HxAm0jNAtTKhx3Rsy3lHep2LcE1ecZn6ythE
URYdSWULA2Zn2LFytejdTokGiILfiQlJj/5PoUzD3D4okJmL3ku9Z1PZUwh7lyvY44IAUYjkDs01
FCIJsw2jEWvNseW2QvTrH0bMp8lSu4Hc5oFEEx0OcNaFFTFQjeUTzlsJJmlXUYkA83qVi3FEqpjo
NE7kOH9l3+oNoihe7EUykE91LcqHq7zoKdayUZnGNn8sxLjPDObACihFH4NNfrHQ8PqPKVTwOhXv
1Pw+uZvhYhek+QnKt3sa492iqeJg9h7nXJEsiAxMgzMd72IIoB9sOzBJr4Evgv8Gkg/DaGuiXYtl
ow4mmjFKKiYtgFWFkgkohhLxY6ZYOS1l4YguzAKfX2ngYidKEzY7fqLfI0G7YmgsX9R1LGUt6dxn
KTZP8bgV/mo5RAIoLxrNTVif7N6HhM3TplL0GXz7xvT2+WnwETz4wDCqcX+h4jsFk1WXRzF8j3gv
vAjBrEru3r5wVlETWeP3CUOGxmealEg0WMq7k2mtaUKhs3rr/1Vw02pesY4zbI9RuwcR8+rT9po+
RXYYL6AhMHxaRs2/ypQHd28tqLqNtyNSWm0rMBJxvWGvz2Rll0PlbgovxQ+FXxkhG7C7afChRYPU
1X/D3WeSR8myHzMGpyp2fu77qefl84jYxveOuJkX4uXQJApgX/pt7YqwnS/OPL8H0R6mbdRCwQtD
NQ10hRxOjuW7ZrWIXVQOMrDXS41GQAx19Bk6HTg3Za+HomJy0VUdWLRbD6dBAPhtVIBvgdQEGwoP
B/dmvpOPW+302WPLgKPEt6VFVHXDEFB9ysKr1u2J8w7TMzZzX2QprJczTHVFjeNKPxWr8rQSEB+d
y2vEYDMD6V6jaz2DHC8XLDqKOWjZOi8lywFK4Q3NENKEf1h8WBfJ+U6/9Fyo7HbRE5hRwPRyjulw
wCl7bs8H7NUXgjeAjFx+uc/D+KSqHXovAVlemXlVtCkJ/9fqhgHoyjUfA7T20RomzaTxP5x6iE6z
PleTecrIfWyk/DatK4TgJiVN4dp1DQYAuUk6jXSQcYNyZGfh31wuaLhwaU9n4txM0Paz6bpQAX/G
3wKuqibsKnJJi+CUJ2Idc//2N9sTUxAojsE/I9FgR7Tggyuox/TJrDzd4lyRb3K8kGIN3XqCZ3ph
B9dmIhR3ZiwbFy4MDR4/If5n6/9f9Zs+OCMaBJbL7w9lvU5dUV2uuahboEeShcanQzTpokBndB/4
4AZOerk4ZxiXM62YH5k9NRGt16tXMpNTli7QD20w7/xmY164qrmYktmzdTfIi8vG7Xd5ELVLyHaz
G7CGrllzN3SAARWxewBJT06iVxu9/WZ6yROpOuyAllWZwav1J/MgVcMx/O6LNV75ulgzTlytRHKx
jwhsAdZWpTsWRPpQRRfh0aswvAo4WecQsBilRxWLvwohXzILpp8kH4SXTJ0ZO27SxxFC0CT7guLD
uf/HzUE353GAvaRJpOulCxaWCWnWh22lrllunCqUzI/4M8pkNO67lSgqaZxfhQc88U6brozHv9xW
mmjhievqdVrR4YqTj9xPMATuxCPqQ1MOGw3EZmjO68IdCRZFGTVzEEEJa9SwH2QEzY6QPLpXv51g
1H/kw2M0O/99j7mIYK/H+G2RFshAtercaOnNKo8kU9oQk6d8V3VjBXbEYOzFO5d/hH1xpgwDsGcg
4OFa/tpzudXYAFNWEtlMnXYCrbmEir66UGLn1vrypeMJjaE9ZTfz49jOkso3oLc0kQsU8AVXOaRf
rp3n4W9FLPnL2+de/HYxZQqZZZ5da3NGf8xLp64lNUKykAj1Jh2z4glVrzJmcubSReq8vtYH966F
ouXBAZfNH7TL4lSvrDo9Jl6uePLb2k+TVhSbfOnnwsvPJ4hn1Hcz80LtUFZun9QkHeFigMfjMHGL
48RQ3tSN4nqUGcZiifE8gU1AK48aqleUi3G5CtvsFsS4HYiVRib/bKqxAwz0748UAGuvbeoqYv6x
rNjwxn28qaKzdGBmjlEp52kJg3sB0NsJPKuNf3doR33DpCKbs4bzasIT65sJQ8VetRLG3fatRY3v
gqR+Ir+pRfpNO6u69Du/QUbzsDK6/ojn5zKoNTag9Wr9uU77dUEZbyh4jwPgdLX9D5JcpxDzD7QA
QgLBcWMTsLQM4/6J6yA3U+jAEv27oeyt9QnSRB4DYx/azO8cSH2KNOIc4ygp4deDiFYuaTlkgxZB
FesVy+jIx7NUdzg1EBJNu89puuOkTBLwI2YKb+wja1z2zJ2gv/nJtG+jvQBTkxSMS2QLJ70mk+0F
jqKbHPZZLeWcVBWS3rBrR07xPqmYqyUZepaFdZsdUW+S+FUG7Pk7ANdC4D4KfbHHJkBgzi95iQ9h
L3JV8Ay12taEuWPVL2ui2WGn7D6qj5CBcT/rg3n3pkC/Qj3QgRMUf0isWwmQtKDP7PZ0Tt6DRLvf
fvS/PpuZ/NFgdfmLdlZhHV05uCMpxzwEtzgPD3afR/xa/tyMnaDQ5UZJzD0nujKNLpBDInwM5oJ6
vBH8xaI/GIbTTjGPjX4IttFrb54oVjr2XncVE49i2l1X3CCVtcFMQdFaz7ht0BC+Cn4CYUa+eo53
vDG1d57Dpya5PWslnpt0IydBf6qm65qS2Nmku7VqiJtkNVGk65aCseHMeEktFR96sKQR8WTRzWUe
d1QOFhnlado/cpUN7hBjblxcTM+XyQ3nUQrgYC6ima66ajqe+M+SlDQlBu2zodLJZh8Rh9+w7GTk
j7ec/PJxNlQS83Z8HkZgalUKU1SghFQB/l+AGoKWoiQx239U3DqYzadDqXKGUTMK+S68XFfLZzD5
Sv05IiptZORJzytAHhUY5td5O3QUljxjbLZdafCaFUlqN8/doZwK+sdbsKiYs+C98aBdRoXE1Z4Z
Sac/XeiiSW3xfNEZEVZKJgdjOeESgAnFQu31sgu0o1MdRxKAl1gHjFW8WTZVpiwEbHgLlegAIUlo
thf3OILjZqSqvbnzsntYvRIl5uG8Qd9sZyJhNomGZ9NrgssHhNof7bwj/3Xt0q98eoz1TpGY/tkG
x+1dleFof1NYAnvpstAr0tzdyk+YT3OGZoB1FSo0p0gVFmFil8bd82Ouv1xqKyLBSrWma4mrG6EU
nLcnoeyLRRdSAG+yqQXqyer1VDQB2C9JIQXCvSuqI4z4K7RAutCjKn1pgQKXUSEfkdRprG0XOhYS
920UicJIi4XB28P0Xt8s8+Mu08vGXz4ejtIbnuhXBKkxvjKMUib3Omm5ALKP0RJgRSfpf/zj1utV
Sx8iSwurlvK8ZKMhfkNCELecSFu3PWpe7JAQlyMKdXO7hOYfYXMH/uyXr5L8rJU3JZnR6vpfydJ5
z1WTADdtSBQV4WSch95apgpKPeCW//gb2RYbZ+la7ccKPclKISoiBhCV5DCp/UUClWumdf1CK+Kj
ruglGH8zD4TILPO5r4+WGF9EQA4Hbvh2Jkz1B5YCCr6/HCD1Id/pwVBwoUcU9ndZsjdNlWGHsUiS
uzQtXyowgks7lnYPmYWRad9b08d8U3eVs29icpzACSjz5KXy0noNDs9jU414y+KcSJNxZy1xEQ9b
YW7ZRQXjwlm3LWQydDfHXFd5s7LfzvISAPG9tffghCtkkZyqByxiASICB74TlEw5Dw5tNsmHAsy4
jfMnlOQbajXJN8zbaNBDSLVoU8/sgfTZhBmwXs4omNtAReXcY7zRchDDGAfqITGeUNshnpceMrwW
EK+EiPjMVJVyF+c4aBXHPUerI8dQNi07zkf40geMSbFUmbyedrmAUpDSQuf6RslkZpeY4HWDOm94
g3vQsgaqjNVOVIcLX6Bso63mHXd5KSLelIpUg2WmVb57vNZwRlB+e/bH7mAFOEv5iAWwxMGrtVsk
8zXZb5/NhIImCeH9Ny3FGQUncEfC8krQqWM0tJuyGg2AVCSh4spu8t3HlsO7JNAZ7UgUtMXsxAD+
QXF7zrkEnMhM/MXlmcBVLAeNDYZLewAp2I/t04TPKVHK5hgtSJxm85trqJ2SAHWTnNnXy2uGC0pv
soT/PYkMLOw/c4ri0p3zmQYaekPPHkB6PmvyYXvTOl0BaPbUPvaHwNyPNvFOyZYFYe5gDs0chr9V
SH+LRFdykhSkiJHlX3tR6rgfzC2reWwhpcAgSFcpX2AwU7mIGzAaONFTOyupp2iuFCVALZoXl2HP
dmSLe605TNUaAdBAqaWoRwv4e7RVlebbNP2F29qKCRAqJPwS82q0fNB8A1abxDtB0GfywhkyOdnK
B0bR/fD64+6qiSrxTO21lWmSldu+QEz2NEgtBoNnFxxZSnYQ+xOjpqSnFkfEK8CbNxoQZKFMTzbE
uy7h/eTG4fAAg7vadtXp8OJQVKmQblpZMna4cefnRHhoONX+AjqoYrcq7YJgqigZ+/Dh4z2xQLDS
/gJ/8XzETMukGDzCT3QsEW7oGeLKTiWWfZNJeWA6X39r9t0UsD8NR7eG3RjlrWHrYTcou3PO83Ul
b50JOj1RRWgRLpruQIdYLsb4KdCpEwq0RYTwjoEXezpWD+ySoSBVo6/9SjAIahMLPb9Tcouukgnz
mIAdtuRBYpmlsDRjtnRdSfeqlykiWhTSzYJFDUvNt402gXlFxBEzhwycR/ZiaDd7Lmu1/HMqnlgd
1xNEmmcBTaS3t9k0T1pgJuif/8aBmz9vRF6lgmc69vBbmYNlfUb8//PXE6FhY7S/t3Dgw4FuFvfk
SOn1cTlXw3wa0B19NlI734peWqmv7ZvOzikuslmuyd7psqUj6vmrqR7YcznAnRi0rwMX/A9vLqOL
uuYm/bZdbeqJ6gZGGkkUPaVVgRslis5kVfyR+FmzbN8u/Qao3Z5YY6rH6zaIm54Bj2kX3fRu7y+R
ZzqXtHeT3TXkL6V6R55WD0UD0obVL8UJiOtwuEkSAQp6EjjbCYARUW8N4udU7DowSQx2NJFDYO0e
mMftjxPfOTpAfuSMdfc1GNr+Ex60dfyaYJ2+2kI2zOJHmVHrxTKJY5ELd6Yk7SmnAIOvv1Z6/Ccp
SxaoP0LqWEP/8Oa0Qe08oyBk3w8cWHBa3dG8PB2JDnwkxIAko0sWARIw5BC8L8yTposE91z5vXyi
CbCEYHRdaB7G835eW/pumfz4Ry44wjx6ov2n7tyTBPsz8OzfySvWh7YQfATb5036+sbhxSbuRm2O
qbhUvd6mpDB4yM4t1fF/y8LCYEZy6P7QQXwW8JbT9e3l7TlKe+tFXU+AFO+UFOobATqzXFIOoZ60
qhlUBJ1kb52iKuhPwIGxMv/S4LScMqYyyExs8joi2SfBFHix1+5agrfTUqxmSxe/n83m31zbjMmA
V9spGFVmxXWyc1OF2CVcOTmRlYm9H6KB3CcacKpszLKM2qvul8M5hPfnj/anyWwWvozjFlnMvJL/
4RU0D41NNyL/ulPuK5L3obI/ot9GooPsfaQ9CKrN0xZHp+c4h07ARQxvJur36iZVn40RYxbdrZvQ
ij4S07wi+5UlMkG693DcmmajMI954uGIHYq3Lhm2y/SI+LlEL0xfTXoLyvhSy84H7hgMioxzm4mW
BrR7DhT42cNrU3NvuEVLQ+LuGpkPJFkwsHJvYNKpX4g7X20qeYqwEw+Me1zB918lKp00S3sXGK1a
r9xLXtVfquEsZ6x5xIoBDEm6nncI9Tp2TlzhPpbrt5kKZjTuTegLvqGgloDVK86fbcR+JkKl5AP0
e3jgJH1nbofeYmPb/b6hATHE+atppIf5ao/eXdTFl8o7ZPaFMB37IhIdak609Flegmgz8fJ2bbFM
pBQMFwImWWveifD9pnTEGsUm+oDpOt7+XVbUbla1jlST8BOSBtHffIEJTnLdt9tx7ulzIku/8UAL
T8TxGgjWaT6tZBzMcRDSa/cNG4UxWNnw9Z7YN9GOhO8a9rOjRZXFTca8vOGRDIn/UmPGYUSaWPzg
LFyEwdRNVnGkN5tQSzXVsBg1uax4umZ5qytHrpI1OQTjZESLOCNUkr8qd0nu6ErgIYE0Z/G0LB6+
NYBcinK1Z91fcMIdFdMYrdjNI93Pc0PuzjKQSoxkVEny0cg2KtPQmN+ZfIkE+YCOLQwG4rle5aFX
abxOhgCzTAtC4yt1nSt+8qkIsxlxayeyI8QNqmcCR88UinpVz7phPonyd2TjRzKb+cCDHnSHYM8J
tRDv9JYy9ePuR52bPZ/7PP7ElpM9lg5kA+tXe8aABGBhxQcT90gwHNswCZXFiOP89q6cYRmq/ZoN
AbHwLGxS554mtCUiUnDcK3KKW15PSwEOHYaGgxZfajgbTrJa48hGZ1oo7lI+nyVgJKIX4wA1wvkd
5gywogoh/ihqe91jRdaMHTyUrMgO+Cz1mu+knsWRsMTZ8RPhsS8FGEnPnCuXspOIbZgrAAxRIW+F
idyd8HkjryOGJaWie8L+s0dz1QWGp1tbTG1v26RAE2lO+GmZihf4tYQZfpUGM8/IVdSX7sqB7Xc1
oOqWuujjaN1baZq5984azUxIx9jMGQhbHF6F6G93u9Y7mZREz5h8Rm51spuJr8xNK9f411JudHUs
qpYIDytsEdsbgiIt7a00tkNlX9X6C9/vOFd1v9R2o5K5JjmevktjPM7iaYjZSnmRJA6XlWz4vca2
aUurxKPLECmAaJv5Rci+Y9vOIObgnySZhb7IyojdjqgenoyS4o6s4I0fL+W5vM7PgHybhxUa/tEx
649O0a/9ukZ9kt/Mswr2XT1jQEaemzaz/Vu7xC1dso0LOBEZJ9cDvbkmttpU3ZYI7rdVT8evbAXZ
jEknoZvE6A1gAg5JOq0VsiPtOJANqjCkAoBK4Zd7tWocfedPk/03XxMHsLL2FW192D73bSOJjhDk
Wldna0cHkmatqgYXFYqe+IEqSGa2JE7nqAjCRN9AqNYAYIiOu1aJiBq8cAwT+6HELs0Yg26N6EcE
eSMEifyusJljio+1TIks88DnawaciqpNBx2L6iv96j/rTp5DTvQxX5Lh6nk7eSVeWc4KHPQm2mBF
Nm49vF7kbUkiO1YORAlf36PefsOta3VHSk30HbwjWNXbzU3VSKXOaFCfnKWbl3yoFtJWbJAJWUG1
0GqbhRkCsCI0YkWaTH73atcVrYqYsd0qAkMqbc62kEGzYB1VJNBQ/guPh8J8vf4HY6zxVrxP0vFN
4AhrACpj0vPXMSd0e05j9fCVblog04GbHxBlc7MM0BKYWL7kh3fDCmNwMNQZM1mgpTW+uoTl/vAu
w05oY7I/e0z4mN8JhTJtIXTMqGyTvs4YKZNKksUh+Xdq0RDh6XsG7MCtT+1dNNgJdi3Lu+Ygf0JS
HBk/cx2sjN8iZpcZR/Xm8EdDQVEpRBPHm+bmHx3ddifbeB2yJReGs5ISAJUI5O2ZYGYKiokpol5r
zdHOIoq+TOUkLVEzBXeO3OIVdWS+3lz8tFm+beY9ezuCaO4+Ct0QiMfHybwnMiR182uv+aA2AycG
5W2tuNLkaV8a4nTCP9LszNUCw5TOaa1NfBQMLerqOjH3rOZGSnOOpR9mAE66jMIyceBpedc18P7h
tuXfKOWR1Z6tOE2eXMwH1SKBWCCLEa45LplJ2R2O1WRRi7Z4N4/xKLJbBWpG2lYAKHuuqPijNUMV
XA3ts5kzeYrySbq3m3/5VcB+tK7ZEtG1Zr8isv/eew61YdzGXE3IhKGsJMEf+aTKpXfb4G0DIVTn
k0NQR653uhgdFUoJMMsZuMkafVwfqBNEpwwPedSV6Rpj7WnjkhC6P5We7ib7C/CFo151HALBTj1p
hhDg5a1jEzdICU6v9GBdCDpTlM790rMEKzJIBWDv85llQDggTevOsROAQmfGC4ABH6TU2fVO6+sy
aj46W4zG1cbOIjZWoQHxRp6sqllyqkCqbYiBkjCskWeAl+ApIN42dyP5JiNQSWANyzPv2rrPaq9n
HE0v3n5Y4W0i+Vk8eBukOguqnkb5lkQMWUDg4EEgUjDYPIwoJa60w8uq4i5E/lqhMm2+aYCmca+s
p6MTAQdOQmBzU4oHj9+hdF8r4dNb0NR8gukaDgTO3bG5/2MfcY8vicPPMhA8Lbxiu/A9bH731Rvi
MygBLzeu9A39F+SSrxPVK+suWh5fyKAKbqWN0rxuKDULy/tO79RCjUHBqzlttbAD4+pgISygpFLx
EYd85cYrApg3vFuegn0E2Fp1N6UwKHA10+i/ENS2FqGgVT6rQhcTFAx5tSpntmHP33x4KIH61dfQ
UNjSN1VIncKhc/6uLVPzqvVKzJYuKMAhv+YXS2vNA9YddITgbzbWw783bR4FE/hNEpG/i5tANbIk
yg5qiacIfFsRNcb1kBnyJD9DW2NC4saO/K7sGLRJOKadmMWtUaFW00i6YBDg/4FWbzEQ20W8W0uo
ol7lGbnVRe71pZqBw3UrILBTHKgAxkVXeL4m16tUVA39kQ4G0wVNPVDBq62f9z5AZ9YDb4dXPJtW
1qrvl1nsrYjGz92QVNnuqsjCKqgC4dD2/Z1SL57vXYWuPYQ7rBzFXjdplEucFkYwTPUg36Swe6nG
KBp02Ch2pOj5q46nSQxqA6tMuVOd+Yq3U/KaR8UqN/irKEkn1px1XvDPYVxq3m2n0QaTfDPchkLI
BcNh8cQiAe7Nyl1PMEoRToIQ5Cf0eJfQ6vEpTIlnG91gahMri+Na6EvYWGHPvKfmBPcDI/dZZFBg
2amkrUf26SOAuxTp3sLs75HgZsEPwOGKnHwDyIV30+iwR8EOYLNob6MsF0LJnSDyU+l5PG+Alvj+
ccI7W3VATGRP3A0eSpa8UnBksvlcF1xdJKsLHrcjWlzC7RrkHiqH6nku4+fv3nELXz3zNvT6sB7l
1Dnfg2uHcIz6VWpZ0xG1zcFM+vwRkdZmYCYUqUhJCzNpLeHwf65nfSFJj/f0ucoJt8fY/gQ4yNqM
2y22KyY4va+6wldPidNsuucclcbv3l6cEeLFcT+hyxPCjKcityahJp5Fh/dCcLXZGqXfQseeDxeH
KE00e0rS/rdrKE4oNWo2PvhC5kJEFh+e/Adf1APIuwz1wha3rDRwxeRDIGx9zMDv38WN16gPzL+1
+2eYCFPIHsfQkHvg3E2ufnf20PriRS5LtbKpwxXoXbTb3eYyzsE3axdre3UQECH3AefVZR8v9g/7
95XmRP9IhB2KaGh96CPJIF5poL8XrJFofkOT4fGn9zoXq2IkPwyY+DJ9TLsBBWaDBNGrCnT1We21
kbbpadwVBL55t5EDFcLrn4zW2HihzUdWbUZaV0mY4BgMmZJY52cFhsBa0mawVtdBEayihOsDsUDw
hJWm24X+naDT6mkBx7hoOrETAgleduAyT9uzRPobC1M9zi+LpNQW1Kz0PJiZoja29MF+NiY1oTh7
cU0JXrtH6Y78CnuOWih3RXDNgSDYS52qpg9Rry8Hx+N+7A7dfR7bWLGIPG+/1FOrjSbSBq7q+BPP
ecEO3KDFQoKZHFdprqOSPV+GBNS+/2fFOZ4yiCqAY3qT4WjtKfE9P+je52YKfRC2fJcTf6GVSzSz
Ld4YNd8OtGkQ+btDfHJ12///vSnqiFAauRm6JquUGaoiknZCaPwFXmaKPZTeyiC35AqpGkhgSaTw
gAdoqZgQG7yVOV9NF+lRk06oQF7k7zWcDurXlONJeNZZNNwdkmHW15VjhCZIXQocfwjRtuWMH6ao
fy/9CdNQR5IuVgzAeIxKjwdmLrd1pxpvNTjJ64+GPVtld/595aec6vShsx8Ogui5+8UHE88WSuyE
wxyFqNMI8keEU68suDZE+xkepWycXY7Rn0GEPtRgdsLCoJkoRnT9ugAy4DyU+uriY0BkLYYYJ8Nk
/57Vkl9u20RwcQ38xECRXUm0VMzN74vjgWDBERuHkFZ1qUCxNroWJfnXbnx2aERif540Q93cdcG3
socQLOkKjD+CKGEYIb3fVLFmGp6o9DEgeBvwy+mSLp2J8abI4p7uTKQvwELgN2qWsDSUHiQFtG3c
FbVlVSz0EH8pfUt9bM4v108R2Tt6SSPKlgohTIVjHC/B9RTlA9wGDt9PBQIwlqrlSzVaWJJXOh5n
oGqripWHmnVDD2rg/AkVGIoW4K3DXm3QalDs/C5x+s6dBk8agHsY9PEs3jE0NqXdo1fiHxLlEpUY
oMED+igXZt7/8xxDPeLJpJpbjF/fExx60r4BZikp6XoXjkfQVLpCHyT4bi1NnrDWqC1NEHBMRd5x
nCeaYAxdgEhUft3v3sz9SyAFwQtG4UZpkpl993rN9pZ8I80e5TUEvMQSJ1IQsTwPSOpyhA81VAbi
26p7NqbkWMlXOuf0A2mLfw9xAHVQX250wGukHsMfTo0YVrSGkxXb2pQD6nu/G5ibFoaSSX2ld35P
D+vk1gqSC2i9d7bGmGv6j5fL9jO1lXPrtgTZeKoWvb4qs7yK5/WIx/qoIM65y5S+ZXBO78bpSoza
DABOoOnvSzRcQ3QNJM/URDXJm9J4wWdNJti7TOpDXzuJIg1PFKLTcMyBFIS70JNaU2rIm5wnqkBk
+IStkkqkDvIjAm5hcY/R365rSQOsIhI1b+lxjBd4YrmXh0H3MvuS2CKAICZ+Tc0gzl3GEV5tgnrm
gsuFopTlefOqu4EGt2zqlHrQZGz/y2v6S2EIH6TE3Y0fe/Z767A9lU5lvFj56I/+4SqQbyUtPZcT
FcyE4UxrvtvGg50LjWPi8q9SEhW2BK1kKAjjxW9o/WdcItcImhGsrS8L0cSriiEAKv5PVJHIJROg
huRjkhOcNufW3GSdPh3l207uXhGR7DGmFxxy9arEJJ7yleOky8d8CFhx4mejtL4pZXCRgzK8xXT9
mgAFvDTPM4e1dwGGGyL6Pep1w2nqyUCDd7PvBBiirTr2KBZvSvnxcu740uiSFiUs7UsicOF+QCoN
vntpeea7I1Kn9OTP+dsmE1Q+52lP27285/nFEBu4iyOvxLlwKcG9qIAE81U29Ah6TIQyt285z0LY
kQ91eVNjHGy6wIt2n+50dSDFb8f5PaMxaebOG/7cSr1OXlE3PVngB/96xpEMe4guLnGttwcIFsIB
gSCecvYsFvZIZVVi2gaWBQ5zmOaEkMsu4uDmTgXQGJ3u1Y0tygNwmDWdwyXYNDVTfVuThOvgWgr1
L5soEdK2SGo1l5XP35op0pqA2tZm/trbQEfnlwpenzLvZgUlz0xJTSsiWu6F0kXCPpTORNtjIO66
aAmDmZUUJLx5OpzFDq3cd6A0/iG9QmBZQhMQf1zSI4Ogw3SAYybQ84B/A3Mz/lCVG1UyfthpwM5k
55VfT/SbEdAbowbc+KVWaaK9yMPKEZUIEyYsfv63g4pJXVYlH2zhpmxmIqylS3ZpIz9GB3hy8nI0
M+JrGX3U7bBjQgYcx2/4V2mT9fB1yQbYR4UdY7ukfYCvRWc0omMc8xyGI0XBmgx+Uv5pihDChlHR
/WZgJyQSuAjHt9EpvGsQBEXLbpoEUuKHP7YOkSSvwyLNr9gZK+7JQLBycI2ya56jrdfo0u1zMOG7
RFl1S7xj8g/mfVlhpzw6hoRon1BpcXF9S7owhVEhpfNPzN2iVU+hNnhv+ByFLd69YE0FLoUU4dBi
mtWRf+WNHcFDJbuDok66AcX8d+m6vyzdpIpGaQqQSALkR6HGHbATs3jwYnQFKs684Nwn6TTWcChm
NKqFiUywRybgQ8s56vT9lN3OAVzHcj0vq4l9EwQ1gWc2kHlVpOXjBWFTCVmyqW/P88imwP8nndho
eCmnZzW6UzIrZv9WhUNit1RbHqyE0LaTkOhn6ELaPETrkYY+FA333Qr8enLts7E4DMCHvuk7dgA4
UWihqhNfoCh4bcohnTXc6sQs/CZzkfnznAlb6d3ci30Oq1MlUNteca86mGN4CUd4BPOkglRbKTMj
S6VFdRgdhCsrKvS1MxQswmsYt3NubqQyKCRRSqCPqumqTRG5nZ3TO8PQ5ux5DULpfR+sv5piA1Z+
moEV57Pzzbk3U+uNzmXC+8NU+DrqoyApe6Tj7hmvzBnOv/lg4C+KoomWjkOQZxdHbchTjYHwg2DI
AwjRapoTsijLLWOTyk6AnC83XhP0qFqikFmnypnYSELjCb4ayuz1iK3KYBKSuRofrKaDF3LqYypB
IjchI7u/ZvErFuMN66M6kAmqN0UtE0ZccNjlvmIwbny4FgcwUkbAwg34BeW1EO9EbfgW832gWMVT
X48quDOL6Mgb3/rasK+dITjrtA1XImndtTgUaM2kjYGxqmyxchz1z7+1TxB6UfdbmomO2vKqBYFY
i9JmVxf6EkgkzrPdR2VwVKOijy54AxAHW9fy+s2yXe5U3ZhPoe6W8Hml0zydrMQeAhvVWcDqBtdh
hyxIB69G6kEQeU9iL1DPDM6U5a17kq+6aW6+EQXEeNORUX5izGL0+gRz2jGMC3hJYa5zbSbES/Q8
WMfwlAGCQWxCOD3Fok+rYwVy4h9CaIS1+KTtpEyZ2H5TuWhItJWZ6hbh3D323U3ZWwxHDzJOiZSj
hkNlxyE/SdjE4lgodD2jlfHuAY7eMlRvxxehib5JqUux1iR31EC3/FOWHvpj97znx2ZO27NXJrWr
6ouxadOY3sxYJp1d2T/dNndKC2XhjpO0K/T/1leuip7bzfo2CxRRYUuD90ABnJuRCXmhGRpy2v9U
6dkyAWHMcpfixr2nRQFDEKpfN6NGvGa6gQjChcF1YJj3U3DIJ5tUj9I0NHJurFMLXYOIkvE61nuJ
fx6YNmYsBUbRmPdG3gMbzPlIdsbpBE0J4CGauV5eI9VKLZy8qhD85zco53XGqh7+/kAItnjY6dgd
4VZo+SW2BvlwGA++yefXNPAgNXF+AAUbQsmB/hMbstjEFyGKGrCvSYNPP/cQcxd03c46xg1vrQeZ
rNROJamJNhRGEbxD6gT2Sny1xea2Zv2ABjz5X0EebKCfxZZnU0OqQCpSG29Yv4aoFf8FdpMgdhA0
tt0uQufjuIwyGXk19jPz3Y9FAA/jexzJNZeNzhkCkIwwkxjD76Jr7ffjTJiz0dJ7aYV9N5FG71kN
1du0vDgPwc8jC/cF24KBbwZoD1kOK+dldfujwA35hgtdbd++7xlvPOUbNtpKnJXgUUrn8YeLsqwx
OqoK1YZi05vZn1sENSJ3M1NuIML4XS3l0FzjA4NY6QoMspA7Nd5StRXsIhpcAR2UNBAhJlX2zkxX
my+HVOczmKcb82+MbUK7XNs1UTNIz/zLR+AW7/ioPX0u/hNAbi5aL2nxOENfaQ9TLLqAQK7lS5IA
bYYN2DE6gfUdhkyGU74Yt4McJpS7EHeg5nHjySNJAmMfT2Fs9pER5gLileAHLwsqF3/96B9CIqxs
Bw7D1OZr+QGxUqPdWSuNqsV01ZdZC7D6IW76sruf63w44hbDPBVW87rywe6o0kpVMa1Ci/YqquZi
hXf47cgmZLrDOYpC8X5AB/pxhBGz3+RRvdvSkCWQWGOEGWzevhp+C7UmZhganxwAbCPT4OXIibu/
7vnGiTJXrEP/5tmty7VDDg8xnSpzv4vHkZGRcBRZlYdtFfr8NDVunTmBFYDNtvIICU6efe7FLObg
vfYEqiOkT+ziy9bg6gxtUe2lOlXDeZ2jc0G8ZzmUE7z8S9fsJL0oY6nySdgoDFJVzFKDzSVRpmeb
KJ7qmj5r8zWElIgIgKompvBm2rdHf/5zxlqYEnRNnkMVbi7ecVqpGM+f4aHAIO+kifeeLsryToPM
BRs+G+cFK8uwtKOjYAWtBYD7rV0/NwTny7b1fI7+HzMWxxJ2hlC7dcrQnLER/LlQADmZql7SGwjS
HEOahRB4JE0QP8X5Xp/0Q5C41i5FkKfznzyFKmTkDU8vf7ZuIGrmJ+SNPG29F6KkfxUxl4inu++c
7h4nY7zROQGR3dIt+ZUIHJJtdfEPNRsamWlV0NWm93tfFF//FPMIdI4ZPL56EOj1tFlLgyet31S2
HsRwv6HQbIAUHrN/VzhOIURru2cen/HR9jY4AzTa2XUssaynzYDFkU+Obil1JX/jHkH7mL0qGWdE
hnoU6kgXNjYAU58qGwobutF1g7xQAwMDwXzdprkbC9FozeReX4qRTWHC9rLEhrs0EOuwyDbM2+QE
uPHVUgUz38M4IPAa2xUKRwc28wLjnR7rCOcbmqu97al5pd7rFMWb1+6kPJtdTAoz3kTGpiCboLTu
W9+p19YZSmsNFR+EUO7ApUAXYJttR2ItIpyEd6RJDuGlAt0gZ19/dZsF95w1Zm6nuE+Pf4gNGB7+
jS0PBYMwUP8lMhxfL0JtqZINWeAO6ozv5PWkZbmibNVFXsphbiVyJ/klRo4r2es5jl+6eGj759ij
BHJTVlYJmpkSaEfbN+38VqDL2RdOqxUeUZian84cYiVtx4ZxEVc7/JgW4QNn/BQZYkzhj4jD/E3B
AgMnuDKK77/5oqS77e2iRuvso18BhLnLgAzauAjj6Lv0pQzISFz1DdGD7seSLBC0psm1B91kWqNx
a0AyXKup0Y6CI6NU2ac61wQHrZzbZ33Rmebnc4gIk5ni2JsTZZTDoa9z2fn6OrES4iYXVsaa+xmJ
IfQFTvWOtCRNxFhDXPIT0annNtHA9kxtahDqwGXZu3/PJozpKJPeyy/7u36x4JnP1zsh4ZHsokGk
pEOo4mUhKlR2L5TWz3rU/pCeYVyY/fps6WfgPgndvaVaOlpiZEXxQPtoJDRoJgfLymXVT1pIj1dX
crbvZiEo7nPMhvnoE6ai+8qmmIY+oo6QtsQmrbBk8wbITp+6+VkL1IyzyWccb7wstnUUHWyT9hPL
rbYcokhCGlMP2dU7fT8eihEnHvPRXvjafMzOyOXAX/zclcOwPPvPa3lcT8GCEGOQb9ij66ag8pLB
qljZzIiOtB5qANxGETQK2RyOOvmNs+N2yN+j1zq8NG+1syd7LyZyQ+xnXt4fFTkqD5t20sGQwkf1
qWmFovOSUDIw+Y85Wl5jvuwQtpRoQ46IsA+tsmpMC5E7yMYwe5O++rs1ANyINyxDpQwZAFk7BCc1
SGSU/YOY8TwuZ5hOmCEYzd/vsEC5zQzBm/U4VMUev7IC335qqDc98fFm3olQR91R/ocXbg1Zjs8Z
vf32a5LONVmphJduGAmD8AenJylu9cUttstftOHOQs8Cq9aylBAWWiV/kNeP85KfqEGAPgBJGHM2
2ta1A5Qsw1UuC59vHhZlcAlx32PWYlLJSGRib1mrM0o2r1Qcl/efPr6h1VNfd5LRBAJ2uN66Sq3L
TRuRtM17rSyTtQS5+k4jmdrGTCok7fnVuCFM2R36f8eEhos9HPDTh0pPTwlxzhFFGxJhgCgFcliM
Es/kyTxRK+QMqCH558jouuIbuUVM6Gs3ejUZbhDQ8rXI0ntG1pQKmXlPG7bt0DGl1XEpxegKXVXR
ZErVuMkJmuOse3kMOyUu/8B5ReMp/Gy5ntnNPJhicZhT57K2FpJXAaq3YcF8ZTmLPbfYa76SExoo
fZEx1O7ipEN98JUSUIsQ7AyPbzeQfLLxQax9+jHjCKroIfXStou0RIl8qy+xNr9p6IvbAhdvB/HX
TfYwQ3aicnWLx2YXzmfvEyXCuz1vqOU4+D8PbBVS7ogLWdh+Uor96nwgg1Sx1TN+M6MoZi6yhFqu
98to+5YCQ1AjeoWujWWN/rsKdENxKHtLynFoPaMNjXEanpXFEz04xa6hmwWn99VsOaJSCBz0QlO8
L67cdmnCD6I2zwCkGjIuBxuB7iMAS4Ou7+68rsl3nDDLPa8LIufZnZ5/TEdKcEn8/tzwQKTpDrL8
E71CsswFQ6iuuKcFijo08ixU27kZ9XBvZLZmXu5NMy7RvXHBFyeC8qgUhQBf7EZonwQgrB0p2YKX
j6TdwwkJ1t0VWAV0aQ1aJ2UD9dIctQGDwRBQd8CYcl0U3PV5hQ+a9PD/rtA3akR++mVdFjZuoHzy
rg9sMKvYHVE8xhQH5qfdej8KJEd6mEKmH1n8dr7ItB3hFAjELz+0BKmUnZ9j9IUYtFMEDj03/1Tv
wGyOTOw+pcp073oS02Hydb6CVpKdPz4UaHihUDs78uRxWNS5X4UgT5K2tWWvp6vuXpUiwbhsMeTE
f33P1g9q7P0foKdDOLdOc8Gy4jkEdbJOXevrW6LLZ1NskaILgXrcZKxDHMurnWl7xR6rp7oPjtY0
K7NuvMuFoDahbuWzbvZ4k2DExjE1QeTCVxFRNWuqO7KjOfUWkw6v/mIJ0snRHlY59KE1MMurPnBt
KfkmbUYmzDrrW5+sTxzd+O58QyX0cLeayUMvW42TvC3jpSWA8eTTrRT12q94QXExYtK7trSpM/7l
TMfR1TbI4Odl1Qmg1HbAb8NB3idfnRpO3PuLEp4fX1pnyI0iKPtmsSUSq6WCi7gJo+yYbRAQU3yW
FZUGxyJFAKTSFmzyRpXBy+rlqy3tL5z+nD9I+iRye35dKYYFQudzxTd9QyCrp/eAYKzi1OPgAG8W
UDSY39wMntDDYaGGtcqnyzRXo1MLHa9lMwEmlON+1Z7q5lAWD5U0QB3ro0i6KBr1Kw+CaiTn2gsT
c/sZGv+0tOHxvgtIUYTTCpJuTApGBrRHQmZVeB8t+QTDg5DLQ+G1P7Jhye6mvqwqxiQL3njHSvXB
AMt1VbwFpXsIM+vU7t90g0wnCplC2u7Wc2YBqTTt3kMxS2J39eW6K/MTmN9s+/bijKM09hpCm+X4
14IoWn0M71rtNcckqYKw2nMVNn7flDwuj8MBYRYZJFS1Wq8habQ8MignQHRtwRlaRwhejapiYhh2
amCbPEmCIaBf/D+5S1dQzMyyd/0JGx9CeV8Addu3lrc7v/8Oa+qIEDfQV1VN1dVJN6teLlgclQaW
vg5qfZ0ywnzSbTzNb/ayfy3iOJWd+6a2LTdBmu5xn2lBXSPfDatsy0TEURMZXcoX0oCXX9fpXVEi
VzN1S0/ErESJuXPZS4PHcob3m5YH7gUg8+Bco4ESfYizNaRX5hB6Ta++95zthr1FAIyJ87rRQQdw
9x+Wb5n9AAGT4IKjWfPM30mzy76e9wvEVgFPxZlZu7nrUk24Et3C9d5HeLpTEgyanHrw+0CUeCfB
kvFBnlUqNq2+pNCsqtMy1MNqLmMK9n9qdFnoD91+YoVsiSAk7D6HEzMWFBEw1Rj1EP71KI5T/6O7
qaLlxJ5OPgq1sRydOzA+Tlpmv47a1zsCE7vDbg96PgZVLSuVn8i1uRI1O423bVBOzuB0MCHIDD6V
bcd2EPDN7HTStohpEzIgz3UCsIJ+7xvccmiBkj4EW5jG78F0XiI1E1koBDqMnM1BI9LAvZDL3O04
9czanHzhdvX/8HnFX//BB7TGRnlXp2guELwfWqKbNYP+TMEjyIm6tBGAmJatm3MyvBcL+yi375mn
nMP4GztupOFWhJ4cLsXNdPV/b2HUJeRrawfwKVeJ/Sxq+rVsY++/dcfNCNwxWV0EWajUMs53VE1+
k0pas4olvyuP+lZmXwa96tAlCeX9xgVnV3QIvvvUZ8RBxvYtpCoJG1QWxnmgKrixBvGrmPZfuo/p
BHQ4PepPmqIVXftf5Oxy5RJbBbkm/XmSK21aC9TqSePFFkPTb4rBrYOwM+07IZsdJ8iDmjKLX4sL
1AqDpPrBNgZfcRCpmpqaMg4ypc0tDmN8lHGevShOVSlGZZ2x5ERvC1Wr6xrAHqRFeBipet9lJWZg
+M/OSlNvLgtnrzhXwMzUS9J0vsWJ2a0g/gSaJtWq7tIJaJOIxqMtXzF5SzyZxMvdNvM9xpv7uAVt
gTz6bwf6wu7+18ohLLcvogkybMBznUpLkHqAhmWrzapHzm/D+zAup8kv2cDQHlPTKdcTvF6NG+tK
bRrmahfF3BSsxVbV0bNU24UNVr1BH9pSYYbDSP2C9KxPtOg0Dkl24v7ix4XfneQj9UPVEDVZEEwY
kWthW+qdGlKAe3C1oV39WHdpB5/jtm6sggprWGxnYVMaWm6q8rWu4gGmp4XxCjmMyFBpoyjYm/8x
eHqKL82pE2ZjzxCkKMdAcaYHemiLJS73PAuexOtN2qCFRbzpHekOUfwyzXsZP8bpTX4T1tYKmRE8
vIsQcxew9jaOM//2qRoT82vpB9lZDFODozrgRw5kPJMyH69L3+fnQZHUoGyQKevPbEuCtO96X2nd
J7hZwJDTx98fCtvP6yMTfmlhaNV/pi4ytxYWi2gLL7By1+tayIiUY8hwvKnjmskoWy+62Jk8ip0m
in+K1JuoOknK3kEaIr2BhyWXbZW21jETTFDrafWpeURGQi/MSr5g3tpsH1oYYabdUu6xSBYoF1mT
sdKjqNGdRH4ziCxMLXyLUx+KrDbzzvaq33YBiV5jEN+VNn4dSE0RX5t62bgwrzlYQPQgOkzSlnsp
3Q1JbwLBkvJiAiwfD7Clh1PFOp2X8+yM3cWYJ6ybEq9+AUwZC+UcGU4cSUUVLvIftbkf99zf1QII
5Q43f89SUwyY2YEziMLiVrFyaHYJjIyXDuKM0d4JM9UYQAH2WyE6FA/4/fJvYWxyoU9zG80GtKHg
rghFbn2sfJrSNcRLipjP51Mj7Xf0VjccJKvJR5E1+8n0MaZk3qb/Kr6YsDJvMqqIox/yrn1YjyP8
GYtkYvt9rzUHULBp9eD4JRjepouRUSq4h1URjtrc8ZeWmOz8Vuy/o0/oZZ/N+bb6SCxmp+lv8oBS
D8x+YfE7Ep8MfW7SngI+QA3NnvymxKUhdH6CJkqY+/32OjFXhF/8iYKilBBYu6v1+Wq6re5kJgl3
36o7MBI1SUSydxtrVAtwHBnwbUHTRpwmXmMgYJCp0HrwmPujSXS/oHheUZAH4FXRWwhWyRNaCsr7
5c+ZRJgwVpZj3kgtIkdSfhbBz4nMFypgG7/lWvAX2UIuhBRPMVNHmKjnl7eTbjII/u/1PUJbdMlP
iz17Wxx8lYgUZ+ZSi1ajH+8sVYzKhzhgW0lnJmtY1x0wJtoMw0Qh2hblDkXl3EWtomJchm61UlRB
qmeEGrKuje5iHGHo6GjlKfyz3zsl0BGAzSaH9SKqhEqpNfgp6W9ddjLUnKgzIJN6pDs/4FD8Ej6o
JZiv0+FYJX0bALpFtRvvktcO+KIyMAmdZTl9uTBMI9b+LhT68Pxr3Fls2KX5Ygy9Kv6yVPEsFGJ3
n5VTgFYfIk9ehvN5xpcxmQnkQguHPQAkK5HaOm7TWZ7h7hP9kd/FyDY1oOvynYQyxuUxZhGALZHe
KVBwAUdu8rwtqY47Q6xLgeSHHhtdFQvCmnmUfMt0gSZ9btEtV6vjP+G5P4HxgS9npnkETEfBEYew
qsUJnQbRvk9ZedGw2MGQftN1AeUctv89URu7symUa6PisR9RRbw922tzFi0C6q4J4rPBVA232u9+
QdRmhH2Vo8LLxDZfO6DggYE0g65mn1QmBHXOEdKOHZqYuSZrqpxHKZ73MhkoCOJR2waNdGo2No6t
gwxk5z1rexFDBXPoX9AOa6anDMvMYWiPrQUGhD4lJZrt+Iv1r8GniQDePnOhrzCOKl5619RkfYHs
IxeqU36dmMZQNeZVL30uBd6BO4/8nBJJxbrH0kk4vKEOptIS8P8XwXpiDivW2NR6Dcu2OhzRSLmq
7sULpfYYCzZmgG6VNCC8oImAEyLYWkNEVac/EkYL7YIyf2gTPPmbfKBs1lRpxbcKOXj6PwY8RfWU
wai8x2RbkowaETPvPJGsvaQcSfBQDpPu8JG8c1RFwq0kWp/s1r6ifmIQsWvBg3PHpJJu61AH1XfL
y2BvSBXERnZJHCz4YxBpMTYhk+sG+KUPvoRYlaOt0iQTkxmsuBjaj3WebNUaMqOlYpvhfxHAbCT2
RfqLPOSKAnmiryCairwTDzWLTv75JnEDKYVXGzB7RBgyutuamV1j3b2CreKOwkqwRDjAlq7rcgqu
BS+mDT/Q9cpKXcfEJRjU7eUKgA710YfBLDuvHBNPT7iMhlnLJ8ayspf62mkRoKwBwzpFOA0doy7U
UhY3KLsDbJ+nTU9Cp6+oYQYxLaQd9jznICVyRNJUgEhkmZh6AwrodIR2bL3zDufwS0hRGPURQORb
l69FlG9c/BiCPjWcuqNsFbnTO0YSEI+1elRpJNTlG/CLlYo2oLfGUds4nQClEyDosalFea+TS+5X
4v7/hUobBdNCldrtvFIoZzNcC9CNExTe8+fkZ3ttWIxuk+CiymnZMA04a0dPz+j6Y+O+UFGhZdpV
fPlZ6BdegbV+ZEnXZiuojivU+aa2qTKYExKAIn1aE7NGU0k5wfCfnhHoAPFwqbMownezklXiYyWr
2/eP5e+39lkN5IP0GbUc2hZT7uVwwKfWuEG+l0oFl3i8hqXsRVNKqwQdN7TDBTSCA29Xh+OxLiJ4
WIgA+mzhsrX90IbPP89mWpqGNrTrK+VzxBZJP24hyuDwMRCQhAdNtbKgCB0iON4vvcAK+LLaoesh
MA6X8vFLZrNMkWFsai8DFfW8sdaRsHDoLUhZFKK6tBCkb04SdqdRjva423jKPtYVwVmaVnf8WdXt
NfQmhPu8qgR5JkxPEF91mEhK2sXwnMTGYtxHRtUcnihFxN00rQ49D/xZPD8CtEPxPwtztZoj5GeP
hFhDVvA/oen432znWAP2itRFZxQd5l55C88CP94l1b+V06oGWd/8RQyZ/E5L66ycZ80yhGnMCvev
Ve1AZYsAi0E22+bS0N2/qwlwkrpN+z+vI497q8INwTWkqHPtFu0hNwSYyf07KTVAMSccvzpJS4t0
qIlEj4gOd7MaJsaWRlhW5Hkx62bXxF6c6wUDSO1OvqHAvrWQym5M4l0vquT4KlpNbqLtxa/iJD3b
0DfPXsbpOGAS5HoMA50hn65ZmGKDJz+DsULuMhoQBCOvH4T5SXUUwTbSgCOpgPWWiZKAEg6kaw+G
IwU12885XsJtpeNAKTRewFgDGkBEzX8yyLgjf6FqaOqXJsc7X7vXX3f4MLuBhSsNY56oHALCMl4V
yJn0zu5ob+vGwooJKmCq0LMMIV+p6VgiU6VcQXVkgSR6kdKWLKNjUDSO2KZTwu6h+zxulLS8TQP4
+/uhVAjR01v7dNJRIorwoijR/oGLd22JkQha+qyb2bSYWkSqQ+SRsVWvwHnExkismrmU/SKQI7aJ
TqrLZF2B+Ry2p1aqwi0mMGmR3CVVXepEyrOMRnfZltd3D2wLO9gR2rJcYsoo2B1w+D8PYFDOYTQn
YJgJRQz31Hq+bMuGJ4JuLSHfK+d6N0PmB6q9Dc6jPfuKVfOBP+6kI7cN7N3E9SHBJ7VDuXCT7OVH
YC0z6bmI9nRW1+Z+u+NgZjyc7M3dI1MSGY4aPH6MeI29g5hS7rJnPLvRfP511RGO6gPNy1jA0QJV
vn/0UF/noafNlPud+kT+TnSk670OFSuHixsWHt5DMk63N11I6jr3/c3bX7hgCyq46UgxUbeb/7iD
Ggx1+TV/BIz+juJirHhCComVVklrj4PWYcPM5FhyjRPx4GqZ7uOQ3pTKNxFWc4hXPPdiKGAjz3Mf
UN28j/ryWPJZJRJ3/5Lk5QWRv8osMDFmmSYff9KxJ2H/C4sWhyDG5iX+O4JjGyvEiKFKz568Omfk
S6i5qIAHQ1pXkukrbtrt9rk6ntNDUlLWqc+bp8aJtNFjhvidh7/EVfuwGKU1ab2XCGHmDF8Q8Ibk
gn2b0owGkEJvIJ4QRx2JGhIzHG2KJo2fxXDYRBIgveOivM4HeO31aZgsjfc3POM+P4GEGVPk2+tD
+3aipEYICJGrlGTpBTw+Rgq2Zy0uRRXy9QFMfFl/dqr3y/PR7MAZw4ke+BSiTjpq77UcD+ZUHt/o
r5IThMyU9uwH6hetHqkcb1df8JuG3eFWuB/9lUJmgXl7jsvAACLazrXb4+XU3+SQ+L/u+FQtCesX
+lLV/nJzuVzfIIqIIPkKYOSm+SA3uZ3KQbreWCRfTQhoW6Kc1zyjL/JR6mxsQNp61z/SuaYBdAn9
Qz1X4oWyhtGloor+1kkSUr8NCZ2B7PIF+oElyQPGbeVlDE/0iRzvYRDoBbCxiEUb4MtjJkmS6h4b
geGMTVWGy36Tg7N4fL4qZt07qp2wawuEmyr80U5b+4gPGjpoZjTgBWINokTAEQweDvByx+DQrLP7
TkQGJVR8uS8jR0OMfuukcO+lsAgwhYFQwILHZFOlPRIJwtHtf3q5FWMdHGhm8IrQSHgcxY2lqIdu
es91AyqcDdXd9lfjY9Xfj9Zf5Uu61SGXRRzwyxDjEu3Lnt2oJSp8clbrgiclH6n6IXCYcWor+/gW
xdbWP+LYsgOlqiwmSDhtTO5OHVtdZzrgMhWq+gmFbrxrbCTS88aitOeaPqXgXULJgWjqMcRFxKr2
Mn8UYFUjLHBLrHNBMD10+++EquB6qAV+fEvUTWxUjvyqdboQkjCQAlSkkLwfljDXhVd6YrNvPFof
qJo94bmgfhKX6wolRW2ezoUU4Be3x/WiYKiWvEHkJHH2yw3yS6RBGwBfHIoVk2RtkyrZGHwSpjah
SlTJeBHM57pEUnYoa5Q4zTPfPY55tQZ0Qs/z3Uef0RnEB2heoWugWNUwf5Jx+ihciCxgUeIkVpyk
a6H/RqOxUfeTRgG80j8X5zeFobbEEOO+hGUqgCNkIQkCBR+awFK0qP1Fgj8+pazgEgU6KQ+PKM+V
nNrkB280dL0dPBb4nyDZun61IG7nxz46tryJmOtitDVboKADwHvMdfhPXhHA+2HHZOSwh608clrh
27cChwROmvp8kTGMk/PXaQrA2cAEfFEBeDCks30vcYvTesb7icGR9PmjlGamYm7tjSoynvfMiTgY
4eRlt9zReML0Ey9rARUfPTKHQT1y5QyCC9rtcut0dukTJDOXlN2hxk9nSdoryLjQ2/0UPB3BsLym
032qQZQGQuvUbpPvrB3I2shODi8djMcptvmwRQ4T25VWHIgicrDPwe5HVEy6I1gTB6e27eiuIfuy
T7/raNKZt8GjeiEgGXwsTvRw9qcRI8XuPTO7qjowfLSEZR32jQQy11HAolL9v+OB2vvVI28M9g5Q
Jf+E3z9p5mhqd4XEU6GaTS+srdsER+oVzOUcBsKWPYOyccCdRkqicS4QAmwm24Qlx6Do8QaBoQSk
+S+g2lJuDYfUSUZhrOJpEXiI4tq/q3ypx2azl9mgpSZzKKysFsyqBdjBqT2aAUx+dvK3VLsRZPE6
V/7RWJEkbliJz2suDnqHOhySLJQEu+V38UJSgdCr+5D4OTZAEwi+FT1t88B9tIXDQLHFMnQJOLd8
amCnOso5CctFtxiIozoJ/cyL+OQ9J26+MLFgvizEWLv8yagQJH1m6T94vktq8bAVV2fgviS8EUdd
fCeqh3ensVnOcZJpkHwNGd+d/eyT6MswQHJXHSI+xPT8HxTzmt9LL9/Ld4WpvmJzO2vxNOKY/VWx
/GuUpOkxS9K/s7nMaLl0EkjEeN1PcJAz7nNheXWcejP+ZHG4ZeyLJz9bYiLPc6DKjV86Ody6xu3O
CW4Rgc/US6rC8mOqStDUgMNk2ur+PU49mHfUAWp1F6aI0RTklPA6NKadoZkzt+mAtdhUMJyjkqu/
jLQZATbezuH4JdUih/8ex6PJ5UfA9ynSmpdgY5/9es7oRtBjrEWXok/znvEtrpI5Z1UciLrt2N6Q
FUpRXV9OGvBKGqhG+Qog+wOMCD99BIe6sCwwS5rpGkbXU51xiGeFZrBJVHvjS1lMZrGPFj1jI6vB
tbpmhRogeV1kjPGFf1OauxJ4SHbyaQNl88EFZnjQcHLl6rxe5E2IoGHng3AM0VH6ktm1FJySsNBU
vighP8F/VsWHcKQlWx5+yNwYWVMUkZV61awxTDgM1/B8ZfhrCPbqzDDU278P5Eu1oQCaEBvUW+cZ
d0RwGyyrWuph/5jH2gmOjXQ3SbsmE7QE+2kfg8xXmjAQBNOCHOBdOINHMWuaHjsfddk35IXxEue5
x/tCueJbLhLMcbspYq/7BrFll1CAFLjpgp5rwYfK/OQFbkqqhy2TsoXuRZv8zdCW+1kuayDBeQ8S
SyP6YnAwcvMK/xfHIPP+UiF3/FU9juboiIZBnv7dUfSs3w4LcbTeT6vDDhT8xv56uEQNB5RXSr6r
Z6TDx6HypWo4aaHe5zyk29DBVNfCwxm1/6N1mvoOUZGez+v4pG1vHMgLWKm6a5oFEiMLeuaYVCMg
p2AyTIRqnniVyIOfplOAKOf4D7wu14PhC8KquuYNwrEeRkfv2PjXMMrD9qkDmeRXTIlqS/rblubs
gB4di+qHHMLkL1uP0an9kJGeyQnmvp/J2ovcDo8+AAMz5bn5r/a6behg5rEKY53JAqmQifrrxpfO
8h94+k2fwEL02OEciBIxMsi75vPtr4YCX5odZRptEnVx91pjss7H2ehQ8MSOIUtW4cxri4qg/XmQ
wHcN9Y+XVneXxJHY5HryiwhThTvmcaoBKkNm67JlS4J9HgX/B29Xh0cXOPfDm7tXG1quV7OTHpXR
UrTZ1/jg96QnfSV/62VxU3lGz7tzldVFGZ0N+Vv2OgBeFwRlWMQ0sm5UzWlUPiKyzDPh/vIvkStz
/J/tP7y5C4wLoSwVaCnJflRHjpIW142RqHfPclObZBvvrcxH6BCCtIyEkPudpW2ja0n8C/M076M5
bJHotJga1L8kOfv5zOghPX+5SaWSLFFgCh1uZyTw5G6f2fhV/MZAvWfyNX2OjYL4QQfjSYmboSc8
AAoeQ6EXyu9cgekD6ASUhII/cu7ek/vSdbddSFGddkq6jeN3VAQmJvgxCLcqbwNH10mg38jxNa9y
ONRReWdM+6sKWBn6OWxpKVfLYbnHpw0/EN8rYD0Ku8GUuV5BesCDRAc63kJtRlw6WD3DYdqhHLg+
dUg1784xPjdWWsB+os8v2QGdNJ5odWlp9wHN75NME3k5OOTFjfcVBIh66O8FhSJazmWvCKEYfpWB
/DpZn2KOJyuWZxI7vag+rabK4R7q7dzdogrx1dQ+5EnXeCj+aEQ/pZlwO9Jw7wuDrB6PXcCVm5qJ
vEGSevHvGTpCwo6OM2Xz64DnPPPRXEcSjEbMfvv8tdQ8gEbHiaH1eh8Q/qFjaR4JnM95Gj3NbPEC
bJ6GzNdiKhKspVy6+qZrN5+xc7w4gNaSwn29Le7wtUy+HtDnD6BCgb8NNvx6Ca3DFLA5g5sEaG7h
1D+e2/9v8/A93D8KwMpvGBxEGUne6eXULjMyPnQuHKtltNsHAgxvYuXcpJPgC/pEPQLMhMeGHCry
bDVVLYWwQCHv957Jg6Fb9NRwdXMtCxTz/sFpocY/R1sytIul6L/1J5HmBssygExV69Vj6MtrG/r0
1LdUJwpifoUHdEEyJ7JIT7Kuo8qLJ3ugqVYXZ8wq47jXGcZUbF8ChSG/wOLRpbFUaPqjARQy6wUu
d/c4ZaJ364xin3HFqTwAPi/XlG8k2nQaMbHT2UCXk+Gxs/h4891FMhI82/HMGBdMVJ9q+k+MIoXa
lWJndlJ7W/8CrvYU9Z6GcfUPBytXdjbbva7laGsbej8OHEh690/0t0pzqZJKLyMP8yxOSuvZg0xX
NNlSfotAK7PRgQT1bY8yL6NBjfbmFm5+53TXpL8Fd+RXgCwZ6UM1LeUlHz5Jz+3nShx4uYodEdWm
nXPHGcWXpc/5VBRWrlQI2Rp2JN1Rk4zkHWqWeVY5xAMAfyxiu6zZTm31L9e9MzGZ6fHgBqeMhsKk
C//SHmpOta7bLsuGV8m0949o/k2VLhTAbGPy4Q6PGTf9f9u2a1hh1Dm4JQQDGqLq7At7UoxAImZL
5Nr3u6oy/+pLAQiWEtsmn8QFd5m7DzQ4ceAegW/m4sQPgTDSX5ZwMCrJ/0R+ZB5C9sPGF/Tsnn9z
YE7EWM+Yz3gePW2ChxId28d5VyWUpkgJIPRVjYuKxQ36VkrvgcV7H2h+A5KHJV/gP3NI7kjzic4O
7J/9xGOhTWFARFdHEMErK6Hn4W0v6kHgC+i+CVlIl9Vah4NxOmKlDVPngAHXHRk+09OaErSegfbZ
4WMLWgPQfNj0rfPosEOee5iF9MoSN8f3Gevz1/TLXQ75zU7M89mv8eg2/eSwxc8lFK2M72OK1Rb9
BgTlFK9Sp+xPUzVlcjPFkFK/mpTxOV8dnS6yQklC0H4nt6s+kqU1OK6eDEDHXn9TOto+w3fmU690
c59Ohos+3AP0eKtUU8uS9L9jrscYjQ8FuQU2REizq0EBlhh/D9dj8jLjrN4BzQEUAw9a0bgN4zxp
xymrCQzyfsyzOUkzg2H6gMmW7aY+Itwv0wFlPY+dv29UxriacV7Roa5x/9cF7EGetnvniK+U4FOG
XrYHGt2rC0Txn41o2TVDEHcPHrDjRQ4ZS6N0CsAPxWKsSy3XW3NxYcQaI9j9LoZxm5Up1hYiTuV4
E/gZeDQEHkR99BgrAMwFi853C552psEj0l5DInUwPST1X/j2wkaG1UujUkm7+tfUBaffmcnv2UNW
9K17arl2bKv6K8GpLTjo4p7BgcBxxcyqMPkR77gjTZjtuIE3J4iITTTHgeGD4CaYOU1QEJNurXsL
Mr9cQvS6n29qX/dvqNIc4i8BdHA3aylnVO/6cJH0ef+ab7JNdJ0ahKSjiljEFNqDPXpAEKwmZRWG
0G+IenMF+l94vFS+vJ82WQecLCu4JjLcacdtMy3yzjCmXneAqL9fHmLbL8DnvISCf53tJdHQ14/M
N0D0k+1uuE1cDYy0IIkOXRd4fiakh0crREjjbHZud1Sh0gNR8tlIp1B5hR8qQrqvjyLQM2cIYcTp
3BeCD0wz8MH41jcHeSLPNY8ni/Ia/wjEaf6ibNMlCvCoEPnqbtLvPZko5fN0YwKkzPlIzaTGLi4c
RgnssEGlayN6IC82ZQttghJhLmvlJwUsGIaoE9q3cx7sgb1wRmR/xQbcBac2dvlZG8b0aIjr6kYx
4Xz1/4Dq/pKbXLKpITsR0hkHKRC35aY/6EHcEtayv+FovvgqSL6b/6uY18MXQY7RN0HZ7jaAakf5
Yvl/bUd2wx4XEbnibR7ZIRVKRiqwCY/7gOYFIGv4+j0/L5e5RMDwhLaLg692oreEhIKh2hxPU051
18eiI6RlsYqhXbUT8kWiDtelU4L5Wfas5ETZVzAkATqqKVvNfxfup7Hk+71fK9okxLoU+qGd0yy8
bFXXW1WSPDv/CS+ia0OMBAI6ELLy8pgvgtgNuIWxEUPNa5IESYwznzlPplZY4DdQ3MRND/Meye+g
36w02QeINPz5KL80FjUUEnKEtNOCJZrsRlcaRNC4iMD60d35oaxDpWbhcv8Oury86+x+aAds1M1B
dvo4IKRP9GHPNY7HYezBsVyRGS6+GXyw9E147+pZbCyzUmOUBWUd0UQkRCCFoULQUcbbtRUtqk+w
dFf2L5iURZ/6DMaUeIwK9z76SzYmTt4JveDEgmhHg0bJTBRvBgbZrQNpIq/jGOuku0+gl/2Gv/Dl
AGzzaQniAM8fcYLP7gCM84FNZifXWVUunWqiCWMg4sRkJr0as2zdHHxIvoQ322t+dNEYKk5dbVST
j1jnWKp+U8uPvWxMK8MW96kd0VLRzLv97ii7K3IzxpQfYZjy+pO/IYIR9LnX8eGKM9oeQgMlEenx
JhkbpZWvj7owsFkxPfp4v3Otje0HVInulKgbHmXU7I3Jp62OQY/h6yTVzeoq68GLN/A8oe8T6Rz5
IJmYvhQ45OfF8/glNb46gAcjyDb8ghQyngTvC2KXq7DTesPshpdbkr5pfpGzVUltgWZiZDJvU+RX
lK2dzQMcwvqYl4v29KCu7tpFPUUSUwr+17osmRlOPr2zOWXCGWobAmqmNzdho7IjEa4QBRcIg/Vg
1g92Zaza+HOkrQ88X1gPMrE1/NKC8kdtd+L24ArQA+r9RnljTRpitVsegklnOH57NPjZe/vc/iTg
U513oyCA7s3aWn1U0oD3pLKeXM/uOZ7qkNSvMQ4vMPgJu4iH9rcVa9WVZ0tEU8TWioEAzo44JjH+
kiuf84jsrVNzw7qYwBUFz5PJXNG6yLvK/a60AqGd4aJ4hM9u1193+YrRPWEEo0a7QLwGZX5WSvK9
xNkvrHwxcSnFhrHGa1Tl94DNidk/hDQ5MC9+oevVX7v3HgvZ/IvdxHpYYfwMRjSvd+4ejE7hhJXm
qyD0LgHJIQ1aNYPRPC/2Wr/dNoBzs8BrNwTgqxzbhZ/WC+gkFSZ+s/IkUPY2B14zHbyzfj/oGL74
FdAVo0ewjDi3QSO0xuW3+sAsqAf31QDGxSa4UvxVlKUeteydmA1iFa9KE85TKj0xtCtgykHMj6ot
XMHvcAw5MDGbNtMsTkV96ychhkm12ITx2L3xz0zv2j4S3tlGB8bi+UimBnK2H41keKbT6vbhtdn3
sZQztrG3lZsBZ4RTAW29nD/FnoSNPjCLk2CSPP9zLvZSpwyBpvf0EjWa/ZqKRdHthhFh7XCNqlwZ
PCTlaqOig5GlsJ1enMqDyRFUj5GpOlS3XYRI5owSaS1PSK7K68OlGEsSNK5zZrk+RUby5TdptLrW
FrMFfw3URjPiAhiODWMXFMxxcEbxDbfLU8HlotEdjCNwkrMhRPyE/uUpxw4/uCEl4O06lteKGVYz
7WmPrbWj40Q4bmWPm4xLY0i2B4a4VGpW8LLwcU7d8x7kiQ+ZZfUmEXGaklVfoWZmSEFg3PUhLiUz
8xSMGeWAUIoJhuQAC7f+kClwIKaM4jGkdo/1Q/XWoJyEeNnuCjNWqTXmt+Bau7aU5RfbASuy5x4d
5FMYGbRhOTCNupajdrChShY1lzKd8VlmBOAYdKTOGzULqjJUPRqTnVVBxoExuuZ80Gh5egGPr6+9
5OLKsZXZlo0HcMc9DIKdLMMs2yhCRoVbnaRMnnZ+kQjUIk/y2ROyWDMb/cki+sidU2Y53OGbPYYg
z19DvO0DPsDLpuCWBqGyJ/LKBhVdvZfoTzgT0nCRb6SIHkro3jXILjFpZTHP0MXcOSlFWLuXUzz5
zgeMH5rA7MibTgmN9/q/KDwyZO6v5cWK5RQjSCZgYATw5Zp/RyDMNGB0ZmMIMClLku2ZrCg3Ae7K
PYvM562XtfthYRrJP2AvJW8Heg/DT4JHLKBwWKX+AgQBn8c6xbaAaAEDYpkBUcc1jf97r9eZWseG
ajou57OAHhvaVw+I1RYLZVXmo0IQjYx8bThSvFnXAIjVZ6loMlpo1KGGmF9CcXJ9IrYOvLwS4C8d
Il6KFkmQgP7lEsIbfygBQTiAG6YXD0hTNUfQoFBQGaIGs3ol8/bS6bZY3GM1fFrIhQ0opVdzSdYh
BbOrsoz0BTLUcpzmM3jdSnbi3q8fmje+cC1nRqCKQD7q37G2TwWcYUWnDHXy5gN5G7+KJg3nFYwC
K9+PJ/GVhdDe/zBH741HWM3t7D1G2jq+QCEGiBKqN6sXEc3a2TCCN/8ALEiUimxYNnW9ncFX+H9+
fl6VarD2RsT7LP58i/+zkA7zPGH9Cu3TFRmImt/jOo4f+ZMhHh/UfZuXt5YA+fnT5xTniIMjPl64
O+DSOYcBWvwHDwg7hRMaoIXByFmSC1ARim4CX/gnmlXrOi5brnt46d7oSlR80W5wJsqPE66gVmHk
0jbSCEBW2Kc4o/8NeBnH5XdtQbwtjJYdzoKNAbDWFZL0e41auQ3LM9v9QffLY7ILgHJn5nM1Mb+D
U6v/FvbohAhjO7Jmyxf3OzkpXmTZZ9mAV4NuYe6LCZ+3rU8i79126Z+WONJ8xh7Hb5o99QOzdy+J
wFo1To+blNSJWgGYX3mX2JydBMJuOiV3fxRa+Q9ZMJd7KFqmavtz+CHvS9c2ypjQW2BnfAZJ71if
PDiZ0peGC0QKPBRN3f9xOXfrA6lMGm3K6dDlX9ZCXs2TfpDlakIK2Zd5J4kEJAMsarwyyO4VK7BY
GJNAKq0iuAL3INXSzVncyKXYi7zix7TN7HXSWKgs5ZBpn2VAbUzdRIyImOu5GX9nYmj/SjLQURA2
9+6dHzJC+z67tNroCtoFSIJnBun8rfIOIvyRrupL9iCsoh0O317pFlWTOFSYy+czqlMoZ+fi+rAy
9VGA+PjgOFoXQKOO1h+RRauRHM16F4s4wNaI0uVJNPiSZj8eF6JjrYOvpn9fOU68u57DKQi50lgx
cm373KF3Nssl6uuzX9oZi6octDQArks53l0A9KgW3rn08JfyXdqN20wTGfoB1vZxCzAaGdxHuv1S
FDL8rWFBdrWv9h4mbMQoLnoj0Kt3nEnibVqQVVxnjBSTFKTJK4/FcSIHsVCeRoGZH4RHKQ0DVCa8
ef7NGEqZJtD9DvDErCUoLTE+Z/NT1td3rrOqWzL7fVXwywkyrhd7x9CwUHD/liV+uK+tsh22vlMG
OT7C9s0+hg+8cYN9YZPIgewQjiLJ8a4q+9Q7WWnlt+f1wCSGrfnQ9raxoSnfDFnaqN1X1R6Lp+DL
gBkqDvL7G8HX408TRkoAnAUO/AqIwJQzaU604eKG0I0/Rk4dQH0B7YMxm/Ar3sptS8/05aqvwFjf
Vvc+/LGz2NDiJ4ocqjjRigG6s6Dv4sfdNdTFy6UmRS2J8NEZYOKTpAoVeQJ3ynQkBXgjzRmpUiV4
SpsygJsZMXKoJrJ+wSKNWGs6Bmy9DcLGvBj8r1mkXTyVpGKfyqM06CN/zv1TsJEPem6RL49lA/fn
mpmGi9MI8eupmncNlexl2Ve5jtW+31OOzarStjsBZ/VHqRL+DCjBFykP1Wydc8ZoPlUUH4bTZk4p
ZT8RJR9DhFK0DcOXhcFikcWNrLaJ0RXN+3QoVn9zaV0axoNDVYnxB8b8llk+bdk26yUkBurKNuH1
/CetMpVAhAWbdTexIdHt1Lc2jm3QzIL5+BMdw6l9iHm3v8vqH8lI5QT2IPwhGji70iYgPYhaUyr0
ur1Eg+FVe4CksTjOTA99bdSnZa8+MfqqweQ37DFUg7sIpnUFe+rtkw5PpgbdVTriRQGgcVMJGHPE
w74yFW985inpN1J83e3eOHb9SKbpy4OCnBCde/4i0N1go0paQfT8CeePWEn+0ZwEkgAP/ot4VAYu
wDi3q28NS7qGYK4duxEHeCSAsdkdRn79dlDati2/Rj5QX4sD9+48OGTjM5Z7w7lIFCIeP2fbSFX+
HjM66UgmPXAwwReO/WrpziI3sbRFPHAI492uwkofC1aPtwRBpUG+nI9STYqavYmaDXjI01MIKPtl
kmmRS/80sORyrKODJ67tX965qlGyTXi32/K96jkmum1pB8bKQ40wKNdVTpnAzLm1Ogb7VNXelJ63
Rii8vlNtMlRqvmuMywX08QNzihF95/hlJAMtc99dpznM0kFJVPIebyvMaFZkIJOFDvoagpfA/6Nw
0LQoY3kdiqZsq2qqyzzEbXPG/2ZvnAevN4RJIdj4mUnPlMBe7oVvmNUQT0tADZ/yXYmfut6fV0Jg
EUcui3rELzeGYGvx3/sLeMqBsMb6wnuQVa3DGOQLQtIGxB8DYZ43mhjkQWMMzuHHRvrVbzccbSjm
idPutbcBBGdxr8jSE0vKEfQ5XteVnbU/Z7RcullHwmGkw0ur+DPimr9DGf9G+fkVdDiFKgGhNxlr
5CaFmZ65jDOEqCCvDOUu6nw9qrHCEI7v3RladEE/A6WeoljM+M61NafrEoWZ/6f6LU/dm1C9L4Lo
O7mPKXQe/Yp7AtyDeu29zV1K2F9WLQlNbb1Q3FdXFBBg4kj6nMjEqATX77BlHw6pi7FoZRt9kzkX
MAeacmrFBz+fpGQ3tR9028h5bhpo050v6JX2iLDEIbBz2kp6t9M75KKNg8hiKhbByCFuxWuxG/RI
I0YwvKOoX4eecJZn1aw52gotCNOYHurLu0Zt1NKq4DXv/5ECr4ZlQMTqwdhmEjcH0+ca3SUqhM3f
EoiN8iNCYKl37j9Wc83H34LGonf8loVWYeZf4uzoVTa2zNqGtF0++IQsfqIszO2dQ6m/GjWVez/r
nhFmuoqMCH01R7zAUNyy1gzfyZqOSV5p4aOA8dJIxE427BSQMs14EmvgBV7iCMzU7tDjhlBVJZjT
1Y0jT+gT2Y/6KQx18/xhUPGWvJADpin8p5YCtSCnz4iH+/BLQXvAC++RcszNLgvWSrwo7bykcrpY
Xy1SMYXCEqioKl4ZJunYeuoNM/QtbTc0QR732DT8+w6v2n2QwvwmMtIxViFoORhUIlNiQcgN1cVr
oueMn1868g4S5+b+hNFefYwkqK5IrBdy5BZg50NfHfWv0J6gxVAZvYyZWqOxcxXC55yTSdgaCiwI
1+uL4RDiMk/fTX65EYFtMg9N8VN92tFqvxUgnFPbkgDLjYNIgYIZK3NBFWZTkV2axZT+CCJ1Zul6
oiO47h5wNuZJCUVczqC58NwQb07OX0oZ4Ao3nIe6PNkiJlHOC5xCRrXKLu5ymoexbzgIH2E6CQpH
FW0nKeKZtwww0jeDW6jCdp3MMtWAnUGJZHvrYMeqkw7tP4QQPe7/+df3YeCeRyfJbUR7IyMLjKi6
u8QuvSdSq7IXg3KHAxfIwSldfsARomrdXDm9dCBmuCV29Hc7OEEAm0JiKGFq7Fe0c6bycCkx1lIV
P3fjBvhEJfvMCc1ZUSbAgPcQvtrr9+hZh9DQH+PE8eNvnqCedwTGKLcFKhWmA5PeLVSL9yIHP1QP
ok5VXHJkqBkZ9Dj8bsa/5FZWXlJyI7YhfDedSkRgOtM/hlJBjtIhkTQwAit0/aCyQFHKEU9H6rFS
LD5xZXfW7A0N9rLBVZzEvoo7TNGquCGa+Lqd7IuVFt+R/xhPAThNSltaKTfMJuvMOIyrfSpIGlq8
xkWbGqJhc2KV8G0Pu2HUQtznxj3gcBuiPg9ZIeOZrIDrsGJFu72Sd+/k4li4ZeCIMAZMocllcL+e
cmcxVMW1xXoCOQ5bnXZec4t2P0qWOQV27pcPmswok5yvh/m6k18JDPH9+4Az1F1eTEoZlyz8UxYA
38yh1NqIbKzDp6IS1Rhx5e3jQTCswNuNf/ViuaEDcvSImFJJ4s7KMZavy/bsv1OLAqQBhwGzph+0
NNI2lvSC0j53SqcVC0WE+rnaFo9xncLBYsIdt23S8e+6txqAK9FhBmYmmNX1WXeTPK/FQWaAkx0A
hkMiZ2v/D17ebg58MUWVnrmeezJWrVlBS7elSjnsXVxdkzA25y3yzQcCGVZBI5kgcqNpyms/9O8x
7Q37IlnZzmFw9NCICUDNWCfmLlsilw9I59pZhsdIGzUkF1KNoQQeLlPZfXQk+Uo5lnLU/9pnEisC
rrqol0sCwPMiR+nk+gB6WeO4APIHi1zcQwLnEsZv2OzQjY3oifCSOxWrynPwLvU6L133xEd4VXoO
rGrQYOeQrt8u8bhUMcNbu4GXRQ46L6DJ/MhfvFfQMK3cmRGCsZda5cOD+McAZqnhvXxiQl0L++G8
Uo1rWsPMoFxTGMLgfs+w3lSiMRVdr2TmraX7tlP/n85hitp6tHjSPAgZEH9OtmmpPJHe9B+vWht0
FfFy6BYMPl+HuPbL+Cg32A+lERTj4vsMGGlacNp15XtobZ3Jgr7BkdECRM1g5k/z7peM2L2W6mOx
mqgJEjqT5G9NdcVkVnwxiNdNNkc99yOrTgzw7/lhz4AAHxuzIzRAPkQvMHcrJT9CtDaHPEflIMTz
Xx8U+Jv6BPKs+hZ2FnhV7Eq7lOrK0JQj8bLVQiwxPo0o8yDzwVaMvUoQVAykqmHVnNVtRGGfnK4Q
tJyJBFYNI5gjuPD/XmdKky8qa5cczz321+VjNpj/RgcIA25rzmOqaRZ0KJsQoHOA/52PpUYX3T+J
g05voPwzSWlJktWJQIRCTcaTjDWUiDMDa4eATlWqQlySb3rINH61sEl+ZeIdNhW/X9Tf1FiMFh16
knYvSG5NXjwNJMyCzlyo/nHh/VmkO88Gr/dhuY0u3XMXJxNKh6ZH+hUUelCWLYWJnnjSF5JpkDYw
3gzfBQrxYRJ3gFNMIyoPKncXnMlZdvz1Kco8k17+m/AFLEPEobS16W1M+FwaztiUPqTwb/W3pUQ9
kqpvJZbRTeTsyV78Q764ovbVkKXlzLEXGN4tPej61SDVa2/P8AArRonfaqnbQIn9AEyCfTq9N0Vy
7fmVLJ3mLEZa5GeLg9haAz824IUJhKOUSTnMLNej1qVtyxjZ6M/rHjIYOVgRxl+Mwb3Go8z8dx/i
A0w2XKZ3omA6hPycDcwgk27sclK5khhy1geoy/N/ecwiTP93CrG20N+Cd+hN1uU03B0WCBfDOFS+
gd8N5xo7+VNLgJR1Dq88saDgncCSj+xDIvzkCumCiJtvgHDsMMKaNk6VtHieBDczCYLFUfPzogXn
pNyH+e3wLEkHjsxsa1wtY0HGD2c7e8dKLtJsDjiA7UfKhNs3agstoJvvyaCzbl6ys20tDLEaxt6c
DVJ/Ou5WOVk7NSTx5umvBbsF544R3YsINkBiQ7IVSPXgpjuw9KIvRdQloyIM7yJdiJ1G3pxszmCt
En70yj1gcvgNcgCXM3iKULl6IuCtf3bkSZdH6pHCU+YTD91zFaHLEqXfrPsMOFPyRC813MrOwaWK
CTQ66mM6qat7wKASrovjtJ0QQ3KHrWz2pjA5duxp1BAUYkQDvKUuAZsGFX9OBYUEV0qJDXNRFR+B
TuMpf6tCk8NCAE7F+g01EvudVeZExnVz0yPXmilZT+N0fbFdruWarhuXyOnN/OJnCNQAEN8L7kQc
oTlsdxSHdZYfeZnQssGjpiwmOWzyZpg7i98h+iH7WT6sIrvSdA8GoT0m3lC1epKkv0PJmiNbNoXx
R+ypWOKROx4dDrw28koHWSrm1fVZL/f4lkOzP0zZsXDhupiVLnpqEKvdB010ZY4lS3yvgaHkd/js
RSrUUFdqHWlajJBZ16EyJsP9xOJDC14vvJATJ7jJs/ImcUk2UqVbEJCZjE7MLf8ZxESiyqsVxl2i
bHQxyvVbEud7eVwyex2uvAzHdO3gE93X+R1HAUXnZpeSr8MSaX6A8SSjajW0PcHhj2SRBZW1jlcP
t9BAB9IqrdhuF3CP8xkKRXU8jrWzm5kSQ4iApjV66Wb6rCbYFvbgVaYiZjFp0CPMn4l9bPz3u5OM
0fco1Wnf1fiQudxH5wK8nria2Ly/n5qNVHjusBK1Co9Cgov82ZiLgKc/GHyTqSG+xCd4iCtjxUvv
3GKwjvBzaSFAkb9zye+2xkFv/ckCzThFkTTeoSkvIQEmpCHanEvVu22HfEtvWMQDvRn9jmWLfVN7
JHYnfzJyPxn8nI05BXxs9hGHUyw5t5CFZ6jxdHu62gUuXzfKQGGTYSRRHUx6aT8o/pbmpZd7t5Mm
n9WEoCDlVYjBk7+aJOWYcTfcDmG7Xtu5rVFOv8VaoDEZw9dd5KR/hwrr+ueVNQhnikOERfGQk2fl
aPpe87eDxFTq8IC/zVVQcVHMshnFkr7oqicMib832lAGypvZFN/Vh30ojYu0niEdreNdIdJaYbXt
ydPNW9SxJ5FDyXMtmc22EhkHvXzV8vTrKs417tZs4xL+MVq5mZ1E6JXdD7XTJkTeCiWl4K05nmIX
D01bBN6v0IcSdZlxapOjvvoKqfE8e140OzJxIBYMSbEd/ZGJxZMTdm82fSewB9xqxiwQsMwhfHwp
ZO7iyvF6aLrn7T/nXnsPyCXpOsb1yE9Z3WbFKQBvr2Pk4PM750CBY/uy/zF1+uo8VVmyL4RzjSJU
Bw09+p6xTt1LIAKLPLLEBZfVEN3n1uSMj/dpBMAFlWh5frAT/vtVf0oyLKqE37DMsx/2XHjJenqe
Dy3I5dxeyKLLGEu45N9suP0a9PtjCEkfg7nbLMnlpY4qMfrLxbBIhz5paT1SwgeBRbuHiC/daJzm
S8N6QyJaYTyhtCJ4OUWmYc8SCQmgHvKGjxgbqjBFpi1H7G+OSR8DE4afJmDixpFpC/g5douXxOLh
TzJAKpWbw2IxHfKtRl0I23a7dSS56SbLo5LPm4By7d5ZTiIKXG2v79mRvGJzYiTZZl7GJjDvH+lO
q/snZHqFP8ITcDOTEzPvK+MoG2ZvrUh+XZoPXb0UcIHEjUI/Z2S/VTYbOzaBcS9sQiXBnkU8DfIR
OjhJ6BtSiMXD2g93nh1tkt3e9EjKKNjN2e9v6ZAptKuMaeYPV5QoIkWAebleZjQmj0Yc/E+dQVaw
atsgyV6YOD+BopqYrZKe6kXka7y06pPzi8zs068XOA9HYWlzrjtr0oO7LRmB9Y7CuJWFYTUStzKE
JtVKHuqo1uhNvxWJ1foKIU1b75R0Wa6kamWKKPO3XtZwYzxnxePIJNi1O/lq+R/sc9CZFSjr+K4D
ZOCnAdCRrrzcLuikBX4A3XDZBcG06Kfm6WKbmVxGu43QFn/kZQXlshP7io9FHJzaMApleoX4NCxs
BgnkL1OStREMk85Iged5O+wK6jFDVlXyFRZjfU5UxTR912vMmvr3SSzcbKNUyqKmQ01LEqdhne7M
p6AARaYnmOS0j9qL9Ju5o5+jdbJBqrNY/CZ+xbLA52g8apmGYmZlYDNUxdlUKHm3j2N0jyh9ok+j
KHMDhzya+Tx7PHi+FBBBeeqoB6wm79YP01URJjZNAgo97R7kQTur338ib+O++gaCx4ytGwMXjxuz
pOGnpCmcMk7CkxiM6rBdyuTNm2W+Q1XPtaJZIYtw4K29S+QmAaMrZ0XOSzKT7SucToDWeo9+DpxJ
kMA2Afgd05olx+Qj45ngBB4PQ03MhIlS+Yader9aR85Ok8e9S7zUjgO3vJt5eyiajoBQZFMv1sz4
5efK4UPcF2jKv4IPl9T7uG2VfSXoXdAkCTUFjql6fZKNGDDRN7U7iaAL8Z2p/GHlsRh97GR8KfHE
iAa8rSVGqL/wC/yeUI61b7pvzN44v18QTTLa7ZOEByERO54YDaUFySNGDqCTmRz1XjRt7wY6UtRZ
Gg2vQoOIHOh2JkB9rbBXq+QHM9MI+6YIzs4mWj50yp8oO064+O5maOsGe770VhFB1c7N7Qc5r+v7
P7veUPnAgVUoDloe+dWWbKQpBGGk9IAGl8J2TDVlEiWdzLwOtmT4npuusHJDPZr59axilk0YxArq
1UeH8UWwdwOmAe7uvmfLLQI8EcAp5UjDtpG25Gx2zLtEXe9A+umTSacEfPbSS3mIpTDnM2vKzokd
QxGoJzHpyZz4YFQjwKC07+QRZiyXdQzOul/AiFCS8LQ+VBMKGaxmVSPgwC0UxkNfdSvqvyXj5P1c
Uth9jWACwHpNXK+mqmVANp5MhUtGSLoigqvBb+1JANvo/+CSKsANlyRGGhmhuif6CBikFM8B8Pgg
/khgFozYkGpxxvugswkvUP+vbFno3I+G2irrBg0iYxj5nMQHNGGNyIRixxfKLloGDPYDz7cR5JeU
N/T4bYmVHdVOUkH93P0Xza3gd3xNHBptQyYBSq25cMp4MueYPkGxbPOat9rVvoSzo5qq73cK0v80
L+qSbZ55qRQxWyiGNFUPFB/O1p7DvhIiOkVnQW4umjd/hXRPgSDIasMkkvJO6mQQnvtEsRXyxTJU
6zyIEl2CWyMta63JHB87DfeDNwRzyFYjcO2r8GwRDQqKAPSoRhDqZA3sb+0XyWRy8Q3IqtQGA7aZ
1kUE0eOZTY21qW3uIJB3CTDVzi+s8aNMvR3Q4feI/V70r87lox4SyFzAyb9gNWz6cBJkhX6dWOtD
9ffT7I1quGXVkBWVKjM3RVYq7Q7Bt9HXXpMr3bW5ghpwcbKiQvvVq8VCS+E6UDfTzukWstS/Wx3S
LwNbFd4hBfAW/ItxjivlL5SOxKfKHzGHdRZLOi9QIEJl/LO7TSr2r5UUXebsW7ACOipaMptoRZt/
3JrlsHMczZswvRKdOaoN++uoyyNEJ8RWZkpNN9iOoMtYMkAecaFFCcc1Qj8lpOQ/tkQP1vTQ000o
58UbURsdrZBSkmKgijUUFKwUMjnxzyj8ABABNHn9pNWbOBFMAaGtr1xgbeov7PIqzjncplrT2v11
EqulqKA8Ztb+LJlnnKYinDJCeMqI6mfI0xwdc5IQ4uaKUPyH5eR8DGpSb8Qp4e98FPzKJ5sI5tVl
C3r1SmqDey7/2vlLP4mFS8zFCnNYuyxIFBFX0YJbvTglkVMxjDzEG8GlEZvVEny12e4V4TQObngQ
k8TAIJhp5kfynVsIpNnCl/evn6vEyPy+M93qI0s5TrvDt6Jkfii3G4ix0Ma2iKUqtAKXYPAYCZV1
XkaUV92czRBS9v2zhJs3bzlYP/NLSgjCyeXP0MmFgTbFcri19DpeL+QeankxLYFG9mnD4CQKOlmb
Wyo/DJ1Rt5k0LHP6Kfu7IwJIKPTcyrPOvNZt8XPibCbjAdvqIy79AicnlhbSFr5kFqL2+Qd34fwG
GHVO8N4lFCr9LL5MZ7VkVCcWfGLp39p5b+P0n2bZo025Q4ZhmCMZNui9nHBu2n6sDIDG2E1VYX8a
5c99vb7gdsB1WVcgegbkMs5Jq/BfytjvG9FEASNjdLacPIdnP9NVz4fT/Ea9o2Syv76DqHfb+S2H
1Q94+LVV0/IjUxzy5hCdJG8aaf+dibn0bM9In/Z8B4Ns9/Jb6iGArAjuAQ/Gs0HeUhvoKrnPs5aP
sC+G4CwChQn1jdhlA2vlcumX+msCX+l63lrU39u3Aq2tyhlm3aAtrMTgjhpJrfuTMOYhp9Rkm/+e
JbqD5AAuuYw36//mA+y3e6YEL9gHSOAvIXcANZdxPKu8M1iCpSWfgWNtuRo3NjpVY8N99Qt+KFUd
6bH6V06ea1VzxDhgpvN2kQKbdiEDq/A/xDg1f30DCwzzIA4ZHg1C9ewrhlt3EX6YUkQPLlPRtY1E
cj19VWapJ4Ce9PT2l8CN45zNNXcNiNcees7w1HQg/avM1/Z3ZIqZgjorxiMoJq9PEjpTl8LN5mrD
2YW2M4/K/fmZuypSILzMWj55QXO0JDpTn9jIb7ByaWqzjgFE0j/Z8YFBAjUzbizguxz6oNQ2Bdqz
fpEXr01msf6gNgZG7SLFpm9QCKmxoSb/LmK4kJSL5iXSWf5AVLKMeNwmoqvprA4OsvQtGSS+6k+L
TWtqiFUov3RvyLspAteOcVImj2KLnjpuBN5N2TWPSwxChfFK6A5VW1XbyG0r+0xwLgOXBnP5rUgl
RuXqgLNR31hA91E7PbmYJea+Sr5mOWknC5j7HcwJdJuaZCW92PEQqSR/fDg41CAu7YC5mLdF2Dhj
zUlEpZDdp3ArHTOaqcxfOm0ctQ/vF+Q4eAYV263f/wShJsPt2vpf42ThKOFA83WX/HhiqxgYy3a3
hGp2FKS5eMod6mlL4Rf9OoWFKeOWHEhCjnIEdQQ22q5mzjQvMQn8wr26fnzU7Szcyt9nG/QhF+zU
tYlIrRN61SKOGBT1pDzNWxnfr4+ECArG3tNfDBZozm6Zpry/JY5smlYcYzdQAgozguL32ispBCpJ
rKihyMOexk6pnqZnwW2VYy7A/oeNggwl+ct5O4CCMEUfg5jxzkqfhL9fLKHRO2DcD4iA2cXCKyL9
+clpZZ32pnVAJ6NSW4dRYP/bPLOs85P0dXr8fBf5GLJqftdGA7XBF/QbUWc7yYsmdJ73a+3sIyD3
Qp7Wn0Qh5rk718CnY3xtCcItM5QQvDjI9AfkfJwapZT+1jv5V/IDlrtqJ/8rO68vS+HA7S27GKJ0
XMvFzZdaFMBdo1suaInwF5gwwiZuKYiymFj9pTaZnqAD/8DZfSxYUhzvq28cOnc7mZ1iqNubYEny
NlahiHYsMtVbvzzn61TRBiIkUIQlU+i90no7P+rwm9g3bBNXrfOxduiWB+iWsSEukEjKxNo3wmlX
NzynIz5J+7fS9HnIGU1KtC+nC1s1ijhWOMl92JUnKd20R6hidZynGwyJHcGlso0YITuSy2uoDrdT
W/50n6KLF9q2+fT6wqivO3bncGPRah1NxAIIwfBgZ4YqBL1DwCnDFzVG20zsUNePQ+o39BPaXK45
oiMTSBdEwUq7fE3WUgBaQtMQrolOBG+yJm1hgO6mpXzNS7XSQg0LwOF8nsj/luOhShC4UxD+KAvM
z71NBeRpi8IloSiIpQB1DOYa2lvLBxxv+0AhXO7/GWn8bEzKVV9lm3C8WtndrbLA7WNfP+Wo9Z1a
v1AUBLLePfEujr8nTbiwKxBypnMuVAhBNCeBbShEDdAOWkWw+g4hlSC9ivqsuKA1bKTJUjLh58BL
ivM5dQUjwJO2pamP/uBP6vAFRHDsdltBGy3FurfMHbEOQ9nXmLl4oEdCVTVqdKZtDLt2IKISbSaL
0rOuPJF+hnXUrnR9uPRzpmx51xYw7hZKhHUgOgttd6qKcbaRRr1cI+6Znmz0usr53yX0nAX9yLmD
6fZ4U2YFxS4ZFA5+c+ZW8jCycFkz6Z2exTklD4gh0xLYBYaxrPBckueKtC+4meHuR/yNx7RD2QNu
IPaPT1mBtG0OwLtEiIwzXrxWbg+nvEkAK2/659+xtcDrfIMwtScQSxOqcMNhVUA2xvOyg5FLOMjJ
IMgKORZPu++mzguB08qMVvQiPUNnU2rqY7sZWUDBhdVyYu4HS22UU6NBllX3O7y/OSekHUZ3WI/H
wktDRmvKy1vF5AAR7C6J1tueYITdzdhMynaNM6/TRhHuKP0f2XgFOQmsV+973RKQe160s25ZR5AH
XiVjL13+E8vz8sf84qLo5eLtUVBnVYClCW6nWuOC8H5GcLmVDE7izcZnrBeoX/uByciZhnXbAfm8
HDoDIyx6uGlG80uzJXj+IK2Cled3/rvIlnI9tyjMDYX3wzzrMX5oY6ccWDU4oFNcDiAtnnFa5xBG
X+gMh8DqQN2i8im37ripIBJ4b9uXHoAveZvtAr7goIIImYk34DPBdOONnDFQzT22ce4+2SgTutcR
N2ngS9bLrY1CL8mZ1GWh9XHDZrVO7zuKYPMmxEgCmA8uIoBfscRITAfmlFLfdaKg+bmvPruPCnBC
ZSa2Ss/OHE7F5fZ8jiu1VdfrRQovpY7ii1mYX2lY5PNhtMSE2VbXqFVt/s4hh3CvdDqWerg9GE80
veIlXfHX5mxs3W7A7cjrcCmhIO57EGgIdN2T/YoYQYytCICaieka/5MlG2qK7bIkn5ngkNsrjUYv
qjCMleA32PrkZhbdlQGmm6VlCeszFE4zPX4ui2AlNohkxb5GTJRxv8hRGMj1UEPk7TnacE+VBRmu
dK/ZIHE1cOytw83Z9lOzeEwTP50LSTTKFGSQmBd1KSvMeGpg3gZa39zawQyzbizL4fj9S3O1CCfs
D8Q6vizOIhzlwx/QpBTXta5Pao+L1AfThO5sJjifSobhS+5ivuIMDhmAdN5ZCm6K3X2fN+nZHeE/
Z4EB12O+9qYbJzzM87xveBFqfhsuY0erTn86JjcwA+f5pLC2LkQ5nRSjBUdM1lGArG52ZeS8jeHP
WowFDa2c4Ahn4ejsemZ5puMHLsV4BhvQxCYdda4qSW285A4cPFb/9yiMZDrRIa7YJqVbEnuzXh8Y
W+pMG+1K9ix/+9aF2k+HJ4fb7b0VCcGrhzLq0+OrDmUOijesQhW3Nmym/uZFohgIVMDLN6jkZhzW
PA7hUWxjMlWXs008U3JV9ZCBo3OhF4ZJB1thuB+VI2CGVNASMdzet9g08F72Hed4H1yVsP5H41ry
Cmx7nn0abV0F5I+twKSqCg66Rthmu3itnOQoP5uyCHhTbtgoNReG23nsND3zQtHIKyUWG80esjUG
GgJCv4kG882Ax0jkAbxNsLUTZZNNzXqi7cZygKuZz7cAXDh5+p+r1g3IJvvfAaDhvXK5I98iNfRT
9FEj2Am9vlbnC5BZUCe48zTAT+cPRxODH6lpWjN1HRx2K8A4DdqP9wWnianOnmluB0VjMgNH2tlQ
WVkYpQrSz/Ar5XsvFDeLbxJxZ7FbWEgq2SgaNp1A5hugupTcZnzfwco7EsD9Su9oq/PZNXks2s7Y
NjVxYWq5ma3s84IaInhtqevwCZ557m83zcj/r/WI3aJxzJGjeft7IdA7OKwxQDhmOD160ByL5lO3
mFgb0aNMCYRnR0+xfhC6pWjN2nawyjWjRzPbkcfQZD8az3kMLLQ2UNh2Zw+J12ElsF75BNiW++/7
TM2E+b/KlewQTr0XGVAOEDbPPaMiwVKPAG6SmQ2/sBeFoaMwkNYvA+oj6UTIdFrmSr0qKNRsflNT
AARbkNgRzJY0XBDqGWf2JN+qQ3xr3aO/EfsVw8Rwu4qfQ+q9yc0XqO6In8k1r7ka2GRLKh63/ZQM
42sOWQMUwv+pXGUHZ1U+8ctKQyN2oSf6WpA0ikQZklsKfrUelk2cNS6gaoTf/PO/nO2/8Ck7RYuR
j8ZEO1xAZac9poTxSQVfVDb2oZUqGmDJ4B4AadyEB73BIRqqruyOw3ZWlB+StXEY7l90rp5onA0I
FRuQyhlJ21E5i/XOKy8ZSs6OS5hDu53PxC+x8wYHuJGFMkPzL/T6ldia+eQWAdFNDJkAuh3aUpPW
mTKDiEKruwulrUPj8SIdXGym0WDIX56rM5aktjgHCBxlS7A4nEMMqhnqF3dBQL7Hh68Lvz+LlFw6
wFJC96fMyCfqlcaY3r3fblXymS9/iaHAAUbyG1lXYN9IzGsZMJA25Ded3E5EGs9BsHLe2PAP6K6w
h6UFNODAscV8YH6UaORCB607lxOkXbXPvh+vdTTWyaT7m6u9z51NqcO7/JW5KyGr5IXzSHo8KbUH
upVTG3dHDTBnoUv0YBBakmD0u00BmPuCBc9qkP3pigyhAp7r83c7t6RgcZQL2M5gTeD0pqiIr6D2
HYpGm34lX6/kj67p+X+NifHyDWwA8OTmNV442wMidfSkfcL/9ttz4aAPeYPp+pXYCAhgl4u7cnSn
/fp+izpsNAoSMxgZKnAwB3pOQtS5jL7TrdXWMnKT5GIUKj0Q5/U1TnhRo6TU50rpHjiAC3H4Tmp6
tV5lt7d5EOGRF2tEEVY8e7AiNtbwnuErY2co8iwPDGNohe2hW2znCc7WynTsEP7Emd5UXNoDMDKT
psKsoPnUvPEk1rT9rKb9wMTOtsNAPj0MRQML5p1Xis1uwDPWf8elZy+LVnaJ5SgEFun8ozukCbLB
CyIGvSYtZBXknA1Xrck83rs7lo1O4V/uBVL7BTslwQrj0sShw3AyYQB4fXtfwv75fk/aewAD2Pfj
GaAh3crUJzO1o/pWFB61XI32WLNnp7Q0P6mRGNYvAjd1w3ymIGwgHWmDzYEKsEvSrAsA4gPJ1Jp3
AMJwYOIgzJJYnSzUxzRpa/l4IshtrfM8dahtoFHU/exiTtAPvs7tnhU0vZY5yflnxx+S5K3K6R64
1UHli5uEHLjWQCacj8Cl66eYeUSYy86JE7+K8knkLXEz0NErGww7Uk7DgFP7ZbfX7Xax4aMBCapb
wyaABgCQ7BB/eHnLPN9tJUEBZ7joCD5a/yVHdJ442IEavKZvfYvW3ZNpXuzuCUDWPlPPZSS9MwKC
BhQTKClrFKRv5pmgXIRQo/TftFewFW7eUKTvkVFRQnySocfIwMMy0MyYwBwIFwLjdICtGZ4uhp0t
3hcvApBiUqzkq2/6czI/m2iybgqVZw8Bc3sN3KPDKKrZpbRNK1Tsy08AG+mX/1PnyGx54KLkyHOd
KPm38xJID9Pf+csFEK3heHRCIMFHY/HoRYCWBP9Kshb1kTgi1yYhHN7ApjLr9OaRjc36MHRsmlz/
RZ5USNytHDPFagT9xW526ye9cKcOiuQuiEDhDk6BNgMSOWXU7/iJDHhQXw+V0evnEt83JqC4XloJ
whMsXfZXXL8bsGofCu61XJY8/MPmYhVMmli/687K8rGA5syRrF3gmi6kOok9zYCKHJw/mHBC2/Ej
nbKf58aAlNhQsiViTP0WIBlpaoKRZZ/Mv2LUr55/RclO10IqPmfQ72RPLdHt2HdtfZcCq7Tu1XpS
7wmQmBGu88xeVP65ys+lDeM9GPFReGq6S1gnWhKTRwkzZUz6Y8jR+MNIK5Qh9XvxXA1qsICz6K0O
SomwKcIwToBGkZZSwJNMDGU0orai9Bqd3WXHe8uVjlaJyC/Z9bLapt7r0/PWypjblsaxq75LGtRs
TNrFY4ryoAyYualnLDWaNokUpD9VuuBTGyPr5PwdtPlUd4Dqp8riS/bWwKYTdJhQjV9vDwSgs+Ez
Esj6h9vsedaaQf/mwPI0vC+Nu7zXcwlesDK+aGZ6ulyhmuYHlrW0NMlmdZN28ct59OPlQkJ7mVH9
MRX9U9A6km4XUwjheKOJux8FDmWeG39EIMvzvPDVwo3yomh8F/+xj8hqd8luiW8gIJDYZAzq1CKo
6ypbKmrwr+icHTuLiNj2lbd4vOzVDNMz/4rW5lNjg4NvWPuyvzR7wLTNaXqeHKi8kWXCS6BeSIeI
X1tJDc8DSCV9qCcb1AJGuAC2gHjbKtbupJC7Jtsu1PhR7IR4ZX4rF5UJKsqCiUf78eex9gg8oYGz
8xjkyEexGVy9+uyk1M3FxmCOOGXHFjYOPQvHeADICMRxnW5fJ/P4tF78uK+rbW2iwicqlDgdzuMg
3Ydc35PP95jv32Wigw7uZx3z+hxGa1H3AYEW9i+ZXSKiQZ7+x71+K7eqhv+h0JXRgbHFSxoqPEFf
DxenyKsU1dFtbQCGX52r5DAV3hJB0///ZOcIWNfZuyhvgmV6zn0mYyhlLn9H3cZPOJEzLHxhJU23
QSZTmVxQNtx9DxI9SdKo2KBcqaRcbtk44Qp+Zy5/2zZ+M8FS1Y50QUFuCyR33amrtdw++oo3aHvJ
dKyhtNBgaBkzihpGOBRU5oVS4PQUc+uQd/FqKcGN/hhJf1Kma2VcVYNtYAr3TMcrz2P4SVRI70ds
Ea0c7YXLCJHdbxIHNRDCytljR3CmMv0kKLXMSyqet7qvFDMCOXfjAmOS2JMman7ziQ+4OPOWSBlM
jycwcnJ+vdQ1tQdcLRVdHi5PdGa2rJFWCqoVPEye4rqYT1QA1JnD8IrBXGeuN+SrLICE8/L9YuX4
E+yV95sTNEQM7TPxm6LXyLNE2cL5n5W/IBl7Rq9IqqUGM1eJyKXEzHJxZUrpOUN42LG70ViVmUGp
3mZ98F6ThaZxRNN06GtfKGcKS+SPjUDWIdUmyWC2mPCbJH8aO+CBnV0W3Sy9pKqPJTo9duYIgFyU
BY81bJc/oDi6eERxAkrQ5OzvIgASGvF2b74HMuHVKUH4kceFJAviFJHFoDJo/+ZDsf4tyunLd3vA
dlBd0zlDzkGnUul65+7DPa2YaDbIY2tQF2ZOMDEwQG29kXLNQen7pQmm91agINK8xxIt7Z6MDXfk
rIcnoV1IbCkf0FmVnbNPcQLCwABHPF8/SL0Loq8xS7VoKXxhaiWAfrua+XOzslpdFoa+6BlBThRS
pqZ/A9ZI0ggN8JeGfmlYVYulUFhIOmHmRTYqInRI8CY8JeHYDlVmSyhdCkC3M4g+/JYt+GCPC143
hJ48cfgtZ+UN7qwQl72ECEvSaqUEZu22NmzPpTU+l3thTgvvOxYOkG69lBkRF4n0ds7agp74g6WJ
9lt4SRFt8Gv1MouKPu6mXtATjdL7/OZukTw7DHj511uPk9BkW9rV49ZyzObfTwLRMO72b2o3JJTO
DCfbqcJgedYQkPNPTK/5E9KvJv5Gf6eX/oWduYG/LVlNYb7fXcp+U1P9DQDvFtKKBUUa6NzSZpDU
ERL89p7VT6+9FfSDq8niVErrCK475XEBs04ZQ/UMxEZOVbkdx03we9QArVFhpUU8QDayHlFpKlb5
4uB917WwI8rvs90H4HhFUidzaP650NUhhx6P3RGkdvajee8XcpW33QznKbRnS1uRlup1KcSw6G42
JnFEgXGimUubFFdW4mGQvGqEe5Az/c9qryfiieDxYAPNaOWrLnB1LVX9zhtESd/t6bkV5ZAcR3Ft
ZA1oXF6dlgX5SQr6QZR9u7s8O+UeVkQ+EsnZnJCzq7NhkO0U/e8Xq5NBweghtsHNx7HGDrRzf/En
Pio+J/yOUBrmOk9yepVE1SU+jC7sVfatkoR57FKxk1aDB8A64yN7RSmcvFE6Cmxfp3q4sziN0uvk
yIlOJAt8BbHP/8Cs2L6Urtk9hV9MIKffx9LFg4wp1Oszu40X38PasESXhN7/N+sPcVbvpwqRhEzk
/o71uxRxRio4q+yBlPj/hnMYV437i5fNqwxXtWUBt19bVl3WxrM9ChCEpopmH7LsbjksTkCxvCey
dG1t27GqiPeYzgWHV1/lM07n/KtOLDckPTwoGA95xrf8zjZ9ZoHlDiIb7OPNnwc7jWg+UtMX1cW1
OPeiJTCgGIWBIy1R6/dVIoGrZlxrjj1Bzd89fzU8D0SPCZCXTxOm+h3g7ffhm3ZUkO2TnVJuqdPC
oB9C9Rd/W8awsymopeP5AD/EsNyya2ZrmJSeiAfCRIZPGstsKHwrQJ7EzZ1grTfC/YaRiOPoONwf
aq/3miqNNOtlf9wXQ/B/7dWe+dVBghPAXqufacR/vND+gUKr33MeMy8xEJOWqMFLldEYeRMK2ksI
e/WxvljLCgol2peL7L/2BHH8zA4oHmGN3CnoCBO16WNwkMprkW0v2xPOkKxLQ2m9bwxgVL+h98mR
xuHbOKooXsaOWGQnOxJhSM5VtS4P8svQU/DRgJf9JGPn1th9Jqbp30doL9ArftsNhmMk0qnCqSvZ
t+OIO+JOC5CaU2sAi1av6DyJjGx7db4Exgk90qRJKgcj9/cwIjYHgPLnwlaG7jlCBqx/PNen6hBA
Z0hTyat2cLISWuNgZw+zcbzepI9RWEj3K5ZuR2HMfiWVd1/K/msMBlxda555z8bWIX2nJIKBOoXS
DeZiDbxNafIlozIjEaNJdAUyBT3H7FXRWVO4qwoSgOG5YseVMuokdPXsqZ30wRHI1kXl5/pFc9f4
o6XpaxK7EP5vstXOKPVh1pwSqSCYtJS+JkQ2TzEkC7Hr3VBzQfkjOgaHtcOQe92XW43Bm2zIslDz
dNZuRaJY4cgXQ6raAbhXzmDs6z3YGgaqUtNH4lfm/QsFO39IZ1NYWKW3CjbV7OxTSfrfjLn2R4St
27iIMQh1aWHlxQpbtOXbCO4nZfr6rEhLPUT1CgRzHnlSaUyqFuCqn0e6IRWsY9rt683gGLE/6BKv
QJaFcnbECHZ5Lu02gIE3efOHJ5syGcbbmKpAfLLJLmPzjQIuQyDi3ggIx4JKRT3XjygHF3WjL65P
gCFjLBacQk/6rv3uEpQ+nl99f3rLek4a/DSnC89HW9sIJqMJ+a6fwjHG16fEu7ymasu2vMX0cxGW
lhmkvsujbL6Fr4P4DcIJU43XTcUSgojF5a4wh/AKgUw2J5IpoTHAjuHc/ZIB8yK1vaLOxDTd9eyo
yIz2zHKcJYTtmt7oDWvpDVKP9uOOq7Zi+cOE6wiB053UTbsT+YLY9ccmP1KMzICrEehQOpcQ8o30
E/8eWLLpJr0u85qGPs+AxeMOApWkFe50XUE+BE7J6TH7HOO8mHabocRlUb9MCLm1KLuVHXHdrL8L
5ON36hXLo+b5R7vAvbMk+ESNu4l+QZoHX6QE0S0ZI5LAobXpUU1VUESLSeJiZJ+xYsxXdT1wyBRz
TC10LJJcqQ67U5UdwC15UExEDuCOKoKA3kE2xSVVjyzIUDrKZlFEdAcSQRpbQP38fqNaxT/2JSw7
UN6gWY6CNWhuPJab+pZ+d4AyWEGLpndATthH04p9q55Y8gZJM7ivCQlKPQSjSTUv4u6HytQXSH1L
EjIWvXMtQiRI1bsgnOyzm/Rqb7KRwjcrHF3162VnGD/kTVDFUv6HRla5dNtZDzmPLBf4PiWZ2vLy
W1pRl4Rjv/IORqlHbTuQwbcZgbx8bkKMN5yGs8IyiHJ1tt92Sc4UZBque7/DvFUtvBMuHAuObouB
qSLGE/qr2iu48ot/sSez8623cSdBes6lHzZL0m8uuDrDti6QNeaeRQgqOOTJQS9Rr3LRt7feh0qp
nViijbrTPvUkkseWgUMadF+SmkiR8wpmRHCQbOZdXsxxRsybgqeqXIqBvcvFg6Huh+7oUaEgS/Mn
e3P8Ug9CJyme67MJSi4OIWhSj18dhyogysqfnX5dtTmAjkcTC4yIU5VXZdSMmqkR8wB2S6imR7UW
1jtfJaXR9Mx142afQIokdzn0UYWQTgO3NEqJxqoZG0PminbWwG6JhxnhRlpS7TOrR5a25xz8vFYk
K92l2pRV6cWhkTfU+9nQFfm0KjgRxNObnfW/K8hxF7VL2opc500xFlCjpHnXwIpgzHhbsoWgXA37
wKiFj/yKPcxBX12+VxMgOs8DxPLrGhUZsLnDzF0cTU+QgCkwpMDVTTkRf1aIUqfC0Zc+SsSIC5qZ
DJBv6u9QeFORzXKmxumw8SWI9EnPhiOpPlabMXgVR66JTazGd1a3VQfhaWdDEM9373nP2TXYB3CN
+x4fsUi6tmiPgi84I5CHWEMQLEiWHUMTjd8qR2ND1owxJtALXmzSCcdhuDTegrJYArpcAEZcgKwJ
OsZwneo+vIzy+Y6W3Pr79H/y2zdUKELHlGQZEcooGwba8FNJnPkQTaAiai2XoVVVvuhkN135e3I1
veL1Fnni/HmYh1ytA8g2fVYgs3r7ZyZpqGD7aMxRg5whME3XjBBSbB6iej9VoRxOeaYRpJK680mM
JJeh5TzROV+SIPAF5gvEd6DOjj0+lDec82/W9AXNtHsHZQHPuc0/9f7e5Es+NyNj7vyqBNcSxZ8+
Hg+8XGsUG3hyCoqxbl6/eXd4rRExHhhtDGRZjlZzuEyCPx6adsqbTAZEcvdubsSw4xZLUtgmK8EU
i5XsjvFJ5AzDdggh0DMIBChPjDbES9ehjCJJcZVxQiwjrXywuZjBfeR1ltcdPItDDsYCPYCQ1bbv
0cbwzKsgQa1Tkg6vkUY3ZSBEemyZOz3FpmWxQ5pvd49en9uolIzffoOmXFnpeGggN5uhwq1D+Cbq
0XaiYBtOmCakYJi4/mGFv5UHjUnj1pvU5rrxly9c/EgxAM5LF4tYByshDnVD9U0m9u+LtL/799lS
CkB0ELlHdOohl4kBKiIKXfKzrDWQeGIYhOYd617jNPCn8iqpfNkwYKFrNacR5ngMrgdHRLq7QsU0
mkXx+ktNcTMcxelWVNxl8aeelA/ypxyRStfXyr7sjSoyJKjX+UQajui+ODN9PmoLGW1wEb/S/Kxl
qGXFEfOX7aXST9aV0NScs0LlSYAenxSHJyTHqZO0QVSqj6GuzNw+4973UWXTqMlrGLxAdG+rUit9
nbEMPL2lfQ4OVkXa+or9n7n8eDgM0acJLUP9OUyIZYHWT+3aPsD5Ehfr4t+Y5Wep8BCuc2vGCsNy
bNcPDHk85qjkZHMrvkAjWCNLN9O5x46XACXSkymr9yJRaefhpTUQFvCeVTqo27PHttWT7I7SVyPs
4QKEW/0hVsFZOpnFPR5nVHjzj+rxLRP57fm4Ijpvp3rJz7yNHf8A/vzqKBX0TmouDw57IRKeZos6
U6nQXb8uWG5yBIBUmy3tFOLQBm6gJT99VuxHK3S99eLZfklCuyI+kTieSq1iUffYR6byfEA2KXKm
kphHGbVjSHjySzN5k1d/weJmRpFug+kvnAPgxcjHeKaVFLIBtks14/xshXp1Xwssraei8PdkEVd6
9Pmy8lIrBOx4vD1IdZ/x579wPinmmqQlPnlQSwBpmfV5yJas6k6vrspfKqRZENL40xdJpFnxSdd1
uiav11FtrziuzpmAoEB5DIVl56ElOM5hEXPPjYvUlv0sR2mUpAvKRu332VCfCxbNm06oqmD7BOP7
1x9DipEvCHHXV/kbmV0qjRLcBftLtUBux0UoGPqEfxlg2Txs7nFcOci/RReVKZxn0YuFatBmfv6Y
9AYahekvpCkXNbm8+JWIqlt6+GmqbpdBqzGQPt0yu28cMqj0vAW+UFXPEFmYO+t+cCXcPpCMbVbV
fwHKpUld6hORx84vGzQuIMbvJcwKlEqxMcf4bQ+qkkn3kqqbptVvSeJ1Ipl3fqbaj4ct1oPB9bkD
jGcrqxza8HQDPXeDpNRLxx6nxKkOFmraU2YpW4WhS/PEERVZBuzCcqpKXQ3ZlZ2uHGwim8dKHwV1
+n/RjZOIkYcVoOlhcHx0qTo6xTi6J6g+e2wLSw95mRfvEq1BxNuTB85O9Q+EkRtq0TRU+LoSqSGe
h+AvUbJUft7/M2zeVqYM5vo25Ue1KqH0P6igo+6YUPYuMq47plii1u5061yDJfdaXoa1Sd8uLtX5
bYhdliTozCdxFtu+7GERoMnYaThw5suqcs0QcT66SOm8qO9fnhLNPWoch1JVzELscCIvwTvg74Or
UvLQU+h6ilmHs4LkROIRbTBNLEuzXgTR3LrTNAAaz3tv06cTdHRg1hYPaoAF+OvzBnzXxuwpmDfT
dpJC3hb7RlAcCO8WKYJhuMvmLCqumLusMg6y0KDRhdG/JRcYUtIblFjhNEtqXsElGmn0ZCRC8YPu
CUDGQzTWABcKfSM21+YiK7QApwzIoDPZy2dfJjMAbqukjgp/QfLV1h4oOJJHvU51BhTJ2UIbvVc5
Sw79eQ/5gd1ZNSLMvwChOqXzEnFWIRM2T5z8kWuwAh4ncwPQJpAKSCEycoawQwx/pk3LuN0Ebtrf
8c9HjwVWjUV+aT5tklMH42OOFS+f4rLJE930gDPUN9yaez/z7DCqPKNFSQHVKMedMjpkBkGoEm7Y
zKOCqlfFj+GALcs6SO2NCN9VFUiV7h1oZI88O7PESuXjaL3Y1Cx2k4q55c57tcC+WT0PuWkP/f75
B0oWiFPFG3b1oY95nG2cVfWwgB/rY4zA9HlSa0dMnrp73bULNiPFQCiiFo6bfhjmdqp9GCTFDSUv
Qgwu6aqiYqC6IHNwHXuzk0Ad5UnbvqVZ1DuENbtRA2sr2Ubu5qxtJGR1kWnVsRFp+pK4z9KUjPb6
96+jq2hawBXminz0i4qdG/99/BeMS1Pj/k6KNQnSycMy+ASnF1/GwWWL8I/6CiDD2ng5L3ec0bWo
VPiiiOh8vdSx5UTHdBG3ithW61HHGZtmgzZhF6oXpJNPE5cjN9Fd6lpMGjzYfGE0E8EV/LOm6YyM
j6PxRPom0FoBNYGzkplcQk/3VvnXlYjPgdED7Qutn3Km6uIb29su8ULb8GAey2laLEAZDwUbD1M5
yHvxJ+klboxRtIdYz+tkVjUw0MfWCcuYzGotMsvKDJATc7jE9fJRb5ttDyRB45f+5KOsZTu5DoOy
12B5a947bRJdilSN9drC9qb9hABf9vR28tfgnHPF0AWopkhQac6xDuuGYqxRFc2K5+5TROY/9lL9
j00qIumGrPul/kNWDoZPYgEmm3Abti5klUjKhznWRGobawjBBHIrcMgCv/zrG3JyhpE2Mh8eBkqb
BPzJ1oOcxUiN6HPRUXf+WJD7n4bKRu8hjyMF864ebX55ZWcdIzQvHoxAIQ61grcNvyFxHaIzyUqj
2cYimYZqPAo6hCdyirWf4z13n/durv1uVxgFh+5/kWazWevRD1RDOzJYDWrwptyaM7cS6q22XTVp
jyYqBCq35rlCf0VrY4N3XSc/v7T43t2/n21C3DZuSb3MbCb2U5XdSph8QDVxIbV4xn5kwTyQ2JER
ApD2BcZVYGW/lgROyi14Mm8Q3ufvXbIDUBLabuuIdXT1/b5MMRWpSLX6OW8uHISl+urVDgbVHP40
jf+caJCX3Hn07Wl4QhemVu2uyit87LQ2OmFHyrLgMy+cdHWv8iIYqFrrgizruo3A0jOZuw7qdBH7
Vzyv9pW8uKy0NTH5T57rzHxO88+6Zt5+RgVbVjAZwErgS3d6O7OyuW86NWVgqc0N2PLRHmZh5Nhf
lsz5yqyH67Fx30CCxk6zO61nwB+wBWmAdW66uV7N4GS/W72aR98557W7dp0z3RfsO4G2PzgG3ttk
j7Tg1jLMD/HyfiR8WvRiXPUhlqsvvrzRPo397k8mitOgcGJ5eFLXMbu589amOJMt05kDIFEQUvIl
jEB3dxE1hu3HOiy3LXWmI7a7vuTtsnK1mU9EUfAcryOGKKbMaeR6U6QdjPC+XO4RdhJ/juC2YsjQ
pWoEHLOgveA0z46D0Ju5IHDUfd/KtQPtzi1EnID0meEXhfVdY0rfT2WhwOf/PWcWPSrR39tqGGlY
Cp+ex7FTI8m0ASRwzvQwzJGxpeyW2O9twgFttn62XrxJjWvsHjHQjeFsvbsYumRGiuJATvVTj53d
N4LRssbGNiLJ8JUZdudc5w664V0IUYktB9kcykedzCPPb0SJbbqqVD9Q7wyU0gTzHsAEcQEDQTg4
4HDZm/NsmxPyz7+aM3FJHPCzdQcfEDCFlLfSxUK4qqggmddrmRNwhC2ef6rpH/NnuloY08S5r2cP
toJzP08Bq2iXzuptbNbDP+h7QII6FkHrKvEbGeFFEsEKtjwi1hLnQhHU2lFmeAKEZFpo2Q4ShF6q
g7FqeeLXNs5ZkCNfXTBA53ccv9dXRSxU8CaoqoJ13kmwPszZqV7RKxs32rsNJOqVISx3lZzPhlxG
FxzuOEEyr8cGdIBxe21OHG2T5pCNyWNXNTGNxPFX8O8lfa4jj0JeiN5rUwsis1a7W5r2QJSbPMy6
UTcvYQo8rmOwHlr1y94dFKogN3U4BZbV3fhXitjT3yhD/xF3MM6gjOARFs19GgZVyOXOQqJyF2ja
+rOkguJo81MgePpiEIiwBPWMMBa2PBLx+1PazhhxK4V55QztCqd0ErfgvLvl5HXlCmFdcntRhY18
xBElfErrtBPROdFI3SjXp6/e9/zJpFfQG+FFhpdh6bdiu5l2utxxxgB0BWvdnmmEsUPEjLmN1SvP
anxw4ut4apAE/dtOPPwqmQfqeiyI3tkKxNCSzz2fhM/hUaNoEs/xLIfG54XfVGmQcRmKgpkNLyMQ
xBoBbqNU918A3sgbMmKSQmPQqdfxnqBDJMoke72BKmfdEBU6ku/Cck19OJBzRi/RWeMsoMTPX44/
pSXuh4UG4BOXmxzN939ZwyJv+9hYE6cP8KzkaHC6yLiak38OKWYUkWWmc/YnHWsGYbpTHQpAUZ9t
VCF/vyhNL6HamPQBOlbj7do/T5lWbWw42dUB9HiiWBkNIMfxdBWu5vUF+2uFjaZ0GkUBT7RFgzX2
y5DWNlG0ycJomogXcmG7EP8h+m6kD8EB4pzdn1cLnp8QSEI2rblzi3j8D+aIRI1HSXRmitZYJPHQ
zRiQK7ZL0fob3w/Crr2FHVHZswRo59+3nN83fpX+CaqJMvXsD/hnSR0250g4AAraJ+5upl1qqVRl
A9+UAfyhII32M3RU6gl6SOE4CLtXly809Ru4iGnw4V0XXMBNQTXAQRE4mZ8GXZqexGyPZudjUqZq
VnEKOOrVRlV6oJ0S9xZQfofi7XHo/nZdmrdw6ab4diXkAU/8eIEdNxCDvSVDhpzZ39tZEfaesPVU
mkahrRm4bB4/Nm6s3ijedMe1HU2wOa9DoxxtyCAb6xON/XVJhwwKZFHYaW0HdUgpU+eWjBIQ+QYQ
MaF8D+RU8frutZb3/xNhm1cN5PPoxiBYKAIpjtcSxnKn5HKlp8LYYlu/99htMNHmAs8VlPlErO3H
xethceVqvUbx4iH0k+Zp7lAsBBvOJn8LtZJXCQ2FJlSOhjAmVxoKD6KMsz5v4Cb6WNqlBBUjiXRw
+0LYSyQ2OnPdMlx37AeUTDM3W2UfUUzdqj1PCPRV6XD7OdlbiN/hp+IdVLbHUMu0+oGAO82wcJQB
jJk6cTdvAdiEjmfA27kK02nsAlOsxufLDlasJQF2IOQo6Mp2Z60kfnAnlgFq1LVBgl2rH5yrOZAy
mvNMgQZK4RPelu7IW9la/gni7CTBl03pCajBwPdJ8UjgU+KblJABA0l9J36Qr4tMxgLkYBRyYnUn
iaVKP3eTH/+2hRCBC4ZJmp4ICTnvKuf43rT6tEBKZ4bkDvJWPcRJ00lA7iGLYza91crEFKChBSH6
QrJFEq2ceWuynjv0TRE2hhbJksBqK4CdQJhoCoUzrJ64X/7o6VGWRH5GlPaUEBu2QLdbt2YydG/r
7DgJT4dG+ngmxGaTwn8WS8lKbBGAXy5Li9dhdugiOaqPJT2nlNDRu0L/z8W3Zd3ZZHQaWTHiGUIh
Vfnm1UfCJSkCaQ+cyBpe8cO1qCNOtqKG7ey52RLR3mS4yNr7kJqfriOMntv0hBIXlYhQLMwdgzxT
GCjgw+yaDoVG5qT8/tHtlNDIV6t27+MCDMFcea/wW7us9VEDW1Wm2vURid6PcMdLwybmv0gpGICq
1r+tUGuKQ6R05NPk48TwWsTNW2T2b/Iw0Swa1w9BqcaHPGWnu90KdZYI1L3kw7k8vt2KjzvDKDlT
da/yZqmNikKv5vO9yGJPfcoHPd2L0Al8P9KeUKyROFQuvHdqSwN7d2kDni9umxY5xx+ErFNHWFcM
UGFIzdtu5rkyQKNtFWMe95UjiVEwjr+TD0IjLZwdH2HR9k0KvJcDBqb9P8+3dDCZUStERkkKXAIx
yTiWuliC5QP3FH/dVC9QkX/s1GAYB+IS6VZVEtaQV3OZjJNJ2x1x7XcDPTeNuU4OZQ2YeuNa18eg
Lc7ro6SaYuxkdaE/T0zkXzlMuVm6lERh1kkc4kstZKBIfoL51N4Nvoatj94OAjCgB3T+c34r7dA3
XeNZryjYAYazSdvy3wXz+I1A/FyGZLMwqjXygFpg1LlG3AVJQtibTYVwltx/nSqPwqnA0uKkc9QO
FY+pA1F3IjYfaBklApF/jmi/1NqVvv+B6GONANRt17Cb57kKPevQin4W+HtFwMWJn53B+ph5ioFy
QEB/QWHPw0iX+cnTUyNzQZ/wdKxM3PvGnn38rvme/x/wtqL74vmkYOdsJBmzZa+O9y8MbeG2E30v
+9jts6ruud4qFJ0Lb7VEIB6ZefOt7qSZyB3aiAHpqJx4F13pzGMUwaXJooTGi+dHMH0rq7WW2GnU
2tyYpwkNlK78JWIU3ABtsyMHIJ/eLrMd6FkDr0lBhBHNr0ZMCb30814pa2HBtMgsdElEWZacDh7c
nTGGA4K8qaoND7ZJd6KJptgwvNXeGESaqdZoSJuGB68kgBWY4iQYSIWbMiyTkkGqhtBBpU68CRkm
sKYJC2kEmWWC7JVZL4fBkF1Hzn6KtRHEEBkJpVD4XzsskiFeBhNKH4R66IE73drZu52Z1xIq+Ix4
LfGspCNVT0ulF7YSMaZRKrMCdXx9TWVwRUv1zRfil6seigvfz9+NZ+1u7r1fOJiipk9eekB/6ZK5
iigkIkPcIO5fGL53+r2k4QY/gx8336YlBn5sk9NNxxL8DZ/UwrHjy8HX5ASID/qG4/nccjH63qUY
UoNZiItos1pdcrwUldPD0dMC2VB3ttygqcd9BAywfNFjB4vLtr3B3WmTEPNo5uMJHmsZIEhvv72Y
63eBGjNjC+aU5VPvGHJPMpWi9DTfgUkLHQv4gZ0wQ2ncFeYaahXYZbV38A4pf/n7SjE7NHsaQo/B
tUKwOkOKiyN3YEhzwF2QPbE4QngR2tTfuZ8NBnfouXLr6jZkMFNc3ByOEU8OuVb3BI2VnHT6cyO9
IPEd5ZiL9LAKpG2NTWUmCXupOn+CBEepyzbWc9o5ZT/pT4deYkI2hzfRwlPttj+oo3l9/eh9MUAE
o7ODpombkYx+1AnJgc5AAlIYgUqffCnCftaBumolKH4QBuEnneyVo3vp102T51woa3AaMIbtV2u0
3KwOHH3IlW42lcy3fvBo5RqjX0d2VuNtS1M22S0+RdBXCC1H2eTJXIFa+EOxRPs6NT/hfYEEfk8A
StN7SLJ/3Hbx0M31dqbnfmcJoemVjReFVRo+PFllO5Ba+eoQHvFBHEuCLry8Stx8+riI3e50y9wJ
BfjivWpx1wjdJ72+V1XUlXSA0KhRWm05ex/Yh2aAizrqsNOzVK3hW/jVWvxWWhLQEyp48WxQPYCo
SZfHLf3CaMMor/EPSo0yEbL4k5nRUm9SnH9w76Zqm4L1EXkdil/3pyR4X2eEtUu8s1uTdEyqFdzB
i3i/tJgKgU4up5XALaYqmqPwTmJnndZFCCmSaouyssKjquS02x+5gsyrOu0bLj6ydNSDExB0HnnU
POI1mL8nOkag9KXf7EvEqrFwnicySpCGzjZjNXKNV2Ao4S1d4+BXgB9nS5ObchtigdMFsYWaOqUJ
PYbIqgTObTHVqKk/QFXHfyx/xR3EXwDIUs8+F4Q6cKOJwYCCiTiQkq/h9+zD70YsRvpGJFUgec0c
nVFxry6QHbM6v3bJmBsNCCt3VhPgqNO8wTE7ijVEsEOCkYKunXCaT3XjNI3yd7PiIa0NM8av86le
wx/Sx+89GR1KhGvIgSNjbJACk8tQqFQX6Gz7fCAupOJnfDj1+1GVWXm3rTVZ6WT69ubak9coMNjU
XlabHK0tdOQRU+Cy3Xo0ILSUfBGJwpYyfZDZcTmoBNK5l3WANoGwCc+vyQ+VJgQiuT0u9Ynd+Ztw
lJ+JAsH8rLCsNC2hkVPuo1Bw7Nn/K5eZp8Eboow1S0D7m7cxBltSt8Z2ZsvnolW97svNeZg1fsZD
LixWUVSaFKqjmfomfutOrqbkXYBFpRrsD/c8UGq5s3FWxp2/jwU4DKaaLSqMeQgnsrdirF9Iwtr9
w/6xO0QY/UiNvGjwqQTIXd1jhUCl6A4IVB3EDzWG8PbaPxTANodtsCgAgPSDXHtNebvgr/5/67VY
2sY0Fxi68MbuYPttSU0ehM0KmDGkcSrILUrqWdp/y49NSfD2t4cGmm5VRVeg4yySD85uXKJ/HugV
UjFDeTrSr5Cbg+hcsF/M3TRvYcuW6MmHzPUz+V9dj3V71yHjqSgW7c9zhGJA9Sr36RLHdEqYYhLc
ewl60CdOzx2+TsI7ooPfFE02lkbRCsJYtQw0WqkWdBb2+zkaa6EWlbMPNTyf8RYkIYYNMiS1v8b0
Ol+ZutYaEjQiU0mei/7HompWbK6p+HNh0/NpruYRaUepbHknD/1QYkm9nZtZHDz6voZGIsryQRka
z1ItTDmi2CHDfCX1tdsqBV7vPw34VuJx1E/YEWuzsiavozFMih+w0pdegOkJLm6+u3GvsBxz1V6g
A+QYzJwzi/cqwQrO80UWKTsoLo0sdZHb2P7aqq95kgTvdC9IeT9jMQR72R9aDh9RaLiYDj8oYRkO
X3Tkm1nUl7M8+65i95k1yCMHnb3qZpikChaktLS3QW3WBGJ6gqM1My4GX/Fy9snnpUVtWLnXxIjF
jJ/o5RLaoCP5zOha4etHOOjvTz6Fp7TnnHW1kXBKLnEER/dc8B7JPd57zCDqmHofL373r6VNv1Vt
lgKQ5vZT++YKDrhFT+HACeu1R28j55Vs9OtXUWJffcGL3mUNmMtPvenuTmgb5EeEOy4DBhH0R4fR
LSRdw4+V56OBIFvWaspqKevbqynN0pMwRaoVFtTD6/nkz3XOL8fnHHDhcj9Sg4IhJWwOmwyRWp/U
nimUyTqMS+gfyrTzHZhc3pYuEIgD4GpPmR3jI0YVlpWaLbny1p/oLKS1YrVEJ3ILUYb8f8u0BTRb
A11Eb2NEJhyqH6Ifzo3l7c5r12c3hC3K/9lPLLVQG5K+51ZfhgF6D+ct+7MW/z+VwrlLk09qbR6Z
bJ8Ug9CbL3E4R7S5m1+4UrM/b/l5mbPhN1nuv6rFL6s8ztKJELIMBjuKdmTse+q547cQ7p1QQnhZ
Gb8nYRaIArIVEYqOHxUWPKgmabq4KG7yw8EArzdk20Mxje7zOwWrPjBRUHi7p+UWVbfKM/DhKTxI
jC9/ywV/DuvMZ7GFY0ylKpK4ds3dpEsyL0MpkV4gvMvHrcME1As+XaQo+eML+gwDk+D2rgb/9iPC
gR6RHHL+h4OW8uRUDuGVHXKlWDvInj7dr3ZnDPpsUYoo1scsPb4EaeMXeSvgnrAwYivKzm54b5dp
Kss3zirqI+mAYGtN6I2fFxZ4W1fx+KQv/oGRz/8scfimL6ebAGZi0A2TUxbt+bI4+Guv9LZ9Gwlj
AunXkQ5VSvQjlYJugn7JihUk/sYH+VdcPmvDSq23bRYA8apgYsMc+hCvAl6qU5c8GLAAWwAo815U
RSoVQl9xJKG3GnPUfwN19uhuczSDZIG5fr0ovH6Cc3idOdp1IXGuz0ehgsH+tlYk3B55TLFb4X3h
qv5IG3q2PiYuKewEy0Dp9PeEE5s+rpi/AAc9zF6vssSjH07+xx0uC9S276A4jRJWt277cFq118Xk
VELQGb+4CVyULbZE55Vv2uZRjt2WTaQP/gz6prqWU9PoV3jmOa6N+Mnh/7kQ3c9Ahd8qdwn9fz/a
HD9eftuYgcFqgtres2AEaCdTYA1EiccGuu01ct9q+nfCqRVpe8T+bN3i+dyEbUioZLwG+FxjXf3m
2YnSeROIK6A6nB6hiW+oPu8mVUCsL5FvpwsSSmcMGACkhkmUSa7m7yHnv4r3yrO8hNqC9Qr0OGrd
wiC04LrjO3lXIx9coZi3o9A+Xe8WuyP52MacAcQqrMALC01sgT1QIsSEl3PcIGIdYBXiOoPNZnoq
yLrsrUJOst6aUf6M/6KX/L94QPNqNYwKRfDQ+ExphSLYXlWzN60eGoTHNSiYWehYWeSLNKAenKMM
hJrLC2boMRsfqIbP/sjjxOGoSOy+YTEQ+6/fF9UtG90wy+KBCFd855C0p7qA+8igvG0/6NN4D147
TzN9jIh6TmB7mrGsBLOvpReDl7FAIgNwgeVBMiTFvu9h4V/Z4rQZQa0gpR2IkSB1lpRlG9DyZU1M
rn2NdjoP8sl9S6nKBJpcu1QYucstkNxS1yFuKasYDrr2oGEuQ2Cqf6zJ55vZxfCVOdhygfZSFBAo
z6hq3SNY8/uNhSlLPn0Oy4/o6jAP/qVRbXLRlYbttGUfGRIcq+zpkG0VFjUh3dv/EEVxiCIpFSCX
uxgpkRs2ClzDhfTQ0l5Jr4EtVFaNXCe5Ileynj7Aylt1b6brK7nH3Wc9mrs2ZWOshq++LhCGHlmR
VzSPdF5k2bDABw8ZNsy7zJXwYm+Z1wGaN+C3Bt7eiyVTsKOX4u8qGLSQsgXnGDcmDE3B4QCV6RoF
Dhowztc4Ky8BzUM1KzU7sfaMw36ml9xikmnkhVVhRNlNBKrRd+88VL4GWz+dpMe95y7vRZ4nWiN6
kv3+n3jFb5GXzglGipS/RtGA51Vt5rVUcZngLozrjKTPL0cmgbQCKFXw/wmJpuzUMnzuwTtJq1h6
fZhB9FJmE+hn8+NBs4PMtVKgpjKQe1RxTBDptIpLrB+8KRdvJLluZ8A1C/5qFNifGNkDCd1M4Wkz
ya5Az9IK1vDnOE3USbST+DqZpbQ7BczR1V3itKUyoT2YrpNakSVrYJC4quevaeTocHodhJEIi9aN
oRdhyW9MoCZXDVdrQ3neFOotPiP6aBm40YN/9oc0xAwLLMOkpI7EBnQ3piZOep+oRFMi/RYldxEB
3TIIUp1tGPa2z3/f7ETN54SPaqCMCBp1m3wsD1AO6l/O1Q+fRpoMOZHUmt3cbuZm9wXDkedF1gJK
ROXs8xHcnn92X/5LmGkWccRw86CeUmAjPNW26fml2gA5kHA2uwbuzvcCx+2BVVRLiqpY5vIv9Y8c
rKj2+yBPo7E/+sv5NxhdiahAatIlmPm+2tGRaR3t0BL+XzJ4NuS8m53I9Yfi0ZpJcMu2s8Umykhx
WMK+NNbv59QNQoOjWhIRc7I3cVko3OuyJt05pB4OxVxQ1ikpc1DJsZgKEO3CVNs1rFdEsL3vg1s6
KpCjijqDMA32K5OWe/1DvfwhlGVX7Vq+PuF0BhFzf0bJ+S0bHx4nw4bpcIjN/v3keWt71Bbmz/OR
JeQ9Qtbx3glx+rlEhRyAHzWR1VSI2X5A1Qixq7hfqS91Q+GdJHMAKqUwgi6C5m0GkCkx7lrREQAc
BYn4y7rcUXynj1wN5QWzbe+yhBJ+ks49I57HCZnNSIExqNaStE35RBdXS/0YsZbV5mySBm2mG1bM
4jObjV4mOuDgFMmB8dr/PfXgp43tt7ZWZsTdSOxLRQpFlKrdkpx2Saofy8ezcwQ3QWyyXbZPAjAP
vR2nqMx3HbtwDV0g3nSoEjy7TT6H8oPCkZQ8BjZDDTWHeY+Q5L5sE0K2smiPnyeiiqCL2coRXlct
ZNFLP/nzDzwh1mlzJ15p2sBas/uttC0OGCFsqxsEg3+v8zeY9WYrB8nj+m9klrkdGhVHqxgtabPy
iLlulUMprVFzW8sRZo+X6SzMqHmkOT8590bLWIoRagVzbchwNX7IFvbcprQJNMPUiv2mXdTW70Tx
PkBJ6rZeSEi09LCG4Bd7XqtrVZm6hn8UNl7C4IQpGP9frJZA3uW046fKuJP56KrmMHSZQF9ne25e
W4oWBM1mFphMO9fgh9c5SXpndZ/uOAbcYVM4WSIe+3cOWQOLgz/c5aCN39Uahsaq+zdOCYiRzkgh
4LAsjTYWb/l4DZ1fqya1YTKuc3MwcY7hLUuBzDaQty5BwHN7ZwzcG+QELxIgKA+l7dBiqGfHRmIT
SWkiv+R2fJ0Tm0HcOdYVigTzz2N5unN7BlAymOjG+ZFILimEtJyFeSeZGYvmiMdjAHQPouUG1xYp
mo6hfBaza9gEa3RR4xiMMAp9jlpXrnjcSRNeCACyLj0GJia0rsSFVZAxG/fEuQFTkEVeJliIa/1X
VhmWDilZmXLCcHM2K3OD98VqKhMeI2/nypDDsOD4FkyCWr0TpdQ+cVep2yf1HLZhAQtSz5UdMAkO
SxHkpkMObsPG9AnDbNpRfAoTq15hN66kjqXHh1vXuD1jhlqqTqEqCVs6mwmim6jb5GtgwAkZENJF
CyTODBsW5zP3Ex02qfRUHA0r23lOPKR3gnqUkrQf5IRTz/FWA78X2Y2GBxK2wmCCvEDhI1fgzolx
6yIRgu4JUsgTWckUTSCceRKFX6oBwvDUQyiI1Habhx/a+jKN2IwcUDd+iYyoU+m9HxLq9z4AThqt
4DNL0moU01Wn2SLRzjNCgUFNd9Nh8W7jGR2cWfNRumEOSUDVaJC/2H889qht4ZSVfruVTj3BKkmA
6ET8qMoDcNsJDIZaUlk0+MfiTcDPb+JglPFKCPNKEuXgbujuZAPUFa2+QoA1eWXeSK4XOquNtxKX
qOCedBI+qCiyG5n+JLAmo+mCKlGLL4ksHauzCoJUjFbox9a1kHHY3PvFMZhElk24nCi2CstyneGT
0D/4JyR2fd7nB0uujj9Pvd6UY1p1zaL1Obe6pOS0Y4efxuDRTVXx+7VBYxgNhlG4Z2mYXx7U0Ge9
0jiEYzamlcfRVHLVzbjriAmZUfhVxdw0bTiY67VFXJan5tJ7h/f8CT9jVPo/3MinWFp1ICeIkodK
Ucxq10VV8qgFXEtSq9zLeAjGWy53GEb78GGPsx8+4Z9YToN7JLjMlefcZaV0KLM1ASPQ+GB28K9V
us6jphIkZfL5iIUv4hgo5qiO5ksFKgRd7M2VQrP4Vx3bGOjvWwk/Wtxri2xokDAm3KujC5J/PjKc
dCUcpazCHKegW5DcVUJIeZguaXleLwAbIe2Dm/Rsr+qNVzMeiO5rSXO8PKQSu24YAPvnpAhQFKEd
c2CCDDtpPdIcVUVJQBk8km3gzGKHq6RH1YS9ax4TLFeq62vw+teLUlzViFybM/qkXRhmFMnblxwT
xjYushKjB3fDGKgDSgp34KoN88SPgnZdGDmbgfLw8cD8sFS/5SbAINR+xoWF6xbVA3QPl9qeobDb
O3fnrA4ELM91a/fUIs4aWxmyZ8An18YSR+AwsGZCsajXu96vMwHwEq0qPcbNglkJ+kYhaGmDYSTl
R3lkx31s99EP9tVbb5m3ypbJbI+Zagjb9umKbJorkTH/4fpAGs3qPh2CPmcmcgFAEAW48QT+y8DE
31SgTJNf6XI42hYexAXvSUq70KQiociEoFBR1/15om6yWKPtGKVR/aEtoHMNiOtaSatTr9HGyoTQ
t/Yb09gkbswaoJmtEcbZPyyUfUH0X8GY6h9gMa36jtSzzCx4d70DY6oUCOTsbLZY3XwJK8qhaQ8C
k/Sv9uujYpfGfOuiwl+a5yYUzpnAe40KU4nwIIKqRtCriZiwFRD7b6KdpUzj3NYQx2GZIdso10nY
I/vJUVupq5nhWjBE3W0eQCRkhrCUPBZ4CJbsji0NskGvInD2Rd7DyreUQK+ry/tQnt8Sq2kC7AQX
JmSiKyjXyyU987Ro6C55E6y45Xber2SlI0rKrNk7B/JG45XRagzufl55OlrD1HQSdy2P8kQ95dib
U2oVR8scvJGlf7+GlQNsQvqzvuGbECG+46t0Pvzi8ujzy4IAV3IXLOLrHthnM/gAXwKsRrOKn0kO
gWZzv7sxIB51eodkBeRsU0IFKdpfJbe+rHXY9zjCBO3rGxCviVsOlQhP20R72NYx7EhrF2cUP2PD
ZfO8icyP7z9gIN7kAB8+GiiPTgRQw7wqX9dIVE6ax3Cc6UhJ7uKgzirlTrIVg5h0pwBADkbH6sSZ
9p+WeGRczAlXmJOI395TCAHK4koxfALn2M3e1RqJ0WiGJblUUNQbpZuc1c3pxFs7kH6FzU5WbmZ2
lDCj+We6b4Q24E+T85W2U+zg8c2dtwfC2hsx6IwRhpqGjcuVHxvWHyUFhRwqJT68UsqhR85454xd
pDqxq1AyJGxr2/8PS5bdKmRQA+xV6HxyNHnMA0ZQs4q9AeQ1q9Z/CEtDFegC0z0d22cYMw4lQncv
URUhiGKUzwO9t10+jL98f4152TN/VGZPs9+tHlN6EVqksSuc/wjtNZkpAJivOHVQd1U4q6P5a0Bl
IkL95LSN77wcpQtol3FahE5hEHcpkLwmtuJWI44ie170OfQ8P6Kpoc90lvTG9py1pY41rtAIZLm1
xI4ptWCDkvt9P4Y/y54v2/k0xvdlMFbuKWIGQUGGDw68F78NAgW81+qvqXPg9CHHxEX0c31KOShQ
wONoFqQYkNzREoD+2gU1rH85pMYtV5Ggvk4Yt+9cifxka7iD4jnuTzolu5G4sciLFLuKrFP/zajd
HcRRE86ea56qMZMRzJ2k9hgB8SqT8Ll1tJ3y4EwUCf/Xegxihmqhr4+grBZpXs/Yf1zvYyfE4Z5G
xUD8WfLJER//MPMq0yF3OVkTBhkA3MTfR/TK7WWz3T4D6sJlrX4Vj5/dBxrhe9ycnNc5VrfK8K/y
5HwkRCdo4u0imwvmesygiTJfLfIskwzOmX//tBV2g2rtBNqKHk9CuIsmi22V5PCAB8busQ6Fozq2
jkfQmvbukxML8Xt39QgYJpYxa47X785Iz/wX9hD5hf/+kNOfrHnXmffr+Up2sQHwC7D54zcn6WLW
qYIQ6Q2JJcemYPPPIRECMgNleVv1ISQEhIA6K8u9GZxvqGwzoRSm6EpwC1Q8qsvj6hkYsEAp55jy
hCAYpDcovqXAik+e7TPd0mceXINXJRP72Ppfjh1l9YmiNVOclcWCTQB82nYDnfFC0ZDBrxg72Ov8
rch6CxlNPG7js8U7c5R1oXgCxS6qvrXPg17Qj6E1ICfVpe90jylPcN+FpdJYm2HUySP8d5bYgesg
KKkV1qwupC+WV/qD7imznvwwL6wfSEDB0GzodVp08+CdgoOh++NuHi/3iobuQ1l2Jlv905m26wnv
7TvrioAk6YJaBZrw++2ZzhXl+TbYTd8Up68QJDe8CdSdARBdheiFzD5ZdfsRowTvF5GvlbyYyyFW
9hJfAQBjrrc13lpvMCfEhEnhzCkM+ZhC6ZjHxyaEB8qnv3SGJ180jWFYsBZORO2CLp4hZO7lgAVW
j2rKqSOAPuS4DPhdSvzWCidf9rUf9qPj05AIBmtWvuZIuX6pduuvj0F9cu7ZN9462h6CgYMbLSu+
Oi788EwXwjtchoy42EyTPoe/g/CJV92XoxRWlDToyX/k1HmCS2yK2Gum6zeG/ln6s+TOmgi0e0qO
IkQPGvPqvyH0KqZufVeQLWB33ugRw19SC61p2pn6pVjVN+iDvhpINYgAaunlA0XsE35XdE/91w63
+OfVbOFXsDE2+nB4azfHJbkUqs8HYO+z3t8uNSBXX+mX/fx9LOmWfR3pBzHMRAP1q0QP+D7CSUMw
YhBCNI9sHIAqANYcdn2FzewPv1jU1RKfiv85GNx64768bNj7urg0PwyOkiYgEgMMKPTzZUr971WO
QC7zVvsydXVXZyWSePZMuxTDeVTOldxCc1zftOlUkEmGXss9PRcvz0oJFd0tXS0AYTHL2Zy0eqjo
DEb4C6eHbeq6dX2o6fbSFdTz72u6FhYRZt6fSvNnPVduqHyxOZ2AVjWdXa7AR+y/F065fgeS748H
9cFYEye0Qqw27zpW5BL7I9Mti3i2ya52EqQRrHIbezv2enE+IBSMdektyTcMRHV07wCWF0Ch19Tf
MQ700rhmWVPSrWzwainmUyGnmB/pMLS1iYePRhXBycAYqilZqCnu4kfYNVdxnlShdxeU1/z5f6GA
b/A25BS8w6FUsgACY3TZXnvUXMzo6vNiYhVDp0opOgX6dNNKlXe3oOHrbYS6hkDuZFfouenKnF4A
h2VKXa69l9d7931pBPsw4pyPCiqP9PSV/yBuEgznTccfKOHjWiCuOClj29o8Lfs+62MsbuUiNa28
MPxEIL2oN5iQiglzRmXpkb97YHrafndOgl1fnEyDrg9vNe2YujnmmyONnjWyzhY5JJ/PLzlAZKJv
A9/wTMRea57NpyxHOsu9iAdnRGPAX/xBFRegUUOY8487tjB+wmET7mw8vHNWPup9h0xkiK7/r1uw
5wBPQ/g+/0skhhCBCeF8SEhIv4Kqv54zN+HPvBq/7rOfs+CW7wd7eI9AEDuLwEOlFhLQvXn6z2+S
0Ij4jD2k3X/oANV0RedZoPLor3WdbPVEJQMvucaIEWi3Q6DKKxDWpHxgNUE78/BIK0Sc3TxLyrZM
UUA5SKGvJJ41DbYJ4fDtqI0HIDgTPbj0CRgbWqRWY/omGdES+aWp90kspaMR8vnTf/X3Y027qBbN
mhEtPTpYOnn6nVwEau6eicycn3EdXBQxkHl7CS/lveUJAWMNi7fn3d6mRqlRdst1k3NpkZoEJjzX
xHSFipxRFnps4v0ePE/TxUDdXRB9ZvWLqyQEaKekemE3iLCjctvp0sCPu/+Jw09zA2k8/nNshv6h
8FF4tsAivvijhocxan0Crr8j5InoPp0DtNCaBMhfAFUU545ifEcgI94KkSvMMBELViWvmjaajK8Q
OwQFau/qLIlWMnQXs6t76aal66zC2o7xqPv+06cVBIifEnOiTjbhYS+sOtoPAbrOVGMns5GRo9wG
js7V0w6MXNme/Kk2zB8mQ8GVxei1kBylH3OVVwP4Xe/JC7s5C9L5iA17YM9cu4x6gmeC5EZ5Mn8i
/ZYd8mdRXaFKdHKIkt0gNHsIFROtcstepjonJ9uPY6S6JP5YCHpw9pU586OJUIy7WO0eDy8NbDew
FQ1Rq5QM3okVbDFrxTeYcxDGoanV6oI8nuGxFJjqBB+ysHXyl4MoLkv8WFCZYtFznb8w3Wr696+j
/2nDVjRIuRaGRVFKln75/OJ9V6SOJN9w4bYdb2hklugyT4GmR7AkJTgZhAZuqnYW4oPfH6jKU01h
XwSwRkeZFyF4cqQObwwehcLCMHeBgC5AqZwRFl5RFoP6lMEzTEpC0ZzgxSnDgjCmNhcGr4S8rU42
asm7NlfGJuVuLg9FFZu3+5gBm13qD7yABfaDPXMdgv3wNYGSE0AMbtI0etqypMiviHv5tT6usq+i
91R6dhAf1oM1TOsPH9L8mKumnLHl0Ma7GWnq3Mqfamr6DZYTEKn9v0Zo4n9ZUh/HoJKhclgvwW3h
tQW+L7GZ6np2LUka99v/6TVVE0yX6fFjHA8aYX49OqqQvdxkF6IAdJ10b5t56FWWFVMDdWjYXJIe
aWwxhxu0zQt+c3d/jCeu0M+uWfez4AUGj8zZfqWV7VFAfxIuUVTC1m/uUcb6OKnALAYpPj1VS73N
m+ajBmr0uv0I3AUC4ZNzozi2lprOiBCaTNj0IZlFj2LAF37a44aktYSmL+qybabFi628P3+Pyc+B
lAbAVKvbN0XIy0XEIXm5+2UX4ItagK2STNIIy8b/BnryVRL5ZF289AlY2ShIO8S24I4sjWhR6/iW
ToI/3EBeb3Tt5Kn2la/oBFfRR/z+lAeD8jwBh0Qi/UjQj8IsJStXq0RtO8dQmHYKF3yu6BjYkmrE
LKGkJK/KogH5vNIK8eDKtPG7s9pZKv7N7KY0t2BilDsTGD9bKRLgLakT+PdCMOuxJd5VS4wrAMo2
FMxUz+3m9ZDZIqZb3H355+mfeLjXRXi/L/0cm3zW+ecfm66kqo2lQmEFa5CdZTiA1MCV662jaQ3c
oId+dtWDOJMrd6ZBtsej1xGwfrZdHm3TRwYAW/TzPrvGAeKs5Jsu/9tPyH1ZzwztPZcksglM6v3S
92QuLIoUyq5TZw5K62o3nI1Jc5JgjXzl8JYhtsdbM1201v/mliNyL3DH3uWFuPvQH38QgN7IHrVw
ZYTvp+jWVH2ykDMl0Mxa8NCODvAoKi9nWY7m28x85Ye0t5LvnRD1pymCdkGmswtcP4FPfe3GYCHa
GHsPBJD3vx26MuqyTdFDLHZ/Q0yw1196sEKLkpMvtugA7VNMa9KUJxIoqLgwrCNIzd7Nme4pjilj
XFWqZxa3EAWyEh5N3gIEF//6s0Zl2ncAavd1YWzy0Dq+RlPXJ16FP3ENkDh5JXWntfzAoRdbM6v6
ayd3U0OgxE9adKnRw8PoSoun0jhRwpUayUY0yxQNeypSIG/2ZauLJXE7nhXwK+Lo8ABngEA4Ktzw
v7Fj16UHq1KTMf5R5SQlNBAKosdp3B4XWmJjjSi9V71TmVXSla0Qum9G3wNMchGiBv/7mtoJmwyn
GYEnoFF84G8yY5Qq56uG5CZeeyRTZ8zCMtJ18atBqWEDG0FbLxsS01fZ5jHM4mrncVDobYhcc3M9
oTQJxJcHk6lp8oPqfZu3Lyk7hShMIqoM5FdfLnjOJUe25LF8lmCYim814R255LQYgdIb6Y7ancEL
is1S3VDTvsZoXNtL2E2S3ZCwvWekfVMVNI1HfouMLBo2vQ610jeJUq8RQ6dZBkHHOpb0KjkqCm97
MhUubQkvNVfp+of0APHf+4888jAyTFrDOHOTof1JokSwfhEKGMyu2nIZR3BVImJAD3uq78Fa8TUn
owZWl25qy88aE3GOtUexLMVv0zsVjUHE5IEJL7/EiYjIBlaxEyoJuxtMizveJq6Cnlr1Tw/anOH3
btbBvWqbSFlWv1VZKvnUx95B1frbN37IW7Le3KWB81Wemo7gm0omI7A3ZaQ4oh3mMsytV7lCYfhW
xblBxsuNp2ImeiBCuuBmSKXxnWw93jGUCbrkSXstB/rV8xBC5tJaP5jteQDSgt2fgIfHEoe0M3uZ
XmMy6qwweoYufzpAQ96GSK6AdckKaVKa13kWis+IQ/uZQyxtvKbo+g+CoRBqdNlaksYwsdxN7dB/
plnr+MxCi+KMonz9RF+Lf3KsIuyfzkItQSmlOEYWcPTXPxCy05VmftjrxF8NCt8Oq9bIPvTHSKQ/
eoFvnxi0N8mdUI9HoI2V7QGCI7vlkSNNIYuxTbTjFMmUI7Dv81RhNfrMw5OqMsbrQwcJxxj3wvba
h09th0pwYdkH5WlJonHJuRDGcfZtVkFO9tcBcktRGtVyHRqPKW3WPOhlJ1CRxT1q3rm7nTuHdaoX
JS3SZn+f9LusJGZDFrs0vUkwYu03wlvWGu4Lr5L79L/o6X5kRfqYFAZvyz0XxWQ1kq6NSLndu7D4
Uwg9IrpKT9QfYsuyhGiyV9PtOAJNGcM9stxR+ksXcyL3SPGKSRl4/XsXUFWui4SUMm1NnPkEfmF2
mDT9U54uhlXtb8cqLB6ZwBLfgdgT7PPFNlxKvEs5CL6SwqLxuUNn5QkUgtwjLghZi8TwbE3TWX4B
yfSAsI95TtQh6m0kh/LlHxCqOO4GclfJcpvqY33il5VgQkP7BLkYD2wTHK8RZkqXUq8nrCCTKlBK
L+e1bPyerXJ4H87S4mCtuUkbtEJOT2gY4LFg8CBK8FR/bk6gWWC5na5obQ4te+9eQhbqoiBs07rS
iu8RkQKgc3cdknhM7hgZmOPoFgOvEv/FmQHpMbU3yfEmJyJC3mGsFTapvqFOTZx1nhPsZe2/oxOz
1M2D49Fs7UncbHZ6e/0o0gK946eMVsGYbOoB3/jLKLFf0D2rhlsfeRbiBR396WlR9QXHV7z+og22
wLB0thgMpS0TMvermjBmkPUPl3n3Q8868avqZxyA5uJRvPAASHvXty4IedETyOtMs7JrtoQc6jFm
2//LfKacx/IuxFwAk01NFbrpCakSjJ327TRGKxXhpfvntTVC6MaCGg7s9DOKpusxorl+LDB1jLdy
mdLb2JFIULscvpy3iCLyOXcFfA9q+wgtxEzGwPJlBmFT5buocW4DO9Jq16ugtduAXqc1hExZLxth
LdvnrkIOHMX80VWka3+fNclFj+HBeH6nsa1Lxkjzw946N6KTIrzWFMhjezNrpPaAsd4uhSt/Do5v
6Xzcr7IdPtsn3sS04cvcRQ/2s7db3zFV6yv3jizVcLCiyLSKFb2wrMjvnS2WguhRjn3KMGrOzgjb
Oajtu1nISPL6Kd2bGUjPoQS/rG/HJDtXVWJm1er89Vu5Pss8MoZQoojZuuqkUlCEhJ/DDQbOxkJ3
Ggfl9rS++kVqLX6YQGbVTSxayDOxW9x7uuAFjZYurUcCtAxHk5fHUd5pXLXB6CynvNdFI20KTLZ3
eHIFRyoTT92uJ+APkMQeroomwYcFDkxlgkHmbordW1RPkre1rwlJbHrWXJ7KDfNIvfKAqVF9s1n8
38RbocQcUcDSiHpnwuMUCbQwe4Aic/TWKDjeEidYZCBuX9u5RcKnuOhwjuUALmk0NtzrxOSQBkDx
Tx9OzYhGGOYsxoOLzaM4B64D7HZ0yFan6QvHZQgO52PQqWjubcnw9NQNKRxcPB/qr2CuUY4Np6g6
QghAVZL5c0xIh+DASQ81xGHcYYO+xFxsbDdJNRrtAWifyLyx3WLHJm1xSxajTQRIH7eXkeklk8N6
2j88OUvFe0WgEMUMCAgS14w4n2zybnWnRA0Y0615RLenrQmiVU3icpTtEPNZ9/x/TiWlzej58Go3
H80HJw50YzvhUaIx8EjgdQtN6CarZ01EGxdN+PKMABW6WXU44FmAJJPcYMlAMT7CjAv3QNHTL9T1
rnoIu6FjdqHvfVGvtphzVjcncBfqyhe1uPaBV+E1M8cUI3e9QqmaRMbg+yeH9u+qqKhEOtqtUCOR
LkoP8AV2/cXyrPlaT5XVaiE1JrjED+t7wLjtixTtPKeCZaDsBpUEHGgDcQig4yNAaXtWimGECJal
JbXLyDsajDcQkHAq1LlVFlJhFXGkcOIWgoU7fUIvtec2S5/dqrCkhc2Kq2NNVtFGyN4x/xstugGg
1kiFaOb91c2aximvRO1bePnejRcf2AR2OMbqI17ynv+MjteTWTQds71AwTjo9gnDa6RKtadafMjk
jtHgEKS9XCl+s05E1UpzFTKROXnKqaDCrO0cb1MT0qITNyvH18Z4Cvfs4lvY93AE09NSB8a4YqHQ
knRgsgQxH8Eeb92E0ivqEBUHm3crV0Ih7hqXOdvd/K3WhNre2aEeQqc9beXyK+UL8s8VOjfT74Gm
mxWqdu4TJbTCj6Qu2KAtVzoGVcZIE2R65QCpJHz5zBQvL5rdxwRqPH3pcgO3nQJj7S1xLn0AB4Mq
ppJgH2XUoIT1QTJr2Qvx+Syp8p47KRLWPRkJ7vKKIj6rb1nm0foUY3OBrsgOlM8qzWr3oBXAC73u
gEYY4a4ZH6kakTbn04TmgP3bID+RiUjFTHo7ti5m7E7btSqury0Y056QgnGbJfzo3O4MDwm73f2u
4o6zGq+ESmk1z9YstONZKsonCixcQoIQdz7AGX3EGfasLzM33kOxhdasoPozwL7L9xTBK20Ct3dj
I9QvngBJusMf2ZV8J8o8BGUZLgol7ylzKm1icaA55KCb3LdXapQCyoTJs5hYTVRf0QVZSLsIHieV
iqkJUpjFJ4cfWh3GxiSxFz3D1CK32d0OCWia/vLobNMfZw28cG2nJoYLm3Q1OkrTVIqzkrC0yMUs
W+ZpUy7rgYwBB9pza+wSNkQh0gfg1F0IX9zdRvAr1bZ9IXeN+MmjJJTVVxDx+tbbA9/ZeU0jYmTM
DZstOiwUUv3PJruQb8uLyfYP8UL/e+RiGsFBs6K0Wi8HpE6VSM52TcnGje534PjzBVhvYKZzvidl
FGIArU+gXPzsbm3hYC2VeFZRrlWAKHVialDyksqfdg1VggPm700VOaHDGo1TN96ssIGCyOMTpteB
GlA8huY5aP/o6/hpF6bI4CqTKtBLIzms0Eaw/robm/7zvuh7YE4TU8comcxuqHjpXyWFXy87SViL
xiwfYGqFPAUWurrSFpa8/cGLdEtaVewIK9J9a6pU1VNfOnaYH6SHBidja3INJ3QW0aPs2VdMgNPk
XxYJUoqV24EZ1NsJRsRv2ITECd3tCG/YgJ2ce/uilKywLj0FDGduQ2d+k0AsEqN734tfUyzdu+yH
WUtxG3gu42rk+Wv4t5zWpfsxEJRIsVLZYKUvGJC2RgTKXbhCEJ9gE9Kn1OUlGZo95cl66MDk3bhz
NaJukrJzOPZL8yhGQNZnMQkhdeKVrleaNdq3nRebA6sPKTwCftqCwCibYjalf7xr8Vc2s+Xo5who
00RZUi45LrW3jpmPBlhNoAxHr3BwmvYYaRHdnwGZVWCufh78eda3IyYN5q2H65tRoQIY28ZoWmxz
Th17PGMS3mdOro6bAiMmdXTXdeL+vnDTZXiI0pxq0ywtS0xbEMh8N7Gi6ylQNwRpXPBIt9O/LCek
le++PeCG5EktTJMeLFdRB0pwfAGmIFy5cLgXE4MsHvo8rOyFtBfxSg1tWGLZE+BYy3XBD9vGX2qb
48EKbsLi4WPfugppR+J7lrt070wastWyykZy+tAMrFc5Y8N4mN6cd7mhA1GvhS/lOfgJnhSntoMV
9r1oRPug28FHjAvlpOt/Q29TsVM2d648fW626eUc0A6479nkQr2zIsKrTY9AjSXO2kCnNqV1N999
Q57q2Y0OFut9w5YzlZMFAS306EaJgFWmDSU7lq6WHeKT04XXfAm5QENSFOocSZ6ogHEwDAZmOZ4q
3ufBJcxX45ZduUS6tJFhJYkvQbYGXpYF38KxVhnwVY/Sz1OpMfrL4w+0lI/6oCXuAzSa0HMVw+t0
wGxC6Grk1nIH8tHrMlA41OQeIsAOCKI6hcDt6DbRlm57yQNTcf+c2baRSwnsr2InbpQ0nHoLTxsr
zqFmWDj/QjOru6QWnqaOvLHJpbmLh9P65BxVL52Kg6u/MU9ZuPsnM7jMejay2q0kuZ+th+2RzyJc
OW2T/GYoZdlYZjAG/NvLWUdBraRVs3t4ErLxDFoVSQkAD8dJ+HRSPrQwmtYHpllB/42m/oVhYmos
DbCyx3vH3cX0+zI0vpGAH4Zo5NKrLtuG4w//dbUNFCVWLt3H2mtWdHW5ygGudIz6T0nwqFPj6ZBk
fojgF0OjrXVuCA1wnhoK7MC8QbG0Afdfi5imwyKnXuZ7BnZ5BPcj88JFlcHM/wRVIIZ7CR4eqna5
crJqZVj2GOgMfx+nq7gMPM12U0VyfjGaLs3FKyle62+F5s8wNpopTrgoj1wFqr+ZwxVEmL6Mxwd/
LkmusnbZr7WhvGGuHWXpUmD27/awDBzVyvtkccVZ5VDFl1Tslk2j89YvyxZOZkFPxq5sk83sxlXk
ov0JqanH14Nr+y+snIzBQ3kVrl4RcfSgj9wjS6WJucRRaXw2/aax8/UhV5Pu4vqitzJevGChi69f
pBEJ2q6+rxQvZfSf20XA6DfoD48/m4V3ofTuT9UqHykiGMBmLPxkyVsyeeuosrmw2Zkd1GrORvlp
4S2x+0IHfzBp28Ykd7I8b6vjLp1MkLLGuPLJ5IYL8C5/S4rAyXsuTRfnUkMQ0GPnPS5O/EyK2hci
qZ1JlIJww7ePu9aA32fznjZMWZHSAV2NbTrHqijeUz7kMpV6Xtqz2ZCWsqv/qKf7tZRNdAOMb/58
JIncMUCfKJrGNyh00xs3y/TY4uiuedjkW4ylNArTBM6OmwZBYDWqVV1qhjR02+82DHk+LOHAZrSe
wpIXxCvN7o/gGKT0zTmlfLOL11u3jZNMP8fBkzWlbMHwspfnwJ2zqb9t71xSNiVHTLpMcEKMODbJ
LcvW7CO0tDpzTooRPHl4REDILA46OuuJAORPsrHxb7mH5uPShllVcQNyPyvZRVQFbfOhNdoZ7L0Q
9QvrWSrhFdG6iYMgSL3n/EVjjoaeoa2XMPDf3ST+1BSiDsUjFUOlC4M1jBsJHo56fQ4kqE7Wubf+
TaguNyLF3dvnmClE5X7Prb+tBhgSctmFYndul++uMZSoXSZZQ5hjeBOuUKhWGses/ikMpWSE6Sq8
94GMHHVUJXngWohLXO6z+UDOIM6D6SLMaiuhPtvRCWdz7Iq84mfYSonBejK4FEbpwVRglYJ1dsVg
KundW3wa0RV8tr5GOpgoMmgY52kUN/+cX050tM6JT09UcmA5adLlUaXNlxrb6VIZ3SWwpBs/kgyz
3Oa2OC9bgWDYVcKdIR2XL0HJQfv/UWZSEge+trNk59dzslrdVVqD8Jv32GD3HXKuKRH1Ly1Qo59z
kJNAyMl6fyT4PDwR067ctq5Vv/PvNgTunIFadz2gYvUQyBEc3K7xpaYRoszK19gAZt5tyBTDQ9yZ
t5UuiK77eaD+6X08oCrD37DbdtF8RaKjEZ6zf0Py1Ps7k4eQAuaf7yWK++Vb3Bos4j70PUyU2gZE
hbtwzXujeLyT1vlP5Wt/s7Pq+5ZKaR9Lbv2MUpUkClsTjUr/J9/tMyYl6flV1wkeb8kPBTMPMFEu
oFwfCA+lwxMke0mjzEvEpHDSWBGzdvYRTLP1L42p9l4jLQapJyOUf9iLfccJdYBzkTn7wqQuL8XE
l2Cxdsx6vd2V6Fvye8dsBI4En7WKPcKQDxIh9cw2XAqxrZbiOhLXdlLD2emT1RwqrBHsq/GC+NQ2
TZUeGT/zCkTlpDKJ7PuQtr2/kzmNZxKiR5pTszHGZAvsHK43V3Mdv2V9PKAxqg8x0YBYfdDgAsbc
EZvJowZc6D/lM1XQuu8VM41cx+0Gjz1He9yT3PhI9XWRJoMlR9BH8YvExcTxbx3udS1ETj6kLWPO
AFcMthZafr8BAD+83j3U6Iego540tGOCFn2u/OyEXiZwc5HE2pyF94HtGSDQiSctA/wblhAYK4s0
53YmdKiCaDB3xEs7QgPlx24u4iUNqjIsvhQgQf2qsOAVSjjR4kpvFXyiJVhAZcw3yH8xZKJI3fng
gGYI5b1HNJCt1gErtUz7TXcLCACn58DpNPvDDwU2JMcEHrga0gcLeI9nzu+L0o3PjwkQjZmP403/
R+rB8IVLLUWCVvAa16VPJOH2rhfpwS5V9mO0Yv5Y2er5GcH23uyflDl6A4U8Fh2L71vGXktyQjSp
nmLzBL0citpx+iCmeZxXlE6J0/rDiogXyaY3n32+P0OengrY+u7oineUx4SqEhDg6rOnkUGT+0mc
SosYZs3gtMYjewh2PuXH+5IBiVrL7dZ3Neh9lF3T0hWQBovdONqE4uipGiE3JeC5q7BgnJQqcOtr
LI25CpwvRaRDncougFAXq0ren7mc5ZJNzB7NtIt6Ehlrf2K0tjFYfFVNUDlQgIIutD07wneF2QJ0
LKCcQfFbXLm74HW1HiyG4tCn19R26/L37UoFiKqlnuWrZgXM/IMDFJulf7qmiT7dMaU8489s1qQN
rWewfTtrMNvA76ob0ruzk/23XDMiddLKPoWSfnidALD+KGd1z5Wzc0ux9E5Zy23cZylMhowOEGWK
6zh3ONVT+ozYy6sIdeA6hg4/QGyPyFT6mP7ZxkX8vS2Mn7WKx4nQ0hZspVC6YitRsERnmuRtjkXD
g3BPWKPWyqqTTSlxshji4mN9GwNLJy0EZONchEN2gq8WoCzgDQA6PDSgjDwsUBVVuwCsSh8RBYfa
CLKywyCC5Q9ipXpQmf0rP9iNlZeHRwWBtmvUalewzQPARjrZ01aKlHELUNsV8JNa9nKL+2wYeuxE
zPNUt2NOoPWeOuvlq+0js35DHES0s3ltRt9OTHcF7Gruh/63nzZVn/bUGEKZ/NcObfXJAzCUB98F
eK+c/TViwz0bhMePPejI9sfMH457YpSDGTvKlLsvmYhINeD0Hnr1yL9Ouet2A8LFCRwL0AWAByPO
4M4tjPYHWFYmNnaXSoJo32Ejn0DpEMYXHE4+3MIyNytAyUh/ZnmGBTG1VDNVtDA93q5xGW0sDZc+
gvlKDNHr4dBVEp6xsYQiOhH4reUOsao+Y9FPxBwJQAA6KfO4f/stybMO56RbnEHOm+kxbOCj4Qzn
xvQNd/RNTmR/um5gnw1GIQ0VYUsGmELk6x93B28ieQp3g+hNUtDz2Vu/NDA4/jqU8Y4RgOJgcOdJ
mPfwDmkWFfsJ0z6gIHmhVmfJQeIAalovckxvV9jY8gbt16C0hqKJuv1UynIHVSqmH8rWOVKx0oPT
iBTzC66elVwYvhQxYbu5Dt4Zah4KWDcCfzNHeYAXEhOXH2ohUo/8KIMllS4AtVmRBeHtbPcY1ugt
DFc/CDlfB5F5IQJIFnkVhfggnktmqFT2tJRyLmJUs8lDxg0dnFXoNB+k/1FGyBBS6Ha5C/q2QOSv
WgepisVsb7Bvhb5oW62CSaYyYo9a/SFCcvsXaMWobDyI9YaZfMlEs4OVWBhMSQMkxgCM/LlV9Mxj
k82WDI/vz36XHunorORJ880rUvMxZp64XvrNtOEa02+7ct2FkNzbFSEDEyVDQ/EzXzC/KA8JFssl
8A1S77hWbZHw5LPNGBHBAQByK4OCMZuRghjAg37C4fGNV674ZMldBY5JMIcF92+jgbFLYPrcLeTp
482tDy/zU3X3Lp0i8P8BppIn/rfloLjeeH8XtMGfpNDhF5b78SclrWCgGuEuKcU41m0osWWnXVFG
dnQSlAysC8KIODKl87TL/eNW7twd39JFzKuqQcDkIeVy7HjV4pP2wV/0x59YCccAiD6DOp8ZGsUf
Go4wTefcte0qm0v08rVYObJ+dLBfDtwZlPhUTvwrm7l1WoOX1OG+q0VuNLo6PF3KYx5X8prgBlNp
HZUhy5/vj5vKxufEdiUAPXldUWtNAwpdgwoMM0dMeAc0ZVgKLwscNYxHYgpPAahXhuTIme59NfY2
s4ktLA7E2UY+rypEXA+qNFmEiRe2lh4jDSt/H5N+VLp1NQD/+1SziqmTX2DKXO84XJTRa1UUMQTE
BGyd1f/FjFePoR3y/rD+IBsuzsQfq7cgWHpStOjs7X/xLOh0HfHGaTiTElY08EhzuQzhDiBx7fOw
QfT4JJmyRMMq1sWHQB5fYOAV9Tkhbo9ECtGYAHBSy86iLKOIIyD2rji5gxGht1etwkPmxyenTYCz
Xmq6HSc35+KUg9vJTY4tzDz0KchPrAlBzII1zLxAatDkdpGRJPmziYZCtXelcchuTH/1YuTThoJ7
f0ZdD1ox1jMXJFFYZFIQFYyHZz8hsLvcdeI7D0QANYRmRT89K3N3KOAP8Jd7Y96RTXjiO+PApl38
RxIn8V5M4+wfc+a4MkbwBEsuqXqTtH2jVvQTOYBTa6oYf4cshW0/mMkppFXndHW2X74Q2Dc2OljZ
gyLQ31M1p5dSkbTvmi+Rr1SQ42oaSRFQ8qDzzlQ97+gQP1/q141X17jvR4VdkZwo9g23xKgQlvM0
3AGJB9r5kXGzXqOHqco0//NS6T4ZtlSBQ8vUzhTcd8AM3dBkn23eQS+7hSlW14p/h5uYAlpGA13j
q7O+04S6Myp+mbmJoG2SDjQ/zUHjFfahgKHCaQdU6LYzZ8/7UD7eRnJCMVCy4vL1BaJHW5ONTlv4
uBXjW/mYtcEC1kcu1QRXiMaSIOMW7H0C94hBcbexUwLLjz2ZNFIlKHD8iMK/ad5EJ/TXb6kbrId1
pOEY/2JCcWJsLBMxZhv6VcFui7YJ0F9zKGNb23L2JFI2Z0fTkgqs/UOGTQlZzx07Cc4pw4ZHg+4x
krw0EYgD+P6qE8VGoGkh9HTGW6oplcRrwtrtSpctPU9cy8TAOe8Zf9XLkfgyELOWNBviANFkFKj1
zVSb8HHUOSdMlVHdSyBR33SEvb90CSFVTQWgfVIwdH+NtAx2rp0ri8w9Nq07lCDkZz5+CMCJlYfZ
6jTQbeu/uWGKZvH/BaNLF0viSZSGWIAHgMaUA/LVK+//cJlmU674vMGAmBCC0qO6AEIP9Ouaq8+j
u3rwUxlBF7HSXAtxoO6fwWXm4vm7d9X7V4vyv5TejMU4X+kDxlo4jMQrjvUEgRfeEH41DPQfKuoU
XHEbEzJSqb3MwPly1m8QT6xHOsfd6MYiTJU6qxyQlbz2rk4RH/Zp5s+pFq8e3k27KiaddXtbs0Jh
ny5ymV7LV6znxPlh/8XrgYa7samye6vRgFHK3rlXRq9FirxvKyz53BaA3WQmy4VR2ijnw46DawgJ
Wc4zPg6BFdX/L0OeCudvWsItz6WngnhFvYx6aCFxxL78trzIeMhbxJsB19UujB1bXKgaxcx5EZh3
wW8DuEhloPSLiN1ovvYeX+mC/Z+ZlZXrWDLFcV7Q9aB8X0TFcJAPJvdHNxO1v4cnqWpjqKL0AFzD
zhjDdFXNdOX61qLUJX8qCfHfKZraDlgqNXHQCMFNElA8+RzrA2dwJUR2gffd5xvrhha2/AwssbK+
FWyxeA9K4kdyJoP/AXJbczOIKMRq/IgHpt0PIIdQYXwLisJ+ZvN7FNdAh3G1xQ2nl/8snhm6gw1O
k4cgsj30cj/D6Lbg+OzM7ocJGDnT1Qo0sYErs+c/KW5GPXRLycskB6xnAoIFq1JLLvXN1AVhsUhl
DJEvt0eWCwvVtRQ5OFcarNIO+OBaO23SqyKWKeBhqcWmTAaPMpzE2PBldrl6VzXl8G8UUtdEKaNg
C5DzRGgSQbnZR+zmG+/iVVtOsW9or6rWetSzyanp2gEG39MgGmtOKuhPsMKVEC2b6iiva+6BAm1z
ijb6MVLhsTEHU+U5A+kkXlh7tgF4qsWR8S5jIuTRxsm47QFdFBccR/isNkJiilRGmZw4N/iX3Urs
hzgvS6twm0cF+WGsoebwfb6j0gQIYZxluHZZQKtPb8ulROsGFLVLSrl8VnYZSHSaRnFag3gzVg7m
Mm1N2i49m8+rJ+wU53r+GS7bFVlbthgMe4QWhjuOl2b3rMSxUB3211K9cyLC4lKr1V7njLqSnGLS
95RI0YnxVJnKfb8c/l23xDtvvnIuQ/NrwtzPrYGq7F5zedIiUbF/9rAmeR5uCSccKtYGzHukW9F6
RUSICthZ6p3SeQzfMsxcu5s2BQfZlPpX+2b98lsgZG305dv9MTEyZgv3tdpxpsR5C6fj5P3eO2Gg
eprpbQe3GFMRKfxhoJBFj525EUCXPqIUV029/p2xC8ZAodQA3pol5Qx7VQNpsbOLCWZ4VPECGuZb
LnnKS4TKaxkazcxhlHwpsUNrXFhbnQ+iMxR2hp3b+poeFUUciCjeJer2WyXYFPf6EAIMa7KXAwyN
3y3kNgu1jnxHE2wNUVX9D/CTlZjJKDLoL9jcH7T4eSSoVZYzWd10ki5gXbzYVLutAbjj6YijzVhS
flQI/083/izwu/mDHVKALIggPl99cyxdg/EmWP7y+PFdo+d5EIgIwQFPFfcUILb4CeeOELjyENaM
SUHAdYCt81FCad874yBdH0GG+OJbx/ClcEhfD4+ZKvnGfoHeSvKO0PUqEU5DheipXz23RQIZZz9C
BRIH+i0LPAFuu4h5IZaCBzWxL5S6Jz2k3ndzXmIu4USenPGbKmQ14QafdQqMZYPdScOfO09+YODY
DOAYpJN8p88r9P2ZW4zOhrHw0WS8mmfYpJQvJZVqy/FPzpDpYP6EifgvG4raLEvwCSql94+pFi4A
11ZWAOL2dfInu8ROS59jutFXNDoguYZNiY9gP4iQSt0R8b+Unok0+eyWp8x4DUGSAXROwku8embZ
7clF6sOUZ51SAA0yDB2Bj7BO7ZMBU4GEIs5dFgfsgfYUO+RmSvKxHx3LurT0v2CSQ0GQ6Y/26iYT
KlAkafSyTDAC4G0xX0ekxrAZmx2wDVrFRuu1TRy4S5JHz7QuReP6r74UHpXh5W9ZVDW75Sd0b9tp
/7CgsdoaNnYogv4xmbPUKBSgQj0xT6eF2DfOTejm7J2qR085aXPr8uafAvF6hiIBLSbwZpEwzSS7
UHBQG1cl1Zz659U+fMS/kbq2pFUL+iZulafjfxVNjVu1q8Cw1h1dqzpoIkdNJ+qlaDW9Q4GB17XR
kz9eXJ6fogV84GOhBWhw7nCbhI9pAdcVukq3X+e77LhbxHRjdC3vs4wVbe1Pl2M+35sccXENUaHX
w3MtQ+8z6/TlY0RWObw45BgpiSH5xWuY9VirGjP1aoSUNajuGiPd3zuaHkwb7ud8LNyITz49t1M4
M0QO2JoajemH/WaieCFjmnv5yKBTdGie+jkCKqg3wsQSGd1H7tL9yeq/mET428mGha3xZbK6SS2y
/W07hT/0iaDavW4bo6LZ6AuOhjy2V6yJM3u52evZCDKlTZ8SnadgX1MnQGkQy2lz0QYJbJUfPbO2
1ktzsPlDAQSLP09eW+o+Xb/lzZg0OMIsoPjwjjUvcvsYbRwVVPlVFjmB5u4rbbpVryJdIvwHg04M
WgdYSEDryIEjYx18dDNFV8/grdhB2KfH6p4NS78wKdlE3VMe6/TashF0XsBmYhRcfcy/gDnRaMO+
kbO5lbr8LlVXp4sOn3YJRhKGw+eL+RI+D+WIUGQ/oMJ2wswCIqO6EGRlMo8JOlT3bLWOsGZ9oZDx
hJWNvEkM74f3rtVIc9v8mEXcdIOX6zulLtl5GyenA0hWuobOVLkxyK/R4Jzegl0ePh5wzKPBXmS6
h94Pqddn/xFEOlOK9ztpoa7EE0vomtrtqKmvDqGZ7+gLYVduztjNL+PYoB36Cyr6IK2u1dVwK/52
JDBtROIThDZPj/tJ6WF5t6q2+I8QiufP94Ji8CmXoM4aIgkDhq033FAILKemv8E3lWb29nQwg6U5
CI7737rOlmxlo43tf9aDouzrbRO+KtNDr2S6L9a3W1g6TRZ41ezQLoi1GGZ7r3lTcWw5XpIcc7nX
kxfNthyGCvTjUKM1vrBpOhh0FAWn3P3gTZmgVILx9xvg1HlzZ3PwKCYZdBhxvVKwNTpOsLtjML0f
aCVXxxL1Uufd0XahCPI8BFlKE5zNc3YF8OIC6QzeGenbLCuxVBIno0tCYKvUisFWmOFNXJ+ydEOc
o6MfZXLX0YyP1pMDT9YBmoa0RMFg0MNWiGqzv7mTgYqXADbEFz1tnQF0u9Y4NCPboC2nasuXJGA7
87xdwv9IauY8ZULgxchNOPp8NCZ9GDFJwwEzpHfwIE3v+VKW1Rn++7bPkU1oKn8Z8x+pg3za2q/0
YF5b/24/hspJk3S8Ll5qTczSrZd/4285K1SOwRICbz5G7jIzXy1bxcq6Xr3TrNpk9YXhklQa/EPd
nCpSTSPPH7sHy+WmiO9cSJpviAiK9o3pbPJ6rqBGgHsXRoJQvFP+3ib2cx1aRdHVEPclapXwxue0
b1O0hgs1BcD3lRbWVlIugtWwgUnB819JkoD1YpzHLdJgQ2UNsPe28mZeBEZbGUDS7VIYUefbog+y
M9Gi+lNOY9tTvRCb6eghS17kT/UTg06tckdd+BlKwHmTFdcNcWotTiNABf1pFahZBbe4sfzWKpFe
l0gqxmcVnWTOqBXq0vsywnphG/20fCKrVs5pAQWMxFJzY2+QEqioWnhRT7vR3CXRode9YO1iAte6
gG3hDEGUywCHyNJ9/6TtSp2LUealLvqo/R3m8NjVXofixzwvMJcX7o8+P0q6IzqGWh282n0JEGYI
4h0ZwASUL7ij/6zNxWlLIPFbtcqDuNeLLkUCe6ddKcgmjG7JBFmGh05E26le4ZkTm+QJsiRDmnzN
xCLstMYFXN/GNzec8go5cWrnXX/zYL7oBNkt5y6x6zqwPw1kiDlIQInajTyZHWFehLZaTrY8uJUJ
6vXl2CVRfW3c1GKsMq//i6Ie1D/gblyE+YmF1Q+YlSNVPEsgYVKah+tcpk6waZogzRSdbNtTZIYF
pxbKkw0KjWSCSgbnmrGrgBod3K0PrN3cMgQzplcygC97wwQHD+TkIQWNEFadO+ridDuI/NnTS+k5
FXc0/9S3aCsYU78J6xSFYoaDhXe4RenYu4gChs3gCZM+2gAXZ24ttGAyVnkabi765pO+Z/ix5dS+
jd90wgg6K5BtndBelrmU/2aWLJ5Udi2oZlQiJ2lrqy/gCvyFGcwjHp0zIbhHCky9Szc/h8LTS+Yf
+rNh5TAEj3JBLOYlPD+95JUKR0l1oBvvLoc3XK3QvDLXjpYr6EteHlhmv/txjYpx6ER9U5FHCWFT
bGSov4fvZsEEH6N0HDN6PrXRkfv9Y86CLXyyZN4hYIMN6qcZ4hI4N3SmPHMEfN7k26csa7TuZMsj
Qf3vB+jelmQBPzN3ts6dQRn+CPqg6jbQA6lR3xgPhV0eQbwJ5wUvwKJAsYOZImowl2lwyVgrZ9Rr
ekOMI9iPxATz+nNCV5taFhdVxHnrfWZFIdGkTXjEh4jMLrfEvZPEgQE3eL/ypSm0a3EX8n3I0jWx
7tamnH0x60ij40xVQzHMHxQXrpjYtVwEM8mjWwEG4Q3EwLBw9R+nChIl7AB4qFoFt3WiJjtsG2yW
j0MyOJa8JUWteMN3Rx/2W8CZIw2TL6hzZ474nYoYlvjBAsp3Mwi5MMJR8/jPl7a+xzvOtXMI4h7M
8JltU6qZ3DYLfJfD7WUSVeMQ7Ae3bRxhnq6lSUhzUGr1sTDpikDEpraxUwekgdGoeg1wau/L0Lh/
iEVbP72uDuLawQR/rDXNmTUDQTXC57llyVvPqZzam3k8dKpLiO5b296rw5+M3/4RzGAmkyeBEi8s
yVOVwxbdXMwqZmjGmNVNj5Tm/RLoPEIqnp9p+M3wTwDqetBCucS2No38YhkV5wXRlwHl6s8l489U
2YnYaPhiIzfQ0kfTVjwPlJjE8e0BVlGfQyKTyccnt/I0dY+VTVbKrPE5OSiOssajWNoJ25xoB+Hv
5EQv7Z5rVhmIMpx9gsZYpk8fzs+VYKIwbSOOxaLmUiS2D4pacYpCPDRC+5XsRbCZb0d+I+PFLiXm
mv9XOzD1tHNbZpjMnRGyGCStqjXuALtGHX7NUdQ17zovs+ppm6tE2kkYfMAkkRJ8M2HeP45UCMxo
MZS3mCsbl6TjZBoNSqBBIMHCE5INNhctAcDzl+AaRkXpmYxgLm5Dm0ih9flZCe0RvVVnW0Iyb+dP
QUUrTUuXtK5ZXDmlZeXoen1/Egp8S8xTl+OFsdwq6RVPBP8poEkqj8DYvgCVpcnUQXYd3SimxGs3
0IYSLEHWxGGwtFT2bY5QyDOTETVJVtWODwkTyPxQsp2mFsAoPexXGgtaMj7CdBodAlvYmjQUhcaW
RT2cXQmgMwFp62xzRG7ir2IDYA0CJYnN87IegOKa9BVPjin1Y5Rxbnrs3a0UONix4fSTn49OTnil
7ZwWmcJmMo6MBC1XpviF9q5Q+3zBdWF01ALxh7OQeI0hxMtNci7OeXj6/RvZQa/3z0Y4SijmUpfb
N18dDI4iyK+4ercMRndSeqGFlx69R0+qXwBsbE3saYY5KNTIDNg2PZORCv3KbgrGSigDxxZsf3J1
FPGwb1jOMSQtAhnBwjGuWrjhb9QJttWZ3boIkWFGMOrnWde0DzCMH5CSLecUCDfOwZYb5e3GvlXV
bfBXx6AT+zPalB5Mo6F6Fx/7RgMB+Eycs1kdwotah5lChq3ErqUi5Sl3kNWE0BC1t/ofHisntgPD
Zfv9rrg5XY/ChS5SmNKf7iJzdV2eCGsE0zvcmf3Rt19DYnJzyFUeUIvT5OICyhjLjFpzu0O0YVNO
GxqLcQ4dKDQ0774qV2UAmn7BHUkG9FNdc9QfiPRRiRkZHhmEfpp+THrEEQXOjPlVVfER9aF8Tg0q
vWcC/jV0rpqLu+kB98F19SASUm2k41UJRRbdu7TvygjTthZajuhIys1REHHhLB84XwnNX2zLEt3Q
TiO+AKs80zmHJC4PczFvstaBgq42vuv/zkRPuD84VNcRL94zzdVCXSI2EAdMTsAF4b/F5s7i6H8Z
fAlCZGo3nJJ7yZ89b4UO0D8E7X4n2dFmLRtXqji3Ex9KFPSu8LCJCvzgx6xSlgMLmEovlM/C2OEz
CTLAjOUou6JCPF++VF1kKJsDumMQ2yr7KRztVgAzimyubfQT/UufNy3Ayw9uQIW/5Xg0idA75D0V
En7B5HSNaVBezOs14xtIdCavSUoZxEoT0mt8v7BfRIz2UDCj9P/sUnfAFQe7UJvIjMnAyaJ2yiJI
trnq2wktx4kzaZHaeJrQX9nMCKyCINjedlW7aUNEw7s+xzbq4MyOwBo7tnQ6XUeL1yGMUk7uSQ5d
pYgQq/pXP34E7AueoDd1KmvcH0tGYBeSMro/WZX4xOaLJGpyqoEXrT1NmZUfbslkYpWU+3aWVakn
KyEAAWtToBttGVLibmWOVSDwH0N1jB2fKuZ6TdFLvfq8fe2WSBUdTyzKlHad4Bk/xeX4ywSdC7X7
pGgmkKVjKqqsvSoXv/C6pUPeQeYQhpJhjj5XhCXywNe8V/Lfz1eOetoRno6YK5yid/fAq8cy1Ka1
OXUoT/8oDt3LK5n6rVBB9l6hpCPKKfNc9u1jXIB5Sgg9soyT82f7IcJ5lOxmjsP9phMkTVXBIoUT
KgwnL+H6MCD/lPdPBpHKU1wv8dHzKEkLiMJYZCiPWKGx1eLtc0rrQZmpu2dZS1ANiYONENpD0tFD
NXkA0KF+hZkHIWVi2rrwO9MPjGeir0D+LRrpplP/pCF9Gk5Fa/qZR+KXa19cjz8Icw/ksv1UJETe
i2oyfk6n7wIzPhKW+URhdmFh1uS9dQZs7bTJ3UtCO0zIUcgwKkmEAw+neAu4bR4L2N5t3Iu3PxRH
8IfJF6ISyW+qjvXU5mxxZUZkd43Ib+UXcQJTpFTJ+YlPCwRw5HU7bOJofc5FiGvJsrZt+dUTJnnR
5rX4P9yQBO/0me1IC9FtOBRuQs4sMDAnSEQ9UcUErP/Iq7YykqMb0uC+Kj1KEnj39/oOSfYHTsf0
6Mq4FzemajCmeSZvXthLnVy1NiDBCpM2xRBixSg33ds0CZeFxe207+9nCB+0QOo0tBc0hf7PR59P
WGbzihR9FnnzKU5psrqa8HDYf5G4dEMZHNwYQwfLyYSaO2BTnudVNGJsCrxLnbURV/likQtFwhaj
U+p51h6sZpNq/wybWyxG3ZtyvsGdqdXcB8+jC3iKbPPC9qQPKjfOKL8+xMdeym2dlhF+hXfra0W6
0GOUmbI+xURWUHP4aj6Rn1XH1b7Rg6iLSJsrxIO2u3p+uvZa/+hvm0xFVQHZfan3DHkDlufZdOC9
v4tD32T+frV9YFAFI3EzylHjqNfyLE/xURRVBrDPL3pfZU0SrCLuCRERJwM0/ZKjIdyi+oxzcJZ6
7Vh3J6yMra/vklguZQRk9bCaABrHqwW2duEvQom190fHn4+73kESPZ95rGvxPWyLngnEgkzlJAIy
od5N4MNBKqEjFRg2PrLxuI5vw338gRI6DipGpw1vZ08/rbN5InnemcFcUMPVrF9SrB510ofiqvFP
qi9qc15sqHd/uX4rxoj/y802uc4uI5H1JWqvQ2GxSTt/mc++hC4aJL7DvWMiigyfziPKGGBV4+VV
v4YU8QrpObsm023tgrtpbZI4ZYNZgAFkF7D7Fr5tisLp8C0t1ohKYVeOnJmaeXI7w0XV+rodWOkS
7o96SSZbjEimiU2jEc5K3TB6uNStRZ4ey/49SZaP5Q2rL2N+7NfrSbSJUoeVjgCeaM8tpeNZTSfE
ZekeG4qH/utVte3QZWQe3qKpM/DqJi5aL6/1zTdgiVgEoN7b9Z8Qkq3sYNCag6Qg48i0Zzh/Zgco
V2GKi5o8eND1s6H/HhkFhONsLlMiHpMRI1fNMO73lyVkD3KLplhdAxS9JWMpRbSMbWuYeb9defGn
hEu+oQp9yQO3og7FDE+MsvCv/sK+CBXP6Nem816WWc9H5fT+HSXsGBYEQYamsmXBv2c/8A4kFFFp
cwCENmoWdeL6YlO9IcRU6XCpEasiEjSLPhjz0gHdDt5W9nGHWoB0Gceo8aG9wFKIlWBuTUPpq11X
E9nGkzGBlfN8de9lf21sYyAHOsEw++LoUYpuUzdHwkcKBWI2sxRMs1DWizlbS7cY1uYUZWSrdw6f
QVA+OAnym+LL0F+q6p/Wy29lhgGGB5625rUyengieb+hxQVXhB/MGIyId6WNYrUshPNnI2EHpppX
29kLUGTHdsmbbYRuLeL0MvaAx3vXyzeNChRDcQkeNghTPfdGV8czGbtwH6PtCRaTP/lAlraVez4s
pwup8kifVmfl2QCajEoigH8VLlwL1a+SyvsItcven2M+Z1M5DsobgmwCZ5vc5ocUQNO6vw37bDrW
vyz67biR5Kc1pBKU+WubLMSxW7djEW46TMxa2FDOyGB7Yy5RY4bSnQ4n74F6TDdIPjJBgh3+ZcZz
9PZ7DERVKLSQhItbYjhHm2EVRvR9s7qAqeNcq4K/9qUcZ0a/PZYv17mTJLnE3RU5Uv1F1x2HMqZL
oZNZSsKN3sWbAmM2LuI9XBE8IzdbCBnz6JZGFW28zLHU28SZNcwFP+WJe2TWv5uFasnjuNTm39qj
bDTBxRGezMZGqL3QT+YnE40/DxahKpUb95lUIsF6AKsS/ptHc2bSw/Jv/AzxoNAnKYbsmFJVvaZP
W3k5or9u9pZg6V01z5Puztpl8vp1KkIRr6vDYKqXzudLcM29XLHXQXcC2TLDsyYm/A082fCXdUi0
9yJzSmMXaGG5tCk6iTEXj6vz/xi/2lK3Ay1WTwSHBFQ2Mwt0TNpxdSa/9+pS3YsPkpPBWXthu/8J
nXp5ucTb8I+H2Q+rabTCRTW/AcZss5swjQ35EvBXU3R6Xk1ZHWxTptgnKpgeW2ruiuQ4UD/QqPGd
7KGLWl3XZr6FnAROw0XOe6C2BlsM8aGp+Xjt4TomTdAzg6EaVQfh0V/BWpPE6vA9dNYvi6fQ+4YT
9rmL6CggE6RiagYrgzGRP7ay2VeMBXoGH7r/Yzsg/vA27n8YH13VXg7EBHFFppREoelNpXFD4zjN
PI0M2ov0py4wHtoRT3oXQ7EprzJ7i3sC71INRxhhSfENDIqeHaR6xxxEiWQo9kZ0BuJQiNT64y5i
fx6Syq2RS5+6wDVVqgSfeEJkUYSxA/Vz+WBJFRHqTfxfpuqvD2N0UHiRovPN0iDII9wouvgxkQu1
7j8hqdNjmIALmRU+NNAyoDRW9G0irvoJyEuk5tcZzlz5Z6imeMbeVs0BjoDdaWU8eaha49HCYq9b
YCexYtMcf7DbZC+sO7+tDeMJgPDxN5p8wpyN3LAYmXKA/8G1Q3p0GPTNyKXMGGl4SGIfWdJudNv0
v70D+JM8URiuu0cXcihjkggGHfzmlxS047AXUktcgufIG9UXFjfiQLlaPATIRsHO/bIIrZoTXsnd
OVZf3pcUZ4hgjCX3QMSmpJQQXkmqupMgvMUEw4BGgXE5vTU9flyna6MYp8+YGVm2c+t/cKqS7dQl
avjDgv1eQZBfxdASOy4lQPfsonTnWkI4Jufp6Yxnu1WXk/eveMNkt3QZM5FRR/dogtFLq6lXSqDe
m0DeNRVOgR5dO6aYXC5mt7jvzcJOyw4GnLXN+BfqkubJYiUNACIXQx5yZHxmHrL4otf3B9lE1KQf
Tv5xugyKrzFIIH10uOZToWCPSJ/7ZNDQYUzw9vYxXU7h+/qLEgoylXhoqNe7iCWUuC+WCKD7qdM8
rKztcJN5ZCFhFaJzDwZaAyugjxkotaQKUbDrpk9XsezcBqXo3mhs6F9oS3vxNN5QN4Cc5/TPBJno
zLZrPs9pW7MLxsTbCI6XhXf1piqizdbXQclRm4ZnC/5gHeG4jxLH2o1+CjaEdjDFz3MY728CxBDx
BlJHjeLF23mZPqyi7Ecc3rOFnEwdzzbFni8XXBDswyEPeyAvtfBrqZccReAXN7kNe1ljqU/H1kpy
DF7/qZYXUEIZpEoqo6DFkjEz8psthwPH67D0jQu5HlRc6myaeZ0epG97CzUuzRKy8aqjW544h9Zu
0yw4B0cLXC3+DB5c5jPR19Ix1NeSIoymbRmq5a+61lM85oZ7+l18yt9E4ZarQTlM8lrcBPyF3v3m
uHQwp+gPEHwSBUlutkRaX1P66blJxF0EHo78DPqMLjL9TrR89gSSPOCwp7+QQBHtgOzGYUDGxPQp
zk7VKQUMOSyarIYZJAru253mR+GDUHwvfKIs6UQ1m1ohV0CeC06bbhGBKRll7l5X2r4+7s6Prb/x
PYzmRgvVdMx3qU4O1OpF7xU1o26FEjLbRufYYRoTCqxo6Ohb8Uw1mfRpmueFV9W6RDnIi4pqUl8K
BFNPNPerj0nSPrEEHO0qXqE3/XF4Bcoav4/hl9QWsUV+sb+HlRin7FjXcKD0zH7vQA7gPwuzlvMT
iObmKWY3ZSyBkbRX32pbd7Uq+H+5OYMCIRMlzFCmcYmSSpA8gzyPuLCV5kPa0/Z0olnGFyZQusO4
7VHqT6W/Edc/C2HjRYW8mYBC3FPRpiCIcTa7o/oZYVdGDBKEdVb0Vj6P1RJwRykQ4ZMhYzD9aPHk
xQcRaf606NiWPEe71+r8WJ2WWQidPezR8P+jzqrMMEmm5cxgsT/R7lD8SrDyG1qbW4pTVhzjBrri
Jyy4JaGLkv2Eo5KbvvE1vq0SJkObEY4nMsfZH64cUgGRBkghceooq92Qw/Ny9I2PVuFDUU+zuMgT
y3w9QLRcLWHg9JME9F8yYA/qqnt57rbsYiS9s6xRwMQKYNX6h4P2g81ncchfe0mOyFh78glvRcvO
DMcm7KRE1yq0Vxspam+QhQ7WuWg0H7ZU/LTmeyt5TJvDRz6cUROy3Ifbw5IPJOZrLMkUNEZ1zioj
Ahr9kbS/R91lfGkflhSq7xOTEmcxpCrAd7dWYwjxYFCumkcRMVCr5iTBnYSq8AbVaUAq2JnMDPKW
H2QvYpeyuaUKWKQUtMzmM906KWBiKil2/RjdfrxXWCrdPmq+uKx3lUIeZzOeqo7ZvNGv5crOi1AF
QwPvXJUTOMtjGnOD7aOKHnCi/0375mHKHSxW7+TlLZDrWmduwXlj0++eUjN8LFjkV0TRjY6i/Uqz
/HPNBWT/5g4NjaFC9rAQWtOC2ZuFAhuYjfXQiU8qwjiYL8WSDTfNTGTSGF+lKoo+CXkZgz91YlBh
bd7xdJMLvZ2MZZHRXvMz4spMXUTujk7jOQLeT9EocFIDOyi9ms2wDJ/cboltWOh63q4uAh3LTLNj
OLii97JLTUaXHENXOaZCoBO6PgdLxJjKSpAyJSaI5UQn5J2V0iULdAKIVIhcd4nzjhzYqpcyxmWZ
t/mcVuzF7nsTbVo7E3mi3Jm0v0ldvnWHCvyZwC+dURAFeDKmt3l5sEgwuEAgdqr3ND5Xc/1SWwKa
v/woJzZciNJydD7xz2AFuysUGgkSmSbdnElI2/mBZXMtIH6PUIJIYjQBjegM3SFZTliuQ0iL/DMc
vgDA0N94WmPj5iUYLcqtAYFWCoxYcAid8rwk7w5NYmv0AAh0Z2xvQQWrzp4od7W1twj0WFAFS7uo
FNlsjvKF2vJIt0akt/WvYyDnm9oFCxB2tUzvRJ8g90dWeWC6VI52Ogo6NuA/A9e+IDZjcLSu5sUe
NZG52aoXDTSqnkrK1ytdXb/w200Fqc3WodpYDst3KjBEw+Qdy/4Bs2L4IGsJ2bwUjnaCWNTQZyXX
UfJrLR6fI5JHvhiuhIWNz7U6/lh6SAARwSR/voxMfpsLrXh7cfnVi54nEi+Si2IgnIHGztWcvPfx
xfrrdHZLK+qWPkeMlIInP1fs1yta8VgOTKxg2YN5eH55Rf60PBEYRfAncdYnDHxx5yIAvlHoyzZo
lvYof905cboO9jKWUU+K5df28En615nzATsH2P52lsfCSelHblLBIvrSZI0R8BTup8HhZthceRbL
AYPWLArcbzruxpmrvPNwZCwYetmyf65RZiCEKbwMPEbvpGyKwbI6fjUP3mOJWExGBCAvcOd3m+Wm
QWusy6AL5ZXGtX1/Wp+rD8nDnFxMDwptd3O01cef8YESfGIwjC9FINptr3Lm1U05CfZn4/udSO3m
o4VLm0VbgaiggSqjHb7BN302axy/uJib19iqNYmmgDuus++FlqWHdDFZMGVfav5BHebckIElWEp+
8ZB4nfMRKlBbp7xXy7T6BtPd9j5XPACuXoOA3vXcnFxTWod1eq3AXAR8cxmqDg/2Me8lWtVm20ms
fXdCSdM7DAbPp3tx28LVEJA7Fw6wMqiGMAm0LDeI8hckosuB63rqbcNlCk0sKYUjf5zh2trzVi76
6qzDbC9YbXfb6vydU0gdBQ2AalCDlodBtI6z0c41wAecE3A/h23y/+jfDI6huMPBtVy/dj8e58b7
/Bt5dQoFgQNF7gnFS2uhuLJ/U9qjkbkQ2F8OqnNf4CgqvxucaLLPtm+8BA3c9FAe1/BoaNnw2jBO
UAieRKyAX2JDo/+X+8tVvEbb9Hnsz7bmSnQi1M+yjGvUtbIH+S2vBReyBc7A5SAfucM34UvI/2oF
SxrJ9KPeu0mo/QWu/DOoLo+fAf8+K7mlFY2St4kZPwM3shqy+znpN3USLkbdOpD2A69N6w1qcB01
zZ0wgHA8wXLXDzABWcBDY3tplV47wUHiyvaRmBxsr0nA0IRf2BYOkSbGJ9e4vBP5oI3Q7B2EeMzR
1SmMJBlnv8mR1ImXLxsjk+iSnTNh0BMd+IPYBNUjmgCU+FVK3cOmbYHh9JBhsBq6HZNUWosUjzxt
HGJF7axx1la1E91UVpaJZWkHTJFyqhbwkU5/NFCdMJ7V9goznULUb/rBOPCv34R+i0+u4+XGru7A
G+7VQiP5KHYiggDRxdif2UXfWkpTC0jNwp9NZBp8RntmAM4gqg2fXPCWQyZ0WeYsY2ieWJaYtxta
4s0aBMYEbfajofZ/FTErnp0BHZiugCEy4O+MneldY1E2oAwVcDEhAULO321t8H50SViMStAYghid
aLYhiwjkg448SxxTTQKdyUMgzwnI0G/5k3f88NY0ESA4COLTTHxKHuGWrWqCCM5zn3OBEoCroU9o
A65bIMkn/GtaCXhF8nv/d766uPw/WS1TNGOO8BrgpIiWPYiL8LqI97qKJ+PQQZPUzAFXYja30VI6
uSkZdHt1JWyznHFvmHPjzxILGlZMphibnDpsG/9Gxl9mfHbLBgbwkVE83U6aztzKd8sN80U3qa61
JeYH7Mm2TxcZN8yAXyjF+yJtRXxV1uWPr41MV2+hANzu6W1LcPEtnxbtCuXtyEQ3Fl0VSmq9jAKl
coub1g/1SeEb384AT0HYWb5fYa+1gcoWD1jGLQGKh2DH3KaNijZGKsj8r44p63O6PwAgurtt2zB3
mhTfvRHqnXkYCOHZ7pe91bbncgvki5UEDg1xi/ffwYYF7Qp/ICkU53zs/VxhsB6d8hzRfBQS/Zmv
D0tcn9jSpxLICyGCGyW8QuPO0T5URQV6TIpKqUtyBvlybvOLJ3lcQN9LJLaGKp+41jdIU0NsabnJ
UoOvpB/qqOZ9Vcmj4yzJ0s0EQSFtGsKYpPnwz3ZIV3fIwIfyvCY6Pvs+74VPTri2/EMdsCaVik3u
HbQ5N4EE6xxIkXECoOgteX1qyeOiSlIBHuLQy/SHN7LRhEaUV+U+6usTiUG9RIVcQiMbuPFwxN4T
B2aKBnmTVZo/xXsgJ+vmX/6Dxy0SaGZIi2Urkj+P6B4tNsOxfkCPfGjjTwn48/kUm78UABMxWT3K
gvuDTqHuZtsmz+4wN/MuFIp4Y/nTV8ss1b/zWrnSge8UYXGlZt0yHVjTbaZYyJSQZ7vsBBXbNImC
lnAfrNqWgB3pCwEpShzYCuVjGOj59ro6R4/bEnBcypbPR9zNHGOAu/e2LIQL1/gAgHX+ftDek/EO
p73byY405gsXFaIYsdGQkMgO8Mqa0jK/pQDcM0az0NT9ZP4bi6I3sNM7+vCnGGInMiuBooDu+8JJ
CHhVCQRYdR/B5SF7W8IBsNNGITxFUgxzGL/WAugL0vBUepvXcCezBzCv8fcLwf3EKjI8r6RHrPvk
AOfnMyJ97CmIZL4x69fO5ICzzB7egnJv7+FHFrl9p4StuLXYMbBEaky+8oseLe6le/k2Ho4ohuTi
O42DUwGUS5fOmxWUvu0totPVZjC4lLxHHo+eZsRZRnRMqEtrVnW1bz1MAWwCe/B90+puT8dYLJNc
COIdvypPMHzan1VqBxchtR7exj+CTkLg7tZZAHU9hdnaEgjRQMzAC9VCAl+QhzGAnyj17t83iz5R
JY1udenja2Z9WshBJ6GYUR74dU04EaxjqDg0m/oz33nIaLFjAH411ynVRML7vPV8tq2CX2dHH6An
7olbI+mIXMT09UJ6vcOJqXG7Ln8sVxBYD67nOL6PPrNjBUDoFlvl4ehAmSUquwfrDrjztC4/xVWv
y0hvtuAlFVOZA4SgJHzA1K7jolhFZBc5eANZFmY30DT1OQ72TUrAnUqvLZSM9LKPwOFefjBbcT9Q
LwpfI3L6hE5B/rDskfK43jjGQLGY/gQayFTfbZGg2uKhJ7lxpeEWB5505GKfSispBGj+CHpG8B30
rRxb13lxai9d5OCCD6uc+VTh5JRk5hFVZlfYkNTXz0CXovhbZrxzWAncRM7yxpbR/o7+d3cP6iL5
MB8rhC0C56V4K4dGl3/NdQaLp5isj+tj6KRqAw9FWNYFreTw7KCBmXyNkRsHmODzxOXxpq6YJE71
XLDfRy9wUbw+g1VpP3mcBSeV8A0mx5TUzXIXx1yG6X9N6Ir+jzzwWxA3PFasI6+lQd6Mvs1YNbb/
T/mdrCW9yLGxDpcpsQENQsYO4p5vCDAv+JDQjQztfgQTpSWicVCVYBm+GOROfFNYy9f65jNfin0W
+SPXjeC9pktegecdWDIGIL7OuCEOPpAdStz0fL+vdgFOjdfVr+y/65+QO6mxdpnxsTrNiUlW22Ti
6VhPpeKXEt18hR8BpwYwMnd7PxtOeIxPqdFxXgk6uH0xbmcqnfQ07VgdiwGdcn2Q+YJD9gBjZo1l
RJhiX+9sx/okF1CLGxnLC3DWlPwYLZYLOgfeOc5Eqv+Y1+l2yNv5033xI0FUKL75NraUVce4gYG4
9+lpDVqzhDOifH4oZt4O1t6U/TR+yIqoNMbZBb4vv5/bfxeK8CzdxgKYnSDEgGFH5dXZ2qJNVWnP
t6atx7BdHFoQstCn3IM1Qzx5xZ52tqch01gkVN5SvP7BTr6HXBabooumd/WMZ7sV4EezoMxxYIq9
pbUMXoiDREqbfG5CsnbS64fli6UKTm3s5z3ivj2VZKMgicVhY3K3+NczeDK6TIoDSOCJXpd+f24M
UAGanpQdS7WH5a8R4aKKtfdLiS3kc32Pmkh5Tnl90VMzDqw4CiHs1q1bkXcXdxCah7EcU8mZmsd2
6Ou9FsQLIMJplrBAl+wyKGSgbJUX/wqZgPyOwKtDxpcgmQUga4SUUW3A7LeeFmh9/jUUik/w1fg5
Qe+aaRLCHdC5UQW5FgS1sumRjusk0XK6moMTSZsFQAxmmSO/wr+DBL3WhzW+ls//q5DVFIqQWG3w
B32eO5Ie2W8u6Eu9Yp1Z9Ql9+DbojehqDfGtcneN6B0s3cTjpb2bcFzhqTCcPuZXsLIUipFcgKOr
CbHcPqRjhLO3VRAzOTVyAWp9MA2+xcl38J3ofRrj/balgszy0yg0ywjIUeKJIITK62LfgrizYqAL
JAox/SkQNBMllO3SetlBXMDo/+r6u3e5r+bFDogl7eN4hc5PWfhzdzg9Yui7qD8guSa/PadVOFKc
cxrzP9EfdkIu6pP1hXW2qcsdwBTIkk2Nok5RoJ2FmEWLAKMHm/3NPkQQeWwwWr75UaHG/sDwjPv3
6AbAv5fmvPys17BDd9uDnuiMd8gechR8vG3pcXHTF1MhYHMa/fN9rXnqSg2hzzoDxjWXUo7BZtyg
3jbi06JCdIUQkfzaITVwPpBDRSeD8PchDIUfXU4iRyUlWogQjyvVPSsywEm5Tr10iRHeSberw2GX
0WPcovs5JnrXD7Jl15S3bnouNgc4ujw4aEkNzkh36cr/270tN+Gl4JFdc7v/JZtfyr4z63BtHwpZ
hVrNPdriEwMfGaWkjXLA4Z1q2P+rvFdmdJB4eKNxQSwe8A1NAoJZdA7wYTbWPE7zcenlXdwz5PNx
nmSTJ6kqtFmcWvcKFhnFsuOj3XgQym2Z8qpVB8FoA5ozh8neAaBi7leWCrN9k04K/v/T8QMhGRWi
zyiy7OntAF2S2SdLHPHChdLeZYZfs6xJsa5Yp0+Lh7mw8sQmkXNEW4steimAHZG4QDTXBHVm7E6n
Zg6bfX84mZBqM4YoTk+nZJvY0sl2tOTddepsSLOEfdjKFKgF5uRl58mzT3tQedogk/iygjIqerui
/nIUvVuKHbs/+UoLSLv9/T77JwRHSWOIcEeudE5AQ+LmQqIKTdfheaAMek2iRynJuA4rfRjb9QqO
J7ni0Hdt1dad5VoOql4W6EzZp9sTXIB1BWUbciNv1a5n4NEOcGrhgH0MLXeyxqb+jnCK9/cgH1Ua
3M7P0A8S/tHqhNVXXjvYknpwB5wrq9O3PYr+AuwVVYw5NmoxcucHyjDRmb43IGlh6IpRZeJYlJKm
jVxsZZctj1qzNvt77Kae+e5GIARhIL9LXzTzaxhaDfh56hEZ6gfMYlTmM60b4ICC2zrmCDGMxRfJ
RU5a/1KzgwenUIwLCU4rvfJYNwS3VpynsVij7Y2bzejLBP9i17veylTdesJu/N1xd7UkYZjildee
W+WuUYrXMygpTUtekKRsZKRwin5WdhRda4C+k7yVZmfifcl2Kyzc8Jq97LOeAEzZ4A5PBjE4rAI8
V9xWyoISTStX+LQPaMS0euFnD+F0z957yep/FjoP9XhAUk9WbA8dmYoEKoTIMwT9yOJUzxN7eQWf
JqxYaUG0ZuYDpG/jF2AniZKHc8+UFIi1eSEm1g5tFslANBstNANzRZkZ9Y4+XzUc4+NHCuNPCK2v
tf7/w4JDMCVd3K6Z2iyh+ioWWSGK+iYQrMsXt8yDjRCx64XjxAIvurh4PEuvlhb3MaykkAOkSGeI
GDgmI+Kz5zrjbibo29L807lJ6TnpSKvKqLeYZ5Gd488kOkq0itVugNOIiMYnBGpGqNWz5tPHG94x
eUPusIvIlKHeZkdibYpDOsRElC7f+DvsPosO1OEmPUena0SwvMr+DjRnOOGC3VnRxC2C8p/rjNQb
Cfh0Qh9LuhwxOdl2tbb1sU2K57bK5mcxDhWvaX8FZx+EfX78vfa+UJmii80R6DGKBk1lmEEvVqHw
AJ3kOOecMNh8lV1Zxb6vqLFiRBrUJYkAAn4L8Xo7bzosgvd2xu6A6WvgbxouHBJNUwn256H+ovw3
hYYWcNINYG5hBrD3VUxKzLILtpQL24br1Vmrdp74fwhW3aqwGNQOxODt2mPLeXib12Kk7boC2E7G
oP0bYc5HTqfWuCOj/jW4CslVPKmDIO5GHkdisOtUNQA7W9o5cy6v/hnETYldHn9g38sxYPAD7YId
Uz+EQD4VekPvZvS8oIpFm+zC/FYxt1fpJW/HKyb5I8DkRuCfkRAmxgIZPiT4c/HR15qX5uzhytRy
+vbD3t3qu6YJl8xVRQC/l61ngfgpKLBADQlMFGo1znNGmD++jun8TMZE0OzH3N0WSqeX+wlu3fik
UZHVTQym2XGt9ugKGwIBGcxMTwfI6WBSlg5+UqwCw3W8upF0bx+abUmYuOdtYk6bXc7DoqLc99yw
aXhlJEGnc25rTEn7G76xoWm0gRJVluAlQ7Ob1e2mVboBHtoccMbiHIK8idMMb7QLg4GTCDLMboWB
cn/0E5Vo99LywxDKX3VVBNXDbCRyLY8xe1LbM+VxpS0eYBAGdFSkSQCqXXnVWYC4TwAIV/Lepg+q
83zvJSAFpk1854U83A04sjZEJ5Be3au/nknkMFC3xNbraR4ABvf0h0zACZe84KkRFaXCUrd2GAFH
04IZHdKrj6xwOCgYPMbw3h6ZLSvNLvUiBPtwRJLYFv3qs0/0bSf7k2Sify3l/xfkuKtquACYxN7t
y13MDJrvlqQMbQdb7jpyqqUpFx1+Y2ObpRHVjlAAJTEZ227EettLtgtHundbAynd9HZijH/XviwE
VbwuRZ1g1ifS3PHVNYDYoPJ7eb8tBfNLponWjHNSWNtoJ2KYW0/AkVd6an2RjrpJQE1ymzMaK22I
kz4WEDDQjV+EGjZbcCurNJut+xacQ/qcWGBFjWPPR8YBjnMu0+nEEhRc1nJy0mzXvzWm/8FR3TjO
CKffvhq7g+MkX5y1GsdwG4sSa8AOIcxcJ68fEUUdo2rlZFfefj2IH1+fUfTgYeUxo71wHY2QrF1y
h/bkI++2qKAXOA0pdQQDNeAvxT0Vz+4UNypJkjSKhvpq2vR6ZhX3cMUA14755oq7tSE2L1OT/sC3
dTToOvuKyZIz7/Jnlo4qNtdI7Gq/yJ1Z7LlrZYxQnY998hxCPqrTpr3FnipATnimOvtQPHT7IeL3
FcIAHPMX/4a5+zSWlLGRRTF+j8wYVMnDhy9xb6wTEbrfL7pmiCwlMIS+suVSkHcF2NpLhbRg60qw
d0QDO1kd6WvPtoU3uFkjVrVETnhAJhdTYoGPjySFhCYaApTyU/xJny/dhn9ok49U0+rfQluSVe4Q
QT8nEStW/Bhd+zmOvsKDD1ORMA9m+aqLMEGbpIliV0hmAfKmoabDjn0OAhjUw+0aG89KZoMALbUp
XUQAuDcmQiK3qVtjl0fj0F7eTFiXbCwqTtOab6eEnEgDJfRsgWKc0/+AszEtD0P2P3p5cv8LdCZx
8D0/ZCzuBnB9fb0/vSNhtX6nKExEgnc4OXmgXo+op4R6bFrbB2MyYL80hi+EP6nne9Ar552PhTh2
VT1FZ6Rqw6auq9BHuz9ZeIpqZc4a1GcrnkFZTF1nXx5/1K1Ly0RYF2hfSiF5Zd+r2mh7ujrtrcVW
1hwDUNIqt/XShMP0CBABP58Hd6mhrQK/TOsbgoubm3zk1te/TNQLbh3YrwJu8rv9MvvPtmE8FiKH
UGTOL419z3rvyzesnfVXumExNMXyw/ePmy/oPrAuP6pDin13AgxwmbWmLD2BhOEv2vQnKU+2FHf6
A0dLw/dpuWesMLFUrSE139jh4PuJFCUK+gzXeKxdMO1Rx4SLohyW+dg2quuobWfmT/AZWM4y4u6n
di/UVmLXMCwDjJnQMiB72os8/NK4D7WZ2drQvlhbmRu1HqaKhIXz/mP+QlGq79B3fTCoWC+swtnz
U5L5LzCMNS5vr9GIbY/HytveGuR6ouclgElKgARJWKwtQiSyf7AdbXhEgfIiUCiKdf/b/sLXRFkm
i/Nat8s56nMbY6wWLocf3BOADWOy2cZRbchY5YSTgNPobW4lw02zDAgJ+plL7fwIOao9fudU6yx0
vTSBJ0Zx5z4CtRypHkJYBDF+0ilZ3JYq3PFZbq6EA97g0zSbKzVdjQegGMIBKgrJiSvvtIZjhcQd
C7d1S6pe6fct64H7WtWy8TpOY1ZPWwHPT/ydd4a/q9YsVEPwT2/ZQ7sKEXqSzyZWrzEyQKhOwwnp
UhJiKANmhg7V1WP28GT5qYhQiJzxPbHJsmsgT9XyMNO6XXfRs35CsiDUTI3HQl7eNi0LHpf4czhQ
c7k09WwIBBolq6qYvxu9GrgwCV2KEbkh8jLLJzMxA9goOa0eFKBdtU4RytFGOv3galcRi4d/SWHQ
PMiv6dTTTq0drS1P6Fp6Uwa8HUUo5OmnVNZckahzs3Byzy3cnlme3GSJR15mDdmc+eVAT2ayjJiv
lx1qcxfgyjgSf9RjWC6sserQgjG2TY1s83SQ+tVxGcbGXCkLIZXDSvf2MPtmyHYJ3IcjTmiscvOy
jBmcYmBCCO8L4pPNHnVeCMKHjoteTBEdRpDCebKEYx+Yt6nthL/qKLSyEFlTsCEyNGVg6KP2LQVH
O+ZYeHAp9DIHDuHN4ygkGW9172dz7dbqyo73wPLIh4tqs2n0jy0YFgYQ80Jz0ac1ETrvBfMZPmjq
/S4Pm8DGgsP4Ow7hR/jhqmzwVQ8PfRJeDKDN3Tt8Dp1HfqM1Qt1Zv00nSqWG8wvQN9YbyI7byZR9
pCF976qzcoyXj3aVe8Q0/SWeCh4aDMq5w1ByL57lsng2aYlCUVnA79VfHDCXeFEo/fBRGcTKvpiq
0ihUCW+4PdIYx9Y/NVT1AsWTc8uNHq2tFJHXSRKIRt/DJihrgnhiLcxx769fYVS02k9riMClc5f8
2/4orbqpKyRt7A3/5lB/fjJxfVxZQtha2qMSNvMDBkSJ7UGVc7LOPvhRi7noFJo7tdakeXQM4hA1
Bs2sHoP+BMevk5Clo/db5mOk6ZBEGqy2iBAGP+P6JLB4gWY6CFWwWvGRNNNIKjz1MFaUCfaqEWyp
exJJbwsat/b0YJ6MqfVZr9nHiRgkjWuc8VfKEv/+FvCY1eL2KV+FYBoVStc9dgbJ2gZkqRcx4r+B
4dAV2golNnHrDrUuRYflFEsNP4Lmv72+pIWnbJDcaRi8BtWrzi6oltnQ/kXeftcFHC18GbqTvPEB
C3ZoD/DUWgSYu1FCb5GjpItXsh/EOjCls0fUNnjaX9oEFmBh2pePWjAO/6TwlwfLGI1JFybwE6Bi
tRrhMLiMxLMDE44e4OYiqOxNssY0az2B0SKzK4mx9q7Ms+/jkYPYv2XRfo3CBtjT1bD0b4jGXGV1
e1F1BDVrmNIdBb1IeK6+T0VlUgmjsRclvNo/fIhsUwdEvivjes3fyqWh59JBXTfp4cpOL/vox2BP
xHndo/LB57bjnv/P107CM5AC9gJ2X/Abw/5gCPP0kLYSbXvCnxMSIi6tSygTVxW9yfw7fLB+uIeY
JNC76jtsP/Tj5+93wCqp3DCTt53PYGuH+qgZsR40b9NgL9N4N8dLALjUpz9kOgbuNbqapTKtwNkj
Id/egu5Z45VKnPK74wGO+t9Z5NeaCz4PJJeU63Vdy51kQ0ZrMUwyAFESpGzKFESJgRDrssBM19ZD
nvh+25zVXmzOYhC1753VLyGQV/Rs6LOGtWjzKnQUlTKQ0fiAXkg5aIJyFRoHloA724GNHtyJxB57
j+8FPJhGMVlKH0fBHTyIgKJUY+C7DvzWJOnZzb/6I+AYyYFV5Wj/3jNDAJvsmg6h2imji6RASgjG
/+RFl5/rvFCOzHLwAkEL4k8sksMsOGgnJ9PrkNrXB3bzSKnnWppWgkJgSkLqspcaG9eluFTrTqJk
5coKRv8D/RTcP32xXs83CQ3/9QC5BScHRd+NaPaWI+JN4195nUIdYG05YXbF9BsZwSqnZIZSe1YN
btSshAnWEpmzln1f73cGeElVajbiQ7YDTz+KwmklM+YzgV0ceXO/OprAB1dv5IEssp/0juWUsFa4
fn9Ftpq+nJI9qhm1RAxQV7OqSMrfyUAhFgjIw9PNxbtz3LvJb90d1tAzQAbdozDjLPDjlD037d4C
ZimRZb3XuZU9Jp862rWLrWXXubhIWYchxYJ/Q/CEKNRKMEvJZUg/AFX76XZnXr2JjO1BPPrjfsXB
tQ/mn7vu5hjW7LYX5RcF/He3exSHSSF1Eo/Qc6n6AtOexGnv42xHwCx7BE84rat3kJmju1seZJTu
+tpic64w+a7sgSzdccMpUEsA981/20Q6wDqNXGZGOT8DbBAt//l621EQ6Ae0KaD9gDJIqoDs28M7
Rdp5wbNSialJ3TG1fwVSukaelnE4S/YQCGbH3JtirUIuaKww0k+BhB1YPYeUjno9JNtky2GncPMH
EqlBj2aVXlWns2olHTU+wRzpEokj0oNTQZ8QDscrPrCTYpKeNCJP/byfCLJNAhHF/JsWBLCtJO6M
wWWpDMLkPTuXq9BzG+VvtflHaBxci2135593zt6X2i+CRVbYPH9bypwCRenVZC4TYf+OEWUlfn4A
Bz6N0WHmziIFu08DuXLVz8Lm9NA8aXwa6tugWYMJ3vmH1h1kdfRqMAGzzzRLa6xXWt7Vk9ZaqSWU
kmsQ89gl1bvKDqzv6Rqncja3/FmxOOPJcEeA4kSmyLZ8UFiDDc/apSgdpjIZR7G0qFUiIi0X4tst
TmBE9yL0Rbwx9WumO5YISse4q8QVjkD7DbfWUMd01An3A+6rjuQg75XReZ8WSfSOT1h/tKuaSf7o
8u1PObmMb81bYuceuGCV7M9oDmDrqF7sCci8oBXKcQbzjoAehpPvQQaiZU8Uv2Dya4vlz90D5plX
87ZqDPP9zounC97RB83AqzWEx7r8NdBN3r2NDAgFI0DYm8dbQn16Dfr0lFVnx3VT26dBuwRdx6P8
svaVVpTg7mfVcaWi3FaFzLSI4dT5Muf9Wx0g3HXw3QThJWe65XtGnSGP6sMW2s7OfZVwjWFLI77+
Op74HIEkffSqFR/W3Tn4p2suaS5/XNNoKsth8RxHe/66AXTIPXgp1n7GrYD+SvB42YALD6a76ice
YpopwFknrQmGSGDmeFDB9GAs5aJZqxbr3Br9JmjbWEFrWV6ytMnpauZBaqeFJYUgv6S6tdHrPOkw
afFvuDoe4sZdu9tMkf6Qy0AiWzkVeYIhLj1H0DPzRv2mYvqCa6d5Jq8B8puYLx6VizVolzLPhk+W
TA0qtBmTfHzRNLbID3hrYV7yik5QeECQssNTI24fktXNHYNfZDAhvFGsFg4UML9aUiI3n/FVqDxp
LPVNDa8rGdV3l634r5YwxiIxhVSeWn6JmcbQvMUrITQco9/IN0bMWStBSqbWB0LuizwlScGrb25U
J26jWfFjJR+K0ahtY8EkCDhkMC/Cb41iPLG+LkczcmUWZ6K3l4eUwkleDI65hWkkwlz9PKgK0FU0
8++AiFIOBxP+z3wEnzd5bml1F8PZQPMBoRQKDyxXkOdAHW/kkZDWvqJiqfftIH0jl4u2zAa7HP4y
8X8mhXG28BY6ooyF7Q5cPp9MV5RdSKRvxtoDnl2btTdA97AkGoL4p3TkJISDN5d4ff8g/c98PmY4
iBONXaMrLLL0O4ubqKSgdwWd0WrCs2QhuPxo8bj9Y73uy1pOCSVGB69HeN1LCb0d3i98cTcGAMoO
20wxWurJSKaQq5jA5gRnclJCBwEXY118m1I//BCLoBzhtXOKz1DbC6+9wZnk7B9itLT6vN76QUxJ
IOfQex+6EfpYTI5mIjiBO6+0eAM3EYixfGsxv1ZY++MuncIfqC+JwuD9PN5pd8EzJleEh2oDcGx0
ODIPLfMn7DYxneVP+SpNTwFH3XT468kN+RnrVVs6isIiaq4H6Uxqkd/kUvB1XOgipxOsn+qu855n
x+/875GvlDpuveihya1YX9rf8Pic8AGp3LALS4xxspVA6d9+YAW4bmJKgkM8qOu4QTqqP+aBVJcZ
8jAkS7LsXryauXlbfTzK3Di85jROhx+OlmNqrs8dljOm6RIerAiHEXk/Q59g89uuoattoIgPl434
FVq/4WtoftJxfohfBNvtN50QCa9/kiTaeg2b1QQjzbaVLzgwK3WDGTaAoevp4F4wdEoHs9B5CbKO
fIvALUryO8sWvH9d/H3uTtmcmqYN4Sfk7ciH0Fcox8cY/EeBThcyEaPC0g19bDzf3sN+VihGu8iW
MfS4opWYONbTp5x5Fm3L6Ddh5TDRTuCfkaCzB3oL4e9jyJeqG44Tc1YmIEq2TSLvxIrXTSvNCRp7
Da+sf6H5XxNj9Ud7SVXT34XGFyskhIBhh5TUNGAe8hqOFNmqzDMXHrSut8ghGCsbHzfiOa5SRWgE
yQ41uh9GiyIzyvgsliaFX8BtZnNTTb68zuY3j+AQaLzXzhdhpZf3dYUcA/LJ8AUdmWBz2KEPm9me
iDfvvhYupEnLOxWGhGi3y3GtIIKsGG7M31xUoAEi88g2Jlpo2xnn9b7iee368Wa8i7nqga95K1UC
+9AjhPfidvgBN9jgVwxXMM3ziO+GubbHG9g9lz0/uw/+ts//9jQwSD6zHxhKGrY5e7u3uZrSuYwV
sd1hQDXCuSqmWurrD2oqGHpE+JGuG829WUgvHLJAs/Pv+HhwkwQ52SgVCpUbdQ8zz6o8Y+EK2X+4
2mrXJXpcz2EI9BxawG8epAPaYh2/2iHEnq1fHkx1ty4ytC6iPC3MLx+Z/5N+I+vZLQkpdZWjjPIB
24prBtpll76glntVVdC1fHl9C0j+72AkPEmKHQQPto4n0rU+yKSlfL7sMpxH3ljoAsamZy7KAZH2
0zhgMNMT9eADmPVT+bo77WCW/QmGW1zY0iLk/lZb0/gvrodmvGkKdAiHKXjLtaxp//tY+iI4wSsq
ut8Bo2HZDORmaeZTToXdi6snZHBIrFAeX90kAvi8D39BiAvd1KKfEvsSS19jmbprIop9mNf1+h16
GrVje++ZcJKQ66V7cH1Bktp3kHYobVpqjarfRK1XAG38Va+cniiRLBhdhErCAYrCW/Mw0GFF6cbk
1OoMFkZwTbIunNAYubkjy7k9tXF6yyHx7d06g4fSouGKZyUU81qCq8bYhVBrjFv9q8eIVfK6J1bl
MLsW7xshsOFPjrqlvp1bxMGVLAGQeaYMCOobjc6kEuoF2Gd4ILc0AbgYPQXzLJTKLnpiCKcDOD/6
wHvvgEzaAcjWIsEhPG5QKiwKkAnVUprsIYeMKFfsZsshscOwmPzYwPRENaK8EF+O/cJS1B+zoD0y
O34XSY+R+gafV7lo4k3et2LzmgHEU5VwwLbHFjzA168yybYpn0ccNxbGN3SjSW1ATOQMoPghsAEE
CN9Iv/gy9ZWPccfi83NuVEnJsvOXwgmpyeYALEVJUdpVflCUErSf3I9cgcn0muWbC9tSgNJt6tzN
BHanahzy5qNT/PzwbUIembrQmOLQeH8PSrorDGWit/eFKNyooVlsPBo3GjnPLEXVtA9WCIWw7iI6
Ku8noelk9ALpQ5wMYyrlN336Wozr1yudxynJMj2SxA850wMjyW8ONwLKXAhI2I+DK7G8B2LsadIJ
exyn0LnDPO/enq54EbccEXXqjZCzM6r5Xek9RZl6OSeBYAPvTGiaWAh5cpSCJEIhTZ0sovD4Fizb
fTFBaaSzsoyfzcz/wasMjz6aUQRAWpRw41W3qkYutosl1iGtGaWLmkPF3rDibfcA7avsnvxfxwpY
KDx37xEhyTktSjy38VB3+E1YWebmvz6Dv0HauGBNp3/UocdYOM13L2mAIRm5pkGyr9+acSg9pssy
0+bm7Q+ZOUY9v+uA6XbwScM0DUmXf3oJ8XdLTfQL0wqxXaC/MaecOZPRk+BM6Q0EPod/6TTbmc6L
uj7tW1tK2eCfUILAWWXWFu9x9DWGZ5g+AQXrHPNiSWUBETVlALqJczupg6m5nVFFrS8+tqUhr6g3
yOvq0iYv0UIVRl0/syjDPWp48koZzETKrFHT59gtGO38wwXQwu6O3/+f2mdmZZt75Z/Qt2oM/CpP
f6C/mwwyeHLNhGn3MicF42toHnmF2AtLtY92nxE9XUl4ujdRYNIPZ/fS5dU3aUjtWDcbW7VvvYBw
/s59mJBrcja9cNmvtQWKeu0YIlcIF9sDln3ZM9dDV+zdo5E9Vk7vsLViYdnvdd5mImMWg2zT7+ht
fxvNR4yH7jwx14mj+4Llu5SHzNCqxHLE7EujCdbmmfMyZWntA7XWKAzaqjrJXm+EteKThFSM+KGn
IHccgGhdBlA+25k8Kq4nyXN6e4mmISCGvvaGs4kg63V+BhdOFmE8GUiIxrNRuzwsbssr+apDole5
SGLBLi6zHhOy189d48FNPZKRnsXtEvZ+nSEh17qLoy3UiKPXxvmKGGSskHhoTPH/rC35vGfMMSvQ
R7jLStXE/Gvaw2OB83jAxmGnyxjEV4rxhR24xpHJlCU5TUF0gS1MtvYWvtZPvPpxumCgO2Sl4Pmo
trv21TeFP7Eg6PbxljmSVwSQ8lSxIAYHbk5LmZ6AetUA4ZpE9rSk/Amghqi646aVRIVm4lg81niN
HQ1UJPZwZc882A/3be12xZwcrCs6LEHbfiFmlVycFTNNbBalVCmOpNTDMgg4XSExPfjgG2x8lB4m
v4iCzHuPUaHduaeHtumJQ1WxIrfqBE0bYTcjppIj+kvjzu5+ePij6B8ZSWACOCH+OjPxU3e/Bq9U
PhC8D3l81egTqcg6IxVyNk2HukVSy8R5fLNeJD+BfM/KqinQE4LPzk2mqoxiEnaM1wxNwoCLUQJ4
hRs9UxKOy+2rQLVokRu0auwhwoUrmK3mrM2I0+ReNk5eKdKQSfBjE6uP/oUCuZbYlMQjvJzOrxlA
Y8VAuJsZ9dZyVyy6UqaluypC/Ah3DJKizzafQB7j0L7dT/FDQM/IxuWvpywy963fGCF7yBo0I5v8
3j4QeRVN2Rcfl8tdoAeMl+UA83Df5k9ccVSHWEg07HmN+kdYprNuJGOgK21Zb0DtXeUKYPcuip5X
wzeZS70aTO2mjZClMq/JruSN/97kYg+8zXss6HQmY1vzKVYPqeBRXOQ37199Fn81/P5hEBpuWyqE
Bt3fsfYVD2s6Bh/0OPzCm/1i1AIdSNjNlAN0K04gSengA/bWEfQT7KddMPLrdgvkUwhLZVJgouYg
PvzdbcA4xcNRRyR5qzJQhZbzxEiF5VP/HeknOM8k/pyzsGmMC/aflg1DyEzCRfWnwnM2JYp1AXGu
mwyr8RQ6RqOpsE0bGLaAaK3Zf9tngpe3UiuMBkBCiYSnMrYl1GGLGCr6Q+hFEpLCYNF5iXy/MpzA
3S2OYqqpSG8PbCWZ/ZJ5Wgbmr9Eh/fDelNzeE2Dmfyjuy7oBkax0w85PTasEcNiGWolNUV2AGC/7
xiDCzZHY91O6kU9sVGIco3d4K6BcuvPxgnne7CHqIoCyiAX29XdRUaqGoDhpd7GbSH70FMcaROkd
tLx+7be6BOPSaSpiybnoscDyHiEoUaeRY8Ykm5WMFYV1XZZVbGDJ9MA8Pshh1TVqPRqvSTXE4fp5
RWJ2KVdAtDbOQW0OSe1gBWsIiNEoFrOebnUyq/VkQiOOSiA2dElai7WRlRrpIB81gnG7gI8Qo+A+
BDigF6/KuMgtdFWHjVSJIdOgfFo1Eog+susPa2BFWl4RP3MmYcPmxRIYWv/wLrLphubcTKVKbRVm
KNELe0FhfCRj4F4rOHO4GVP4jcUZl7J5qMGPfuRkCckakp8m79NadNzu/gnHSgxFSe/QnTqFtDZ3
TDZlBjb90MK+m8tC4hyNUG1M+1mtDYuBom2u0R7BRa6RD8Ksyv6OC61IyGdAmVbLKNer78rcSLaX
onmK5l0WL2BZdvzZ1sKZAkqCLDn1QwqNSmwJdL1Lum3FHJKQldxlTMIUhzkf7XkPfowaABvDGWuC
WUwroxnrQOi16i0brEUS4Yh8+yUydwPy3GSIh538wMWqGkd14t6lrAw2SL0KHWEAC2VhdLUV3Vp+
Xc/8IaO5rjGQ+/IsDNXQ1B7IRYm3UU1aN/cKm6lIyBubgetqFsds+zYigaUaxtE1Bj7PSTebAC94
nyeOY+hRF3hvmEtLqCRJCu3VH/8CWsYiu40UP/kerIVio5tDond2Xeo4cD/ZsSWUfZWC0gn2T8Lp
OFmkAY6HB9W/sfZHkxBHCYXvHaOVU0H7a41WnII4tZ6LhNegdmPxA7UGQH7JlPp19IWQMRAQPT7A
TEjkTherPvpjQO1Ty4ytQ1XtrlqhIyvTdldG96anhzm70W2Qe3xclNsW7HqcoZlBmiUghaRY2jOh
RvWNrrPycFkU+3dKJRsQxYbleJrzXm/saUW+KK6vJhmy673K7I3ko5qM+kTR09GoPk1Wdaz963tS
THHvm0jLsK7cgFIg5sCiMMdVyjDXIrROYXCLT/a8Kq7ouXOG3pEKCBXM/fqOQHpeBwLwjj/na4Y+
DT7SvHMPSRHY68xknnSZjZhO6X6L9D/Lw50XymwsKmGvKpg8hwMhwH1ovN8DVWmUfVcLY8RV5fPu
cvYrJ8G9XNy2d7u95sznubRil751Cp9pDSwVZ8JW/oOGxA4zkJB8iQ8eL6h5uwbhvB4u4auZ4NJX
1CPX1Ta1AtTIKhZUKloT5YjwKsNU2svZKlolI1K/g9yI5Azjfq6jUKz0VZ1rzK1rFtcRU95UXR13
bSVs0QDQtTkcwb2U6bmVrQDindiNJCJSVB01lkn7uVxnbFkwlucFZ4gJDKzhpKc4rmtfQ5tvLK87
c/pXijgEDoDb+V8jWAx3hvnFNXAL2PrMqiImcKRU9aEs8NvMzaaFdIESPU43ZPYLhmgibKNHTyRP
dw9BUv07GidQsWY5Jfz9BR1zlrdPdOyii97Z3U50q41ZCQzQBUZLMbSp4T2pzluN37YRGkXuIgvk
CdHSYUR1w6YAF9NpD2V6WFskVZw2U3TBMYZPPJo+lOZKXbtBFYiSuxEXmV/O1JreTfwY39qV8d5+
zG+SLmAcj/tw9eQS7fpcdQUKwtpvUS4yO56tsNObxnq/T99zU0ew04gN7cfTr8cAzYwAmZTcQyB9
Wp/J1Fa5BzKejIPZLdrtvjofqW7QOEX88IeSEJTabmLMksBHo9CY23hvoI4670G+PdVMc61TV7mu
t2+qfCoOrbFiqg7G/jwFGIB5Sx2pUTUqfa2UpJ/fJ6lnDzoY/+TboF32ovWfEHC31GoJL1EqmW+5
aWMq41HFe7vQq/sUvx26qPvSPXxGUgJbi0vaVN2axpvm+nz010BhG7dDQKIL/22Nis8rqb0qcBv8
VgVImfuY2RDDrQHvF8k3Wshklu472cSq8AF16izb0g+6dX8G/A/tl9pdehzkkF2WJrJJNzFMwUSy
Z6gf5jS+r4AW4q/jFvjRK30zyYwIWahHru0vC+VfdsPgmUw6CybX/uwcCkqfbSPqC34dmKHD6lpK
SsyFZSG1z5x6/J4QyWbB6GO9GrTykNXnI4LX50vbdR465MAYMgAc0PW+s1wd7KCMt6VYaIcQwlNB
Nh/oSXczkU75rcP0Ng6UyaS6dD+kv1IrX/4ym5lgO0Mq90fn8RMaIMHrh02KTOPin/UqcV/BLwb7
SGbJTEicfVwda/665scUTP+PomIgN4XDksEmd1lJ7QPPKRauOib4MPQJ2ADZcaCfbT3rfMYDqLuV
YuLS1AaWoMimrbe1t+SSfyjzlBnbD0xSadQ0HDe8Gy3yQ5iamTurznixXKXH+gOGX1kqVUOM6TIV
89feDfSSx0qfujK6lFBwmooJHDpdlhnr61u5N9nROjNI7Vj+zwhsQ+LYW133wuAYEUxfC21OY8E3
pEOJYeX3YpTIsnsZ/Sn0Ow9q9dIsdvL4W96BleBwE3G0p3WLyGYjgBRdV19LWYARQQQRkYxPOyBo
NcTlh5MOzHqcw0cgKpTXur5F3q5Tx1/SwIhwNTWoMOIv+XFjsovcGwSkfZTRHsb0STi2fOk5Pkpa
UdgDn061fUWEG5rTPv2Pi/IHzPXVGcGEHXSQaiJK4lhk1RNYfoLv7gSRPiaXXPeZo44PWZSseUjk
4pJTAUaZtvC8hR7/PchbsIG/8jZV/7bz6JkQ7Q6yy31lrsHXOhNFino9tLnleBZJjPERTW8M/Myh
DC/UlCjPwoWe/VdE0rizjYYVkEswn5CFXuvIzSnuhAD+yngs0e0NUK1lh2Cu8CS5rNO7E0J1JNZq
gnnS4OheJv36ODWV/H1PP0LJM4/x3BWdTNpewMjPAz93n+XoW02ZsTz+foYV8ur7ZQgOwAkNgMmn
wXv9CQvFIkyOTEDdeUMQw0UfxhWz+xBs4m2ffD6p2XARKB7E+osVd/WsQgXhYxOm8cEqn2z87tGk
LZ2X4rZPFtq9oXX7FV1wQwmnc0znfOzef9GA3xuuSebp5O3rmHho9+mfj5JNyKXlQBizcYAn2SQE
bPyWokHR5vlkdQMwmP1kWAYlf5qokDnir2lPWNIVu3sUSYqNNaqlGULrCau2/Eec55l5n1GwF3bf
Yb9aCEOWA5DRtLdqFNgdRctMIcFHxyOitXraVs8Bl9Xe4j+rlW/sakBPV90oQ8cVf0o35nLQF9kN
66Tuzrtcfu697MVteMVKcBas3ZTYte9ua8ryzbZ0w3sIMZ8IHjpjfVIZtidHFNX1tJhohcAcCRdj
vwF+zjD/6dgo55cZoNtoPxjMhrZ6+T83ArBK/UYPyX+Y+hTIrF1B80T2x63aeP7Rj5ENp7nDono1
Bf88Ly5cPgWuT6aR3bSsvS2VlB0Ay4Du7iHl3gB7PVSRfuwOPIsZo+P1K24UmyZdVgq6Mtad1RnG
EUUySbapAZJpfYzHdk9NJ8dU9fbdIjeU+JVM2totfpWMBY4zjfqLomOIC9XInObLBkoQ5W7qfpwo
W2U3/h2hnlK3COtSch+mH0VdsIfA80WkSdKFtXebZcqnxGucgNWIMu97Zq5tr1MmNomtLTOekkfr
pcyIyeygDJJ+RUwfV4gk7NNObJj84CGqasd5c0AGoJytttLQQRYj97vFyvQ3750uuNu6LultdMQ4
tl4WHtLsnysf7jyTfjuCmUGHOB3M57yGei/8C3eHMZaGabC+/vCMl1pJ9+pXW66iNk3qLiya3Gss
qH8dtw2wIOYRRZNAuD5p31gwV84i55q6RCXZmBOjwqtTFIEXn/w/SCChROaaCRVYjfBkqZ6JwS2U
xma72dRL1h7rF1hufkCF3EkdLALj4ByrYlQmM9c0tZCUHoVlrjGKg/n+TOmBfbyhS68naUvDehz8
rwnMDGSNG/pH2Gi4FXyBoFgz1A4rXInu5oG7jtBtBKZkKvMAtUC5MhM2afLKuZ8umxNI1CxYSbfd
MAM1uLqs6LSmWV4ENx/WbjkfZQJl96/ufYJ13E6aPgmn4oZ16VYl8HL3JU5+486nypD5ns0yzsEm
9T1FQUuj9+J8akJDHA8Ts/rhcpnxceb2OZ+TFq4UEV1UkWUIm+GCP0cFzf8A4ub5I+CYA6jxV+Ks
IU1UnCearq0xZAK6SWhiBs/ltjUX/Ac/oQ497t73oafmMieb9fWI3O6cHX1+nZpKRwQUtG1e2VKz
oKhcYgyYeGn7TzvD8KuE8bLjgaj7tyBM/Sd2U9dRtfUiov5q6qvLGnw8YJuvgfbqMKJZXlWVJBIB
7GJRtflfQs1Nr2tVEAylU0QnXKYubwxW+sjGg9/j8NOrDU6Uc5x4r3ZSuy21ts90PrxDS6Ug87C4
9WmfEs81lLMNAXXrYgbpA4ZoWVusEOrYzZNT1vAOICJtxOuRc5Qcn40jpezenTtAb9PvBtu3SkU4
MuAKi9GEjEDvbuhoQUp4QYlyJ6PxmuqKrnqeBm7gGHl6P5k3b24AH4rje9zGBeKRWawIiC40W+vQ
lDuiB4PgEzAKCj608jfcKq43IIcdB98ZpObTm7EVCy8FljuJal/U0R/pE0IPwHQJQrDZ8cTRsLRb
87RLMw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 95536)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztB/h+4PvAs/N0XI0cN9OT8nV3gs0Dpd/RXDA4Vc3dmwziA
NwElhjRY3VJxDTskfz+mxWNFaf1+mPePrYVqlwPTMBAxpvGimC8dYYQqLJKeeN1ZgTT7hwUkM2z1
Qy84CcCZcArvoNTfBy0dkWCCscLO7FYjYdrltlJMSy8CDdjskSxeftCs1jkCE/tStmrqLGxjbT6f
C92mpUd5YCmVlDJSoyG1Rmk3H90KWuHUMBc4d/nTIqIeHq74s/5YZbg6Itq+omXbAlchsha/ae76
9FWmmOPV5pGgbO9pUb/MAoiGnE0LV3UxmCzxLGMR5z068+xQRaJogr8gIRx4YzXucEDuMm6kq+U/
DJ8q3+UroFofr/QazQtIkbprz4hnKB1pQ9WCRHlWqYPmrTOztTQ4ZG+pAcx0IYfnFhwKTspFW+7y
GVx0kYGoMrgq7RbxX18WgYUZLMUFfRe6xSzxKiK5kNCdSzOH1JhyEU9M4B2sCcF5xcT7K2tFVZhx
cOoGlhAsPEMuJPF65qYCcRfu6UC7PJuefitD/S7Rr62kMcVw6pREvkYzRs+qsbgNnfPabgzwOYLp
olR7zI8hlqAGIZzAnxQDewB8HIRF0Cgw+b9popHU1CVbEfrPyAP2H9rTagex/AtB726oU3NS/Hto
hL3uC69KGFYAENJTVq04Ff518xRZvbDhZk4t7/Zpna6SOSIzrODGUJSP0FvZZ09QlakBg3Wo50tY
pgmp4DoT7CrqwvHOwtpgiLSWvTFKDLrISVTMjwWznwzIhQ773VhYwUgBwfVumnYIA8G6jaBfBGLn
337ecvtYSoD2WCjY57N+HiWBgdUQDQ3NSmVXDdKaQQjU+G8lATwv+bAb0d2har2upRJoeMobJ656
sfolUjfmew0LyjHzcPgiiMXxmQ//k5PhQRSAt8ggHr1+QYtC5Fh8GgB8scvBnTUM1XAO6R+HNs1L
U27gBJbGILSvUpTBZUXNkyoi8+s03L5a+vlwiEGgNBCUxq83tbJM454XJo07BkuS08KsFVnKwFol
BUxHZ12vFrTlJEeYdgyh64SsThJH99ZA6uEJZTSV37DhOLcIz86Z/+PfhZiByqnY0gn+wYCvOaR9
ocdEJsAWit/14k2h20xNDsh7vHErwyFqka7Ply4vS69D1gzEs/cwndFSR1Rm4eG7Zx13Pb2eR91A
vsj2o/4d7k6a8tH+bI8oDZQ/Qik/iGzOxZd3OZ9GvU8W+nKFx374cVoWAVRDAULUwyeFSZ8E+i4q
dROg4VnjRV1scMxi2bcOCuRJbX6vzKu9ao2v6me0KWbJrYk6Pb9VqAXmSAuxX1soQOyX8RLsDiWu
87+V9QkKz3gnZoSnwvxHt1paDTyWjfL4QMWA7yN1HbAvNPVY1XzuiTaKKEsyf9tvN3B/JY124zWT
CwibACdVqWqVFnC6vA4TidGx3yPOC9UhqDqcnqK5yfS7XC/KBwTP61QDQmo+8oWydyiuC+/NKVvt
xxNgeNW5WZL+UPd4qQ4ztuHmm9pfbJYKiuOJ4PkE6fuWkYPIhlX5QNKRqmLlF3jI6g6q2jl/S9KF
osulJvpp9IreJsYUeJoAOUYKglzMoa4rbTolwNg1kaiUPo7l5mXLcK0SujbMFWWGBRaLCfleNqCt
zawyhYjxey/Hi6IAQNbpyV42kQw66RXAvkbnjvc1Q/4UJ5rUo3Y+BfUc/d6QtoQ/MM2DnzZSelhz
wuszJzcVPod7VaEeVJQoYhSX/X+K3VQKZs2qHjRAh3XGV9YuAF3++sWBmfFfgurXmByZIYDa8kG1
7ZqIxa03vBFzHPJOv6aVvwWhnLmhSlVPCIHJxHiCGClZqCwm4y91AzIrXc9bPQNFscMLSg18PeG+
DaO3k99xUA9pn0STbk95TsxkbAAjVNbWBxRf9UedMz2Sj3o8XoBTOQYO2J+U066n+tTbHFYav1rR
9+sxamPEgAx/m5VI7mTLxdi0W2dgRRA4XDWHFWifRPN1KzIxNPHcTykgw/Lm//RZxB8MPUoBtMTv
ZLGrbVtckg65yrTYytUXEVL0eEGX99q4F5ZD7HmggQj/TehQOqyJaeGRkF0iyLX3+6bJxTqZWTkM
E9InS3J5wzbPVE3Pnz95yL45bs7pjKcK5Wq97wYr2xOxkApeasVKwvVSnGdxZ3dD8J71KiH7xG4j
IiU8QzbswZSUR0PukpVOPr7GcqrqOww/EAwXmesEJh0iEamU/ApOkbw8VZz0DcNew0BtRSv4oJn0
YVzugB/ed+9BIWsevE4e4JWi9vIXmUBT/uxNTF4cIDVP8RoxUJyU49US+VYMX+h6zYO0wxW/e/3q
GGFfRTxrDEX4+kwKXlfTe0Ryfled6Hfe25WkbytJZsJO11a+oiZrrrxLilzx9YraiqOSOJ0leUdK
6f6LbYP28aPSZxITy7N37ClpKNEZAsfvjXjI+fU6WItoDfHlnRgUP8kk6pzNyr2cSv4Mlg8S7zvo
ctupzXJVB+2WWab3RwqY3O4WwctcKkE7Mu9IPJjczuTATT/gFi6qOIUy0IeuDBMu7yfxvapNVXUw
x/XHP7kpFa5xaFPZLGgEyZwXZaOFNJ8gpmEjnHVUV8Nhrix4J7xLYfZ6r0+AiYhRCMMbuV46k6ew
DJLx1p3eKNSDagcWjIFx0oFXKM1MYJkymZpAFr+eTGw2up4fXuKo/DLd7vUiZYlt18Xw78+btiEv
VZCl5PS6ecifRQUmuW7wUQLJ5xxXco2P9v96725mgey2TRdWYXLdZQ1V8zsnwpZhINsLIMM1wT2E
Z/4Jlan/b4Zsw+9yMPAEMlN26qzCpzctSH/z5OrlpY49tjCWSpkqPM1l1BpbaAbi5nfYEoXMFOeT
3jTzFbWQ2tmzc3FPkORk9SqZMGl0agAeyQagVZsLeL8FxdQFK3Y5MgwzIOVV9N4/ouRr9BMhJylB
pE47x6S6ncVe3PPCxE1R3CYSUJJWb14e6OnlbSfrR1jTCppWEFUstCgOAU8m+D5GCqWe8zdILdlj
YVMbKliRzjsBZYMiXuBCjZYpJ/hu4pdE+56Km5r72/sGlwpLh0Sp3qFx3/QY60or8+nqNxjRVqk6
9Pu3EvIRyKCuk1fExvo9V5Zs62RrE6CxOL0NpxrYwn7PSChgdL6XSH+DfuTLAaDxXlkaM7r3Sr5k
6FbBdl0Bn4I7rwYV1cA5kPU8rGxOt1WJao5O9kG/TbxPqNPdrG3ZlEwSzi7J4QWmqCjzjzewXt9X
zmletWZ+HZMYVcLf7BB0zap0EO5N0XBbpxu+e+h+OGrXmFH0vlVv6jXXgJVEZhVw/dV72W+J4QvQ
7N5/Y6Hr5kpPZZ01uoNwTFORiT/PwJLbPj2fBb5Gupszp4mlgz5O1srWhwUzJ4ykKwhtQ5tk3ftx
EncTUon2WC0cUTNxeAxJTSs9wFPwNskezNjJ0tnXdwNiJI8kUrRZ9oszqKoasW8PcDueaSwjb2PD
JavrQhmgEOCBAgCnkPTno9NGlcek7DcPaq6uhwb50gYY2l2UYPMAcfrREJFdP8i3XffmUArvDNEA
hAnZbc677LlBoxG39d509+AoCHpo8BYl1DjMsP2+nJqaY56Crq3mip+KpqU20a6GnkZtXvPh6DVO
YUd+d0dSZUBv5Jaf67F96NUK/ZHgjMitGyfJzi1QzZ58EBcqYFCtNnceVpAtoN4bL9dhrzCh0nHg
MIUuDgdLdZg56MsdvfuRWLF8b/1Vh+j0J0VBvAUlBNvU1cM2zvUBkKhgPplG/6+J4+BgY6F3zNs2
E8aTB3D8gLnt4PtbmDbg5tbe4C+2DVb86cTrTGw299kZM+ygqVuiJVLzkM3HoqyCTYi+CnYwTPK/
y/XPY2wobFm0hVk+oUY6bPKxJnrs78fSpKYCsvBkIpmD10jW/Nm01hhpmD0uM3axfPe/99ANehUH
7fpJUTnGpOTayowtnZOrndV6huw2x86n43VyZuL+FXzIcUPYKGIC33W3zZ5/zbGT9xlK1SpYxlnH
/ppFj9iNqzCviDzyau+llMtjcfT6n2bb4gi2xhl9FcFCC/+KvGdaUJbalCRsmC2nUFgVEASgt4y+
q992c+slBpmDw0taTdwawRL5BBzSYHPcW+59Vk5z3x6WPcpKOwhK9wp+yXxcID2zXmFeLpldmL0I
Y4vWB0IFu1Uo65b3V6dmSVgMHCaGvZQ6MJvS80iCf2/oDacpLNOZkqa3DFC4XV0NkQD2EHqS1Bd7
Noj7ZW4mBzeMessx5D/91heXx/RqOy7/pl+B0XfW5qN+QxiwZWFDjCF/5T8+qXxlUdetQuYt43Qt
AdGhtGnd35GYO2bFGES0k7Da0FhfXhFYvkTTKxxDOSQe+uo9iYZmrRVQdW8iYJbqjDWytxfXX0Kx
3y9tB1FTg4/oSo1meuQSvqFourhD62tW0W8CfImuVnMpmgx803NJ/ftSoVsfVaWsKjyLWxWfRl+r
/c9DfsPalq2CZJWdnxy7Co4PtLr1oeDoO6Fh9j7ij5BvsJqhp2dD2Q1Pp4jdcY7GRfx/s6qpYfjF
Qe+EpssNScsqF1DpODQxSWFlVnlkK+s/JobFp+IjSWFUKJ93ppkLcDIzymZQ1YKHLaJLD99JgfYX
RLXBjcqlicOhUntYoWbOq62SvBwrM3+r2JSKS1zfoCW7diS5rKJDairlH6b07Df6sARnHgdtyvvs
wzoA8/6IMp5M/54p1AUnVhHKh8oE9i6raHwMjr4vLijAGWPMOcBYj2eRL3nf8yEzeQu8XrFwSdnp
9soB6+nAGNVBfaYMJRgoINTHd/t80sdsnt0dnc7OfHM1iNWo/XxkeQLX1Z1xYKIz2XxkTQbfjTUE
xV+7BFWCJoboXsmxldrKomYpXCq6iDGhc4m3/x5J7mxNJkFWobhHchcGgjsed5wcsPCJtD3o/Qkf
mPnoh+6FPdiK/pHCChdbGItAyYAMzuGs9moowM0jahLcRGlgQSQbRtUc17x3Jt/JPcj59ROJM9iQ
aToEB1fFa5ALLIMO990eT5C8x/f0txA4cFc+gSDKCpOxA8DgX+Cn1tSto/VVhjpNE3vhpRdWgKDT
QCBO32bUWpGpNSZ2mALB79qTAf1gtX4oS4PW/yqjNkA7vJZ5W1Ep7LbaHT5Kd6K1KvFZ7K4zsCnD
bZB1asu0sCnXOGy4tGDNDu87/W9YKynMVtEDan1nNPZh2MnYo1+0HGnKETiQCPsk9SD0uhlPfGET
GzUd30zy2VdFsYvHIZyc/oc5ShZvVko9KdUkQ2wbUIH1VCvkk01EaWm7JrAVbpno3YzlDMAxcTFY
4iPcZJm/Q6fBXllaUXtqMfKn/cLnJTu8UPqveOFrYWbW++8K15jKnYwmwBFiM8u7V28cWF3vGiPX
JpR1mIcHPRnp7ywMrNWwxxz+LOcaLd0BDeaKUHmmd1mcr9QXopzJ9u0Is+EG6+Y+XqaElZzev470
SbvcF+pk1F9KhDjfJ09zIAdaAa18yWpo2n920VijmiK2Rntt/OXM3MA1/RLDKQWGd1E1akKmHZCQ
2f4+jnSPliZZl/6HNYXqLkaKU3oDEnHZEpIUZDWxPr4ABMHG4vDQHEM+4TRgbvC4eeIX9WdFj3V7
9JQ4FI/fTQtLGMHL3JO/PbRYkcJaCbLayzHV0XRRyrf9H1f293w6M6ssFbExIOMRmgFGwJDsURJb
FMvIjbQhgOCeKxQLnZ0+NHGpU2NmPTnPchyDzCA1H1/b+ZYRr7+gyTXbpvU7eC7ZMZJ2XRpVL012
oAMm+Ap+Oid5SwtFA7qpEsaHLlR/Wex9JmnUFKAj4Do2xCvHIm7+BXkOzQjzXNWYxFGZrU+xtA8B
cCpO4uRc56S2eDWb0JoXv0SKypg/JR99YVnETpC9ZFbb0odtnyYL9Lt+MB3YtqHFsamqAvpmUSJo
gpOupM24T7ED4SU7H5kcB4v3jLQ49hZEOTgafERRw3hazIZktU6bZqJHU8WeC4qMBJZ3OJ0S5wiJ
4sT1FewY4C+E8itTd80OUhYMa/5nUbBozYxNnBheUDfF1L/kfSUnXQstIpO9BTGF30LOPsxEoHrS
TKbn8sSq7YWKdUgNBFNFr7aBhrCkymIvB9YHF5ZDGvJ0zBLAeK5vC59vIKbjx3sO7YVubeSKs6Pv
K53T+7qkHuPULU8r6TksEIfIQwPf0P5WFf9LGqAxv+w5THHUMpAxc978FW0xJ+ATe7ey+rwWmvXi
EepaB1EwshLp45w2tYNzZoNEWKapASif/ojS2VCO8kuw1rLY1obQ9HVA6xPadqu48FBPHQ+74tuK
wOY37WuuyKxSp9ipLLYPtUem0F4B9H5QIGQoY056nz1XffujAGuqtlHOu/VU/egDi7ksi3T848K6
afVhRJVHwyROsV5zaIQgO7j7rOOJxjXj0AL7J6eTOyZQSfpg+lyY/5JL3OA3n67CyAaJPle8F2//
yXF1TMnDWGiz+LJ4/tpKAB+ep7+25zmewAzueWctvyDd81E/+vel/qf1DchiMed6N+zOnmr03lAW
/jH9UKkeDdz0B46MBKOJF3iHsGkeR9XNtMP7NsrBZx+GQSmbOKXxtRROPJZQnnh9TAgyfmvubEN2
oTdk+AYIOtJPiNDnb3/ShalJJowuygg2dCMgfPcFUWWJxYRGhfx1NK2pHz4G6MYl3FjqFI58V5Yu
P2jjlmTfiJM5gsFIMNm2fXyGp/3p/PIDACDrSqDTfza2lc6HsJyStW5rX0XjcMAazq3s0X7UGK35
njjab0JAtar2KvLn7iRtuSVpOHX5TVjSqVVZGLzTz55zM5rqgFmwRK7b1PGwxswDHKU46yj89va+
M72ncoJecdz14w9WaKoTOQSvkijxIYE9PUaSodR/URjiys7WRHYmMatapl/IrM366IouVihpw0gE
29Tqb6mKcaZDuCCkhpvjBlLz575PFUN2A/J/RwlRhTm7R/5cjoT+bZrLVuCdcr+pGea4K7U4LFEk
OW/Wd+DXpuSaOzO8zAttgjTxwnxuiY5yNn0nfCPigCczr2eG5zjBKRjapq5tKn59IX+Fy93RxHHd
niuH8uTMAyBxo3V1e6+6O4Qb3WsEiwGKM4KdCsLvMMOsLu1rQ9FUpJv/OuRdxyH8QleUiMl74kEx
Rdq//sCW5pWbKFrcNTDOzBCOEtzvwiu+ppCwDL3A5GBzzqSlS7Tj1F2nn7pYYQBFRSRVwS0c5Y2Y
xxWfniwfrPuP27l4JewCuzwmIKgAhAnVy5UOf7GTQzksgZrI4VTOXg74GzT8hUv6YYSekgJsLrdT
ADdqiVgdtysoOn0TarcxZemh60uYUE0Mz+X3d7CmPi+PV1oCpAjEgcZC//at+lTlksptnpW4w6Zl
geD1tbQWyTqm9051zQf4tqKTpqlOu9tadafn5+vmnICIty9v02HBRyOZ2uK+vIOEtGCKF78KEmhT
cX4+R2FpikbT6ELjUAR+Wr8nQbFSCirAhNWKx6lFhXLrPX58FL0/fr6iM5BG08HFIHdG1Ofy78Hr
T+khaBwOSxE1E7++jao/IfrYlC7Bj+PijA5ivaC4nBEJVvvBPcouiwTwyh3rO/fsV9BfSsN44Q89
uX8CsJA5/TF9O49W6PQ0+g0WNcC9hHYgqSnKpGF0AQzimofBQc3g0M2DS4+TUDCVQmAJxsIEc7S9
JG2YnesYAaLnR4cUUWcj2FxqFkUNCgEBJRKpjWPZmDbTDgwfRZx0H9NWUzksG4buj1ULbeP7/eCy
4QihsOnTftd6jV/1KZHhvqMKaMt2lkBqBnz9OPH8l+8i/1tscn7JjuFm0B2hlPeEln3ve8PTui0v
O1xoNfnmcvOYS1zXTEsMo946kMiP+XDahoVHYvR29Hz0lkm0dKsNqsIA7Fjh8dB3pMBQ3GPvxQht
1F5DhTR8jFQF15PXinIGZPg6VVjOOQlkA/0AzmC6RQwLvaLEB1ClayDzl3JNs3JR/I38ys2DtHas
KlTJUmJwSKpk20eOu0zG4QM1X10HoxmER4BThMGhF9XfzVetBzNpiDxcY5rypE93ly+JaMxL/YnI
er1AhHiOp+v9PL5+NZ5Irv+biqp1na/tAp+CroxH7jUiq/PkUtq8iajsIyI6x1jlE8QdLgqO21CQ
eAlW0oQd+z43dsOMBX4l9No69p0x5G74X+GtUwAX3QaWvogBeyT8qcPECATrLU66fZFTdW1mGydz
X7spXsQ9VrwMCAoEWk1eHyt/+W7lbd4+5o8o7kSI7V53f9MvWgE5essO4oaw2ODv9qrGsgM5JyVJ
54ZojqFg/b4rxWr9sxkfNeBf/LEPdG815RL/iy9yeZ+yqXxVoWyuV2WsUuFBNkiv0CDOtebdN2qC
PffE9o82SoaKCSilxjcKzfkHobBOOpulHY80AYxraMcq20BpaCpwVXcgkR99bdQcCJsQUhLY9/GW
aMAwob4oKVJ5ZQgMi5uLmP9KL2qSGZkYi/7tyPcsf7mJmDeSxp1GWzQX8E8ZjLtVsd+8Q1/NSRdl
rwypTMi0Cq4Lmu7KuI4P2BB2NHb9Rp0g171FEZwowk1IDQzj9OSqSxmuMrbwnHdMLky6q7FePkUS
+jkeOoXds+5L2mnTMSRsQEeFnCh+mAh3Gjh3JiHcUbSYHwXj9vDM7IvVH2432cDCUAeUnEMZe9BO
OVpC527TtY6WVxAgx2nIrdP5ocF4AFSFvjvGbVRXsBLie+/7wR3dpES4ekCj3PxlQzkU0SU52ega
BdPdlXwQH87nsro92CPzn7BUTmD0RhhSQIcw/ib/4XCo0LiDhBv9Yi8OmrEPgmFWPUB5agMU2fzb
RKYYoYKyXzh7WVEZF7C2R7ZV4XoPgBWa2e3DH2ShHLvFIYaEmmSB/YGkUCcYwEub9m40ly7Wfczs
GpxXHjKvx/U8wBjxvWCZ7FwSYQ/GWDYZGEbw6CJZyX+Y87fCiMdQqsXGLT7AJQufSy8XHvXlPnFA
p+9/v00bZhuRsskGcDf5NhEvaNdpQ54yUTmm8/j07XtybWTqTH13VCxgofciS+MVMx4sO1XJNMd5
Oq/bN0Fh1v2WMCRgTWBGCIGhbqMw/qv2O6UJPOUGtNk8qUCOtBxG8N6m6z14uk+qCzgQFv3zRm6U
017WWQxFl7OlKHe9iwCoRfXoyz4xpq2mWBoAzshnXfzGbBHMvDF/wh0gpcDPqB0iz3VeowRMqEHp
DxXfj17pWu/bFcH+dgWfIQMHwKfYL+6NdCSMgDBFadU0/lUm1CDzfrLa/NwNrBBpJTteKSPKi5sr
xMIK+T6OLB3+jlYBH1d5fjCY8KuUdV6PKCa0FWKOQbN1rByH4vWfFn9YI2vpqemVkNKlWxtw98t3
7YTmA++q9jiA0Y11M4BeLeI7KpVoZf6HglC7ohm3wiczIXAHPljhvVifkz/P0qE6EjTkTBtopYrf
mXeOcjkwpVSMNc3WmZViUiqDsyCdpkMZms+uJ5EqnA9Gtsg8OlyF4DgbaZhqfiffd5yx0UDRVAfv
nxGDfsP3Zdl8jLWG/4n8l/qaGZEhYhoPgFo0fYBs5Hkjp8JRO0t5WFQYdc7/YEhOvYxOCy8T2wOL
+rmoF9E3WWxuCDoIimuXfR2e3mdottzPBYpEu/lU6cqYnL+GLgj9//BFDj191Qb4EAobWzWIFMxX
WyqP1VvvhD8tBwpS07T6LnLV1W6FNjLDYFRFM/3a9c+6DcbGVgu/CaoU0V3W59W8PLgbgRP0H9H7
59xG9vn+JF6KVTemFMnaITTvfeM64HG4Kda0MQ0oItadwlwUuERJmu8nEtC4lHbxMt7h4LUQPkao
cHuVD9NJcuZ1rUWDah/RHB4cuow50hNjJOcxzcKez4u+02lmrx8cOlATOX2ulxG+R4L+EXmYP0GA
HyyCznR9Mjj137uWaYw2NwZ+MBcQuUlbIH2+ghW/NDL1CsnCF7HEwzdyTSBfKNLvouJuwSBksCy1
YQFzs+CwFBHX0+ZtkWBNRPqt/LhLLE/IFbR7L9J5Y+PaVmKrccVwlG6xp5NRMtewV0s4YL/ZTtHK
wjwCeV6zUiP7GjvU034OQwq21A7Ji+kTq8IXQFi+4OC5eE8g2wlftMLeP8MouoUjzqEcMRfxXXLE
xuvDuJedd1PYad79B+7Nf3r9wIH9BY6DAqiaV++QY4n2NVQo8Q2+E44vu5YVMolrgKSq+P1vW+17
JPjb23Dfi0czi7NPrN8JtHStk+QiQdZd0LjT6lVaSCmdI/Ag64PsANMCUvXqzuWHBv0BZkP2G1Qu
ea0eatg4Y/pudRt91Lusr2wHqLekSoIh6EXQzZWcY28O1W1PaE0FTPJ4aa1APknMcG2XrORCNHet
WnDE8a8vGidAe+fjWr/YexFGVYcyHud84wjEXZtYo3ZpGTdg5FplBM0bZqmbxOD0qqog+Df6e3LE
SH0BMCF9I+tMEO7I4rbcjw2cy8dzJuJQFDLI8Xavy+lU6FrkKRWNZjn7rwzZPkBNAsWkXK+Vo2MM
u/V30eXNhkCSnluY4kWdI9+ZAfeZyF/lJ0yVhUJJuY5z8KkD4O+w7wx4iVwLo+kJ+y9KVYkPm0sz
6/CLq+zdlqnkWPkqzuD+ZLQYs2FcRgcBbOd22ssoqOiM9E2MKxWGz8oNpXSQSeIS2RnO99COFBk3
FgwnITLdkaTpSa9R9J5gTwl5OlKDbitvZ/c3L9X5KnRj6x8BDKEtCOUzSH52dJxde7WZcBcJ4RWU
9Z9uuRaQYiDvAjYcQDFeMHtxsdaashYCp5J8HuLkXgB7GLGPKEmsXpUcn95GWavBX6d64jWQtv2O
JUfm1AdqsKL5CqGc9MSSl2mJiB6FhTkipc4NcognZup9LetL7eTaBwsFB7anGaPkQa78AgF7/HbQ
pRtl1jz3q5M5XccdiH9whn+ktL8iWXxRJmho4W+GfQkhrb0pCgjGvC3HMzGxJhPwDIe12kY3a7Zk
mO9hipTjbu8P4kmDQzvYQW+yXJKLgb9blX+SNyA3EUcEpDBzBQvtsH8NJ5RBsEfa7YZB3thUQJQg
csqAGoqHpP2rrUA8GFfNcB40v0BJauwvLrWl/96Z4LokYuAuXnfzQ2EA7pUvmVnf/bojv07qmizn
bIuSl6f4gPDJCCn2BDPJXhFJqFOjSYnWJdnvLauyqOZXMSRhfX33dTmILR6B8l8U+dVSrjDNPgG4
MxZg4hyDdYI1dxlKbAM+GCIN0nfxc0VYCBSC/c6B4/S99AqH6ECw/rHcWnKQHTe8O9KLvUz2LRfG
qLJK4tXxtknGVpqURD+Zmkic+mUwlYNwS3cxIOj0vR1B5RGELLVrwqf60f31TjCUMvRuuK5zrqr5
sQiVFkxkHZEd6IL7k1uX7PGzURaXHNJZAeO0J0iFbUrIivzZKVzOAYdr+WIB7XNF8PcyKHjuR32c
P1xIX65iIFPV+fqreLuGiUknt5rjofjjE8CN/A7yk9LUjptaRJT+Yg1VTwYfK4Ea/+oq7XtvmCTQ
Ch+Q7aw2rgMdw6rqmXwZwd1s00ro5RoE3uDn1RfTITdvEnzA0pq5G7Vi/t01sypXWtK6YuKx9hx2
YEbN0FZOITCdYyhv8epXrM081X1m5TURm46Uipe6HN0gheY9yu0Jr05CMhlSBisqqC7GuL0PaNLQ
IvMO7tfv6W7K8o6QYzK7/jy9LoC4XObLmWctsLRjBp43XRxOGkkrzQbcp1egIQtZHRZmywM7Vo0G
SqiYRP5hFjKfPO0vzN+lY12M0BQqSssj6MJAR85Jc/TtjXNpoR69NiD1JsSZosUi5iGj3lMTvw9o
NOlQIS6SdhvfJT5bebbpq1BNV1Q7pW21jky9my+vi6DXxyBfN8GBsoNeJuKy6FZFQbhyWNZSKegL
HKtEU/j8cSXEYeay7ZBBMUjr6B5Qfab+4ZawIoTbdFDJIJHF1iq+/UX6f6ubszhxRD/C8PgoFneq
ywtNsVsMAq3yuzIjVnHz7YECgy+m9RrEX0+7TtnA065G7wXCmurdOD002QuiBB2PoQJO2PnU3JnR
YYYaVfvvdGtiuJtymvW8cR5SY0BNB0UZC1ctY5YEMbCUAZNsLD/Ac4Va0iTiMA390XrINPp9PRA0
QRQ2BepR3rrbVTGmaqXMvDknGZ7pM2GVn3YNTdtcr7WMjOKv1+wOCtHdW7J1HicKNSJof3qN/YWQ
K3PzLzd+m/yNqRtz9zguRW5jhoiSzLfYFQITcED7NJAUQ9PCsQW7yAPzwUI1noeHUu5n0mWw8Io0
9jaDcg6VrtlcYMlREcGRjFJTFrucgDqwmYucwyT+CWGZp2R9rO6s9429d9IfVwTXJp+WFd7AS91o
jxWXzY5iIKjI6K292dJYoWFnmPN3duRdWa55ALezeowDBeMUk3j6B5B6pbj8L2AqIu689QYY8Z3Z
ofdaVS0NdSfXp3M2AFOcJ2Z8vq7qBWGflZYqVRC+UiAx+C5VTiapu79WXsjsPJSVzOPmpeGEGymE
okQ2azg9EaTHDqxkj/ZZwCFF1Ky2EUb0DNHOy6iTNp//5YBDgrHXWmDO1GNUQVlwf/K4xHIT6eJK
l/IiZ/Xe/cauv7n9NA1h43ZLRcRpFPjH8Y7eWncgOsQ0y6IqUdMQU+weo0nsOsV7oDd4vzf7CLrb
x1eugr1d0K2577CWnfqjA/Z890gmnrHZV8Q4gHTybwH+ux1nXq67J/QptDzg0n+m2XfCBROc7u4u
AJcm253a1ZdHD3nGV8dW2cgmw4o70t2y4yDy8MdhtstsLIVzBMJQrzRIxGykb2+sCFFcBLCpjAXH
bRfNBW6YfbfeO/W410LqEGkXtYphoB2XFPpsDw7ujy1+alnJ1gZPmessMdh5JteCLST7qXk9qpPE
WgKFuN0RIrrjpOAyZsOnLXqslB2qWBoRDiUtanoM1cHC0jEfDOBub0QN/9yVNO+x4hSC9+dvkH3X
hXlhVt3VmBfxAew5OWYwTEVaL3XCbuvp0wf0qTiK+j4FV7TBwxh74Lwfr80R9Dy1DDZ3ZnLX7OKN
G0Dw/f57NgWVcW03pDzQL9x+BUbEwIep3ANwzdROXWQcLZNGI/u/RDbA+qYqbl6CITAEqoESv35b
SCb/fp9dSp6H3oWYkcoX7X0EM/4lcRD+FF6902xyEDkQ3hdSpf5jHF+okafmXtOwdEcQrZY2nUIt
kLFTlriZ8axCnPj9lnoX0quERFQ4rmZMuBQyn/XZi+hhiblmeNz6pf60dPdzSYNqpuMHz2O4T0XO
Xd9gUrmyGndNKePb9jTY4yHnkyyegIplJeibFvFcMfCe2fuy4dK3+VjvH0C9PeHWUZGOn7noGT7L
8Cbegb0cv1PpV2E/yQNe1KpiY1IQZCu/nIv3uRpdNi0dlTIDs9Y3bya4xOeWhZQKwFJ3pAs01BRT
tlfgOyRkI6u7Vwrm2w/mEmOBli1HY3BDE5Hoyr2mr0GCxoBYVMLJZskeP4N3wER+jbIxHnu/A/dG
V3/iVT9shoKQzD77FqqGKuKxKAQjytefetnfPFZ6uZ2l/bWTU2mdCUGAlBLO2RKCjLHZthJjDuK1
LRO2AfxsCI57idVVcZIO8ESjFd77xQLkF6SGxvctCShdOTx8x++Ks4WFzJiMZaSTKl3MoSu4oFpq
4yWXpxCdTr7njznr96YNPLMnh85ENDod5Umc2dZHQdN6uHl2ygkxQQbvQ32AwL8WgcNRlIHfmwoI
TT8r0iYOIA/7baedkWVD6zeFBSqmxwcIqV4XgoidAR7LQs2jWKqJkqKKrPaey87DTyAOYVZFof/R
iiUUuFZWugr4d4MxxQAFrfbHzsqIGCJzhMSx1tLw5qqYWc6RFU5Oj0T7mxqztoDyNzah2eycBjam
LRog5XmaEL4doJDEiuboxnV85qElBk7yXMWLna4unRIAb+B9GrwZAMw0r27DdKjkb30RgMWPYyES
7mR/aaPKkrS356tD186vUPsBaM8kAHuV5vu10jBNCqi2drGjHjqNb4QsMsSXFJ4G1ziiKrQ6XTqT
XbisxDzNGxbM1KEjANG87/PLzHM2WCX5tzLwLX5CYj5Hv905an+K27tMzHj20xbe2ZmuJyobjjco
QbV0nJF/boxcJV8S3d+g8lS+ZhNBVp/szLMVfcoFyI3pUvstUiHJqZhmQfaSMZZgDAMreMa+2fkh
wj+Bv+xIg3RxeNIDX1z0SOYMdY35p9V4B4l7giji5RC9JmLvIHCzpDDL9T+Rak21uxeqE+f1Tuez
L6qmg451FDGGjbDiO4Xw19wWpJhL5Ngb0OVUIZcXpRWoZSvPzy5M/N+mBD7hednKcUee4ccim03U
0t2/Sp3DhFxkUf19m8PgjG48ScmNUBYCtnGVjP+QSVd/l6z9MLy6rDuIgJqu8lBjOu8FXnfvviHb
bvQVC4On3v6r9dz+SAymle622X5n4ZVfJKJz3tZnqdxyv68kck2PAf3cqLtfILzPd2u3ifvtn5Mj
DfTDeEeoG5OUBWD3ipre8R7Ekh5Ipn/IkuTcCzeNftm8iZfi/we+H+VC+PJdUc/tVPM9oxeDf5ph
zze8ZKuz0LXFJhqU5F/4CxH3i6q7mm61JjjUGb10RgQ2eJweaxR81eARI7OUwNJhqKHnk2g0lLlW
2i2ggKUi5MNbPSBX2PpaBveHXgX1sFXlKQqS6bfaWoa5SVADwAoFLrrmaVlzKvYhIcNPsCKKxJ/a
AqAtqS2IW8TPHnWJq9DF15N2EFGcaSJS83crcG0yQrsBe/sb9PxMv3WMH7TXgak77HxBoXP/QN3r
1u6c/tLSbp8JgmHfSSrRxeAgVLUh6SJy8mUqjbb/FZXLY/laoSYOCEvV9ZaOrk7QFsY8dqQJ7I5K
hB7HRrQYpgD3zcvcFiugtLP6p1EER5fJXWb3hPBFH56hKP0cD8GO3/TKgW31KLkyGByrN4Eae5F5
xUhQrKRN/RiwmwJzcG/rOjtci8aUH8JbR6fhxs3/EB7ndoJmC4odaG/43KNXIunlSYqgFIFrj8UL
jhacJwpk+VP2WA7/3ym703OXA7b1XmKdoSie7sX92LUhrgGGHk9Qeu7vn1tiBYCfK2Mt5WWnRCnn
+TPEN0RB/kSWgLPwz+5/rrLdNIcNQvb1GsGYnZv13j77u3jozl54S7yOX5cYZ/dJLhvasBb4LnIt
S7qObJR5xuXgRe6vCNGFlt3lqeoBoft+6EUCVFbBpeWm0qtZioS6l7KDmO3sPtMqZrWPPXp0xkSB
6RdXc81lfkMPciwxLgTFOez1Rbk3n3xUz8fAZGTaac76Ty3qqJVo37fwdGORDxQcyfLrCq4Nd6CP
8eALqcd1aSeJneV8uz06IcM35b0uFSL+WeQhTl5kdZAidKEcWtqkLa7dAcn/kDiG1kCcGmvGHfXa
qn1irjO9qhyO4CFY9s0nhe6/ksILBE6Z1quldWkTOG5DEdSyGFwVbM9GrFPgDgCUNezQiEhSHtYE
LiexJy9/HcUjg0YnUBsFgi0C+SKKzNT+o05GL2vJTD2tcuBlsYNddciBtr3aEHu+AYc6cZb8QTER
q9F7WXcZxWkR7AlktPochgdBrRUw9ZVfhdZHooGufJIbmNsRoXJ/32D9crK9dV8WYtry8PQ9amwL
NbEiYqd364+SCg6UqvHVw4u+QULqXq5jBERGKHcypm7czYPSL79KAzFdgVJFKJPCYvys4jHkbvQ0
7/KKvTwYY4nDkj+oDpsd7jhtA+Y4/bHcWf3CtXlvc9Hmm9OyOUv/6q8Noo+wPUxp3wjKA+xYiasT
fvepHfhPXUjFCDc2OYV/XA7CJnaoDag2POozp9ieok2OV0io2+j4WlYzMRT3YP7TrcUhv/4d818g
qkoO+VK7R4AWi1KTGpXsxAGK5Mk7D78d5hutfgGANT/WLYbShz2C4iy/LnJQPrhQxn9ovXkkwNCI
Glh9J0RZcV8o5e61W4xA79q03Zyw62LElDj/w67F22WeFbezMFrIT5JfKZsZd3DtIyrrslINdkoT
RV6hjgKROquC1vdpL1ZvvDiXbwQGWWjhYCWl3AoISvV72vxOyViceZW9p9eA4Fahu+p3rovuxPvl
SJ0LX0tOduZXw4r50nw4GsWijnpvVOtagdK19x0EEOxo1Lm0v84Qfgp+bamVmL2WGuc8MQ9Od3fa
yRWl/eZBLLqbsPT+BegFmyST6uDZNlkXpKCKL5SgOUKGD8g7Rz6so7i3djobhGWSlLkF9IdfQvfM
TlRsgF9GNvm622P7oafqzVkmSnGnc5OlQRWCPuyvhznoVvXrBU4FNliyB9WkAsQBTOWOxzgtH+jk
Kwlh+6ZYkDDQxuScWaX+cwQY+Tie55ati38u92QDnjhbt1WRfrla+Nl1SHn6m8MpUdqZ+zBL5A4v
e6WfvQcGpo1hFsiue0bwaRM69/8JnAg2pJPgQLuTklwmVXEuLf3p2ZgeNTrmAK/varOnuqkSg1k5
nfjKmUBaJBhFqHH0m4jrX0HFqiQFt8d9vcDFTM8plQeIY2u+S3UHIIeXhTH4xmvWWTo86zPJYY9F
VSb83LM1DDQUZH2G7Ei4bBRJr31tszLdzBX0aVMkdoyPIDoF1Ti36hxbij1O4z/femuvtjYMRXcT
F8XWzmraun5bau0YDtTolverTX1I9QXp7rX7wIl9A/ukg+6nJyGZAf8lMx8ygha4CO+SvP9U071J
ffE3Qdw60RgMINeYAegmAX8X3Eq19fs1r4/LJwa+RFCXRIw5teuDXIhenoFULdSKli4BT0DuPmiA
zVqI5D1+MboPitJQp2aWbpN25+gDGAULsDc786te4qw0+NcSUnqAqX9X7K7r7iSMtOPigPB3xXSi
LoPnagE6C770mM0okHieTZEA5OorsKU0+dhgPQXr31cc/yorByhjaTWmEFwLqY8g3Qug9LksD9+Z
2eEUkwjrR7q03nqpURquplM84th+7LdL1ac3PstmG230MNvWoCVXWu2Ttt/sKtzuk71KDFKH/Qtu
W13L3RO5O8Zd9AKsGGQsRJS6QebFhMb6qry1v9XWKaWfAQhC1D0A1TWWcnNaM/yQXf1TNxmzJm5U
ow/RvCduLwPt/Ax3RxDgGnIzBgr9CKVFjY2m9nJOFWZBtRrPAWtly3coyMcAM5uCbD9wn7DwDjbL
Byxg7J+yzg4qGP5Xs9Q/bpf4NvfoGZWgIPUbGm7Jo4JUvgmlDO89fZMR98Iznb4UIJNlcBkWZbCm
asmRTq3OFKMWzrZof8FYYI/IpzN3gTkJXkTVlWysbCNIoGMYCjDQs/AdmaF815MTOdnMvmXbh+Fc
ETXS5M0PSLdvkESbUpBP4FTMVZ0Y+fT8qpMDpxw9/Bjglxucl9IoTjezNfaYnvw8EJpERHem/ZNI
BXJybuy+BOmZS6Bue8kU7McvHm2BVed4IVhJreY1yawpggPmLj2X6RhXpC58fFRM7L4iN6LYkHFG
NNlFq2oGqiW7hp9JeD6i2BWwbJHAGPs348z5yn3wTxCqdcuGc/WzBINAs6VYY8qzZVdKQmfj5QM/
MnAwofN+QLWLlKbTYXmSdUW68AUp4lDnQFpgMpGPjKhM0B+YVzhNWhD54ByAssV3KU6eV8xaAk0G
8hzTmTEqiHjhSZIQBfez2hWop/aAhqWNLXqCLolQCQiP2hFJEcHeYwaS8coqQtJA5XQISimlBoWE
PMTeiogxyLM4OrZLz2WWyxQPr0ASEgBApawrlXmqo4RjkOqZO6kUYI84PCyqoxZz8xgAGkJ8mC6d
mITN96leA3ZLUz1ZivhAaAQu6wIvKav1k8fvVLAb2LC+5ZPqzZ3F+W3+n5at4iacUj+rImeRX9ky
4kHCWQnrBTuUL6kPCUPwbCGu1ZAlGPWE4lA8q7Lqb+d2+YNP/d/tZX4EhKOGXnZ/YbQITo5ehLU0
Ogu9PQK+gaNzABJ4tzWyzskESKfcb7pAenjAT3jMqJ3FQKm3lGdnsIPsyOwvBPmlG/k8orjGxRGo
Y1hQnS7RUz4wU3g5edgWBxXpJz+IMQZf5sMAJHSKHMZcPNhH57l3vO162ZURVJjzuBMjZ/AAl4U5
nEBa/6vh0C5f5a2o/1ZoTHk2gv2Izr4WyrRKUHIO76/C4H63JIrJiWHv+/K/lKXk+2Y0snXyeAYj
NqGa9Zo3goEbnf71kIvIsWTHW6mYxFD5qhzXXEMY6pPo3+QrMC5M0XQ+44O2v0C60RNhLCKib+qP
teFLxSdGXdtGWsBjlppRYKBriEBA2DjXamxVMFmtlG8hXQ+O3xirfZavSO/I21Kj0UyL/WaAFfW/
IUp4wk8J97pZLq9gvk0BjeOqCpXEhoMaco3L59ViwAjahDbTQOPSvWxQhaLQ14qXv0cVxuwf3aJM
6YvKpRL7xEeJMIyiiEh0AjUVk+ZfEeOTFXRmzPAv+l5m/hz0DFYAyh994gxzVeRqv/2y/SUobsB+
JYYyZaNviBTdvxw45TMs1tmADAQFulU3GIOW3XahXH/G6HlLlq9xSBAXUIj0O78F6nt9X88pr45o
75g1aqDooeplNaUHMwzcS05WxMHt/ohYXuyvHRqZhynnFgSBv5W06qBJqt2o03JTh5HAxPNOUS0M
t4WliZ7z1rSnQ7m88yG3nc/BdGEQR2Wo8219Tn/B4HEQWm74PChGCVNjpIT+ACUxgHf2W2MRcs4s
BcWhgNtAPcvqSHMeo8NE4n46Jy1sg3LxU5bJPb7w70Y5RzZ0EEV/tyUw2NIlGYZ5cKFwt3HVJycq
Jw7jt3kP3E5nxtqb43uYz/5mSxZInBBTIa8rhLgCAognLSnQSl+vC8uiDDh/gMDOldbbsCTrU1EY
y6E8MciYYgVaHFUjx7z1whjA0tBfQ+kRzbZwp4QfgDAHTQ/6KEg99ryM3lWqzRS+2Rmx8Zyse+9S
mY0Zz4vKpFGRm9X8kpFmjdvc+dTzr6CX6LsRmH1E6JawqDpbgIW7FG/u1qbr+V4HhtziOWVXw8vM
0f7b1hJnlEDSThrVDZiMbl9+tmY+XO0djeczofhHvTnLUUV+D2gfk7B8OoCFF2WOFTcUERmL080g
1eMs5FphXnDhoFRfYtAfxMPybnCm+GC09HMP8yoYeVTeyim69Jz7bGzwvhiRXaeJhdkPKJMQbgQN
6VdEQzcokO2jJ+XljpLe3H1ilAf2hU8dRaK7Fm3oj2TD6HCoQsvX2ahmR/2OalXSDNWjm9Sk2rn3
iJmu6KPEkvsn+uTdA3TkBnU9zjXXZnHZpebNMZMCSSk9uYd9IhxS+mGWSmDM3GCysE/GGgqFr4aY
wx9yv4ajCHERFojAlh4kiH9jFGSF5O3bEvwHvwny9yHOp1WiIgzwPg0bs/F4Fxw5Q9kj33WPmP+X
yq87ObIAEEgql6s2+hXVf7LTfMFgilqDKMjPil2jMs5rl4eSuP9mMRDV+BASz2cc82EtmnyzLOUG
1yfysW2M5EeF2gDOf8+3v4LhKhrHCDGZlvBLY/kaB8nWB68/Im5y7lK3UDafleHmsdNHuqj2tLhy
NR/pJ4NPMFkrFkrsxQWHBIyI5s/HqyFu2LfzqpgU5uwi3M/2kU0QLxQb/Jl6bHxKoD2zY0Ktlm9T
rKiuAK1izkUYH8D4b0GaSLJn6UbmCdXNb/lTeUYNfnjVr23dBBoz1ZYA+ebhHn3zaLCWHwzHezw1
Vl2/PewA70oFBLv49Puyf5A7cWasP0YFKFx98VlSaF4VcyVsahRh5dwqvt/djXq8vo5vg4I1DIB4
RIJyV0SQuKpqfu3EcYqQUcImt6Gvci9bP/FN0h/9HxAm0jNAtTKhx3Rsy3lHep2LcE1ecZn6ythE
URYdSWULA2Zn2LFytejdTokGiILfiQlJj/5PoUzD3D4okJmL3ku9Z1PZUwh7lyvY44IAUYjkDs01
FCIJsw2jEWvNseW2QvTrH0bMp8lSu4Hc5oFEEx0OcNaFFTFQjeUTzlsJJmlXUYkA83qVi3FEqpjo
NE7kOH9l3+oNoihe7EUykE91LcqHq7zoKdayUZnGNn8sxLjPDObACihFH4NNfrHQ8PqPKVTwOhXv
1Pw+uZvhYhek+QnKt3sa492iqeJg9h7nXJEsiAxMgzMd72IIoB9sOzBJr4Evgv8Gkg/DaGuiXYtl
ow4mmjFKKiYtgFWFkgkohhLxY6ZYOS1l4YguzAKfX2ngYidKEzY7fqLfI0G7YmgsX9R1LGUt6dxn
KTZP8bgV/mo5RAIoLxrNTVif7N6HhM3TplL0GXz7xvT2+WnwETz4wDCqcX+h4jsFk1WXRzF8j3gv
vAjBrEru3r5wVlETWeP3CUOGxmealEg0WMq7k2mtaUKhs3rr/1Vw02pesY4zbI9RuwcR8+rT9po+
RXYYL6AhMHxaRs2/ypQHd28tqLqNtyNSWm0rMBJxvWGvz2Rll0PlbgovxQ+FXxkhG7C7afChRYPU
1X/D3WeSR8myHzMGpyp2fu77qefl84jYxveOuJkX4uXQJApgX/pt7YqwnS/OPL8H0R6mbdRCwQtD
NQ10hRxOjuW7ZrWIXVQOMrDXS41GQAx19Bk6HTg3Za+HomJy0VUdWLRbD6dBAPhtVIBvgdQEGwoP
B/dmvpOPW+302WPLgKPEt6VFVHXDEFB9ysKr1u2J8w7TMzZzX2QprJczTHVFjeNKPxWr8rQSEB+d
y2vEYDMD6V6jaz2DHC8XLDqKOWjZOi8lywFK4Q3NENKEf1h8WBfJ+U6/9Fyo7HbRE5hRwPRyjulw
wCl7bs8H7NUXgjeAjFx+uc/D+KSqHXovAVlemXlVtCkJ/9fqhgHoyjUfA7T20RomzaTxP5x6iE6z
PleTecrIfWyk/DatK4TgJiVN4dp1DQYAuUk6jXSQcYNyZGfh31wuaLhwaU9n4txM0Paz6bpQAX/G
3wKuqibsKnJJi+CUJ2Idc//2N9sTUxAojsE/I9FgR7Tggyuox/TJrDzd4lyRb3K8kGIN3XqCZ3ph
B9dmIhR3ZiwbFy4MDR4/If5n6/9f9Zs+OCMaBJbL7w9lvU5dUV2uuahboEeShcanQzTpokBndB/4
4AZOerk4ZxiXM62YH5k9NRGt16tXMpNTli7QD20w7/xmY164qrmYktmzdTfIi8vG7Xd5ELVLyHaz
G7CGrllzN3SAARWxewBJT06iVxu9/WZ6yROpOuyAllWZwav1J/MgVcMx/O6LNV75ulgzTlytRHKx
jwhsAdZWpTsWRPpQRRfh0aswvAo4WecQsBilRxWLvwohXzILpp8kH4SXTJ0ZO27SxxFC0CT7guLD
uf/HzUE353GAvaRJpOulCxaWCWnWh22lrllunCqUzI/4M8pkNO67lSgqaZxfhQc88U6brozHv9xW
mmjhievqdVrR4YqTj9xPMATuxCPqQ1MOGw3EZmjO68IdCRZFGTVzEEEJa9SwH2QEzY6QPLpXv51g
1H/kw2M0O/99j7mIYK/H+G2RFshAtercaOnNKo8kU9oQk6d8V3VjBXbEYOzFO5d/hH1xpgwDsGcg
4OFa/tpzudXYAFNWEtlMnXYCrbmEir66UGLn1vrypeMJjaE9ZTfz49jOkso3oLc0kQsU8AVXOaRf
rp3n4W9FLPnL2+de/HYxZQqZZZ5da3NGf8xLp64lNUKykAj1Jh2z4glVrzJmcubSReq8vtYH966F
ouXBAZfNH7TL4lSvrDo9Jl6uePLb2k+TVhSbfOnnwsvPJ4hn1Hcz80LtUFZun9QkHeFigMfjMHGL
48RQ3tSN4nqUGcZiifE8gU1AK48aqleUi3G5CtvsFsS4HYiVRib/bKqxAwz0748UAGuvbeoqYv6x
rNjwxn28qaKzdGBmjlEp52kJg3sB0NsJPKuNf3doR33DpCKbs4bzasIT65sJQ8VetRLG3fatRY3v
gqR+Ir+pRfpNO6u69Du/QUbzsDK6/ojn5zKoNTag9Wr9uU77dUEZbyh4jwPgdLX9D5JcpxDzD7QA
QgLBcWMTsLQM4/6J6yA3U+jAEv27oeyt9QnSRB4DYx/azO8cSH2KNOIc4ygp4deDiFYuaTlkgxZB
FesVy+jIx7NUdzg1EBJNu89puuOkTBLwI2YKb+wja1z2zJ2gv/nJtG+jvQBTkxSMS2QLJ70mk+0F
jqKbHPZZLeWcVBWS3rBrR07xPqmYqyUZepaFdZsdUW+S+FUG7Pk7ANdC4D4KfbHHJkBgzi95iQ9h
L3JV8Ay12taEuWPVL2ui2WGn7D6qj5CBcT/rg3n3pkC/Qj3QgRMUf0isWwmQtKDP7PZ0Tt6DRLvf
fvS/PpuZ/NFgdfmLdlZhHV05uCMpxzwEtzgPD3afR/xa/tyMnaDQ5UZJzD0nujKNLpBDInwM5oJ6
vBH8xaI/GIbTTjGPjX4IttFrb54oVjr2XncVE49i2l1X3CCVtcFMQdFaz7ht0BC+Cn4CYUa+eo53
vDG1d57Dpya5PWslnpt0IydBf6qm65qS2Nmku7VqiJtkNVGk65aCseHMeEktFR96sKQR8WTRzWUe
d1QOFhnlado/cpUN7hBjblxcTM+XyQ3nUQrgYC6ima66ajqe+M+SlDQlBu2zodLJZh8Rh9+w7GTk
j7ec/PJxNlQS83Z8HkZgalUKU1SghFQB/l+AGoKWoiQx239U3DqYzadDqXKGUTMK+S68XFfLZzD5
Sv05IiptZORJzytAHhUY5td5O3QUljxjbLZdafCaFUlqN8/doZwK+sdbsKiYs+C98aBdRoXE1Z4Z
Sac/XeiiSW3xfNEZEVZKJgdjOeESgAnFQu31sgu0o1MdRxKAl1gHjFW8WTZVpiwEbHgLlegAIUlo
thf3OILjZqSqvbnzsntYvRIl5uG8Qd9sZyJhNomGZ9NrgssHhNof7bwj/3Xt0q98eoz1TpGY/tkG
x+1dleFof1NYAnvpstAr0tzdyk+YT3OGZoB1FSo0p0gVFmFil8bd82Ouv1xqKyLBSrWma4mrG6EU
nLcnoeyLRRdSAG+yqQXqyer1VDQB2C9JIQXCvSuqI4z4K7RAutCjKn1pgQKXUSEfkdRprG0XOhYS
920UicJIi4XB28P0Xt8s8+Mu08vGXz4ejtIbnuhXBKkxvjKMUib3Omm5ALKP0RJgRSfpf/zj1utV
Sx8iSwurlvK8ZKMhfkNCELecSFu3PWpe7JAQlyMKdXO7hOYfYXMH/uyXr5L8rJU3JZnR6vpfydJ5
z1WTADdtSBQV4WSch95apgpKPeCW//gb2RYbZ+la7ccKPclKISoiBhCV5DCp/UUClWumdf1CK+Kj
ruglGH8zD4TILPO5r4+WGF9EQA4Hbvh2Jkz1B5YCCr6/HCD1Id/pwVBwoUcU9ndZsjdNlWGHsUiS
uzQtXyowgks7lnYPmYWRad9b08d8U3eVs29icpzACSjz5KXy0noNDs9jU414y+KcSJNxZy1xEQ9b
YW7ZRQXjwlm3LWQydDfHXFd5s7LfzvISAPG9tffghCtkkZyqByxiASICB74TlEw5Dw5tNsmHAsy4
jfMnlOQbajXJN8zbaNBDSLVoU8/sgfTZhBmwXs4omNtAReXcY7zRchDDGAfqITGeUNshnpceMrwW
EK+EiPjMVJVyF+c4aBXHPUerI8dQNi07zkf40geMSbFUmbyedrmAUpDSQuf6RslkZpeY4HWDOm94
g3vQsgaqjNVOVIcLX6Bso63mHXd5KSLelIpUg2WmVb57vNZwRlB+e/bH7mAFOEv5iAWwxMGrtVsk
8zXZb5/NhIImCeH9Ny3FGQUncEfC8krQqWM0tJuyGg2AVCSh4spu8t3HlsO7JNAZ7UgUtMXsxAD+
QXF7zrkEnMhM/MXlmcBVLAeNDYZLewAp2I/t04TPKVHK5hgtSJxm85trqJ2SAHWTnNnXy2uGC0pv
soT/PYkMLOw/c4ri0p3zmQYaekPPHkB6PmvyYXvTOl0BaPbUPvaHwNyPNvFOyZYFYe5gDs0chr9V
SH+LRFdykhSkiJHlX3tR6rgfzC2reWwhpcAgSFcpX2AwU7mIGzAaONFTOyupp2iuFCVALZoXl2HP
dmSLe605TNUaAdBAqaWoRwv4e7RVlebbNP2F29qKCRAqJPwS82q0fNB8A1abxDtB0GfywhkyOdnK
B0bR/fD64+6qiSrxTO21lWmSldu+QEz2NEgtBoNnFxxZSnYQ+xOjpqSnFkfEK8CbNxoQZKFMTzbE
uy7h/eTG4fAAg7vadtXp8OJQVKmQblpZMna4cefnRHhoONX+AjqoYrcq7YJgqigZ+/Dh4z2xQLDS
/gJ/8XzETMukGDzCT3QsEW7oGeLKTiWWfZNJeWA6X39r9t0UsD8NR7eG3RjlrWHrYTcou3PO83Ul
b50JOj1RRWgRLpruQIdYLsb4KdCpEwq0RYTwjoEXezpWD+ySoSBVo6/9SjAIahMLPb9Tcouukgnz
mIAdtuRBYpmlsDRjtnRdSfeqlykiWhTSzYJFDUvNt402gXlFxBEzhwycR/ZiaDd7Lmu1/HMqnlgd
1xNEmmcBTaS3t9k0T1pgJuif/8aBmz9vRF6lgmc69vBbmYNlfUb8//PXE6FhY7S/t3Dgw4FuFvfk
SOn1cTlXw3wa0B19NlI734peWqmv7ZvOzikuslmuyd7psqUj6vmrqR7YcznAnRi0rwMX/A9vLqOL
uuYm/bZdbeqJ6gZGGkkUPaVVgRslis5kVfyR+FmzbN8u/Qao3Z5YY6rH6zaIm54Bj2kX3fRu7y+R
ZzqXtHeT3TXkL6V6R55WD0UD0obVL8UJiOtwuEkSAQp6EjjbCYARUW8N4udU7DowSQx2NJFDYO0e
mMftjxPfOTpAfuSMdfc1GNr+Ex60dfyaYJ2+2kI2zOJHmVHrxTKJY5ELd6Yk7SmnAIOvv1Z6/Ccp
SxaoP0LqWEP/8Oa0Qe08oyBk3w8cWHBa3dG8PB2JDnwkxIAko0sWARIw5BC8L8yTposE91z5vXyi
CbCEYHRdaB7G835eW/pumfz4Ry44wjx6ov2n7tyTBPsz8OzfySvWh7YQfATb5036+sbhxSbuRm2O
qbhUvd6mpDB4yM4t1fF/y8LCYEZy6P7QQXwW8JbT9e3l7TlKe+tFXU+AFO+UFOobATqzXFIOoZ60
qhlUBJ1kb52iKuhPwIGxMv/S4LScMqYyyExs8joi2SfBFHix1+5agrfTUqxmSxe/n83m31zbjMmA
V9spGFVmxXWyc1OF2CVcOTmRlYm9H6KB3CcacKpszLKM2qvul8M5hPfnj/anyWwWvozjFlnMvJL/
4RU0D41NNyL/ulPuK5L3obI/ot9GooPsfaQ9CKrN0xZHp+c4h07ARQxvJur36iZVn40RYxbdrZvQ
ij4S07wi+5UlMkG693DcmmajMI954uGIHYq3Lhm2y/SI+LlEL0xfTXoLyvhSy84H7hgMioxzm4mW
BrR7DhT42cNrU3NvuEVLQ+LuGpkPJFkwsHJvYNKpX4g7X20qeYqwEw+Me1zB918lKp00S3sXGK1a
r9xLXtVfquEsZ6x5xIoBDEm6nncI9Tp2TlzhPpbrt5kKZjTuTegLvqGgloDVK86fbcR+JkKl5AP0
e3jgJH1nbofeYmPb/b6hATHE+atppIf5ao/eXdTFl8o7ZPaFMB37IhIdak609Flegmgz8fJ2bbFM
pBQMFwImWWveifD9pnTEGsUm+oDpOt7+XVbUbla1jlST8BOSBtHffIEJTnLdt9tx7ulzIku/8UAL
T8TxGgjWaT6tZBzMcRDSa/cNG4UxWNnw9Z7YN9GOhO8a9rOjRZXFTca8vOGRDIn/UmPGYUSaWPzg
LFyEwdRNVnGkN5tQSzXVsBg1uax4umZ5qytHrpI1OQTjZESLOCNUkr8qd0nu6ErgIYE0Z/G0LB6+
NYBcinK1Z91fcMIdFdMYrdjNI93Pc0PuzjKQSoxkVEny0cg2KtPQmN+ZfIkE+YCOLQwG4rle5aFX
abxOhgCzTAtC4yt1nSt+8qkIsxlxayeyI8QNqmcCR88UinpVz7phPonyd2TjRzKb+cCDHnSHYM8J
tRDv9JYy9ePuR52bPZ/7PP7ElpM9lg5kA+tXe8aABGBhxQcT90gwHNswCZXFiOP89q6cYRmq/ZoN
AbHwLGxS554mtCUiUnDcK3KKW15PSwEOHYaGgxZfajgbTrJa48hGZ1oo7lI+nyVgJKIX4wA1wvkd
5gywogoh/ihqe91jRdaMHTyUrMgO+Cz1mu+knsWRsMTZ8RPhsS8FGEnPnCuXspOIbZgrAAxRIW+F
idyd8HkjryOGJaWie8L+s0dz1QWGp1tbTG1v26RAE2lO+GmZihf4tYQZfpUGM8/IVdSX7sqB7Xc1
oOqWuujjaN1baZq5984azUxIx9jMGQhbHF6F6G93u9Y7mZREz5h8Rm51spuJr8xNK9f411JudHUs
qpYIDytsEdsbgiIt7a00tkNlX9X6C9/vOFd1v9R2o5K5JjmevktjPM7iaYjZSnmRJA6XlWz4vca2
aUurxKPLECmAaJv5Rci+Y9vOIObgnySZhb7IyojdjqgenoyS4o6s4I0fL+W5vM7PgHybhxUa/tEx
649O0a/9ukZ9kt/Mswr2XT1jQEaemzaz/Vu7xC1dso0LOBEZJ9cDvbkmttpU3ZYI7rdVT8evbAXZ
jEknoZvE6A1gAg5JOq0VsiPtOJANqjCkAoBK4Zd7tWocfedPk/03XxMHsLL2FW192D73bSOJjhDk
Wldna0cHkmatqgYXFYqe+IEqSGa2JE7nqAjCRN9AqNYAYIiOu1aJiBq8cAwT+6HELs0Yg26N6EcE
eSMEifyusJljio+1TIks88DnawaciqpNBx2L6iv96j/rTp5DTvQxX5Lh6nk7eSVeWc4KHPQm2mBF
Nm49vF7kbUkiO1YORAlf36PefsOta3VHSk30HbwjWNXbzU3VSKXOaFCfnKWbl3yoFtJWbJAJWUG1
0GqbhRkCsCI0YkWaTH73atcVrYqYsd0qAkMqbc62kEGzYB1VJNBQ/guPh8J8vf4HY6zxVrxP0vFN
4AhrACpj0vPXMSd0e05j9fCVblog04GbHxBlc7MM0BKYWL7kh3fDCmNwMNQZM1mgpTW+uoTl/vAu
w05oY7I/e0z4mN8JhTJtIXTMqGyTvs4YKZNKksUh+Xdq0RDh6XsG7MCtT+1dNNgJdi3Lu+Ygf0JS
HBk/cx2sjN8iZpcZR/Xm8EdDQVEpRBPHm+bmHx3ddifbeB2yJReGs5ISAJUI5O2ZYGYKiokpol5r
zdHOIoq+TOUkLVEzBXeO3OIVdWS+3lz8tFm+beY9ezuCaO4+Ct0QiMfHybwnMiR182uv+aA2AycG
5W2tuNLkaV8a4nTCP9LszNUCw5TOaa1NfBQMLerqOjH3rOZGSnOOpR9mAE66jMIyceBpedc18P7h
tuXfKOWR1Z6tOE2eXMwH1SKBWCCLEa45LplJ2R2O1WRRi7Z4N4/xKLJbBWpG2lYAKHuuqPijNUMV
XA3ts5kzeYrySbq3m3/5VcB+tK7ZEtG1Zr8isv/eew61YdzGXE3IhKGsJMEf+aTKpXfb4G0DIVTn
k0NQR653uhgdFUoJMMsZuMkafVwfqBNEpwwPedSV6Rpj7WnjkhC6P5We7ib7C/CFo151HALBTj1p
hhDg5a1jEzdICU6v9GBdCDpTlM790rMEKzJIBWDv85llQDggTevOsROAQmfGC4ABH6TU2fVO6+sy
aj46W4zG1cbOIjZWoQHxRp6sqllyqkCqbYiBkjCskWeAl+ApIN42dyP5JiNQSWANyzPv2rrPaq9n
HE0v3n5Y4W0i+Vk8eBukOguqnkb5lkQMWUDg4EEgUjDYPIwoJa60w8uq4i5E/lqhMm2+aYCmca+s
p6MTAQdOQmBzU4oHj9+hdF8r4dNb0NR8gukaDgTO3bG5/2MfcY8vicPPMhA8Lbxiu/A9bH731Rvi
MygBLzeu9A39F+SSrxPVK+suWh5fyKAKbqWN0rxuKDULy/tO79RCjUHBqzlttbAD4+pgISygpFLx
EYd85cYrApg3vFuegn0E2Fp1N6UwKHA10+i/ENS2FqGgVT6rQhcTFAx5tSpntmHP33x4KIH61dfQ
UNjSN1VIncKhc/6uLVPzqvVKzJYuKMAhv+YXS2vNA9YddITgbzbWw783bR4FE/hNEpG/i5tANbIk
yg5qiacIfFsRNcb1kBnyJD9DW2NC4saO/K7sGLRJOKadmMWtUaFW00i6YBDg/4FWbzEQ20W8W0uo
ol7lGbnVRe71pZqBw3UrILBTHKgAxkVXeL4m16tUVA39kQ4G0wVNPVDBq62f9z5AZ9YDb4dXPJtW
1qrvl1nsrYjGz92QVNnuqsjCKqgC4dD2/Z1SL57vXYWuPYQ7rBzFXjdplEucFkYwTPUg36Swe6nG
KBp02Ch2pOj5q46nSQxqA6tMuVOd+Yq3U/KaR8UqN/irKEkn1px1XvDPYVxq3m2n0QaTfDPchkLI
BcNh8cQiAe7Nyl1PMEoRToIQ5Cf0eJfQ6vEpTIlnG91gahMri+Na6EvYWGHPvKfmBPcDI/dZZFBg
2amkrUf26SOAuxTp3sLs75HgZsEPwOGKnHwDyIV30+iwR8EOYLNob6MsF0LJnSDyU+l5PG+Alvj+
ccI7W3VATGRP3A0eSpa8UnBksvlcF1xdJKsLHrcjWlzC7RrkHiqH6nku4+fv3nELXz3zNvT6sB7l
1Dnfg2uHcIz6VWpZ0xG1zcFM+vwRkdZmYCYUqUhJCzNpLeHwf65nfSFJj/f0ucoJt8fY/gQ4yNqM
2y22KyY4va+6wldPidNsuucclcbv3l6cEeLFcT+hyxPCjKcityahJp5Fh/dCcLXZGqXfQseeDxeH
KE00e0rS/rdrKE4oNWo2PvhC5kJEFh+e/Adf1APIuwz1wha3rDRwxeRDIGx9zMDv38WN16gPzL+1
+2eYCFPIHsfQkHvg3E2ufnf20PriRS5LtbKpwxXoXbTb3eYyzsE3axdre3UQECH3AefVZR8v9g/7
95XmRP9IhB2KaGh96CPJIF5poL8XrJFofkOT4fGn9zoXq2IkPwyY+DJ9TLsBBWaDBNGrCnT1We21
kbbpadwVBL55t5EDFcLrn4zW2HihzUdWbUZaV0mY4BgMmZJY52cFhsBa0mawVtdBEayihOsDsUDw
hJWm24X+naDT6mkBx7hoOrETAgleduAyT9uzRPobC1M9zi+LpNQW1Kz0PJiZoja29MF+NiY1oTh7
cU0JXrtH6Y78CnuOWih3RXDNgSDYS52qpg9Rry8Hx+N+7A7dfR7bWLGIPG+/1FOrjSbSBq7q+BPP
ecEO3KDFQoKZHFdprqOSPV+GBNS+/2fFOZ4yiCqAY3qT4WjtKfE9P+je52YKfRC2fJcTf6GVSzSz
Ld4YNd8OtGkQ+btDfHJ12///vSnqiFAauRm6JquUGaoiknZCaPwFXmaKPZTeyiC35AqpGkhgSaTw
gAdoqZgQG7yVOV9NF+lRk06oQF7k7zWcDurXlONJeNZZNNwdkmHW15VjhCZIXQocfwjRtuWMH6ao
fy/9CdNQR5IuVgzAeIxKjwdmLrd1pxpvNTjJ64+GPVtld/595aec6vShsx8Ogui5+8UHE88WSuyE
wxyFqNMI8keEU68suDZE+xkepWycXY7Rn0GEPtRgdsLCoJkoRnT9ugAy4DyU+uriY0BkLYYYJ8Nk
/57Vkl9u20RwcQ38xECRXUm0VMzN74vjgWDBERuHkFZ1qUCxNroWJfnXbnx2aERif540Q93cdcG3
socQLOkKjD+CKGEYIb3fVLFmGp6o9DEgeBvwy+mSLp2J8abI4p7uTKQvwELgN2qWsDSUHiQFtG3c
FbVlVSz0EH8pfUt9bM4v108R2Tt6SSPKlgohTIVjHC/B9RTlA9wGDt9PBQIwlqrlSzVaWJJXOh5n
oGqripWHmnVDD2rg/AkVGIoW4K3DXm3QalDs/C5x+s6dBk8agHsY9PEs3jE0NqXdo1fiHxLlEpUY
oMED+igXZt7/8xxDPeLJpJpbjF/fExx60r4BZikp6XoXjkfQVLpCHyT4bi1NnrDWqC1NEHBMRd5x
nCeaYAxdgEhUft3v3sz9SyAFwQtG4UZpkpl993rN9pZ8I80e5TUEvMQSJ1IQsTwPSOpyhA81VAbi
26p7NqbkWMlXOuf0A2mLfw9xAHVQX250wGukHsMfTo0YVrSGkxXb2pQD6nu/G5ibFoaSSX2ld35P
D+vk1gqSC2i9d7bGmGv6j5fL9jO1lXPrtgTZeKoWvb4qs7yK5/WIx/qoIM65y5S+ZXBO78bpSoza
DABOoOnvSzRcQ3QNJM/URDXJm9J4wWdNJti7TOpDXzuJIg1PFKLTcMyBFIS70JNaU2rIm5wnqkBk
+IStkkqkDvIjAm5hcY/R365rSQOsIhI1b+lxjBd4YrmXh0H3MvuS2CKAICZ+Tc0gzl3GEV5tgnrm
gsuFopTlefOqu4EGt2zqlHrQZGz/y2v6S2EIH6TE3Y0fe/Z767A9lU5lvFj56I/+4SqQbyUtPZcT
FcyE4UxrvtvGg50LjWPi8q9SEhW2BK1kKAjjxW9o/WdcItcImhGsrS8L0cSriiEAKv5PVJHIJROg
huRjkhOcNufW3GSdPh3l207uXhGR7DGmFxxy9arEJJ7yleOky8d8CFhx4mejtL4pZXCRgzK8xXT9
mgAFvDTPM4e1dwGGGyL6Pep1w2nqyUCDd7PvBBiirTr2KBZvSvnxcu740uiSFiUs7UsicOF+QCoN
vntpeea7I1Kn9OTP+dsmE1Q+52lP27285/nFEBu4iyOvxLlwKcG9qIAE81U29Ah6TIQyt285z0LY
kQ91eVNjHGy6wIt2n+50dSDFb8f5PaMxaebOG/7cSr1OXlE3PVngB/96xpEMe4guLnGttwcIFsIB
gSCecvYsFvZIZVVi2gaWBQ5zmOaEkMsu4uDmTgXQGJ3u1Y0tygNwmDWdwyXYNDVTfVuThOvgWgr1
L5soEdK2SGo1l5XP35op0pqA2tZm/trbQEfnlwpenzLvZgUlz0xJTSsiWu6F0kXCPpTORNtjIO66
aAmDmZUUJLx5OpzFDq3cd6A0/iG9QmBZQhMQf1zSI4Ogw3SAYybQ84B/A3Mz/lCVG1UyfthpwM5k
55VfT/SbEdAbowbc+KVWaaK9yMPKEZUIEyYsfv63g4pJXVYlH2zhpmxmIqylS3ZpIz9GB3hy8nI0
M+JrGX3U7bBjQgYcx2/4V2mT9fB1yQbYR4UdY7ukfYCvRWc0omMc8xyGI0XBmgx+Uv5pihDChlHR
/WZgJyQSuAjHt9EpvGsQBEXLbpoEUuKHP7YOkSSvwyLNr9gZK+7JQLBycI2ya56jrdfo0u1zMOG7
RFl1S7xj8g/mfVlhpzw6hoRon1BpcXF9S7owhVEhpfNPzN2iVU+hNnhv+ByFLd69YE0FLoUU4dBi
mtWRf+WNHcFDJbuDok66AcX8d+m6vyzdpIpGaQqQSALkR6HGHbATs3jwYnQFKs684Nwn6TTWcChm
NKqFiUywRybgQ8s56vT9lN3OAVzHcj0vq4l9EwQ1gWc2kHlVpOXjBWFTCVmyqW/P88imwP8nndho
eCmnZzW6UzIrZv9WhUNit1RbHqyE0LaTkOhn6ELaPETrkYY+FA333Qr8enLts7E4DMCHvuk7dgA4
UWihqhNfoCh4bcohnTXc6sQs/CZzkfnznAlb6d3ci30Oq1MlUNteca86mGN4CUd4BPOkglRbKTMj
S6VFdRgdhCsrKvS1MxQswmsYt3NubqQyKCRRSqCPqumqTRG5nZ3TO8PQ5ux5DULpfR+sv5piA1Z+
moEV57Pzzbk3U+uNzmXC+8NU+DrqoyApe6Tj7hmvzBnOv/lg4C+KoomWjkOQZxdHbchTjYHwg2DI
AwjRapoTsijLLWOTyk6AnC83XhP0qFqikFmnypnYSELjCb4ayuz1iK3KYBKSuRofrKaDF3LqYypB
IjchI7u/ZvErFuMN66M6kAmqN0UtE0ZccNjlvmIwbny4FgcwUkbAwg34BeW1EO9EbfgW832gWMVT
X48quDOL6Mgb3/rasK+dITjrtA1XImndtTgUaM2kjYGxqmyxchz1z7+1TxB6UfdbmomO2vKqBYFY
i9JmVxf6EkgkzrPdR2VwVKOijy54AxAHW9fy+s2yXe5U3ZhPoe6W8Hml0zydrMQeAhvVWcDqBtdh
hyxIB69G6kEQeU9iL1DPDM6U5a17kq+6aW6+EQXEeNORUX5izGL0+gRz2jGMC3hJYa5zbSbES/Q8
WMfwlAGCQWxCOD3Fok+rYwVy4h9CaIS1+KTtpEyZ2H5TuWhItJWZ6hbh3D323U3ZWwxHDzJOiZSj
hkNlxyE/SdjE4lgodD2jlfHuAY7eMlRvxxehib5JqUux1iR31EC3/FOWHvpj97znx2ZO27NXJrWr
6ouxadOY3sxYJp1d2T/dNndKC2XhjpO0K/T/1leuip7bzfo2CxRRYUuD90ABnJuRCXmhGRpy2v9U
6dkyAWHMcpfixr2nRQFDEKpfN6NGvGa6gQjChcF1YJj3U3DIJ5tUj9I0NHJurFMLXYOIkvE61nuJ
fx6YNmYsBUbRmPdG3gMbzPlIdsbpBE0J4CGauV5eI9VKLZy8qhD85zco53XGqh7+/kAItnjY6dgd
4VZo+SW2BvlwGA++yefXNPAgNXF+AAUbQsmB/hMbstjEFyGKGrCvSYNPP/cQcxd03c46xg1vrQeZ
rNROJamJNhRGEbxD6gT2Sny1xea2Zv2ABjz5X0EebKCfxZZnU0OqQCpSG29Yv4aoFf8FdpMgdhA0
tt0uQufjuIwyGXk19jPz3Y9FAA/jexzJNZeNzhkCkIwwkxjD76Jr7ffjTJiz0dJ7aYV9N5FG71kN
1du0vDgPwc8jC/cF24KBbwZoD1kOK+dldfujwA35hgtdbd++7xlvPOUbNtpKnJXgUUrn8YeLsqwx
OqoK1YZi05vZn1sENSJ3M1NuIML4XS3l0FzjA4NY6QoMspA7Nd5StRXsIhpcAR2UNBAhJlX2zkxX
my+HVOczmKcb82+MbUK7XNs1UTNIz/zLR+AW7/ioPX0u/hNAbi5aL2nxOENfaQ9TLLqAQK7lS5IA
bYYN2DE6gfUdhkyGU74Yt4McJpS7EHeg5nHjySNJAmMfT2Fs9pER5gLileAHLwsqF3/96B9CIqxs
Bw7D1OZr+QGxUqPdWSuNqsV01ZdZC7D6IW76sruf63w44hbDPBVW87rywe6o0kpVMa1Ci/YqquZi
hXf47cgmZLrDOYpC8X5AB/pxhBGz3+RRvdvSkCWQWGOEGWzevhp+C7UmZhganxwAbCPT4OXIibu/
7vnGiTJXrEP/5tmty7VDDg8xnSpzv4vHkZGRcBRZlYdtFfr8NDVunTmBFYDNtvIICU6efe7FLObg
vfYEqiOkT+ziy9bg6gxtUe2lOlXDeZ2jc0G8ZzmUE7z8S9fsJL0oY6nySdgoDFJVzFKDzSVRpmeb
KJ7qmj5r8zWElIgIgKompvBm2rdHf/5zxlqYEnRNnkMVbi7ecVqpGM+f4aHAIO+kifeeLsryToPM
BRs+G+cFK8uwtKOjYAWtBYD7rV0/NwTny7b1fI7+HzMWxxJ2hlC7dcrQnLER/LlQADmZql7SGwjS
HEOahRB4JE0QP8X5Xp/0Q5C41i5FkKfznzyFKmTkDU8vf7ZuIGrmJ+SNPG29F6KkfxUxl4inu++c
7h4nY7zROQGR3dIt+ZUIHJJtdfEPNRsamWlV0NWm93tfFF//FPMIdI4ZPL56EOj1tFlLgyet31S2
HsRwv6HQbIAUHrN/VzhOIURru2cen/HR9jY4AzTa2XUssaynzYDFkU+Obil1JX/jHkH7mL0qGWdE
hnoU6kgXNjYAU58qGwobutF1g7xQAwMDwXzdprkbC9FozeReX4qRTWHC9rLEhrs0EOuwyDbM2+QE
uPHVUgUz38M4IPAa2xUKRwc28wLjnR7rCOcbmqu97al5pd7rFMWb1+6kPJtdTAoz3kTGpiCboLTu
W9+p19YZSmsNFR+EUO7ApUAXYJttR2ItIpyEd6RJDuGlAt0gZ19/dZsF95w1Zm6nuE+Pf4gNGB7+
jS0PBYMwUP8lMhxfL0JtqZINWeAO6ozv5PWkZbmibNVFXsphbiVyJ/klRo4r2es5jl+6eGj759ij
BHJTVlYJmpkSaEfbN+38VqDL2RdOqxUeUZian84cYiVtx4ZxEVc7/JgW4QNn/BQZYkzhj4jD/E3B
AgMnuDKK77/5oqS77e2iRuvso18BhLnLgAzauAjj6Lv0pQzISFz1DdGD7seSLBC0psm1B91kWqNx
a0AyXKup0Y6CI6NU2ac61wQHrZzbZ33Rmebnc4gIk5ni2JsTZZTDoa9z2fn6OrES4iYXVsaa+xmJ
IfQFTvWOtCRNxFhDXPIT0annNtHA9kxtahDqwGXZu3/PJozpKJPeyy/7u36x4JnP1zsh4ZHsokGk
pEOo4mUhKlR2L5TWz3rU/pCeYVyY/fps6WfgPgndvaVaOlpiZEXxQPtoJDRoJgfLymXVT1pIj1dX
crbvZiEo7nPMhvnoE6ai+8qmmIY+oo6QtsQmrbBk8wbITp+6+VkL1IyzyWccb7wstnUUHWyT9hPL
rbYcokhCGlMP2dU7fT8eihEnHvPRXvjafMzOyOXAX/zclcOwPPvPa3lcT8GCEGOQb9ij66ag8pLB
qljZzIiOtB5qANxGETQK2RyOOvmNs+N2yN+j1zq8NG+1syd7LyZyQ+xnXt4fFTkqD5t20sGQwkf1
qWmFovOSUDIw+Y85Wl5jvuwQtpRoQ46IsA+tsmpMC5E7yMYwe5O++rs1ANyINyxDpQwZAFk7BCc1
SGSU/YOY8TwuZ5hOmCEYzd/vsEC5zQzBm/U4VMUev7IC335qqDc98fFm3olQR91R/ocXbg1Zjs8Z
vf32a5LONVmphJduGAmD8AenJylu9cUttstftOHOQs8Cq9aylBAWWiV/kNeP85KfqEGAPgBJGHM2
2ta1A5Qsw1UuC59vHhZlcAlx32PWYlLJSGRib1mrM0o2r1Qcl/efPr6h1VNfd5LRBAJ2uN66Sq3L
TRuRtM17rSyTtQS5+k4jmdrGTCok7fnVuCFM2R36f8eEhos9HPDTh0pPTwlxzhFFGxJhgCgFcliM
Es/kyTxRK+QMqCH558jouuIbuUVM6Gs3ejUZbhDQ8rXI0ntG1pQKmXlPG7bt0DGl1XEpxegKXVXR
ZErVuMkJmuOse3kMOyUu/8B5ReMp/Gy5ntnNPJhicZhT57K2FpJXAaq3YcF8ZTmLPbfYa76SExoo
fZEx1O7ipEN98JUSUIsQ7AyPbzeQfLLxQax9+jHjCKroIfXStou0RIl8qy+xNr9p6IvbAhdvB/HX
TfYwQ3aicnWLx2YXzmfvEyXCuz1vqOU4+D8PbBVS7ogLWdh+Uor96nwgg1Sx1TN+M6MoZi6yhFqu
98to+5YCQ1AjeoWujWWN/rsKdENxKHtLynFoPaMNjXEanpXFEz04xa6hmwWn99VsOaJSCBz0QlO8
L67cdmnCD6I2zwCkGjIuBxuB7iMAS4Ou7+68rsl3nDDLPa8LIufZnZ5/TEdKcEn8/tzwQKTpDrL8
E71CsswFQ6iuuKcFijo08ixU27kZ9XBvZLZmXu5NMy7RvXHBFyeC8qgUhQBf7EZonwQgrB0p2YKX
j6TdwwkJ1t0VWAV0aQ1aJ2UD9dIctQGDwRBQd8CYcl0U3PV5hQ+a9PD/rtA3akR++mVdFjZuoHzy
rg9sMKvYHVE8xhQH5qfdej8KJEd6mEKmH1n8dr7ItB3hFAjELz+0BKmUnZ9j9IUYtFMEDj03/1Tv
wGyOTOw+pcp073oS02Hydb6CVpKdPz4UaHihUDs78uRxWNS5X4UgT5K2tWWvp6vuXpUiwbhsMeTE
f33P1g9q7P0foKdDOLdOc8Gy4jkEdbJOXevrW6LLZ1NskaILgXrcZKxDHMurnWl7xR6rp7oPjtY0
K7NuvMuFoDahbuWzbvZ4k2DExjE1QeTCVxFRNWuqO7KjOfUWkw6v/mIJ0snRHlY59KE1MMurPnBt
KfkmbUYmzDrrW5+sTxzd+O58QyX0cLeayUMvW42TvC3jpSWA8eTTrRT12q94QXExYtK7trSpM/7l
TMfR1TbI4Odl1Qmg1HbAb8NB3idfnRpO3PuLEp4fX1pnyI0iKPtmsSUSq6WCi7gJo+yYbRAQU3yW
FZUGxyJFAKTSFmzyRpXBy+rlqy3tL5z+nD9I+iRye35dKYYFQudzxTd9QyCrp/eAYKzi1OPgAG8W
UDSY39wMntDDYaGGtcqnyzRXo1MLHa9lMwEmlON+1Z7q5lAWD5U0QB3ro0i6KBr1Kw+CaiTn2gsT
c/sZGv+0tOHxvgtIUYTTCpJuTApGBrRHQmZVeB8t+QTDg5DLQ+G1P7Jhye6mvqwqxiQL3njHSvXB
AMt1VbwFpXsIM+vU7t90g0wnCplC2u7Wc2YBqTTt3kMxS2J39eW6K/MTmN9s+/bijKM09hpCm+X4
14IoWn0M71rtNcckqYKw2nMVNn7flDwuj8MBYRYZJFS1Wq8habQ8MignQHRtwRlaRwhejapiYhh2
amCbPEmCIaBf/D+5S1dQzMyyd/0JGx9CeV8Addu3lrc7v/8Oa+qIEDfQV1VN1dVJN6teLlgclQaW
vg5qfZ0ywnzSbTzNb/ayfy3iOJWd+6a2LTdBmu5xn2lBXSPfDatsy0TEURMZXcoX0oCXX9fpXVEi
VzN1S0/ErESJuXPZS4PHcob3m5YH7gUg8+Bco4ESfYizNaRX5hB6Ta++95zthr1FAIyJ87rRQQdw
9x+Wb5n9AAGT4IKjWfPM30mzy76e9wvEVgFPxZlZu7nrUk24Et3C9d5HeLpTEgyanHrw+0CUeCfB
kvFBnlUqNq2+pNCsqtMy1MNqLmMK9n9qdFnoD91+YoVsiSAk7D6HEzMWFBEw1Rj1EP71KI5T/6O7
qaLlxJ5OPgq1sRydOzA+Tlpmv47a1zsCE7vDbg96PgZVLSuVn8i1uRI1O423bVBOzuB0MCHIDD6V
bcd2EPDN7HTStohpEzIgz3UCsIJ+7xvccmiBkj4EW5jG78F0XiI1E1koBDqMnM1BI9LAvZDL3O04
9czanHzhdvX/8HnFX//BB7TGRnlXp2guELwfWqKbNYP+TMEjyIm6tBGAmJatm3MyvBcL+yi375mn
nMP4GztupOFWhJ4cLsXNdPV/b2HUJeRrawfwKVeJ/Sxq+rVsY++/dcfNCNwxWV0EWajUMs53VE1+
k0pas4olvyuP+lZmXwa96tAlCeX9xgVnV3QIvvvUZ8RBxvYtpCoJG1QWxnmgKrixBvGrmPZfuo/p
BHQ4PepPmqIVXftf5Oxy5RJbBbkm/XmSK21aC9TqSePFFkPTb4rBrYOwM+07IZsdJ8iDmjKLX4sL
1AqDpPrBNgZfcRCpmpqaMg4ypc0tDmN8lHGevShOVSlGZZ2x5ERvC1Wr6xrAHqRFeBipet9lJWZg
+M/OSlNvLgtnrzhXwMzUS9J0vsWJ2a0g/gSaJtWq7tIJaJOIxqMtXzF5SzyZxMvdNvM9xpv7uAVt
gTz6bwf6wu7+18ohLLcvogkybMBznUpLkHqAhmWrzapHzm/D+zAup8kv2cDQHlPTKdcTvF6NG+tK
bRrmahfF3BSsxVbV0bNU24UNVr1BH9pSYYbDSP2C9KxPtOg0Dkl24v7ix4XfneQj9UPVEDVZEEwY
kWthW+qdGlKAe3C1oV39WHdpB5/jtm6sggprWGxnYVMaWm6q8rWu4gGmp4XxCjmMyFBpoyjYm/8x
eHqKL82pE2ZjzxCkKMdAcaYHemiLJS73PAuexOtN2qCFRbzpHekOUfwyzXsZP8bpTX4T1tYKmRE8
vIsQcxew9jaOM//2qRoT82vpB9lZDFODozrgRw5kPJMyH69L3+fnQZHUoGyQKevPbEuCtO96X2nd
J7hZwJDTx98fCtvP6yMTfmlhaNV/pi4ytxYWi2gLL7By1+tayIiUY8hwvKnjmskoWy+62Jk8ip0m
in+K1JuoOknK3kEaIr2BhyWXbZW21jETTFDrafWpeURGQi/MSr5g3tpsH1oYYabdUu6xSBYoF1mT
sdKjqNGdRH4ziCxMLXyLUx+KrDbzzvaq33YBiV5jEN+VNn4dSE0RX5t62bgwrzlYQPQgOkzSlnsp
3Q1JbwLBkvJiAiwfD7Clh1PFOp2X8+yM3cWYJ6ybEq9+AUwZC+UcGU4cSUUVLvIftbkf99zf1QII
5Q43f89SUwyY2YEziMLiVrFyaHYJjIyXDuKM0d4JM9UYQAH2WyE6FA/4/fJvYWxyoU9zG80GtKHg
rghFbn2sfJrSNcRLipjP51Mj7Xf0VjccJKvJR5E1+8n0MaZk3qb/Kr6YsDJvMqqIox/yrn1YjyP8
GYtkYvt9rzUHULBp9eD4JRjepouRUSq4h1URjtrc8ZeWmOz8Vuy/o0/oZZ/N+bb6SCxmp+lv8oBS
D8x+YfE7Ep8MfW7SngI+QA3NnvymxKUhdH6CJkqY+/32OjFXhF/8iYKilBBYu6v1+Wq6re5kJgl3
36o7MBI1SUSydxtrVAtwHBnwbUHTRpwmXmMgYJCp0HrwmPujSXS/oHheUZAH4FXRWwhWyRNaCsr7
5c+ZRJgwVpZj3kgtIkdSfhbBz4nMFypgG7/lWvAX2UIuhBRPMVNHmKjnl7eTbjII/u/1PUJbdMlP
iz17Wxx8lYgUZ+ZSi1ajH+8sVYzKhzhgW0lnJmtY1x0wJtoMw0Qh2hblDkXl3EWtomJchm61UlRB
qmeEGrKuje5iHGHo6GjlKfyz3zsl0BGAzSaH9SKqhEqpNfgp6W9ddjLUnKgzIJN6pDs/4FD8Ej6o
JZiv0+FYJX0bALpFtRvvktcO+KIyMAmdZTl9uTBMI9b+LhT68Pxr3Fls2KX5Ygy9Kv6yVPEsFGJ3
n5VTgFYfIk9ehvN5xpcxmQnkQguHPQAkK5HaOm7TWZ7h7hP9kd/FyDY1oOvynYQyxuUxZhGALZHe
KVBwAUdu8rwtqY47Q6xLgeSHHhtdFQvCmnmUfMt0gSZ9btEtV6vjP+G5P4HxgS9npnkETEfBEYew
qsUJnQbRvk9ZedGw2MGQftN1AeUctv89URu7symUa6PisR9RRbw922tzFi0C6q4J4rPBVA232u9+
QdRmhH2Vo8LLxDZfO6DggYE0g65mn1QmBHXOEdKOHZqYuSZrqpxHKZ73MhkoCOJR2waNdGo2No6t
gwxk5z1rexFDBXPoX9AOa6anDMvMYWiPrQUGhD4lJZrt+Iv1r8GniQDePnOhrzCOKl5619RkfYHs
IxeqU36dmMZQNeZVL30uBd6BO4/8nBJJxbrH0kk4vKEOptIS8P8XwXpiDivW2NR6Dcu2OhzRSLmq
7sULpfYYCzZmgG6VNCC8oImAEyLYWkNEVac/EkYL7YIyf2gTPPmbfKBs1lRpxbcKOXj6PwY8RfWU
wai8x2RbkowaETPvPJGsvaQcSfBQDpPu8JG8c1RFwq0kWp/s1r6ifmIQsWvBg3PHpJJu61AH1XfL
y2BvSBXERnZJHCz4YxBpMTYhk+sG+KUPvoRYlaOt0iQTkxmsuBjaj3WebNUaMqOlYpvhfxHAbCT2
RfqLPOSKAnmiryCairwTDzWLTv75JnEDKYVXGzB7RBgyutuamV1j3b2CreKOwkqwRDjAlq7rcgqu
BS+mDT/Q9cpKXcfEJRjU7eUKgA710YfBLDuvHBNPT7iMhlnLJ8ayspf62mkRoKwBwzpFOA0doy7U
UhY3KLsDbJ+nTU9Cp6+oYQYxLaQd9jznICVyRNJUgEhkmZh6AwrodIR2bL3zDufwS0hRGPURQORb
l69FlG9c/BiCPjWcuqNsFbnTO0YSEI+1elRpJNTlG/CLlYo2oLfGUds4nQClEyDosalFea+TS+5X
4v7/hUobBdNCldrtvFIoZzNcC9CNExTe8+fkZ3ttWIxuk+CiymnZMA04a0dPz+j6Y+O+UFGhZdpV
fPlZ6BdegbV+ZEnXZiuojivU+aa2qTKYExKAIn1aE7NGU0k5wfCfnhHoAPFwqbMownezklXiYyWr
2/eP5e+39lkN5IP0GbUc2hZT7uVwwKfWuEG+l0oFl3i8hqXsRVNKqwQdN7TDBTSCA29Xh+OxLiJ4
WIgA+mzhsrX90IbPP89mWpqGNrTrK+VzxBZJP24hyuDwMRCQhAdNtbKgCB0iON4vvcAK+LLaoesh
MA6X8vFLZrNMkWFsai8DFfW8sdaRsHDoLUhZFKK6tBCkb04SdqdRjva423jKPtYVwVmaVnf8WdXt
NfQmhPu8qgR5JkxPEF91mEhK2sXwnMTGYtxHRtUcnihFxN00rQ49D/xZPD8CtEPxPwtztZoj5GeP
hFhDVvA/oen432znWAP2itRFZxQd5l55C88CP94l1b+V06oGWd/8RQyZ/E5L66ycZ80yhGnMCvev
Ve1AZYsAi0E22+bS0N2/qwlwkrpN+z+vI497q8INwTWkqHPtFu0hNwSYyf07KTVAMSccvzpJS4t0
qIlEj4gOd7MaJsaWRlhW5Hkx62bXxF6c6wUDSO1OvqHAvrWQym5M4l0vquT4KlpNbqLtxa/iJD3b
0DfPXsbpOGAS5HoMA50hn65ZmGKDJz+DsULuMhoQBCOvH4T5SXUUwTbSgCOpgPWWiZKAEg6kaw+G
IwU12885XsJtpeNAKTRewFgDGkBEzX8yyLgjf6FqaOqXJsc7X7vXX3f4MLuBhSsNY56oHALCMl4V
yJn0zu5ob+vGwooJKmCq0LMMIV+p6VgiU6VcQXVkgSR6kdKWLKNjUDSO2KZTwu6h+zxulLS8TQP4
+/uhVAjR01v7dNJRIorwoijR/oGLd22JkQha+qyb2bSYWkSqQ+SRsVWvwHnExkismrmU/SKQI7aJ
TqrLZF2B+Ry2p1aqwi0mMGmR3CVVXepEyrOMRnfZltd3D2wLO9gR2rJcYsoo2B1w+D8PYFDOYTQn
YJgJRQz31Hq+bMuGJ4JuLSHfK+d6N0PmB6q9Dc6jPfuKVfOBP+6kI7cN7N3E9SHBJ7VDuXCT7OVH
YC0z6bmI9nRW1+Z+u+NgZjyc7M3dI1MSGY4aPH6MeI29g5hS7rJnPLvRfP511RGO6gPNy1jA0QJV
vn/0UF/noafNlPud+kT+TnSk670OFSuHixsWHt5DMk63N11I6jr3/c3bX7hgCyq46UgxUbeb/7iD
Ggx1+TV/BIz+juJirHhCComVVklrj4PWYcPM5FhyjRPx4GqZ7uOQ3pTKNxFWc4hXPPdiKGAjz3Mf
UN28j/ryWPJZJRJ3/5Lk5QWRv8osMDFmmSYff9KxJ2H/C4sWhyDG5iX+O4JjGyvEiKFKz568Omfk
S6i5qIAHQ1pXkukrbtrt9rk6ntNDUlLWqc+bp8aJtNFjhvidh7/EVfuwGKU1ab2XCGHmDF8Q8Ibk
gn2b0owGkEJvIJ4QRx2JGhIzHG2KJo2fxXDYRBIgveOivM4HeO31aZgsjfc3POM+P4GEGVPk2+tD
+3aipEYICJGrlGTpBTw+Rgq2Zy0uRRXy9QFMfFl/dqr3y/PR7MAZw4ke+BSiTjpq77UcD+ZUHt/o
r5IThMyU9uwH6hetHqkcb1df8JuG3eFWuB/9lUJmgXl7jsvAACLazrXb4+XU3+SQ+L/u+FQtCesX
+lLV/nJzuVzfIIqIIPkKYOSm+SA3uZ3KQbreWCRfTQhoW6Kc1zyjL/JR6mxsQNp61z/SuaYBdAn9
Qz1X4oWyhtGloor+1kkSUr8NCZ2B7PIF+oElyQPGbeVlDE/0iRzvYRDoBbCxiEUb4MtjJkmS6h4b
geGMTVWGy36Tg7N4fL4qZt07qp2wawuEmyr80U5b+4gPGjpoZjTgBWINokTAEQweDvByx+DQrLP7
TkQGJVR8uS8jR0OMfuukcO+lsAgwhYFQwILHZFOlPRIJwtHtf3q5FWMdHGhm8IrQSHgcxY2lqIdu
es91AyqcDdXd9lfjY9Xfj9Zf5Uu61SGXRRzwyxDjEu3Lnt2oJSp8clbrgiclH6n6IXCYcWor+/gW
xdbWP+LYsgOlqiwmSDhtTO5OHVtdZzrgMhWq+gmFbrxrbCTS88aitOeaPqXgXULJgWjqMcRFxKr2
Mn8UYFUjLHBLrHNBMD10+++EquB6qAV+fEvUTWxUjvyqdboQkjCQAlSkkLwfljDXhVd6YrNvPFof
qJo94bmgfhKX6wolRW2ezoUU4Be3x/WiYKiWvEHkJHH2yw3yS6RBGwBfHIoVk2RtkyrZGHwSpjah
SlTJeBHM57pEUnYoa5Q4zTPfPY55tQZ0Qs/z3Uef0RnEB2heoWugWNUwf5Jx+ihciCxgUeIkVpyk
a6H/RqOxUfeTRgG80j8X5zeFobbEEOO+hGUqgCNkIQkCBR+awFK0qP1Fgj8+pazgEgU6KQ+PKM+V
nNrkB280dL0dPBb4nyDZun61IG7nxz46tryJmOtitDVboKADwHvMdfhPXhHA+2HHZOSwh608clrh
27cChwROmvp8kTGMk/PXaQrA2cAEfFEBeDCks30vcYvTesb7icGR9PmjlGamYm7tjSoynvfMiTgY
4eRlt9zReML0Ey9rARUfPTKHQT1y5QyCC9rtcut0dukTJDOXlN2hxk9nSdoryLjQ2/0UPB3BsLym
032qQZQGQuvUbpPvrB3I2shODi8djMcptvmwRQ4T25VWHIgicrDPwe5HVEy6I1gTB6e27eiuIfuy
T7/raNKZt8GjeiEgGXwsTvRw9qcRI8XuPTO7qjowfLSEZR32jQQy11HAolL9v+OB2vvVI28M9g5Q
Jf+E3z9p5mhqd4XEU6GaTS+srdsER+oVzOUcBsKWPYOyccCdRkqicS4QAmwm24Qlx6Do8QaBoQSk
+S+g2lJuDYfUSUZhrOJpEXiI4tq/q3ypx2azl9mgpSZzKKysFsyqBdjBqT2aAUx+dvK3VLsRZPE6
V/7RWJEkbliJz2suDnqHOhySLJQEu+V38UJSgdCr+5D4OTZAEwi+FT1t88B9tIXDQLHFMnQJOLd8
amCnOso5CctFtxiIozoJ/cyL+OQ9J26+MLFgvizEWLv8yagQJH1m6T94vktq8bAVV2fgviS8EUdd
fCeqh3ensVnOcZJpkHwNGd+d/eyT6MswQHJXHSI+xPT8HxTzmt9LL9/Ld4WpvmJzO2vxNOKY/VWx
/GuUpOkxS9K/s7nMaLl0EkjEeN1PcJAz7nNheXWcejP+ZHG4ZeyLJz9bYiLPc6DKjV86Ody6xu3O
CW4Rgc/US6rC8mOqStDUgMNk2ur+PU49mHfUAWp1F6aI0RTklPA6NKadoZkzt+mAtdhUMJyjkqu/
jLQZATbezuH4JdUih/8ex6PJ5UfA9ynSmpdgY5/9es7oRtBjrEWXok/znvEtrpI5Z1UciLrt2N6Q
FUpRXV9OGvBKGqhG+Qog+wOMCD99BIe6sCwwS5rpGkbXU51xiGeFZrBJVHvjS1lMZrGPFj1jI6vB
tbpmhRogeV1kjPGFf1OauxJ4SHbyaQNl88EFZnjQcHLl6rxe5E2IoGHng3AM0VH6ktm1FJySsNBU
vighP8F/VsWHcKQlWx5+yNwYWVMUkZV61awxTDgM1/B8ZfhrCPbqzDDU278P5Eu1oQCaEBvUW+cZ
d0RwGyyrWuph/5jH2gmOjXQ3SbsmE7QE+2kfg8xXmjAQBNOCHOBdOINHMWuaHjsfddk35IXxEue5
x/tCueJbLhLMcbspYq/7BrFll1CAFLjpgp5rwYfK/OQFbkqqhy2TsoXuRZv8zdCW+1kuayDBeQ8S
SyP6YnAwcvMK/xfHIPP+UiF3/FU9juboiIZBnv7dUfSs3w4LcbTeT6vDDhT8xv56uEQNB5RXSr6r
Z6TDx6HypWo4aaHe5zyk29DBVNfCwxm1/6N1mvoOUZGez+v4pG1vHMgLWKm6a5oFEiMLeuaYVCMg
p2AyTIRqnniVyIOfplOAKOf4D7wu14PhC8KquuYNwrEeRkfv2PjXMMrD9qkDmeRXTIlqS/rblubs
gB4di+qHHMLkL1uP0an9kJGeyQnmvp/J2ovcDo8+AAMz5bn5r/a6behg5rEKY53JAqmQifrrxpfO
8h94+k2fwEL02OEciBIxMsi75vPtr4YCX5odZRptEnVx91pjss7H2ehQ8MSOIUtW4cxri4qg/XmQ
wHcN9Y+XVneXxJHY5HryiwhThTvmcaoBKkNm67JlS4J9HgX/B29Xh0cXOPfDm7tXG1quV7OTHpXR
UrTZ1/jg96QnfSV/62VxU3lGz7tzldVFGZ0N+Vv2OgBeFwRlWMQ0sm5UzWlUPiKyzDPh/vIvkStz
/J/tP7y5C4wLoSwVaCnJflRHjpIW142RqHfPclObZBvvrcxH6BCCtIyEkPudpW2ja0n8C/M076M5
bJHotJga1L8kOfv5zOghPX+5SaWSLFFgCh1uZyTw5G6f2fhV/MZAvWfyNX2OjYL4QQfjSYmboSc8
AAoeQ6EXyu9cgekD6ASUhII/cu7ek/vSdbddSFGddkq6jeN3VAQmJvgxCLcqbwNH10mg38jxNa9y
ONRReWdM+6sKWBn6OWxpKVfLYbnHpw0/EN8rYD0Ku8GUuV5BesCDRAc63kJtRlw6WD3DYdqhHLg+
dUg1784xPjdWWsB+os8v2QGdNJ5odWlp9wHN75NME3k5OOTFjfcVBIh66O8FhSJazmWvCKEYfpWB
/DpZn2KOJyuWZxI7vag+rabK4R7q7dzdogrx1dQ+5EnXeCj+aEQ/pZlwO9Jw7wuDrB6PXcCVm5qJ
vEGSevHvGTpCwo6OM2Xz64DnPPPRXEcSjEbMfvv8tdQ8gEbHiaH1eh8Q/qFjaR4JnM95Gj3NbPEC
bJ6GzNdiKhKspVy6+qZrN5+xc7w4gNaSwn29Le7wtUy+HtDnD6BCgb8NNvx6Ca3DFLA5g5sEaG7h
1D+e2/9v8/A93D8KwMpvGBxEGUne6eXULjMyPnQuHKtltNsHAgxvYuXcpJPgC/pEPQLMhMeGHCry
bDVVLYWwQCHv957Jg6Fb9NRwdXMtCxTz/sFpocY/R1sytIul6L/1J5HmBssygExV69Vj6MtrG/r0
1LdUJwpifoUHdEEyJ7JIT7Kuo8qLJ3ugqVYXZ8wq47jXGcZUbF8ChSG/wOLRpbFUaPqjARQy6wUu
d/c4ZaJ364xin3HFqTwAPi/XlG8k2nQaMbHT2UCXk+Gxs/h4891FMhI82/HMGBdMVJ9q+k+MIoXa
lWJndlJ7W/8CrvYU9Z6GcfUPBytXdjbbva7laGsbej8OHEh690/0t0pzqZJKLyMP8yxOSuvZg0xX
NNlSfotAK7PRgQT1bY8yL6NBjfbmFm5+53TXpL8Fd+RXgCwZ6UM1LeUlHz5Jz+3nShx4uYodEdWm
nXPHGcWXpc/5VBRWrlQI2Rp2JN1Rk4zkHWqWeVY5xAMAfyxiu6zZTm31L9e9MzGZ6fHgBqeMhsKk
C//SHmpOta7bLsuGV8m0949o/k2VLhTAbGPy4Q6PGTf9f9u2a1hh1Dm4JQQDGqLq7At7UoxAImZL
5Nr3u6oy/+pLAQiWEtsmn8QFd5m7DzQ4ceAegW/m4sQPgTDSX5ZwMCrJ/0R+ZB5C9sPGF/Tsnn9z
YE7EWM+Yz3gePW2ChxId28d5VyWUpkgJIPRVjYuKxQ36VkrvgcV7H2h+A5KHJV/gP3NI7kjzic4O
7J/9xGOhTWFARFdHEMErK6Hn4W0v6kHgC+i+CVlIl9Vah4NxOmKlDVPngAHXHRk+09OaErSegfbZ
4WMLWgPQfNj0rfPosEOee5iF9MoSN8f3Gevz1/TLXQ75zU7M89mv8eg2/eSwxc8lFK2M72OK1Rb9
BgTlFK9Sp+xPUzVlcjPFkFK/mpTxOV8dnS6yQklC0H4nt6s+kqU1OK6eDEDHXn9TOto+w3fmU690
c59Ohos+3AP0eKtUU8uS9L9jrscYjQ8FuQU2REizq0EBlhh/D9dj8jLjrN4BzQEUAw9a0bgN4zxp
xymrCQzyfsyzOUkzg2H6gMmW7aY+Itwv0wFlPY+dv29UxriacV7Roa5x/9cF7EGetnvniK+U4FOG
XrYHGt2rC0Txn41o2TVDEHcPHrDjRQ4ZS6N0CsAPxWKsSy3XW3NxYcQaI9j9LoZxm5Up1hYiTuV4
E/gZeDQEHkR99BgrAMwFi853C552psEj0l5DInUwPST1X/j2wkaG1UujUkm7+tfUBaffmcnv2UNW
9K17arl2bKv6K8GpLTjo4p7BgcBxxcyqMPkR77gjTZjtuIE3J4iITTTHgeGD4CaYOU1QEJNurXsL
Mr9cQvS6n29qX/dvqNIc4i8BdHA3aylnVO/6cJH0ef+ab7JNdJ0ahKSjiljEFNqDPXpAEKwmZRWG
0G+IenMF+l94vFS+vJ82WQecLCu4JjLcacdtMy3yzjCmXneAqL9fHmLbL8DnvISCf53tJdHQ14/M
N0D0k+1uuE1cDYy0IIkOXRd4fiakh0crREjjbHZud1Sh0gNR8tlIp1B5hR8qQrqvjyLQM2cIYcTp
3BeCD0wz8MH41jcHeSLPNY8ni/Ia/wjEaf6ibNMlCvCoEPnqbtLvPZko5fN0YwKkzPlIzaTGLi4c
RgnssEGlayN6IC82ZQttghJhLmvlJwUsGIaoE9q3cx7sgb1wRmR/xQbcBac2dvlZG8b0aIjr6kYx
4Xz1/4Dq/pKbXLKpITsR0hkHKRC35aY/6EHcEtayv+FovvgqSL6b/6uY18MXQY7RN0HZ7jaAakf5
Yvl/bUd2wx4XEbnibR7ZIRVKRiqwCY/7gOYFIGv4+j0/L5e5RMDwhLaLg692oreEhIKh2hxPU051
18eiI6RlsYqhXbUT8kWiDtelU4L5Wfas5ETZVzAkATqqKVvNfxfup7Hk+71fK9okxLoU+qGd0yy8
bFXXW1WSPDv/CS+ia0OMBAI6ELLy8pgvgtgNuIWxEUPNa5IESYwznzlPplZY4DdQ3MRND/Meye+g
36w02QeINPz5KL80FjUUEnKEtNOCJZrsRlcaRNC4iMD60d35oaxDpWbhcv8Oury86+x+aAds1M1B
dvo4IKRP9GHPNY7HYezBsVyRGS6+GXyw9E147+pZbCyzUmOUBWUd0UQkRCCFoULQUcbbtRUtqk+w
dFf2L5iURZ/6DMaUeIwK9z76SzYmTt4JveDEgmhHg0bJTBRvBgbZrQNpIq/jGOuku0+gl/2Gv/Dl
AGzzaQniAM8fcYLP7gCM84FNZifXWVUunWqiCWMg4sRkJr0as2zdHHxIvoQ322t+dNEYKk5dbVST
j1jnWKp+U8uPvWxMK8MW96kd0VLRzLv97ii7K3IzxpQfYZjy+pO/IYIR9LnX8eGKM9oeQgMlEenx
JhkbpZWvj7owsFkxPfp4v3Otje0HVInulKgbHmXU7I3Jp62OQY/h6yTVzeoq68GLN/A8oe8T6Rz5
IJmYvhQ45OfF8/glNb46gAcjyDb8ghQyngTvC2KXq7DTesPshpdbkr5pfpGzVUltgWZiZDJvU+RX
lK2dzQMcwvqYl4v29KCu7tpFPUUSUwr+17osmRlOPr2zOWXCGWobAmqmNzdho7IjEa4QBRcIg/Vg
1g92Zaza+HOkrQ88X1gPMrE1/NKC8kdtd+L24ArQA+r9RnljTRpitVsegklnOH57NPjZe/vc/iTg
U513oyCA7s3aWn1U0oD3pLKeXM/uOZ7qkNSvMQ4vMPgJu4iH9rcVa9WVZ0tEU8TWioEAzo44JjH+
kiuf84jsrVNzw7qYwBUFz5PJXNG6yLvK/a60AqGd4aJ4hM9u1193+YrRPWEEo0a7QLwGZX5WSvK9
xNkvrHwxcSnFhrHGa1Tl94DNidk/hDQ5MC9+oevVX7v3HgvZ/IvdxHpYYfwMRjSvd+4ejE7hhJXm
qyD0LgHJIQ1aNYPRPC/2Wr/dNoBzs8BrNwTgqxzbhZ/WC+gkFSZ+s/IkUPY2B14zHbyzfj/oGL74
FdAVo0ewjDi3QSO0xuW3+sAsqAf31QDGxSa4UvxVlKUeteydmA1iFa9KE85TKj0xtCtgykHMj6ot
XMHvcAw5MDGbNtMsTkV96ychhkm12ITx2L3xz0zv2j4S3tlGB8bi+UimBnK2H41keKbT6vbhtdn3
sZQztrG3lZsBZ4RTAW29nD/FnoSNPjCLk2CSPP9zLvZSpwyBpvf0EjWa/ZqKRdHthhFh7XCNqlwZ
PCTlaqOig5GlsJ1enMqDyRFUj5GpOlS3XYRI5owSaS1PSK7K68OlGEsSNK5zZrk+RUby5TdptLrW
FrMFfw3URjPiAhiODWMXFMxxcEbxDbfLU8HlotEdjCNwkrMhRPyE/uUpxw4/uCEl4O06lteKGVYz
7WmPrbWj40Q4bmWPm4xLY0i2B4a4VGpW8LLwcU7d8x7kiQ+ZZfUmEXGaklVfoWZmSEFg3PUhLiUz
8xSMGeWAUIoJhuQAC7f+kClwIKaM4jGkdo/1Q/XWoJyEeNnuCjNWqTXmt+Bau7aU5RfbASuy5x4d
5FMYGbRhOTCNupajdrChShY1lzKd8VlmBOAYdKTOGzULqjJUPRqTnVVBxoExuuZ80Gh5egGPr6+9
5OLKsZXZlo0HcMc9DIKdLMMs2yhCRoVbnaRMnnZ+kQjUIk/y2ROyWDMb/cki+sidU2Y53OGbPYYg
z19DvO0DPsDLpuCWBqGyJ/LKBhVdvZfoTzgT0nCRb6SIHkro3jXILjFpZTHP0MXcOSlFWLuXUzz5
zgeMH5rA7MibTgmN9/q/KDwyZO6v5cWK5RQjSCZgYATw5Zp/RyDMNGB0ZmMIMClLku2ZrCg3Ae7K
PYvM562XtfthYRrJP2AvJW8Heg/DT4JHLKBwWKX+AgQBn8c6xbaAaAEDYpkBUcc1jf97r9eZWseG
ajou57OAHhvaVw+I1RYLZVXmo0IQjYx8bThSvFnXAIjVZ6loMlpo1KGGmF9CcXJ9IrYOvLwS4C8d
Il6KFkmQgP7lEsIbfygBQTiAG6YXD0hTNUfQoFBQGaIGs3ol8/bS6bZY3GM1fFrIhQ0opVdzSdYh
BbOrsoz0BTLUcpzmM3jdSnbi3q8fmje+cC1nRqCKQD7q37G2TwWcYUWnDHXy5gN5G7+KJg3nFYwC
K9+PJ/GVhdDe/zBH741HWM3t7D1G2jq+QCEGiBKqN6sXEc3a2TCCN/8ALEiUimxYNnW9ncFX+H9+
fl6VarD2RsT7LP58i/+zkA7zPGH9Cu3TFRmImt/jOo4f+ZMhHh/UfZuXt5YA+fnT5xTniIMjPl64
O+DSOYcBWvwHDwg7hRMaoIXByFmSC1ARim4CX/gnmlXrOi5brnt46d7oSlR80W5wJsqPE66gVmHk
0jbSCEBW2Kc4o/8NeBnH5XdtQbwtjJYdzoKNAbDWFZL0e41auQ3LM9v9QffLY7ILgHJn5nM1Mb+D
U6v/FvbohAhjO7Jmyxf3OzkpXmTZZ9mAV4NuYe6LCZ+3rU8i79126Z+WONJ8xh7Hb5o99QOzdy+J
wFo1To+blNSJWgGYX3mX2JydBMJuOiV3fxRa+Q9ZMJd7KFqmavtz+CHvS9c2ypjQW2BnfAZJ71if
PDiZ0peGC0QKPBRN3f9xOXfrA6lMGm3K6dDlX9ZCXs2TfpDlakIK2Zd5J4kEJAMsarwyyO4VK7BY
GJNAKq0iuAL3INXSzVncyKXYi7zix7TN7HXSWKgs5ZBpn2VAbUzdRIyImOu5GX9nYmj/SjLQURA2
9+6dHzJC+z67tNroCtoFSIJnBun8rfIOIvyRrupL9iCsoh0O317pFlWTOFSYy+czqlMoZ+fi+rAy
9VGA+PjgOFoXQKOO1h+RRauRHM16F4s4wNaI0uVJNPiSZj8eF6JjrYOvpn9fOU68u57DKQi50lgx
cm373KF3Nssl6uuzX9oZi6octDQArks53l0A9KgW3rn08JfyXdqN20wTGfoB1vZxCzAaGdxHuv1S
FDL8rWFBdrWv9h4mbMQoLnoj0Kt3nEnibVqQVVxnjBSTFKTJK4/FcSIHsVCeRoGZH4RHKQ0DVCa8
ef7NGEqZJtD9DvDErCUoLTE+Z/NT1td3rrOqWzL7fVXwywkyrhd7x9CwUHD/liV+uK+tsh22vlMG
OT7C9s0+hg+8cYN9YZPIgewQjiLJ8a4q+9Q7WWnlt+f1wCSGrfnQ9raxoSnfDFnaqN1X1R6Lp+DL
gBkqDvL7G8HX408TRkoAnAUO/AqIwJQzaU604eKG0I0/Rk4dQH0B7YMxm/Ar3sptS8/05aqvwFjf
Vvc+/LGz2NDiJ4ocqjjRigG6s6Dv4sfdNdTFy6UmRS2J8NEZYOKTpAoVeQJ3ynQkBXgjzRmpUiV4
SpsygJsZMXKoJrJ+wSKNWGs6Bmy9DcLGvBj8r1mkXTyVpGKfyqM06CN/zv1TsJEPem6RL49lA/fn
mpmGi9MI8eupmncNlexl2Ve5jtW+31OOzarStjsBZ/VHqRL+DCjBFykP1Wydc8ZoPlUUH4bTZk4p
ZT8RJR9DhFK0DcOXhcFikcWNrLaJ0RXN+3QoVn9zaV0axoNDVYnxB8b8llk+bdk26yUkBurKNuH1
/CetMpVAhAWbdTexIdHt1Lc2jm3QzIL5+BMdw6l9iHm3v8vqH8lI5QT2IPwhGji70iYgPYhaUyr0
ur1Eg+FVe4CksTjOTA99bdSnZa8+MfqqweQ37DFUg7sIpnUFe+rtkw5PpgbdVTriRQGgcVMJGHPE
w74yFW985inpN1J83e3eOHb9SKbpy4OCnBCde/4i0N1go0paQfT8CeePWEn+0ZwEkgAP/ot4VAYu
wDi3q28NS7qGYK4duxEHeCSAsdkdRn79dlDati2/Rj5QX4sD9+48OGTjM5Z7w7lIFCIeP2fbSFX+
HjM66UgmPXAwwReO/WrpziI3sbRFPHAI492uwkofC1aPtwRBpUG+nI9STYqavYmaDXjI01MIKPtl
kmmRS/80sORyrKODJ67tX965qlGyTXi32/K96jkmum1pB8bKQ40wKNdVTpnAzLm1Ogb7VNXelJ63
Rii8vlNtMlRqvmuMywX08QNzihF95/hlJAMtc99dpznM0kFJVPIebyvMaFZkIJOFDvoagpfA/6Nw
0LQoY3kdiqZsq2qqyzzEbXPG/2ZvnAevN4RJIdj4mUnPlMBe7oVvmNUQT0tADZ/yXYmfut6fV0Jg
EUcui3rELzeGYGvx3/sLeMqBsMb6wnuQVa3DGOQLQtIGxB8DYZ43mhjkQWMMzuHHRvrVbzccbSjm
idPutbcBBGdxr8jSE0vKEfQ5XteVnbU/Z7RcullHwmGkw0ur+DPimr9DGf9G+fkVdDiFKgGhNxlr
5CaFmZ65jDOEqCCvDOUu6nw9qrHCEI7v3RladEE/A6WeoljM+M61NafrEoWZ/6f6LU/dm1C9L4Lo
O7mPKXQe/Yp7AtyDeu29zV1K2F9WLQlNbb1Q3FdXFBBg4kj6nMjEqATX77BlHw6pi7FoZRt9kzkX
MAeacmrFBz+fpGQ3tR9028h5bhpo050v6JX2iLDEIbBz2kp6t9M75KKNg8hiKhbByCFuxWuxG/RI
I0YwvKOoX4eecJZn1aw52gotCNOYHurLu0Zt1NKq4DXv/5ECr4ZlQMTqwdhmEjcH0+ca3SUqhM3f
EoiN8iNCYKl37j9Wc83H34LGonf8loVWYeZf4uzoVTa2zNqGtF0++IQsfqIszO2dQ6m/GjWVez/r
nhFmuoqMCH01R7zAUNyy1gzfyZqOSV5p4aOA8dJIxE427BSQMs14EmvgBV7iCMzU7tDjhlBVJZjT
1Y0jT+gT2Y/6KQx18/xhUPGWvJADpin8p5YCtSCnz4iH+/BLQXvAC++RcszNLgvWSrwo7bykcrpY
Xy1SMYXCEqioKl4ZJunYeuoNM/QtbTc0QR732DT8+w6v2n2QwvwmMtIxViFoORhUIlNiQcgN1cVr
oueMn1868g4S5+b+hNFefYwkqK5IrBdy5BZg50NfHfWv0J6gxVAZvYyZWqOxcxXC55yTSdgaCiwI
1+uL4RDiMk/fTX65EYFtMg9N8VN92tFqvxUgnFPbkgDLjYNIgYIZK3NBFWZTkV2axZT+CCJ1Zul6
oiO47h5wNuZJCUVczqC58NwQb07OX0oZ4Ao3nIe6PNkiJlHOC5xCRrXKLu5ymoexbzgIH2E6CQpH
FW0nKeKZtwww0jeDW6jCdp3MMtWAnUGJZHvrYMeqkw7tP4QQPe7/+df3YeCeRyfJbUR7IyMLjKi6
u8QuvSdSq7IXg3KHAxfIwSldfsARomrdXDm9dCBmuCV29Hc7OEEAm0JiKGFq7Fe0c6bycCkx1lIV
P3fjBvhEJfvMCc1ZUSbAgPcQvtrr9+hZh9DQH+PE8eNvnqCedwTGKLcFKhWmA5PeLVSL9yIHP1QP
ok5VXHJkqBkZ9Dj8bsa/5FZWXlJyI7YhfDedSkRgOtM/hlJBjtIhkTQwAit0/aCyQFHKEU9H6rFS
LD5xZXfW7A0N9rLBVZzEvoo7TNGquCGa+Lqd7IuVFt+R/xhPAThNSltaKTfMJuvMOIyrfSpIGlq8
xkWbGqJhc2KV8G0Pu2HUQtznxj3gcBuiPg9ZIeOZrIDrsGJFu72Sd+/k4li4ZeCIMAZMocllcL+e
cmcxVMW1xXoCOQ5bnXZec4t2P0qWOQV27pcPmswok5yvh/m6k18JDPH9+4Az1F1eTEoZlyz8UxYA
38yh1NqIbKzDp6IS1Rhx5e3jQTCswNuNf/ViuaEDcvSImFJJ4s7KMZavy/bsv1OLAqQBhwGzph+0
NNI2lvSC0j53SqcVC0WE+rnaFo9xncLBYsIdt23S8e+6txqAK9FhBmYmmNX1WXeTPK/FQWaAkx0A
hkMiZ2v/D17ebg58MUWVnrmeezJWrVlBS7elSjnsXVxdkzA25y3yzQcCGVZBI5kgcqNpyms/9O8x
7Q37IlnZzmFw9NCICUDNWCfmLlsilw9I59pZhsdIGzUkF1KNoQQeLlPZfXQk+Uo5lnLU/9pnEisC
rrqol0sCwPMiR+nk+gB6WeO4APIHi1zcQwLnEsZv2OzQjY3oifCSOxWrynPwLvU6L133xEd4VXoO
rGrQYOeQrt8u8bhUMcNbu4GXRQ46L6DJ/MhfvFfQMK3cmRGCsZda5cOD+McAZqnhvXxiQl0L++G8
Uo1rWsPMoFxTGMLgfs+w3lSiMRVdr2TmraX7tlP/n85hitp6tHjSPAgZEH9OtmmpPJHe9B+vWht0
FfFy6BYMPl+HuPbL+Cg32A+lERTj4vsMGGlacNp15XtobZ3Jgr7BkdECRM1g5k/z7peM2L2W6mOx
mqgJEjqT5G9NdcVkVnwxiNdNNkc99yOrTgzw7/lhz4AAHxuzIzRAPkQvMHcrJT9CtDaHPEflIMTz
Xx8U+Jv6BPKs+hZ2FnhV7Eq7lOrK0JQj8bLVQiwxPo0o8yDzwVaMvUoQVAykqmHVnNVtRGGfnK4Q
tJyJBFYNI5gjuPD/XmdKky8qa5cczz321+VjNpj/RgcIA25rzmOqaRZ0KJsQoHOA/52PpUYX3T+J
g05voPwzSWlJktWJQIRCTcaTjDWUiDMDa4eATlWqQlySb3rINH61sEl+ZeIdNhW/X9Tf1FiMFh16
knYvSG5NXjwNJMyCzlyo/nHh/VmkO88Gr/dhuY0u3XMXJxNKh6ZH+hUUelCWLYWJnnjSF5JpkDYw
3gzfBQrxYRJ3gFNMIyoPKncXnMlZdvz1Kco8k17+m/AFLEPEobS16W1M+FwaztiUPqTwb/W3pUQ9
kqpvJZbRTeTsyV78Q764ovbVkKXlzLEXGN4tPej61SDVa2/P8AArRonfaqnbQIn9AEyCfTq9N0Vy
7fmVLJ3mLEZa5GeLg9haAz824IUJhKOUSTnMLNej1qVtyxjZ6M/rHjIYOVgRxl+Mwb3Go8z8dx/i
A0w2XKZ3omA6hPycDcwgk27sclK5khhy1geoy/N/ecwiTP93CrG20N+Cd+hN1uU03B0WCBfDOFS+
gd8N5xo7+VNLgJR1Dq88saDgncCSj+xDIvzkCumCiJtvgHDsMMKaNk6VtHieBDczCYLFUfPzogXn
pNyH+e3wLEkHjsxsa1wtY0HGD2c7e8dKLtJsDjiA7UfKhNs3agstoJvvyaCzbl6ys20tDLEaxt6c
DVJ/Ou5WOVk7NSTx5umvBbsF544R3YsINkBiQ7IVSPXgpjuw9KIvRdQloyIM7yJdiJ1G3pxszmCt
En70yj1gcvgNcgCXM3iKULl6IuCtf3bkSZdH6pHCU+YTD91zFaHLEqXfrPsMOFPyRC813MrOwaWK
CTQ66mM6qat7wKASrovjtJ0QQ3KHrWz2pjA5duxp1BAUYkQDvKUuAZsGFX9OBYUEV0qJDXNRFR+B
TuMpf6tCk8NCAE7F+g01EvudVeZExnVz0yPXmilZT+N0fbFdruWarhuXyOnN/OJnCNQAEN8L7kQc
oTlsdxSHdZYfeZnQssGjpiwmOWzyZpg7i98h+iH7WT6sIrvSdA8GoT0m3lC1epKkv0PJmiNbNoXx
R+ypWOKROx4dDrw28koHWSrm1fVZL/f4lkOzP0zZsXDhupiVLnpqEKvdB010ZY4lS3yvgaHkd/js
RSrUUFdqHWlajJBZ16EyJsP9xOJDC14vvJATJ7jJs/ImcUk2UqVbEJCZjE7MLf8ZxESiyqsVxl2i
bHQxyvVbEud7eVwyex2uvAzHdO3gE93X+R1HAUXnZpeSr8MSaX6A8SSjajW0PcHhj2SRBZW1jlcP
t9BAB9IqrdhuF3CP8xkKRXU8jrWzm5kSQ4iApjV66Wb6rCbYFvbgVaYiZjFp0CPMn4l9bPz3u5OM
0fco1Wnf1fiQudxH5wK8nria2Ly/n5qNVHjusBK1Co9Cgov82ZiLgKc/GHyTqSG+xCd4iCtjxUvv
3GKwjvBzaSFAkb9zye+2xkFv/ckCzThFkTTeoSkvIQEmpCHanEvVu22HfEtvWMQDvRn9jmWLfVN7
JHYnfzJyPxn8nI05BXxs9hGHUyw5t5CFZ6jxdHu62gUuXzfKQGGTYSRRHUx6aT8o/pbmpZd7t5Mm
n9WEoCDlVYjBk7+aJOWYcTfcDmG7Xtu5rVFOv8VaoDEZw9dd5KR/hwrr+ueVNQhnikOERfGQk2fl
aPpe87eDxFTq8IC/zVVQcVHMshnFkr7oqicMib832lAGypvZFN/Vh30ojYu0niEdreNdIdJaYbXt
ydPNW9SxJ5FDyXMtmc22EhkHvXzV8vTrKs417tZs4xL+MVq5mZ1E6JXdD7XTJkTeCiWl4K05nmIX
D01bBN6v0IcSdZlxapOjvvoKqfE8e140OzJxIBYMSbEd/ZGJxZMTdm82fSewB9xqxiwQsMwhfHwp
ZO7iyvF6aLrn7T/nXnsPyCXpOsb1yE9Z3WbFKQBvr2Pk4PM750CBY/uy/zF1+uo8VVmyL4RzjSJU
Bw09+p6xTt1LIAKLPLLEBZfVEN3n1uSMj/dpBMAFlWh5frAT/vtVf0oyLKqE37DMsx/2XHjJenqe
Dy3I5dxeyKLLGEu45N9suP0a9PtjCEkfg7nbLMnlpY4qMfrLxbBIhz5paT1SwgeBRbuHiC/daJzm
S8N6QyJaYTyhtCJ4OUWmYc8SCQmgHvKGjxgbqjBFpi1H7G+OSR8DE4afJmDixpFpC/g5douXxOLh
TzJAKpWbw2IxHfKtRl0I23a7dSS56SbLo5LPm4By7d5ZTiIKXG2v79mRvGJzYiTZZl7GJjDvH+lO
q/snZHqFP8ITcDOTEzPvK+MoG2ZvrUh+XZoPXb0UcIHEjUI/Z2S/VTYbOzaBcS9sQiXBnkU8DfIR
OjhJ6BtSiMXD2g93nh1tkt3e9EjKKNjN2e9v6ZAptKuMaeYPV5QoIkWAebleZjQmj0Yc/E+dQVaw
atsgyV6YOD+BopqYrZKe6kXka7y06pPzi8zs068XOA9HYWlzrjtr0oO7LRmB9Y7CuJWFYTUStzKE
JtVKHuqo1uhNvxWJ1foKIU1b75R0Wa6kamWKKPO3XtZwYzxnxePIJNi1O/lq+R/sc9CZFSjr+K4D
ZOCnAdCRrrzcLuikBX4A3XDZBcG06Kfm6WKbmVxGu43QFn/kZQXlshP7io9FHJzaMApleoX4NCxs
BgnkL1OStREMk85Iged5O+wK6jFDVlXyFRZjfU5UxTR912vMmvr3SSzcbKNUyqKmQ01LEqdhne7M
p6AARaYnmOS0j9qL9Ju5o5+jdbJBqrNY/CZ+xbLA52g8apmGYmZlYDNUxdlUKHm3j2N0jyh9ok+j
KHMDhzya+Tx7PHi+FBBBeeqoB6wm79YP01URJjZNAgo97R7kQTur338ib+O++gaCx4ytGwMXjxuz
pOGnpCmcMk7CkxiM6rBdyuTNm2W+Q1XPtaJZIYtw4K29S+QmAaMrZ0XOSzKT7SucToDWeo9+DpxJ
kMA2Afgd05olx+Qj45ngBB4PQ03MhIlS+Yader9aR85Ok8e9S7zUjgO3vJt5eyiajoBQZFMv1sz4
5efK4UPcF2jKv4IPl9T7uG2VfSXoXdAkCTUFjql6fZKNGDDRN7U7iaAL8Z2p/GHlsRh97GR8KfHE
iAa8rSVGqL/wC/yeUI61b7pvzN44v18QTTLa7ZOEByERO54YDaUFySNGDqCTmRz1XjRt7wY6UtRZ
Gg2vQoOIHOh2JkB9rbBXq+QHM9MI+6YIzs4mWj50yp8oO064+O5maOsGe770VhFB1c7N7Qc5r+v7
P7veUPnAgVUoDloe+dWWbKQpBGGk9IAGl8J2TDVlEiWdzLwOtmT4npuusHJDPZr59axilk0YxArq
1UeH8UWwdwOmAe7uvmfLLQI8EcAp5UjDtpG25Gx2zLtEXe9A+umTSacEfPbSS3mIpTDnM2vKzokd
QxGoJzHpyZz4YFQjwKC07+QRZiyXdQzOul/AiFCS8LQ+VBMKGaxmVSPgwC0UxkNfdSvqvyXj5P1c
Uth9jWACwHpNXK+mqmVANp5MhUtGSLoigqvBb+1JANvo/+CSKsANlyRGGhmhuif6CBikFM8B8Pgg
/khgFozYkGpxxvugswkvUP+vbFno3I+G2irrBg0iYxj5nMQHNGGNyIRixxfKLloGDPYDz7cR5JeU
N/T4bYmVHdVOUkH93P0Xza3gd3xNHBptQyYBSq25cMp4MueYPkGxbPOat9rVvoSzo5qq73cK0v80
L+qSbZ55qRQxWyiGNFUPFB/O1p7DvhIiOkVnQW4umjd/hXRPgSDIasMkkvJO6mQQnvtEsRXyxTJU
6zyIEl2CWyMta63JHB87DfeDNwRzyFYjcO2r8GwRDQqKAPSoRhDqZA3sb+0XyWRy8Q3IqtQGA7aZ
1kUE0eOZTY21qW3uIJB3CTDVzi+s8aNMvR3Q4feI/V70r87lox4SyFzAyb9gNWz6cBJkhX6dWOtD
9ffT7I1quGXVkBWVKjM3RVYq7Q7Bt9HXXpMr3bW5ghpwcbKiQvvVq8VCS+E6UDfTzukWstS/Wx3S
LwNbFd4hBfAW/ItxjivlL5SOxKfKHzGHdRZLOi9QIEJl/LO7TSr2r5UUXebsW7ACOipaMptoRZt/
3JrlsHMczZswvRKdOaoN++uoyyNEJ8RWZkpNN9iOoMtYMkAecaFFCcc1Qj8lpOQ/tkQP1vTQ000o
58UbURsdrZBSkmKgijUUFKwUMjnxzyj8ABABNHn9pNWbOBFMAaGtr1xgbeov7PIqzjncplrT2v11
EqulqKA8Ztb+LJlnnKYinDJCeMqI6mfI0xwdc5IQ4uaKUPyH5eR8DGpSb8Qp4e98FPzKJ5sI5tVl
C3r1SmqDey7/2vlLP4mFS8zFCnNYuyxIFBFX0YJbvTglkVMxjDzEG8GlEZvVEny12e4V4TQObngQ
k8TAIJhp5kfynVsIpNnCl/evn6vEyPy+M93qI0s5TrvDt6Jkfii3G4ix0Ma2iKUqtAKXYPAYCZV1
XkaUV92czRBS9v2zhJs3bzlYP/NLSgjCyeXP0MmFgTbFcri19DpeL+QeankxLYFG9mnD4CQKOlmb
Wyo/DJ1Rt5k0LHP6Kfu7IwJIKPTcyrPOvNZt8XPibCbjAdvqIy79AicnlhbSFr5kFqL2+Qd34fwG
GHVO8N4lFCr9LL5MZ7VkVCcWfGLp39p5b+P0n2bZo025Q4ZhmCMZNui9nHBu2n6sDIDG2E1VYX8a
5c99vb7gdsB1WVcgegbkMs5Jq/BfytjvG9FEASNjdLacPIdnP9NVz4fT/Ea9o2Syv76DqHfb+S2H
1Q94+LVV0/IjUxzy5hCdJG8aaf+dibn0bM9In/Z8B4Ns9/Jb6iGArAjuAQ/Gs0HeUhvoKrnPs5aP
sC+G4CwChQn1jdhlA2vlcumX+msCX+l63lrU39u3Aq2tyhlm3aAtrMTgjhpJrfuTMOYhp9Rkm/+e
JbqD5AAuuYw36//mA+y3e6YEL9gHSOAvIXcANZdxPKu8M1iCpSWfgWNtuRo3NjpVY8N99Qt+KFUd
6bH6V06ea1VzxDhgpvN2kQKbdiEDq/A/xDg1f30DCwzzIA4ZHg1C9ewrhlt3EX6YUkQPLlPRtY1E
cj19VWapJ4Ce9PT2l8CN45zNNXcNiNcees7w1HQg/avM1/Z3ZIqZgjorxiMoJq9PEjpTl8LN5mrD
2YW2M4/K/fmZuypSILzMWj55QXO0JDpTn9jIb7ByaWqzjgFE0j/Z8YFBAjUzbizguxz6oNQ2Bdqz
fpEXr01msf6gNgZG7SLFpm9QCKmxoSb/LmK4kJSL5iXSWf5AVLKMeNwmoqvprA4OsvQtGSS+6k+L
TWtqiFUov3RvyLspAteOcVImj2KLnjpuBN5N2TWPSwxChfFK6A5VW1XbyG0r+0xwLgOXBnP5rUgl
RuXqgLNR31hA91E7PbmYJea+Sr5mOWknC5j7HcwJdJuaZCW92PEQqSR/fDg41CAu7YC5mLdF2Dhj
zUlEpZDdp3ArHTOaqcxfOm0ctQ/vF+Q4eAYV263f/wShJsPt2vpf42ThKOFA83WX/HhiqxgYy3a3
hGp2FKS5eMod6mlL4Rf9OoWFKeOWHEhCjnIEdQQ22q5mzjQvMQn8wr26fnzU7Szcyt9nG/QhF+zU
tYlIrRN61SKOGBT1pDzNWxnfr4+ECArG3tNfDBZozm6Zpry/JY5smlYcYzdQAgozguL32ispBCpJ
rKihyMOexk6pnqZnwW2VYy7A/oeNggwl+ct5O4CCMEUfg5jxzkqfhL9fLKHRO2DcD4iA2cXCKyL9
+clpZZ32pnVAJ6NSW4dRYP/bPLOs85P0dXr8fBf5GLJqftdGA7XBF/QbUWc7yYsmdJ73a+3sIyD3
Qp7Wn0Qh5rk718CnY3xtCcItM5QQvDjI9AfkfJwapZT+1jv5V/IDlrtqJ/8rO68vS+HA7S27GKJ0
XMvFzZdaFMBdo1suaInwF5gwwiZuKYiymFj9pTaZnqAD/8DZfSxYUhzvq28cOnc7mZ1iqNubYEny
NlahiHYsMtVbvzzn61TRBiIkUIQlU+i90no7P+rwm9g3bBNXrfOxduiWB+iWsSEukEjKxNo3wmlX
NzynIz5J+7fS9HnIGU1KtC+nC1s1ijhWOMl92JUnKd20R6hidZynGwyJHcGlso0YITuSy2uoDrdT
W/50n6KLF9q2+fT6wqivO3bncGPRah1NxAIIwfBgZ4YqBL1DwCnDFzVG20zsUNePQ+o39BPaXK45
oiMTSBdEwUq7fE3WUgBaQtMQrolOBG+yJm1hgO6mpXzNS7XSQg0LwOF8nsj/luOhShC4UxD+KAvM
z71NBeRpi8IloSiIpQB1DOYa2lvLBxxv+0AhXO7/GWn8bEzKVV9lm3C8WtndrbLA7WNfP+Wo9Z1a
v1AUBLLePfEujr8nTbiwKxBypnMuVAhBNCeBbShEDdAOWkWw+g4hlSC9ivqsuKA1bKTJUjLh58BL
ivM5dQUjwJO2pamP/uBP6vAFRHDsdltBGy3FurfMHbEOQ9nXmLl4oEdCVTVqdKZtDLt2IKISbSaL
0rOuPJF+hnXUrnR9uPRzpmx51xYw7hZKhHUgOgttd6qKcbaRRr1cI+6Znmz0usr53yX0nAX9yLmD
6fZ4U2YFxS4ZFA5+c+ZW8jCycFkz6Z2exTklD4gh0xLYBYaxrPBckueKtC+4meHuR/yNx7RD2QNu
IPaPT1mBtG0OwLtEiIwzXrxWbg+nvEkAK2/659+xtcDrfIMwtScQSxOqcMNhVUA2xvOyg5FLOMjJ
IMgKORZPu++mzguB08qMVvQiPUNnU2rqY7sZWUDBhdVyYu4HS22UU6NBllX3O7y/OSekHUZ3WI/H
wktDRmvKy1vF5AAR7C6J1tueYITdzdhMynaNM6/TRhHuKP0f2XgFOQmsV+973RKQe160s25ZR5AH
XiVjL13+E8vz8sf84qLo5eLtUVBnVYClCW6nWuOC8H5GcLmVDE7izcZnrBeoX/uByciZhnXbAfm8
HDoDIyx6uGlG80uzJXj+IK2Cled3/rvIlnI9tyjMDYX3wzzrMX5oY6ccWDU4oFNcDiAtnnFa5xBG
X+gMh8DqQN2i8im37ripIBJ4b9uXHoAveZvtAr7goIIImYk34DPBdOONnDFQzT22ce4+2SgTutcR
N2ngS9bLrY1CL8mZ1GWh9XHDZrVO7zuKYPMmxEgCmA8uIoBfscRITAfmlFLfdaKg+bmvPruPCnBC
ZSa2Ss/OHE7F5fZ8jiu1VdfrRQovpY7ii1mYX2lY5PNhtMSE2VbXqFVt/s4hh3CvdDqWerg9GE80
veIlXfHX5mxs3W7A7cjrcCmhIO57EGgIdN2T/YoYQYytCICaieka/5MlG2qK7bIkn5ngkNsrjUYv
qjCMleA32PrkZhbdlQGmm6VlCeszFE4zPX4ui2AlNohkxb5GTJRxv8hRGMj1UEPk7TnacE+VBRmu
dK/ZIHE1cOytw83Z9lOzeEwTP50LSTTKFGSQmBd1KSvMeGpg3gZa39zawQyzbizL4fj9S3O1CCfs
D8Q6vizOIhzlwx/QpBTXta5Pao+L1AfThO5sJjifSobhS+5ivuIMDhmAdN5ZCm6K3X2fN+nZHeE/
Z4EB12O+9qYbJzzM87xveBFqfhsuY0erTn86JjcwA+f5pLC2LkQ5nRSjBUdM1lGArG52ZeS8jeHP
WowFDa2c4Ahn4ejsemZ5puMHLsV4BhvQxCYdda4qSW285A4cPFb/9yiMZDrRIa7YJqVbEnuzXh8Y
W+pMG+1K9ix/+9aF2k+HJ4fb7b0VCcGrhzLq0+OrDmUOijesQhW3Nmym/uZFohgIVMDLN6jkZhzW
PA7hUWxjMlWXs008U3JV9ZCBo3OhF4ZJB1thuB+VI2CGVNASMdzet9g08F72Hed4H1yVsP5H41ry
Cmx7nn0abV0F5I+twKSqCg66Rthmu3itnOQoP5uyCHhTbtgoNReG23nsND3zQtHIKyUWG80esjUG
GgJCv4kG882Ax0jkAbxNsLUTZZNNzXqi7cZygKuZz7cAXDh5+p+r1g3IJvvfAaDhvXK5I98iNfRT
9FEj2Am9vlbnC5BZUCe48zTAT+cPRxODH6lpWjN1HRx2K8A4DdqP9wWnianOnmluB0VjMgNH2tlQ
WVkYpQrSz/Ar5XsvFDeLbxJxZ7FbWEgq2SgaNp1A5hugupTcZnzfwco7EsD9Su9oq/PZNXks2s7Y
NjVxYWq5ma3s84IaInhtqevwCZ557m83zcj/r/WI3aJxzJGjeft7IdA7OKwxQDhmOD160ByL5lO3
mFgb0aNMCYRnR0+xfhC6pWjN2nawyjWjRzPbkcfQZD8az3kMLLQ2UNh2Zw+J12ElsF75BNiW++/7
TM2E+b/KlewQTr0XGVAOEDbPPaMiwVKPAG6SmQ2/sBeFoaMwkNYvA+oj6UTIdFrmSr0qKNRsflNT
AARbkNgRzJY0XBDqGWf2JN+qQ3xr3aO/EfsVw8Rwu4qfQ+q9yc0XqO6In8k1r7ka2GRLKh63/ZQM
42sOWQMUwv+pXGUHZ1U+8ctKQyN2oSf6WpA0ikQZklsKfrUelk2cNS6gaoTf/PO/nO2/8Ck7RYuR
j8ZEO1xAZac9poTxSQVfVDb2oZUqGmDJ4B4AadyEB73BIRqqruyOw3ZWlB+StXEY7l90rp5onA0I
FRuQyhlJ21E5i/XOKy8ZSs6OS5hDu53PxC+x8wYHuJGFMkPzL/T6ldia+eQWAdFNDJkAuh3aUpPW
mTKDiEKruwulrUPj8SIdXGym0WDIX56rM5aktjgHCBxlS7A4nEMMqhnqF3dBQL7Hh68Lvz+LlFw6
wFJC96fMyCfqlcaY3r3fblXymS9/iaHAAUbyG1lXYN9IzGsZMJA25Ded3E5EGs9BsHLe2PAP6K6w
h6UFNODAscV8YH6UaORCB607lxOkXbXPvh+vdTTWyaT7m6u9z51NqcO7/JW5KyGr5IXzSHo8KbUH
upVTG3dHDTBnoUv0YBBakmD0u00BmPuCBc9qkP3pigyhAp7r83c7t6RgcZQL2M5gTeD0pqiIr6D2
HYpGm34lX6/kj67p+X+NifHyDWwA8OTmNV442wMidfSkfcL/9ttz4aAPeYPp+pXYCAhgl4u7cnSn
/fp+izpsNAoSMxgZKnAwB3pOQtS5jL7TrdXWMnKT5GIUKj0Q5/U1TnhRo6TU50rpHjiAC3H4Tmp6
tV5lt7d5EOGRF2tEEVY8e7AiNtbwnuErY2co8iwPDGNohe2hW2znCc7WynTsEP7Emd5UXNoDMDKT
psKsoPnUvPEk1rT9rKb9wMTOtsNAPj0MRQML5p1Xis1uwDPWf8elZy+LVnaJ5SgEFun8ozukCbLB
CyIGvSYtZBXknA1Xrck83rs7lo1O4V/uBVL7BTslwQrj0sShw3AyYQB4fXtfwv75fk/aewAD2Pfj
GaAh3crUJzO1o/pWFB61XI32WLNnp7Q0P6mRGNYvAjd1w3ymIGwgHWmDzYEKsEvSrAsA4gPJ1Jp3
AMJwYOIgzJJYnSzUxzRpa/l4IshtrfM8dahtoFHU/exiTtAPvs7tnhU0vZY5yflnxx+S5K3K6R64
1UHli5uEHLjWQCacj8Cl66eYeUSYy86JE7+K8knkLXEz0NErGww7Uk7DgFP7ZbfX7Xax4aMBCapb
wyaABgCQ7BB/eHnLPN9tJUEBZ7joCD5a/yVHdJ442IEavKZvfYvW3ZNpXuzuCUDWPlPPZSS9MwKC
BhQTKClrFKRv5pmgXIRQo/TftFewFW7eUKTvkVFRQnySocfIwMMy0MyYwBwIFwLjdICtGZ4uhp0t
3hcvApBiUqzkq2/6czI/m2iybgqVZw8Bc3sN3KPDKKrZpbRNK1Tsy08AG+mX/1PnyGx54KLkyHOd
KPm38xJID9Pf+csFEK3heHRCIMFHY/HoRYCWBP9Kshb1kTgi1yYhHN7ApjLr9OaRjc36MHRsmlz/
RZ5USNytHDPFagT9xW526ye9cKcOiuQuiEDhDk6BNgMSOWXU7/iJDHhQXw+V0evnEt83JqC4XloJ
whMsXfZXXL8bsGofCu61XJY8/MPmYhVMmli/687K8rGA5syRrF3gmi6kOok9zYCKHJw/mHBC2/Ej
nbKf58aAlNhQsiViTP0WIBlpaoKRZZ/Mv2LUr55/RclO10IqPmfQ72RPLdHt2HdtfZcCq7Tu1XpS
7wmQmBGu88xeVP65ys+lDeM9GPFReGq6S1gnWhKTRwkzZUz6Y8jR+MNIK5Qh9XvxXA1qsICz6K0O
SomwKcIwToBGkZZSwJNMDGU0orai9Bqd3WXHe8uVjlaJyC/Z9bLapt7r0/PWypjblsaxq75LGtRs
TNrFY4ryoAyYualnLDWaNokUpD9VuuBTGyPr5PwdtPlUd4Dqp8riS/bWwKYTdJhQjV9vDwSgs+Ez
Esj6h9vsedaaQf/mwPI0vC+Nu7zXcwlesDK+aGZ6ulyhmuYHlrW0NMlmdZN28ct59OPlQkJ7mVH9
MRX9U9A6km4XUwjheKOJux8FDmWeG39EIMvzvPDVwo3yomh8F/+xj8hqd8luiW8gIJDYZAzq1CKo
6ypbKmrwr+icHTuLiNj2lbd4vOzVDNMz/4rW5lNjg4NvWPuyvzR7wLTNaXqeHKi8kWXCS6BeSIeI
X1tJDc8DSCV9qCcb1AJGuAC2gHjbKtbupJC7Jtsu1PhR7IR4ZX4rF5UJKsqCiUf78eex9gg8oYGz
8xjkyEexGVy9+uyk1M3FxmCOOGXHFjYOPQvHeADICMRxnW5fJ/P4tF78uK+rbW2iwicqlDgdzuMg
3Ydc35PP95jv32Wigw7uZx3z+hxGa1H3AYEW9i+ZXSKiQZ7+x71+K7eqhv+h0JXRgbHFSxoqPEFf
DxenyKsU1dFtbQCGX52r5DAV3hJB0///ZOcIWNfZuyhvgmV6zn0mYyhlLn9H3cZPOJEzLHxhJU23
QSZTmVxQNtx9DxI9SdKo2KBcqaRcbtk44Qp+Zy5/2zZ+M8FS1Y50QUFuCyR33amrtdw++oo3aHvJ
dKyhtNBgaBkzihpGOBRU5oVS4PQUc+uQd/FqKcGN/hhJf1Kma2VcVYNtYAr3TMcrz2P4SVRI70ds
Ea0c7YXLCJHdbxIHNRDCytljR3CmMv0kKLXMSyqet7qvFDMCOXfjAmOS2JMman7ziQ+4OPOWSBlM
jycwcnJ+vdQ1tQdcLRVdHi5PdGa2rJFWCqoVPEye4rqYT1QA1JnD8IrBXGeuN+SrLICE8/L9YuX4
E+yV95sTNEQM7TPxm6LXyLNE2cL5n5W/IBl7Rq9IqqUGM1eJyKXEzHJxZUrpOUN42LG70ViVmUGp
3mZ98F6ThaZxRNN06GtfKGcKS+SPjUDWIdUmyWC2mPCbJH8aO+CBnV0W3Sy9pKqPJTo9duYIgFyU
BY81bJc/oDi6eERxAkrQ5OzvIgASGvF2b74HMuHVKUH4kceFJAviFJHFoDJo/+ZDsf4tyunLd3vA
dlBd0zlDzkGnUul65+7DPa2YaDbIY2tQF2ZOMDEwQG29kXLNQen7pQmm91agINK8xxIt7Z6MDXfk
rIcnoV1IbCkf0FmVnbNPcQLCwABHPF8/SL0Loq8xS7VoKXxhaiWAfrua+XOzslpdFoa+6BlBThRS
pqZ/A9ZI0ggN8JeGfmlYVYulUFhIOmHmRTYqInRI8CY8JeHYDlVmSyhdCkC3M4g+/JYt+GCPC143
hJ48cfgtZ+UN7qwQl72ECEvSaqUEZu22NmzPpTU+l3thTgvvOxYOkG69lBkRF4n0ds7agp74g6WJ
9lt4SRFt8Gv1MouKPu6mXtATjdL7/OZukTw7DHj511uPk9BkW9rV49ZyzObfTwLRMO72b2o3JJTO
DCfbqcJgedYQkPNPTK/5E9KvJv5Gf6eX/oWduYG/LVlNYb7fXcp+U1P9DQDvFtKKBUUa6NzSZpDU
ERL89p7VT6+9FfSDq8niVErrCK475XEBs04ZQ/UMxEZOVbkdx03we9QArVFhpUU8QDayHlFpKlb5
4uB917WwI8rvs90H4HhFUidzaP650NUhhx6P3RGkdvajee8XcpW33QznKbRnS1uRlup1KcSw6G42
JnFEgXGimUubFFdW4mGQvGqEe5Az/c9qryfiieDxYAPNaOWrLnB1LVX9zhtESd/t6bkV5ZAcR3Ft
ZA1oXF6dlgX5SQr6QZR9u7s8O+UeVkQ+EsnZnJCzq7NhkO0U/e8Xq5NBweghtsHNx7HGDrRzf/En
Pio+J/yOUBrmOk9yepVE1SU+jC7sVfatkoR57FKxk1aDB8A64yN7RSmcvFE6Cmxfp3q4sziN0uvk
yIlOJAt8BbHP/8Cs2L6Urtk9hV9MIKffx9LFg4wp1Oszu40X38PasESXhN7/N+sPcVbvpwqRhEzk
/o71uxRxRio4q+yBlPj/hnMYV437i5fNqwxXtWUBt19bVl3WxrM9ChCEpopmH7LsbjksTkCxvCey
dG1t27GqiPeYzgWHV1/lM07n/KtOLDckPTwoGA95xrf8zjZ9ZoHlDiIb7OPNnwc7jWg+UtMX1cW1
OPeiJTCgGIWBIy1R6/dVIoGrZlxrjj1Bzd89fzU8D0SPCZCXTxOm+h3g7ffhm3ZUkO2TnVJuqdPC
oB9C9Rd/W8awsymopeP5AD/EsNyya2ZrmJSeiAfCRIZPGstsKHwrQJ7EzZ1grTfC/YaRiOPoONwf
aq/3miqNNOtlf9wXQ/B/7dWe+dVBghPAXqufacR/vND+gUKr33MeMy8xEJOWqMFLldEYeRMK2ksI
e/WxvljLCgol2peL7L/2BHH8zA4oHmGN3CnoCBO16WNwkMprkW0v2xPOkKxLQ2m9bwxgVL+h98mR
xuHbOKooXsaOWGQnOxJhSM5VtS4P8svQU/DRgJf9JGPn1th9Jqbp30doL9ArftsNhmMk0qnCqSvZ
t+OIO+JOC5CaU2sAi1av6DyJjGx7db4Exgk90qRJKgcj9/cwIjYHgPLnwlaG7jlCBqx/PNen6hBA
Z0hTyat2cLISWuNgZw+zcbzepI9RWEj3K5ZuR2HMfiWVd1/K/msMBlxda555z8bWIX2nJIKBOoXS
DeZiDbxNafIlozIjEaNJdAUyBT3H7FXRWVO4qwoSgOG5YseVMuokdPXsqZ30wRHI1kXl5/pFc9f4
o6XpaxK7EP5vstXOKPVh1pwSqSCYtJS+JkQ2TzEkC7Hr3VBzQfkjOgaHtcOQe92XW43Bm2zIslDz
dNZuRaJY4cgXQ6raAbhXzmDs6z3YGgaqUtNH4lfm/QsFO39IZ1NYWKW3CjbV7OxTSfrfjLn2R4St
27iIMQh1aWHlxQpbtOXbCO4nZfr6rEhLPUT1CgRzHnlSaUyqFuCqn0e6IRWsY9rt683gGLE/6BKv
QJaFcnbECHZ5Lu02gIE3efOHJ5syGcbbmKpAfLLJLmPzjQIuQyDi3ggIx4JKRT3XjygHF3WjL65P
gCFjLBacQk/6rv3uEpQ+nl99f3rLek4a/DSnC89HW9sIJqMJ+a6fwjHG16fEu7ymasu2vMX0cxGW
lhmkvsujbL6Fr4P4DcIJU43XTcUSgojF5a4wh/AKgUw2J5IpoTHAjuHc/ZIB8yK1vaLOxDTd9eyo
yIz2zHKcJYTtmt7oDWvpDVKP9uOOq7Zi+cOE6wiB053UTbsT+YLY9ccmP1KMzICrEehQOpcQ8o30
E/8eWLLpJr0u85qGPs+AxeMOApWkFe50XUE+BE7J6TH7HOO8mHabocRlUb9MCLm1KLuVHXHdrL8L
5ON36hXLo+b5R7vAvbMk+ESNu4l+QZoHX6QE0S0ZI5LAobXpUU1VUESLSeJiZJ+xYsxXdT1wyBRz
TC10LJJcqQ67U5UdwC15UExEDuCOKoKA3kE2xSVVjyzIUDrKZlFEdAcSQRpbQP38fqNaxT/2JSw7
UN6gWY6CNWhuPJab+pZ+d4AyWEGLpndATthH04p9q55Y8gZJM7ivCQlKPQSjSTUv4u6HytQXSH1L
EjIWvXMtQiRI1bsgnOyzm/Rqb7KRwjcrHF3162VnGD/kTVDFUv6HRla5dNtZDzmPLBf4PiWZ2vLy
W1pRl4Rjv/IORqlHbTuQwbcZgbx8bkKMN5yGs8IyiHJ1tt92Sc4UZBque7/DvFUtvBMuHAuObouB
qSLGE/qr2iu48ot/sSez8623cSdBes6lHzZL0m8uuDrDti6QNeaeRQgqOOTJQS9Rr3LRt7feh0qp
nViijbrTPvUkkseWgUMadF+SmkiR8wpmRHCQbOZdXsxxRsybgqeqXIqBvcvFg6Huh+7oUaEgS/Mn
e3P8Ug9CJyme67MJSi4OIWhSj18dhyogysqfnX5dtTmAjkcTC4yIU5VXZdSMmqkR8wB2S6imR7UW
1jtfJaXR9Mx142afQIokdzn0UYWQTgO3NEqJxqoZG0PminbWwG6JhxnhRlpS7TOrR5a25xz8vFYk
K92l2pRV6cWhkTfU+9nQFfm0KjgRxNObnfW/K8hxF7VL2opc500xFlCjpHnXwIpgzHhbsoWgXA37
wKiFj/yKPcxBX12+VxMgOs8DxPLrGhUZsLnDzF0cTU+QgCkwpMDVTTkRf1aIUqfC0Zc+SsSIC5qZ
DJBv6u9QeFORzXKmxumw8SWI9EnPhiOpPlabMXgVR66JTazGd1a3VQfhaWdDEM9373nP2TXYB3CN
+x4fsUi6tmiPgi84I5CHWEMQLEiWHUMTjd8qR2ND1owxJtALXmzSCcdhuDTegrJYArpcAEZcgKwJ
OsZwneo+vIzy+Y6W3Pr79H/y2zdUKELHlGQZEcooGwba8FNJnPkQTaAiai2XoVVVvuhkN135e3I1
veL1Fnni/HmYh1ytA8g2fVYgs3r7ZyZpqGD7aMxRg5whME3XjBBSbB6iej9VoRxOeaYRpJK680mM
JJeh5TzROV+SIPAF5gvEd6DOjj0+lDec82/W9AXNtHsHZQHPuc0/9f7e5Es+NyNj7vyqBNcSxZ8+
Hg+8XGsUG3hyCoqxbl6/eXd4rRExHhhtDGRZjlZzuEyCPx6adsqbTAZEcvdubsSw4xZLUtgmK8EU
i5XsjvFJ5AzDdggh0DMIBChPjDbES9ehjCJJcZVxQiwjrXywuZjBfeR1ltcdPItDDsYCPYCQ1bbv
0cbwzKsgQa1Tkg6vkUY3ZSBEemyZOz3FpmWxQ5pvd49en9uolIzffoOmXFnpeGggN5uhwq1D+Cbq
0XaiYBtOmCakYJi4/mGFv5UHjUnj1pvU5rrxly9c/EgxAM5LF4tYByshDnVD9U0m9u+LtL/799lS
CkB0ELlHdOohl4kBKiIKXfKzrDWQeGIYhOYd617jNPCn8iqpfNkwYKFrNacR5ngMrgdHRLq7QsU0
mkXx+ktNcTMcxelWVNxl8aeelA/ypxyRStfXyr7sjSoyJKjX+UQajui+ODN9PmoLGW1wEb/S/Kxl
qGXFEfOX7aXST9aV0NScs0LlSYAenxSHJyTHqZO0QVSqj6GuzNw+4973UWXTqMlrGLxAdG+rUit9
nbEMPL2lfQ4OVkXa+or9n7n8eDgM0acJLUP9OUyIZYHWT+3aPsD5Ehfr4t+Y5Wep8BCuc2vGCsNy
bNcPDHk85qjkZHMrvkAjWCNLN9O5x46XACXSkymr9yJRaefhpTUQFvCeVTqo27PHttWT7I7SVyPs
4QKEW/0hVsFZOpnFPR5nVHjzj+rxLRP57fm4Ijpvp3rJz7yNHf8A/vzqKBX0TmouDw57IRKeZos6
U6nQXb8uWG5yBIBUmy3tFOLQBm6gJT99VuxHK3S99eLZfklCuyI+kTieSq1iUffYR6byfEA2KXKm
kphHGbVjSHjySzN5k1d/weJmRpFug+kvnAPgxcjHeKaVFLIBtks14/xshXp1Xwssraei8PdkEVd6
9Pmy8lIrBOx4vD1IdZ/x579wPinmmqQlPnlQSwBpmfV5yJas6k6vrspfKqRZENL40xdJpFnxSdd1
uiav11FtrziuzpmAoEB5DIVl56ElOM5hEXPPjYvUlv0sR2mUpAvKRu332VCfCxbNm06oqmD7BOP7
1x9DipEvCHHXV/kbmV0qjRLcBftLtUBux0UoGPqEfxlg2Txs7nFcOci/RReVKZxn0YuFatBmfv6Y
9AYahekvpCkXNbm8+JWIqlt6+GmqbpdBqzGQPt0yu28cMqj0vAW+UFXPEFmYO+t+cCXcPpCMbVbV
fwHKpUld6hORx84vGzQuIMbvJcwKlEqxMcf4bQ+qkkn3kqqbptVvSeJ1Ipl3fqbaj4ct1oPB9bkD
jGcrqxza8HQDPXeDpNRLxx6nxKkOFmraU2YpW4WhS/PEERVZBuzCcqpKXQ3ZlZ2uHGwim8dKHwV1
+n/RjZOIkYcVoOlhcHx0qTo6xTi6J6g+e2wLSw95mRfvEq1BxNuTB85O9Q+EkRtq0TRU+LoSqSGe
h+AvUbJUft7/M2zeVqYM5vo25Ue1KqH0P6igo+6YUPYuMq47plii1u5061yDJfdaXoa1Sd8uLtX5
bYhdliTozCdxFtu+7GERoMnYaThw5suqcs0QcT66SOm8qO9fnhLNPWoch1JVzELscCIvwTvg74Or
UvLQU+h6ilmHs4LkROIRbTBNLEuzXgTR3LrTNAAaz3tv06cTdHRg1hYPaoAF+OvzBnzXxuwpmDfT
dpJC3hb7RlAcCO8WKYJhuMvmLCqumLusMg6y0KDRhdG/JRcYUtIblFjhNEtqXsElGmn0ZCRC8YPu
CUDGQzTWABcKfSM21+YiK7QApwzIoDPZy2dfJjMAbqukjgp/QfLV1h4oOJJHvU51BhTJ2UIbvVc5
Sw79eQ/5gd1ZNSLMvwChOqXzEnFWIRM2T5z8kWuwAh4ncwPQJpAKSCEycoawQwx/pk3LuN0Ebtrf
8c9HjwVWjUV+aT5tklMH42OOFS+f4rLJE930gDPUN9yaez/z7DCqPKNFSQHVKMedMjpkBkGoEm7Y
zKOCqlfFj+GALcs6SO2NCN9VFUiV7h1oZI88O7PESuXjaL3Y1Cx2k4q55c57tcC+WT0PuWkP/f75
B0oWiFPFG3b1oY95nG2cVfWwgB/rY4zA9HlSa0dMnrp73bULNiPFQCiiFo6bfhjmdqp9GCTFDSUv
Qgwu6aqiYqC6IHNwHXuzk0Ad5UnbvqVZ1DuENbtRA2sr2Ubu5qxtJGR1kWnVsRFp+pK4z9KUjPb6
96+jq2hawBXminz0i4qdG/99/BeMS1Pj/k6KNQnSycMy+ASnF1/GwWWL8I/6CiDD2ng5L3ec0bWo
VPiiiOh8vdSx5UTHdBG3ithW61HHGZtmgzZhF6oXpJNPE5cjN9Fd6lpMGjzYfGE0E8EV/LOm6YyM
j6PxRPom0FoBNYGzkplcQk/3VvnXlYjPgdED7Qutn3Km6uIb29su8ULb8GAey2laLEAZDwUbD1M5
yHvxJ+klboxRtIdYz+tkVjUw0MfWCcuYzGotMsvKDJATc7jE9fJRb5ttDyRB45f+5KOsZTu5DoOy
12B5a947bRJdilSN9drC9qb9hABf9vR28tfgnHPF0AWopkhQac6xDuuGYqxRFc2K5+5TROY/9lL9
j00qIumGrPul/kNWDoZPYgEmm3Abti5klUjKhznWRGobawjBBHIrcMgCv/zrG3JyhpE2Mh8eBkqb
BPzJ1oOcxUiN6HPRUXf+WJD7n4bKRu8hjyMF864ebX55ZWcdIzQvHoxAIQ61grcNvyFxHaIzyUqj
2cYimYZqPAo6hCdyirWf4z13n/durv1uVxgFh+5/kWazWevRD1RDOzJYDWrwptyaM7cS6q22XTVp
jyYqBCq35rlCf0VrY4N3XSc/v7T43t2/n21C3DZuSb3MbCb2U5XdSph8QDVxIbV4xn5kwTyQ2JER
ApD2BcZVYGW/lgROyi14Mm8Q3ufvXbIDUBLabuuIdXT1/b5MMRWpSLX6OW8uHISl+urVDgbVHP40
jf+caJCX3Hn07Wl4QhemVu2uyit87LQ2OmFHyrLgMy+cdHWv8iIYqFrrgizruo3A0jOZuw7qdBH7
Vzyv9pW8uKy0NTH5T57rzHxO88+6Zt5+RgVbVjAZwErgS3d6O7OyuW86NWVgqc0N2PLRHmZh5Nhf
lsz5yqyH67Fx30CCxk6zO61nwB+wBWmAdW66uV7N4GS/W72aR98557W7dp0z3RfsO4G2PzgG3ttk
j7Tg1jLMD/HyfiR8WvRiXPUhlqsvvrzRPo397k8mitOgcGJ5eFLXMbu589amOJMt05kDIFEQUvIl
jEB3dxE1hu3HOiy3LXWmI7a7vuTtsnK1mU9EUfAcryOGKKbMaeR6U6QdjPC+XO4RdhJ/juC2YsjQ
pWoEHLOgveA0z46D0Ju5IHDUfd/KtQPtzi1EnID0meEXhfVdY0rfT2WhwOf/PWcWPSrR39tqGGlY
Cp+ex7FTI8m0ASRwzvQwzJGxpeyW2O9twgFttn62XrxJjWvsHjHQjeFsvbsYumRGiuJATvVTj53d
N4LRssbGNiLJ8JUZdudc5w664V0IUYktB9kcykedzCPPb0SJbbqqVD9Q7wyU0gTzHsAEcQEDQTg4
4HDZm/NsmxPyz7+aM3FJHPCzdQcfEDCFlLfSxUK4qqggmddrmRNwhC2ef6rpH/NnuloY08S5r2cP
toJzP08Bq2iXzuptbNbDP+h7QII6FkHrKvEbGeFFEsEKtjwi1hLnQhHU2lFmeAKEZFpo2Q4ShF6q
g7FqeeLXNs5ZkCNfXTBA53ccv9dXRSxU8CaoqoJ13kmwPszZqV7RKxs32rsNJOqVISx3lZzPhlxG
FxzuOEEyr8cGdIBxe21OHG2T5pCNyWNXNTGNxPFX8O8lfa4jj0JeiN5rUwsis1a7W5r2QJSbPMy6
UTcvYQo8rmOwHlr1y94dFKogN3U4BZbV3fhXitjT3yhD/xF3MM6gjOARFs19GgZVyOXOQqJyF2ja
+rOkguJo81MgePpiEIiwBPWMMBa2PBLx+1PazhhxK4V55QztCqd0ErfgvLvl5HXlCmFdcntRhY18
xBElfErrtBPROdFI3SjXp6/e9/zJpFfQG+FFhpdh6bdiu5l2utxxxgB0BWvdnmmEsUPEjLmN1SvP
anxw4ut4apAE/dtOPPwqmQfqeiyI3tkKxNCSzz2fhM/hUaNoEs/xLIfG54XfVGmQcRmKgpkNLyMQ
xBoBbqNU918A3sgbMmKSQmPQqdfxnqBDJMoke72BKmfdEBU6ku/Cck19OJBzRi/RWeMsoMTPX44/
pSXuh4UG4BOXmxzN939ZwyJv+9hYE6cP8KzkaHC6yLiak38OKWYUkWWmc/YnHWsGYbpTHQpAUZ9t
VCF/vyhNL6HamPQBOlbj7do/T5lWbWw42dUB9HiiWBkNIMfxdBWu5vUF+2uFjaZ0GkUBT7RFgzX2
y5DWNlG0ycJomogXcmG7EP8h+m6kD8EB4pzdn1cLnp8QSEI2rblzi3j8D+aIRI1HSXRmitZYJPHQ
zRiQK7ZL0fob3w/Crr2FHVHZswRo59+3nN83fpX+CaqJMvXsD/hnSR0250g4AAraJ+5upl1qqVRl
A9+UAfyhII32M3RU6gl6SOE4CLtXly809Ru4iGnw4V0XXMBNQTXAQRE4mZ8GXZqexGyPZudjUqZq
VnEKOOrVRlV6oJ0S9xZQfofi7XHo/nZdmrdw6ab4diXkAU/8eIEdNxCDvSVDhpzZ39tZEfaesPVU
mkahrRm4bB4/Nm6s3ijedMe1HU2wOa9DoxxtyCAb6xON/XVJhwwKZFHYaW0HdUgpU+eWjBIQ+QYQ
MaF8D+RU8frutZb3/xNhm1cN5PPoxiBYKAIpjtcSxnKn5HKlp8LYYlu/99htMNHmAs8VlPlErO3H
xethceVqvUbx4iH0k+Zp7lAsBBvOJn8LtZJXCQ2FJlSOhjAmVxoKD6KMsz5v4Cb6WNqlBBUjiXRw
+0LYSyQ2OnPdMlx37AeUTDM3W2UfUUzdqj1PCPRV6XD7OdlbiN/hp+IdVLbHUMu0+oGAO82wcJQB
jJk6cTdvAdiEjmfA27kK02nsAlOsxufLDlasJQF2IOQo6Mp2Z60kfnAnlgFq1LVBgl2rH5yrOZAy
mvNMgQZK4RPelu7IW9la/gni7CTBl03pCajBwPdJ8UjgU+KblJABA0l9J36Qr4tMxgLkYBRyYnUn
iaVKP3eTH/+2hRCBC4ZJmp4ICTnvKuf43rT6tEBKZ4bkDvJWPcRJ00lA7iGLYza91crEFKChBSH6
QrJFEq2ceWuynjv0TRE2hhbJksBqK4CdQJhoCoUzrJ64X/7o6VGWRH5GlPaUEBu2QLdbt2YydG/r
7DgJT4dG+ngmxGaTwn8WS8lKbBGAXy5Li9dhdugiOaqPJT2nlNDRu0L/z8W3Zd3ZZHQaWTHiGUIh
Vfnm1UfCJSkCaQ+cyBpe8cO1qCNOtqKG7ey52RLR3mS4yNr7kJqfriOMntv0hBIXlYhQLMwdgzxT
GCjgw+yaDoVG5qT8/tHtlNDIV6t27+MCDMFcea/wW7us9VEDW1Wm2vURid6PcMdLwybmv0gpGICq
1r+tUGuKQ6R05NPk48TwWsTNW2T2b/Iw0Swa1w9BqcaHPGWnu90KdZYI1L3kw7k8vt2KjzvDKDlT
da/yZqmNikKv5vO9yGJPfcoHPd2L0Al8P9KeUKyROFQuvHdqSwN7d2kDni9umxY5xx+ErFNHWFcM
UGFIzdtu5rkyQKNtFWMe95UjiVEwjr+TD0IjLZwdH2HR9k0KvJcDBqb9P8+3dDCZUStERkkKXAIx
yTiWuliC5QP3FH/dVC9QkX/s1GAYB+IS6VZVEtaQV3OZjJNJ2x1x7XcDPTeNuU4OZQ2YeuNa18eg
Lc7ro6SaYuxkdaE/T0zkXzlMuVm6lERh1kkc4kstZKBIfoL51N4Nvoatj94OAjCgB3T+c34r7dA3
XeNZryjYAYazSdvy3wXz+I1A/FyGZLMwqjXygFpg1LlG3AVJQtibTYVwltx/nSqPwqnA0uKkc9QO
FY+pA1F3IjYfaBklApF/jmi/1NqVvv+B6GONANRt17Cb57kKPevQin4W+HtFwMWJn53B+ph5ioFy
QEB/QWHPw0iX+cnTUyNzQZ/wdKxM3PvGnn38rvme/x/wtqL74vmkYOdsJBmzZa+O9y8MbeG2E30v
+9jts6ruud4qFJ0Lb7VEIB6ZefOt7qSZyB3aiAHpqJx4F13pzGMUwaXJooTGi+dHMH0rq7WW2GnU
2tyYpwkNlK78JWIU3ABtsyMHIJ/eLrMd6FkDr0lBhBHNr0ZMCb30814pa2HBtMgsdElEWZacDh7c
nTGGA4K8qaoND7ZJd6KJptgwvNXeGESaqdZoSJuGB68kgBWY4iQYSIWbMiyTkkGqhtBBpU68CRkm
sKYJC2kEmWWC7JVZL4fBkF1Hzn6KtRHEEBkJpVD4XzsskiFeBhNKH4R66IE73drZu52Z1xIq+Ix4
LfGspCNVT0ulF7YSMaZRKrMCdXx9TWVwRUv1zRfil6seigvfz9+NZ+1u7r1fOJiipk9eekB/6ZK5
iigkIkPcIO5fGL53+r2k4QY/gx8336YlBn5sk9NNxxL8DZ/UwrHjy8HX5ASID/qG4/nccjH63qUY
UoNZiItos1pdcrwUldPD0dMC2VB3ttygqcd9BAywfNFjB4vLtr3B3WmTEPNo5uMJHmsZIEhvv72Y
63eBGjNjC+aU5VPvGHJPMpWi9DTfgUkLHQv4gZ0wQ2ncFeYaahXYZbV38A4pf/n7SjE7NHsaQo/B
tUKwOkOKiyN3YEhzwF2QPbE4QngR2tTfuZ8NBnfouXLr6jZkMFNc3ByOEU8OuVb3BI2VnHT6cyO9
IPEd5ZiL9LAKpG2NTWUmCXupOn+CBEepyzbWc9o5ZT/pT4deYkI2hzfRwlPttj+oo3l9/eh9MUAE
o7ODpombkYx+1AnJgc5AAlIYgUqffCnCftaBumolKH4QBuEnneyVo3vp102T51woa3AaMIbtV2u0
3KwOHH3IlW42lcy3fvBo5RqjX0d2VuNtS1M22S0+RdBXCC1H2eTJXIFa+EOxRPs6NT/hfYEEfk8A
StN7SLJ/3Hbx0M31dqbnfmcJoemVjReFVRo+PFllO5Ba+eoQHvFBHEuCLry8Stx8+riI3e50y9wJ
BfjivWpx1wjdJ72+V1XUlXSA0KhRWm05ex/Yh2aAizrqsNOzVK3hW/jVWvxWWhLQEyp48WxQPYCo
SZfHLf3CaMMor/EPSo0yEbL4k5nRUm9SnH9w76Zqm4L1EXkdil/3pyR4X2eEtUu8s1uTdEyqFdzB
i3i/tJgKgU4up5XALaYqmqPwTmJnndZFCCmSaouyssKjquS02x+5gsyrOu0bLj6ydNSDExB0HnnU
POI1mL8nOkag9KXf7EvEqrFwnicySpCGzjZjNXKNV2Ao4S1d4+BXgB9nS5ObchtigdMFsYWaOqUJ
PYbIqgTObTHVqKk/QFXHfyx/xR3EXwDIUs8+F4Q6cKOJwYCCiTiQkq/h9+zD70YsRvpGJFUgec0c
nVFxry6QHbM6v3bJmBsNCCt3VhPgqNO8wTE7ijVEsEOCkYKunXCaT3XjNI3yd7PiIa0NM8av86le
wx/Sx+89GR1KhGvIgSNjbJACk8tQqFQX6Gz7fCAupOJnfDj1+1GVWXm3rTVZ6WT69ubak9coMNjU
XlabHK0tdOQRU+Cy3Xo0ILSUfBGJwpYyfZDZcTmoBNK5l3WANoGwCc+vyQ+VJgQiuT0u9Ynd+Ztw
lJ+JAsH8rLCsNC2hkVPuo1Bw7Nn/K5eZp8Eboow1S0D7m7cxBltSt8Z2ZsvnolW97svNeZg1fsZD
LixWUVSaFKqjmfomfutOrqbkXYBFpRrsD/c8UGq5s3FWxp2/jwU4DKaaLSqMeQgnsrdirF9Iwtr9
w/6xO0QY/UiNvGjwqQTIXd1jhUCl6A4IVB3EDzWG8PbaPxTANodtsCgAgPSDXHtNebvgr/5/67VY
2sY0Fxi68MbuYPttSU0ehM0KmDGkcSrILUrqWdp/y49NSfD2t4cGmm5VRVeg4yySD85uXKJ/HugV
UjFDeTrSr5Cbg+hcsF/M3TRvYcuW6MmHzPUz+V9dj3V71yHjqSgW7c9zhGJA9Sr36RLHdEqYYhLc
ewl60CdOzx2+TsI7ooPfFE02lkbRCsJYtQw0WqkWdBb2+zkaa6EWlbMPNTyf8RYkIYYNMiS1v8b0
Ol+ZutYaEjQiU0mei/7HompWbK6p+HNh0/NpruYRaUepbHknD/1QYkm9nZtZHDz6voZGIsryQRka
z1ItTDmi2CHDfCX1tdsqBV7vPw34VuJx1E/YEWuzsiavozFMih+w0pdegOkJLm6+u3GvsBxz1V6g
A+QYzJwzi/cqwQrO80UWKTsoLo0sdZHb2P7aqq95kgTvdC9IeT9jMQR72R9aDh9RaLiYDj8oYRkO
X3Tkm1nUl7M8+65i95k1yCMHnb3qZpikChaktLS3QW3WBGJ6gqM1My4GX/Fy9snnpUVtWLnXxIjF
jJ/o5RLaoCP5zOha4etHOOjvTz6Fp7TnnHW1kXBKLnEER/dc8B7JPd57zCDqmHofL373r6VNv1Vt
lgKQ5vZT++YKDrhFT+HACeu1R28j55Vs9OtXUWJffcGL3mUNmMtPvenuTmgb5EeEOy4DBhH0R4fR
LSRdw4+V56OBIFvWaspqKevbqynN0pMwRaoVFtTD6/nkz3XOL8fnHHDhcj9Sg4IhJWwOmwyRWp/U
nimUyTqMS+gfyrTzHZhc3pYuEIgD4GpPmR3jI0YVlpWaLbny1p/oLKS1YrVEJ3ILUYb8f8u0BTRb
A11Eb2NEJhyqH6Ifzo3l7c5r12c3hC3K/9lPLLVQG5K+51ZfhgF6D+ct+7MW/z+VwrlLk09qbR6Z
bJ8Ug9CbL3E4R7S5m1+4UrM/b/l5mbPhN1nuv6rFL6s8ztKJELIMBjuKdmTse+q547cQ7p1QQnhZ
Gb8nYRaIArIVEYqOHxUWPKgmabq4KG7yw8EArzdk20Mxje7zOwWrPjBRUHi7p+UWVbfKM/DhKTxI
jC9/ywV/DuvMZ7GFY0ylKpK4ds3dpEsyL0MpkV4gvMvHrcME1As+XaQo+eML+gwDk+D2rgb/9iPC
gR6RHHL+h4OW8uRUDuGVHXKlWDvInj7dr3ZnDPpsUYoo1scsPb4EaeMXeSvgnrAwYivKzm54b5dp
Kss3zirqI+mAYGtN6I2fFxZ4W1fx+KQv/oGRz/8scfimL6ebAGZi0A2TUxbt+bI4+Guv9LZ9Gwlj
AunXkQ5VSvQjlYJugn7JihUk/sYH+VdcPmvDSq23bRYA8apgYsMc+hCvAl6qU5c8GLAAWwAo815U
RSoVQl9xJKG3GnPUfwN19uhuczSDZIG5fr0ovH6Cc3idOdp1IXGuz0ehgsH+tlYk3B55TLFb4X3h
qv5IG3q2PiYuKewEy0Dp9PeEE5s+rpi/AAc9zF6vssSjH07+xx0uC9S276A4jRJWt277cFq118Xk
VELQGb+4CVyULbZE55Vv2uZRjt2WTaQP/gz6prqWU9PoV3jmOa6N+Mnh/7kQ3c9Ahd8qdwn9fz/a
HD9eftuYgcFqgtres2AEaCdTYA1EiccGuu01ct9q+nfCqRVpe8T+bN3i+dyEbUioZLwG+FxjXf3m
2YnSeROIK6A6nB6hiW+oPu8mVUCsL5FvpwsSSmcMGACkhkmUSa7m7yHnv4r3yrO8hNqC9Qr0OGrd
wiC04LrjO3lXIx9coZi3o9A+Xe8WuyP52MacAcQqrMALC01sgT1QIsSEl3PcIGIdYBXiOoPNZnoq
yLrsrUJOst6aUf6M/6KX/L94QPNqNYwKRfDQ+ExphSLYXlWzN60eGoTHNSiYWehYWeSLNKAenKMM
hJrLC2boMRsfqIbP/sjjxOGoSOy+YTEQ+6/fF9UtG90wy+KBCFd855C0p7qA+8igvG0/6NN4D147
TzN9jIh6TmB7mrGsBLOvpReDl7FAIgNwgeVBMiTFvu9h4V/Z4rQZQa0gpR2IkSB1lpRlG9DyZU1M
rn2NdjoP8sl9S6nKBJpcu1QYucstkNxS1yFuKasYDrr2oGEuQ2Cqf6zJ55vZxfCVOdhygfZSFBAo
z6hq3SNY8/uNhSlLPn0Oy4/o6jAP/qVRbXLRlYbttGUfGRIcq+zpkG0VFjUh3dv/EEVxiCIpFSCX
uxgpkRs2ClzDhfTQ0l5Jr4EtVFaNXCe5Ileynj7Aylt1b6brK7nH3Wc9mrs2ZWOshq++LhCGHlmR
VzSPdF5k2bDABw8ZNsy7zJXwYm+Z1wGaN+C3Bt7eiyVTsKOX4u8qGLSQsgXnGDcmDE3B4QCV6RoF
Dhowztc4Ky8BzUM1KzU7sfaMw36ml9xikmnkhVVhRNlNBKrRd+88VL4GWz+dpMe95y7vRZ4nWiN6
kv3+n3jFb5GXzglGipS/RtGA51Vt5rVUcZngLozrjKTPL0cmgbQCKFXw/wmJpuzUMnzuwTtJq1h6
fZhB9FJmE+hn8+NBs4PMtVKgpjKQe1RxTBDptIpLrB+8KRdvJLluZ8A1C/5qFNifGNkDCd1M4Wkz
ya5Az9IK1vDnOE3USbST+DqZpbQ7BczR1V3itKUyoT2YrpNakSVrYJC4quevaeTocHodhJEIi9aN
oRdhyW9MoCZXDVdrQ3neFOotPiP6aBm40YN/9oc0xAwLLMOkpI7EBnQ3piZOep+oRFMi/RYldxEB
3TIIUp1tGPa2z3/f7ETN54SPaqCMCBp1m3wsD1AO6l/O1Q+fRpoMOZHUmt3cbuZm9wXDkedF1gJK
ROXs8xHcnn92X/5LmGkWccRw86CeUmAjPNW26fml2gA5kHA2uwbuzvcCx+2BVVRLiqpY5vIv9Y8c
rKj2+yBPo7E/+sv5NxhdiahAatIlmPm+2tGRaR3t0BL+XzJ4NuS8m53I9Yfi0ZpJcMu2s8Umykhx
WMK+NNbv59QNQoOjWhIRc7I3cVko3OuyJt05pB4OxVxQ1ikpc1DJsZgKEO3CVNs1rFdEsL3vg1s6
KpCjijqDMA32K5OWe/1DvfwhlGVX7Vq+PuF0BhFzf0bJ+S0bHx4nw4bpcIjN/v3keWt71Bbmz/OR
JeQ9Qtbx3glx+rlEhRyAHzWR1VSI2X5A1Qixq7hfqS91Q+GdJHMAKqUwgi6C5m0GkCkx7lrREQAc
BYn4y7rcUXynj1wN5QWzbe+yhBJ+ks49I57HCZnNSIExqNaStE35RBdXS/0YsZbV5mySBm2mG1bM
4jObjV4mOuDgFMmB8dr/PfXgp43tt7ZWZsTdSOxLRQpFlKrdkpx2Saofy8ezcwQ3QWyyXbZPAjAP
vR2nqMx3HbtwDV0g3nSoEjy7TT6H8oPCkZQ8BjZDDTWHeY+Q5L5sE0K2smiPnyeiiqCL2coRXlct
ZNFLP/nzDzwh1mlzJ15p2sBas/uttC0OGCFsqxsEg3+v8zeY9WYrB8nj+m9klrkdGhVHqxgtabPy
iLlulUMprVFzW8sRZo+X6SzMqHmkOT8590bLWIoRagVzbchwNX7IFvbcprQJNMPUiv2mXdTW70Tx
PkBJ6rZeSEi09LCG4Bd7XqtrVZm6hn8UNl7C4IQpGP9frJZA3uW046fKuJP56KrmMHSZQF9ne25e
W4oWBM1mFphMO9fgh9c5SXpndZ/uOAbcYVM4WSIe+3cOWQOLgz/c5aCN39Uahsaq+zdOCYiRzkgh
4LAsjTYWb/l4DZ1fqya1YTKuc3MwcY7hLUuBzDaQty5BwHN7ZwzcG+QELxIgKA+l7dBiqGfHRmIT
SWkiv+R2fJ0Tm0HcOdYVigTzz2N5unN7BlAymOjG+ZFILimEtJyFeSeZGYvmiMdjAHQPouUG1xYp
mo6hfBaza9gEa3RR4xiMMAp9jlpXrnjcSRNeCACyLj0GJia0rsSFVZAxG/fEuQFTkEVeJliIa/1X
VhmWDilZmXLCcHM2K3OD98VqKhMeI2/nypDDsOD4FkyCWr0TpdQ+cVep2yf1HLZhAQtSz5UdMAkO
SxHkpkMObsPG9AnDbNpRfAoTq15hN66kjqXHh1vXuD1jhlqqTqEqCVs6mwmim6jb5GtgwAkZENJF
CyTODBsW5zP3Ex02qfRUHA0r23lOPKR3gnqUkrQf5IRTz/FWA78X2Y2GBxK2wmCCvEDhI1fgzolx
6yIRgu4JUsgTWckUTSCceRKFX6oBwvDUQyiI1Habhx/a+jKN2IwcUDd+iYyoU+m9HxLq9z4AThqt
4DNL0moU01Wn2SLRzjNCgUFNd9Nh8W7jGR2cWfNRumEOSUDVaJC/2H889qht4ZSVfruVTj3BKkmA
6ET8qMoDcNsJDIZaUlk0+MfiTcDPb+JglPFKCPNKEuXgbujuZAPUFa2+QoA1eWXeSK4XOquNtxKX
qOCedBI+qCiyG5n+JLAmo+mCKlGLL4ksHauzCoJUjFbox9a1kHHY3PvFMZhElk24nCi2CstyneGT
0D/4JyR2fd7nB0uujj9Pvd6UY1p1zaL1Obe6pOS0Y4efxuDRTVXx+7VBYxgNhlG4Z2mYXx7U0Ge9
0jiEYzamlcfRVHLVzbjriAmZUfhVxdw0bTiY67VFXJan5tJ7h/f8CT9jVPo/3MinWFp1ICeIkodK
Ucxq10VV8qgFXEtSq9zLeAjGWy53GEb78GGPsx8+4Z9YToN7JLjMlefcZaV0KLM1ASPQ+GB28K9V
us6jphIkZfL5iIUv4hgo5qiO5ksFKgRd7M2VQrP4Vx3bGOjvWwk/Wtxri2xokDAm3KujC5J/PjKc
dCUcpazCHKegW5DcVUJIeZguaXleLwAbIe2Dm/Rsr+qNVzMeiO5rSXO8PKQSu24YAPvnpAhQFKEd
c2CCDDtpPdIcVUVJQBk8km3gzGKHq6RH1YS9ax4TLFeq62vw+teLUlzViFybM/qkXRhmFMnblxwT
xjYushKjB3fDGKgDSgp34KoN88SPgnZdGDmbgfLw8cD8sFS/5SbAINR+xoWF6xbVA3QPl9qeobDb
O3fnrA4ELM91a/fUIs4aWxmyZ8An18YSR+AwsGZCsajXu96vMwHwEq0qPcbNglkJ+kYhaGmDYSTl
R3lkx31s99EP9tVbb5m3ypbJbI+Zagjb9umKbJorkTH/4fpAGs3qPh2CPmcmcgFAEAW48QT+y8DE
31SgTJNf6XI42hYexAXvSUq70KQiociEoFBR1/15om6yWKPtGKVR/aEtoHMNiOtaSatTr9HGyoTQ
t/Yb09gkbswaoJmtEcbZPyyUfUH0X8GY6h9gMa36jtSzzCx4d70DY6oUCOTsbLZY3XwJK8qhaQ8C
k/Sv9uujYpfGfOuiwl+a5yYUzpnAe40KU4nwIIKqRtCriZiwFRD7b6KdpUzj3NYQx2GZIdso10nY
I/vJUVupq5nhWjBE3W0eQCRkhrCUPBZ4CJbsji0NskGvInD2Rd7DyreUQK+ry/tQnt8Sq2kC7AQX
JmSiKyjXyyU987Ro6C55E6y45Xber2SlI0rKrNk7B/JG45XRagzufl55OlrD1HQSdy2P8kQ95dib
U2oVR8scvJGlf7+GlQNsQvqzvuGbECG+46t0Pvzi8ujzy4IAV3IXLOLrHthnM/gAXwKsRrOKn0kO
gWZzv7sxIB51eodkBeRsU0IFKdpfJbe+rHXY9zjCBO3rGxCviVsOlQhP20R72NYx7EhrF2cUP2PD
ZfO8icyP7z9gIN7kAB8+GiiPTgRQw7wqX9dIVE6ax3Cc6UhJ7uKgzirlTrIVg5h0pwBADkbH6sSZ
9p+WeGRczAlXmJOI395TCAHK4koxfALn2M3e1RqJ0WiGJblUUNQbpZuc1c3pxFs7kH6FzU5WbmZ2
lDCj+We6b4Q24E+T85W2U+zg8c2dtwfC2hsx6IwRhpqGjcuVHxvWHyUFhRwqJT68UsqhR85454xd
pDqxq1AyJGxr2/8PS5bdKmRQA+xV6HxyNHnMA0ZQs4q9AeQ1q9Z/CEtDFegC0z0d22cYMw4lQncv
URUhiGKUzwO9t10+jL98f4152TN/VGZPs9+tHlN6EVqksSuc/wjtNZkpAJivOHVQd1U4q6P5a0Bl
IkL95LSN77wcpQtol3FahE5hEHcpkLwmtuJWI44ie170OfQ8P6Kpoc90lvTG9py1pY41rtAIZLm1
xI4ptWCDkvt9P4Y/y54v2/k0xvdlMFbuKWIGQUGGDw68F78NAgW81+qvqXPg9CHHxEX0c31KOShQ
wONoFqQYkNzREoD+2gU1rH85pMYtV5Ggvk4Yt+9cifxka7iD4jnuTzolu5G4sciLFLuKrFP/zajd
HcRRE86ea56qMZMRzJ2k9hgB8SqT8Ll1tJ3y4EwUCf/Xegxihmqhr4+grBZpXs/Yf1zvYyfE4Z5G
xUD8WfLJER//MPMq0yF3OVkTBhkA3MTfR/TK7WWz3T4D6sJlrX4Vj5/dBxrhe9ycnNc5VrfK8K/y
5HwkRCdo4u0imwvmesygiTJfLfIskwzOmX//tBV2g2rtBNqKHk9CuIsmi22V5PCAB8busQ6Fozq2
jkfQmvbukxML8Xt39QgYJpYxa47X785Iz/wX9hD5hf/+kNOfrHnXmffr+Up2sQHwC7D54zcn6WLW
qYIQ6Q2JJcemYPPPIRECMgNleVv1ISQEhIA6K8u9GZxvqGwzoRSm6EpwC1Q8qsvj6hkYsEAp55jy
hCAYpDcovqXAik+e7TPd0mceXINXJRP72Ppfjh1l9YmiNVOclcWCTQB82nYDnfFC0ZDBrxg72Ov8
rch6CxlNPG7js8U7c5R1oXgCxS6qvrXPg17Qj6E1ICfVpe90jylPcN+FpdJYm2HUySP8d5bYgesg
KKkV1qwupC+WV/qD7imznvwwL6wfSEDB0GzodVp08+CdgoOh++NuHi/3iobuQ1l2Jlv905m26wnv
7TvrioAk6YJaBZrw++2ZzhXl+TbYTd8Up68QJDe8CdSdARBdheiFzD5ZdfsRowTvF5GvlbyYyyFW
9hJfAQBjrrc13lpvMCfEhEnhzCkM+ZhC6ZjHxyaEB8qnv3SGJ180jWFYsBZORO2CLp4hZO7lgAVW
j2rKqSOAPuS4DPhdSvzWCidf9rUf9qPj05AIBmtWvuZIuX6pduuvj0F9cu7ZN9462h6CgYMbLSu+
Oi788EwXwjtchoy42EyTPoe/g/CJV92XoxRWlDToyX/k1HmCS2yK2Gum6zeG/ln6s+TOmgi0e0qO
IkQPGvPqvyH0KqZufVeQLWB33ugRw19SC61p2pn6pVjVN+iDvhpINYgAaunlA0XsE35XdE/91w63
+OfVbOFXsDE2+nB4azfHJbkUqs8HYO+z3t8uNSBXX+mX/fx9LOmWfR3pBzHMRAP1q0QP+D7CSUMw
YhBCNI9sHIAqANYcdn2FzewPv1jU1RKfiv85GNx64768bNj7urg0PwyOkiYgEgMMKPTzZUr971WO
QC7zVvsydXVXZyWSePZMuxTDeVTOldxCc1zftOlUkEmGXss9PRcvz0oJFd0tXS0AYTHL2Zy0eqjo
DEb4C6eHbeq6dX2o6fbSFdTz72u6FhYRZt6fSvNnPVduqHyxOZ2AVjWdXa7AR+y/F065fgeS748H
9cFYEye0Qqw27zpW5BL7I9Mti3i2ya52EqQRrHIbezv2enE+IBSMdektyTcMRHV07wCWF0Ch19Tf
MQ700rhmWVPSrWzwainmUyGnmB/pMLS1iYePRhXBycAYqilZqCnu4kfYNVdxnlShdxeU1/z5f6GA
b/A25BS8w6FUsgACY3TZXnvUXMzo6vNiYhVDp0opOgX6dNNKlXe3oOHrbYS6hkDuZFfouenKnF4A
h2VKXa69l9d7931pBPsw4pyPCiqP9PSV/yBuEgznTccfKOHjWiCuOClj29o8Lfs+62MsbuUiNa28
MPxEIL2oN5iQiglzRmXpkb97YHrafndOgl1fnEyDrg9vNe2YujnmmyONnjWyzhY5JJ/PLzlAZKJv
A9/wTMRea57NpyxHOsu9iAdnRGPAX/xBFRegUUOY8487tjB+wmET7mw8vHNWPup9h0xkiK7/r1uw
5wBPQ/g+/0skhhCBCeF8SEhIv4Kqv54zN+HPvBq/7rOfs+CW7wd7eI9AEDuLwEOlFhLQvXn6z2+S
0Ij4jD2k3X/oANV0RedZoPLor3WdbPVEJQMvucaIEWi3Q6DKKxDWpHxgNUE78/BIK0Sc3TxLyrZM
UUA5SKGvJJ41DbYJ4fDtqI0HIDgTPbj0CRgbWqRWY/omGdES+aWp90kspaMR8vnTf/X3Y027qBbN
mhEtPTpYOnn6nVwEau6eicycn3EdXBQxkHl7CS/lveUJAWMNi7fn3d6mRqlRdst1k3NpkZoEJjzX
xHSFipxRFnps4v0ePE/TxUDdXRB9ZvWLqyQEaKekemE3iLCjctvp0sCPu/+Jw09zA2k8/nNshv6h
8FF4tsAivvijhocxan0Crr8j5InoPp0DtNCaBMhfAFUU545ifEcgI94KkSvMMBELViWvmjaajK8Q
OwQFau/qLIlWMnQXs6t76aal66zC2o7xqPv+06cVBIifEnOiTjbhYS+sOtoPAbrOVGMns5GRo9wG
js7V0w6MXNme/Kk2zB8mQ8GVxei1kBylH3OVVwP4Xe/JC7s5C9L5iA17YM9cu4x6gmeC5EZ5Mn8i
/ZYd8mdRXaFKdHKIkt0gNHsIFROtcstepjonJ9uPY6S6JP5YCHpw9pU586OJUIy7WO0eDy8NbDew
FQ1Rq5QM3okVbDFrxTeYcxDGoanV6oI8nuGxFJjqBB+ysHXyl4MoLkv8WFCZYtFznb8w3Wr696+j
/2nDVjRIuRaGRVFKln75/OJ9V6SOJN9w4bYdb2hklugyT4GmR7AkJTgZhAZuqnYW4oPfH6jKU01h
XwSwRkeZFyF4cqQObwwehcLCMHeBgC5AqZwRFl5RFoP6lMEzTEpC0ZzgxSnDgjCmNhcGr4S8rU42
asm7NlfGJuVuLg9FFZu3+5gBm13qD7yABfaDPXMdgv3wNYGSE0AMbtI0etqypMiviHv5tT6usq+i
91R6dhAf1oM1TOsPH9L8mKumnLHl0Ma7GWnq3Mqfamr6DZYTEKn9v0Zo4n9ZUh/HoJKhclgvwW3h
tQW+L7GZ6np2LUka99v/6TVVE0yX6fFjHA8aYX49OqqQvdxkF6IAdJ10b5t56FWWFVMDdWjYXJIe
aWwxhxu0zQt+c3d/jCeu0M+uWfez4AUGj8zZfqWV7VFAfxIuUVTC1m/uUcb6OKnALAYpPj1VS73N
m+ajBmr0uv0I3AUC4ZNzozi2lprOiBCaTNj0IZlFj2LAF37a44aktYSmL+qybabFi628P3+Pyc+B
lAbAVKvbN0XIy0XEIXm5+2UX4ItagK2STNIIy8b/BnryVRL5ZF289AlY2ShIO8S24I4sjWhR6/iW
ToI/3EBeb3Tt5Kn2la/oBFfRR/z+lAeD8jwBh0Qi/UjQj8IsJStXq0RtO8dQmHYKF3yu6BjYkmrE
LKGkJK/KogH5vNIK8eDKtPG7s9pZKv7N7KY0t2BilDsTGD9bKRLgLakT+PdCMOuxJd5VS4wrAMo2
FMxUz+3m9ZDZIqZb3H355+mfeLjXRXi/L/0cm3zW+ecfm66kqo2lQmEFa5CdZTiA1MCV662jaQ3c
oId+dtWDOJMrd6ZBtsej1xGwfrZdHm3TRwYAW/TzPrvGAeKs5Jsu/9tPyH1ZzwztPZcksglM6v3S
92QuLIoUyq5TZw5K62o3nI1Jc5JgjXzl8JYhtsdbM1201v/mliNyL3DH3uWFuPvQH38QgN7IHrVw
ZYTvp+jWVH2ykDMl0Mxa8NCODvAoKi9nWY7m28x85Ye0t5LvnRD1pymCdkGmswtcP4FPfe3GYCHa
GHsPBJD3vx26MuqyTdFDLHZ/Q0yw1196sEKLkpMvtugA7VNMa9KUJxIoqLgwrCNIzd7Nme4pjilj
XFWqZxa3EAWyEh5N3gIEF//6s0Zl2ncAavd1YWzy0Dq+RlPXJ16FP3ENkDh5JXWntfzAoRdbM6v6
ayd3U0OgxE9adKnRw8PoSoun0jhRwpUayUY0yxQNeypSIG/2ZauLJXE7nhXwK+Lo8ABngEA4Ktzw
v7Fj16UHq1KTMf5R5SQlNBAKosdp3B4XWmJjjSi9V71TmVXSla0Qum9G3wNMchGiBv/7mtoJmwyn
GYEnoFF84G8yY5Qq56uG5CZeeyRTZ8zCMtJ18atBqWEDG0FbLxsS01fZ5jHM4mrncVDobYhcc3M9
oTQJxJcHk6lp8oPqfZu3Lyk7hShMIqoM5FdfLnjOJUe25LF8lmCYim814R255LQYgdIb6Y7ancEL
is1S3VDTvsZoXNtL2E2S3ZCwvWekfVMVNI1HfouMLBo2vQ610jeJUq8RQ6dZBkHHOpb0KjkqCm97
MhUubQkvNVfp+of0APHf+4888jAyTFrDOHOTof1JokSwfhEKGMyu2nIZR3BVImJAD3uq78Fa8TUn
owZWl25qy88aE3GOtUexLMVv0zsVjUHE5IEJL7/EiYjIBlaxEyoJuxtMizveJq6Cnlr1Tw/anOH3
btbBvWqbSFlWv1VZKvnUx95B1frbN37IW7Le3KWB81Wemo7gm0omI7A3ZaQ4oh3mMsytV7lCYfhW
xblBxsuNp2ImeiBCuuBmSKXxnWw93jGUCbrkSXstB/rV8xBC5tJaP5jteQDSgt2fgIfHEoe0M3uZ
XmMy6qwweoYufzpAQ96GSK6AdckKaVKa13kWis+IQ/uZQyxtvKbo+g+CoRBqdNlaksYwsdxN7dB/
plnr+MxCi+KMonz9RF+Lf3KsIuyfzkItQSmlOEYWcPTXPxCy05VmftjrxF8NCt8Oq9bIPvTHSKQ/
eoFvnxi0N8mdUI9HoI2V7QGCI7vlkSNNIYuxTbTjFMmUI7Dv81RhNfrMw5OqMsbrQwcJxxj3wvba
h09th0pwYdkH5WlJonHJuRDGcfZtVkFO9tcBcktRGtVyHRqPKW3WPOhlJ1CRxT1q3rm7nTuHdaoX
JS3SZn+f9LusJGZDFrs0vUkwYu03wlvWGu4Lr5L79L/o6X5kRfqYFAZvyz0XxWQ1kq6NSLndu7D4
Uwg9IrpKT9QfYsuyhGiyV9PtOAJNGcM9stxR+ksXcyL3SPGKSRl4/XsXUFWui4SUMm1NnPkEfmF2
mDT9U54uhlXtb8cqLB6ZwBLfgdgT7PPFNlxKvEs5CL6SwqLxuUNn5QkUgtwjLghZi8TwbE3TWX4B
yfSAsI95TtQh6m0kh/LlHxCqOO4GclfJcpvqY33il5VgQkP7BLkYD2wTHK8RZkqXUq8nrCCTKlBK
L+e1bPyerXJ4H87S4mCtuUkbtEJOT2gY4LFg8CBK8FR/bk6gWWC5na5obQ4te+9eQhbqoiBs07rS
iu8RkQKgc3cdknhM7hgZmOPoFgOvEv/FmQHpMbU3yfEmJyJC3mGsFTapvqFOTZx1nhPsZe2/oxOz
1M2D49Fs7UncbHZ6e/0o0gK946eMVsGYbOoB3/jLKLFf0D2rhlsfeRbiBR396WlR9QXHV7z+og22
wLB0thgMpS0TMvermjBmkPUPl3n3Q8868avqZxyA5uJRvPAASHvXty4IedETyOtMs7JrtoQc6jFm
2//LfKacx/IuxFwAk01NFbrpCakSjJ327TRGKxXhpfvntTVC6MaCGg7s9DOKpusxorl+LDB1jLdy
mdLb2JFIULscvpy3iCLyOXcFfA9q+wgtxEzGwPJlBmFT5buocW4DO9Jq16ugtduAXqc1hExZLxth
LdvnrkIOHMX80VWka3+fNclFj+HBeH6nsa1Lxkjzw946N6KTIrzWFMhjezNrpPaAsd4uhSt/Do5v
6Xzcr7IdPtsn3sS04cvcRQ/2s7db3zFV6yv3jizVcLCiyLSKFb2wrMjvnS2WguhRjn3KMGrOzgjb
Oajtu1nISPL6Kd2bGUjPoQS/rG/HJDtXVWJm1er89Vu5Pss8MoZQoojZuuqkUlCEhJ/DDQbOxkJ3
Ggfl9rS++kVqLX6YQGbVTSxayDOxW9x7uuAFjZYurUcCtAxHk5fHUd5pXLXB6CynvNdFI20KTLZ3
eHIFRyoTT92uJ+APkMQeroomwYcFDkxlgkHmbordW1RPkre1rwlJbHrWXJ7KDfNIvfKAqVF9s1n8
38RbocQcUcDSiHpnwuMUCbQwe4Aic/TWKDjeEidYZCBuX9u5RcKnuOhwjuUALmk0NtzrxOSQBkDx
Tx9OzYhGGOYsxoOLzaM4B64D7HZ0yFan6QvHZQgO52PQqWjubcnw9NQNKRxcPB/qr2CuUY4Np6g6
QghAVZL5c0xIh+DASQ81xGHcYYO+xFxsbDdJNRrtAWifyLyx3WLHJm1xSxajTQRIH7eXkeklk8N6
2j88OUvFe0WgEMUMCAgS14w4n2zybnWnRA0Y0615RLenrQmiVU3icpTtEPNZ9/x/TiWlzej58Go3
H80HJw50YzvhUaIx8EjgdQtN6CarZ01EGxdN+PKMABW6WXU44FmAJJPcYMlAMT7CjAv3QNHTL9T1
rnoIu6FjdqHvfVGvtphzVjcncBfqyhe1uPaBV+E1M8cUI3e9QqmaRMbg+yeH9u+qqKhEOtqtUCOR
LkoP8AV2/cXyrPlaT5XVaiE1JrjED+t7wLjtixTtPKeCZaDsBpUEHGgDcQig4yNAaXtWimGECJal
JbXLyDsajDcQkHAq1LlVFlJhFXGkcOIWgoU7fUIvtec2S5/dqrCkhc2Kq2NNVtFGyN4x/xstugGg
1kiFaOb91c2aximvRO1bePnejRcf2AR2OMbqI17ynv+MjteTWTQds71AwTjo9gnDa6RKtadafMjk
jtHgEKS9XCl+s05E1UpzFTKROXnKqaDCrO0cb1MT0qITNyvH18Z4Cvfs4lvY93AE09NSB8a4YqHQ
knRgsgQxH8Eeb92E0ivqEBUHm3crV0Ih7hqXOdvd/K3WhNre2aEeQqc9beXyK+UL8s8VOjfT74Gm
mxWqdu4TJbTCj6Qu2KAtVzoGVcZIE2R65QCpJHz5zBQvL5rdxwRqPH3pcgO3nQJj7S1xLn0AB4Mq
ppJgH2XUoIT1QTJr2Qvx+Syp8p47KRLWPRkJ7vKKIj6rb1nm0foUY3OBrsgOlM8qzWr3oBXAC73u
gEYY4a4ZH6kakTbn04TmgP3bID+RiUjFTHo7ti5m7E7btSqury0Y056QgnGbJfzo3O4MDwm73f2u
4o6zGq+ESmk1z9YstONZKsonCixcQoIQdz7AGX3EGfasLzM33kOxhdasoPozwL7L9xTBK20Ct3dj
I9QvngBJusMf2ZV8J8o8BGUZLgol7ylzKm1icaA55KCb3LdXapQCyoTJs5hYTVRf0QVZSLsIHieV
iqkJUpjFJ4cfWh3GxiSxFz3D1CK32d0OCWia/vLobNMfZw28cG2nJoYLm3Q1OkrTVIqzkrC0yMUs
W+ZpUy7rgYwBB9pza+wSNkQh0gfg1F0IX9zdRvAr1bZ9IXeN+MmjJJTVVxDx+tbbA9/ZeU0jYmTM
DZstOiwUUv3PJruQb8uLyfYP8UL/e+RiGsFBs6K0Wi8HpE6VSM52TcnGje534PjzBVhvYKZzvidl
FGIArU+gXPzsbm3hYC2VeFZRrlWAKHVialDyksqfdg1VggPm700VOaHDGo1TN96ssIGCyOMTpteB
GlA8huY5aP/o6/hpF6bI4CqTKtBLIzms0Eaw/robm/7zvuh7YE4TU8comcxuqHjpXyWFXy87SViL
xiwfYGqFPAUWurrSFpa8/cGLdEtaVewIK9J9a6pU1VNfOnaYH6SHBidja3INJ3QW0aPs2VdMgNPk
XxYJUoqV24EZ1NsJRsRv2ITECd3tCG/YgJ2ce/uilKywLj0FDGduQ2d+k0AsEqN734tfUyzdu+yH
WUtxG3gu42rk+Wv4t5zWpfsxEJRIsVLZYKUvGJC2RgTKXbhCEJ9gE9Kn1OUlGZo95cl66MDk3bhz
NaJukrJzOPZL8yhGQNZnMQkhdeKVrleaNdq3nRebA6sPKTwCftqCwCibYjalf7xr8Vc2s+Xo5who
00RZUi45LrW3jpmPBlhNoAxHr3BwmvYYaRHdnwGZVWCufh78eda3IyYN5q2H65tRoQIY28ZoWmxz
Th17PGMS3mdOro6bAiMmdXTXdeL+vnDTZXiI0pxq0ywtS0xbEMh8N7Gi6ylQNwRpXPBIt9O/LCek
le++PeCG5EktTJMeLFdRB0pwfAGmIFy5cLgXE4MsHvo8rOyFtBfxSg1tWGLZE+BYy3XBD9vGX2qb
48EKbsLi4WPfugppR+J7lrt070wastWyykZy+tAMrFc5Y8N4mN6cd7mhA1GvhS/lOfgJnhSntoMV
9r1oRPug28FHjAvlpOt/Q29TsVM2d648fW626eUc0A6479nkQr2zIsKrTY9AjSXO2kCnNqV1N999
Q57q2Y0OFut9w5YzlZMFAS306EaJgFWmDSU7lq6WHeKT04XXfAm5QENSFOocSZ6ogHEwDAZmOZ4q
3ufBJcxX45ZduUS6tJFhJYkvQbYGXpYF38KxVhnwVY/Sz1OpMfrL4w+0lI/6oCXuAzSa0HMVw+t0
wGxC6Grk1nIH8tHrMlA41OQeIsAOCKI6hcDt6DbRlm57yQNTcf+c2baRSwnsr2InbpQ0nHoLTxsr
zqFmWDj/QjOru6QWnqaOvLHJpbmLh9P65BxVL52Kg6u/MU9ZuPsnM7jMejay2q0kuZ+th+2RzyJc
OW2T/GYoZdlYZjAG/NvLWUdBraRVs3t4ErLxDFoVSQkAD8dJ+HRSPrQwmtYHpllB/42m/oVhYmos
DbCyx3vH3cX0+zI0vpGAH4Zo5NKrLtuG4w//dbUNFCVWLt3H2mtWdHW5ygGudIz6T0nwqFPj6ZBk
fojgF0OjrXVuCA1wnhoK7MC8QbG0Afdfi5imwyKnXuZ7BnZ5BPcj88JFlcHM/wRVIIZ7CR4eqna5
crJqZVj2GOgMfx+nq7gMPM12U0VyfjGaLs3FKyle62+F5s8wNpopTrgoj1wFqr+ZwxVEmL6Mxwd/
LkmusnbZr7WhvGGuHWXpUmD27/awDBzVyvtkccVZ5VDFl1Tslk2j89YvyxZOZkFPxq5sk83sxlXk
ov0JqanH14Nr+y+snIzBQ3kVrl4RcfSgj9wjS6WJucRRaXw2/aax8/UhV5Pu4vqitzJevGChi69f
pBEJ2q6+rxQvZfSf20XA6DfoD48/m4V3ofTuT9UqHykiGMBmLPxkyVsyeeuosrmw2Zkd1GrORvlp
4S2x+0IHfzBp28Ykd7I8b6vjLp1MkLLGuPLJ5IYL8C5/S4rAyXsuTRfnUkMQ0GPnPS5O/EyK2hci
qZ1JlIJww7ePu9aA32fznjZMWZHSAV2NbTrHqijeUz7kMpV6Xtqz2ZCWsqv/qKf7tZRNdAOMb/58
JIncMUCfKJrGNyh00xs3y/TY4uiuedjkW4ylNArTBM6OmwZBYDWqVV1qhjR02+82DHk+LOHAZrSe
wpIXxCvN7o/gGKT0zTmlfLOL11u3jZNMP8fBkzWlbMHwspfnwJ2zqb9t71xSNiVHTLpMcEKMODbJ
LcvW7CO0tDpzTooRPHl4REDILA46OuuJAORPsrHxb7mH5uPShllVcQNyPyvZRVQFbfOhNdoZ7L0Q
9QvrWSrhFdG6iYMgSL3n/EVjjoaeoa2XMPDf3ST+1BSiDsUjFUOlC4M1jBsJHo56fQ4kqE7Wubf+
TaguNyLF3dvnmClE5X7Prb+tBhgSctmFYndul++uMZSoXSZZQ5hjeBOuUKhWGses/ikMpWSE6Sq8
94GMHHVUJXngWohLXO6z+UDOIM6D6SLMaiuhPtvRCWdz7Iq84mfYSonBejK4FEbpwVRglYJ1dsVg
KundW3wa0RV8tr5GOpgoMmgY52kUN/+cX050tM6JT09UcmA5adLlUaXNlxrb6VIZ3SWwpBs/kgyz
3Oa2OC9bgWDYVcKdIR2XL0HJQfv/UWZSEge+trNk59dzslrdVVqD8Jv32GD3HXKuKRH1Ly1Qo59z
kJNAyMl6fyT4PDwR067ctq5Vv/PvNgTunIFadz2gYvUQyBEc3K7xpaYRoszK19gAZt5tyBTDQ9yZ
t5UuiK77eaD+6X08oCrD37DbdtF8RaKjEZ6zf0Py1Ps7k4eQAuaf7yWK++Vb3Bos4j70PUyU2gZE
hbtwzXujeLyT1vlP5Wt/s7Pq+5ZKaR9Lbv2MUpUkClsTjUr/J9/tMyYl6flV1wkeb8kPBTMPMFEu
oFwfCA+lwxMke0mjzEvEpHDSWBGzdvYRTLP1L42p9l4jLQapJyOUf9iLfccJdYBzkTn7wqQuL8XE
l2Cxdsx6vd2V6Fvye8dsBI4En7WKPcKQDxIh9cw2XAqxrZbiOhLXdlLD2emT1RwqrBHsq/GC+NQ2
TZUeGT/zCkTlpDKJ7PuQtr2/kzmNZxKiR5pTszHGZAvsHK43V3Mdv2V9PKAxqg8x0YBYfdDgAsbc
EZvJowZc6D/lM1XQuu8VM41cx+0Gjz1He9yT3PhI9XWRJoMlR9BH8YvExcTxbx3udS1ETj6kLWPO
AFcMthZafr8BAD+83j3U6Iego540tGOCFn2u/OyEXiZwc5HE2pyF94HtGSDQiSctA/wblhAYK4s0
53YmdKiCaDB3xEs7QgPlx24u4iUNqjIsvhQgQf2qsOAVSjjR4kpvFXyiJVhAZcw3yH8xZKJI3fng
gGYI5b1HNJCt1gErtUz7TXcLCACn58DpNPvDDwU2JMcEHrga0gcLeI9nzu+L0o3PjwkQjZmP403/
R+rB8IVLLUWCVvAa16VPJOH2rhfpwS5V9mO0Yv5Y2er5GcH23uyflDl6A4U8Fh2L71vGXktyQjSp
nmLzBL0citpx+iCmeZxXlE6J0/rDiogXyaY3n32+P0OengrY+u7oineUx4SqEhDg6rOnkUGT+0mc
SosYZs3gtMYjewh2PuXH+5IBiVrL7dZ3Neh9lF3T0hWQBovdONqE4uipGiE3JeC5q7BgnJQqcOtr
LI25CpwvRaRDncougFAXq0ren7mc5ZJNzB7NtIt6Ehlrf2K0tjFYfFVNUDlQgIIutD07wneF2QJ0
LKCcQfFbXLm74HW1HiyG4tCn19R26/L37UoFiKqlnuWrZgXM/IMDFJulf7qmiT7dMaU8489s1qQN
rWewfTtrMNvA76ob0ruzk/23XDMiddLKPoWSfnidALD+KGd1z5Wzc0ux9E5Zy23cZylMhowOEGWK
6zh3ONVT+ozYy6sIdeA6hg4/QGyPyFT6mP7ZxkX8vS2Mn7WKx4nQ0hZspVC6YitRsERnmuRtjkXD
g3BPWKPWyqqTTSlxshji4mN9GwNLJy0EZONchEN2gq8WoCzgDQA6PDSgjDwsUBVVuwCsSh8RBYfa
CLKywyCC5Q9ipXpQmf0rP9iNlZeHRwWBtmvUalewzQPARjrZ01aKlHELUNsV8JNa9nKL+2wYeuxE
zPNUt2NOoPWeOuvlq+0js35DHES0s3ltRt9OTHcF7Gruh/63nzZVn/bUGEKZ/NcObfXJAzCUB98F
eK+c/TViwz0bhMePPejI9sfMH457YpSDGTvKlLsvmYhINeD0Hnr1yL9Ouet2A8LFCRwL0AWAByPO
4M4tjPYHWFYmNnaXSoJo32Ejn0DpEMYXHE4+3MIyNytAyUh/ZnmGBTG1VDNVtDA93q5xGW0sDZc+
gvlKDNHr4dBVEp6xsYQiOhH4reUOsao+Y9FPxBwJQAA6KfO4f/stybMO56RbnEHOm+kxbOCj4Qzn
xvQNd/RNTmR/um5gnw1GIQ0VYUsGmELk6x93B28ieQp3g+hNUtDz2Vu/NDA4/jqU8Y4RgOJgcOdJ
mPfwDmkWFfsJ0z6gIHmhVmfJQeIAalovckxvV9jY8gbt16C0hqKJuv1UynIHVSqmH8rWOVKx0oPT
iBTzC66elVwYvhQxYbu5Dt4Zah4KWDcCfzNHeYAXEhOXH2ohUo/8KIMllS4AtVmRBeHtbPcY1ugt
DFc/CDlfB5F5IQJIFnkVhfggnktmqFT2tJRyLmJUs8lDxg0dnFXoNB+k/1FGyBBS6Ha5C/q2QOSv
WgepisVsb7Bvhb5oW62CSaYyYo9a/SFCcvsXaMWobDyI9YaZfMlEs4OVWBhMSQMkxgCM/LlV9Mxj
k82WDI/vz36XHunorORJ880rUvMxZp64XvrNtOEa02+7ct2FkNzbFSEDEyVDQ/EzXzC/KA8JFssl
8A1S77hWbZHw5LPNGBHBAQByK4OCMZuRghjAg37C4fGNV674ZMldBY5JMIcF92+jgbFLYPrcLeTp
482tDy/zU3X3Lp0i8P8BppIn/rfloLjeeH8XtMGfpNDhF5b78SclrWCgGuEuKcU41m0osWWnXVFG
dnQSlAysC8KIODKl87TL/eNW7twd39JFzKuqQcDkIeVy7HjV4pP2wV/0x59YCccAiD6DOp8ZGsUf
Go4wTefcte0qm0v08rVYObJ+dLBfDtwZlPhUTvwrm7l1WoOX1OG+q0VuNLo6PF3KYx5X8prgBlNp
HZUhy5/vj5vKxufEdiUAPXldUWtNAwpdgwoMM0dMeAc0ZVgKLwscNYxHYgpPAahXhuTIme59NfY2
s4ktLA7E2UY+rypEXA+qNFmEiRe2lh4jDSt/H5N+VLp1NQD/+1SziqmTX2DKXO84XJTRa1UUMQTE
BGyd1f/FjFePoR3y/rD+IBsuzsQfq7cgWHpStOjs7X/xLOh0HfHGaTiTElY08EhzuQzhDiBx7fOw
QfT4JJmyRMMq1sWHQB5fYOAV9Tkhbo9ECtGYAHBSy86iLKOIIyD2rji5gxGht1etwkPmxyenTYCz
Xmq6HSc35+KUg9vJTY4tzDz0KchPrAlBzII1zLxAatDkdpGRJPmziYZCtXelcchuTH/1YuTThoJ7
f0ZdD1ox1jMXJFFYZFIQFYyHZz8hsLvcdeI7D0QANYRmRT89K3N3KOAP8Jd7Y96RTXjiO+PApl38
RxIn8V5M4+wfc+a4MkbwBEsuqXqTtH2jVvQTOYBTa6oYf4cshW0/mMkppFXndHW2X74Q2Dc2OljZ
gyLQ31M1p5dSkbTvmi+Rr1SQ42oaSRFQ8qDzzlQ97+gQP1/q141X17jvR4VdkZwo9g23xKgQlvM0
3AGJB9r5kXGzXqOHqco0//NS6T4ZtlSBQ8vUzhTcd8AM3dBkn23eQS+7hSlW14p/h5uYAlpGA13j
q7O+04S6Myp+mbmJoG2SDjQ/zUHjFfahgKHCaQdU6LYzZ8/7UD7eRnJCMVCy4vL1BaJHW5ONTlv4
uBXjW/mYtcEC1kcu1QRXiMaSIOMW7H0C94hBcbexUwLLjz2ZNFIlKHD8iMK/ad5EJ/TXb6kbrId1
pOEY/2JCcWJsLBMxZhv6VcFui7YJ0F9zKGNb23L2JFI2Z0fTkgqs/UOGTQlZzx07Cc4pw4ZHg+4x
krw0EYgD+P6qE8VGoGkh9HTGW6oplcRrwtrtSpctPU9cy8TAOe8Zf9XLkfgyELOWNBviANFkFKj1
zVSb8HHUOSdMlVHdSyBR33SEvb90CSFVTQWgfVIwdH+NtAx2rp0ri8w9Nq07lCDkZz5+CMCJlYfZ
6jTQbeu/uWGKZvH/BaNLF0viSZSGWIAHgMaUA/LVK+//cJlmU674vMGAmBCC0qO6AEIP9Ouaq8+j
u3rwUxlBF7HSXAtxoO6fwWXm4vm7d9X7V4vyv5TejMU4X+kDxlo4jMQrjvUEgRfeEH41DPQfKuoU
XHEbEzJSqb3MwPly1m8QT6xHOsfd6MYiTJU6qxyQlbz2rk4RH/Zp5s+pFq8e3k27KiaddXtbs0Jh
ny5ymV7LV6znxPlh/8XrgYa7samye6vRgFHK3rlXRq9FirxvKyz53BaA3WQmy4VR2ijnw46DawgJ
Wc4zPg6BFdX/L0OeCudvWsItz6WngnhFvYx6aCFxxL78trzIeMhbxJsB19UujB1bXKgaxcx5EZh3
wW8DuEhloPSLiN1ovvYeX+mC/Z+ZlZXrWDLFcV7Q9aB8X0TFcJAPJvdHNxO1v4cnqWpjqKL0AFzD
zhjDdFXNdOX61qLUJX8qCfHfKZraDlgqNXHQCMFNElA8+RzrA2dwJUR2gffd5xvrhha2/AwssbK+
FWyxeA9K4kdyJoP/AXJbczOIKMRq/IgHpt0PIIdQYXwLisJ+ZvN7FNdAh3G1xQ2nl/8snhm6gw1O
k4cgsj30cj/D6Lbg+OzM7ocJGDnT1Qo0sYErs+c/KW5GPXRLycskB6xnAoIFq1JLLvXN1AVhsUhl
DJEvt0eWCwvVtRQ5OFcarNIO+OBaO23SqyKWKeBhqcWmTAaPMpzE2PBldrl6VzXl8G8UUtdEKaNg
C5DzRGgSQbnZR+zmG+/iVVtOsW9or6rWetSzyanp2gEG39MgGmtOKuhPsMKVEC2b6iiva+6BAm1z
ijb6MVLhsTEHU+U5A+kkXlh7tgF4qsWR8S5jIuTRxsm47QFdFBccR/isNkJiilRGmZw4N/iX3Urs
hzgvS6twm0cF+WGsoebwfb6j0gQIYZxluHZZQKtPb8ulROsGFLVLSrl8VnYZSHSaRnFag3gzVg7m
Mm1N2i49m8+rJ+wU53r+GS7bFVlbthgMe4QWhjuOl2b3rMSxUB3211K9cyLC4lKr1V7njLqSnGLS
95RI0YnxVJnKfb8c/l23xDtvvnIuQ/NrwtzPrYGq7F5zedIiUbF/9rAmeR5uCSccKtYGzHukW9F6
RUSICthZ6p3SeQzfMsxcu5s2BQfZlPpX+2b98lsgZG305dv9MTEyZgv3tdpxpsR5C6fj5P3eO2Gg
eprpbQe3GFMRKfxhoJBFj525EUCXPqIUV029/p2xC8ZAodQA3pol5Qx7VQNpsbOLCWZ4VPECGuZb
LnnKS4TKaxkazcxhlHwpsUNrXFhbnQ+iMxR2hp3b+poeFUUciCjeJer2WyXYFPf6EAIMa7KXAwyN
3y3kNgu1jnxHE2wNUVX9D/CTlZjJKDLoL9jcH7T4eSSoVZYzWd10ki5gXbzYVLutAbjj6YijzVhS
flQI/083/izwu/mDHVKALIggPl99cyxdg/EmWP7y+PFdo+d5EIgIwQFPFfcUILb4CeeOELjyENaM
SUHAdYCt81FCad874yBdH0GG+OJbx/ClcEhfD4+ZKvnGfoHeSvKO0PUqEU5DheipXz23RQIZZz9C
BRIH+i0LPAFuu4h5IZaCBzWxL5S6Jz2k3ndzXmIu4USenPGbKmQ14QafdQqMZYPdScOfO09+YODY
DOAYpJN8p88r9P2ZW4zOhrHw0WS8mmfYpJQvJZVqy/FPzpDpYP6EifgvG4raLEvwCSql94+pFi4A
11ZWAOL2dfInu8ROS59jutFXNDoguYZNiY9gP4iQSt0R8b+Unok0+eyWp8x4DUGSAXROwku8embZ
7clF6sOUZ51SAA0yDB2Bj7BO7ZMBU4GEIs5dFgfsgfYUO+RmSvKxHx3LurT0v2CSQ0GQ6Y/26iYT
KlAkafSyTDAC4G0xX0ekxrAZmx2wDVrFRuu1TRy4S5JHz7QuReP6r74UHpXh5W9ZVDW75Sd0b9tp
/7CgsdoaNnYogv4xmbPUKBSgQj0xT6eF2DfOTejm7J2qR085aXPr8uafAvF6hiIBLSbwZpEwzSS7
UHBQG1cl1Zz659U+fMS/kbq2pFUL+iZulafjfxVNjVu1q8Cw1h1dqzpoIkdNJ+qlaDW9Q4GB17XR
kz9eXJ6fogV84GOhBWhw7nCbhI9pAdcVukq3X+e77LhbxHRjdC3vs4wVbe1Pl2M+35sccXENUaHX
w3MtQ+8z6/TlY0RWObw45BgpiSH5xWuY9VirGjP1aoSUNajuGiPd3zuaHkwb7ud8LNyITz49t1M4
M0QO2JoajemH/WaieCFjmnv5yKBTdGie+jkCKqg3wsQSGd1H7tL9yeq/mET428mGha3xZbK6SS2y
/W07hT/0iaDavW4bo6LZ6AuOhjy2V6yJM3u52evZCDKlTZ8SnadgX1MnQGkQy2lz0QYJbJUfPbO2
1ktzsPlDAQSLP09eW+o+Xb/lzZg0OMIsoPjwjjUvcvsYbRwVVPlVFjmB5u4rbbpVryJdIvwHg04M
WgdYSEDryIEjYx18dDNFV8/grdhB2KfH6p4NS78wKdlE3VMe6/TashF0XsBmYhRcfcy/gDnRaMO+
kbO5lbr8LlVXp4sOn3YJRhKGw+eL+RI+D+WIUGQ/oMJ2wswCIqO6EGRlMo8JOlT3bLWOsGZ9oZDx
hJWNvEkM74f3rtVIc9v8mEXcdIOX6zulLtl5GyenA0hWuobOVLkxyK/R4Jzegl0ePh5wzKPBXmS6
h94Pqddn/xFEOlOK9ztpoa7EE0vomtrtqKmvDqGZ7+gLYVduztjNL+PYoB36Cyr6IK2u1dVwK/52
JDBtROIThDZPj/tJ6WF5t6q2+I8QiufP94Ji8CmXoM4aIgkDhq033FAILKemv8E3lWb29nQwg6U5
CI7737rOlmxlo43tf9aDouzrbRO+KtNDr2S6L9a3W1g6TRZ41ezQLoi1GGZ7r3lTcWw5XpIcc7nX
kxfNthyGCvTjUKM1vrBpOhh0FAWn3P3gTZmgVILx9xvg1HlzZ3PwKCYZdBhxvVKwNTpOsLtjML0f
aCVXxxL1Uufd0XahCPI8BFlKE5zNc3YF8OIC6QzeGenbLCuxVBIno0tCYKvUisFWmOFNXJ+ydEOc
o6MfZXLX0YyP1pMDT9YBmoa0RMFg0MNWiGqzv7mTgYqXADbEFz1tnQF0u9Y4NCPboC2nasuXJGA7
87xdwv9IauY8ZULgxchNOPp8NCZ9GDFJwwEzpHfwIE3v+VKW1Rn++7bPkU1oKn8Z8x+pg3za2q/0
YF5b/24/hspJk3S8Ll5qTczSrZd/4285K1SOwRICbz5G7jIzXy1bxcq6Xr3TrNpk9YXhklQa/EPd
nCpSTSPPH7sHy+WmiO9cSJpviAiK9o3pbPJ6rqBGgHsXRoJQvFP+3ib2cx1aRdHVEPclapXwxue0
b1O0hgs1BcD3lRbWVlIugtWwgUnB819JkoD1YpzHLdJgQ2UNsPe28mZeBEZbGUDS7VIYUefbog+y
M9Gi+lNOY9tTvRCb6eghS17kT/UTg06tckdd+BlKwHmTFdcNcWotTiNABf1pFahZBbe4sfzWKpFe
l0gqxmcVnWTOqBXq0vsywnphG/20fCKrVs5pAQWMxFJzY2+QEqioWnhRT7vR3CXRode9YO1iAte6
gG3hDEGUywCHyNJ9/6TtSp2LUealLvqo/R3m8NjVXofixzwvMJcX7o8+P0q6IzqGWh282n0JEGYI
4h0ZwASUL7ij/6zNxWlLIPFbtcqDuNeLLkUCe6ddKcgmjG7JBFmGh05E26le4ZkTm+QJsiRDmnzN
xCLstMYFXN/GNzec8go5cWrnXX/zYL7oBNkt5y6x6zqwPw1kiDlIQInajTyZHWFehLZaTrY8uJUJ
6vXl2CVRfW3c1GKsMq//i6Ie1D/gblyE+YmF1Q+YlSNVPEsgYVKah+tcpk6waZogzRSdbNtTZIYF
pxbKkw0KjWSCSgbnmrGrgBod3K0PrN3cMgQzplcygC97wwQHD+TkIQWNEFadO+ridDuI/NnTS+k5
FXc0/9S3aCsYU78J6xSFYoaDhXe4RenYu4gChs3gCZM+2gAXZ24ttGAyVnkabi765pO+Z/ix5dS+
jd90wgg6K5BtndBelrmU/2aWLJ5Udi2oZlQiJ2lrqy/gCvyFGcwjHp0zIbhHCky9Szc/h8LTS+Yf
+rNh5TAEj3JBLOYlPD+95JUKR0l1oBvvLoc3XK3QvDLXjpYr6EteHlhmv/txjYpx6ER9U5FHCWFT
bGSov4fvZsEEH6N0HDN6PrXRkfv9Y86CLXyyZN4hYIMN6qcZ4hI4N3SmPHMEfN7k26csa7TuZMsj
Qf3vB+jelmQBPzN3ts6dQRn+CPqg6jbQA6lR3xgPhV0eQbwJ5wUvwKJAsYOZImowl2lwyVgrZ9Rr
ekOMI9iPxATz+nNCV5taFhdVxHnrfWZFIdGkTXjEh4jMLrfEvZPEgQE3eL/ypSm0a3EX8n3I0jWx
7tamnH0x60ij40xVQzHMHxQXrpjYtVwEM8mjWwEG4Q3EwLBw9R+nChIl7AB4qFoFt3WiJjtsG2yW
j0MyOJa8JUWteMN3Rx/2W8CZIw2TL6hzZ474nYoYlvjBAsp3Mwi5MMJR8/jPl7a+xzvOtXMI4h7M
8JltU6qZ3DYLfJfD7WUSVeMQ7Ae3bRxhnq6lSUhzUGr1sTDpikDEpraxUwekgdGoeg1wau/L0Lh/
iEVbP72uDuLawQR/rDXNmTUDQTXC57llyVvPqZzam3k8dKpLiO5b296rw5+M3/4RzGAmkyeBEi8s
yVOVwxbdXMwqZmjGmNVNj5Tm/RLoPEIqnp9p+M3wTwDqetBCucS2No38YhkV5wXRlwHl6s8l489U
2YnYaPhiIzfQ0kfTVjwPlJjE8e0BVlGfQyKTyccnt/I0dY+VTVbKrPE5OSiOssajWNoJ25xoB+Hv
5EQv7Z5rVhmIMpx9gsZYpk8fzs+VYKIwbSOOxaLmUiS2D4pacYpCPDRC+5XsRbCZb0d+I+PFLiXm
mv9XOzD1tHNbZpjMnRGyGCStqjXuALtGHX7NUdQ17zovs+ppm6tE2kkYfMAkkRJ8M2HeP45UCMxo
MZS3mCsbl6TjZBoNSqBBIMHCE5INNhctAcDzl+AaRkXpmYxgLm5Dm0ih9flZCe0RvVVnW0Iyb+dP
QUUrTUuXtK5ZXDmlZeXoen1/Egp8S8xTl+OFsdwq6RVPBP8poEkqj8DYvgCVpcnUQXYd3SimxGs3
0IYSLEHWxGGwtFT2bY5QyDOTETVJVtWODwkTyPxQsp2mFsAoPexXGgtaMj7CdBodAlvYmjQUhcaW
RT2cXQmgMwFp62xzRG7ir2IDYA0CJYnN87IegOKa9BVPjin1Y5Rxbnrs3a0UONix4fSTn49OTnil
7ZwWmcJmMo6MBC1XpviF9q5Q+3zBdWF01ALxh7OQeI0hxMtNci7OeXj6/RvZQa/3z0Y4SijmUpfb
N18dDI4iyK+4ercMRndSeqGFlx69R0+qXwBsbE3saYY5KNTIDNg2PZORCv3KbgrGSigDxxZsf3J1
FPGwb1jOMSQtAhnBwjGuWrjhb9QJttWZ3boIkWFGMOrnWde0DzCMH5CSLecUCDfOwZYb5e3GvlXV
bfBXx6AT+zPalB5Mo6F6Fx/7RgMB+Eycs1kdwotah5lChq3ErqUi5Sl3kNWE0BC1t/ofHisntgPD
Zfv9rrg5XY/ChS5SmNKf7iJzdV2eCGsE0zvcmf3Rt19DYnJzyFUeUIvT5OICyhjLjFpzu0O0YVNO
GxqLcQ4dKDQ0774qV2UAmn7BHUkG9FNdc9QfiPRRiRkZHhmEfpp+THrEEQXOjPlVVfER9aF8Tg0q
vWcC/jV0rpqLu+kB98F19SASUm2k41UJRRbdu7TvygjTthZajuhIys1REHHhLB84XwnNX2zLEt3Q
TiO+AKs80zmHJC4PczFvstaBgq42vuv/zkRPuD84VNcRL94zzdVCXSI2EAdMTsAF4b/F5s7i6H8Z
fAlCZGo3nJJ7yZ89b4UO0D8E7X4n2dFmLRtXqji3Ex9KFPSu8LCJCvzgx6xSlgMLmEovlM/C2OEz
CTLAjOUou6JCPF++VF1kKJsDumMQ2yr7KRztVgAzimyubfQT/UufNy3Ayw9uQIW/5Xg0idA75D0V
En7B5HSNaVBezOs14xtIdCavSUoZxEoT0mt8v7BfRIz2UDCj9P/sUnfAFQe7UJvIjMnAyaJ2yiJI
trnq2wktx4kzaZHaeJrQX9nMCKyCINjedlW7aUNEw7s+xzbq4MyOwBo7tnQ6XUeL1yGMUk7uSQ5d
pYgQq/pXP34E7AueoDd1KmvcH0tGYBeSMro/WZX4xOaLJGpyqoEXrT1NmZUfbslkYpWU+3aWVakn
KyEAAWtToBttGVLibmWOVSDwH0N1jB2fKuZ6TdFLvfq8fe2WSBUdTyzKlHad4Bk/xeX4ywSdC7X7
pGgmkKVjKqqsvSoXv/C6pUPeQeYQhpJhjj5XhCXywNe8V/Lfz1eOetoRno6YK5yid/fAq8cy1Ka1
OXUoT/8oDt3LK5n6rVBB9l6hpCPKKfNc9u1jXIB5Sgg9soyT82f7IcJ5lOxmjsP9phMkTVXBIoUT
KgwnL+H6MCD/lPdPBpHKU1wv8dHzKEkLiMJYZCiPWKGx1eLtc0rrQZmpu2dZS1ANiYONENpD0tFD
NXkA0KF+hZkHIWVi2rrwO9MPjGeir0D+LRrpplP/pCF9Gk5Fa/qZR+KXa19cjz8Icw/ksv1UJETe
i2oyfk6n7wIzPhKW+URhdmFh1uS9dQZs7bTJ3UtCO0zIUcgwKkmEAw+neAu4bR4L2N5t3Iu3PxRH
8IfJF6ISyW+qjvXU5mxxZUZkd43Ib+UXcQJTpFTJ+YlPCwRw5HU7bOJofc5FiGvJsrZt+dUTJnnR
5rX4P9yQBO/0me1IC9FtOBRuQs4sMDAnSEQ9UcUErP/Iq7YykqMb0uC+Kj1KEnj39/oOSfYHTsf0
6Mq4FzemajCmeSZvXthLnVy1NiDBCpM2xRBixSg33ds0CZeFxe207+9nCB+0QOo0tBc0hf7PR59P
WGbzihR9FnnzKU5psrqa8HDYf5G4dEMZHNwYQwfLyYSaO2BTnudVNGJsCrxLnbURV/likQtFwhaj
U+p51h6sZpNq/wybWyxG3ZtyvsGdqdXcB8+jC3iKbPPC9qQPKjfOKL8+xMdeym2dlhF+hXfra0W6
0GOUmbI+xURWUHP4aj6Rn1XH1b7Rg6iLSJsrxIO2u3p+uvZa/+hvm0xFVQHZfan3DHkDlufZdOC9
v4tD32T+frV9YFAFI3EzylHjqNfyLE/xURRVBrDPL3pfZU0SrCLuCRERJwM0/ZKjIdyi+oxzcJZ6
7Vh3J6yMra/vklguZQRk9bCaABrHqwW2duEvQom190fHn4+73kESPZ95rGvxPWyLngnEgkzlJAIy
od5N4MNBKqEjFRg2PrLxuI5vw338gRI6DipGpw1vZ08/rbN5InnemcFcUMPVrF9SrB510ofiqvFP
qi9qc15sqHd/uX4rxoj/y802uc4uI5H1JWqvQ2GxSTt/mc++hC4aJL7DvWMiigyfziPKGGBV4+VV
v4YU8QrpObsm023tgrtpbZI4ZYNZgAFkF7D7Fr5tisLp8C0t1ohKYVeOnJmaeXI7w0XV+rodWOkS
7o96SSZbjEimiU2jEc5K3TB6uNStRZ4ey/49SZaP5Q2rL2N+7NfrSbSJUoeVjgCeaM8tpeNZTSfE
ZekeG4qH/utVte3QZWQe3qKpM/DqJi5aL6/1zTdgiVgEoN7b9Z8Qkq3sYNCag6Qg48i0Zzh/Zgco
V2GKi5o8eND1s6H/HhkFhONsLlMiHpMRI1fNMO73lyVkD3KLplhdAxS9JWMpRbSMbWuYeb9defGn
hEu+oQp9yQO3og7FDE+MsvCv/sK+CBXP6Nem816WWc9H5fT+HSXsGBYEQYamsmXBv2c/8A4kFFFp
cwCENmoWdeL6YlO9IcRU6XCpEasiEjSLPhjz0gHdDt5W9nGHWoB0Gceo8aG9wFKIlWBuTUPpq11X
E9nGkzGBlfN8de9lf21sYyAHOsEw++LoUYpuUzdHwkcKBWI2sxRMs1DWizlbS7cY1uYUZWSrdw6f
QVA+OAnym+LL0F+q6p/Wy29lhgGGB5625rUyengieb+hxQVXhB/MGIyId6WNYrUshPNnI2EHpppX
29kLUGTHdsmbbYRuLeL0MvaAx3vXyzeNChRDcQkeNghTPfdGV8czGbtwH6PtCRaTP/lAlraVez4s
pwup8kifVmfl2QCajEoigH8VLlwL1a+SyvsItcven2M+Z1M5DsobgmwCZ5vc5ocUQNO6vw37bDrW
vyz67biR5Kc1pBKU+WubLMSxW7djEW46TMxa2FDOyGB7Yy5RY4bSnQ4n74F6TDdIPjJBgh3+ZcZz
9PZ7DERVKLSQhItbYjhHm2EVRvR9s7qAqeNcq4K/9qUcZ0a/PZYv17mTJLnE3RU5Uv1F1x2HMqZL
oZNZSsKN3sWbAmM2LuI9XBE8IzdbCBnz6JZGFW28zLHU28SZNcwFP+WJe2TWv5uFasnjuNTm39qj
bDTBxRGezMZGqL3QT+YnE40/DxahKpUb95lUIsF6AKsS/ptHc2bSw/Jv/AzxoNAnKYbsmFJVvaZP
W3k5or9u9pZg6V01z5Puztpl8vp1KkIRr6vDYKqXzudLcM29XLHXQXcC2TLDsyYm/A082fCXdUi0
9yJzSmMXaGG5tCk6iTEXj6vz/xi/2lK3Ay1WTwSHBFQ2Mwt0TNpxdSa/9+pS3YsPkpPBWXthu/8J
nXp5ucTb8I+H2Q+rabTCRTW/AcZss5swjQ35EvBXU3R6Xk1ZHWxTptgnKpgeW2ruiuQ4UD/QqPGd
7KGLWl3XZr6FnAROw0XOe6C2BlsM8aGp+Xjt4TomTdAzg6EaVQfh0V/BWpPE6vA9dNYvi6fQ+4YT
9rmL6CggE6RiagYrgzGRP7ay2VeMBXoGH7r/Yzsg/vA27n8YH13VXg7EBHFFppREoelNpXFD4zjN
PI0M2ov0py4wHtoRT3oXQ7EprzJ7i3sC71INRxhhSfENDIqeHaR6xxxEiWQo9kZ0BuJQiNT64y5i
fx6Syq2RS5+6wDVVqgSfeEJkUYSxA/Vz+WBJFRHqTfxfpuqvD2N0UHiRovPN0iDII9wouvgxkQu1
7j8hqdNjmIALmRU+NNAyoDRW9G0irvoJyEuk5tcZzlz5Z6imeMbeVs0BjoDdaWU8eaha49HCYq9b
YCexYtMcf7DbZC+sO7+tDeMJgPDxN5p8wpyN3LAYmXKA/8G1Q3p0GPTNyKXMGGl4SGIfWdJudNv0
v70D+JM8URiuu0cXcihjkggGHfzmlxS047AXUktcgufIG9UXFjfiQLlaPATIRsHO/bIIrZoTXsnd
OVZf3pcUZ4hgjCX3QMSmpJQQXkmqupMgvMUEw4BGgXE5vTU9flyna6MYp8+YGVm2c+t/cKqS7dQl
avjDgv1eQZBfxdASOy4lQPfsonTnWkI4Jufp6Yxnu1WXk/eveMNkt3QZM5FRR/dogtFLq6lXSqDe
m0DeNRVOgR5dO6aYXC5mt7jvzcJOyw4GnLXN+BfqkubJYiUNACIXQx5yZHxmHrL4otf3B9lE1KQf
Tv5xugyKrzFIIH10uOZToWCPSJ/7ZNDQYUzw9vYxXU7h+/qLEgoylXhoqNe7iCWUuC+WCKD7qdM8
rKztcJN5ZCFhFaJzDwZaAyugjxkotaQKUbDrpk9XsezcBqXo3mhs6F9oS3vxNN5QN4Cc5/TPBJno
zLZrPs9pW7MLxsTbCI6XhXf1piqizdbXQclRm4ZnC/5gHeG4jxLH2o1+CjaEdjDFz3MY728CxBDx
BlJHjeLF23mZPqyi7Ecc3rOFnEwdzzbFni8XXBDswyEPeyAvtfBrqZccReAXN7kNe1ljqU/H1kpy
DF7/qZYXUEIZpEoqo6DFkjEz8psthwPH67D0jQu5HlRc6myaeZ0epG97CzUuzRKy8aqjW544h9Zu
0yw4B0cLXC3+DB5c5jPR19Ix1NeSIoymbRmq5a+61lM85oZ7+l18yt9E4ZarQTlM8lrcBPyF3v3m
uHQwp+gPEHwSBUlutkRaX1P66blJxF0EHo78DPqMLjL9TrR89gSSPOCwp7+QQBHtgOzGYUDGxPQp
zk7VKQUMOSyarIYZJAru253mR+GDUHwvfKIs6UQ1m1ohV0CeC06bbhGBKRll7l5X2r4+7s6Prb/x
PYzmRgvVdMx3qU4O1OpF7xU1o26FEjLbRufYYRoTCqxo6Ohb8Uw1mfRpmueFV9W6RDnIi4pqUl8K
BFNPNPerj0nSPrEEHO0qXqE3/XF4Bcoav4/hl9QWsUV+sb+HlRin7FjXcKD0zH7vQA7gPwuzlvMT
iObmKWY3ZSyBkbRX32pbd7Uq+H+5OYMCIRMlzFCmcYmSSpA8gzyPuLCV5kPa0/Z0olnGFyZQusO4
7VHqT6W/Edc/C2HjRYW8mYBC3FPRpiCIcTa7o/oZYVdGDBKEdVb0Vj6P1RJwRykQ4ZMhYzD9aPHk
xQcRaf606NiWPEe71+r8WJ2WWQidPezR8P+jzqrMMEmm5cxgsT/R7lD8SrDyG1qbW4pTVhzjBrri
Jyy4JaGLkv2Eo5KbvvE1vq0SJkObEY4nMsfZH64cUgGRBkghceooq92Qw/Ny9I2PVuFDUU+zuMgT
y3w9QLRcLWHg9JME9F8yYA/qqnt57rbsYiS9s6xRwMQKYNX6h4P2g81ncchfe0mOyFh78glvRcvO
DMcm7KRE1yq0Vxspam+QhQ7WuWg0H7ZU/LTmeyt5TJvDRz6cUROy3Ifbw5IPJOZrLMkUNEZ1zioj
Ahr9kbS/R91lfGkflhSq7xOTEmcxpCrAd7dWYwjxYFCumkcRMVCr5iTBnYSq8AbVaUAq2JnMDPKW
H2QvYpeyuaUKWKQUtMzmM906KWBiKil2/RjdfrxXWCrdPmq+uKx3lUIeZzOeqo7ZvNGv5crOi1AF
QwPvXJUTOMtjGnOD7aOKHnCi/0375mHKHSxW7+TlLZDrWmduwXlj0++eUjN8LFjkV0TRjY6i/Uqz
/HPNBWT/5g4NjaFC9rAQWtOC2ZuFAhuYjfXQiU8qwjiYL8WSDTfNTGTSGF+lKoo+CXkZgz91YlBh
bd7xdJMLvZ2MZZHRXvMz4spMXUTujk7jOQLeT9EocFIDOyi9ms2wDJ/cboltWOh63q4uAh3LTLNj
OLii97JLTUaXHENXOaZCoBO6PgdLxJjKSpAyJSaI5UQn5J2V0iULdAKIVIhcd4nzjhzYqpcyxmWZ
t/mcVuzF7nsTbVo7E3mi3Jm0v0ldvnWHCvyZwC+dURAFeDKmt3l5sEgwuEAgdqr3ND5Xc/1SWwKa
v/woJzZciNJydD7xz2AFuysUGgkSmSbdnElI2/mBZXMtIH6PUIJIYjQBjegM3SFZTliuQ0iL/DMc
vgDA0N94WmPj5iUYLcqtAYFWCoxYcAid8rwk7w5NYmv0AAh0Z2xvQQWrzp4od7W1twj0WFAFS7uo
FNlsjvKF2vJIt0akt/WvYyDnm9oFCxB2tUzvRJ8g90dWeWC6VI52Ogo6NuA/A9e+IDZjcLSu5sUe
NZG52aoXDTSqnkrK1ytdXb/w200Fqc3WodpYDst3KjBEw+Qdy/4Bs2L4IGsJ2bwUjnaCWNTQZyXX
UfJrLR6fI5JHvhiuhIWNz7U6/lh6SAARwSR/voxMfpsLrXh7cfnVi54nEi+Si2IgnIHGztWcvPfx
xfrrdHZLK+qWPkeMlIInP1fs1yta8VgOTKxg2YN5eH55Rf60PBEYRfAncdYnDHxx5yIAvlHoyzZo
lvYof905cboO9jKWUU+K5df28En615nzATsH2P52lsfCSelHblLBIvrSZI0R8BTup8HhZthceRbL
AYPWLArcbzruxpmrvPNwZCwYetmyf65RZiCEKbwMPEbvpGyKwbI6fjUP3mOJWExGBCAvcOd3m+Wm
QWusy6AL5ZXGtX1/Wp+rD8nDnFxMDwptd3O01cef8YESfGIwjC9FINptr3Lm1U05CfZn4/udSO3m
o4VLm0VbgaiggSqjHb7BN302axy/uJib19iqNYmmgDuus++FlqWHdDFZMGVfav5BHebckIElWEp+
8ZB4nfMRKlBbp7xXy7T6BtPd9j5XPACuXoOA3vXcnFxTWod1eq3AXAR8cxmqDg/2Me8lWtVm20ms
fXdCSdM7DAbPp3tx28LVEJA7Fw6wMqiGMAm0LDeI8hckosuB63rqbcNlCk0sKYUjf5zh2trzVi76
6qzDbC9YbXfb6vydU0gdBQ2AalCDlodBtI6z0c41wAecE3A/h23y/+jfDI6huMPBtVy/dj8e58b7
/Bt5dQoFgQNF7gnFS2uhuLJ/U9qjkbkQ2F8OqnNf4CgqvxucaLLPtm+8BA3c9FAe1/BoaNnw2jBO
UAieRKyAX2JDo/+X+8tVvEbb9Hnsz7bmSnQi1M+yjGvUtbIH+S2vBReyBc7A5SAfucM34UvI/2oF
SxrJ9KPeu0mo/QWu/DOoLo+fAf8+K7mlFY2St4kZPwM3shqy+znpN3USLkbdOpD2A69N6w1qcB01
zZ0wgHA8wXLXDzABWcBDY3tplV47wUHiyvaRmBxsr0nA0IRf2BYOkSbGJ9e4vBP5oI3Q7B2EeMzR
1SmMJBlnv8mR1ImXLxsjk+iSnTNh0BMd+IPYBNUjmgCU+FVK3cOmbYHh9JBhsBq6HZNUWosUjzxt
HGJF7axx1la1E91UVpaJZWkHTJFyqhbwkU5/NFCdMJ7V9goznULUb/rBOPCv34R+i0+u4+XGru7A
G+7VQiP5KHYiggDRxdif2UXfWkpTC0jNwp9NZBp8RntmAM4gqg2fXPCWQyZ0WeYsY2ieWJaYtxta
4s0aBMYEbfajofZ/FTErnp0BHZiugCEy4O+MneldY1E2oAwVcDEhAULO321t8H50SViMStAYghid
aLYhiwjkg448SxxTTQKdyUMgzwnI0G/5k3f88NY0ESA4COLTTHxKHuGWrWqCCM5zn3OBEoCroU9o
A65bIMkn/GtaCXhF8nv/d766uPw/WS1TNGOO8BrgpIiWPYiL8LqI97qKJ+PQQZPUzAFXYja30VI6
uSkZdHt1JWyznHFvmHPjzxILGlZMphibnDpsG/9Gxl9mfHbLBgbwkVE83U6aztzKd8sN80U3qa61
JeYH7Mm2TxcZN8yAXyjF+yJtRXxV1uWPr41MV2+hANzu6W1LcPEtnxbtCuXtyEQ3Fl0VSmq9jAKl
coub1g/1SeEb384AT0HYWb5fYa+1gcoWD1jGLQGKh2DH3KaNijZGKsj8r44p63O6PwAgurtt2zB3
mhTfvRHqnXkYCOHZ7pe91bbncgvki5UEDg1xi/ffwYYF7Qp/ICkU53zs/VxhsB6d8hzRfBQS/Zmv
D0tcn9jSpxLICyGCGyW8QuPO0T5URQV6TIpKqUtyBvlybvOLJ3lcQN9LJLaGKp+41jdIU0NsabnJ
UoOvpB/qqOZ9Vcmj4yzJ0s0EQSFtGsKYpPnwz3ZIV3fIwIfyvCY6Pvs+74VPTri2/EMdsCaVik3u
HbQ5N4EE6xxIkXECoOgteX1qyeOiSlIBHuLQy/SHN7LRhEaUV+U+6usTiUG9RIVcQiMbuPFwxN4T
B2aKBnmTVZo/xXsgJ+vmX/6Dxy0SaGZIi2Urkj+P6B4tNsOxfkCPfGjjTwn48/kUm78UABMxWT3K
gvuDTqHuZtsmz+4wN/MuFIp4Y/nTV8ss1b/zWrnSge8UYXGlZt0yHVjTbaZYyJSQZ7vsBBXbNImC
lnAfrNqWgB3pCwEpShzYCuVjGOj59ro6R4/bEnBcypbPR9zNHGOAu/e2LIQL1/gAgHX+ftDek/EO
p73byY405gsXFaIYsdGQkMgO8Mqa0jK/pQDcM0az0NT9ZP4bi6I3sNM7+vCnGGInMiuBooDu+8JJ
CHhVCQRYdR/B5SF7W8IBsNNGITxFUgxzGL/WAugL0vBUepvXcCezBzCv8fcLwf3EKjI8r6RHrPvk
AOfnMyJ97CmIZL4x69fO5ICzzB7egnJv7+FHFrl9p4StuLXYMbBEaky+8oseLe6le/k2Ho4ohuTi
O42DUwGUS5fOmxWUvu0totPVZjC4lLxHHo+eZsRZRnRMqEtrVnW1bz1MAWwCe/B90+puT8dYLJNc
COIdvypPMHzan1VqBxchtR7exj+CTkLg7tZZAHU9hdnaEgjRQMzAC9VCAl+QhzGAnyj17t83iz5R
JY1udenja2Z9WshBJ6GYUR74dU04EaxjqDg0m/oz33nIaLFjAH411ynVRML7vPV8tq2CX2dHH6An
7olbI+mIXMT09UJ6vcOJqXG7Ln8sVxBYD67nOL6PPrNjBUDoFlvl4ehAmSUquwfrDrjztC4/xVWv
y0hvtuAlFVOZA4SgJHzA1K7jolhFZBc5eANZFmY30DT1OQ72TUrAnUqvLZSM9LKPwOFefjBbcT9Q
LwpfI3L6hE5B/rDskfK43jjGQLGY/gQayFTfbZGg2uKhJ7lxpeEWB5505GKfSispBGj+CHpG8B30
rRxb13lxai9d5OCCD6uc+VTh5JRk5hFVZlfYkNTXz0CXovhbZrxzWAncRM7yxpbR/o7+d3cP6iL5
MB8rhC0C56V4K4dGl3/NdQaLp5isj+tj6KRqAw9FWNYFreTw7KCBmXyNkRsHmODzxOXxpq6YJE71
XLDfRy9wUbw+g1VpP3mcBSeV8A0mx5TUzXIXx1yG6X9N6Ir+jzzwWxA3PFasI6+lQd6Mvs1YNbb/
T/mdrCW9yLGxDpcpsQENQsYO4p5vCDAv+JDQjQztfgQTpSWicVCVYBm+GOROfFNYy9f65jNfin0W
+SPXjeC9pktegecdWDIGIL7OuCEOPpAdStz0fL+vdgFOjdfVr+y/65+QO6mxdpnxsTrNiUlW22Ti
6VhPpeKXEt18hR8BpwYwMnd7PxtOeIxPqdFxXgk6uH0xbmcqnfQ07VgdiwGdcn2Q+YJD9gBjZo1l
RJhiX+9sx/okF1CLGxnLC3DWlPwYLZYLOgfeOc5Eqv+Y1+l2yNv5033xI0FUKL75NraUVce4gYG4
9+lpDVqzhDOifH4oZt4O1t6U/TR+yIqoNMbZBb4vv5/bfxeK8CzdxgKYnSDEgGFH5dXZ2qJNVWnP
t6atx7BdHFoQstCn3IM1Qzx5xZ52tqch01gkVN5SvP7BTr6HXBabooumd/WMZ7sV4EezoMxxYIq9
pbUMXoiDREqbfG5CsnbS64fli6UKTm3s5z3ivj2VZKMgicVhY3K3+NczeDK6TIoDSOCJXpd+f24M
UAGanpQdS7WH5a8R4aKKtfdLiS3kc32Pmkh5Tnl90VMzDqw4CiHs1q1bkXcXdxCah7EcU8mZmsd2
6Ou9FsQLIMJplrBAl+wyKGSgbJUX/wqZgPyOwKtDxpcgmQUga4SUUW3A7LeeFmh9/jUUik/w1fg5
Qe+aaRLCHdC5UQW5FgS1sumRjusk0XK6moMTSZsFQAxmmSO/wr+DBL3WhzW+ls//q5DVFIqQWG3w
B32eO5Ie2W8u6Eu9Yp1Z9Ql9+DbojehqDfGtcneN6B0s3cTjpb2bcFzhqTCcPuZXsLIUipFcgKOr
CbHcPqRjhLO3VRAzOTVyAWp9MA2+xcl38J3ofRrj/balgszy0yg0ywjIUeKJIITK62LfgrizYqAL
JAox/SkQNBMllO3SetlBXMDo/+r6u3e5r+bFDogl7eN4hc5PWfhzdzg9Yui7qD8guSa/PadVOFKc
cxrzP9EfdkIu6pP1hXW2qcsdwBTIkk2Nok5RoJ2FmEWLAKMHm/3NPkQQeWwwWr75UaHG/sDwjPv3
6AbAv5fmvPys17BDd9uDnuiMd8gechR8vG3pcXHTF1MhYHMa/fN9rXnqSg2hzzoDxjWXUo7BZtyg
3jbi06JCdIUQkfzaITVwPpBDRSeD8PchDIUfXU4iRyUlWogQjyvVPSsywEm5Tr10iRHeSberw2GX
0WPcovs5JnrXD7Jl15S3bnouNgc4ujw4aEkNzkh36cr/270tN+Gl4JFdc7v/JZtfyr4z63BtHwpZ
hVrNPdriEwMfGaWkjXLA4Z1q2P+rvFdmdJB4eKNxQSwe8A1NAoJZdA7wYTbWPE7zcenlXdwz5PNx
nmSTJ6kqtFmcWvcKFhnFsuOj3XgQym2Z8qpVB8FoA5ozh8neAaBi7leWCrN9k04K/v/T8QMhGRWi
zyiy7OntAF2S2SdLHPHChdLeZYZfs6xJsa5Yp0+Lh7mw8sQmkXNEW4steimAHZG4QDTXBHVm7E6n
Zg6bfX84mZBqM4YoTk+nZJvY0sl2tOTddepsSLOEfdjKFKgF5uRl58mzT3tQedogk/iygjIqerui
/nIUvVuKHbs/+UoLSLv9/T77JwRHSWOIcEeudE5AQ+LmQqIKTdfheaAMek2iRynJuA4rfRjb9QqO
J7ni0Hdt1dad5VoOql4W6EzZp9sTXIB1BWUbciNv1a5n4NEOcGrhgH0MLXeyxqb+jnCK9/cgH1Ua
3M7P0A8S/tHqhNVXXjvYknpwB5wrq9O3PYr+AuwVVYw5NmoxcucHyjDRmb43IGlh6IpRZeJYlJKm
jVxsZZctj1qzNvt77Kae+e5GIARhIL9LXzTzaxhaDfh56hEZ6gfMYlTmM60b4ICC2zrmCDGMxRfJ
RU5a/1KzgwenUIwLCU4rvfJYNwS3VpynsVij7Y2bzejLBP9i17veylTdesJu/N1xd7UkYZjildee
W+WuUYrXMygpTUtekKRsZKRwin5WdhRda4C+k7yVZmfifcl2Kyzc8Jq97LOeAEzZ4A5PBjE4rAI8
V9xWyoISTStX+LQPaMS0euFnD+F0z957yep/FjoP9XhAUk9WbA8dmYoEKoTIMwT9yOJUzxN7eQWf
JqxYaUG0ZuYDpG/jF2AniZKHc8+UFIi1eSEm1g5tFslANBstNANzRZkZ9Y4+XzUc4+NHCuNPCK2v
tf7/w4JDMCVd3K6Z2iyh+ioWWSGK+iYQrMsXt8yDjRCx64XjxAIvurh4PEuvlhb3MaykkAOkSGeI
GDgmI+Kz5zrjbibo29L807lJ6TnpSKvKqLeYZ5Gd488kOkq0itVugNOIiMYnBGpGqNWz5tPHG94x
eUPusIvIlKHeZkdibYpDOsRElC7f+DvsPosO1OEmPUena0SwvMr+DjRnOOGC3VnRxC2C8p/rjNQb
Cfh0Qh9LuhwxOdl2tbb1sU2K57bK5mcxDhWvaX8FZx+EfX78vfa+UJmii80R6DGKBk1lmEEvVqHw
AJ3kOOecMNh8lV1Zxb6vqLFiRBrUJYkAAn4L8Xo7bzosgvd2xu6A6WvgbxouHBJNUwn256H+ovw3
hYYWcNINYG5hBrD3VUxKzLILtpQL24br1Vmrdp74fwhW3aqwGNQOxODt2mPLeXib12Kk7boC2E7G
oP0bYc5HTqfWuCOj/jW4CslVPKmDIO5GHkdisOtUNQA7W9o5cy6v/hnETYldHn9g38sxYPAD7YId
Uz+EQD4VekPvZvS8oIpFm+zC/FYxt1fpJW/HKyb5I8DkRuCfkRAmxgIZPiT4c/HR15qX5uzhytRy
+vbD3t3qu6YJl8xVRQC/l61ngfgpKLBADQlMFGo1znNGmD++jun8TMZE0OzH3N0WSqeX+wlu3fik
UZHVTQym2XGt9ugKGwIBGcxMTwfI6WBSlg5+UqwCw3W8upF0bx+abUmYuOdtYk6bXc7DoqLc99yw
aXhlJEGnc25rTEn7G76xoWm0gRJVluAlQ7Ob1e2mVboBHtoccMbiHIK8idMMb7QLg4GTCDLMboWB
cn/0E5Vo99LywxDKX3VVBNXDbCRyLY8xe1LbM+VxpS0eYBAGdFSkSQCqXXnVWYC4TwAIV/Lepg+q
83zvJSAFpk1854U83A04sjZEJ5Be3au/nknkMFC3xNbraR4ABvf0h0zACZe84KkRFaXCUrd2GAFH
04IZHdKrj6xwOCgYPMbw3h6ZLSvNLvUiBPtwRJLYFv3qs0/0bSf7k2Sify3l/xfkuKtquACYxN7t
y13MDJrvlqQMbQdb7jpyqqUpFx1+Y2ObpRHVjlAAJTEZ227EettLtgtHundbAynd9HZijH/XviwE
VbwuRZ1g1ifS3PHVNYDYoPJ7eb8tBfNLponWjHNSWNtoJ2KYW0/AkVd6an2RjrpJQE1ymzMaK22I
kz4WEDDQjV+EGjZbcCurNJut+xacQ/qcWGBFjWPPR8YBjnMu0+nEEhRc1nJy0mzXvzWm/8FR3TjO
CKffvhq7g+MkX5y1GsdwG4sSa8AOIcxcJ68fEUUdo2rlZFfefj2IH1+fUfTgYeUxo71wHY2QrF1y
h/bkI++2qKAXOA0pdQQDNeAvxT0Vz+4UNypJkjSKhvpq2vR6ZhX3cMUA14755oq7tSE2L1OT/sC3
dTToOvuKyZIz7/Jnlo4qNtdI7Gq/yJ1Z7LlrZYxQnY998hxCPqrTpr3FnipATnimOvtQPHT7IeL3
FcIAHPMX/4a5+zSWlLGRRTF+j8wYVMnDhy9xb6wTEbrfL7pmiCwlMIS+suVSkHcF2NpLhbRg60qw
d0QDO1kd6WvPtoU3uFkjVrVETnhAJhdTYoGPjySFhCYaApTyU/xJny/dhn9ok49U0+rfQluSVe4Q
QT8nEStW/Bhd+zmOvsKDD1ORMA9m+aqLMEGbpIliV0hmAfKmoabDjn0OAhjUw+0aG89KZoMALbUp
XUQAuDcmQiK3qVtjl0fj0F7eTFiXbCwqTtOab6eEnEgDJfRsgWKc0/+AszEtD0P2P3p5cv8LdCZx
8D0/ZCzuBnB9fb0/vSNhtX6nKExEgnc4OXmgXo+op4R6bFrbB2MyYL80hi+EP6nne9Ar552PhTh2
VT1FZ6Rqw6auq9BHuz9ZeIpqZc4a1GcrnkFZTF1nXx5/1K1Ly0RYF2hfSiF5Zd+r2mh7ujrtrcVW
1hwDUNIqt/XShMP0CBABP58Hd6mhrQK/TOsbgoubm3zk1te/TNQLbh3YrwJu8rv9MvvPtmE8FiKH
UGTOL419z3rvyzesnfVXumExNMXyw/ePmy/oPrAuP6pDin13AgxwmbWmLD2BhOEv2vQnKU+2FHf6
A0dLw/dpuWesMLFUrSE139jh4PuJFCUK+gzXeKxdMO1Rx4SLohyW+dg2quuobWfmT/AZWM4y4u6n
di/UVmLXMCwDjJnQMiB72os8/NK4D7WZ2drQvlhbmRu1HqaKhIXz/mP+QlGq79B3fTCoWC+swtnz
U5L5LzCMNS5vr9GIbY/HytveGuR6ouclgElKgARJWKwtQiSyf7AdbXhEgfIiUCiKdf/b/sLXRFkm
i/Nat8s56nMbY6wWLocf3BOADWOy2cZRbchY5YSTgNPobW4lw02zDAgJ+plL7fwIOao9fudU6yx0
vTSBJ0Zx5z4CtRypHkJYBDF+0ilZ3JYq3PFZbq6EA97g0zSbKzVdjQegGMIBKgrJiSvvtIZjhcQd
C7d1S6pe6fct64H7WtWy8TpOY1ZPWwHPT/ydd4a/q9YsVEPwT2/ZQ7sKEXqSzyZWrzEyQKhOwwnp
UhJiKANmhg7V1WP28GT5qYhQiJzxPbHJsmsgT9XyMNO6XXfRs35CsiDUTI3HQl7eNi0LHpf4czhQ
c7k09WwIBBolq6qYvxu9GrgwCV2KEbkh8jLLJzMxA9goOa0eFKBdtU4RytFGOv3galcRi4d/SWHQ
PMiv6dTTTq0drS1P6Fp6Uwa8HUUo5OmnVNZckahzs3Byzy3cnlme3GSJR15mDdmc+eVAT2ayjJiv
lx1qcxfgyjgSf9RjWC6sserQgjG2TY1s83SQ+tVxGcbGXCkLIZXDSvf2MPtmyHYJ3IcjTmiscvOy
jBmcYmBCCO8L4pPNHnVeCMKHjoteTBEdRpDCebKEYx+Yt6nthL/qKLSyEFlTsCEyNGVg6KP2LQVH
O+ZYeHAp9DIHDuHN4ygkGW9172dz7dbqyo73wPLIh4tqs2n0jy0YFgYQ80Jz0ac1ETrvBfMZPmjq
/S4Pm8DGgsP4Ow7hR/jhqmzwVQ8PfRJeDKDN3Tt8Dp1HfqM1Qt1Zv00nSqWG8wvQN9YbyI7byZR9
pCF976qzcoyXj3aVe8Q0/SWeCh4aDMq5w1ByL57lsng2aYlCUVnA79VfHDCXeFEo/fBRGcTKvpiq
0ihUCW+4PdIYx9Y/NVT1AsWTc8uNHq2tFJHXSRKIRt/DJihrgnhiLcxx769fYVS02k9riMClc5f8
2/4orbqpKyRt7A3/5lB/fjJxfVxZQtha2qMSNvMDBkSJ7UGVc7LOPvhRi7noFJo7tdakeXQM4hA1
Bs2sHoP+BMevk5Clo/db5mOk6ZBEGqy2iBAGP+P6JLB4gWY6CFWwWvGRNNNIKjz1MFaUCfaqEWyp
exJJbwsat/b0YJ6MqfVZr9nHiRgkjWuc8VfKEv/+FvCY1eL2KV+FYBoVStc9dgbJ2gZkqRcx4r+B
4dAV2golNnHrDrUuRYflFEsNP4Lmv72+pIWnbJDcaRi8BtWrzi6oltnQ/kXeftcFHC18GbqTvPEB
C3ZoD/DUWgSYu1FCb5GjpItXsh/EOjCls0fUNnjaX9oEFmBh2pePWjAO/6TwlwfLGI1JFybwE6Bi
tRrhMLiMxLMDE44e4OYiqOxNssY0az2B0SKzK4mx9q7Ms+/jkYPYv2XRfo3CBtjT1bD0b4jGXGV1
e1F1BDVrmNIdBb1IeK6+T0VlUgmjsRclvNo/fIhsUwdEvivjes3fyqWh59JBXTfp4cpOL/vox2BP
xHndo/LB57bjnv/P107CM5AC9gJ2X/Abw/5gCPP0kLYSbXvCnxMSIi6tSygTVxW9yfw7fLB+uIeY
JNC76jtsP/Tj5+93wCqp3DCTt53PYGuH+qgZsR40b9NgL9N4N8dLALjUpz9kOgbuNbqapTKtwNkj
Id/egu5Z45VKnPK74wGO+t9Z5NeaCz4PJJeU63Vdy51kQ0ZrMUwyAFESpGzKFESJgRDrssBM19ZD
nvh+25zVXmzOYhC1753VLyGQV/Rs6LOGtWjzKnQUlTKQ0fiAXkg5aIJyFRoHloA724GNHtyJxB57
j+8FPJhGMVlKH0fBHTyIgKJUY+C7DvzWJOnZzb/6I+AYyYFV5Wj/3jNDAJvsmg6h2imji6RASgjG
/+RFl5/rvFCOzHLwAkEL4k8sksMsOGgnJ9PrkNrXB3bzSKnnWppWgkJgSkLqspcaG9eluFTrTqJk
5coKRv8D/RTcP32xXs83CQ3/9QC5BScHRd+NaPaWI+JN4195nUIdYG05YXbF9BsZwSqnZIZSe1YN
btSshAnWEpmzln1f73cGeElVajbiQ7YDTz+KwmklM+YzgV0ceXO/OprAB1dv5IEssp/0juWUsFa4
fn9Ftpq+nJI9qhm1RAxQV7OqSMrfyUAhFgjIw9PNxbtz3LvJb90d1tAzQAbdozDjLPDjlD037d4C
ZimRZb3XuZU9Jp862rWLrWXXubhIWYchxYJ/Q/CEKNRKMEvJZUg/AFX76XZnXr2JjO1BPPrjfsXB
tQ/mn7vu5hjW7LYX5RcF/He3exSHSSF1Eo/Qc6n6AtOexGnv42xHwCx7BE84rat3kJmju1seZJTu
+tpic64w+a7sgSzdccMpUEsA981/20Q6wDqNXGZGOT8DbBAt//l621EQ6Ae0KaD9gDJIqoDs28M7
Rdp5wbNSialJ3TG1fwVSukaelnE4S/YQCGbH3JtirUIuaKww0k+BhB1YPYeUjno9JNtky2GncPMH
EqlBj2aVXlWns2olHTU+wRzpEokj0oNTQZ8QDscrPrCTYpKeNCJP/byfCLJNAhHF/JsWBLCtJO6M
wWWpDMLkPTuXq9BzG+VvtflHaBxci2135593zt6X2i+CRVbYPH9bypwCRenVZC4TYf+OEWUlfn4A
Bz6N0WHmziIFu08DuXLVz8Lm9NA8aXwa6tugWYMJ3vmH1h1kdfRqMAGzzzRLa6xXWt7Vk9ZaqSWU
kmsQ89gl1bvKDqzv6Rqncja3/FmxOOPJcEeA4kSmyLZ8UFiDDc/apSgdpjIZR7G0qFUiIi0X4tst
TmBE9yL0Rbwx9WumO5YISse4q8QVjkD7DbfWUMd01An3A+6rjuQg75XReZ8WSfSOT1h/tKuaSf7o
8u1PObmMb81bYuceuGCV7M9oDmDrqF7sCci8oBXKcQbzjoAehpPvQQaiZU8Uv2Dya4vlz90D5plX
87ZqDPP9zounC97RB83AqzWEx7r8NdBN3r2NDAgFI0DYm8dbQn16Dfr0lFVnx3VT26dBuwRdx6P8
svaVVpTg7mfVcaWi3FaFzLSI4dT5Muf9Wx0g3HXw3QThJWe65XtGnSGP6sMW2s7OfZVwjWFLI77+
Op74HIEkffSqFR/W3Tn4p2suaS5/XNNoKsth8RxHe/66AXTIPXgp1n7GrYD+SvB42YALD6a76ice
YpopwFknrQmGSGDmeFDB9GAs5aJZqxbr3Br9JmjbWEFrWV6ytMnpauZBaqeFJYUgv6S6tdHrPOkw
afFvuDoe4sZdu9tMkf6Qy0AiWzkVeYIhLj1H0DPzRv2mYvqCa6d5Jq8B8puYLx6VizVolzLPhk+W
TA0qtBmTfHzRNLbID3hrYV7yik5QeECQssNTI24fktXNHYNfZDAhvFGsFg4UML9aUiI3n/FVqDxp
LPVNDa8rGdV3l634r5YwxiIxhVSeWn6JmcbQvMUrITQco9/IN0bMWStBSqbWB0LuizwlScGrb25U
J26jWfFjJR+K0ahtY8EkCDhkMC/Cb41iPLG+LkczcmUWZ6K3l4eUwkleDI65hWkkwlz9PKgK0FU0
8++AiFIOBxP+z3wEnzd5bml1F8PZQPMBoRQKDyxXkOdAHW/kkZDWvqJiqfftIH0jl4u2zAa7HP4y
8X8mhXG28BY6ooyF7Q5cPp9MV5RdSKRvxtoDnl2btTdA97AkGoL4p3TkJISDN5d4ff8g/c98PmY4
iBONXaMrLLL0O4ubqKSgdwWd0WrCs2QhuPxo8bj9Y73uy1pOCSVGB69HeN1LCb0d3i98cTcGAMoO
20wxWurJSKaQq5jA5gRnclJCBwEXY118m1I//BCLoBzhtXOKz1DbC6+9wZnk7B9itLT6vN76QUxJ
IOfQex+6EfpYTI5mIjiBO6+0eAM3EYixfGsxv1ZY++MuncIfqC+JwuD9PN5pd8EzJleEh2oDcGx0
ODIPLfMn7DYxneVP+SpNTwFH3XT468kN+RnrVVs6isIiaq4H6Uxqkd/kUvB1XOgipxOsn+qu855n
x+/875GvlDpuveihya1YX9rf8Pic8AGp3LALS4xxspVA6d9+YAW4bmJKgkM8qOu4QTqqP+aBVJcZ
8jAkS7LsXryauXlbfTzK3Di85jROhx+OlmNqrs8dljOm6RIerAiHEXk/Q59g89uuoattoIgPl434
FVq/4WtoftJxfohfBNvtN50QCa9/kiTaeg2b1QQjzbaVLzgwK3WDGTaAoevp4F4wdEoHs9B5CbKO
fIvALUryO8sWvH9d/H3uTtmcmqYN4Sfk7ciH0Fcox8cY/EeBThcyEaPC0g19bDzf3sN+VihGu8iW
MfS4opWYONbTp5x5Fm3L6Ddh5TDRTuCfkaCzB3oL4e9jyJeqG44Tc1YmIEq2TSLvxIrXTSvNCRp7
Da+sf6H5XxNj9Ud7SVXT34XGFyskhIBhh5TUNGAe8hqOFNmqzDMXHrSut8ghGCsbHzfiOa5SRWgE
yQ41uh9GiyIzyvgsliaFX8BtZnNTTb68zuY3j+AQaLzXzhdhpZf3dYUcA/LJ8AUdmWBz2KEPm9me
iDfvvhYupEnLOxWGhGi3y3GtIIKsGG7M31xUoAEi88g2Jlpo2xnn9b7iee368Wa8i7nqga95K1UC
+9AjhPfidvgBN9jgVwxXMM3ziO+GubbHG9g9lz0/uw/+ts//9jQwSD6zHxhKGrY5e7u3uZrSuYwV
sd1hQDXCuSqmWurrD2oqGHpE+JGuG829WUgvHLJAs/Pv+HhwkwQ52SgVCpUbdQ8zz6o8Y+EK2X+4
2mrXJXpcz2EI9BxawG8epAPaYh2/2iHEnq1fHkx1ty4ytC6iPC3MLx+Z/5N+I+vZLQkpdZWjjPIB
24prBtpll76glntVVdC1fHl9C0j+72AkPEmKHQQPto4n0rU+yKSlfL7sMpxH3ljoAsamZy7KAZH2
0zhgMNMT9eADmPVT+bo77WCW/QmGW1zY0iLk/lZb0/gvrodmvGkKdAiHKXjLtaxp//tY+iI4wSsq
ut8Bo2HZDORmaeZTToXdi6snZHBIrFAeX90kAvi8D39BiAvd1KKfEvsSS19jmbprIop9mNf1+h16
GrVje++ZcJKQ66V7cH1Bktp3kHYobVpqjarfRK1XAG38Va+cniiRLBhdhErCAYrCW/Mw0GFF6cbk
1OoMFkZwTbIunNAYubkjy7k9tXF6yyHx7d06g4fSouGKZyUU81qCq8bYhVBrjFv9q8eIVfK6J1bl
MLsW7xshsOFPjrqlvp1bxMGVLAGQeaYMCOobjc6kEuoF2Gd4ILc0AbgYPQXzLJTKLnpiCKcDOD/6
wHvvgEzaAcjWIsEhPG5QKiwKkAnVUprsIYeMKFfsZsshscOwmPzYwPRENaK8EF+O/cJS1B+zoD0y
O34XSY+R+gafV7lo4k3et2LzmgHEU5VwwLbHFjzA168yybYpn0ccNxbGN3SjSW1ATOQMoPghsAEE
CN9Iv/gy9ZWPccfi83NuVEnJsvOXwgmpyeYALEVJUdpVflCUErSf3I9cgcn0muWbC9tSgNJt6tzN
BHanahzy5qNT/PzwbUIembrQmOLQeH8PSrorDGWit/eFKNyooVlsPBo3GjnPLEXVtA9WCIWw7iI6
Ku8noelk9ALpQ5wMYyrlN336Wozr1yudxynJMj2SxA850wMjyW8ONwLKXAhI2I+DK7G8B2LsadIJ
exyn0LnDPO/enq54EbccEXXqjZCzM6r5Xek9RZl6OSeBYAPvTGiaWAh5cpSCJEIhTZ0sovD4Fizb
fTFBaaSzsoyfzcz/wasMjz6aUQRAWpRw41W3qkYutosl1iGtGaWLmkPF3rDibfcA7avsnvxfxwpY
KDx37xEhyTktSjy38VB3+E1YWebmvz6Dv0HauGBNp3/UocdYOM13L2mAIRm5pkGyr9+acSg9pssy
0+bm7Q+ZOUY9v+uA6XbwScM0DUmXf3oJ8XdLTfQL0wqxXaC/MaecOZPRk+BM6Q0EPod/6TTbmc6L
uj7tW1tK2eCfUILAWWXWFu9x9DWGZ5g+AQXrHPNiSWUBETVlALqJczupg6m5nVFFrS8+tqUhr6g3
yOvq0iYv0UIVRl0/syjDPWp48koZzETKrFHT59gtGO38wwXQwu6O3/+f2mdmZZt75Z/Qt2oM/CpP
f6C/mwwyeHLNhGn3MicF42toHnmF2AtLtY92nxE9XUl4ujdRYNIPZ/fS5dU3aUjtWDcbW7VvvYBw
/s59mJBrcja9cNmvtQWKeu0YIlcIF9sDln3ZM9dDV+zdo5E9Vk7vsLViYdnvdd5mImMWg2zT7+ht
fxvNR4yH7jwx14mj+4Llu5SHzNCqxHLE7EujCdbmmfMyZWntA7XWKAzaqjrJXm+EteKThFSM+KGn
IHccgGhdBlA+25k8Kq4nyXN6e4mmISCGvvaGs4kg63V+BhdOFmE8GUiIxrNRuzwsbssr+apDole5
SGLBLi6zHhOy189d48FNPZKRnsXtEvZ+nSEh17qLoy3UiKPXxvmKGGSskHhoTPH/rC35vGfMMSvQ
R7jLStXE/Gvaw2OB83jAxmGnyxjEV4rxhR24xpHJlCU5TUF0gS1MtvYWvtZPvPpxumCgO2Sl4Pmo
trv21TeFP7Eg6PbxljmSVwSQ8lSxIAYHbk5LmZ6AetUA4ZpE9rSk/Amghqi646aVRIVm4lg81niN
HQ1UJPZwZc882A/3be12xZwcrCs6LEHbfiFmlVycFTNNbBalVCmOpNTDMgg4XSExPfjgG2x8lB4m
v4iCzHuPUaHduaeHtumJQ1WxIrfqBE0bYTcjppIj+kvjzu5+ePij6B8ZSWACOCH+OjPxU3e/Bq9U
PhC8D3l81egTqcg6IxVyNk2HukVSy8R5fLNeJD+BfM/KqinQE4LPzk2mqoxiEnaM1wxNwoCLUQJ4
hRs9UxKOy+2rQLVokRu0auwhwoUrmK3mrM2I0+ReNk5eKdKQSfBjE6uP/oUCuZbYlMQjvJzOrxlA
Y8VAuJsZ9dZyVyy6UqaluypC/Ah3DJKizzafQB7j0L7dT/FDQM/IxuWvpywy963fGCF7yBo0I5v8
3j4QeRVN2Rcfl8tdoAeMl+UA83Df5k9ccVSHWEg07HmN+kdYprNuJGOgK21Zb0DtXeUKYPcuip5X
wzeZS70aTO2mjZClMq/JruSN/97kYg+8zXss6HQmY1vzKVYPqeBRXOQ37199Fn81/P5hEBpuWyqE
Bt3fsfYVD2s6Bh/0OPzCm/1i1AIdSNjNlAN0K04gSengA/bWEfQT7KddMPLrdgvkUwhLZVJgouYg
PvzdbcA4xcNRRyR5qzJQhZbzxEiF5VP/HeknOM8k/pyzsGmMC/aflg1DyEzCRfWnwnM2JYp1AXGu
mwyr8RQ6RqOpsE0bGLaAaK3Zf9tngpe3UiuMBkBCiYSnMrYl1GGLGCr6Q+hFEpLCYNF5iXy/MpzA
3S2OYqqpSG8PbCWZ/ZJ5Wgbmr9Eh/fDelNzeE2Dmfyjuy7oBkax0w85PTasEcNiGWolNUV2AGC/7
xiDCzZHY91O6kU9sVGIco3d4K6BcuvPxgnne7CHqIoCyiAX29XdRUaqGoDhpd7GbSH70FMcaROkd
tLx+7be6BOPSaSpiybnoscDyHiEoUaeRY8Ykm5WMFYV1XZZVbGDJ9MA8Pshh1TVqPRqvSTXE4fp5
RWJ2KVdAtDbOQW0OSe1gBWsIiNEoFrOebnUyq/VkQiOOSiA2dElai7WRlRrpIB81gnG7gI8Qo+A+
BDigF6/KuMgtdFWHjVSJIdOgfFo1Eog+susPa2BFWl4RP3MmYcPmxRIYWv/wLrLphubcTKVKbRVm
KNELe0FhfCRj4F4rOHO4GVP4jcUZl7J5qMGPfuRkCckakp8m79NadNzu/gnHSgxFSe/QnTqFtDZ3
TDZlBjb90MK+m8tC4hyNUG1M+1mtDYuBom2u0R7BRa6RD8Ksyv6OC61IyGdAmVbLKNer78rcSLaX
onmK5l0WL2BZdvzZ1sKZAkqCLDn1QwqNSmwJdL1Lum3FHJKQldxlTMIUhzkf7XkPfowaABvDGWuC
WUwroxnrQOi16i0brEUS4Yh8+yUydwPy3GSIh538wMWqGkd14t6lrAw2SL0KHWEAC2VhdLUV3Vp+
Xc/8IaO5rjGQ+/IsDNXQ1B7IRYm3UU1aN/cKm6lIyBubgetqFsds+zYigaUaxtE1Bj7PSTebAC94
nyeOY+hRF3hvmEtLqCRJCu3VH/8CWsYiu40UP/kerIVio5tDond2Xeo4cD/ZsSWUfZWC0gn2T8Lp
OFmkAY6HB9W/sfZHkxBHCYXvHaOVU0H7a41WnII4tZ6LhNegdmPxA7UGQH7JlPp19IWQMRAQPT7A
TEjkTherPvpjQO1Ty4ytQ1XtrlqhIyvTdldG96anhzm70W2Qe3xclNsW7HqcoZlBmiUghaRY2jOh
RvWNrrPycFkU+3dKJRsQxYbleJrzXm/saUW+KK6vJhmy673K7I3ko5qM+kTR09GoPk1Wdaz963tS
THHvm0jLsK7cgFIg5sCiMMdVyjDXIrROYXCLT/a8Kq7ouXOG3pEKCBXM/fqOQHpeBwLwjj/na4Y+
DT7SvHMPSRHY68xknnSZjZhO6X6L9D/Lw50XymwsKmGvKpg8hwMhwH1ovN8DVWmUfVcLY8RV5fPu
cvYrJ8G9XNy2d7u95sznubRil751Cp9pDSwVZ8JW/oOGxA4zkJB8iQ8eL6h5uwbhvB4u4auZ4NJX
1CPX1Ta1AtTIKhZUKloT5YjwKsNU2svZKlolI1K/g9yI5Azjfq6jUKz0VZ1rzK1rFtcRU95UXR13
bSVs0QDQtTkcwb2U6bmVrQDindiNJCJSVB01lkn7uVxnbFkwlucFZ4gJDKzhpKc4rmtfQ5tvLK87
c/pXijgEDoDb+V8jWAx3hvnFNXAL2PrMqiImcKRU9aEs8NvMzaaFdIESPU43ZPYLhmgibKNHTyRP
dw9BUv07GidQsWY5Jfz9BR1zlrdPdOyii97Z3U50q41ZCQzQBUZLMbSp4T2pzluN37YRGkXuIgvk
CdHSYUR1w6YAF9NpD2V6WFskVZw2U3TBMYZPPJo+lOZKXbtBFYiSuxEXmV/O1JreTfwY39qV8d5+
zG+SLmAcj/tw9eQS7fpcdQUKwtpvUS4yO56tsNObxnq/T99zU0ew04gN7cfTr8cAzYwAmZTcQyB9
Wp/J1Fa5BzKejIPZLdrtvjofqW7QOEX88IeSEJTabmLMksBHo9CY23hvoI4670G+PdVMc61TV7mu
t2+qfCoOrbFiqg7G/jwFGIB5Sx2pUTUqfa2UpJ/fJ6lnDzoY/+TboF32ovWfEHC31GoJL1EqmW+5
aWMq41HFe7vQq/sUvx26qPvSPXxGUgJbi0vaVN2axpvm+nz010BhG7dDQKIL/22Nis8rqb0qcBv8
VgVImfuY2RDDrQHvF8k3Wshklu472cSq8AF16izb0g+6dX8G/A/tl9pdehzkkF2WJrJJNzFMwUSy
Z6gf5jS+r4AW4q/jFvjRK30zyYwIWahHru0vC+VfdsPgmUw6CybX/uwcCkqfbSPqC34dmKHD6lpK
SsyFZSG1z5x6/J4QyWbB6GO9GrTykNXnI4LX50vbdR465MAYMgAc0PW+s1wd7KCMt6VYaIcQwlNB
Nh/oSXczkU75rcP0Ng6UyaS6dD+kv1IrX/4ym5lgO0Mq90fn8RMaIMHrh02KTOPin/UqcV/BLwb7
SGbJTEicfVwda/665scUTP+PomIgN4XDksEmd1lJ7QPPKRauOib4MPQJ2ADZcaCfbT3rfMYDqLuV
YuLS1AaWoMimrbe1t+SSfyjzlBnbD0xSadQ0HDe8Gy3yQ5iamTurznixXKXH+gOGX1kqVUOM6TIV
89feDfSSx0qfujK6lFBwmooJHDpdlhnr61u5N9nROjNI7Vj+zwhsQ+LYW133wuAYEUxfC21OY8E3
pEOJYeX3YpTIsnsZ/Sn0Ow9q9dIsdvL4W96BleBwE3G0p3WLyGYjgBRdV19LWYARQQQRkYxPOyBo
NcTlh5MOzHqcw0cgKpTXur5F3q5Tx1/SwIhwNTWoMOIv+XFjsovcGwSkfZTRHsb0STi2fOk5Pkpa
UdgDn061fUWEG5rTPv2Pi/IHzPXVGcGEHXSQaiJK4lhk1RNYfoLv7gSRPiaXXPeZo44PWZSseUjk
4pJTAUaZtvC8hR7/PchbsIG/8jZV/7bz6JkQ7Q6yy31lrsHXOhNFino9tLnleBZJjPERTW8M/Myh
DC/UlCjPwoWe/VdE0rizjYYVkEswn5CFXuvIzSnuhAD+yngs0e0NUK1lh2Cu8CS5rNO7E0J1JNZq
gnnS4OheJv36ODWV/H1PP0LJM4/x3BWdTNpewMjPAz93n+XoW02ZsTz+foYV8ur7ZQgOwAkNgMmn
wXv9CQvFIkyOTEDdeUMQw0UfxhWz+xBs4m2ffD6p2XARKB7E+osVd/WsQgXhYxOm8cEqn2z87tGk
LZ2X4rZPFtq9oXX7FV1wQwmnc0znfOzef9GA3xuuSebp5O3rmHho9+mfj5JNyKXlQBizcYAn2SQE
bPyWokHR5vlkdQMwmP1kWAYlf5qokDnir2lPWNIVu3sUSYqNNaqlGULrCau2/Eec55l5n1GwF3bf
Yb9aCEOWA5DRtLdqFNgdRctMIcFHxyOitXraVs8Bl9Xe4j+rlW/sakBPV90oQ8cVf0o35nLQF9kN
66Tuzrtcfu697MVteMVKcBas3ZTYte9ua8ryzbZ0w3sIMZ8IHjpjfVIZtidHFNX1tJhohcAcCRdj
vwF+zjD/6dgo55cZoNtoPxjMhrZ6+T83ArBK/UYPyX+Y+hTIrF1B80T2x63aeP7Rj5ENp7nDono1
Bf88Ly5cPgWuT6aR3bSsvS2VlB0Ay4Du7iHl3gB7PVSRfuwOPIsZo+P1K24UmyZdVgq6Mtad1RnG
EUUySbapAZJpfYzHdk9NJ8dU9fbdIjeU+JVM2totfpWMBY4zjfqLomOIC9XInObLBkoQ5W7qfpwo
W2U3/h2hnlK3COtSch+mH0VdsIfA80WkSdKFtXebZcqnxGucgNWIMu97Zq5tr1MmNomtLTOekkfr
pcyIyeygDJJ+RUwfV4gk7NNObJj84CGqasd5c0AGoJytttLQQRYj97vFyvQ3750uuNu6LultdMQ4
tl4WHtLsnysf7jyTfjuCmUGHOB3M57yGei/8C3eHMZaGabC+/vCMl1pJ9+pXW66iNk3qLiya3Gss
qH8dtw2wIOYRRZNAuD5p31gwV84i55q6RCXZmBOjwqtTFIEXn/w/SCChROaaCRVYjfBkqZ6JwS2U
xma72dRL1h7rF1hufkCF3EkdLALj4ByrYlQmM9c0tZCUHoVlrjGKg/n+TOmBfbyhS68naUvDehz8
rwnMDGSNG/pH2Gi4FXyBoFgz1A4rXInu5oG7jtBtBKZkKvMAtUC5MhM2afLKuZ8umxNI1CxYSbfd
MAM1uLqs6LSmWV4ENx/WbjkfZQJl96/ufYJ13E6aPgmn4oZ16VYl8HL3JU5+486nypD5ns0yzsEm
9T1FQUuj9+J8akJDHA8Ts/rhcpnxceb2OZ+TFq4UEV1UkWUIm+GCP0cFzf8A4ub5I+CYA6jxV+Ks
IU1UnCearq0xZAK6SWhiBs/ltjUX/Ac/oQ497t73oafmMieb9fWI3O6cHX1+nZpKRwQUtG1e2VKz
oKhcYgyYeGn7TzvD8KuE8bLjgaj7tyBM/Sd2U9dRtfUiov5q6qvLGnw8YJuvgfbqMKJZXlWVJBIB
7GJRtflfQs1Nr2tVEAylU0QnXKYubwxW+sjGg9/j8NOrDU6Uc5x4r3ZSuy21ts90PrxDS6Ug87C4
9WmfEs81lLMNAXXrYgbpA4ZoWVusEOrYzZNT1vAOICJtxOuRc5Qcn40jpezenTtAb9PvBtu3SkU4
MuAKi9GEjEDvbuhoQUp4QYlyJ6PxmuqKrnqeBm7gGHl6P5k3b24AH4rje9zGBeKRWawIiC40W+vQ
lDuiB4PgEzAKCj608jfcKq43IIcdB98ZpObTm7EVCy8FljuJal/U0R/pE0IPwHQJQrDZ8cTRsLRb
87RLMw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 95536)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztB/h+4PvAs/N0XI0cN9OT8nV3gs0Dpd/RXDA4Vc3dmwziA
NwElhjRY3VJxDTskfz+mxWNFaf1+mPePrYVqlwPTMBAxpvGimC8dYYQqLJKeeN1ZgTT7hwUkM2z1
Qy84CcCZcArvoNTfBy0dkWCCscLO7FYjYdrltlJMSy8CDdjskSxeftCs1jkCE/tStmrqLGxjbT6f
C92mpUd5YCmVlDJSoyG1Rmk3H90KWuHUMBc4d/nTIqIeHq74s/5YZbg6Itq+omXbAlchsha/ae76
9FWmmOPV5pGgbO9pUb/MAoiGnE0LV3UxmCzxLGMR5z068+xQRaJogr8gIRx4YzXucEDuMm6kq+U/
DJ8q3+UroFofr/QazQtIkbprz4hnKB1pQ9WCRHlWqYPmrTOztTQ4ZG+pAcx0IYfnFhwKTspFW+7y
GVx0kYGoMrgq7RbxX18WgYUZLMUFfRe6xSzxKiK5kNCdSzOH1JhyEU9M4B2sCcF5xcT7K2tFVZhx
cOoGlhAsPEMuJPF65qYCcRfu6UC7PJuefitD/S7Rr62kMcVw6pREvkYzRs+qsbgNnfPabgzwOYLp
olR7zI8hlqAGIZzAnxQDewB8HIRF0Cgw+b9popHU1CVbEfrPyAP2H9rTagex/AtB726oU3NS/Hto
hL3uC69KGFYAENJTVq04Ff518xRZvbDhZk4t7/Zpna6SOSIzrODGUJSP0FvZZ09QlakBg3Wo50tY
pgmp4DoT7CrqwvHOwtpgiLSWvTFKDLrISVTMjwWznwzIhQ773VhYwUgBwfVumnYIA8G6jaBfBGLn
337ecvtYSoD2WCjY57N+HiWBgdUQDQ3NSmVXDdKaQQjU+G8lATwv+bAb0d2har2upRJoeMobJ656
sfolUjfmew0LyjHzcPgiiMXxmQ//k5PhQRSAt8ggHr1+QYtC5Fh8GgB8scvBnTUM1XAO6R+HNs1L
U27gBJbGILSvUpTBZUXNkyoi8+s03L5a+vlwiEGgNBCUxq83tbJM454XJo07BkuS08KsFVnKwFol
BUxHZ12vFrTlJEeYdgyh64SsThJH99ZA6uEJZTSV37DhOLcIz86Z/+PfhZiByqnY0gn+wYCvOaR9
ocdEJsAWit/14k2h20xNDsh7vHErwyFqka7Ply4vS69D1gzEs/cwndFSR1Rm4eG7Zx13Pb2eR91A
vsj2o/4d7k6a8tH+bI8oDZQ/Qik/iGzOxZd3OZ9GvU8W+nKFx374cVoWAVRDAULUwyeFSZ8E+i4q
dROg4VnjRV1scMxi2bcOCuRJbX6vzKu9ao2v6me0KWbJrYk6Pb9VqAXmSAuxX1soQOyX8RLsDiWu
87+V9QkKz3gnZoSnwvxHt1paDTyWjfL4QMWA7yN1HbAvNPVY1XzuiTaKKEsyf9tvN3B/JY124zWT
CwibACdVqWqVFnC6vA4TidGx3yPOC9UhqDqcnqK5yfS7XC/KBwTP61QDQmo+8oWydyiuC+/NKVvt
xxNgeNW5WZL+UPd4qQ4ztuHmm9pfbJYKiuOJ4PkE6fuWkYPIhlX5QNKRqmLlF3jI6g6q2jl/S9KF
osulJvpp9IreJsYUeJoAOUYKglzMoa4rbTolwNg1kaiUPo7l5mXLcK0SujbMFWWGBRaLCfleNqCt
zawyhYjxey/Hi6IAQNbpyV42kQw66RXAvkbnjvc1Q/4UJ5rUo3Y+BfUc/d6QtoQ/MM2DnzZSelhz
wuszJzcVPod7VaEeVJQoYhSX/X+K3VQKZs2qHjRAh3XGV9YuAF3++sWBmfFfgurXmByZIYDa8kG1
7ZqIxa03vBFzHPJOv6aVvwWhnLmhSlVPCIHJxHiCGClZqCwm4y91AzIrXc9bPQNFscMLSg18PeG+
DaO3k99xUA9pn0STbk95TsxkbAAjVNbWBxRf9UedMz2Sj3o8XoBTOQYO2J+U066n+tTbHFYav1rR
9+sxamPEgAx/m5VI7mTLxdi0W2dgRRA4XDWHFWifRPN1KzIxNPHcTykgw/Lm//RZxB8MPUoBtMTv
ZLGrbVtckg65yrTYytUXEVL0eEGX99q4F5ZD7HmggQj/TehQOqyJaeGRkF0iyLX3+6bJxTqZWTkM
E9InS3J5wzbPVE3Pnz95yL45bs7pjKcK5Wq97wYr2xOxkApeasVKwvVSnGdxZ3dD8J71KiH7xG4j
IiU8QzbswZSUR0PukpVOPr7GcqrqOww/EAwXmesEJh0iEamU/ApOkbw8VZz0DcNew0BtRSv4oJn0
YVzugB/ed+9BIWsevE4e4JWi9vIXmUBT/uxNTF4cIDVP8RoxUJyU49US+VYMX+h6zYO0wxW/e/3q
GGFfRTxrDEX4+kwKXlfTe0Ryfled6Hfe25WkbytJZsJO11a+oiZrrrxLilzx9YraiqOSOJ0leUdK
6f6LbYP28aPSZxITy7N37ClpKNEZAsfvjXjI+fU6WItoDfHlnRgUP8kk6pzNyr2cSv4Mlg8S7zvo
ctupzXJVB+2WWab3RwqY3O4WwctcKkE7Mu9IPJjczuTATT/gFi6qOIUy0IeuDBMu7yfxvapNVXUw
x/XHP7kpFa5xaFPZLGgEyZwXZaOFNJ8gpmEjnHVUV8Nhrix4J7xLYfZ6r0+AiYhRCMMbuV46k6ew
DJLx1p3eKNSDagcWjIFx0oFXKM1MYJkymZpAFr+eTGw2up4fXuKo/DLd7vUiZYlt18Xw78+btiEv
VZCl5PS6ecifRQUmuW7wUQLJ5xxXco2P9v96725mgey2TRdWYXLdZQ1V8zsnwpZhINsLIMM1wT2E
Z/4Jlan/b4Zsw+9yMPAEMlN26qzCpzctSH/z5OrlpY49tjCWSpkqPM1l1BpbaAbi5nfYEoXMFOeT
3jTzFbWQ2tmzc3FPkORk9SqZMGl0agAeyQagVZsLeL8FxdQFK3Y5MgwzIOVV9N4/ouRr9BMhJylB
pE47x6S6ncVe3PPCxE1R3CYSUJJWb14e6OnlbSfrR1jTCppWEFUstCgOAU8m+D5GCqWe8zdILdlj
YVMbKliRzjsBZYMiXuBCjZYpJ/hu4pdE+56Km5r72/sGlwpLh0Sp3qFx3/QY60or8+nqNxjRVqk6
9Pu3EvIRyKCuk1fExvo9V5Zs62RrE6CxOL0NpxrYwn7PSChgdL6XSH+DfuTLAaDxXlkaM7r3Sr5k
6FbBdl0Bn4I7rwYV1cA5kPU8rGxOt1WJao5O9kG/TbxPqNPdrG3ZlEwSzi7J4QWmqCjzjzewXt9X
zmletWZ+HZMYVcLf7BB0zap0EO5N0XBbpxu+e+h+OGrXmFH0vlVv6jXXgJVEZhVw/dV72W+J4QvQ
7N5/Y6Hr5kpPZZ01uoNwTFORiT/PwJLbPj2fBb5Gupszp4mlgz5O1srWhwUzJ4ykKwhtQ5tk3ftx
EncTUon2WC0cUTNxeAxJTSs9wFPwNskezNjJ0tnXdwNiJI8kUrRZ9oszqKoasW8PcDueaSwjb2PD
JavrQhmgEOCBAgCnkPTno9NGlcek7DcPaq6uhwb50gYY2l2UYPMAcfrREJFdP8i3XffmUArvDNEA
hAnZbc677LlBoxG39d509+AoCHpo8BYl1DjMsP2+nJqaY56Crq3mip+KpqU20a6GnkZtXvPh6DVO
YUd+d0dSZUBv5Jaf67F96NUK/ZHgjMitGyfJzi1QzZ58EBcqYFCtNnceVpAtoN4bL9dhrzCh0nHg
MIUuDgdLdZg56MsdvfuRWLF8b/1Vh+j0J0VBvAUlBNvU1cM2zvUBkKhgPplG/6+J4+BgY6F3zNs2
E8aTB3D8gLnt4PtbmDbg5tbe4C+2DVb86cTrTGw299kZM+ygqVuiJVLzkM3HoqyCTYi+CnYwTPK/
y/XPY2wobFm0hVk+oUY6bPKxJnrs78fSpKYCsvBkIpmD10jW/Nm01hhpmD0uM3axfPe/99ANehUH
7fpJUTnGpOTayowtnZOrndV6huw2x86n43VyZuL+FXzIcUPYKGIC33W3zZ5/zbGT9xlK1SpYxlnH
/ppFj9iNqzCviDzyau+llMtjcfT6n2bb4gi2xhl9FcFCC/+KvGdaUJbalCRsmC2nUFgVEASgt4y+
q992c+slBpmDw0taTdwawRL5BBzSYHPcW+59Vk5z3x6WPcpKOwhK9wp+yXxcID2zXmFeLpldmL0I
Y4vWB0IFu1Uo65b3V6dmSVgMHCaGvZQ6MJvS80iCf2/oDacpLNOZkqa3DFC4XV0NkQD2EHqS1Bd7
Noj7ZW4mBzeMessx5D/91heXx/RqOy7/pl+B0XfW5qN+QxiwZWFDjCF/5T8+qXxlUdetQuYt43Qt
AdGhtGnd35GYO2bFGES0k7Da0FhfXhFYvkTTKxxDOSQe+uo9iYZmrRVQdW8iYJbqjDWytxfXX0Kx
3y9tB1FTg4/oSo1meuQSvqFourhD62tW0W8CfImuVnMpmgx803NJ/ftSoVsfVaWsKjyLWxWfRl+r
/c9DfsPalq2CZJWdnxy7Co4PtLr1oeDoO6Fh9j7ij5BvsJqhp2dD2Q1Pp4jdcY7GRfx/s6qpYfjF
Qe+EpssNScsqF1DpODQxSWFlVnlkK+s/JobFp+IjSWFUKJ93ppkLcDIzymZQ1YKHLaJLD99JgfYX
RLXBjcqlicOhUntYoWbOq62SvBwrM3+r2JSKS1zfoCW7diS5rKJDairlH6b07Df6sARnHgdtyvvs
wzoA8/6IMp5M/54p1AUnVhHKh8oE9i6raHwMjr4vLijAGWPMOcBYj2eRL3nf8yEzeQu8XrFwSdnp
9soB6+nAGNVBfaYMJRgoINTHd/t80sdsnt0dnc7OfHM1iNWo/XxkeQLX1Z1xYKIz2XxkTQbfjTUE
xV+7BFWCJoboXsmxldrKomYpXCq6iDGhc4m3/x5J7mxNJkFWobhHchcGgjsed5wcsPCJtD3o/Qkf
mPnoh+6FPdiK/pHCChdbGItAyYAMzuGs9moowM0jahLcRGlgQSQbRtUc17x3Jt/JPcj59ROJM9iQ
aToEB1fFa5ALLIMO990eT5C8x/f0txA4cFc+gSDKCpOxA8DgX+Cn1tSto/VVhjpNE3vhpRdWgKDT
QCBO32bUWpGpNSZ2mALB79qTAf1gtX4oS4PW/yqjNkA7vJZ5W1Ep7LbaHT5Kd6K1KvFZ7K4zsCnD
bZB1asu0sCnXOGy4tGDNDu87/W9YKynMVtEDan1nNPZh2MnYo1+0HGnKETiQCPsk9SD0uhlPfGET
GzUd30zy2VdFsYvHIZyc/oc5ShZvVko9KdUkQ2wbUIH1VCvkk01EaWm7JrAVbpno3YzlDMAxcTFY
4iPcZJm/Q6fBXllaUXtqMfKn/cLnJTu8UPqveOFrYWbW++8K15jKnYwmwBFiM8u7V28cWF3vGiPX
JpR1mIcHPRnp7ywMrNWwxxz+LOcaLd0BDeaKUHmmd1mcr9QXopzJ9u0Is+EG6+Y+XqaElZzev470
SbvcF+pk1F9KhDjfJ09zIAdaAa18yWpo2n920VijmiK2Rntt/OXM3MA1/RLDKQWGd1E1akKmHZCQ
2f4+jnSPliZZl/6HNYXqLkaKU3oDEnHZEpIUZDWxPr4ABMHG4vDQHEM+4TRgbvC4eeIX9WdFj3V7
9JQ4FI/fTQtLGMHL3JO/PbRYkcJaCbLayzHV0XRRyrf9H1f293w6M6ssFbExIOMRmgFGwJDsURJb
FMvIjbQhgOCeKxQLnZ0+NHGpU2NmPTnPchyDzCA1H1/b+ZYRr7+gyTXbpvU7eC7ZMZJ2XRpVL012
oAMm+Ap+Oid5SwtFA7qpEsaHLlR/Wex9JmnUFKAj4Do2xCvHIm7+BXkOzQjzXNWYxFGZrU+xtA8B
cCpO4uRc56S2eDWb0JoXv0SKypg/JR99YVnETpC9ZFbb0odtnyYL9Lt+MB3YtqHFsamqAvpmUSJo
gpOupM24T7ED4SU7H5kcB4v3jLQ49hZEOTgafERRw3hazIZktU6bZqJHU8WeC4qMBJZ3OJ0S5wiJ
4sT1FewY4C+E8itTd80OUhYMa/5nUbBozYxNnBheUDfF1L/kfSUnXQstIpO9BTGF30LOPsxEoHrS
TKbn8sSq7YWKdUgNBFNFr7aBhrCkymIvB9YHF5ZDGvJ0zBLAeK5vC59vIKbjx3sO7YVubeSKs6Pv
K53T+7qkHuPULU8r6TksEIfIQwPf0P5WFf9LGqAxv+w5THHUMpAxc978FW0xJ+ATe7ey+rwWmvXi
EepaB1EwshLp45w2tYNzZoNEWKapASif/ojS2VCO8kuw1rLY1obQ9HVA6xPadqu48FBPHQ+74tuK
wOY37WuuyKxSp9ipLLYPtUem0F4B9H5QIGQoY056nz1XffujAGuqtlHOu/VU/egDi7ksi3T848K6
afVhRJVHwyROsV5zaIQgO7j7rOOJxjXj0AL7J6eTOyZQSfpg+lyY/5JL3OA3n67CyAaJPle8F2//
yXF1TMnDWGiz+LJ4/tpKAB+ep7+25zmewAzueWctvyDd81E/+vel/qf1DchiMed6N+zOnmr03lAW
/jH9UKkeDdz0B46MBKOJF3iHsGkeR9XNtMP7NsrBZx+GQSmbOKXxtRROPJZQnnh9TAgyfmvubEN2
oTdk+AYIOtJPiNDnb3/ShalJJowuygg2dCMgfPcFUWWJxYRGhfx1NK2pHz4G6MYl3FjqFI58V5Yu
P2jjlmTfiJM5gsFIMNm2fXyGp/3p/PIDACDrSqDTfza2lc6HsJyStW5rX0XjcMAazq3s0X7UGK35
njjab0JAtar2KvLn7iRtuSVpOHX5TVjSqVVZGLzTz55zM5rqgFmwRK7b1PGwxswDHKU46yj89va+
M72ncoJecdz14w9WaKoTOQSvkijxIYE9PUaSodR/URjiys7WRHYmMatapl/IrM366IouVihpw0gE
29Tqb6mKcaZDuCCkhpvjBlLz575PFUN2A/J/RwlRhTm7R/5cjoT+bZrLVuCdcr+pGea4K7U4LFEk
OW/Wd+DXpuSaOzO8zAttgjTxwnxuiY5yNn0nfCPigCczr2eG5zjBKRjapq5tKn59IX+Fy93RxHHd
niuH8uTMAyBxo3V1e6+6O4Qb3WsEiwGKM4KdCsLvMMOsLu1rQ9FUpJv/OuRdxyH8QleUiMl74kEx
Rdq//sCW5pWbKFrcNTDOzBCOEtzvwiu+ppCwDL3A5GBzzqSlS7Tj1F2nn7pYYQBFRSRVwS0c5Y2Y
xxWfniwfrPuP27l4JewCuzwmIKgAhAnVy5UOf7GTQzksgZrI4VTOXg74GzT8hUv6YYSekgJsLrdT
ADdqiVgdtysoOn0TarcxZemh60uYUE0Mz+X3d7CmPi+PV1oCpAjEgcZC//at+lTlksptnpW4w6Zl
geD1tbQWyTqm9051zQf4tqKTpqlOu9tadafn5+vmnICIty9v02HBRyOZ2uK+vIOEtGCKF78KEmhT
cX4+R2FpikbT6ELjUAR+Wr8nQbFSCirAhNWKx6lFhXLrPX58FL0/fr6iM5BG08HFIHdG1Ofy78Hr
T+khaBwOSxE1E7++jao/IfrYlC7Bj+PijA5ivaC4nBEJVvvBPcouiwTwyh3rO/fsV9BfSsN44Q89
uX8CsJA5/TF9O49W6PQ0+g0WNcC9hHYgqSnKpGF0AQzimofBQc3g0M2DS4+TUDCVQmAJxsIEc7S9
JG2YnesYAaLnR4cUUWcj2FxqFkUNCgEBJRKpjWPZmDbTDgwfRZx0H9NWUzksG4buj1ULbeP7/eCy
4QihsOnTftd6jV/1KZHhvqMKaMt2lkBqBnz9OPH8l+8i/1tscn7JjuFm0B2hlPeEln3ve8PTui0v
O1xoNfnmcvOYS1zXTEsMo946kMiP+XDahoVHYvR29Hz0lkm0dKsNqsIA7Fjh8dB3pMBQ3GPvxQht
1F5DhTR8jFQF15PXinIGZPg6VVjOOQlkA/0AzmC6RQwLvaLEB1ClayDzl3JNs3JR/I38ys2DtHas
KlTJUmJwSKpk20eOu0zG4QM1X10HoxmER4BThMGhF9XfzVetBzNpiDxcY5rypE93ly+JaMxL/YnI
er1AhHiOp+v9PL5+NZ5Irv+biqp1na/tAp+CroxH7jUiq/PkUtq8iajsIyI6x1jlE8QdLgqO21CQ
eAlW0oQd+z43dsOMBX4l9No69p0x5G74X+GtUwAX3QaWvogBeyT8qcPECATrLU66fZFTdW1mGydz
X7spXsQ9VrwMCAoEWk1eHyt/+W7lbd4+5o8o7kSI7V53f9MvWgE5essO4oaw2ODv9qrGsgM5JyVJ
54ZojqFg/b4rxWr9sxkfNeBf/LEPdG815RL/iy9yeZ+yqXxVoWyuV2WsUuFBNkiv0CDOtebdN2qC
PffE9o82SoaKCSilxjcKzfkHobBOOpulHY80AYxraMcq20BpaCpwVXcgkR99bdQcCJsQUhLY9/GW
aMAwob4oKVJ5ZQgMi5uLmP9KL2qSGZkYi/7tyPcsf7mJmDeSxp1GWzQX8E8ZjLtVsd+8Q1/NSRdl
rwypTMi0Cq4Lmu7KuI4P2BB2NHb9Rp0g171FEZwowk1IDQzj9OSqSxmuMrbwnHdMLky6q7FePkUS
+jkeOoXds+5L2mnTMSRsQEeFnCh+mAh3Gjh3JiHcUbSYHwXj9vDM7IvVH2432cDCUAeUnEMZe9BO
OVpC527TtY6WVxAgx2nIrdP5ocF4AFSFvjvGbVRXsBLie+/7wR3dpES4ekCj3PxlQzkU0SU52ega
BdPdlXwQH87nsro92CPzn7BUTmD0RhhSQIcw/ib/4XCo0LiDhBv9Yi8OmrEPgmFWPUB5agMU2fzb
RKYYoYKyXzh7WVEZF7C2R7ZV4XoPgBWa2e3DH2ShHLvFIYaEmmSB/YGkUCcYwEub9m40ly7Wfczs
GpxXHjKvx/U8wBjxvWCZ7FwSYQ/GWDYZGEbw6CJZyX+Y87fCiMdQqsXGLT7AJQufSy8XHvXlPnFA
p+9/v00bZhuRsskGcDf5NhEvaNdpQ54yUTmm8/j07XtybWTqTH13VCxgofciS+MVMx4sO1XJNMd5
Oq/bN0Fh1v2WMCRgTWBGCIGhbqMw/qv2O6UJPOUGtNk8qUCOtBxG8N6m6z14uk+qCzgQFv3zRm6U
017WWQxFl7OlKHe9iwCoRfXoyz4xpq2mWBoAzshnXfzGbBHMvDF/wh0gpcDPqB0iz3VeowRMqEHp
DxXfj17pWu/bFcH+dgWfIQMHwKfYL+6NdCSMgDBFadU0/lUm1CDzfrLa/NwNrBBpJTteKSPKi5sr
xMIK+T6OLB3+jlYBH1d5fjCY8KuUdV6PKCa0FWKOQbN1rByH4vWfFn9YI2vpqemVkNKlWxtw98t3
7YTmA++q9jiA0Y11M4BeLeI7KpVoZf6HglC7ohm3wiczIXAHPljhvVifkz/P0qE6EjTkTBtopYrf
mXeOcjkwpVSMNc3WmZViUiqDsyCdpkMZms+uJ5EqnA9Gtsg8OlyF4DgbaZhqfiffd5yx0UDRVAfv
nxGDfsP3Zdl8jLWG/4n8l/qaGZEhYhoPgFo0fYBs5Hkjp8JRO0t5WFQYdc7/YEhOvYxOCy8T2wOL
+rmoF9E3WWxuCDoIimuXfR2e3mdottzPBYpEu/lU6cqYnL+GLgj9//BFDj191Qb4EAobWzWIFMxX
WyqP1VvvhD8tBwpS07T6LnLV1W6FNjLDYFRFM/3a9c+6DcbGVgu/CaoU0V3W59W8PLgbgRP0H9H7
59xG9vn+JF6KVTemFMnaITTvfeM64HG4Kda0MQ0oItadwlwUuERJmu8nEtC4lHbxMt7h4LUQPkao
cHuVD9NJcuZ1rUWDah/RHB4cuow50hNjJOcxzcKez4u+02lmrx8cOlATOX2ulxG+R4L+EXmYP0GA
HyyCznR9Mjj137uWaYw2NwZ+MBcQuUlbIH2+ghW/NDL1CsnCF7HEwzdyTSBfKNLvouJuwSBksCy1
YQFzs+CwFBHX0+ZtkWBNRPqt/LhLLE/IFbR7L9J5Y+PaVmKrccVwlG6xp5NRMtewV0s4YL/ZTtHK
wjwCeV6zUiP7GjvU034OQwq21A7Ji+kTq8IXQFi+4OC5eE8g2wlftMLeP8MouoUjzqEcMRfxXXLE
xuvDuJedd1PYad79B+7Nf3r9wIH9BY6DAqiaV++QY4n2NVQo8Q2+E44vu5YVMolrgKSq+P1vW+17
JPjb23Dfi0czi7NPrN8JtHStk+QiQdZd0LjT6lVaSCmdI/Ag64PsANMCUvXqzuWHBv0BZkP2G1Qu
ea0eatg4Y/pudRt91Lusr2wHqLekSoIh6EXQzZWcY28O1W1PaE0FTPJ4aa1APknMcG2XrORCNHet
WnDE8a8vGidAe+fjWr/YexFGVYcyHud84wjEXZtYo3ZpGTdg5FplBM0bZqmbxOD0qqog+Df6e3LE
SH0BMCF9I+tMEO7I4rbcjw2cy8dzJuJQFDLI8Xavy+lU6FrkKRWNZjn7rwzZPkBNAsWkXK+Vo2MM
u/V30eXNhkCSnluY4kWdI9+ZAfeZyF/lJ0yVhUJJuY5z8KkD4O+w7wx4iVwLo+kJ+y9KVYkPm0sz
6/CLq+zdlqnkWPkqzuD+ZLQYs2FcRgcBbOd22ssoqOiM9E2MKxWGz8oNpXSQSeIS2RnO99COFBk3
FgwnITLdkaTpSa9R9J5gTwl5OlKDbitvZ/c3L9X5KnRj6x8BDKEtCOUzSH52dJxde7WZcBcJ4RWU
9Z9uuRaQYiDvAjYcQDFeMHtxsdaashYCp5J8HuLkXgB7GLGPKEmsXpUcn95GWavBX6d64jWQtv2O
JUfm1AdqsKL5CqGc9MSSl2mJiB6FhTkipc4NcognZup9LetL7eTaBwsFB7anGaPkQa78AgF7/HbQ
pRtl1jz3q5M5XccdiH9whn+ktL8iWXxRJmho4W+GfQkhrb0pCgjGvC3HMzGxJhPwDIe12kY3a7Zk
mO9hipTjbu8P4kmDQzvYQW+yXJKLgb9blX+SNyA3EUcEpDBzBQvtsH8NJ5RBsEfa7YZB3thUQJQg
csqAGoqHpP2rrUA8GFfNcB40v0BJauwvLrWl/96Z4LokYuAuXnfzQ2EA7pUvmVnf/bojv07qmizn
bIuSl6f4gPDJCCn2BDPJXhFJqFOjSYnWJdnvLauyqOZXMSRhfX33dTmILR6B8l8U+dVSrjDNPgG4
MxZg4hyDdYI1dxlKbAM+GCIN0nfxc0VYCBSC/c6B4/S99AqH6ECw/rHcWnKQHTe8O9KLvUz2LRfG
qLJK4tXxtknGVpqURD+Zmkic+mUwlYNwS3cxIOj0vR1B5RGELLVrwqf60f31TjCUMvRuuK5zrqr5
sQiVFkxkHZEd6IL7k1uX7PGzURaXHNJZAeO0J0iFbUrIivzZKVzOAYdr+WIB7XNF8PcyKHjuR32c
P1xIX65iIFPV+fqreLuGiUknt5rjofjjE8CN/A7yk9LUjptaRJT+Yg1VTwYfK4Ea/+oq7XtvmCTQ
Ch+Q7aw2rgMdw6rqmXwZwd1s00ro5RoE3uDn1RfTITdvEnzA0pq5G7Vi/t01sypXWtK6YuKx9hx2
YEbN0FZOITCdYyhv8epXrM081X1m5TURm46Uipe6HN0gheY9yu0Jr05CMhlSBisqqC7GuL0PaNLQ
IvMO7tfv6W7K8o6QYzK7/jy9LoC4XObLmWctsLRjBp43XRxOGkkrzQbcp1egIQtZHRZmywM7Vo0G
SqiYRP5hFjKfPO0vzN+lY12M0BQqSssj6MJAR85Jc/TtjXNpoR69NiD1JsSZosUi5iGj3lMTvw9o
NOlQIS6SdhvfJT5bebbpq1BNV1Q7pW21jky9my+vi6DXxyBfN8GBsoNeJuKy6FZFQbhyWNZSKegL
HKtEU/j8cSXEYeay7ZBBMUjr6B5Qfab+4ZawIoTbdFDJIJHF1iq+/UX6f6ubszhxRD/C8PgoFneq
ywtNsVsMAq3yuzIjVnHz7YECgy+m9RrEX0+7TtnA065G7wXCmurdOD002QuiBB2PoQJO2PnU3JnR
YYYaVfvvdGtiuJtymvW8cR5SY0BNB0UZC1ctY5YEMbCUAZNsLD/Ac4Va0iTiMA390XrINPp9PRA0
QRQ2BepR3rrbVTGmaqXMvDknGZ7pM2GVn3YNTdtcr7WMjOKv1+wOCtHdW7J1HicKNSJof3qN/YWQ
K3PzLzd+m/yNqRtz9zguRW5jhoiSzLfYFQITcED7NJAUQ9PCsQW7yAPzwUI1noeHUu5n0mWw8Io0
9jaDcg6VrtlcYMlREcGRjFJTFrucgDqwmYucwyT+CWGZp2R9rO6s9429d9IfVwTXJp+WFd7AS91o
jxWXzY5iIKjI6K292dJYoWFnmPN3duRdWa55ALezeowDBeMUk3j6B5B6pbj8L2AqIu689QYY8Z3Z
ofdaVS0NdSfXp3M2AFOcJ2Z8vq7qBWGflZYqVRC+UiAx+C5VTiapu79WXsjsPJSVzOPmpeGEGymE
okQ2azg9EaTHDqxkj/ZZwCFF1Ky2EUb0DNHOy6iTNp//5YBDgrHXWmDO1GNUQVlwf/K4xHIT6eJK
l/IiZ/Xe/cauv7n9NA1h43ZLRcRpFPjH8Y7eWncgOsQ0y6IqUdMQU+weo0nsOsV7oDd4vzf7CLrb
x1eugr1d0K2577CWnfqjA/Z890gmnrHZV8Q4gHTybwH+ux1nXq67J/QptDzg0n+m2XfCBROc7u4u
AJcm253a1ZdHD3nGV8dW2cgmw4o70t2y4yDy8MdhtstsLIVzBMJQrzRIxGykb2+sCFFcBLCpjAXH
bRfNBW6YfbfeO/W410LqEGkXtYphoB2XFPpsDw7ujy1+alnJ1gZPmessMdh5JteCLST7qXk9qpPE
WgKFuN0RIrrjpOAyZsOnLXqslB2qWBoRDiUtanoM1cHC0jEfDOBub0QN/9yVNO+x4hSC9+dvkH3X
hXlhVt3VmBfxAew5OWYwTEVaL3XCbuvp0wf0qTiK+j4FV7TBwxh74Lwfr80R9Dy1DDZ3ZnLX7OKN
G0Dw/f57NgWVcW03pDzQL9x+BUbEwIep3ANwzdROXWQcLZNGI/u/RDbA+qYqbl6CITAEqoESv35b
SCb/fp9dSp6H3oWYkcoX7X0EM/4lcRD+FF6902xyEDkQ3hdSpf5jHF+okafmXtOwdEcQrZY2nUIt
kLFTlriZ8axCnPj9lnoX0quERFQ4rmZMuBQyn/XZi+hhiblmeNz6pf60dPdzSYNqpuMHz2O4T0XO
Xd9gUrmyGndNKePb9jTY4yHnkyyegIplJeibFvFcMfCe2fuy4dK3+VjvH0C9PeHWUZGOn7noGT7L
8Cbegb0cv1PpV2E/yQNe1KpiY1IQZCu/nIv3uRpdNi0dlTIDs9Y3bya4xOeWhZQKwFJ3pAs01BRT
tlfgOyRkI6u7Vwrm2w/mEmOBli1HY3BDE5Hoyr2mr0GCxoBYVMLJZskeP4N3wER+jbIxHnu/A/dG
V3/iVT9shoKQzD77FqqGKuKxKAQjytefetnfPFZ6uZ2l/bWTU2mdCUGAlBLO2RKCjLHZthJjDuK1
LRO2AfxsCI57idVVcZIO8ESjFd77xQLkF6SGxvctCShdOTx8x++Ks4WFzJiMZaSTKl3MoSu4oFpq
4yWXpxCdTr7njznr96YNPLMnh85ENDod5Umc2dZHQdN6uHl2ygkxQQbvQ32AwL8WgcNRlIHfmwoI
TT8r0iYOIA/7baedkWVD6zeFBSqmxwcIqV4XgoidAR7LQs2jWKqJkqKKrPaey87DTyAOYVZFof/R
iiUUuFZWugr4d4MxxQAFrfbHzsqIGCJzhMSx1tLw5qqYWc6RFU5Oj0T7mxqztoDyNzah2eycBjam
LRog5XmaEL4doJDEiuboxnV85qElBk7yXMWLna4unRIAb+B9GrwZAMw0r27DdKjkb30RgMWPYyES
7mR/aaPKkrS356tD186vUPsBaM8kAHuV5vu10jBNCqi2drGjHjqNb4QsMsSXFJ4G1ziiKrQ6XTqT
XbisxDzNGxbM1KEjANG87/PLzHM2WCX5tzLwLX5CYj5Hv905an+K27tMzHj20xbe2ZmuJyobjjco
QbV0nJF/boxcJV8S3d+g8lS+ZhNBVp/szLMVfcoFyI3pUvstUiHJqZhmQfaSMZZgDAMreMa+2fkh
wj+Bv+xIg3RxeNIDX1z0SOYMdY35p9V4B4l7giji5RC9JmLvIHCzpDDL9T+Rak21uxeqE+f1Tuez
L6qmg451FDGGjbDiO4Xw19wWpJhL5Ngb0OVUIZcXpRWoZSvPzy5M/N+mBD7hednKcUee4ccim03U
0t2/Sp3DhFxkUf19m8PgjG48ScmNUBYCtnGVjP+QSVd/l6z9MLy6rDuIgJqu8lBjOu8FXnfvviHb
bvQVC4On3v6r9dz+SAymle622X5n4ZVfJKJz3tZnqdxyv68kck2PAf3cqLtfILzPd2u3ifvtn5Mj
DfTDeEeoG5OUBWD3ipre8R7Ekh5Ipn/IkuTcCzeNftm8iZfi/we+H+VC+PJdUc/tVPM9oxeDf5ph
zze8ZKuz0LXFJhqU5F/4CxH3i6q7mm61JjjUGb10RgQ2eJweaxR81eARI7OUwNJhqKHnk2g0lLlW
2i2ggKUi5MNbPSBX2PpaBveHXgX1sFXlKQqS6bfaWoa5SVADwAoFLrrmaVlzKvYhIcNPsCKKxJ/a
AqAtqS2IW8TPHnWJq9DF15N2EFGcaSJS83crcG0yQrsBe/sb9PxMv3WMH7TXgak77HxBoXP/QN3r
1u6c/tLSbp8JgmHfSSrRxeAgVLUh6SJy8mUqjbb/FZXLY/laoSYOCEvV9ZaOrk7QFsY8dqQJ7I5K
hB7HRrQYpgD3zcvcFiugtLP6p1EER5fJXWb3hPBFH56hKP0cD8GO3/TKgW31KLkyGByrN4Eae5F5
xUhQrKRN/RiwmwJzcG/rOjtci8aUH8JbR6fhxs3/EB7ndoJmC4odaG/43KNXIunlSYqgFIFrj8UL
jhacJwpk+VP2WA7/3ym703OXA7b1XmKdoSie7sX92LUhrgGGHk9Qeu7vn1tiBYCfK2Mt5WWnRCnn
+TPEN0RB/kSWgLPwz+5/rrLdNIcNQvb1GsGYnZv13j77u3jozl54S7yOX5cYZ/dJLhvasBb4LnIt
S7qObJR5xuXgRe6vCNGFlt3lqeoBoft+6EUCVFbBpeWm0qtZioS6l7KDmO3sPtMqZrWPPXp0xkSB
6RdXc81lfkMPciwxLgTFOez1Rbk3n3xUz8fAZGTaac76Ty3qqJVo37fwdGORDxQcyfLrCq4Nd6CP
8eALqcd1aSeJneV8uz06IcM35b0uFSL+WeQhTl5kdZAidKEcWtqkLa7dAcn/kDiG1kCcGmvGHfXa
qn1irjO9qhyO4CFY9s0nhe6/ksILBE6Z1quldWkTOG5DEdSyGFwVbM9GrFPgDgCUNezQiEhSHtYE
LiexJy9/HcUjg0YnUBsFgi0C+SKKzNT+o05GL2vJTD2tcuBlsYNddciBtr3aEHu+AYc6cZb8QTER
q9F7WXcZxWkR7AlktPochgdBrRUw9ZVfhdZHooGufJIbmNsRoXJ/32D9crK9dV8WYtry8PQ9amwL
NbEiYqd364+SCg6UqvHVw4u+QULqXq5jBERGKHcypm7czYPSL79KAzFdgVJFKJPCYvys4jHkbvQ0
7/KKvTwYY4nDkj+oDpsd7jhtA+Y4/bHcWf3CtXlvc9Hmm9OyOUv/6q8Noo+wPUxp3wjKA+xYiasT
fvepHfhPXUjFCDc2OYV/XA7CJnaoDag2POozp9ieok2OV0io2+j4WlYzMRT3YP7TrcUhv/4d818g
qkoO+VK7R4AWi1KTGpXsxAGK5Mk7D78d5hutfgGANT/WLYbShz2C4iy/LnJQPrhQxn9ovXkkwNCI
Glh9J0RZcV8o5e61W4xA79q03Zyw62LElDj/w67F22WeFbezMFrIT5JfKZsZd3DtIyrrslINdkoT
RV6hjgKROquC1vdpL1ZvvDiXbwQGWWjhYCWl3AoISvV72vxOyViceZW9p9eA4Fahu+p3rovuxPvl
SJ0LX0tOduZXw4r50nw4GsWijnpvVOtagdK19x0EEOxo1Lm0v84Qfgp+bamVmL2WGuc8MQ9Od3fa
yRWl/eZBLLqbsPT+BegFmyST6uDZNlkXpKCKL5SgOUKGD8g7Rz6so7i3djobhGWSlLkF9IdfQvfM
TlRsgF9GNvm622P7oafqzVkmSnGnc5OlQRWCPuyvhznoVvXrBU4FNliyB9WkAsQBTOWOxzgtH+jk
Kwlh+6ZYkDDQxuScWaX+cwQY+Tie55ati38u92QDnjhbt1WRfrla+Nl1SHn6m8MpUdqZ+zBL5A4v
e6WfvQcGpo1hFsiue0bwaRM69/8JnAg2pJPgQLuTklwmVXEuLf3p2ZgeNTrmAK/varOnuqkSg1k5
nfjKmUBaJBhFqHH0m4jrX0HFqiQFt8d9vcDFTM8plQeIY2u+S3UHIIeXhTH4xmvWWTo86zPJYY9F
VSb83LM1DDQUZH2G7Ei4bBRJr31tszLdzBX0aVMkdoyPIDoF1Ti36hxbij1O4z/femuvtjYMRXcT
F8XWzmraun5bau0YDtTolverTX1I9QXp7rX7wIl9A/ukg+6nJyGZAf8lMx8ygha4CO+SvP9U071J
ffE3Qdw60RgMINeYAegmAX8X3Eq19fs1r4/LJwa+RFCXRIw5teuDXIhenoFULdSKli4BT0DuPmiA
zVqI5D1+MboPitJQp2aWbpN25+gDGAULsDc786te4qw0+NcSUnqAqX9X7K7r7iSMtOPigPB3xXSi
LoPnagE6C770mM0okHieTZEA5OorsKU0+dhgPQXr31cc/yorByhjaTWmEFwLqY8g3Qug9LksD9+Z
2eEUkwjrR7q03nqpURquplM84th+7LdL1ac3PstmG230MNvWoCVXWu2Ttt/sKtzuk71KDFKH/Qtu
W13L3RO5O8Zd9AKsGGQsRJS6QebFhMb6qry1v9XWKaWfAQhC1D0A1TWWcnNaM/yQXf1TNxmzJm5U
ow/RvCduLwPt/Ax3RxDgGnIzBgr9CKVFjY2m9nJOFWZBtRrPAWtly3coyMcAM5uCbD9wn7DwDjbL
Byxg7J+yzg4qGP5Xs9Q/bpf4NvfoGZWgIPUbGm7Jo4JUvgmlDO89fZMR98Iznb4UIJNlcBkWZbCm
asmRTq3OFKMWzrZof8FYYI/IpzN3gTkJXkTVlWysbCNIoGMYCjDQs/AdmaF815MTOdnMvmXbh+Fc
ETXS5M0PSLdvkESbUpBP4FTMVZ0Y+fT8qpMDpxw9/Bjglxucl9IoTjezNfaYnvw8EJpERHem/ZNI
BXJybuy+BOmZS6Bue8kU7McvHm2BVed4IVhJreY1yawpggPmLj2X6RhXpC58fFRM7L4iN6LYkHFG
NNlFq2oGqiW7hp9JeD6i2BWwbJHAGPs348z5yn3wTxCqdcuGc/WzBINAs6VYY8qzZVdKQmfj5QM/
MnAwofN+QLWLlKbTYXmSdUW68AUp4lDnQFpgMpGPjKhM0B+YVzhNWhD54ByAssV3KU6eV8xaAk0G
8hzTmTEqiHjhSZIQBfez2hWop/aAhqWNLXqCLolQCQiP2hFJEcHeYwaS8coqQtJA5XQISimlBoWE
PMTeiogxyLM4OrZLz2WWyxQPr0ASEgBApawrlXmqo4RjkOqZO6kUYI84PCyqoxZz8xgAGkJ8mC6d
mITN96leA3ZLUz1ZivhAaAQu6wIvKav1k8fvVLAb2LC+5ZPqzZ3F+W3+n5at4iacUj+rImeRX9ky
4kHCWQnrBTuUL6kPCUPwbCGu1ZAlGPWE4lA8q7Lqb+d2+YNP/d/tZX4EhKOGXnZ/YbQITo5ehLU0
Ogu9PQK+gaNzABJ4tzWyzskESKfcb7pAenjAT3jMqJ3FQKm3lGdnsIPsyOwvBPmlG/k8orjGxRGo
Y1hQnS7RUz4wU3g5edgWBxXpJz+IMQZf5sMAJHSKHMZcPNhH57l3vO162ZURVJjzuBMjZ/AAl4U5
nEBa/6vh0C5f5a2o/1ZoTHk2gv2Izr4WyrRKUHIO76/C4H63JIrJiWHv+/K/lKXk+2Y0snXyeAYj
NqGa9Zo3goEbnf71kIvIsWTHW6mYxFD5qhzXXEMY6pPo3+QrMC5M0XQ+44O2v0C60RNhLCKib+qP
teFLxSdGXdtGWsBjlppRYKBriEBA2DjXamxVMFmtlG8hXQ+O3xirfZavSO/I21Kj0UyL/WaAFfW/
IUp4wk8J97pZLq9gvk0BjeOqCpXEhoMaco3L59ViwAjahDbTQOPSvWxQhaLQ14qXv0cVxuwf3aJM
6YvKpRL7xEeJMIyiiEh0AjUVk+ZfEeOTFXRmzPAv+l5m/hz0DFYAyh994gxzVeRqv/2y/SUobsB+
JYYyZaNviBTdvxw45TMs1tmADAQFulU3GIOW3XahXH/G6HlLlq9xSBAXUIj0O78F6nt9X88pr45o
75g1aqDooeplNaUHMwzcS05WxMHt/ohYXuyvHRqZhynnFgSBv5W06qBJqt2o03JTh5HAxPNOUS0M
t4WliZ7z1rSnQ7m88yG3nc/BdGEQR2Wo8219Tn/B4HEQWm74PChGCVNjpIT+ACUxgHf2W2MRcs4s
BcWhgNtAPcvqSHMeo8NE4n46Jy1sg3LxU5bJPb7w70Y5RzZ0EEV/tyUw2NIlGYZ5cKFwt3HVJycq
Jw7jt3kP3E5nxtqb43uYz/5mSxZInBBTIa8rhLgCAognLSnQSl+vC8uiDDh/gMDOldbbsCTrU1EY
y6E8MciYYgVaHFUjx7z1whjA0tBfQ+kRzbZwp4QfgDAHTQ/6KEg99ryM3lWqzRS+2Rmx8Zyse+9S
mY0Zz4vKpFGRm9X8kpFmjdvc+dTzr6CX6LsRmH1E6JawqDpbgIW7FG/u1qbr+V4HhtziOWVXw8vM
0f7b1hJnlEDSThrVDZiMbl9+tmY+XO0djeczofhHvTnLUUV+D2gfk7B8OoCFF2WOFTcUERmL080g
1eMs5FphXnDhoFRfYtAfxMPybnCm+GC09HMP8yoYeVTeyim69Jz7bGzwvhiRXaeJhdkPKJMQbgQN
6VdEQzcokO2jJ+XljpLe3H1ilAf2hU8dRaK7Fm3oj2TD6HCoQsvX2ahmR/2OalXSDNWjm9Sk2rn3
iJmu6KPEkvsn+uTdA3TkBnU9zjXXZnHZpebNMZMCSSk9uYd9IhxS+mGWSmDM3GCysE/GGgqFr4aY
wx9yv4ajCHERFojAlh4kiH9jFGSF5O3bEvwHvwny9yHOp1WiIgzwPg0bs/F4Fxw5Q9kj33WPmP+X
yq87ObIAEEgql6s2+hXVf7LTfMFgilqDKMjPil2jMs5rl4eSuP9mMRDV+BASz2cc82EtmnyzLOUG
1yfysW2M5EeF2gDOf8+3v4LhKhrHCDGZlvBLY/kaB8nWB68/Im5y7lK3UDafleHmsdNHuqj2tLhy
NR/pJ4NPMFkrFkrsxQWHBIyI5s/HqyFu2LfzqpgU5uwi3M/2kU0QLxQb/Jl6bHxKoD2zY0Ktlm9T
rKiuAK1izkUYH8D4b0GaSLJn6UbmCdXNb/lTeUYNfnjVr23dBBoz1ZYA+ebhHn3zaLCWHwzHezw1
Vl2/PewA70oFBLv49Puyf5A7cWasP0YFKFx98VlSaF4VcyVsahRh5dwqvt/djXq8vo5vg4I1DIB4
RIJyV0SQuKpqfu3EcYqQUcImt6Gvci9bP/FN0h/9HxAm0jNAtTKhx3Rsy3lHep2LcE1ecZn6ythE
URYdSWULA2Zn2LFytejdTokGiILfiQlJj/5PoUzD3D4okJmL3ku9Z1PZUwh7lyvY44IAUYjkDs01
FCIJsw2jEWvNseW2QvTrH0bMp8lSu4Hc5oFEEx0OcNaFFTFQjeUTzlsJJmlXUYkA83qVi3FEqpjo
NE7kOH9l3+oNoihe7EUykE91LcqHq7zoKdayUZnGNn8sxLjPDObACihFH4NNfrHQ8PqPKVTwOhXv
1Pw+uZvhYhek+QnKt3sa492iqeJg9h7nXJEsiAxMgzMd72IIoB9sOzBJr4Evgv8Gkg/DaGuiXYtl
ow4mmjFKKiYtgFWFkgkohhLxY6ZYOS1l4YguzAKfX2ngYidKEzY7fqLfI0G7YmgsX9R1LGUt6dxn
KTZP8bgV/mo5RAIoLxrNTVif7N6HhM3TplL0GXz7xvT2+WnwETz4wDCqcX+h4jsFk1WXRzF8j3gv
vAjBrEru3r5wVlETWeP3CUOGxmealEg0WMq7k2mtaUKhs3rr/1Vw02pesY4zbI9RuwcR8+rT9po+
RXYYL6AhMHxaRs2/ypQHd28tqLqNtyNSWm0rMBJxvWGvz2Rll0PlbgovxQ+FXxkhG7C7afChRYPU
1X/D3WeSR8myHzMGpyp2fu77qefl84jYxveOuJkX4uXQJApgX/pt7YqwnS/OPL8H0R6mbdRCwQtD
NQ10hRxOjuW7ZrWIXVQOMrDXS41GQAx19Bk6HTg3Za+HomJy0VUdWLRbD6dBAPhtVIBvgdQEGwoP
B/dmvpOPW+302WPLgKPEt6VFVHXDEFB9ysKr1u2J8w7TMzZzX2QprJczTHVFjeNKPxWr8rQSEB+d
y2vEYDMD6V6jaz2DHC8XLDqKOWjZOi8lywFK4Q3NENKEf1h8WBfJ+U6/9Fyo7HbRE5hRwPRyjulw
wCl7bs8H7NUXgjeAjFx+uc/D+KSqHXovAVlemXlVtCkJ/9fqhgHoyjUfA7T20RomzaTxP5x6iE6z
PleTecrIfWyk/DatK4TgJiVN4dp1DQYAuUk6jXSQcYNyZGfh31wuaLhwaU9n4txM0Paz6bpQAX/G
3wKuqibsKnJJi+CUJ2Idc//2N9sTUxAojsE/I9FgR7Tggyuox/TJrDzd4lyRb3K8kGIN3XqCZ3ph
B9dmIhR3ZiwbFy4MDR4/If5n6/9f9Zs+OCMaBJbL7w9lvU5dUV2uuahboEeShcanQzTpokBndB/4
4AZOerk4ZxiXM62YH5k9NRGt16tXMpNTli7QD20w7/xmY164qrmYktmzdTfIi8vG7Xd5ELVLyHaz
G7CGrllzN3SAARWxewBJT06iVxu9/WZ6yROpOuyAllWZwav1J/MgVcMx/O6LNV75ulgzTlytRHKx
jwhsAdZWpTsWRPpQRRfh0aswvAo4WecQsBilRxWLvwohXzILpp8kH4SXTJ0ZO27SxxFC0CT7guLD
uf/HzUE353GAvaRJpOulCxaWCWnWh22lrllunCqUzI/4M8pkNO67lSgqaZxfhQc88U6brozHv9xW
mmjhievqdVrR4YqTj9xPMATuxCPqQ1MOGw3EZmjO68IdCRZFGTVzEEEJa9SwH2QEzY6QPLpXv51g
1H/kw2M0O/99j7mIYK/H+G2RFshAtercaOnNKo8kU9oQk6d8V3VjBXbEYOzFO5d/hH1xpgwDsGcg
4OFa/tpzudXYAFNWEtlMnXYCrbmEir66UGLn1vrypeMJjaE9ZTfz49jOkso3oLc0kQsU8AVXOaRf
rp3n4W9FLPnL2+de/HYxZQqZZZ5da3NGf8xLp64lNUKykAj1Jh2z4glVrzJmcubSReq8vtYH966F
ouXBAZfNH7TL4lSvrDo9Jl6uePLb2k+TVhSbfOnnwsvPJ4hn1Hcz80LtUFZun9QkHeFigMfjMHGL
48RQ3tSN4nqUGcZiifE8gU1AK48aqleUi3G5CtvsFsS4HYiVRib/bKqxAwz0748UAGuvbeoqYv6x
rNjwxn28qaKzdGBmjlEp52kJg3sB0NsJPKuNf3doR33DpCKbs4bzasIT65sJQ8VetRLG3fatRY3v
gqR+Ir+pRfpNO6u69Du/QUbzsDK6/ojn5zKoNTag9Wr9uU77dUEZbyh4jwPgdLX9D5JcpxDzD7QA
QgLBcWMTsLQM4/6J6yA3U+jAEv27oeyt9QnSRB4DYx/azO8cSH2KNOIc4ygp4deDiFYuaTlkgxZB
FesVy+jIx7NUdzg1EBJNu89puuOkTBLwI2YKb+wja1z2zJ2gv/nJtG+jvQBTkxSMS2QLJ70mk+0F
jqKbHPZZLeWcVBWS3rBrR07xPqmYqyUZepaFdZsdUW+S+FUG7Pk7ANdC4D4KfbHHJkBgzi95iQ9h
L3JV8Ay12taEuWPVL2ui2WGn7D6qj5CBcT/rg3n3pkC/Qj3QgRMUf0isWwmQtKDP7PZ0Tt6DRLvf
fvS/PpuZ/NFgdfmLdlZhHV05uCMpxzwEtzgPD3afR/xa/tyMnaDQ5UZJzD0nujKNLpBDInwM5oJ6
vBH8xaI/GIbTTjGPjX4IttFrb54oVjr2XncVE49i2l1X3CCVtcFMQdFaz7ht0BC+Cn4CYUa+eo53
vDG1d57Dpya5PWslnpt0IydBf6qm65qS2Nmku7VqiJtkNVGk65aCseHMeEktFR96sKQR8WTRzWUe
d1QOFhnlado/cpUN7hBjblxcTM+XyQ3nUQrgYC6ima66ajqe+M+SlDQlBu2zodLJZh8Rh9+w7GTk
j7ec/PJxNlQS83Z8HkZgalUKU1SghFQB/l+AGoKWoiQx239U3DqYzadDqXKGUTMK+S68XFfLZzD5
Sv05IiptZORJzytAHhUY5td5O3QUljxjbLZdafCaFUlqN8/doZwK+sdbsKiYs+C98aBdRoXE1Z4Z
Sac/XeiiSW3xfNEZEVZKJgdjOeESgAnFQu31sgu0o1MdRxKAl1gHjFW8WTZVpiwEbHgLlegAIUlo
thf3OILjZqSqvbnzsntYvRIl5uG8Qd9sZyJhNomGZ9NrgssHhNof7bwj/3Xt0q98eoz1TpGY/tkG
x+1dleFof1NYAnvpstAr0tzdyk+YT3OGZoB1FSo0p0gVFmFil8bd82Ouv1xqKyLBSrWma4mrG6EU
nLcnoeyLRRdSAG+yqQXqyer1VDQB2C9JIQXCvSuqI4z4K7RAutCjKn1pgQKXUSEfkdRprG0XOhYS
920UicJIi4XB28P0Xt8s8+Mu08vGXz4ejtIbnuhXBKkxvjKMUib3Omm5ALKP0RJgRSfpf/zj1utV
Sx8iSwurlvK8ZKMhfkNCELecSFu3PWpe7JAQlyMKdXO7hOYfYXMH/uyXr5L8rJU3JZnR6vpfydJ5
z1WTADdtSBQV4WSch95apgpKPeCW//gb2RYbZ+la7ccKPclKISoiBhCV5DCp/UUClWumdf1CK+Kj
ruglGH8zD4TILPO5r4+WGF9EQA4Hbvh2Jkz1B5YCCr6/HCD1Id/pwVBwoUcU9ndZsjdNlWGHsUiS
uzQtXyowgks7lnYPmYWRad9b08d8U3eVs29icpzACSjz5KXy0noNDs9jU414y+KcSJNxZy1xEQ9b
YW7ZRQXjwlm3LWQydDfHXFd5s7LfzvISAPG9tffghCtkkZyqByxiASICB74TlEw5Dw5tNsmHAsy4
jfMnlOQbajXJN8zbaNBDSLVoU8/sgfTZhBmwXs4omNtAReXcY7zRchDDGAfqITGeUNshnpceMrwW
EK+EiPjMVJVyF+c4aBXHPUerI8dQNi07zkf40geMSbFUmbyedrmAUpDSQuf6RslkZpeY4HWDOm94
g3vQsgaqjNVOVIcLX6Bso63mHXd5KSLelIpUg2WmVb57vNZwRlB+e/bH7mAFOEv5iAWwxMGrtVsk
8zXZb5/NhIImCeH9Ny3FGQUncEfC8krQqWM0tJuyGg2AVCSh4spu8t3HlsO7JNAZ7UgUtMXsxAD+
QXF7zrkEnMhM/MXlmcBVLAeNDYZLewAp2I/t04TPKVHK5hgtSJxm85trqJ2SAHWTnNnXy2uGC0pv
soT/PYkMLOw/c4ri0p3zmQYaekPPHkB6PmvyYXvTOl0BaPbUPvaHwNyPNvFOyZYFYe5gDs0chr9V
SH+LRFdykhSkiJHlX3tR6rgfzC2reWwhpcAgSFcpX2AwU7mIGzAaONFTOyupp2iuFCVALZoXl2HP
dmSLe605TNUaAdBAqaWoRwv4e7RVlebbNP2F29qKCRAqJPwS82q0fNB8A1abxDtB0GfywhkyOdnK
B0bR/fD64+6qiSrxTO21lWmSldu+QEz2NEgtBoNnFxxZSnYQ+xOjpqSnFkfEK8CbNxoQZKFMTzbE
uy7h/eTG4fAAg7vadtXp8OJQVKmQblpZMna4cefnRHhoONX+AjqoYrcq7YJgqigZ+/Dh4z2xQLDS
/gJ/8XzETMukGDzCT3QsEW7oGeLKTiWWfZNJeWA6X39r9t0UsD8NR7eG3RjlrWHrYTcou3PO83Ul
b50JOj1RRWgRLpruQIdYLsb4KdCpEwq0RYTwjoEXezpWD+ySoSBVo6/9SjAIahMLPb9Tcouukgnz
mIAdtuRBYpmlsDRjtnRdSfeqlykiWhTSzYJFDUvNt402gXlFxBEzhwycR/ZiaDd7Lmu1/HMqnlgd
1xNEmmcBTaS3t9k0T1pgJuif/8aBmz9vRF6lgmc69vBbmYNlfUb8//PXE6FhY7S/t3Dgw4FuFvfk
SOn1cTlXw3wa0B19NlI734peWqmv7ZvOzikuslmuyd7psqUj6vmrqR7YcznAnRi0rwMX/A9vLqOL
uuYm/bZdbeqJ6gZGGkkUPaVVgRslis5kVfyR+FmzbN8u/Qao3Z5YY6rH6zaIm54Bj2kX3fRu7y+R
ZzqXtHeT3TXkL6V6R55WD0UD0obVL8UJiOtwuEkSAQp6EjjbCYARUW8N4udU7DowSQx2NJFDYO0e
mMftjxPfOTpAfuSMdfc1GNr+Ex60dfyaYJ2+2kI2zOJHmVHrxTKJY5ELd6Yk7SmnAIOvv1Z6/Ccp
SxaoP0LqWEP/8Oa0Qe08oyBk3w8cWHBa3dG8PB2JDnwkxIAko0sWARIw5BC8L8yTposE91z5vXyi
CbCEYHRdaB7G835eW/pumfz4Ry44wjx6ov2n7tyTBPsz8OzfySvWh7YQfATb5036+sbhxSbuRm2O
qbhUvd6mpDB4yM4t1fF/y8LCYEZy6P7QQXwW8JbT9e3l7TlKe+tFXU+AFO+UFOobATqzXFIOoZ60
qhlUBJ1kb52iKuhPwIGxMv/S4LScMqYyyExs8joi2SfBFHix1+5agrfTUqxmSxe/n83m31zbjMmA
V9spGFVmxXWyc1OF2CVcOTmRlYm9H6KB3CcacKpszLKM2qvul8M5hPfnj/anyWwWvozjFlnMvJL/
4RU0D41NNyL/ulPuK5L3obI/ot9GooPsfaQ9CKrN0xZHp+c4h07ARQxvJur36iZVn40RYxbdrZvQ
ij4S07wi+5UlMkG693DcmmajMI954uGIHYq3Lhm2y/SI+LlEL0xfTXoLyvhSy84H7hgMioxzm4mW
BrR7DhT42cNrU3NvuEVLQ+LuGpkPJFkwsHJvYNKpX4g7X20qeYqwEw+Me1zB918lKp00S3sXGK1a
r9xLXtVfquEsZ6x5xIoBDEm6nncI9Tp2TlzhPpbrt5kKZjTuTegLvqGgloDVK86fbcR+JkKl5AP0
e3jgJH1nbofeYmPb/b6hATHE+atppIf5ao/eXdTFl8o7ZPaFMB37IhIdak609Flegmgz8fJ2bbFM
pBQMFwImWWveifD9pnTEGsUm+oDpOt7+XVbUbla1jlST8BOSBtHffIEJTnLdt9tx7ulzIku/8UAL
T8TxGgjWaT6tZBzMcRDSa/cNG4UxWNnw9Z7YN9GOhO8a9rOjRZXFTca8vOGRDIn/UmPGYUSaWPzg
LFyEwdRNVnGkN5tQSzXVsBg1uax4umZ5qytHrpI1OQTjZESLOCNUkr8qd0nu6ErgIYE0Z/G0LB6+
NYBcinK1Z91fcMIdFdMYrdjNI93Pc0PuzjKQSoxkVEny0cg2KtPQmN+ZfIkE+YCOLQwG4rle5aFX
abxOhgCzTAtC4yt1nSt+8qkIsxlxayeyI8QNqmcCR88UinpVz7phPonyd2TjRzKb+cCDHnSHYM8J
tRDv9JYy9ePuR52bPZ/7PP7ElpM9lg5kA+tXe8aABGBhxQcT90gwHNswCZXFiOP89q6cYRmq/ZoN
AbHwLGxS554mtCUiUnDcK3KKW15PSwEOHYaGgxZfajgbTrJa48hGZ1oo7lI+nyVgJKIX4wA1wvkd
5gywogoh/ihqe91jRdaMHTyUrMgO+Cz1mu+knsWRsMTZ8RPhsS8FGEnPnCuXspOIbZgrAAxRIW+F
idyd8HkjryOGJaWie8L+s0dz1QWGp1tbTG1v26RAE2lO+GmZihf4tYQZfpUGM8/IVdSX7sqB7Xc1
oOqWuujjaN1baZq5984azUxIx9jMGQhbHF6F6G93u9Y7mZREz5h8Rm51spuJr8xNK9f411JudHUs
qpYIDytsEdsbgiIt7a00tkNlX9X6C9/vOFd1v9R2o5K5JjmevktjPM7iaYjZSnmRJA6XlWz4vca2
aUurxKPLECmAaJv5Rci+Y9vOIObgnySZhb7IyojdjqgenoyS4o6s4I0fL+W5vM7PgHybhxUa/tEx
649O0a/9ukZ9kt/Mswr2XT1jQEaemzaz/Vu7xC1dso0LOBEZJ9cDvbkmttpU3ZYI7rdVT8evbAXZ
jEknoZvE6A1gAg5JOq0VsiPtOJANqjCkAoBK4Zd7tWocfedPk/03XxMHsLL2FW192D73bSOJjhDk
Wldna0cHkmatqgYXFYqe+IEqSGa2JE7nqAjCRN9AqNYAYIiOu1aJiBq8cAwT+6HELs0Yg26N6EcE
eSMEifyusJljio+1TIks88DnawaciqpNBx2L6iv96j/rTp5DTvQxX5Lh6nk7eSVeWc4KHPQm2mBF
Nm49vF7kbUkiO1YORAlf36PefsOta3VHSk30HbwjWNXbzU3VSKXOaFCfnKWbl3yoFtJWbJAJWUG1
0GqbhRkCsCI0YkWaTH73atcVrYqYsd0qAkMqbc62kEGzYB1VJNBQ/guPh8J8vf4HY6zxVrxP0vFN
4AhrACpj0vPXMSd0e05j9fCVblog04GbHxBlc7MM0BKYWL7kh3fDCmNwMNQZM1mgpTW+uoTl/vAu
w05oY7I/e0z4mN8JhTJtIXTMqGyTvs4YKZNKksUh+Xdq0RDh6XsG7MCtT+1dNNgJdi3Lu+Ygf0JS
HBk/cx2sjN8iZpcZR/Xm8EdDQVEpRBPHm+bmHx3ddifbeB2yJReGs5ISAJUI5O2ZYGYKiokpol5r
zdHOIoq+TOUkLVEzBXeO3OIVdWS+3lz8tFm+beY9ezuCaO4+Ct0QiMfHybwnMiR182uv+aA2AycG
5W2tuNLkaV8a4nTCP9LszNUCw5TOaa1NfBQMLerqOjH3rOZGSnOOpR9mAE66jMIyceBpedc18P7h
tuXfKOWR1Z6tOE2eXMwH1SKBWCCLEa45LplJ2R2O1WRRi7Z4N4/xKLJbBWpG2lYAKHuuqPijNUMV
XA3ts5kzeYrySbq3m3/5VcB+tK7ZEtG1Zr8isv/eew61YdzGXE3IhKGsJMEf+aTKpXfb4G0DIVTn
k0NQR653uhgdFUoJMMsZuMkafVwfqBNEpwwPedSV6Rpj7WnjkhC6P5We7ib7C/CFo151HALBTj1p
hhDg5a1jEzdICU6v9GBdCDpTlM790rMEKzJIBWDv85llQDggTevOsROAQmfGC4ABH6TU2fVO6+sy
aj46W4zG1cbOIjZWoQHxRp6sqllyqkCqbYiBkjCskWeAl+ApIN42dyP5JiNQSWANyzPv2rrPaq9n
HE0v3n5Y4W0i+Vk8eBukOguqnkb5lkQMWUDg4EEgUjDYPIwoJa60w8uq4i5E/lqhMm2+aYCmca+s
p6MTAQdOQmBzU4oHj9+hdF8r4dNb0NR8gukaDgTO3bG5/2MfcY8vicPPMhA8Lbxiu/A9bH731Rvi
MygBLzeu9A39F+SSrxPVK+suWh5fyKAKbqWN0rxuKDULy/tO79RCjUHBqzlttbAD4+pgISygpFLx
EYd85cYrApg3vFuegn0E2Fp1N6UwKHA10+i/ENS2FqGgVT6rQhcTFAx5tSpntmHP33x4KIH61dfQ
UNjSN1VIncKhc/6uLVPzqvVKzJYuKMAhv+YXS2vNA9YddITgbzbWw783bR4FE/hNEpG/i5tANbIk
yg5qiacIfFsRNcb1kBnyJD9DW2NC4saO/K7sGLRJOKadmMWtUaFW00i6YBDg/4FWbzEQ20W8W0uo
ol7lGbnVRe71pZqBw3UrILBTHKgAxkVXeL4m16tUVA39kQ4G0wVNPVDBq62f9z5AZ9YDb4dXPJtW
1qrvl1nsrYjGz92QVNnuqsjCKqgC4dD2/Z1SL57vXYWuPYQ7rBzFXjdplEucFkYwTPUg36Swe6nG
KBp02Ch2pOj5q46nSQxqA6tMuVOd+Yq3U/KaR8UqN/irKEkn1px1XvDPYVxq3m2n0QaTfDPchkLI
BcNh8cQiAe7Nyl1PMEoRToIQ5Cf0eJfQ6vEpTIlnG91gahMri+Na6EvYWGHPvKfmBPcDI/dZZFBg
2amkrUf26SOAuxTp3sLs75HgZsEPwOGKnHwDyIV30+iwR8EOYLNob6MsF0LJnSDyU+l5PG+Alvj+
ccI7W3VATGRP3A0eSpa8UnBksvlcF1xdJKsLHrcjWlzC7RrkHiqH6nku4+fv3nELXz3zNvT6sB7l
1Dnfg2uHcIz6VWpZ0xG1zcFM+vwRkdZmYCYUqUhJCzNpLeHwf65nfSFJj/f0ucoJt8fY/gQ4yNqM
2y22KyY4va+6wldPidNsuucclcbv3l6cEeLFcT+hyxPCjKcityahJp5Fh/dCcLXZGqXfQseeDxeH
KE00e0rS/rdrKE4oNWo2PvhC5kJEFh+e/Adf1APIuwz1wha3rDRwxeRDIGx9zMDv38WN16gPzL+1
+2eYCFPIHsfQkHvg3E2ufnf20PriRS5LtbKpwxXoXbTb3eYyzsE3axdre3UQECH3AefVZR8v9g/7
95XmRP9IhB2KaGh96CPJIF5poL8XrJFofkOT4fGn9zoXq2IkPwyY+DJ9TLsBBWaDBNGrCnT1We21
kbbpadwVBL55t5EDFcLrn4zW2HihzUdWbUZaV0mY4BgMmZJY52cFhsBa0mawVtdBEayihOsDsUDw
hJWm24X+naDT6mkBx7hoOrETAgleduAyT9uzRPobC1M9zi+LpNQW1Kz0PJiZoja29MF+NiY1oTh7
cU0JXrtH6Y78CnuOWih3RXDNgSDYS52qpg9Rry8Hx+N+7A7dfR7bWLGIPG+/1FOrjSbSBq7q+BPP
ecEO3KDFQoKZHFdprqOSPV+GBNS+/2fFOZ4yiCqAY3qT4WjtKfE9P+je52YKfRC2fJcTf6GVSzSz
Ld4YNd8OtGkQ+btDfHJ12///vSnqiFAauRm6JquUGaoiknZCaPwFXmaKPZTeyiC35AqpGkhgSaTw
gAdoqZgQG7yVOV9NF+lRk06oQF7k7zWcDurXlONJeNZZNNwdkmHW15VjhCZIXQocfwjRtuWMH6ao
fy/9CdNQR5IuVgzAeIxKjwdmLrd1pxpvNTjJ64+GPVtld/595aec6vShsx8Ogui5+8UHE88WSuyE
wxyFqNMI8keEU68suDZE+xkepWycXY7Rn0GEPtRgdsLCoJkoRnT9ugAy4DyU+uriY0BkLYYYJ8Nk
/57Vkl9u20RwcQ38xECRXUm0VMzN74vjgWDBERuHkFZ1qUCxNroWJfnXbnx2aERif540Q93cdcG3
socQLOkKjD+CKGEYIb3fVLFmGp6o9DEgeBvwy+mSLp2J8abI4p7uTKQvwELgN2qWsDSUHiQFtG3c
FbVlVSz0EH8pfUt9bM4v108R2Tt6SSPKlgohTIVjHC/B9RTlA9wGDt9PBQIwlqrlSzVaWJJXOh5n
oGqripWHmnVDD2rg/AkVGIoW4K3DXm3QalDs/C5x+s6dBk8agHsY9PEs3jE0NqXdo1fiHxLlEpUY
oMED+igXZt7/8xxDPeLJpJpbjF/fExx60r4BZikp6XoXjkfQVLpCHyT4bi1NnrDWqC1NEHBMRd5x
nCeaYAxdgEhUft3v3sz9SyAFwQtG4UZpkpl993rN9pZ8I80e5TUEvMQSJ1IQsTwPSOpyhA81VAbi
26p7NqbkWMlXOuf0A2mLfw9xAHVQX250wGukHsMfTo0YVrSGkxXb2pQD6nu/G5ibFoaSSX2ld35P
D+vk1gqSC2i9d7bGmGv6j5fL9jO1lXPrtgTZeKoWvb4qs7yK5/WIx/qoIM65y5S+ZXBO78bpSoza
DABOoOnvSzRcQ3QNJM/URDXJm9J4wWdNJti7TOpDXzuJIg1PFKLTcMyBFIS70JNaU2rIm5wnqkBk
+IStkkqkDvIjAm5hcY/R365rSQOsIhI1b+lxjBd4YrmXh0H3MvuS2CKAICZ+Tc0gzl3GEV5tgnrm
gsuFopTlefOqu4EGt2zqlHrQZGz/y2v6S2EIH6TE3Y0fe/Z767A9lU5lvFj56I/+4SqQbyUtPZcT
FcyE4UxrvtvGg50LjWPi8q9SEhW2BK1kKAjjxW9o/WdcItcImhGsrS8L0cSriiEAKv5PVJHIJROg
huRjkhOcNufW3GSdPh3l207uXhGR7DGmFxxy9arEJJ7yleOky8d8CFhx4mejtL4pZXCRgzK8xXT9
mgAFvDTPM4e1dwGGGyL6Pep1w2nqyUCDd7PvBBiirTr2KBZvSvnxcu740uiSFiUs7UsicOF+QCoN
vntpeea7I1Kn9OTP+dsmE1Q+52lP27285/nFEBu4iyOvxLlwKcG9qIAE81U29Ah6TIQyt285z0LY
kQ91eVNjHGy6wIt2n+50dSDFb8f5PaMxaebOG/7cSr1OXlE3PVngB/96xpEMe4guLnGttwcIFsIB
gSCecvYsFvZIZVVi2gaWBQ5zmOaEkMsu4uDmTgXQGJ3u1Y0tygNwmDWdwyXYNDVTfVuThOvgWgr1
L5soEdK2SGo1l5XP35op0pqA2tZm/trbQEfnlwpenzLvZgUlz0xJTSsiWu6F0kXCPpTORNtjIO66
aAmDmZUUJLx5OpzFDq3cd6A0/iG9QmBZQhMQf1zSI4Ogw3SAYybQ84B/A3Mz/lCVG1UyfthpwM5k
55VfT/SbEdAbowbc+KVWaaK9yMPKEZUIEyYsfv63g4pJXVYlH2zhpmxmIqylS3ZpIz9GB3hy8nI0
M+JrGX3U7bBjQgYcx2/4V2mT9fB1yQbYR4UdY7ukfYCvRWc0omMc8xyGI0XBmgx+Uv5pihDChlHR
/WZgJyQSuAjHt9EpvGsQBEXLbpoEUuKHP7YOkSSvwyLNr9gZK+7JQLBycI2ya56jrdfo0u1zMOG7
RFl1S7xj8g/mfVlhpzw6hoRon1BpcXF9S7owhVEhpfNPzN2iVU+hNnhv+ByFLd69YE0FLoUU4dBi
mtWRf+WNHcFDJbuDok66AcX8d+m6vyzdpIpGaQqQSALkR6HGHbATs3jwYnQFKs684Nwn6TTWcChm
NKqFiUywRybgQ8s56vT9lN3OAVzHcj0vq4l9EwQ1gWc2kHlVpOXjBWFTCVmyqW/P88imwP8nndho
eCmnZzW6UzIrZv9WhUNit1RbHqyE0LaTkOhn6ELaPETrkYY+FA333Qr8enLts7E4DMCHvuk7dgA4
UWihqhNfoCh4bcohnTXc6sQs/CZzkfnznAlb6d3ci30Oq1MlUNteca86mGN4CUd4BPOkglRbKTMj
S6VFdRgdhCsrKvS1MxQswmsYt3NubqQyKCRRSqCPqumqTRG5nZ3TO8PQ5ux5DULpfR+sv5piA1Z+
moEV57Pzzbk3U+uNzmXC+8NU+DrqoyApe6Tj7hmvzBnOv/lg4C+KoomWjkOQZxdHbchTjYHwg2DI
AwjRapoTsijLLWOTyk6AnC83XhP0qFqikFmnypnYSELjCb4ayuz1iK3KYBKSuRofrKaDF3LqYypB
IjchI7u/ZvErFuMN66M6kAmqN0UtE0ZccNjlvmIwbny4FgcwUkbAwg34BeW1EO9EbfgW832gWMVT
X48quDOL6Mgb3/rasK+dITjrtA1XImndtTgUaM2kjYGxqmyxchz1z7+1TxB6UfdbmomO2vKqBYFY
i9JmVxf6EkgkzrPdR2VwVKOijy54AxAHW9fy+s2yXe5U3ZhPoe6W8Hml0zydrMQeAhvVWcDqBtdh
hyxIB69G6kEQeU9iL1DPDM6U5a17kq+6aW6+EQXEeNORUX5izGL0+gRz2jGMC3hJYa5zbSbES/Q8
WMfwlAGCQWxCOD3Fok+rYwVy4h9CaIS1+KTtpEyZ2H5TuWhItJWZ6hbh3D323U3ZWwxHDzJOiZSj
hkNlxyE/SdjE4lgodD2jlfHuAY7eMlRvxxehib5JqUux1iR31EC3/FOWHvpj97znx2ZO27NXJrWr
6ouxadOY3sxYJp1d2T/dNndKC2XhjpO0K/T/1leuip7bzfo2CxRRYUuD90ABnJuRCXmhGRpy2v9U
6dkyAWHMcpfixr2nRQFDEKpfN6NGvGa6gQjChcF1YJj3U3DIJ5tUj9I0NHJurFMLXYOIkvE61nuJ
fx6YNmYsBUbRmPdG3gMbzPlIdsbpBE0J4CGauV5eI9VKLZy8qhD85zco53XGqh7+/kAItnjY6dgd
4VZo+SW2BvlwGA++yefXNPAgNXF+AAUbQsmB/hMbstjEFyGKGrCvSYNPP/cQcxd03c46xg1vrQeZ
rNROJamJNhRGEbxD6gT2Sny1xea2Zv2ABjz5X0EebKCfxZZnU0OqQCpSG29Yv4aoFf8FdpMgdhA0
tt0uQufjuIwyGXk19jPz3Y9FAA/jexzJNZeNzhkCkIwwkxjD76Jr7ffjTJiz0dJ7aYV9N5FG71kN
1du0vDgPwc8jC/cF24KBbwZoD1kOK+dldfujwA35hgtdbd++7xlvPOUbNtpKnJXgUUrn8YeLsqwx
OqoK1YZi05vZn1sENSJ3M1NuIML4XS3l0FzjA4NY6QoMspA7Nd5StRXsIhpcAR2UNBAhJlX2zkxX
my+HVOczmKcb82+MbUK7XNs1UTNIz/zLR+AW7/ioPX0u/hNAbi5aL2nxOENfaQ9TLLqAQK7lS5IA
bYYN2DE6gfUdhkyGU74Yt4McJpS7EHeg5nHjySNJAmMfT2Fs9pER5gLileAHLwsqF3/96B9CIqxs
Bw7D1OZr+QGxUqPdWSuNqsV01ZdZC7D6IW76sruf63w44hbDPBVW87rywe6o0kpVMa1Ci/YqquZi
hXf47cgmZLrDOYpC8X5AB/pxhBGz3+RRvdvSkCWQWGOEGWzevhp+C7UmZhganxwAbCPT4OXIibu/
7vnGiTJXrEP/5tmty7VDDg8xnSpzv4vHkZGRcBRZlYdtFfr8NDVunTmBFYDNtvIICU6efe7FLObg
vfYEqiOkT+ziy9bg6gxtUe2lOlXDeZ2jc0G8ZzmUE7z8S9fsJL0oY6nySdgoDFJVzFKDzSVRpmeb
KJ7qmj5r8zWElIgIgKompvBm2rdHf/5zxlqYEnRNnkMVbi7ecVqpGM+f4aHAIO+kifeeLsryToPM
BRs+G+cFK8uwtKOjYAWtBYD7rV0/NwTny7b1fI7+HzMWxxJ2hlC7dcrQnLER/LlQADmZql7SGwjS
HEOahRB4JE0QP8X5Xp/0Q5C41i5FkKfznzyFKmTkDU8vf7ZuIGrmJ+SNPG29F6KkfxUxl4inu++c
7h4nY7zROQGR3dIt+ZUIHJJtdfEPNRsamWlV0NWm93tfFF//FPMIdI4ZPL56EOj1tFlLgyet31S2
HsRwv6HQbIAUHrN/VzhOIURru2cen/HR9jY4AzTa2XUssaynzYDFkU+Obil1JX/jHkH7mL0qGWdE
hnoU6kgXNjYAU58qGwobutF1g7xQAwMDwXzdprkbC9FozeReX4qRTWHC9rLEhrs0EOuwyDbM2+QE
uPHVUgUz38M4IPAa2xUKRwc28wLjnR7rCOcbmqu97al5pd7rFMWb1+6kPJtdTAoz3kTGpiCboLTu
W9+p19YZSmsNFR+EUO7ApUAXYJttR2ItIpyEd6RJDuGlAt0gZ19/dZsF95w1Zm6nuE+Pf4gNGB7+
jS0PBYMwUP8lMhxfL0JtqZINWeAO6ozv5PWkZbmibNVFXsphbiVyJ/klRo4r2es5jl+6eGj759ij
BHJTVlYJmpkSaEfbN+38VqDL2RdOqxUeUZian84cYiVtx4ZxEVc7/JgW4QNn/BQZYkzhj4jD/E3B
AgMnuDKK77/5oqS77e2iRuvso18BhLnLgAzauAjj6Lv0pQzISFz1DdGD7seSLBC0psm1B91kWqNx
a0AyXKup0Y6CI6NU2ac61wQHrZzbZ33Rmebnc4gIk5ni2JsTZZTDoa9z2fn6OrES4iYXVsaa+xmJ
IfQFTvWOtCRNxFhDXPIT0annNtHA9kxtahDqwGXZu3/PJozpKJPeyy/7u36x4JnP1zsh4ZHsokGk
pEOo4mUhKlR2L5TWz3rU/pCeYVyY/fps6WfgPgndvaVaOlpiZEXxQPtoJDRoJgfLymXVT1pIj1dX
crbvZiEo7nPMhvnoE6ai+8qmmIY+oo6QtsQmrbBk8wbITp+6+VkL1IyzyWccb7wstnUUHWyT9hPL
rbYcokhCGlMP2dU7fT8eihEnHvPRXvjafMzOyOXAX/zclcOwPPvPa3lcT8GCEGOQb9ij66ag8pLB
qljZzIiOtB5qANxGETQK2RyOOvmNs+N2yN+j1zq8NG+1syd7LyZyQ+xnXt4fFTkqD5t20sGQwkf1
qWmFovOSUDIw+Y85Wl5jvuwQtpRoQ46IsA+tsmpMC5E7yMYwe5O++rs1ANyINyxDpQwZAFk7BCc1
SGSU/YOY8TwuZ5hOmCEYzd/vsEC5zQzBm/U4VMUev7IC335qqDc98fFm3olQR91R/ocXbg1Zjs8Z
vf32a5LONVmphJduGAmD8AenJylu9cUttstftOHOQs8Cq9aylBAWWiV/kNeP85KfqEGAPgBJGHM2
2ta1A5Qsw1UuC59vHhZlcAlx32PWYlLJSGRib1mrM0o2r1Qcl/efPr6h1VNfd5LRBAJ2uN66Sq3L
TRuRtM17rSyTtQS5+k4jmdrGTCok7fnVuCFM2R36f8eEhos9HPDTh0pPTwlxzhFFGxJhgCgFcliM
Es/kyTxRK+QMqCH558jouuIbuUVM6Gs3ejUZbhDQ8rXI0ntG1pQKmXlPG7bt0DGl1XEpxegKXVXR
ZErVuMkJmuOse3kMOyUu/8B5ReMp/Gy5ntnNPJhicZhT57K2FpJXAaq3YcF8ZTmLPbfYa76SExoo
fZEx1O7ipEN98JUSUIsQ7AyPbzeQfLLxQax9+jHjCKroIfXStou0RIl8qy+xNr9p6IvbAhdvB/HX
TfYwQ3aicnWLx2YXzmfvEyXCuz1vqOU4+D8PbBVS7ogLWdh+Uor96nwgg1Sx1TN+M6MoZi6yhFqu
98to+5YCQ1AjeoWujWWN/rsKdENxKHtLynFoPaMNjXEanpXFEz04xa6hmwWn99VsOaJSCBz0QlO8
L67cdmnCD6I2zwCkGjIuBxuB7iMAS4Ou7+68rsl3nDDLPa8LIufZnZ5/TEdKcEn8/tzwQKTpDrL8
E71CsswFQ6iuuKcFijo08ixU27kZ9XBvZLZmXu5NMy7RvXHBFyeC8qgUhQBf7EZonwQgrB0p2YKX
j6TdwwkJ1t0VWAV0aQ1aJ2UD9dIctQGDwRBQd8CYcl0U3PV5hQ+a9PD/rtA3akR++mVdFjZuoHzy
rg9sMKvYHVE8xhQH5qfdej8KJEd6mEKmH1n8dr7ItB3hFAjELz+0BKmUnZ9j9IUYtFMEDj03/1Tv
wGyOTOw+pcp073oS02Hydb6CVpKdPz4UaHihUDs78uRxWNS5X4UgT5K2tWWvp6vuXpUiwbhsMeTE
f33P1g9q7P0foKdDOLdOc8Gy4jkEdbJOXevrW6LLZ1NskaILgXrcZKxDHMurnWl7xR6rp7oPjtY0
K7NuvMuFoDahbuWzbvZ4k2DExjE1QeTCVxFRNWuqO7KjOfUWkw6v/mIJ0snRHlY59KE1MMurPnBt
KfkmbUYmzDrrW5+sTxzd+O58QyX0cLeayUMvW42TvC3jpSWA8eTTrRT12q94QXExYtK7trSpM/7l
TMfR1TbI4Odl1Qmg1HbAb8NB3idfnRpO3PuLEp4fX1pnyI0iKPtmsSUSq6WCi7gJo+yYbRAQU3yW
FZUGxyJFAKTSFmzyRpXBy+rlqy3tL5z+nD9I+iRye35dKYYFQudzxTd9QyCrp/eAYKzi1OPgAG8W
UDSY39wMntDDYaGGtcqnyzRXo1MLHa9lMwEmlON+1Z7q5lAWD5U0QB3ro0i6KBr1Kw+CaiTn2gsT
c/sZGv+0tOHxvgtIUYTTCpJuTApGBrRHQmZVeB8t+QTDg5DLQ+G1P7Jhye6mvqwqxiQL3njHSvXB
AMt1VbwFpXsIM+vU7t90g0wnCplC2u7Wc2YBqTTt3kMxS2J39eW6K/MTmN9s+/bijKM09hpCm+X4
14IoWn0M71rtNcckqYKw2nMVNn7flDwuj8MBYRYZJFS1Wq8habQ8MignQHRtwRlaRwhejapiYhh2
amCbPEmCIaBf/D+5S1dQzMyyd/0JGx9CeV8Addu3lrc7v/8Oa+qIEDfQV1VN1dVJN6teLlgclQaW
vg5qfZ0ywnzSbTzNb/ayfy3iOJWd+6a2LTdBmu5xn2lBXSPfDatsy0TEURMZXcoX0oCXX9fpXVEi
VzN1S0/ErESJuXPZS4PHcob3m5YH7gUg8+Bco4ESfYizNaRX5hB6Ta++95zthr1FAIyJ87rRQQdw
9x+Wb5n9AAGT4IKjWfPM30mzy76e9wvEVgFPxZlZu7nrUk24Et3C9d5HeLpTEgyanHrw+0CUeCfB
kvFBnlUqNq2+pNCsqtMy1MNqLmMK9n9qdFnoD91+YoVsiSAk7D6HEzMWFBEw1Rj1EP71KI5T/6O7
qaLlxJ5OPgq1sRydOzA+Tlpmv47a1zsCE7vDbg96PgZVLSuVn8i1uRI1O423bVBOzuB0MCHIDD6V
bcd2EPDN7HTStohpEzIgz3UCsIJ+7xvccmiBkj4EW5jG78F0XiI1E1koBDqMnM1BI9LAvZDL3O04
9czanHzhdvX/8HnFX//BB7TGRnlXp2guELwfWqKbNYP+TMEjyIm6tBGAmJatm3MyvBcL+yi375mn
nMP4GztupOFWhJ4cLsXNdPV/b2HUJeRrawfwKVeJ/Sxq+rVsY++/dcfNCNwxWV0EWajUMs53VE1+
k0pas4olvyuP+lZmXwa96tAlCeX9xgVnV3QIvvvUZ8RBxvYtpCoJG1QWxnmgKrixBvGrmPZfuo/p
BHQ4PepPmqIVXftf5Oxy5RJbBbkm/XmSK21aC9TqSePFFkPTb4rBrYOwM+07IZsdJ8iDmjKLX4sL
1AqDpPrBNgZfcRCpmpqaMg4ypc0tDmN8lHGevShOVSlGZZ2x5ERvC1Wr6xrAHqRFeBipet9lJWZg
+M/OSlNvLgtnrzhXwMzUS9J0vsWJ2a0g/gSaJtWq7tIJaJOIxqMtXzF5SzyZxMvdNvM9xpv7uAVt
gTz6bwf6wu7+18ohLLcvogkybMBznUpLkHqAhmWrzapHzm/D+zAup8kv2cDQHlPTKdcTvF6NG+tK
bRrmahfF3BSsxVbV0bNU24UNVr1BH9pSYYbDSP2C9KxPtOg0Dkl24v7ix4XfneQj9UPVEDVZEEwY
kWthW+qdGlKAe3C1oV39WHdpB5/jtm6sggprWGxnYVMaWm6q8rWu4gGmp4XxCjmMyFBpoyjYm/8x
eHqKL82pE2ZjzxCkKMdAcaYHemiLJS73PAuexOtN2qCFRbzpHekOUfwyzXsZP8bpTX4T1tYKmRE8
vIsQcxew9jaOM//2qRoT82vpB9lZDFODozrgRw5kPJMyH69L3+fnQZHUoGyQKevPbEuCtO96X2nd
J7hZwJDTx98fCtvP6yMTfmlhaNV/pi4ytxYWi2gLL7By1+tayIiUY8hwvKnjmskoWy+62Jk8ip0m
in+K1JuoOknK3kEaIr2BhyWXbZW21jETTFDrafWpeURGQi/MSr5g3tpsH1oYYabdUu6xSBYoF1mT
sdKjqNGdRH4ziCxMLXyLUx+KrDbzzvaq33YBiV5jEN+VNn4dSE0RX5t62bgwrzlYQPQgOkzSlnsp
3Q1JbwLBkvJiAiwfD7Clh1PFOp2X8+yM3cWYJ6ybEq9+AUwZC+UcGU4cSUUVLvIftbkf99zf1QII
5Q43f89SUwyY2YEziMLiVrFyaHYJjIyXDuKM0d4JM9UYQAH2WyE6FA/4/fJvYWxyoU9zG80GtKHg
rghFbn2sfJrSNcRLipjP51Mj7Xf0VjccJKvJR5E1+8n0MaZk3qb/Kr6YsDJvMqqIox/yrn1YjyP8
GYtkYvt9rzUHULBp9eD4JRjepouRUSq4h1URjtrc8ZeWmOz8Vuy/o0/oZZ/N+bb6SCxmp+lv8oBS
D8x+YfE7Ep8MfW7SngI+QA3NnvymxKUhdH6CJkqY+/32OjFXhF/8iYKilBBYu6v1+Wq6re5kJgl3
36o7MBI1SUSydxtrVAtwHBnwbUHTRpwmXmMgYJCp0HrwmPujSXS/oHheUZAH4FXRWwhWyRNaCsr7
5c+ZRJgwVpZj3kgtIkdSfhbBz4nMFypgG7/lWvAX2UIuhBRPMVNHmKjnl7eTbjII/u/1PUJbdMlP
iz17Wxx8lYgUZ+ZSi1ajH+8sVYzKhzhgW0lnJmtY1x0wJtoMw0Qh2hblDkXl3EWtomJchm61UlRB
qmeEGrKuje5iHGHo6GjlKfyz3zsl0BGAzSaH9SKqhEqpNfgp6W9ddjLUnKgzIJN6pDs/4FD8Ej6o
JZiv0+FYJX0bALpFtRvvktcO+KIyMAmdZTl9uTBMI9b+LhT68Pxr3Fls2KX5Ygy9Kv6yVPEsFGJ3
n5VTgFYfIk9ehvN5xpcxmQnkQguHPQAkK5HaOm7TWZ7h7hP9kd/FyDY1oOvynYQyxuUxZhGALZHe
KVBwAUdu8rwtqY47Q6xLgeSHHhtdFQvCmnmUfMt0gSZ9btEtV6vjP+G5P4HxgS9npnkETEfBEYew
qsUJnQbRvk9ZedGw2MGQftN1AeUctv89URu7symUa6PisR9RRbw922tzFi0C6q4J4rPBVA232u9+
QdRmhH2Vo8LLxDZfO6DggYE0g65mn1QmBHXOEdKOHZqYuSZrqpxHKZ73MhkoCOJR2waNdGo2No6t
gwxk5z1rexFDBXPoX9AOa6anDMvMYWiPrQUGhD4lJZrt+Iv1r8GniQDePnOhrzCOKl5619RkfYHs
IxeqU36dmMZQNeZVL30uBd6BO4/8nBJJxbrH0kk4vKEOptIS8P8XwXpiDivW2NR6Dcu2OhzRSLmq
7sULpfYYCzZmgG6VNCC8oImAEyLYWkNEVac/EkYL7YIyf2gTPPmbfKBs1lRpxbcKOXj6PwY8RfWU
wai8x2RbkowaETPvPJGsvaQcSfBQDpPu8JG8c1RFwq0kWp/s1r6ifmIQsWvBg3PHpJJu61AH1XfL
y2BvSBXERnZJHCz4YxBpMTYhk+sG+KUPvoRYlaOt0iQTkxmsuBjaj3WebNUaMqOlYpvhfxHAbCT2
RfqLPOSKAnmiryCairwTDzWLTv75JnEDKYVXGzB7RBgyutuamV1j3b2CreKOwkqwRDjAlq7rcgqu
BS+mDT/Q9cpKXcfEJRjU7eUKgA710YfBLDuvHBNPT7iMhlnLJ8ayspf62mkRoKwBwzpFOA0doy7U
UhY3KLsDbJ+nTU9Cp6+oYQYxLaQd9jznICVyRNJUgEhkmZh6AwrodIR2bL3zDufwS0hRGPURQORb
l69FlG9c/BiCPjWcuqNsFbnTO0YSEI+1elRpJNTlG/CLlYo2oLfGUds4nQClEyDosalFea+TS+5X
4v7/hUobBdNCldrtvFIoZzNcC9CNExTe8+fkZ3ttWIxuk+CiymnZMA04a0dPz+j6Y+O+UFGhZdpV
fPlZ6BdegbV+ZEnXZiuojivU+aa2qTKYExKAIn1aE7NGU0k5wfCfnhHoAPFwqbMownezklXiYyWr
2/eP5e+39lkN5IP0GbUc2hZT7uVwwKfWuEG+l0oFl3i8hqXsRVNKqwQdN7TDBTSCA29Xh+OxLiJ4
WIgA+mzhsrX90IbPP89mWpqGNrTrK+VzxBZJP24hyuDwMRCQhAdNtbKgCB0iON4vvcAK+LLaoesh
MA6X8vFLZrNMkWFsai8DFfW8sdaRsHDoLUhZFKK6tBCkb04SdqdRjva423jKPtYVwVmaVnf8WdXt
NfQmhPu8qgR5JkxPEF91mEhK2sXwnMTGYtxHRtUcnihFxN00rQ49D/xZPD8CtEPxPwtztZoj5GeP
hFhDVvA/oen432znWAP2itRFZxQd5l55C88CP94l1b+V06oGWd/8RQyZ/E5L66ycZ80yhGnMCvev
Ve1AZYsAi0E22+bS0N2/qwlwkrpN+z+vI497q8INwTWkqHPtFu0hNwSYyf07KTVAMSccvzpJS4t0
qIlEj4gOd7MaJsaWRlhW5Hkx62bXxF6c6wUDSO1OvqHAvrWQym5M4l0vquT4KlpNbqLtxa/iJD3b
0DfPXsbpOGAS5HoMA50hn65ZmGKDJz+DsULuMhoQBCOvH4T5SXUUwTbSgCOpgPWWiZKAEg6kaw+G
IwU12885XsJtpeNAKTRewFgDGkBEzX8yyLgjf6FqaOqXJsc7X7vXX3f4MLuBhSsNY56oHALCMl4V
yJn0zu5ob+vGwooJKmCq0LMMIV+p6VgiU6VcQXVkgSR6kdKWLKNjUDSO2KZTwu6h+zxulLS8TQP4
+/uhVAjR01v7dNJRIorwoijR/oGLd22JkQha+qyb2bSYWkSqQ+SRsVWvwHnExkismrmU/SKQI7aJ
TqrLZF2B+Ry2p1aqwi0mMGmR3CVVXepEyrOMRnfZltd3D2wLO9gR2rJcYsoo2B1w+D8PYFDOYTQn
YJgJRQz31Hq+bMuGJ4JuLSHfK+d6N0PmB6q9Dc6jPfuKVfOBP+6kI7cN7N3E9SHBJ7VDuXCT7OVH
YC0z6bmI9nRW1+Z+u+NgZjyc7M3dI1MSGY4aPH6MeI29g5hS7rJnPLvRfP511RGO6gPNy1jA0QJV
vn/0UF/noafNlPud+kT+TnSk670OFSuHixsWHt5DMk63N11I6jr3/c3bX7hgCyq46UgxUbeb/7iD
Ggx1+TV/BIz+juJirHhCComVVklrj4PWYcPM5FhyjRPx4GqZ7uOQ3pTKNxFWc4hXPPdiKGAjz3Mf
UN28j/ryWPJZJRJ3/5Lk5QWRv8osMDFmmSYff9KxJ2H/C4sWhyDG5iX+O4JjGyvEiKFKz568Omfk
S6i5qIAHQ1pXkukrbtrt9rk6ntNDUlLWqc+bp8aJtNFjhvidh7/EVfuwGKU1ab2XCGHmDF8Q8Ibk
gn2b0owGkEJvIJ4QRx2JGhIzHG2KJo2fxXDYRBIgveOivM4HeO31aZgsjfc3POM+P4GEGVPk2+tD
+3aipEYICJGrlGTpBTw+Rgq2Zy0uRRXy9QFMfFl/dqr3y/PR7MAZw4ke+BSiTjpq77UcD+ZUHt/o
r5IThMyU9uwH6hetHqkcb1df8JuG3eFWuB/9lUJmgXl7jsvAACLazrXb4+XU3+SQ+L/u+FQtCesX
+lLV/nJzuVzfIIqIIPkKYOSm+SA3uZ3KQbreWCRfTQhoW6Kc1zyjL/JR6mxsQNp61z/SuaYBdAn9
Qz1X4oWyhtGloor+1kkSUr8NCZ2B7PIF+oElyQPGbeVlDE/0iRzvYRDoBbCxiEUb4MtjJkmS6h4b
geGMTVWGy36Tg7N4fL4qZt07qp2wawuEmyr80U5b+4gPGjpoZjTgBWINokTAEQweDvByx+DQrLP7
TkQGJVR8uS8jR0OMfuukcO+lsAgwhYFQwILHZFOlPRIJwtHtf3q5FWMdHGhm8IrQSHgcxY2lqIdu
es91AyqcDdXd9lfjY9Xfj9Zf5Uu61SGXRRzwyxDjEu3Lnt2oJSp8clbrgiclH6n6IXCYcWor+/gW
xdbWP+LYsgOlqiwmSDhtTO5OHVtdZzrgMhWq+gmFbrxrbCTS88aitOeaPqXgXULJgWjqMcRFxKr2
Mn8UYFUjLHBLrHNBMD10+++EquB6qAV+fEvUTWxUjvyqdboQkjCQAlSkkLwfljDXhVd6YrNvPFof
qJo94bmgfhKX6wolRW2ezoUU4Be3x/WiYKiWvEHkJHH2yw3yS6RBGwBfHIoVk2RtkyrZGHwSpjah
SlTJeBHM57pEUnYoa5Q4zTPfPY55tQZ0Qs/z3Uef0RnEB2heoWugWNUwf5Jx+ihciCxgUeIkVpyk
a6H/RqOxUfeTRgG80j8X5zeFobbEEOO+hGUqgCNkIQkCBR+awFK0qP1Fgj8+pazgEgU6KQ+PKM+V
nNrkB280dL0dPBb4nyDZun61IG7nxz46tryJmOtitDVboKADwHvMdfhPXhHA+2HHZOSwh608clrh
27cChwROmvp8kTGMk/PXaQrA2cAEfFEBeDCks30vcYvTesb7icGR9PmjlGamYm7tjSoynvfMiTgY
4eRlt9zReML0Ey9rARUfPTKHQT1y5QyCC9rtcut0dukTJDOXlN2hxk9nSdoryLjQ2/0UPB3BsLym
032qQZQGQuvUbpPvrB3I2shODi8djMcptvmwRQ4T25VWHIgicrDPwe5HVEy6I1gTB6e27eiuIfuy
T7/raNKZt8GjeiEgGXwsTvRw9qcRI8XuPTO7qjowfLSEZR32jQQy11HAolL9v+OB2vvVI28M9g5Q
Jf+E3z9p5mhqd4XEU6GaTS+srdsER+oVzOUcBsKWPYOyccCdRkqicS4QAmwm24Qlx6Do8QaBoQSk
+S+g2lJuDYfUSUZhrOJpEXiI4tq/q3ypx2azl9mgpSZzKKysFsyqBdjBqT2aAUx+dvK3VLsRZPE6
V/7RWJEkbliJz2suDnqHOhySLJQEu+V38UJSgdCr+5D4OTZAEwi+FT1t88B9tIXDQLHFMnQJOLd8
amCnOso5CctFtxiIozoJ/cyL+OQ9J26+MLFgvizEWLv8yagQJH1m6T94vktq8bAVV2fgviS8EUdd
fCeqh3ensVnOcZJpkHwNGd+d/eyT6MswQHJXHSI+xPT8HxTzmt9LL9/Ld4WpvmJzO2vxNOKY/VWx
/GuUpOkxS9K/s7nMaLl0EkjEeN1PcJAz7nNheXWcejP+ZHG4ZeyLJz9bYiLPc6DKjV86Ody6xu3O
CW4Rgc/US6rC8mOqStDUgMNk2ur+PU49mHfUAWp1F6aI0RTklPA6NKadoZkzt+mAtdhUMJyjkqu/
jLQZATbezuH4JdUih/8ex6PJ5UfA9ynSmpdgY5/9es7oRtBjrEWXok/znvEtrpI5Z1UciLrt2N6Q
FUpRXV9OGvBKGqhG+Qog+wOMCD99BIe6sCwwS5rpGkbXU51xiGeFZrBJVHvjS1lMZrGPFj1jI6vB
tbpmhRogeV1kjPGFf1OauxJ4SHbyaQNl88EFZnjQcHLl6rxe5E2IoGHng3AM0VH6ktm1FJySsNBU
vighP8F/VsWHcKQlWx5+yNwYWVMUkZV61awxTDgM1/B8ZfhrCPbqzDDU278P5Eu1oQCaEBvUW+cZ
d0RwGyyrWuph/5jH2gmOjXQ3SbsmE7QE+2kfg8xXmjAQBNOCHOBdOINHMWuaHjsfddk35IXxEue5
x/tCueJbLhLMcbspYq/7BrFll1CAFLjpgp5rwYfK/OQFbkqqhy2TsoXuRZv8zdCW+1kuayDBeQ8S
SyP6YnAwcvMK/xfHIPP+UiF3/FU9juboiIZBnv7dUfSs3w4LcbTeT6vDDhT8xv56uEQNB5RXSr6r
Z6TDx6HypWo4aaHe5zyk29DBVNfCwxm1/6N1mvoOUZGez+v4pG1vHMgLWKm6a5oFEiMLeuaYVCMg
p2AyTIRqnniVyIOfplOAKOf4D7wu14PhC8KquuYNwrEeRkfv2PjXMMrD9qkDmeRXTIlqS/rblubs
gB4di+qHHMLkL1uP0an9kJGeyQnmvp/J2ovcDo8+AAMz5bn5r/a6behg5rEKY53JAqmQifrrxpfO
8h94+k2fwEL02OEciBIxMsi75vPtr4YCX5odZRptEnVx91pjss7H2ehQ8MSOIUtW4cxri4qg/XmQ
wHcN9Y+XVneXxJHY5HryiwhThTvmcaoBKkNm67JlS4J9HgX/B29Xh0cXOPfDm7tXG1quV7OTHpXR
UrTZ1/jg96QnfSV/62VxU3lGz7tzldVFGZ0N+Vv2OgBeFwRlWMQ0sm5UzWlUPiKyzDPh/vIvkStz
/J/tP7y5C4wLoSwVaCnJflRHjpIW142RqHfPclObZBvvrcxH6BCCtIyEkPudpW2ja0n8C/M076M5
bJHotJga1L8kOfv5zOghPX+5SaWSLFFgCh1uZyTw5G6f2fhV/MZAvWfyNX2OjYL4QQfjSYmboSc8
AAoeQ6EXyu9cgekD6ASUhII/cu7ek/vSdbddSFGddkq6jeN3VAQmJvgxCLcqbwNH10mg38jxNa9y
ONRReWdM+6sKWBn6OWxpKVfLYbnHpw0/EN8rYD0Ku8GUuV5BesCDRAc63kJtRlw6WD3DYdqhHLg+
dUg1784xPjdWWsB+os8v2QGdNJ5odWlp9wHN75NME3k5OOTFjfcVBIh66O8FhSJazmWvCKEYfpWB
/DpZn2KOJyuWZxI7vag+rabK4R7q7dzdogrx1dQ+5EnXeCj+aEQ/pZlwO9Jw7wuDrB6PXcCVm5qJ
vEGSevHvGTpCwo6OM2Xz64DnPPPRXEcSjEbMfvv8tdQ8gEbHiaH1eh8Q/qFjaR4JnM95Gj3NbPEC
bJ6GzNdiKhKspVy6+qZrN5+xc7w4gNaSwn29Le7wtUy+HtDnD6BCgb8NNvx6Ca3DFLA5g5sEaG7h
1D+e2/9v8/A93D8KwMpvGBxEGUne6eXULjMyPnQuHKtltNsHAgxvYuXcpJPgC/pEPQLMhMeGHCry
bDVVLYWwQCHv957Jg6Fb9NRwdXMtCxTz/sFpocY/R1sytIul6L/1J5HmBssygExV69Vj6MtrG/r0
1LdUJwpifoUHdEEyJ7JIT7Kuo8qLJ3ugqVYXZ8wq47jXGcZUbF8ChSG/wOLRpbFUaPqjARQy6wUu
d/c4ZaJ364xin3HFqTwAPi/XlG8k2nQaMbHT2UCXk+Gxs/h4891FMhI82/HMGBdMVJ9q+k+MIoXa
lWJndlJ7W/8CrvYU9Z6GcfUPBytXdjbbva7laGsbej8OHEh690/0t0pzqZJKLyMP8yxOSuvZg0xX
NNlSfotAK7PRgQT1bY8yL6NBjfbmFm5+53TXpL8Fd+RXgCwZ6UM1LeUlHz5Jz+3nShx4uYodEdWm
nXPHGcWXpc/5VBRWrlQI2Rp2JN1Rk4zkHWqWeVY5xAMAfyxiu6zZTm31L9e9MzGZ6fHgBqeMhsKk
C//SHmpOta7bLsuGV8m0949o/k2VLhTAbGPy4Q6PGTf9f9u2a1hh1Dm4JQQDGqLq7At7UoxAImZL
5Nr3u6oy/+pLAQiWEtsmn8QFd5m7DzQ4ceAegW/m4sQPgTDSX5ZwMCrJ/0R+ZB5C9sPGF/Tsnn9z
YE7EWM+Yz3gePW2ChxId28d5VyWUpkgJIPRVjYuKxQ36VkrvgcV7H2h+A5KHJV/gP3NI7kjzic4O
7J/9xGOhTWFARFdHEMErK6Hn4W0v6kHgC+i+CVlIl9Vah4NxOmKlDVPngAHXHRk+09OaErSegfbZ
4WMLWgPQfNj0rfPosEOee5iF9MoSN8f3Gevz1/TLXQ75zU7M89mv8eg2/eSwxc8lFK2M72OK1Rb9
BgTlFK9Sp+xPUzVlcjPFkFK/mpTxOV8dnS6yQklC0H4nt6s+kqU1OK6eDEDHXn9TOto+w3fmU690
c59Ohos+3AP0eKtUU8uS9L9jrscYjQ8FuQU2REizq0EBlhh/D9dj8jLjrN4BzQEUAw9a0bgN4zxp
xymrCQzyfsyzOUkzg2H6gMmW7aY+Itwv0wFlPY+dv29UxriacV7Roa5x/9cF7EGetnvniK+U4FOG
XrYHGt2rC0Txn41o2TVDEHcPHrDjRQ4ZS6N0CsAPxWKsSy3XW3NxYcQaI9j9LoZxm5Up1hYiTuV4
E/gZeDQEHkR99BgrAMwFi853C552psEj0l5DInUwPST1X/j2wkaG1UujUkm7+tfUBaffmcnv2UNW
9K17arl2bKv6K8GpLTjo4p7BgcBxxcyqMPkR77gjTZjtuIE3J4iITTTHgeGD4CaYOU1QEJNurXsL
Mr9cQvS6n29qX/dvqNIc4i8BdHA3aylnVO/6cJH0ef+ab7JNdJ0ahKSjiljEFNqDPXpAEKwmZRWG
0G+IenMF+l94vFS+vJ82WQecLCu4JjLcacdtMy3yzjCmXneAqL9fHmLbL8DnvISCf53tJdHQ14/M
N0D0k+1uuE1cDYy0IIkOXRd4fiakh0crREjjbHZud1Sh0gNR8tlIp1B5hR8qQrqvjyLQM2cIYcTp
3BeCD0wz8MH41jcHeSLPNY8ni/Ia/wjEaf6ibNMlCvCoEPnqbtLvPZko5fN0YwKkzPlIzaTGLi4c
RgnssEGlayN6IC82ZQttghJhLmvlJwUsGIaoE9q3cx7sgb1wRmR/xQbcBac2dvlZG8b0aIjr6kYx
4Xz1/4Dq/pKbXLKpITsR0hkHKRC35aY/6EHcEtayv+FovvgqSL6b/6uY18MXQY7RN0HZ7jaAakf5
Yvl/bUd2wx4XEbnibR7ZIRVKRiqwCY/7gOYFIGv4+j0/L5e5RMDwhLaLg692oreEhIKh2hxPU051
18eiI6RlsYqhXbUT8kWiDtelU4L5Wfas5ETZVzAkATqqKVvNfxfup7Hk+71fK9okxLoU+qGd0yy8
bFXXW1WSPDv/CS+ia0OMBAI6ELLy8pgvgtgNuIWxEUPNa5IESYwznzlPplZY4DdQ3MRND/Meye+g
36w02QeINPz5KL80FjUUEnKEtNOCJZrsRlcaRNC4iMD60d35oaxDpWbhcv8Oury86+x+aAds1M1B
dvo4IKRP9GHPNY7HYezBsVyRGS6+GXyw9E147+pZbCyzUmOUBWUd0UQkRCCFoULQUcbbtRUtqk+w
dFf2L5iURZ/6DMaUeIwK9z76SzYmTt4JveDEgmhHg0bJTBRvBgbZrQNpIq/jGOuku0+gl/2Gv/Dl
AGzzaQniAM8fcYLP7gCM84FNZifXWVUunWqiCWMg4sRkJr0as2zdHHxIvoQ322t+dNEYKk5dbVST
j1jnWKp+U8uPvWxMK8MW96kd0VLRzLv97ii7K3IzxpQfYZjy+pO/IYIR9LnX8eGKM9oeQgMlEenx
JhkbpZWvj7owsFkxPfp4v3Otje0HVInulKgbHmXU7I3Jp62OQY/h6yTVzeoq68GLN/A8oe8T6Rz5
IJmYvhQ45OfF8/glNb46gAcjyDb8ghQyngTvC2KXq7DTesPshpdbkr5pfpGzVUltgWZiZDJvU+RX
lK2dzQMcwvqYl4v29KCu7tpFPUUSUwr+17osmRlOPr2zOWXCGWobAmqmNzdho7IjEa4QBRcIg/Vg
1g92Zaza+HOkrQ88X1gPMrE1/NKC8kdtd+L24ArQA+r9RnljTRpitVsegklnOH57NPjZe/vc/iTg
U513oyCA7s3aWn1U0oD3pLKeXM/uOZ7qkNSvMQ4vMPgJu4iH9rcVa9WVZ0tEU8TWioEAzo44JjH+
kiuf84jsrVNzw7qYwBUFz5PJXNG6yLvK/a60AqGd4aJ4hM9u1193+YrRPWEEo0a7QLwGZX5WSvK9
xNkvrHwxcSnFhrHGa1Tl94DNidk/hDQ5MC9+oevVX7v3HgvZ/IvdxHpYYfwMRjSvd+4ejE7hhJXm
qyD0LgHJIQ1aNYPRPC/2Wr/dNoBzs8BrNwTgqxzbhZ/WC+gkFSZ+s/IkUPY2B14zHbyzfj/oGL74
FdAVo0ewjDi3QSO0xuW3+sAsqAf31QDGxSa4UvxVlKUeteydmA1iFa9KE85TKj0xtCtgykHMj6ot
XMHvcAw5MDGbNtMsTkV96ychhkm12ITx2L3xz0zv2j4S3tlGB8bi+UimBnK2H41keKbT6vbhtdn3
sZQztrG3lZsBZ4RTAW29nD/FnoSNPjCLk2CSPP9zLvZSpwyBpvf0EjWa/ZqKRdHthhFh7XCNqlwZ
PCTlaqOig5GlsJ1enMqDyRFUj5GpOlS3XYRI5owSaS1PSK7K68OlGEsSNK5zZrk+RUby5TdptLrW
FrMFfw3URjPiAhiODWMXFMxxcEbxDbfLU8HlotEdjCNwkrMhRPyE/uUpxw4/uCEl4O06lteKGVYz
7WmPrbWj40Q4bmWPm4xLY0i2B4a4VGpW8LLwcU7d8x7kiQ+ZZfUmEXGaklVfoWZmSEFg3PUhLiUz
8xSMGeWAUIoJhuQAC7f+kClwIKaM4jGkdo/1Q/XWoJyEeNnuCjNWqTXmt+Bau7aU5RfbASuy5x4d
5FMYGbRhOTCNupajdrChShY1lzKd8VlmBOAYdKTOGzULqjJUPRqTnVVBxoExuuZ80Gh5egGPr6+9
5OLKsZXZlo0HcMc9DIKdLMMs2yhCRoVbnaRMnnZ+kQjUIk/y2ROyWDMb/cki+sidU2Y53OGbPYYg
z19DvO0DPsDLpuCWBqGyJ/LKBhVdvZfoTzgT0nCRb6SIHkro3jXILjFpZTHP0MXcOSlFWLuXUzz5
zgeMH5rA7MibTgmN9/q/KDwyZO6v5cWK5RQjSCZgYATw5Zp/RyDMNGB0ZmMIMClLku2ZrCg3Ae7K
PYvM562XtfthYRrJP2AvJW8Heg/DT4JHLKBwWKX+AgQBn8c6xbaAaAEDYpkBUcc1jf97r9eZWseG
ajou57OAHhvaVw+I1RYLZVXmo0IQjYx8bThSvFnXAIjVZ6loMlpo1KGGmF9CcXJ9IrYOvLwS4C8d
Il6KFkmQgP7lEsIbfygBQTiAG6YXD0hTNUfQoFBQGaIGs3ol8/bS6bZY3GM1fFrIhQ0opVdzSdYh
BbOrsoz0BTLUcpzmM3jdSnbi3q8fmje+cC1nRqCKQD7q37G2TwWcYUWnDHXy5gN5G7+KJg3nFYwC
K9+PJ/GVhdDe/zBH741HWM3t7D1G2jq+QCEGiBKqN6sXEc3a2TCCN/8ALEiUimxYNnW9ncFX+H9+
fl6VarD2RsT7LP58i/+zkA7zPGH9Cu3TFRmImt/jOo4f+ZMhHh/UfZuXt5YA+fnT5xTniIMjPl64
O+DSOYcBWvwHDwg7hRMaoIXByFmSC1ARim4CX/gnmlXrOi5brnt46d7oSlR80W5wJsqPE66gVmHk
0jbSCEBW2Kc4o/8NeBnH5XdtQbwtjJYdzoKNAbDWFZL0e41auQ3LM9v9QffLY7ILgHJn5nM1Mb+D
U6v/FvbohAhjO7Jmyxf3OzkpXmTZZ9mAV4NuYe6LCZ+3rU8i79126Z+WONJ8xh7Hb5o99QOzdy+J
wFo1To+blNSJWgGYX3mX2JydBMJuOiV3fxRa+Q9ZMJd7KFqmavtz+CHvS9c2ypjQW2BnfAZJ71if
PDiZ0peGC0QKPBRN3f9xOXfrA6lMGm3K6dDlX9ZCXs2TfpDlakIK2Zd5J4kEJAMsarwyyO4VK7BY
GJNAKq0iuAL3INXSzVncyKXYi7zix7TN7HXSWKgs5ZBpn2VAbUzdRIyImOu5GX9nYmj/SjLQURA2
9+6dHzJC+z67tNroCtoFSIJnBun8rfIOIvyRrupL9iCsoh0O317pFlWTOFSYy+czqlMoZ+fi+rAy
9VGA+PjgOFoXQKOO1h+RRauRHM16F4s4wNaI0uVJNPiSZj8eF6JjrYOvpn9fOU68u57DKQi50lgx
cm373KF3Nssl6uuzX9oZi6octDQArks53l0A9KgW3rn08JfyXdqN20wTGfoB1vZxCzAaGdxHuv1S
FDL8rWFBdrWv9h4mbMQoLnoj0Kt3nEnibVqQVVxnjBSTFKTJK4/FcSIHsVCeRoGZH4RHKQ0DVCa8
ef7NGEqZJtD9DvDErCUoLTE+Z/NT1td3rrOqWzL7fVXwywkyrhd7x9CwUHD/liV+uK+tsh22vlMG
OT7C9s0+hg+8cYN9YZPIgewQjiLJ8a4q+9Q7WWnlt+f1wCSGrfnQ9raxoSnfDFnaqN1X1R6Lp+DL
gBkqDvL7G8HX408TRkoAnAUO/AqIwJQzaU604eKG0I0/Rk4dQH0B7YMxm/Ar3sptS8/05aqvwFjf
Vvc+/LGz2NDiJ4ocqjjRigG6s6Dv4sfdNdTFy6UmRS2J8NEZYOKTpAoVeQJ3ynQkBXgjzRmpUiV4
SpsygJsZMXKoJrJ+wSKNWGs6Bmy9DcLGvBj8r1mkXTyVpGKfyqM06CN/zv1TsJEPem6RL49lA/fn
mpmGi9MI8eupmncNlexl2Ve5jtW+31OOzarStjsBZ/VHqRL+DCjBFykP1Wydc8ZoPlUUH4bTZk4p
ZT8RJR9DhFK0DcOXhcFikcWNrLaJ0RXN+3QoVn9zaV0axoNDVYnxB8b8llk+bdk26yUkBurKNuH1
/CetMpVAhAWbdTexIdHt1Lc2jm3QzIL5+BMdw6l9iHm3v8vqH8lI5QT2IPwhGji70iYgPYhaUyr0
ur1Eg+FVe4CksTjOTA99bdSnZa8+MfqqweQ37DFUg7sIpnUFe+rtkw5PpgbdVTriRQGgcVMJGHPE
w74yFW985inpN1J83e3eOHb9SKbpy4OCnBCde/4i0N1go0paQfT8CeePWEn+0ZwEkgAP/ot4VAYu
wDi3q28NS7qGYK4duxEHeCSAsdkdRn79dlDati2/Rj5QX4sD9+48OGTjM5Z7w7lIFCIeP2fbSFX+
HjM66UgmPXAwwReO/WrpziI3sbRFPHAI492uwkofC1aPtwRBpUG+nI9STYqavYmaDXjI01MIKPtl
kmmRS/80sORyrKODJ67tX965qlGyTXi32/K96jkmum1pB8bKQ40wKNdVTpnAzLm1Ogb7VNXelJ63
Rii8vlNtMlRqvmuMywX08QNzihF95/hlJAMtc99dpznM0kFJVPIebyvMaFZkIJOFDvoagpfA/6Nw
0LQoY3kdiqZsq2qqyzzEbXPG/2ZvnAevN4RJIdj4mUnPlMBe7oVvmNUQT0tADZ/yXYmfut6fV0Jg
EUcui3rELzeGYGvx3/sLeMqBsMb6wnuQVa3DGOQLQtIGxB8DYZ43mhjkQWMMzuHHRvrVbzccbSjm
idPutbcBBGdxr8jSE0vKEfQ5XteVnbU/Z7RcullHwmGkw0ur+DPimr9DGf9G+fkVdDiFKgGhNxlr
5CaFmZ65jDOEqCCvDOUu6nw9qrHCEI7v3RladEE/A6WeoljM+M61NafrEoWZ/6f6LU/dm1C9L4Lo
O7mPKXQe/Yp7AtyDeu29zV1K2F9WLQlNbb1Q3FdXFBBg4kj6nMjEqATX77BlHw6pi7FoZRt9kzkX
MAeacmrFBz+fpGQ3tR9028h5bhpo050v6JX2iLDEIbBz2kp6t9M75KKNg8hiKhbByCFuxWuxG/RI
I0YwvKOoX4eecJZn1aw52gotCNOYHurLu0Zt1NKq4DXv/5ECr4ZlQMTqwdhmEjcH0+ca3SUqhM3f
EoiN8iNCYKl37j9Wc83H34LGonf8loVWYeZf4uzoVTa2zNqGtF0++IQsfqIszO2dQ6m/GjWVez/r
nhFmuoqMCH01R7zAUNyy1gzfyZqOSV5p4aOA8dJIxE427BSQMs14EmvgBV7iCMzU7tDjhlBVJZjT
1Y0jT+gT2Y/6KQx18/xhUPGWvJADpin8p5YCtSCnz4iH+/BLQXvAC++RcszNLgvWSrwo7bykcrpY
Xy1SMYXCEqioKl4ZJunYeuoNM/QtbTc0QR732DT8+w6v2n2QwvwmMtIxViFoORhUIlNiQcgN1cVr
oueMn1868g4S5+b+hNFefYwkqK5IrBdy5BZg50NfHfWv0J6gxVAZvYyZWqOxcxXC55yTSdgaCiwI
1+uL4RDiMk/fTX65EYFtMg9N8VN92tFqvxUgnFPbkgDLjYNIgYIZK3NBFWZTkV2axZT+CCJ1Zul6
oiO47h5wNuZJCUVczqC58NwQb07OX0oZ4Ao3nIe6PNkiJlHOC5xCRrXKLu5ymoexbzgIH2E6CQpH
FW0nKeKZtwww0jeDW6jCdp3MMtWAnUGJZHvrYMeqkw7tP4QQPe7/+df3YeCeRyfJbUR7IyMLjKi6
u8QuvSdSq7IXg3KHAxfIwSldfsARomrdXDm9dCBmuCV29Hc7OEEAm0JiKGFq7Fe0c6bycCkx1lIV
P3fjBvhEJfvMCc1ZUSbAgPcQvtrr9+hZh9DQH+PE8eNvnqCedwTGKLcFKhWmA5PeLVSL9yIHP1QP
ok5VXHJkqBkZ9Dj8bsa/5FZWXlJyI7YhfDedSkRgOtM/hlJBjtIhkTQwAit0/aCyQFHKEU9H6rFS
LD5xZXfW7A0N9rLBVZzEvoo7TNGquCGa+Lqd7IuVFt+R/xhPAThNSltaKTfMJuvMOIyrfSpIGlq8
xkWbGqJhc2KV8G0Pu2HUQtznxj3gcBuiPg9ZIeOZrIDrsGJFu72Sd+/k4li4ZeCIMAZMocllcL+e
cmcxVMW1xXoCOQ5bnXZec4t2P0qWOQV27pcPmswok5yvh/m6k18JDPH9+4Az1F1eTEoZlyz8UxYA
38yh1NqIbKzDp6IS1Rhx5e3jQTCswNuNf/ViuaEDcvSImFJJ4s7KMZavy/bsv1OLAqQBhwGzph+0
NNI2lvSC0j53SqcVC0WE+rnaFo9xncLBYsIdt23S8e+6txqAK9FhBmYmmNX1WXeTPK/FQWaAkx0A
hkMiZ2v/D17ebg58MUWVnrmeezJWrVlBS7elSjnsXVxdkzA25y3yzQcCGVZBI5kgcqNpyms/9O8x
7Q37IlnZzmFw9NCICUDNWCfmLlsilw9I59pZhsdIGzUkF1KNoQQeLlPZfXQk+Uo5lnLU/9pnEisC
rrqol0sCwPMiR+nk+gB6WeO4APIHi1zcQwLnEsZv2OzQjY3oifCSOxWrynPwLvU6L133xEd4VXoO
rGrQYOeQrt8u8bhUMcNbu4GXRQ46L6DJ/MhfvFfQMK3cmRGCsZda5cOD+McAZqnhvXxiQl0L++G8
Uo1rWsPMoFxTGMLgfs+w3lSiMRVdr2TmraX7tlP/n85hitp6tHjSPAgZEH9OtmmpPJHe9B+vWht0
FfFy6BYMPl+HuPbL+Cg32A+lERTj4vsMGGlacNp15XtobZ3Jgr7BkdECRM1g5k/z7peM2L2W6mOx
mqgJEjqT5G9NdcVkVnwxiNdNNkc99yOrTgzw7/lhz4AAHxuzIzRAPkQvMHcrJT9CtDaHPEflIMTz
Xx8U+Jv6BPKs+hZ2FnhV7Eq7lOrK0JQj8bLVQiwxPo0o8yDzwVaMvUoQVAykqmHVnNVtRGGfnK4Q
tJyJBFYNI5gjuPD/XmdKky8qa5cczz321+VjNpj/RgcIA25rzmOqaRZ0KJsQoHOA/52PpUYX3T+J
g05voPwzSWlJktWJQIRCTcaTjDWUiDMDa4eATlWqQlySb3rINH61sEl+ZeIdNhW/X9Tf1FiMFh16
knYvSG5NXjwNJMyCzlyo/nHh/VmkO88Gr/dhuY0u3XMXJxNKh6ZH+hUUelCWLYWJnnjSF5JpkDYw
3gzfBQrxYRJ3gFNMIyoPKncXnMlZdvz1Kco8k17+m/AFLEPEobS16W1M+FwaztiUPqTwb/W3pUQ9
kqpvJZbRTeTsyV78Q764ovbVkKXlzLEXGN4tPej61SDVa2/P8AArRonfaqnbQIn9AEyCfTq9N0Vy
7fmVLJ3mLEZa5GeLg9haAz824IUJhKOUSTnMLNej1qVtyxjZ6M/rHjIYOVgRxl+Mwb3Go8z8dx/i
A0w2XKZ3omA6hPycDcwgk27sclK5khhy1geoy/N/ecwiTP93CrG20N+Cd+hN1uU03B0WCBfDOFS+
gd8N5xo7+VNLgJR1Dq88saDgncCSj+xDIvzkCumCiJtvgHDsMMKaNk6VtHieBDczCYLFUfPzogXn
pNyH+e3wLEkHjsxsa1wtY0HGD2c7e8dKLtJsDjiA7UfKhNs3agstoJvvyaCzbl6ys20tDLEaxt6c
DVJ/Ou5WOVk7NSTx5umvBbsF544R3YsINkBiQ7IVSPXgpjuw9KIvRdQloyIM7yJdiJ1G3pxszmCt
En70yj1gcvgNcgCXM3iKULl6IuCtf3bkSZdH6pHCU+YTD91zFaHLEqXfrPsMOFPyRC813MrOwaWK
CTQ66mM6qat7wKASrovjtJ0QQ3KHrWz2pjA5duxp1BAUYkQDvKUuAZsGFX9OBYUEV0qJDXNRFR+B
TuMpf6tCk8NCAE7F+g01EvudVeZExnVz0yPXmilZT+N0fbFdruWarhuXyOnN/OJnCNQAEN8L7kQc
oTlsdxSHdZYfeZnQssGjpiwmOWzyZpg7i98h+iH7WT6sIrvSdA8GoT0m3lC1epKkv0PJmiNbNoXx
R+ypWOKROx4dDrw28koHWSrm1fVZL/f4lkOzP0zZsXDhupiVLnpqEKvdB010ZY4lS3yvgaHkd/js
RSrUUFdqHWlajJBZ16EyJsP9xOJDC14vvJATJ7jJs/ImcUk2UqVbEJCZjE7MLf8ZxESiyqsVxl2i
bHQxyvVbEud7eVwyex2uvAzHdO3gE93X+R1HAUXnZpeSr8MSaX6A8SSjajW0PcHhj2SRBZW1jlcP
t9BAB9IqrdhuF3CP8xkKRXU8jrWzm5kSQ4iApjV66Wb6rCbYFvbgVaYiZjFp0CPMn4l9bPz3u5OM
0fco1Wnf1fiQudxH5wK8nria2Ly/n5qNVHjusBK1Co9Cgov82ZiLgKc/GHyTqSG+xCd4iCtjxUvv
3GKwjvBzaSFAkb9zye+2xkFv/ckCzThFkTTeoSkvIQEmpCHanEvVu22HfEtvWMQDvRn9jmWLfVN7
JHYnfzJyPxn8nI05BXxs9hGHUyw5t5CFZ6jxdHu62gUuXzfKQGGTYSRRHUx6aT8o/pbmpZd7t5Mm
n9WEoCDlVYjBk7+aJOWYcTfcDmG7Xtu5rVFOv8VaoDEZw9dd5KR/hwrr+ueVNQhnikOERfGQk2fl
aPpe87eDxFTq8IC/zVVQcVHMshnFkr7oqicMib832lAGypvZFN/Vh30ojYu0niEdreNdIdJaYbXt
ydPNW9SxJ5FDyXMtmc22EhkHvXzV8vTrKs417tZs4xL+MVq5mZ1E6JXdD7XTJkTeCiWl4K05nmIX
D01bBN6v0IcSdZlxapOjvvoKqfE8e140OzJxIBYMSbEd/ZGJxZMTdm82fSewB9xqxiwQsMwhfHwp
ZO7iyvF6aLrn7T/nXnsPyCXpOsb1yE9Z3WbFKQBvr2Pk4PM750CBY/uy/zF1+uo8VVmyL4RzjSJU
Bw09+p6xTt1LIAKLPLLEBZfVEN3n1uSMj/dpBMAFlWh5frAT/vtVf0oyLKqE37DMsx/2XHjJenqe
Dy3I5dxeyKLLGEu45N9suP0a9PtjCEkfg7nbLMnlpY4qMfrLxbBIhz5paT1SwgeBRbuHiC/daJzm
S8N6QyJaYTyhtCJ4OUWmYc8SCQmgHvKGjxgbqjBFpi1H7G+OSR8DE4afJmDixpFpC/g5douXxOLh
TzJAKpWbw2IxHfKtRl0I23a7dSS56SbLo5LPm4By7d5ZTiIKXG2v79mRvGJzYiTZZl7GJjDvH+lO
q/snZHqFP8ITcDOTEzPvK+MoG2ZvrUh+XZoPXb0UcIHEjUI/Z2S/VTYbOzaBcS9sQiXBnkU8DfIR
OjhJ6BtSiMXD2g93nh1tkt3e9EjKKNjN2e9v6ZAptKuMaeYPV5QoIkWAebleZjQmj0Yc/E+dQVaw
atsgyV6YOD+BopqYrZKe6kXka7y06pPzi8zs068XOA9HYWlzrjtr0oO7LRmB9Y7CuJWFYTUStzKE
JtVKHuqo1uhNvxWJ1foKIU1b75R0Wa6kamWKKPO3XtZwYzxnxePIJNi1O/lq+R/sc9CZFSjr+K4D
ZOCnAdCRrrzcLuikBX4A3XDZBcG06Kfm6WKbmVxGu43QFn/kZQXlshP7io9FHJzaMApleoX4NCxs
BgnkL1OStREMk85Iged5O+wK6jFDVlXyFRZjfU5UxTR912vMmvr3SSzcbKNUyqKmQ01LEqdhne7M
p6AARaYnmOS0j9qL9Ju5o5+jdbJBqrNY/CZ+xbLA52g8apmGYmZlYDNUxdlUKHm3j2N0jyh9ok+j
KHMDhzya+Tx7PHi+FBBBeeqoB6wm79YP01URJjZNAgo97R7kQTur338ib+O++gaCx4ytGwMXjxuz
pOGnpCmcMk7CkxiM6rBdyuTNm2W+Q1XPtaJZIYtw4K29S+QmAaMrZ0XOSzKT7SucToDWeo9+DpxJ
kMA2Afgd05olx+Qj45ngBB4PQ03MhIlS+Yader9aR85Ok8e9S7zUjgO3vJt5eyiajoBQZFMv1sz4
5efK4UPcF2jKv4IPl9T7uG2VfSXoXdAkCTUFjql6fZKNGDDRN7U7iaAL8Z2p/GHlsRh97GR8KfHE
iAa8rSVGqL/wC/yeUI61b7pvzN44v18QTTLa7ZOEByERO54YDaUFySNGDqCTmRz1XjRt7wY6UtRZ
Gg2vQoOIHOh2JkB9rbBXq+QHM9MI+6YIzs4mWj50yp8oO064+O5maOsGe770VhFB1c7N7Qc5r+v7
P7veUPnAgVUoDloe+dWWbKQpBGGk9IAGl8J2TDVlEiWdzLwOtmT4npuusHJDPZr59axilk0YxArq
1UeH8UWwdwOmAe7uvmfLLQI8EcAp5UjDtpG25Gx2zLtEXe9A+umTSacEfPbSS3mIpTDnM2vKzokd
QxGoJzHpyZz4YFQjwKC07+QRZiyXdQzOul/AiFCS8LQ+VBMKGaxmVSPgwC0UxkNfdSvqvyXj5P1c
Uth9jWACwHpNXK+mqmVANp5MhUtGSLoigqvBb+1JANvo/+CSKsANlyRGGhmhuif6CBikFM8B8Pgg
/khgFozYkGpxxvugswkvUP+vbFno3I+G2irrBg0iYxj5nMQHNGGNyIRixxfKLloGDPYDz7cR5JeU
N/T4bYmVHdVOUkH93P0Xza3gd3xNHBptQyYBSq25cMp4MueYPkGxbPOat9rVvoSzo5qq73cK0v80
L+qSbZ55qRQxWyiGNFUPFB/O1p7DvhIiOkVnQW4umjd/hXRPgSDIasMkkvJO6mQQnvtEsRXyxTJU
6zyIEl2CWyMta63JHB87DfeDNwRzyFYjcO2r8GwRDQqKAPSoRhDqZA3sb+0XyWRy8Q3IqtQGA7aZ
1kUE0eOZTY21qW3uIJB3CTDVzi+s8aNMvR3Q4feI/V70r87lox4SyFzAyb9gNWz6cBJkhX6dWOtD
9ffT7I1quGXVkBWVKjM3RVYq7Q7Bt9HXXpMr3bW5ghpwcbKiQvvVq8VCS+E6UDfTzukWstS/Wx3S
LwNbFd4hBfAW/ItxjivlL5SOxKfKHzGHdRZLOi9QIEJl/LO7TSr2r5UUXebsW7ACOipaMptoRZt/
3JrlsHMczZswvRKdOaoN++uoyyNEJ8RWZkpNN9iOoMtYMkAecaFFCcc1Qj8lpOQ/tkQP1vTQ000o
58UbURsdrZBSkmKgijUUFKwUMjnxzyj8ABABNHn9pNWbOBFMAaGtr1xgbeov7PIqzjncplrT2v11
EqulqKA8Ztb+LJlnnKYinDJCeMqI6mfI0xwdc5IQ4uaKUPyH5eR8DGpSb8Qp4e98FPzKJ5sI5tVl
C3r1SmqDey7/2vlLP4mFS8zFCnNYuyxIFBFX0YJbvTglkVMxjDzEG8GlEZvVEny12e4V4TQObngQ
k8TAIJhp5kfynVsIpNnCl/evn6vEyPy+M93qI0s5TrvDt6Jkfii3G4ix0Ma2iKUqtAKXYPAYCZV1
XkaUV92czRBS9v2zhJs3bzlYP/NLSgjCyeXP0MmFgTbFcri19DpeL+QeankxLYFG9mnD4CQKOlmb
Wyo/DJ1Rt5k0LHP6Kfu7IwJIKPTcyrPOvNZt8XPibCbjAdvqIy79AicnlhbSFr5kFqL2+Qd34fwG
GHVO8N4lFCr9LL5MZ7VkVCcWfGLp39p5b+P0n2bZo025Q4ZhmCMZNui9nHBu2n6sDIDG2E1VYX8a
5c99vb7gdsB1WVcgegbkMs5Jq/BfytjvG9FEASNjdLacPIdnP9NVz4fT/Ea9o2Syv76DqHfb+S2H
1Q94+LVV0/IjUxzy5hCdJG8aaf+dibn0bM9In/Z8B4Ns9/Jb6iGArAjuAQ/Gs0HeUhvoKrnPs5aP
sC+G4CwChQn1jdhlA2vlcumX+msCX+l63lrU39u3Aq2tyhlm3aAtrMTgjhpJrfuTMOYhp9Rkm/+e
JbqD5AAuuYw36//mA+y3e6YEL9gHSOAvIXcANZdxPKu8M1iCpSWfgWNtuRo3NjpVY8N99Qt+KFUd
6bH6V06ea1VzxDhgpvN2kQKbdiEDq/A/xDg1f30DCwzzIA4ZHg1C9ewrhlt3EX6YUkQPLlPRtY1E
cj19VWapJ4Ce9PT2l8CN45zNNXcNiNcees7w1HQg/avM1/Z3ZIqZgjorxiMoJq9PEjpTl8LN5mrD
2YW2M4/K/fmZuypSILzMWj55QXO0JDpTn9jIb7ByaWqzjgFE0j/Z8YFBAjUzbizguxz6oNQ2Bdqz
fpEXr01msf6gNgZG7SLFpm9QCKmxoSb/LmK4kJSL5iXSWf5AVLKMeNwmoqvprA4OsvQtGSS+6k+L
TWtqiFUov3RvyLspAteOcVImj2KLnjpuBN5N2TWPSwxChfFK6A5VW1XbyG0r+0xwLgOXBnP5rUgl
RuXqgLNR31hA91E7PbmYJea+Sr5mOWknC5j7HcwJdJuaZCW92PEQqSR/fDg41CAu7YC5mLdF2Dhj
zUlEpZDdp3ArHTOaqcxfOm0ctQ/vF+Q4eAYV263f/wShJsPt2vpf42ThKOFA83WX/HhiqxgYy3a3
hGp2FKS5eMod6mlL4Rf9OoWFKeOWHEhCjnIEdQQ22q5mzjQvMQn8wr26fnzU7Szcyt9nG/QhF+zU
tYlIrRN61SKOGBT1pDzNWxnfr4+ECArG3tNfDBZozm6Zpry/JY5smlYcYzdQAgozguL32ispBCpJ
rKihyMOexk6pnqZnwW2VYy7A/oeNggwl+ct5O4CCMEUfg5jxzkqfhL9fLKHRO2DcD4iA2cXCKyL9
+clpZZ32pnVAJ6NSW4dRYP/bPLOs85P0dXr8fBf5GLJqftdGA7XBF/QbUWc7yYsmdJ73a+3sIyD3
Qp7Wn0Qh5rk718CnY3xtCcItM5QQvDjI9AfkfJwapZT+1jv5V/IDlrtqJ/8rO68vS+HA7S27GKJ0
XMvFzZdaFMBdo1suaInwF5gwwiZuKYiymFj9pTaZnqAD/8DZfSxYUhzvq28cOnc7mZ1iqNubYEny
NlahiHYsMtVbvzzn61TRBiIkUIQlU+i90no7P+rwm9g3bBNXrfOxduiWB+iWsSEukEjKxNo3wmlX
NzynIz5J+7fS9HnIGU1KtC+nC1s1ijhWOMl92JUnKd20R6hidZynGwyJHcGlso0YITuSy2uoDrdT
W/50n6KLF9q2+fT6wqivO3bncGPRah1NxAIIwfBgZ4YqBL1DwCnDFzVG20zsUNePQ+o39BPaXK45
oiMTSBdEwUq7fE3WUgBaQtMQrolOBG+yJm1hgO6mpXzNS7XSQg0LwOF8nsj/luOhShC4UxD+KAvM
z71NBeRpi8IloSiIpQB1DOYa2lvLBxxv+0AhXO7/GWn8bEzKVV9lm3C8WtndrbLA7WNfP+Wo9Z1a
v1AUBLLePfEujr8nTbiwKxBypnMuVAhBNCeBbShEDdAOWkWw+g4hlSC9ivqsuKA1bKTJUjLh58BL
ivM5dQUjwJO2pamP/uBP6vAFRHDsdltBGy3FurfMHbEOQ9nXmLl4oEdCVTVqdKZtDLt2IKISbSaL
0rOuPJF+hnXUrnR9uPRzpmx51xYw7hZKhHUgOgttd6qKcbaRRr1cI+6Znmz0usr53yX0nAX9yLmD
6fZ4U2YFxS4ZFA5+c+ZW8jCycFkz6Z2exTklD4gh0xLYBYaxrPBckueKtC+4meHuR/yNx7RD2QNu
IPaPT1mBtG0OwLtEiIwzXrxWbg+nvEkAK2/659+xtcDrfIMwtScQSxOqcMNhVUA2xvOyg5FLOMjJ
IMgKORZPu++mzguB08qMVvQiPUNnU2rqY7sZWUDBhdVyYu4HS22UU6NBllX3O7y/OSekHUZ3WI/H
wktDRmvKy1vF5AAR7C6J1tueYITdzdhMynaNM6/TRhHuKP0f2XgFOQmsV+973RKQe160s25ZR5AH
XiVjL13+E8vz8sf84qLo5eLtUVBnVYClCW6nWuOC8H5GcLmVDE7izcZnrBeoX/uByciZhnXbAfm8
HDoDIyx6uGlG80uzJXj+IK2Cled3/rvIlnI9tyjMDYX3wzzrMX5oY6ccWDU4oFNcDiAtnnFa5xBG
X+gMh8DqQN2i8im37ripIBJ4b9uXHoAveZvtAr7goIIImYk34DPBdOONnDFQzT22ce4+2SgTutcR
N2ngS9bLrY1CL8mZ1GWh9XHDZrVO7zuKYPMmxEgCmA8uIoBfscRITAfmlFLfdaKg+bmvPruPCnBC
ZSa2Ss/OHE7F5fZ8jiu1VdfrRQovpY7ii1mYX2lY5PNhtMSE2VbXqFVt/s4hh3CvdDqWerg9GE80
veIlXfHX5mxs3W7A7cjrcCmhIO57EGgIdN2T/YoYQYytCICaieka/5MlG2qK7bIkn5ngkNsrjUYv
qjCMleA32PrkZhbdlQGmm6VlCeszFE4zPX4ui2AlNohkxb5GTJRxv8hRGMj1UEPk7TnacE+VBRmu
dK/ZIHE1cOytw83Z9lOzeEwTP50LSTTKFGSQmBd1KSvMeGpg3gZa39zawQyzbizL4fj9S3O1CCfs
D8Q6vizOIhzlwx/QpBTXta5Pao+L1AfThO5sJjifSobhS+5ivuIMDhmAdN5ZCm6K3X2fN+nZHeE/
Z4EB12O+9qYbJzzM87xveBFqfhsuY0erTn86JjcwA+f5pLC2LkQ5nRSjBUdM1lGArG52ZeS8jeHP
WowFDa2c4Ahn4ejsemZ5puMHLsV4BhvQxCYdda4qSW285A4cPFb/9yiMZDrRIa7YJqVbEnuzXh8Y
W+pMG+1K9ix/+9aF2k+HJ4fb7b0VCcGrhzLq0+OrDmUOijesQhW3Nmym/uZFohgIVMDLN6jkZhzW
PA7hUWxjMlWXs008U3JV9ZCBo3OhF4ZJB1thuB+VI2CGVNASMdzet9g08F72Hed4H1yVsP5H41ry
Cmx7nn0abV0F5I+twKSqCg66Rthmu3itnOQoP5uyCHhTbtgoNReG23nsND3zQtHIKyUWG80esjUG
GgJCv4kG882Ax0jkAbxNsLUTZZNNzXqi7cZygKuZz7cAXDh5+p+r1g3IJvvfAaDhvXK5I98iNfRT
9FEj2Am9vlbnC5BZUCe48zTAT+cPRxODH6lpWjN1HRx2K8A4DdqP9wWnianOnmluB0VjMgNH2tlQ
WVkYpQrSz/Ar5XsvFDeLbxJxZ7FbWEgq2SgaNp1A5hugupTcZnzfwco7EsD9Su9oq/PZNXks2s7Y
NjVxYWq5ma3s84IaInhtqevwCZ557m83zcj/r/WI3aJxzJGjeft7IdA7OKwxQDhmOD160ByL5lO3
mFgb0aNMCYRnR0+xfhC6pWjN2nawyjWjRzPbkcfQZD8az3kMLLQ2UNh2Zw+J12ElsF75BNiW++/7
TM2E+b/KlewQTr0XGVAOEDbPPaMiwVKPAG6SmQ2/sBeFoaMwkNYvA+oj6UTIdFrmSr0qKNRsflNT
AARbkNgRzJY0XBDqGWf2JN+qQ3xr3aO/EfsVw8Rwu4qfQ+q9yc0XqO6In8k1r7ka2GRLKh63/ZQM
42sOWQMUwv+pXGUHZ1U+8ctKQyN2oSf6WpA0ikQZklsKfrUelk2cNS6gaoTf/PO/nO2/8Ck7RYuR
j8ZEO1xAZac9poTxSQVfVDb2oZUqGmDJ4B4AadyEB73BIRqqruyOw3ZWlB+StXEY7l90rp5onA0I
FRuQyhlJ21E5i/XOKy8ZSs6OS5hDu53PxC+x8wYHuJGFMkPzL/T6ldia+eQWAdFNDJkAuh3aUpPW
mTKDiEKruwulrUPj8SIdXGym0WDIX56rM5aktjgHCBxlS7A4nEMMqhnqF3dBQL7Hh68Lvz+LlFw6
wFJC96fMyCfqlcaY3r3fblXymS9/iaHAAUbyG1lXYN9IzGsZMJA25Ded3E5EGs9BsHLe2PAP6K6w
h6UFNODAscV8YH6UaORCB607lxOkXbXPvh+vdTTWyaT7m6u9z51NqcO7/JW5KyGr5IXzSHo8KbUH
upVTG3dHDTBnoUv0YBBakmD0u00BmPuCBc9qkP3pigyhAp7r83c7t6RgcZQL2M5gTeD0pqiIr6D2
HYpGm34lX6/kj67p+X+NifHyDWwA8OTmNV442wMidfSkfcL/9ttz4aAPeYPp+pXYCAhgl4u7cnSn
/fp+izpsNAoSMxgZKnAwB3pOQtS5jL7TrdXWMnKT5GIUKj0Q5/U1TnhRo6TU50rpHjiAC3H4Tmp6
tV5lt7d5EOGRF2tEEVY8e7AiNtbwnuErY2co8iwPDGNohe2hW2znCc7WynTsEP7Emd5UXNoDMDKT
psKsoPnUvPEk1rT9rKb9wMTOtsNAPj0MRQML5p1Xis1uwDPWf8elZy+LVnaJ5SgEFun8ozukCbLB
CyIGvSYtZBXknA1Xrck83rs7lo1O4V/uBVL7BTslwQrj0sShw3AyYQB4fXtfwv75fk/aewAD2Pfj
GaAh3crUJzO1o/pWFB61XI32WLNnp7Q0P6mRGNYvAjd1w3ymIGwgHWmDzYEKsEvSrAsA4gPJ1Jp3
AMJwYOIgzJJYnSzUxzRpa/l4IshtrfM8dahtoFHU/exiTtAPvs7tnhU0vZY5yflnxx+S5K3K6R64
1UHli5uEHLjWQCacj8Cl66eYeUSYy86JE7+K8knkLXEz0NErGww7Uk7DgFP7ZbfX7Xax4aMBCapb
wyaABgCQ7BB/eHnLPN9tJUEBZ7joCD5a/yVHdJ442IEavKZvfYvW3ZNpXuzuCUDWPlPPZSS9MwKC
BhQTKClrFKRv5pmgXIRQo/TftFewFW7eUKTvkVFRQnySocfIwMMy0MyYwBwIFwLjdICtGZ4uhp0t
3hcvApBiUqzkq2/6czI/m2iybgqVZw8Bc3sN3KPDKKrZpbRNK1Tsy08AG+mX/1PnyGx54KLkyHOd
KPm38xJID9Pf+csFEK3heHRCIMFHY/HoRYCWBP9Kshb1kTgi1yYhHN7ApjLr9OaRjc36MHRsmlz/
RZ5USNytHDPFagT9xW526ye9cKcOiuQuiEDhDk6BNgMSOWXU7/iJDHhQXw+V0evnEt83JqC4XloJ
whMsXfZXXL8bsGofCu61XJY8/MPmYhVMmli/687K8rGA5syRrF3gmi6kOok9zYCKHJw/mHBC2/Ej
nbKf58aAlNhQsiViTP0WIBlpaoKRZZ/Mv2LUr55/RclO10IqPmfQ72RPLdHt2HdtfZcCq7Tu1XpS
7wmQmBGu88xeVP65ys+lDeM9GPFReGq6S1gnWhKTRwkzZUz6Y8jR+MNIK5Qh9XvxXA1qsICz6K0O
SomwKcIwToBGkZZSwJNMDGU0orai9Bqd3WXHe8uVjlaJyC/Z9bLapt7r0/PWypjblsaxq75LGtRs
TNrFY4ryoAyYualnLDWaNokUpD9VuuBTGyPr5PwdtPlUd4Dqp8riS/bWwKYTdJhQjV9vDwSgs+Ez
Esj6h9vsedaaQf/mwPI0vC+Nu7zXcwlesDK+aGZ6ulyhmuYHlrW0NMlmdZN28ct59OPlQkJ7mVH9
MRX9U9A6km4XUwjheKOJux8FDmWeG39EIMvzvPDVwo3yomh8F/+xj8hqd8luiW8gIJDYZAzq1CKo
6ypbKmrwr+icHTuLiNj2lbd4vOzVDNMz/4rW5lNjg4NvWPuyvzR7wLTNaXqeHKi8kWXCS6BeSIeI
X1tJDc8DSCV9qCcb1AJGuAC2gHjbKtbupJC7Jtsu1PhR7IR4ZX4rF5UJKsqCiUf78eex9gg8oYGz
8xjkyEexGVy9+uyk1M3FxmCOOGXHFjYOPQvHeADICMRxnW5fJ/P4tF78uK+rbW2iwicqlDgdzuMg
3Ydc35PP95jv32Wigw7uZx3z+hxGa1H3AYEW9i+ZXSKiQZ7+x71+K7eqhv+h0JXRgbHFSxoqPEFf
DxenyKsU1dFtbQCGX52r5DAV3hJB0///ZOcIWNfZuyhvgmV6zn0mYyhlLn9H3cZPOJEzLHxhJU23
QSZTmVxQNtx9DxI9SdKo2KBcqaRcbtk44Qp+Zy5/2zZ+M8FS1Y50QUFuCyR33amrtdw++oo3aHvJ
dKyhtNBgaBkzihpGOBRU5oVS4PQUc+uQd/FqKcGN/hhJf1Kma2VcVYNtYAr3TMcrz2P4SVRI70ds
Ea0c7YXLCJHdbxIHNRDCytljR3CmMv0kKLXMSyqet7qvFDMCOXfjAmOS2JMman7ziQ+4OPOWSBlM
jycwcnJ+vdQ1tQdcLRVdHi5PdGa2rJFWCqoVPEye4rqYT1QA1JnD8IrBXGeuN+SrLICE8/L9YuX4
E+yV95sTNEQM7TPxm6LXyLNE2cL5n5W/IBl7Rq9IqqUGM1eJyKXEzHJxZUrpOUN42LG70ViVmUGp
3mZ98F6ThaZxRNN06GtfKGcKS+SPjUDWIdUmyWC2mPCbJH8aO+CBnV0W3Sy9pKqPJTo9duYIgFyU
BY81bJc/oDi6eERxAkrQ5OzvIgASGvF2b74HMuHVKUH4kceFJAviFJHFoDJo/+ZDsf4tyunLd3vA
dlBd0zlDzkGnUul65+7DPa2YaDbIY2tQF2ZOMDEwQG29kXLNQen7pQmm91agINK8xxIt7Z6MDXfk
rIcnoV1IbCkf0FmVnbNPcQLCwABHPF8/SL0Loq8xS7VoKXxhaiWAfrua+XOzslpdFoa+6BlBThRS
pqZ/A9ZI0ggN8JeGfmlYVYulUFhIOmHmRTYqInRI8CY8JeHYDlVmSyhdCkC3M4g+/JYt+GCPC143
hJ48cfgtZ+UN7qwQl72ECEvSaqUEZu22NmzPpTU+l3thTgvvOxYOkG69lBkRF4n0ds7agp74g6WJ
9lt4SRFt8Gv1MouKPu6mXtATjdL7/OZukTw7DHj511uPk9BkW9rV49ZyzObfTwLRMO72b2o3JJTO
DCfbqcJgedYQkPNPTK/5E9KvJv5Gf6eX/oWduYG/LVlNYb7fXcp+U1P9DQDvFtKKBUUa6NzSZpDU
ERL89p7VT6+9FfSDq8niVErrCK475XEBs04ZQ/UMxEZOVbkdx03we9QArVFhpUU8QDayHlFpKlb5
4uB917WwI8rvs90H4HhFUidzaP650NUhhx6P3RGkdvajee8XcpW33QznKbRnS1uRlup1KcSw6G42
JnFEgXGimUubFFdW4mGQvGqEe5Az/c9qryfiieDxYAPNaOWrLnB1LVX9zhtESd/t6bkV5ZAcR3Ft
ZA1oXF6dlgX5SQr6QZR9u7s8O+UeVkQ+EsnZnJCzq7NhkO0U/e8Xq5NBweghtsHNx7HGDrRzf/En
Pio+J/yOUBrmOk9yepVE1SU+jC7sVfatkoR57FKxk1aDB8A64yN7RSmcvFE6Cmxfp3q4sziN0uvk
yIlOJAt8BbHP/8Cs2L6Urtk9hV9MIKffx9LFg4wp1Oszu40X38PasESXhN7/N+sPcVbvpwqRhEzk
/o71uxRxRio4q+yBlPj/hnMYV437i5fNqwxXtWUBt19bVl3WxrM9ChCEpopmH7LsbjksTkCxvCey
dG1t27GqiPeYzgWHV1/lM07n/KtOLDckPTwoGA95xrf8zjZ9ZoHlDiIb7OPNnwc7jWg+UtMX1cW1
OPeiJTCgGIWBIy1R6/dVIoGrZlxrjj1Bzd89fzU8D0SPCZCXTxOm+h3g7ffhm3ZUkO2TnVJuqdPC
oB9C9Rd/W8awsymopeP5AD/EsNyya2ZrmJSeiAfCRIZPGstsKHwrQJ7EzZ1grTfC/YaRiOPoONwf
aq/3miqNNOtlf9wXQ/B/7dWe+dVBghPAXqufacR/vND+gUKr33MeMy8xEJOWqMFLldEYeRMK2ksI
e/WxvljLCgol2peL7L/2BHH8zA4oHmGN3CnoCBO16WNwkMprkW0v2xPOkKxLQ2m9bwxgVL+h98mR
xuHbOKooXsaOWGQnOxJhSM5VtS4P8svQU/DRgJf9JGPn1th9Jqbp30doL9ArftsNhmMk0qnCqSvZ
t+OIO+JOC5CaU2sAi1av6DyJjGx7db4Exgk90qRJKgcj9/cwIjYHgPLnwlaG7jlCBqx/PNen6hBA
Z0hTyat2cLISWuNgZw+zcbzepI9RWEj3K5ZuR2HMfiWVd1/K/msMBlxda555z8bWIX2nJIKBOoXS
DeZiDbxNafIlozIjEaNJdAUyBT3H7FXRWVO4qwoSgOG5YseVMuokdPXsqZ30wRHI1kXl5/pFc9f4
o6XpaxK7EP5vstXOKPVh1pwSqSCYtJS+JkQ2TzEkC7Hr3VBzQfkjOgaHtcOQe92XW43Bm2zIslDz
dNZuRaJY4cgXQ6raAbhXzmDs6z3YGgaqUtNH4lfm/QsFO39IZ1NYWKW3CjbV7OxTSfrfjLn2R4St
27iIMQh1aWHlxQpbtOXbCO4nZfr6rEhLPUT1CgRzHnlSaUyqFuCqn0e6IRWsY9rt683gGLE/6BKv
QJaFcnbECHZ5Lu02gIE3efOHJ5syGcbbmKpAfLLJLmPzjQIuQyDi3ggIx4JKRT3XjygHF3WjL65P
gCFjLBacQk/6rv3uEpQ+nl99f3rLek4a/DSnC89HW9sIJqMJ+a6fwjHG16fEu7ymasu2vMX0cxGW
lhmkvsujbL6Fr4P4DcIJU43XTcUSgojF5a4wh/AKgUw2J5IpoTHAjuHc/ZIB8yK1vaLOxDTd9eyo
yIz2zHKcJYTtmt7oDWvpDVKP9uOOq7Zi+cOE6wiB053UTbsT+YLY9ccmP1KMzICrEehQOpcQ8o30
E/8eWLLpJr0u85qGPs+AxeMOApWkFe50XUE+BE7J6TH7HOO8mHabocRlUb9MCLm1KLuVHXHdrL8L
5ON36hXLo+b5R7vAvbMk+ESNu4l+QZoHX6QE0S0ZI5LAobXpUU1VUESLSeJiZJ+xYsxXdT1wyBRz
TC10LJJcqQ67U5UdwC15UExEDuCOKoKA3kE2xSVVjyzIUDrKZlFEdAcSQRpbQP38fqNaxT/2JSw7
UN6gWY6CNWhuPJab+pZ+d4AyWEGLpndATthH04p9q55Y8gZJM7ivCQlKPQSjSTUv4u6HytQXSH1L
EjIWvXMtQiRI1bsgnOyzm/Rqb7KRwjcrHF3162VnGD/kTVDFUv6HRla5dNtZDzmPLBf4PiWZ2vLy
W1pRl4Rjv/IORqlHbTuQwbcZgbx8bkKMN5yGs8IyiHJ1tt92Sc4UZBque7/DvFUtvBMuHAuObouB
qSLGE/qr2iu48ot/sSez8623cSdBes6lHzZL0m8uuDrDti6QNeaeRQgqOOTJQS9Rr3LRt7feh0qp
nViijbrTPvUkkseWgUMadF+SmkiR8wpmRHCQbOZdXsxxRsybgqeqXIqBvcvFg6Huh+7oUaEgS/Mn
e3P8Ug9CJyme67MJSi4OIWhSj18dhyogysqfnX5dtTmAjkcTC4yIU5VXZdSMmqkR8wB2S6imR7UW
1jtfJaXR9Mx142afQIokdzn0UYWQTgO3NEqJxqoZG0PminbWwG6JhxnhRlpS7TOrR5a25xz8vFYk
K92l2pRV6cWhkTfU+9nQFfm0KjgRxNObnfW/K8hxF7VL2opc500xFlCjpHnXwIpgzHhbsoWgXA37
wKiFj/yKPcxBX12+VxMgOs8DxPLrGhUZsLnDzF0cTU+QgCkwpMDVTTkRf1aIUqfC0Zc+SsSIC5qZ
DJBv6u9QeFORzXKmxumw8SWI9EnPhiOpPlabMXgVR66JTazGd1a3VQfhaWdDEM9373nP2TXYB3CN
+x4fsUi6tmiPgi84I5CHWEMQLEiWHUMTjd8qR2ND1owxJtALXmzSCcdhuDTegrJYArpcAEZcgKwJ
OsZwneo+vIzy+Y6W3Pr79H/y2zdUKELHlGQZEcooGwba8FNJnPkQTaAiai2XoVVVvuhkN135e3I1
veL1Fnni/HmYh1ytA8g2fVYgs3r7ZyZpqGD7aMxRg5whME3XjBBSbB6iej9VoRxOeaYRpJK680mM
JJeh5TzROV+SIPAF5gvEd6DOjj0+lDec82/W9AXNtHsHZQHPuc0/9f7e5Es+NyNj7vyqBNcSxZ8+
Hg+8XGsUG3hyCoqxbl6/eXd4rRExHhhtDGRZjlZzuEyCPx6adsqbTAZEcvdubsSw4xZLUtgmK8EU
i5XsjvFJ5AzDdggh0DMIBChPjDbES9ehjCJJcZVxQiwjrXywuZjBfeR1ltcdPItDDsYCPYCQ1bbv
0cbwzKsgQa1Tkg6vkUY3ZSBEemyZOz3FpmWxQ5pvd49en9uolIzffoOmXFnpeGggN5uhwq1D+Cbq
0XaiYBtOmCakYJi4/mGFv5UHjUnj1pvU5rrxly9c/EgxAM5LF4tYByshDnVD9U0m9u+LtL/799lS
CkB0ELlHdOohl4kBKiIKXfKzrDWQeGIYhOYd617jNPCn8iqpfNkwYKFrNacR5ngMrgdHRLq7QsU0
mkXx+ktNcTMcxelWVNxl8aeelA/ypxyRStfXyr7sjSoyJKjX+UQajui+ODN9PmoLGW1wEb/S/Kxl
qGXFEfOX7aXST9aV0NScs0LlSYAenxSHJyTHqZO0QVSqj6GuzNw+4973UWXTqMlrGLxAdG+rUit9
nbEMPL2lfQ4OVkXa+or9n7n8eDgM0acJLUP9OUyIZYHWT+3aPsD5Ehfr4t+Y5Wep8BCuc2vGCsNy
bNcPDHk85qjkZHMrvkAjWCNLN9O5x46XACXSkymr9yJRaefhpTUQFvCeVTqo27PHttWT7I7SVyPs
4QKEW/0hVsFZOpnFPR5nVHjzj+rxLRP57fm4Ijpvp3rJz7yNHf8A/vzqKBX0TmouDw57IRKeZos6
U6nQXb8uWG5yBIBUmy3tFOLQBm6gJT99VuxHK3S99eLZfklCuyI+kTieSq1iUffYR6byfEA2KXKm
kphHGbVjSHjySzN5k1d/weJmRpFug+kvnAPgxcjHeKaVFLIBtks14/xshXp1Xwssraei8PdkEVd6
9Pmy8lIrBOx4vD1IdZ/x579wPinmmqQlPnlQSwBpmfV5yJas6k6vrspfKqRZENL40xdJpFnxSdd1
uiav11FtrziuzpmAoEB5DIVl56ElOM5hEXPPjYvUlv0sR2mUpAvKRu332VCfCxbNm06oqmD7BOP7
1x9DipEvCHHXV/kbmV0qjRLcBftLtUBux0UoGPqEfxlg2Txs7nFcOci/RReVKZxn0YuFatBmfv6Y
9AYahekvpCkXNbm8+JWIqlt6+GmqbpdBqzGQPt0yu28cMqj0vAW+UFXPEFmYO+t+cCXcPpCMbVbV
fwHKpUld6hORx84vGzQuIMbvJcwKlEqxMcf4bQ+qkkn3kqqbptVvSeJ1Ipl3fqbaj4ct1oPB9bkD
jGcrqxza8HQDPXeDpNRLxx6nxKkOFmraU2YpW4WhS/PEERVZBuzCcqpKXQ3ZlZ2uHGwim8dKHwV1
+n/RjZOIkYcVoOlhcHx0qTo6xTi6J6g+e2wLSw95mRfvEq1BxNuTB85O9Q+EkRtq0TRU+LoSqSGe
h+AvUbJUft7/M2zeVqYM5vo25Ue1KqH0P6igo+6YUPYuMq47plii1u5061yDJfdaXoa1Sd8uLtX5
bYhdliTozCdxFtu+7GERoMnYaThw5suqcs0QcT66SOm8qO9fnhLNPWoch1JVzELscCIvwTvg74Or
UvLQU+h6ilmHs4LkROIRbTBNLEuzXgTR3LrTNAAaz3tv06cTdHRg1hYPaoAF+OvzBnzXxuwpmDfT
dpJC3hb7RlAcCO8WKYJhuMvmLCqumLusMg6y0KDRhdG/JRcYUtIblFjhNEtqXsElGmn0ZCRC8YPu
CUDGQzTWABcKfSM21+YiK7QApwzIoDPZy2dfJjMAbqukjgp/QfLV1h4oOJJHvU51BhTJ2UIbvVc5
Sw79eQ/5gd1ZNSLMvwChOqXzEnFWIRM2T5z8kWuwAh4ncwPQJpAKSCEycoawQwx/pk3LuN0Ebtrf
8c9HjwVWjUV+aT5tklMH42OOFS+f4rLJE930gDPUN9yaez/z7DCqPKNFSQHVKMedMjpkBkGoEm7Y
zKOCqlfFj+GALcs6SO2NCN9VFUiV7h1oZI88O7PESuXjaL3Y1Cx2k4q55c57tcC+WT0PuWkP/f75
B0oWiFPFG3b1oY95nG2cVfWwgB/rY4zA9HlSa0dMnrp73bULNiPFQCiiFo6bfhjmdqp9GCTFDSUv
Qgwu6aqiYqC6IHNwHXuzk0Ad5UnbvqVZ1DuENbtRA2sr2Ubu5qxtJGR1kWnVsRFp+pK4z9KUjPb6
96+jq2hawBXminz0i4qdG/99/BeMS1Pj/k6KNQnSycMy+ASnF1/GwWWL8I/6CiDD2ng5L3ec0bWo
VPiiiOh8vdSx5UTHdBG3ithW61HHGZtmgzZhF6oXpJNPE5cjN9Fd6lpMGjzYfGE0E8EV/LOm6YyM
j6PxRPom0FoBNYGzkplcQk/3VvnXlYjPgdED7Qutn3Km6uIb29su8ULb8GAey2laLEAZDwUbD1M5
yHvxJ+klboxRtIdYz+tkVjUw0MfWCcuYzGotMsvKDJATc7jE9fJRb5ttDyRB45f+5KOsZTu5DoOy
12B5a947bRJdilSN9drC9qb9hABf9vR28tfgnHPF0AWopkhQac6xDuuGYqxRFc2K5+5TROY/9lL9
j00qIumGrPul/kNWDoZPYgEmm3Abti5klUjKhznWRGobawjBBHIrcMgCv/zrG3JyhpE2Mh8eBkqb
BPzJ1oOcxUiN6HPRUXf+WJD7n4bKRu8hjyMF864ebX55ZWcdIzQvHoxAIQ61grcNvyFxHaIzyUqj
2cYimYZqPAo6hCdyirWf4z13n/durv1uVxgFh+5/kWazWevRD1RDOzJYDWrwptyaM7cS6q22XTVp
jyYqBCq35rlCf0VrY4N3XSc/v7T43t2/n21C3DZuSb3MbCb2U5XdSph8QDVxIbV4xn5kwTyQ2JER
ApD2BcZVYGW/lgROyi14Mm8Q3ufvXbIDUBLabuuIdXT1/b5MMRWpSLX6OW8uHISl+urVDgbVHP40
jf+caJCX3Hn07Wl4QhemVu2uyit87LQ2OmFHyrLgMy+cdHWv8iIYqFrrgizruo3A0jOZuw7qdBH7
Vzyv9pW8uKy0NTH5T57rzHxO88+6Zt5+RgVbVjAZwErgS3d6O7OyuW86NWVgqc0N2PLRHmZh5Nhf
lsz5yqyH67Fx30CCxk6zO61nwB+wBWmAdW66uV7N4GS/W72aR98557W7dp0z3RfsO4G2PzgG3ttk
j7Tg1jLMD/HyfiR8WvRiXPUhlqsvvrzRPo397k8mitOgcGJ5eFLXMbu589amOJMt05kDIFEQUvIl
jEB3dxE1hu3HOiy3LXWmI7a7vuTtsnK1mU9EUfAcryOGKKbMaeR6U6QdjPC+XO4RdhJ/juC2YsjQ
pWoEHLOgveA0z46D0Ju5IHDUfd/KtQPtzi1EnID0meEXhfVdY0rfT2WhwOf/PWcWPSrR39tqGGlY
Cp+ex7FTI8m0ASRwzvQwzJGxpeyW2O9twgFttn62XrxJjWvsHjHQjeFsvbsYumRGiuJATvVTj53d
N4LRssbGNiLJ8JUZdudc5w664V0IUYktB9kcykedzCPPb0SJbbqqVD9Q7wyU0gTzHsAEcQEDQTg4
4HDZm/NsmxPyz7+aM3FJHPCzdQcfEDCFlLfSxUK4qqggmddrmRNwhC2ef6rpH/NnuloY08S5r2cP
toJzP08Bq2iXzuptbNbDP+h7QII6FkHrKvEbGeFFEsEKtjwi1hLnQhHU2lFmeAKEZFpo2Q4ShF6q
g7FqeeLXNs5ZkCNfXTBA53ccv9dXRSxU8CaoqoJ13kmwPszZqV7RKxs32rsNJOqVISx3lZzPhlxG
FxzuOEEyr8cGdIBxe21OHG2T5pCNyWNXNTGNxPFX8O8lfa4jj0JeiN5rUwsis1a7W5r2QJSbPMy6
UTcvYQo8rmOwHlr1y94dFKogN3U4BZbV3fhXitjT3yhD/xF3MM6gjOARFs19GgZVyOXOQqJyF2ja
+rOkguJo81MgePpiEIiwBPWMMBa2PBLx+1PazhhxK4V55QztCqd0ErfgvLvl5HXlCmFdcntRhY18
xBElfErrtBPROdFI3SjXp6/e9/zJpFfQG+FFhpdh6bdiu5l2utxxxgB0BWvdnmmEsUPEjLmN1SvP
anxw4ut4apAE/dtOPPwqmQfqeiyI3tkKxNCSzz2fhM/hUaNoEs/xLIfG54XfVGmQcRmKgpkNLyMQ
xBoBbqNU918A3sgbMmKSQmPQqdfxnqBDJMoke72BKmfdEBU6ku/Cck19OJBzRi/RWeMsoMTPX44/
pSXuh4UG4BOXmxzN939ZwyJv+9hYE6cP8KzkaHC6yLiak38OKWYUkWWmc/YnHWsGYbpTHQpAUZ9t
VCF/vyhNL6HamPQBOlbj7do/T5lWbWw42dUB9HiiWBkNIMfxdBWu5vUF+2uFjaZ0GkUBT7RFgzX2
y5DWNlG0ycJomogXcmG7EP8h+m6kD8EB4pzdn1cLnp8QSEI2rblzi3j8D+aIRI1HSXRmitZYJPHQ
zRiQK7ZL0fob3w/Crr2FHVHZswRo59+3nN83fpX+CaqJMvXsD/hnSR0250g4AAraJ+5upl1qqVRl
A9+UAfyhII32M3RU6gl6SOE4CLtXly809Ru4iGnw4V0XXMBNQTXAQRE4mZ8GXZqexGyPZudjUqZq
VnEKOOrVRlV6oJ0S9xZQfofi7XHo/nZdmrdw6ab4diXkAU/8eIEdNxCDvSVDhpzZ39tZEfaesPVU
mkahrRm4bB4/Nm6s3ijedMe1HU2wOa9DoxxtyCAb6xON/XVJhwwKZFHYaW0HdUgpU+eWjBIQ+QYQ
MaF8D+RU8frutZb3/xNhm1cN5PPoxiBYKAIpjtcSxnKn5HKlp8LYYlu/99htMNHmAs8VlPlErO3H
xethceVqvUbx4iH0k+Zp7lAsBBvOJn8LtZJXCQ2FJlSOhjAmVxoKD6KMsz5v4Cb6WNqlBBUjiXRw
+0LYSyQ2OnPdMlx37AeUTDM3W2UfUUzdqj1PCPRV6XD7OdlbiN/hp+IdVLbHUMu0+oGAO82wcJQB
jJk6cTdvAdiEjmfA27kK02nsAlOsxufLDlasJQF2IOQo6Mp2Z60kfnAnlgFq1LVBgl2rH5yrOZAy
mvNMgQZK4RPelu7IW9la/gni7CTBl03pCajBwPdJ8UjgU+KblJABA0l9J36Qr4tMxgLkYBRyYnUn
iaVKP3eTH/+2hRCBC4ZJmp4ICTnvKuf43rT6tEBKZ4bkDvJWPcRJ00lA7iGLYza91crEFKChBSH6
QrJFEq2ceWuynjv0TRE2hhbJksBqK4CdQJhoCoUzrJ64X/7o6VGWRH5GlPaUEBu2QLdbt2YydG/r
7DgJT4dG+ngmxGaTwn8WS8lKbBGAXy5Li9dhdugiOaqPJT2nlNDRu0L/z8W3Zd3ZZHQaWTHiGUIh
Vfnm1UfCJSkCaQ+cyBpe8cO1qCNOtqKG7ey52RLR3mS4yNr7kJqfriOMntv0hBIXlYhQLMwdgzxT
GCjgw+yaDoVG5qT8/tHtlNDIV6t27+MCDMFcea/wW7us9VEDW1Wm2vURid6PcMdLwybmv0gpGICq
1r+tUGuKQ6R05NPk48TwWsTNW2T2b/Iw0Swa1w9BqcaHPGWnu90KdZYI1L3kw7k8vt2KjzvDKDlT
da/yZqmNikKv5vO9yGJPfcoHPd2L0Al8P9KeUKyROFQuvHdqSwN7d2kDni9umxY5xx+ErFNHWFcM
UGFIzdtu5rkyQKNtFWMe95UjiVEwjr+TD0IjLZwdH2HR9k0KvJcDBqb9P8+3dDCZUStERkkKXAIx
yTiWuliC5QP3FH/dVC9QkX/s1GAYB+IS6VZVEtaQV3OZjJNJ2x1x7XcDPTeNuU4OZQ2YeuNa18eg
Lc7ro6SaYuxkdaE/T0zkXzlMuVm6lERh1kkc4kstZKBIfoL51N4Nvoatj94OAjCgB3T+c34r7dA3
XeNZryjYAYazSdvy3wXz+I1A/FyGZLMwqjXygFpg1LlG3AVJQtibTYVwltx/nSqPwqnA0uKkc9QO
FY+pA1F3IjYfaBklApF/jmi/1NqVvv+B6GONANRt17Cb57kKPevQin4W+HtFwMWJn53B+ph5ioFy
QEB/QWHPw0iX+cnTUyNzQZ/wdKxM3PvGnn38rvme/x/wtqL74vmkYOdsJBmzZa+O9y8MbeG2E30v
+9jts6ruud4qFJ0Lb7VEIB6ZefOt7qSZyB3aiAHpqJx4F13pzGMUwaXJooTGi+dHMH0rq7WW2GnU
2tyYpwkNlK78JWIU3ABtsyMHIJ/eLrMd6FkDr0lBhBHNr0ZMCb30814pa2HBtMgsdElEWZacDh7c
nTGGA4K8qaoND7ZJd6KJptgwvNXeGESaqdZoSJuGB68kgBWY4iQYSIWbMiyTkkGqhtBBpU68CRkm
sKYJC2kEmWWC7JVZL4fBkF1Hzn6KtRHEEBkJpVD4XzsskiFeBhNKH4R66IE73drZu52Z1xIq+Ix4
LfGspCNVT0ulF7YSMaZRKrMCdXx9TWVwRUv1zRfil6seigvfz9+NZ+1u7r1fOJiipk9eekB/6ZK5
iigkIkPcIO5fGL53+r2k4QY/gx8336YlBn5sk9NNxxL8DZ/UwrHjy8HX5ASID/qG4/nccjH63qUY
UoNZiItos1pdcrwUldPD0dMC2VB3ttygqcd9BAywfNFjB4vLtr3B3WmTEPNo5uMJHmsZIEhvv72Y
63eBGjNjC+aU5VPvGHJPMpWi9DTfgUkLHQv4gZ0wQ2ncFeYaahXYZbV38A4pf/n7SjE7NHsaQo/B
tUKwOkOKiyN3YEhzwF2QPbE4QngR2tTfuZ8NBnfouXLr6jZkMFNc3ByOEU8OuVb3BI2VnHT6cyO9
IPEd5ZiL9LAKpG2NTWUmCXupOn+CBEepyzbWc9o5ZT/pT4deYkI2hzfRwlPttj+oo3l9/eh9MUAE
o7ODpombkYx+1AnJgc5AAlIYgUqffCnCftaBumolKH4QBuEnneyVo3vp102T51woa3AaMIbtV2u0
3KwOHH3IlW42lcy3fvBo5RqjX0d2VuNtS1M22S0+RdBXCC1H2eTJXIFa+EOxRPs6NT/hfYEEfk8A
StN7SLJ/3Hbx0M31dqbnfmcJoemVjReFVRo+PFllO5Ba+eoQHvFBHEuCLry8Stx8+riI3e50y9wJ
BfjivWpx1wjdJ72+V1XUlXSA0KhRWm05ex/Yh2aAizrqsNOzVK3hW/jVWvxWWhLQEyp48WxQPYCo
SZfHLf3CaMMor/EPSo0yEbL4k5nRUm9SnH9w76Zqm4L1EXkdil/3pyR4X2eEtUu8s1uTdEyqFdzB
i3i/tJgKgU4up5XALaYqmqPwTmJnndZFCCmSaouyssKjquS02x+5gsyrOu0bLj6ydNSDExB0HnnU
POI1mL8nOkag9KXf7EvEqrFwnicySpCGzjZjNXKNV2Ao4S1d4+BXgB9nS5ObchtigdMFsYWaOqUJ
PYbIqgTObTHVqKk/QFXHfyx/xR3EXwDIUs8+F4Q6cKOJwYCCiTiQkq/h9+zD70YsRvpGJFUgec0c
nVFxry6QHbM6v3bJmBsNCCt3VhPgqNO8wTE7ijVEsEOCkYKunXCaT3XjNI3yd7PiIa0NM8av86le
wx/Sx+89GR1KhGvIgSNjbJACk8tQqFQX6Gz7fCAupOJnfDj1+1GVWXm3rTVZ6WT69ubak9coMNjU
XlabHK0tdOQRU+Cy3Xo0ILSUfBGJwpYyfZDZcTmoBNK5l3WANoGwCc+vyQ+VJgQiuT0u9Ynd+Ztw
lJ+JAsH8rLCsNC2hkVPuo1Bw7Nn/K5eZp8Eboow1S0D7m7cxBltSt8Z2ZsvnolW97svNeZg1fsZD
LixWUVSaFKqjmfomfutOrqbkXYBFpRrsD/c8UGq5s3FWxp2/jwU4DKaaLSqMeQgnsrdirF9Iwtr9
w/6xO0QY/UiNvGjwqQTIXd1jhUCl6A4IVB3EDzWG8PbaPxTANodtsCgAgPSDXHtNebvgr/5/67VY
2sY0Fxi68MbuYPttSU0ehM0KmDGkcSrILUrqWdp/y49NSfD2t4cGmm5VRVeg4yySD85uXKJ/HugV
UjFDeTrSr5Cbg+hcsF/M3TRvYcuW6MmHzPUz+V9dj3V71yHjqSgW7c9zhGJA9Sr36RLHdEqYYhLc
ewl60CdOzx2+TsI7ooPfFE02lkbRCsJYtQw0WqkWdBb2+zkaa6EWlbMPNTyf8RYkIYYNMiS1v8b0
Ol+ZutYaEjQiU0mei/7HompWbK6p+HNh0/NpruYRaUepbHknD/1QYkm9nZtZHDz6voZGIsryQRka
z1ItTDmi2CHDfCX1tdsqBV7vPw34VuJx1E/YEWuzsiavozFMih+w0pdegOkJLm6+u3GvsBxz1V6g
A+QYzJwzi/cqwQrO80UWKTsoLo0sdZHb2P7aqq95kgTvdC9IeT9jMQR72R9aDh9RaLiYDj8oYRkO
X3Tkm1nUl7M8+65i95k1yCMHnb3qZpikChaktLS3QW3WBGJ6gqM1My4GX/Fy9snnpUVtWLnXxIjF
jJ/o5RLaoCP5zOha4etHOOjvTz6Fp7TnnHW1kXBKLnEER/dc8B7JPd57zCDqmHofL373r6VNv1Vt
lgKQ5vZT++YKDrhFT+HACeu1R28j55Vs9OtXUWJffcGL3mUNmMtPvenuTmgb5EeEOy4DBhH0R4fR
LSRdw4+V56OBIFvWaspqKevbqynN0pMwRaoVFtTD6/nkz3XOL8fnHHDhcj9Sg4IhJWwOmwyRWp/U
nimUyTqMS+gfyrTzHZhc3pYuEIgD4GpPmR3jI0YVlpWaLbny1p/oLKS1YrVEJ3ILUYb8f8u0BTRb
A11Eb2NEJhyqH6Ifzo3l7c5r12c3hC3K/9lPLLVQG5K+51ZfhgF6D+ct+7MW/z+VwrlLk09qbR6Z
bJ8Ug9CbL3E4R7S5m1+4UrM/b/l5mbPhN1nuv6rFL6s8ztKJELIMBjuKdmTse+q547cQ7p1QQnhZ
Gb8nYRaIArIVEYqOHxUWPKgmabq4KG7yw8EArzdk20Mxje7zOwWrPjBRUHi7p+UWVbfKM/DhKTxI
jC9/ywV/DuvMZ7GFY0ylKpK4ds3dpEsyL0MpkV4gvMvHrcME1As+XaQo+eML+gwDk+D2rgb/9iPC
gR6RHHL+h4OW8uRUDuGVHXKlWDvInj7dr3ZnDPpsUYoo1scsPb4EaeMXeSvgnrAwYivKzm54b5dp
Kss3zirqI+mAYGtN6I2fFxZ4W1fx+KQv/oGRz/8scfimL6ebAGZi0A2TUxbt+bI4+Guv9LZ9Gwlj
AunXkQ5VSvQjlYJugn7JihUk/sYH+VdcPmvDSq23bRYA8apgYsMc+hCvAl6qU5c8GLAAWwAo815U
RSoVQl9xJKG3GnPUfwN19uhuczSDZIG5fr0ovH6Cc3idOdp1IXGuz0ehgsH+tlYk3B55TLFb4X3h
qv5IG3q2PiYuKewEy0Dp9PeEE5s+rpi/AAc9zF6vssSjH07+xx0uC9S276A4jRJWt277cFq118Xk
VELQGb+4CVyULbZE55Vv2uZRjt2WTaQP/gz6prqWU9PoV3jmOa6N+Mnh/7kQ3c9Ahd8qdwn9fz/a
HD9eftuYgcFqgtres2AEaCdTYA1EiccGuu01ct9q+nfCqRVpe8T+bN3i+dyEbUioZLwG+FxjXf3m
2YnSeROIK6A6nB6hiW+oPu8mVUCsL5FvpwsSSmcMGACkhkmUSa7m7yHnv4r3yrO8hNqC9Qr0OGrd
wiC04LrjO3lXIx9coZi3o9A+Xe8WuyP52MacAcQqrMALC01sgT1QIsSEl3PcIGIdYBXiOoPNZnoq
yLrsrUJOst6aUf6M/6KX/L94QPNqNYwKRfDQ+ExphSLYXlWzN60eGoTHNSiYWehYWeSLNKAenKMM
hJrLC2boMRsfqIbP/sjjxOGoSOy+YTEQ+6/fF9UtG90wy+KBCFd855C0p7qA+8igvG0/6NN4D147
TzN9jIh6TmB7mrGsBLOvpReDl7FAIgNwgeVBMiTFvu9h4V/Z4rQZQa0gpR2IkSB1lpRlG9DyZU1M
rn2NdjoP8sl9S6nKBJpcu1QYucstkNxS1yFuKasYDrr2oGEuQ2Cqf6zJ55vZxfCVOdhygfZSFBAo
z6hq3SNY8/uNhSlLPn0Oy4/o6jAP/qVRbXLRlYbttGUfGRIcq+zpkG0VFjUh3dv/EEVxiCIpFSCX
uxgpkRs2ClzDhfTQ0l5Jr4EtVFaNXCe5Ileynj7Aylt1b6brK7nH3Wc9mrs2ZWOshq++LhCGHlmR
VzSPdF5k2bDABw8ZNsy7zJXwYm+Z1wGaN+C3Bt7eiyVTsKOX4u8qGLSQsgXnGDcmDE3B4QCV6RoF
Dhowztc4Ky8BzUM1KzU7sfaMw36ml9xikmnkhVVhRNlNBKrRd+88VL4GWz+dpMe95y7vRZ4nWiN6
kv3+n3jFb5GXzglGipS/RtGA51Vt5rVUcZngLozrjKTPL0cmgbQCKFXw/wmJpuzUMnzuwTtJq1h6
fZhB9FJmE+hn8+NBs4PMtVKgpjKQe1RxTBDptIpLrB+8KRdvJLluZ8A1C/5qFNifGNkDCd1M4Wkz
ya5Az9IK1vDnOE3USbST+DqZpbQ7BczR1V3itKUyoT2YrpNakSVrYJC4quevaeTocHodhJEIi9aN
oRdhyW9MoCZXDVdrQ3neFOotPiP6aBm40YN/9oc0xAwLLMOkpI7EBnQ3piZOep+oRFMi/RYldxEB
3TIIUp1tGPa2z3/f7ETN54SPaqCMCBp1m3wsD1AO6l/O1Q+fRpoMOZHUmt3cbuZm9wXDkedF1gJK
ROXs8xHcnn92X/5LmGkWccRw86CeUmAjPNW26fml2gA5kHA2uwbuzvcCx+2BVVRLiqpY5vIv9Y8c
rKj2+yBPo7E/+sv5NxhdiahAatIlmPm+2tGRaR3t0BL+XzJ4NuS8m53I9Yfi0ZpJcMu2s8Umykhx
WMK+NNbv59QNQoOjWhIRc7I3cVko3OuyJt05pB4OxVxQ1ikpc1DJsZgKEO3CVNs1rFdEsL3vg1s6
KpCjijqDMA32K5OWe/1DvfwhlGVX7Vq+PuF0BhFzf0bJ+S0bHx4nw4bpcIjN/v3keWt71Bbmz/OR
JeQ9Qtbx3glx+rlEhRyAHzWR1VSI2X5A1Qixq7hfqS91Q+GdJHMAKqUwgi6C5m0GkCkx7lrREQAc
BYn4y7rcUXynj1wN5QWzbe+yhBJ+ks49I57HCZnNSIExqNaStE35RBdXS/0YsZbV5mySBm2mG1bM
4jObjV4mOuDgFMmB8dr/PfXgp43tt7ZWZsTdSOxLRQpFlKrdkpx2Saofy8ezcwQ3QWyyXbZPAjAP
vR2nqMx3HbtwDV0g3nSoEjy7TT6H8oPCkZQ8BjZDDTWHeY+Q5L5sE0K2smiPnyeiiqCL2coRXlct
ZNFLP/nzDzwh1mlzJ15p2sBas/uttC0OGCFsqxsEg3+v8zeY9WYrB8nj+m9klrkdGhVHqxgtabPy
iLlulUMprVFzW8sRZo+X6SzMqHmkOT8590bLWIoRagVzbchwNX7IFvbcprQJNMPUiv2mXdTW70Tx
PkBJ6rZeSEi09LCG4Bd7XqtrVZm6hn8UNl7C4IQpGP9frJZA3uW046fKuJP56KrmMHSZQF9ne25e
W4oWBM1mFphMO9fgh9c5SXpndZ/uOAbcYVM4WSIe+3cOWQOLgz/c5aCN39Uahsaq+zdOCYiRzkgh
4LAsjTYWb/l4DZ1fqya1YTKuc3MwcY7hLUuBzDaQty5BwHN7ZwzcG+QELxIgKA+l7dBiqGfHRmIT
SWkiv+R2fJ0Tm0HcOdYVigTzz2N5unN7BlAymOjG+ZFILimEtJyFeSeZGYvmiMdjAHQPouUG1xYp
mo6hfBaza9gEa3RR4xiMMAp9jlpXrnjcSRNeCACyLj0GJia0rsSFVZAxG/fEuQFTkEVeJliIa/1X
VhmWDilZmXLCcHM2K3OD98VqKhMeI2/nypDDsOD4FkyCWr0TpdQ+cVep2yf1HLZhAQtSz5UdMAkO
SxHkpkMObsPG9AnDbNpRfAoTq15hN66kjqXHh1vXuD1jhlqqTqEqCVs6mwmim6jb5GtgwAkZENJF
CyTODBsW5zP3Ex02qfRUHA0r23lOPKR3gnqUkrQf5IRTz/FWA78X2Y2GBxK2wmCCvEDhI1fgzolx
6yIRgu4JUsgTWckUTSCceRKFX6oBwvDUQyiI1Habhx/a+jKN2IwcUDd+iYyoU+m9HxLq9z4AThqt
4DNL0moU01Wn2SLRzjNCgUFNd9Nh8W7jGR2cWfNRumEOSUDVaJC/2H889qht4ZSVfruVTj3BKkmA
6ET8qMoDcNsJDIZaUlk0+MfiTcDPb+JglPFKCPNKEuXgbujuZAPUFa2+QoA1eWXeSK4XOquNtxKX
qOCedBI+qCiyG5n+JLAmo+mCKlGLL4ksHauzCoJUjFbox9a1kHHY3PvFMZhElk24nCi2CstyneGT
0D/4JyR2fd7nB0uujj9Pvd6UY1p1zaL1Obe6pOS0Y4efxuDRTVXx+7VBYxgNhlG4Z2mYXx7U0Ge9
0jiEYzamlcfRVHLVzbjriAmZUfhVxdw0bTiY67VFXJan5tJ7h/f8CT9jVPo/3MinWFp1ICeIkodK
Ucxq10VV8qgFXEtSq9zLeAjGWy53GEb78GGPsx8+4Z9YToN7JLjMlefcZaV0KLM1ASPQ+GB28K9V
us6jphIkZfL5iIUv4hgo5qiO5ksFKgRd7M2VQrP4Vx3bGOjvWwk/Wtxri2xokDAm3KujC5J/PjKc
dCUcpazCHKegW5DcVUJIeZguaXleLwAbIe2Dm/Rsr+qNVzMeiO5rSXO8PKQSu24YAPvnpAhQFKEd
c2CCDDtpPdIcVUVJQBk8km3gzGKHq6RH1YS9ax4TLFeq62vw+teLUlzViFybM/qkXRhmFMnblxwT
xjYushKjB3fDGKgDSgp34KoN88SPgnZdGDmbgfLw8cD8sFS/5SbAINR+xoWF6xbVA3QPl9qeobDb
O3fnrA4ELM91a/fUIs4aWxmyZ8An18YSR+AwsGZCsajXu96vMwHwEq0qPcbNglkJ+kYhaGmDYSTl
R3lkx31s99EP9tVbb5m3ypbJbI+Zagjb9umKbJorkTH/4fpAGs3qPh2CPmcmcgFAEAW48QT+y8DE
31SgTJNf6XI42hYexAXvSUq70KQiociEoFBR1/15om6yWKPtGKVR/aEtoHMNiOtaSatTr9HGyoTQ
t/Yb09gkbswaoJmtEcbZPyyUfUH0X8GY6h9gMa36jtSzzCx4d70DY6oUCOTsbLZY3XwJK8qhaQ8C
k/Sv9uujYpfGfOuiwl+a5yYUzpnAe40KU4nwIIKqRtCriZiwFRD7b6KdpUzj3NYQx2GZIdso10nY
I/vJUVupq5nhWjBE3W0eQCRkhrCUPBZ4CJbsji0NskGvInD2Rd7DyreUQK+ry/tQnt8Sq2kC7AQX
JmSiKyjXyyU987Ro6C55E6y45Xber2SlI0rKrNk7B/JG45XRagzufl55OlrD1HQSdy2P8kQ95dib
U2oVR8scvJGlf7+GlQNsQvqzvuGbECG+46t0Pvzi8ujzy4IAV3IXLOLrHthnM/gAXwKsRrOKn0kO
gWZzv7sxIB51eodkBeRsU0IFKdpfJbe+rHXY9zjCBO3rGxCviVsOlQhP20R72NYx7EhrF2cUP2PD
ZfO8icyP7z9gIN7kAB8+GiiPTgRQw7wqX9dIVE6ax3Cc6UhJ7uKgzirlTrIVg5h0pwBADkbH6sSZ
9p+WeGRczAlXmJOI395TCAHK4koxfALn2M3e1RqJ0WiGJblUUNQbpZuc1c3pxFs7kH6FzU5WbmZ2
lDCj+We6b4Q24E+T85W2U+zg8c2dtwfC2hsx6IwRhpqGjcuVHxvWHyUFhRwqJT68UsqhR85454xd
pDqxq1AyJGxr2/8PS5bdKmRQA+xV6HxyNHnMA0ZQs4q9AeQ1q9Z/CEtDFegC0z0d22cYMw4lQncv
URUhiGKUzwO9t10+jL98f4152TN/VGZPs9+tHlN6EVqksSuc/wjtNZkpAJivOHVQd1U4q6P5a0Bl
IkL95LSN77wcpQtol3FahE5hEHcpkLwmtuJWI44ie170OfQ8P6Kpoc90lvTG9py1pY41rtAIZLm1
xI4ptWCDkvt9P4Y/y54v2/k0xvdlMFbuKWIGQUGGDw68F78NAgW81+qvqXPg9CHHxEX0c31KOShQ
wONoFqQYkNzREoD+2gU1rH85pMYtV5Ggvk4Yt+9cifxka7iD4jnuTzolu5G4sciLFLuKrFP/zajd
HcRRE86ea56qMZMRzJ2k9hgB8SqT8Ll1tJ3y4EwUCf/Xegxihmqhr4+grBZpXs/Yf1zvYyfE4Z5G
xUD8WfLJER//MPMq0yF3OVkTBhkA3MTfR/TK7WWz3T4D6sJlrX4Vj5/dBxrhe9ycnNc5VrfK8K/y
5HwkRCdo4u0imwvmesygiTJfLfIskwzOmX//tBV2g2rtBNqKHk9CuIsmi22V5PCAB8busQ6Fozq2
jkfQmvbukxML8Xt39QgYJpYxa47X785Iz/wX9hD5hf/+kNOfrHnXmffr+Up2sQHwC7D54zcn6WLW
qYIQ6Q2JJcemYPPPIRECMgNleVv1ISQEhIA6K8u9GZxvqGwzoRSm6EpwC1Q8qsvj6hkYsEAp55jy
hCAYpDcovqXAik+e7TPd0mceXINXJRP72Ppfjh1l9YmiNVOclcWCTQB82nYDnfFC0ZDBrxg72Ov8
rch6CxlNPG7js8U7c5R1oXgCxS6qvrXPg17Qj6E1ICfVpe90jylPcN+FpdJYm2HUySP8d5bYgesg
KKkV1qwupC+WV/qD7imznvwwL6wfSEDB0GzodVp08+CdgoOh++NuHi/3iobuQ1l2Jlv905m26wnv
7TvrioAk6YJaBZrw++2ZzhXl+TbYTd8Up68QJDe8CdSdARBdheiFzD5ZdfsRowTvF5GvlbyYyyFW
9hJfAQBjrrc13lpvMCfEhEnhzCkM+ZhC6ZjHxyaEB8qnv3SGJ180jWFYsBZORO2CLp4hZO7lgAVW
j2rKqSOAPuS4DPhdSvzWCidf9rUf9qPj05AIBmtWvuZIuX6pduuvj0F9cu7ZN9462h6CgYMbLSu+
Oi788EwXwjtchoy42EyTPoe/g/CJV92XoxRWlDToyX/k1HmCS2yK2Gum6zeG/ln6s+TOmgi0e0qO
IkQPGvPqvyH0KqZufVeQLWB33ugRw19SC61p2pn6pVjVN+iDvhpINYgAaunlA0XsE35XdE/91w63
+OfVbOFXsDE2+nB4azfHJbkUqs8HYO+z3t8uNSBXX+mX/fx9LOmWfR3pBzHMRAP1q0QP+D7CSUMw
YhBCNI9sHIAqANYcdn2FzewPv1jU1RKfiv85GNx64768bNj7urg0PwyOkiYgEgMMKPTzZUr971WO
QC7zVvsydXVXZyWSePZMuxTDeVTOldxCc1zftOlUkEmGXss9PRcvz0oJFd0tXS0AYTHL2Zy0eqjo
DEb4C6eHbeq6dX2o6fbSFdTz72u6FhYRZt6fSvNnPVduqHyxOZ2AVjWdXa7AR+y/F065fgeS748H
9cFYEye0Qqw27zpW5BL7I9Mti3i2ya52EqQRrHIbezv2enE+IBSMdektyTcMRHV07wCWF0Ch19Tf
MQ700rhmWVPSrWzwainmUyGnmB/pMLS1iYePRhXBycAYqilZqCnu4kfYNVdxnlShdxeU1/z5f6GA
b/A25BS8w6FUsgACY3TZXnvUXMzo6vNiYhVDp0opOgX6dNNKlXe3oOHrbYS6hkDuZFfouenKnF4A
h2VKXa69l9d7931pBPsw4pyPCiqP9PSV/yBuEgznTccfKOHjWiCuOClj29o8Lfs+62MsbuUiNa28
MPxEIL2oN5iQiglzRmXpkb97YHrafndOgl1fnEyDrg9vNe2YujnmmyONnjWyzhY5JJ/PLzlAZKJv
A9/wTMRea57NpyxHOsu9iAdnRGPAX/xBFRegUUOY8487tjB+wmET7mw8vHNWPup9h0xkiK7/r1uw
5wBPQ/g+/0skhhCBCeF8SEhIv4Kqv54zN+HPvBq/7rOfs+CW7wd7eI9AEDuLwEOlFhLQvXn6z2+S
0Ij4jD2k3X/oANV0RedZoPLor3WdbPVEJQMvucaIEWi3Q6DKKxDWpHxgNUE78/BIK0Sc3TxLyrZM
UUA5SKGvJJ41DbYJ4fDtqI0HIDgTPbj0CRgbWqRWY/omGdES+aWp90kspaMR8vnTf/X3Y027qBbN
mhEtPTpYOnn6nVwEau6eicycn3EdXBQxkHl7CS/lveUJAWMNi7fn3d6mRqlRdst1k3NpkZoEJjzX
xHSFipxRFnps4v0ePE/TxUDdXRB9ZvWLqyQEaKekemE3iLCjctvp0sCPu/+Jw09zA2k8/nNshv6h
8FF4tsAivvijhocxan0Crr8j5InoPp0DtNCaBMhfAFUU545ifEcgI94KkSvMMBELViWvmjaajK8Q
OwQFau/qLIlWMnQXs6t76aal66zC2o7xqPv+06cVBIifEnOiTjbhYS+sOtoPAbrOVGMns5GRo9wG
js7V0w6MXNme/Kk2zB8mQ8GVxei1kBylH3OVVwP4Xe/JC7s5C9L5iA17YM9cu4x6gmeC5EZ5Mn8i
/ZYd8mdRXaFKdHKIkt0gNHsIFROtcstepjonJ9uPY6S6JP5YCHpw9pU586OJUIy7WO0eDy8NbDew
FQ1Rq5QM3okVbDFrxTeYcxDGoanV6oI8nuGxFJjqBB+ysHXyl4MoLkv8WFCZYtFznb8w3Wr696+j
/2nDVjRIuRaGRVFKln75/OJ9V6SOJN9w4bYdb2hklugyT4GmR7AkJTgZhAZuqnYW4oPfH6jKU01h
XwSwRkeZFyF4cqQObwwehcLCMHeBgC5AqZwRFl5RFoP6lMEzTEpC0ZzgxSnDgjCmNhcGr4S8rU42
asm7NlfGJuVuLg9FFZu3+5gBm13qD7yABfaDPXMdgv3wNYGSE0AMbtI0etqypMiviHv5tT6usq+i
91R6dhAf1oM1TOsPH9L8mKumnLHl0Ma7GWnq3Mqfamr6DZYTEKn9v0Zo4n9ZUh/HoJKhclgvwW3h
tQW+L7GZ6np2LUka99v/6TVVE0yX6fFjHA8aYX49OqqQvdxkF6IAdJ10b5t56FWWFVMDdWjYXJIe
aWwxhxu0zQt+c3d/jCeu0M+uWfez4AUGj8zZfqWV7VFAfxIuUVTC1m/uUcb6OKnALAYpPj1VS73N
m+ajBmr0uv0I3AUC4ZNzozi2lprOiBCaTNj0IZlFj2LAF37a44aktYSmL+qybabFi628P3+Pyc+B
lAbAVKvbN0XIy0XEIXm5+2UX4ItagK2STNIIy8b/BnryVRL5ZF289AlY2ShIO8S24I4sjWhR6/iW
ToI/3EBeb3Tt5Kn2la/oBFfRR/z+lAeD8jwBh0Qi/UjQj8IsJStXq0RtO8dQmHYKF3yu6BjYkmrE
LKGkJK/KogH5vNIK8eDKtPG7s9pZKv7N7KY0t2BilDsTGD9bKRLgLakT+PdCMOuxJd5VS4wrAMo2
FMxUz+3m9ZDZIqZb3H355+mfeLjXRXi/L/0cm3zW+ecfm66kqo2lQmEFa5CdZTiA1MCV662jaQ3c
oId+dtWDOJMrd6ZBtsej1xGwfrZdHm3TRwYAW/TzPrvGAeKs5Jsu/9tPyH1ZzwztPZcksglM6v3S
92QuLIoUyq5TZw5K62o3nI1Jc5JgjXzl8JYhtsdbM1201v/mliNyL3DH3uWFuPvQH38QgN7IHrVw
ZYTvp+jWVH2ykDMl0Mxa8NCODvAoKi9nWY7m28x85Ye0t5LvnRD1pymCdkGmswtcP4FPfe3GYCHa
GHsPBJD3vx26MuqyTdFDLHZ/Q0yw1196sEKLkpMvtugA7VNMa9KUJxIoqLgwrCNIzd7Nme4pjilj
XFWqZxa3EAWyEh5N3gIEF//6s0Zl2ncAavd1YWzy0Dq+RlPXJ16FP3ENkDh5JXWntfzAoRdbM6v6
ayd3U0OgxE9adKnRw8PoSoun0jhRwpUayUY0yxQNeypSIG/2ZauLJXE7nhXwK+Lo8ABngEA4Ktzw
v7Fj16UHq1KTMf5R5SQlNBAKosdp3B4XWmJjjSi9V71TmVXSla0Qum9G3wNMchGiBv/7mtoJmwyn
GYEnoFF84G8yY5Qq56uG5CZeeyRTZ8zCMtJ18atBqWEDG0FbLxsS01fZ5jHM4mrncVDobYhcc3M9
oTQJxJcHk6lp8oPqfZu3Lyk7hShMIqoM5FdfLnjOJUe25LF8lmCYim814R255LQYgdIb6Y7ancEL
is1S3VDTvsZoXNtL2E2S3ZCwvWekfVMVNI1HfouMLBo2vQ610jeJUq8RQ6dZBkHHOpb0KjkqCm97
MhUubQkvNVfp+of0APHf+4888jAyTFrDOHOTof1JokSwfhEKGMyu2nIZR3BVImJAD3uq78Fa8TUn
owZWl25qy88aE3GOtUexLMVv0zsVjUHE5IEJL7/EiYjIBlaxEyoJuxtMizveJq6Cnlr1Tw/anOH3
btbBvWqbSFlWv1VZKvnUx95B1frbN37IW7Le3KWB81Wemo7gm0omI7A3ZaQ4oh3mMsytV7lCYfhW
xblBxsuNp2ImeiBCuuBmSKXxnWw93jGUCbrkSXstB/rV8xBC5tJaP5jteQDSgt2fgIfHEoe0M3uZ
XmMy6qwweoYufzpAQ96GSK6AdckKaVKa13kWis+IQ/uZQyxtvKbo+g+CoRBqdNlaksYwsdxN7dB/
plnr+MxCi+KMonz9RF+Lf3KsIuyfzkItQSmlOEYWcPTXPxCy05VmftjrxF8NCt8Oq9bIPvTHSKQ/
eoFvnxi0N8mdUI9HoI2V7QGCI7vlkSNNIYuxTbTjFMmUI7Dv81RhNfrMw5OqMsbrQwcJxxj3wvba
h09th0pwYdkH5WlJonHJuRDGcfZtVkFO9tcBcktRGtVyHRqPKW3WPOhlJ1CRxT1q3rm7nTuHdaoX
JS3SZn+f9LusJGZDFrs0vUkwYu03wlvWGu4Lr5L79L/o6X5kRfqYFAZvyz0XxWQ1kq6NSLndu7D4
Uwg9IrpKT9QfYsuyhGiyV9PtOAJNGcM9stxR+ksXcyL3SPGKSRl4/XsXUFWui4SUMm1NnPkEfmF2
mDT9U54uhlXtb8cqLB6ZwBLfgdgT7PPFNlxKvEs5CL6SwqLxuUNn5QkUgtwjLghZi8TwbE3TWX4B
yfSAsI95TtQh6m0kh/LlHxCqOO4GclfJcpvqY33il5VgQkP7BLkYD2wTHK8RZkqXUq8nrCCTKlBK
L+e1bPyerXJ4H87S4mCtuUkbtEJOT2gY4LFg8CBK8FR/bk6gWWC5na5obQ4te+9eQhbqoiBs07rS
iu8RkQKgc3cdknhM7hgZmOPoFgOvEv/FmQHpMbU3yfEmJyJC3mGsFTapvqFOTZx1nhPsZe2/oxOz
1M2D49Fs7UncbHZ6e/0o0gK946eMVsGYbOoB3/jLKLFf0D2rhlsfeRbiBR396WlR9QXHV7z+og22
wLB0thgMpS0TMvermjBmkPUPl3n3Q8868avqZxyA5uJRvPAASHvXty4IedETyOtMs7JrtoQc6jFm
2//LfKacx/IuxFwAk01NFbrpCakSjJ327TRGKxXhpfvntTVC6MaCGg7s9DOKpusxorl+LDB1jLdy
mdLb2JFIULscvpy3iCLyOXcFfA9q+wgtxEzGwPJlBmFT5buocW4DO9Jq16ugtduAXqc1hExZLxth
LdvnrkIOHMX80VWka3+fNclFj+HBeH6nsa1Lxkjzw946N6KTIrzWFMhjezNrpPaAsd4uhSt/Do5v
6Xzcr7IdPtsn3sS04cvcRQ/2s7db3zFV6yv3jizVcLCiyLSKFb2wrMjvnS2WguhRjn3KMGrOzgjb
Oajtu1nISPL6Kd2bGUjPoQS/rG/HJDtXVWJm1er89Vu5Pss8MoZQoojZuuqkUlCEhJ/DDQbOxkJ3
Ggfl9rS++kVqLX6YQGbVTSxayDOxW9x7uuAFjZYurUcCtAxHk5fHUd5pXLXB6CynvNdFI20KTLZ3
eHIFRyoTT92uJ+APkMQeroomwYcFDkxlgkHmbordW1RPkre1rwlJbHrWXJ7KDfNIvfKAqVF9s1n8
38RbocQcUcDSiHpnwuMUCbQwe4Aic/TWKDjeEidYZCBuX9u5RcKnuOhwjuUALmk0NtzrxOSQBkDx
Tx9OzYhGGOYsxoOLzaM4B64D7HZ0yFan6QvHZQgO52PQqWjubcnw9NQNKRxcPB/qr2CuUY4Np6g6
QghAVZL5c0xIh+DASQ81xGHcYYO+xFxsbDdJNRrtAWifyLyx3WLHJm1xSxajTQRIH7eXkeklk8N6
2j88OUvFe0WgEMUMCAgS14w4n2zybnWnRA0Y0615RLenrQmiVU3icpTtEPNZ9/x/TiWlzej58Go3
H80HJw50YzvhUaIx8EjgdQtN6CarZ01EGxdN+PKMABW6WXU44FmAJJPcYMlAMT7CjAv3QNHTL9T1
rnoIu6FjdqHvfVGvtphzVjcncBfqyhe1uPaBV+E1M8cUI3e9QqmaRMbg+yeH9u+qqKhEOtqtUCOR
LkoP8AV2/cXyrPlaT5XVaiE1JrjED+t7wLjtixTtPKeCZaDsBpUEHGgDcQig4yNAaXtWimGECJal
JbXLyDsajDcQkHAq1LlVFlJhFXGkcOIWgoU7fUIvtec2S5/dqrCkhc2Kq2NNVtFGyN4x/xstugGg
1kiFaOb91c2aximvRO1bePnejRcf2AR2OMbqI17ynv+MjteTWTQds71AwTjo9gnDa6RKtadafMjk
jtHgEKS9XCl+s05E1UpzFTKROXnKqaDCrO0cb1MT0qITNyvH18Z4Cvfs4lvY93AE09NSB8a4YqHQ
knRgsgQxH8Eeb92E0ivqEBUHm3crV0Ih7hqXOdvd/K3WhNre2aEeQqc9beXyK+UL8s8VOjfT74Gm
mxWqdu4TJbTCj6Qu2KAtVzoGVcZIE2R65QCpJHz5zBQvL5rdxwRqPH3pcgO3nQJj7S1xLn0AB4Mq
ppJgH2XUoIT1QTJr2Qvx+Syp8p47KRLWPRkJ7vKKIj6rb1nm0foUY3OBrsgOlM8qzWr3oBXAC73u
gEYY4a4ZH6kakTbn04TmgP3bID+RiUjFTHo7ti5m7E7btSqury0Y056QgnGbJfzo3O4MDwm73f2u
4o6zGq+ESmk1z9YstONZKsonCixcQoIQdz7AGX3EGfasLzM33kOxhdasoPozwL7L9xTBK20Ct3dj
I9QvngBJusMf2ZV8J8o8BGUZLgol7ylzKm1icaA55KCb3LdXapQCyoTJs5hYTVRf0QVZSLsIHieV
iqkJUpjFJ4cfWh3GxiSxFz3D1CK32d0OCWia/vLobNMfZw28cG2nJoYLm3Q1OkrTVIqzkrC0yMUs
W+ZpUy7rgYwBB9pza+wSNkQh0gfg1F0IX9zdRvAr1bZ9IXeN+MmjJJTVVxDx+tbbA9/ZeU0jYmTM
DZstOiwUUv3PJruQb8uLyfYP8UL/e+RiGsFBs6K0Wi8HpE6VSM52TcnGje534PjzBVhvYKZzvidl
FGIArU+gXPzsbm3hYC2VeFZRrlWAKHVialDyksqfdg1VggPm700VOaHDGo1TN96ssIGCyOMTpteB
GlA8huY5aP/o6/hpF6bI4CqTKtBLIzms0Eaw/robm/7zvuh7YE4TU8comcxuqHjpXyWFXy87SViL
xiwfYGqFPAUWurrSFpa8/cGLdEtaVewIK9J9a6pU1VNfOnaYH6SHBidja3INJ3QW0aPs2VdMgNPk
XxYJUoqV24EZ1NsJRsRv2ITECd3tCG/YgJ2ce/uilKywLj0FDGduQ2d+k0AsEqN734tfUyzdu+yH
WUtxG3gu42rk+Wv4t5zWpfsxEJRIsVLZYKUvGJC2RgTKXbhCEJ9gE9Kn1OUlGZo95cl66MDk3bhz
NaJukrJzOPZL8yhGQNZnMQkhdeKVrleaNdq3nRebA6sPKTwCftqCwCibYjalf7xr8Vc2s+Xo5who
00RZUi45LrW3jpmPBlhNoAxHr3BwmvYYaRHdnwGZVWCufh78eda3IyYN5q2H65tRoQIY28ZoWmxz
Th17PGMS3mdOro6bAiMmdXTXdeL+vnDTZXiI0pxq0ywtS0xbEMh8N7Gi6ylQNwRpXPBIt9O/LCek
le++PeCG5EktTJMeLFdRB0pwfAGmIFy5cLgXE4MsHvo8rOyFtBfxSg1tWGLZE+BYy3XBD9vGX2qb
48EKbsLi4WPfugppR+J7lrt070wastWyykZy+tAMrFc5Y8N4mN6cd7mhA1GvhS/lOfgJnhSntoMV
9r1oRPug28FHjAvlpOt/Q29TsVM2d648fW626eUc0A6479nkQr2zIsKrTY9AjSXO2kCnNqV1N999
Q57q2Y0OFut9w5YzlZMFAS306EaJgFWmDSU7lq6WHeKT04XXfAm5QENSFOocSZ6ogHEwDAZmOZ4q
3ufBJcxX45ZduUS6tJFhJYkvQbYGXpYF38KxVhnwVY/Sz1OpMfrL4w+0lI/6oCXuAzSa0HMVw+t0
wGxC6Grk1nIH8tHrMlA41OQeIsAOCKI6hcDt6DbRlm57yQNTcf+c2baRSwnsr2InbpQ0nHoLTxsr
zqFmWDj/QjOru6QWnqaOvLHJpbmLh9P65BxVL52Kg6u/MU9ZuPsnM7jMejay2q0kuZ+th+2RzyJc
OW2T/GYoZdlYZjAG/NvLWUdBraRVs3t4ErLxDFoVSQkAD8dJ+HRSPrQwmtYHpllB/42m/oVhYmos
DbCyx3vH3cX0+zI0vpGAH4Zo5NKrLtuG4w//dbUNFCVWLt3H2mtWdHW5ygGudIz6T0nwqFPj6ZBk
fojgF0OjrXVuCA1wnhoK7MC8QbG0Afdfi5imwyKnXuZ7BnZ5BPcj88JFlcHM/wRVIIZ7CR4eqna5
crJqZVj2GOgMfx+nq7gMPM12U0VyfjGaLs3FKyle62+F5s8wNpopTrgoj1wFqr+ZwxVEmL6Mxwd/
LkmusnbZr7WhvGGuHWXpUmD27/awDBzVyvtkccVZ5VDFl1Tslk2j89YvyxZOZkFPxq5sk83sxlXk
ov0JqanH14Nr+y+snIzBQ3kVrl4RcfSgj9wjS6WJucRRaXw2/aax8/UhV5Pu4vqitzJevGChi69f
pBEJ2q6+rxQvZfSf20XA6DfoD48/m4V3ofTuT9UqHykiGMBmLPxkyVsyeeuosrmw2Zkd1GrORvlp
4S2x+0IHfzBp28Ykd7I8b6vjLp1MkLLGuPLJ5IYL8C5/S4rAyXsuTRfnUkMQ0GPnPS5O/EyK2hci
qZ1JlIJww7ePu9aA32fznjZMWZHSAV2NbTrHqijeUz7kMpV6Xtqz2ZCWsqv/qKf7tZRNdAOMb/58
JIncMUCfKJrGNyh00xs3y/TY4uiuedjkW4ylNArTBM6OmwZBYDWqVV1qhjR02+82DHk+LOHAZrSe
wpIXxCvN7o/gGKT0zTmlfLOL11u3jZNMP8fBkzWlbMHwspfnwJ2zqb9t71xSNiVHTLpMcEKMODbJ
LcvW7CO0tDpzTooRPHl4REDILA46OuuJAORPsrHxb7mH5uPShllVcQNyPyvZRVQFbfOhNdoZ7L0Q
9QvrWSrhFdG6iYMgSL3n/EVjjoaeoa2XMPDf3ST+1BSiDsUjFUOlC4M1jBsJHo56fQ4kqE7Wubf+
TaguNyLF3dvnmClE5X7Prb+tBhgSctmFYndul++uMZSoXSZZQ5hjeBOuUKhWGses/ikMpWSE6Sq8
94GMHHVUJXngWohLXO6z+UDOIM6D6SLMaiuhPtvRCWdz7Iq84mfYSonBejK4FEbpwVRglYJ1dsVg
KundW3wa0RV8tr5GOpgoMmgY52kUN/+cX050tM6JT09UcmA5adLlUaXNlxrb6VIZ3SWwpBs/kgyz
3Oa2OC9bgWDYVcKdIR2XL0HJQfv/UWZSEge+trNk59dzslrdVVqD8Jv32GD3HXKuKRH1Ly1Qo59z
kJNAyMl6fyT4PDwR067ctq5Vv/PvNgTunIFadz2gYvUQyBEc3K7xpaYRoszK19gAZt5tyBTDQ9yZ
t5UuiK77eaD+6X08oCrD37DbdtF8RaKjEZ6zf0Py1Ps7k4eQAuaf7yWK++Vb3Bos4j70PUyU2gZE
hbtwzXujeLyT1vlP5Wt/s7Pq+5ZKaR9Lbv2MUpUkClsTjUr/J9/tMyYl6flV1wkeb8kPBTMPMFEu
oFwfCA+lwxMke0mjzEvEpHDSWBGzdvYRTLP1L42p9l4jLQapJyOUf9iLfccJdYBzkTn7wqQuL8XE
l2Cxdsx6vd2V6Fvye8dsBI4En7WKPcKQDxIh9cw2XAqxrZbiOhLXdlLD2emT1RwqrBHsq/GC+NQ2
TZUeGT/zCkTlpDKJ7PuQtr2/kzmNZxKiR5pTszHGZAvsHK43V3Mdv2V9PKAxqg8x0YBYfdDgAsbc
EZvJowZc6D/lM1XQuu8VM41cx+0Gjz1He9yT3PhI9XWRJoMlR9BH8YvExcTxbx3udS1ETj6kLWPO
AFcMthZafr8BAD+83j3U6Iego540tGOCFn2u/OyEXiZwc5HE2pyF94HtGSDQiSctA/wblhAYK4s0
53YmdKiCaDB3xEs7QgPlx24u4iUNqjIsvhQgQf2qsOAVSjjR4kpvFXyiJVhAZcw3yH8xZKJI3fng
gGYI5b1HNJCt1gErtUz7TXcLCACn58DpNPvDDwU2JMcEHrga0gcLeI9nzu+L0o3PjwkQjZmP403/
R+rB8IVLLUWCVvAa16VPJOH2rhfpwS5V9mO0Yv5Y2er5GcH23uyflDl6A4U8Fh2L71vGXktyQjSp
nmLzBL0citpx+iCmeZxXlE6J0/rDiogXyaY3n32+P0OengrY+u7oineUx4SqEhDg6rOnkUGT+0mc
SosYZs3gtMYjewh2PuXH+5IBiVrL7dZ3Neh9lF3T0hWQBovdONqE4uipGiE3JeC5q7BgnJQqcOtr
LI25CpwvRaRDncougFAXq0ren7mc5ZJNzB7NtIt6Ehlrf2K0tjFYfFVNUDlQgIIutD07wneF2QJ0
LKCcQfFbXLm74HW1HiyG4tCn19R26/L37UoFiKqlnuWrZgXM/IMDFJulf7qmiT7dMaU8489s1qQN
rWewfTtrMNvA76ob0ruzk/23XDMiddLKPoWSfnidALD+KGd1z5Wzc0ux9E5Zy23cZylMhowOEGWK
6zh3ONVT+ozYy6sIdeA6hg4/QGyPyFT6mP7ZxkX8vS2Mn7WKx4nQ0hZspVC6YitRsERnmuRtjkXD
g3BPWKPWyqqTTSlxshji4mN9GwNLJy0EZONchEN2gq8WoCzgDQA6PDSgjDwsUBVVuwCsSh8RBYfa
CLKywyCC5Q9ipXpQmf0rP9iNlZeHRwWBtmvUalewzQPARjrZ01aKlHELUNsV8JNa9nKL+2wYeuxE
zPNUt2NOoPWeOuvlq+0js35DHES0s3ltRt9OTHcF7Gruh/63nzZVn/bUGEKZ/NcObfXJAzCUB98F
eK+c/TViwz0bhMePPejI9sfMH457YpSDGTvKlLsvmYhINeD0Hnr1yL9Ouet2A8LFCRwL0AWAByPO
4M4tjPYHWFYmNnaXSoJo32Ejn0DpEMYXHE4+3MIyNytAyUh/ZnmGBTG1VDNVtDA93q5xGW0sDZc+
gvlKDNHr4dBVEp6xsYQiOhH4reUOsao+Y9FPxBwJQAA6KfO4f/stybMO56RbnEHOm+kxbOCj4Qzn
xvQNd/RNTmR/um5gnw1GIQ0VYUsGmELk6x93B28ieQp3g+hNUtDz2Vu/NDA4/jqU8Y4RgOJgcOdJ
mPfwDmkWFfsJ0z6gIHmhVmfJQeIAalovckxvV9jY8gbt16C0hqKJuv1UynIHVSqmH8rWOVKx0oPT
iBTzC66elVwYvhQxYbu5Dt4Zah4KWDcCfzNHeYAXEhOXH2ohUo/8KIMllS4AtVmRBeHtbPcY1ugt
DFc/CDlfB5F5IQJIFnkVhfggnktmqFT2tJRyLmJUs8lDxg0dnFXoNB+k/1FGyBBS6Ha5C/q2QOSv
WgepisVsb7Bvhb5oW62CSaYyYo9a/SFCcvsXaMWobDyI9YaZfMlEs4OVWBhMSQMkxgCM/LlV9Mxj
k82WDI/vz36XHunorORJ880rUvMxZp64XvrNtOEa02+7ct2FkNzbFSEDEyVDQ/EzXzC/KA8JFssl
8A1S77hWbZHw5LPNGBHBAQByK4OCMZuRghjAg37C4fGNV674ZMldBY5JMIcF92+jgbFLYPrcLeTp
482tDy/zU3X3Lp0i8P8BppIn/rfloLjeeH8XtMGfpNDhF5b78SclrWCgGuEuKcU41m0osWWnXVFG
dnQSlAysC8KIODKl87TL/eNW7twd39JFzKuqQcDkIeVy7HjV4pP2wV/0x59YCccAiD6DOp8ZGsUf
Go4wTefcte0qm0v08rVYObJ+dLBfDtwZlPhUTvwrm7l1WoOX1OG+q0VuNLo6PF3KYx5X8prgBlNp
HZUhy5/vj5vKxufEdiUAPXldUWtNAwpdgwoMM0dMeAc0ZVgKLwscNYxHYgpPAahXhuTIme59NfY2
s4ktLA7E2UY+rypEXA+qNFmEiRe2lh4jDSt/H5N+VLp1NQD/+1SziqmTX2DKXO84XJTRa1UUMQTE
BGyd1f/FjFePoR3y/rD+IBsuzsQfq7cgWHpStOjs7X/xLOh0HfHGaTiTElY08EhzuQzhDiBx7fOw
QfT4JJmyRMMq1sWHQB5fYOAV9Tkhbo9ECtGYAHBSy86iLKOIIyD2rji5gxGht1etwkPmxyenTYCz
Xmq6HSc35+KUg9vJTY4tzDz0KchPrAlBzII1zLxAatDkdpGRJPmziYZCtXelcchuTH/1YuTThoJ7
f0ZdD1ox1jMXJFFYZFIQFYyHZz8hsLvcdeI7D0QANYRmRT89K3N3KOAP8Jd7Y96RTXjiO+PApl38
RxIn8V5M4+wfc+a4MkbwBEsuqXqTtH2jVvQTOYBTa6oYf4cshW0/mMkppFXndHW2X74Q2Dc2OljZ
gyLQ31M1p5dSkbTvmi+Rr1SQ42oaSRFQ8qDzzlQ97+gQP1/q141X17jvR4VdkZwo9g23xKgQlvM0
3AGJB9r5kXGzXqOHqco0//NS6T4ZtlSBQ8vUzhTcd8AM3dBkn23eQS+7hSlW14p/h5uYAlpGA13j
q7O+04S6Myp+mbmJoG2SDjQ/zUHjFfahgKHCaQdU6LYzZ8/7UD7eRnJCMVCy4vL1BaJHW5ONTlv4
uBXjW/mYtcEC1kcu1QRXiMaSIOMW7H0C94hBcbexUwLLjz2ZNFIlKHD8iMK/ad5EJ/TXb6kbrId1
pOEY/2JCcWJsLBMxZhv6VcFui7YJ0F9zKGNb23L2JFI2Z0fTkgqs/UOGTQlZzx07Cc4pw4ZHg+4x
krw0EYgD+P6qE8VGoGkh9HTGW6oplcRrwtrtSpctPU9cy8TAOe8Zf9XLkfgyELOWNBviANFkFKj1
zVSb8HHUOSdMlVHdSyBR33SEvb90CSFVTQWgfVIwdH+NtAx2rp0ri8w9Nq07lCDkZz5+CMCJlYfZ
6jTQbeu/uWGKZvH/BaNLF0viSZSGWIAHgMaUA/LVK+//cJlmU674vMGAmBCC0qO6AEIP9Ouaq8+j
u3rwUxlBF7HSXAtxoO6fwWXm4vm7d9X7V4vyv5TejMU4X+kDxlo4jMQrjvUEgRfeEH41DPQfKuoU
XHEbEzJSqb3MwPly1m8QT6xHOsfd6MYiTJU6qxyQlbz2rk4RH/Zp5s+pFq8e3k27KiaddXtbs0Jh
ny5ymV7LV6znxPlh/8XrgYa7samye6vRgFHK3rlXRq9FirxvKyz53BaA3WQmy4VR2ijnw46DawgJ
Wc4zPg6BFdX/L0OeCudvWsItz6WngnhFvYx6aCFxxL78trzIeMhbxJsB19UujB1bXKgaxcx5EZh3
wW8DuEhloPSLiN1ovvYeX+mC/Z+ZlZXrWDLFcV7Q9aB8X0TFcJAPJvdHNxO1v4cnqWpjqKL0AFzD
zhjDdFXNdOX61qLUJX8qCfHfKZraDlgqNXHQCMFNElA8+RzrA2dwJUR2gffd5xvrhha2/AwssbK+
FWyxeA9K4kdyJoP/AXJbczOIKMRq/IgHpt0PIIdQYXwLisJ+ZvN7FNdAh3G1xQ2nl/8snhm6gw1O
k4cgsj30cj/D6Lbg+OzM7ocJGDnT1Qo0sYErs+c/KW5GPXRLycskB6xnAoIFq1JLLvXN1AVhsUhl
DJEvt0eWCwvVtRQ5OFcarNIO+OBaO23SqyKWKeBhqcWmTAaPMpzE2PBldrl6VzXl8G8UUtdEKaNg
C5DzRGgSQbnZR+zmG+/iVVtOsW9or6rWetSzyanp2gEG39MgGmtOKuhPsMKVEC2b6iiva+6BAm1z
ijb6MVLhsTEHU+U5A+kkXlh7tgF4qsWR8S5jIuTRxsm47QFdFBccR/isNkJiilRGmZw4N/iX3Urs
hzgvS6twm0cF+WGsoebwfb6j0gQIYZxluHZZQKtPb8ulROsGFLVLSrl8VnYZSHSaRnFag3gzVg7m
Mm1N2i49m8+rJ+wU53r+GS7bFVlbthgMe4QWhjuOl2b3rMSxUB3211K9cyLC4lKr1V7njLqSnGLS
95RI0YnxVJnKfb8c/l23xDtvvnIuQ/NrwtzPrYGq7F5zedIiUbF/9rAmeR5uCSccKtYGzHukW9F6
RUSICthZ6p3SeQzfMsxcu5s2BQfZlPpX+2b98lsgZG305dv9MTEyZgv3tdpxpsR5C6fj5P3eO2Gg
eprpbQe3GFMRKfxhoJBFj525EUCXPqIUV029/p2xC8ZAodQA3pol5Qx7VQNpsbOLCWZ4VPECGuZb
LnnKS4TKaxkazcxhlHwpsUNrXFhbnQ+iMxR2hp3b+poeFUUciCjeJer2WyXYFPf6EAIMa7KXAwyN
3y3kNgu1jnxHE2wNUVX9D/CTlZjJKDLoL9jcH7T4eSSoVZYzWd10ki5gXbzYVLutAbjj6YijzVhS
flQI/083/izwu/mDHVKALIggPl99cyxdg/EmWP7y+PFdo+d5EIgIwQFPFfcUILb4CeeOELjyENaM
SUHAdYCt81FCad874yBdH0GG+OJbx/ClcEhfD4+ZKvnGfoHeSvKO0PUqEU5DheipXz23RQIZZz9C
BRIH+i0LPAFuu4h5IZaCBzWxL5S6Jz2k3ndzXmIu4USenPGbKmQ14QafdQqMZYPdScOfO09+YODY
DOAYpJN8p88r9P2ZW4zOhrHw0WS8mmfYpJQvJZVqy/FPzpDpYP6EifgvG4raLEvwCSql94+pFi4A
11ZWAOL2dfInu8ROS59jutFXNDoguYZNiY9gP4iQSt0R8b+Unok0+eyWp8x4DUGSAXROwku8embZ
7clF6sOUZ51SAA0yDB2Bj7BO7ZMBU4GEIs5dFgfsgfYUO+RmSvKxHx3LurT0v2CSQ0GQ6Y/26iYT
KlAkafSyTDAC4G0xX0ekxrAZmx2wDVrFRuu1TRy4S5JHz7QuReP6r74UHpXh5W9ZVDW75Sd0b9tp
/7CgsdoaNnYogv4xmbPUKBSgQj0xT6eF2DfOTejm7J2qR085aXPr8uafAvF6hiIBLSbwZpEwzSS7
UHBQG1cl1Zz659U+fMS/kbq2pFUL+iZulafjfxVNjVu1q8Cw1h1dqzpoIkdNJ+qlaDW9Q4GB17XR
kz9eXJ6fogV84GOhBWhw7nCbhI9pAdcVukq3X+e77LhbxHRjdC3vs4wVbe1Pl2M+35sccXENUaHX
w3MtQ+8z6/TlY0RWObw45BgpiSH5xWuY9VirGjP1aoSUNajuGiPd3zuaHkwb7ud8LNyITz49t1M4
M0QO2JoajemH/WaieCFjmnv5yKBTdGie+jkCKqg3wsQSGd1H7tL9yeq/mET428mGha3xZbK6SS2y
/W07hT/0iaDavW4bo6LZ6AuOhjy2V6yJM3u52evZCDKlTZ8SnadgX1MnQGkQy2lz0QYJbJUfPbO2
1ktzsPlDAQSLP09eW+o+Xb/lzZg0OMIsoPjwjjUvcvsYbRwVVPlVFjmB5u4rbbpVryJdIvwHg04M
WgdYSEDryIEjYx18dDNFV8/grdhB2KfH6p4NS78wKdlE3VMe6/TashF0XsBmYhRcfcy/gDnRaMO+
kbO5lbr8LlVXp4sOn3YJRhKGw+eL+RI+D+WIUGQ/oMJ2wswCIqO6EGRlMo8JOlT3bLWOsGZ9oZDx
hJWNvEkM74f3rtVIc9v8mEXcdIOX6zulLtl5GyenA0hWuobOVLkxyK/R4Jzegl0ePh5wzKPBXmS6
h94Pqddn/xFEOlOK9ztpoa7EE0vomtrtqKmvDqGZ7+gLYVduztjNL+PYoB36Cyr6IK2u1dVwK/52
JDBtROIThDZPj/tJ6WF5t6q2+I8QiufP94Ji8CmXoM4aIgkDhq033FAILKemv8E3lWb29nQwg6U5
CI7737rOlmxlo43tf9aDouzrbRO+KtNDr2S6L9a3W1g6TRZ41ezQLoi1GGZ7r3lTcWw5XpIcc7nX
kxfNthyGCvTjUKM1vrBpOhh0FAWn3P3gTZmgVILx9xvg1HlzZ3PwKCYZdBhxvVKwNTpOsLtjML0f
aCVXxxL1Uufd0XahCPI8BFlKE5zNc3YF8OIC6QzeGenbLCuxVBIno0tCYKvUisFWmOFNXJ+ydEOc
o6MfZXLX0YyP1pMDT9YBmoa0RMFg0MNWiGqzv7mTgYqXADbEFz1tnQF0u9Y4NCPboC2nasuXJGA7
87xdwv9IauY8ZULgxchNOPp8NCZ9GDFJwwEzpHfwIE3v+VKW1Rn++7bPkU1oKn8Z8x+pg3za2q/0
YF5b/24/hspJk3S8Ll5qTczSrZd/4285K1SOwRICbz5G7jIzXy1bxcq6Xr3TrNpk9YXhklQa/EPd
nCpSTSPPH7sHy+WmiO9cSJpviAiK9o3pbPJ6rqBGgHsXRoJQvFP+3ib2cx1aRdHVEPclapXwxue0
b1O0hgs1BcD3lRbWVlIugtWwgUnB819JkoD1YpzHLdJgQ2UNsPe28mZeBEZbGUDS7VIYUefbog+y
M9Gi+lNOY9tTvRCb6eghS17kT/UTg06tckdd+BlKwHmTFdcNcWotTiNABf1pFahZBbe4sfzWKpFe
l0gqxmcVnWTOqBXq0vsywnphG/20fCKrVs5pAQWMxFJzY2+QEqioWnhRT7vR3CXRode9YO1iAte6
gG3hDEGUywCHyNJ9/6TtSp2LUealLvqo/R3m8NjVXofixzwvMJcX7o8+P0q6IzqGWh282n0JEGYI
4h0ZwASUL7ij/6zNxWlLIPFbtcqDuNeLLkUCe6ddKcgmjG7JBFmGh05E26le4ZkTm+QJsiRDmnzN
xCLstMYFXN/GNzec8go5cWrnXX/zYL7oBNkt5y6x6zqwPw1kiDlIQInajTyZHWFehLZaTrY8uJUJ
6vXl2CVRfW3c1GKsMq//i6Ie1D/gblyE+YmF1Q+YlSNVPEsgYVKah+tcpk6waZogzRSdbNtTZIYF
pxbKkw0KjWSCSgbnmrGrgBod3K0PrN3cMgQzplcygC97wwQHD+TkIQWNEFadO+ridDuI/NnTS+k5
FXc0/9S3aCsYU78J6xSFYoaDhXe4RenYu4gChs3gCZM+2gAXZ24ttGAyVnkabi765pO+Z/ix5dS+
jd90wgg6K5BtndBelrmU/2aWLJ5Udi2oZlQiJ2lrqy/gCvyFGcwjHp0zIbhHCky9Szc/h8LTS+Yf
+rNh5TAEj3JBLOYlPD+95JUKR0l1oBvvLoc3XK3QvDLXjpYr6EteHlhmv/txjYpx6ER9U5FHCWFT
bGSov4fvZsEEH6N0HDN6PrXRkfv9Y86CLXyyZN4hYIMN6qcZ4hI4N3SmPHMEfN7k26csa7TuZMsj
Qf3vB+jelmQBPzN3ts6dQRn+CPqg6jbQA6lR3xgPhV0eQbwJ5wUvwKJAsYOZImowl2lwyVgrZ9Rr
ekOMI9iPxATz+nNCV5taFhdVxHnrfWZFIdGkTXjEh4jMLrfEvZPEgQE3eL/ypSm0a3EX8n3I0jWx
7tamnH0x60ij40xVQzHMHxQXrpjYtVwEM8mjWwEG4Q3EwLBw9R+nChIl7AB4qFoFt3WiJjtsG2yW
j0MyOJa8JUWteMN3Rx/2W8CZIw2TL6hzZ474nYoYlvjBAsp3Mwi5MMJR8/jPl7a+xzvOtXMI4h7M
8JltU6qZ3DYLfJfD7WUSVeMQ7Ae3bRxhnq6lSUhzUGr1sTDpikDEpraxUwekgdGoeg1wau/L0Lh/
iEVbP72uDuLawQR/rDXNmTUDQTXC57llyVvPqZzam3k8dKpLiO5b296rw5+M3/4RzGAmkyeBEi8s
yVOVwxbdXMwqZmjGmNVNj5Tm/RLoPEIqnp9p+M3wTwDqetBCucS2No38YhkV5wXRlwHl6s8l489U
2YnYaPhiIzfQ0kfTVjwPlJjE8e0BVlGfQyKTyccnt/I0dY+VTVbKrPE5OSiOssajWNoJ25xoB+Hv
5EQv7Z5rVhmIMpx9gsZYpk8fzs+VYKIwbSOOxaLmUiS2D4pacYpCPDRC+5XsRbCZb0d+I+PFLiXm
mv9XOzD1tHNbZpjMnRGyGCStqjXuALtGHX7NUdQ17zovs+ppm6tE2kkYfMAkkRJ8M2HeP45UCMxo
MZS3mCsbl6TjZBoNSqBBIMHCE5INNhctAcDzl+AaRkXpmYxgLm5Dm0ih9flZCe0RvVVnW0Iyb+dP
QUUrTUuXtK5ZXDmlZeXoen1/Egp8S8xTl+OFsdwq6RVPBP8poEkqj8DYvgCVpcnUQXYd3SimxGs3
0IYSLEHWxGGwtFT2bY5QyDOTETVJVtWODwkTyPxQsp2mFsAoPexXGgtaMj7CdBodAlvYmjQUhcaW
RT2cXQmgMwFp62xzRG7ir2IDYA0CJYnN87IegOKa9BVPjin1Y5Rxbnrs3a0UONix4fSTn49OTnil
7ZwWmcJmMo6MBC1XpviF9q5Q+3zBdWF01ALxh7OQeI0hxMtNci7OeXj6/RvZQa/3z0Y4SijmUpfb
N18dDI4iyK+4ercMRndSeqGFlx69R0+qXwBsbE3saYY5KNTIDNg2PZORCv3KbgrGSigDxxZsf3J1
FPGwb1jOMSQtAhnBwjGuWrjhb9QJttWZ3boIkWFGMOrnWde0DzCMH5CSLecUCDfOwZYb5e3GvlXV
bfBXx6AT+zPalB5Mo6F6Fx/7RgMB+Eycs1kdwotah5lChq3ErqUi5Sl3kNWE0BC1t/ofHisntgPD
Zfv9rrg5XY/ChS5SmNKf7iJzdV2eCGsE0zvcmf3Rt19DYnJzyFUeUIvT5OICyhjLjFpzu0O0YVNO
GxqLcQ4dKDQ0774qV2UAmn7BHUkG9FNdc9QfiPRRiRkZHhmEfpp+THrEEQXOjPlVVfER9aF8Tg0q
vWcC/jV0rpqLu+kB98F19SASUm2k41UJRRbdu7TvygjTthZajuhIys1REHHhLB84XwnNX2zLEt3Q
TiO+AKs80zmHJC4PczFvstaBgq42vuv/zkRPuD84VNcRL94zzdVCXSI2EAdMTsAF4b/F5s7i6H8Z
fAlCZGo3nJJ7yZ89b4UO0D8E7X4n2dFmLRtXqji3Ex9KFPSu8LCJCvzgx6xSlgMLmEovlM/C2OEz
CTLAjOUou6JCPF++VF1kKJsDumMQ2yr7KRztVgAzimyubfQT/UufNy3Ayw9uQIW/5Xg0idA75D0V
En7B5HSNaVBezOs14xtIdCavSUoZxEoT0mt8v7BfRIz2UDCj9P/sUnfAFQe7UJvIjMnAyaJ2yiJI
trnq2wktx4kzaZHaeJrQX9nMCKyCINjedlW7aUNEw7s+xzbq4MyOwBo7tnQ6XUeL1yGMUk7uSQ5d
pYgQq/pXP34E7AueoDd1KmvcH0tGYBeSMro/WZX4xOaLJGpyqoEXrT1NmZUfbslkYpWU+3aWVakn
KyEAAWtToBttGVLibmWOVSDwH0N1jB2fKuZ6TdFLvfq8fe2WSBUdTyzKlHad4Bk/xeX4ywSdC7X7
pGgmkKVjKqqsvSoXv/C6pUPeQeYQhpJhjj5XhCXywNe8V/Lfz1eOetoRno6YK5yid/fAq8cy1Ka1
OXUoT/8oDt3LK5n6rVBB9l6hpCPKKfNc9u1jXIB5Sgg9soyT82f7IcJ5lOxmjsP9phMkTVXBIoUT
KgwnL+H6MCD/lPdPBpHKU1wv8dHzKEkLiMJYZCiPWKGx1eLtc0rrQZmpu2dZS1ANiYONENpD0tFD
NXkA0KF+hZkHIWVi2rrwO9MPjGeir0D+LRrpplP/pCF9Gk5Fa/qZR+KXa19cjz8Icw/ksv1UJETe
i2oyfk6n7wIzPhKW+URhdmFh1uS9dQZs7bTJ3UtCO0zIUcgwKkmEAw+neAu4bR4L2N5t3Iu3PxRH
8IfJF6ISyW+qjvXU5mxxZUZkd43Ib+UXcQJTpFTJ+YlPCwRw5HU7bOJofc5FiGvJsrZt+dUTJnnR
5rX4P9yQBO/0me1IC9FtOBRuQs4sMDAnSEQ9UcUErP/Iq7YykqMb0uC+Kj1KEnj39/oOSfYHTsf0
6Mq4FzemajCmeSZvXthLnVy1NiDBCpM2xRBixSg33ds0CZeFxe207+9nCB+0QOo0tBc0hf7PR59P
WGbzihR9FnnzKU5psrqa8HDYf5G4dEMZHNwYQwfLyYSaO2BTnudVNGJsCrxLnbURV/likQtFwhaj
U+p51h6sZpNq/wybWyxG3ZtyvsGdqdXcB8+jC3iKbPPC9qQPKjfOKL8+xMdeym2dlhF+hXfra0W6
0GOUmbI+xURWUHP4aj6Rn1XH1b7Rg6iLSJsrxIO2u3p+uvZa/+hvm0xFVQHZfan3DHkDlufZdOC9
v4tD32T+frV9YFAFI3EzylHjqNfyLE/xURRVBrDPL3pfZU0SrCLuCRERJwM0/ZKjIdyi+oxzcJZ6
7Vh3J6yMra/vklguZQRk9bCaABrHqwW2duEvQom190fHn4+73kESPZ95rGvxPWyLngnEgkzlJAIy
od5N4MNBKqEjFRg2PrLxuI5vw338gRI6DipGpw1vZ08/rbN5InnemcFcUMPVrF9SrB510ofiqvFP
qi9qc15sqHd/uX4rxoj/y802uc4uI5H1JWqvQ2GxSTt/mc++hC4aJL7DvWMiigyfziPKGGBV4+VV
v4YU8QrpObsm023tgrtpbZI4ZYNZgAFkF7D7Fr5tisLp8C0t1ohKYVeOnJmaeXI7w0XV+rodWOkS
7o96SSZbjEimiU2jEc5K3TB6uNStRZ4ey/49SZaP5Q2rL2N+7NfrSbSJUoeVjgCeaM8tpeNZTSfE
ZekeG4qH/utVte3QZWQe3qKpM/DqJi5aL6/1zTdgiVgEoN7b9Z8Qkq3sYNCag6Qg48i0Zzh/Zgco
V2GKi5o8eND1s6H/HhkFhONsLlMiHpMRI1fNMO73lyVkD3KLplhdAxS9JWMpRbSMbWuYeb9defGn
hEu+oQp9yQO3og7FDE+MsvCv/sK+CBXP6Nem816WWc9H5fT+HSXsGBYEQYamsmXBv2c/8A4kFFFp
cwCENmoWdeL6YlO9IcRU6XCpEasiEjSLPhjz0gHdDt5W9nGHWoB0Gceo8aG9wFKIlWBuTUPpq11X
E9nGkzGBlfN8de9lf21sYyAHOsEw++LoUYpuUzdHwkcKBWI2sxRMs1DWizlbS7cY1uYUZWSrdw6f
QVA+OAnym+LL0F+q6p/Wy29lhgGGB5625rUyengieb+hxQVXhB/MGIyId6WNYrUshPNnI2EHpppX
29kLUGTHdsmbbYRuLeL0MvaAx3vXyzeNChRDcQkeNghTPfdGV8czGbtwH6PtCRaTP/lAlraVez4s
pwup8kifVmfl2QCajEoigH8VLlwL1a+SyvsItcven2M+Z1M5DsobgmwCZ5vc5ocUQNO6vw37bDrW
vyz67biR5Kc1pBKU+WubLMSxW7djEW46TMxa2FDOyGB7Yy5RY4bSnQ4n74F6TDdIPjJBgh3+ZcZz
9PZ7DERVKLSQhItbYjhHm2EVRvR9s7qAqeNcq4K/9qUcZ0a/PZYv17mTJLnE3RU5Uv1F1x2HMqZL
oZNZSsKN3sWbAmM2LuI9XBE8IzdbCBnz6JZGFW28zLHU28SZNcwFP+WJe2TWv5uFasnjuNTm39qj
bDTBxRGezMZGqL3QT+YnE40/DxahKpUb95lUIsF6AKsS/ptHc2bSw/Jv/AzxoNAnKYbsmFJVvaZP
W3k5or9u9pZg6V01z5Puztpl8vp1KkIRr6vDYKqXzudLcM29XLHXQXcC2TLDsyYm/A082fCXdUi0
9yJzSmMXaGG5tCk6iTEXj6vz/xi/2lK3Ay1WTwSHBFQ2Mwt0TNpxdSa/9+pS3YsPkpPBWXthu/8J
nXp5ucTb8I+H2Q+rabTCRTW/AcZss5swjQ35EvBXU3R6Xk1ZHWxTptgnKpgeW2ruiuQ4UD/QqPGd
7KGLWl3XZr6FnAROw0XOe6C2BlsM8aGp+Xjt4TomTdAzg6EaVQfh0V/BWpPE6vA9dNYvi6fQ+4YT
9rmL6CggE6RiagYrgzGRP7ay2VeMBXoGH7r/Yzsg/vA27n8YH13VXg7EBHFFppREoelNpXFD4zjN
PI0M2ov0py4wHtoRT3oXQ7EprzJ7i3sC71INRxhhSfENDIqeHaR6xxxEiWQo9kZ0BuJQiNT64y5i
fx6Syq2RS5+6wDVVqgSfeEJkUYSxA/Vz+WBJFRHqTfxfpuqvD2N0UHiRovPN0iDII9wouvgxkQu1
7j8hqdNjmIALmRU+NNAyoDRW9G0irvoJyEuk5tcZzlz5Z6imeMbeVs0BjoDdaWU8eaha49HCYq9b
YCexYtMcf7DbZC+sO7+tDeMJgPDxN5p8wpyN3LAYmXKA/8G1Q3p0GPTNyKXMGGl4SGIfWdJudNv0
v70D+JM8URiuu0cXcihjkggGHfzmlxS047AXUktcgufIG9UXFjfiQLlaPATIRsHO/bIIrZoTXsnd
OVZf3pcUZ4hgjCX3QMSmpJQQXkmqupMgvMUEw4BGgXE5vTU9flyna6MYp8+YGVm2c+t/cKqS7dQl
avjDgv1eQZBfxdASOy4lQPfsonTnWkI4Jufp6Yxnu1WXk/eveMNkt3QZM5FRR/dogtFLq6lXSqDe
m0DeNRVOgR5dO6aYXC5mt7jvzcJOyw4GnLXN+BfqkubJYiUNACIXQx5yZHxmHrL4otf3B9lE1KQf
Tv5xugyKrzFIIH10uOZToWCPSJ/7ZNDQYUzw9vYxXU7h+/qLEgoylXhoqNe7iCWUuC+WCKD7qdM8
rKztcJN5ZCFhFaJzDwZaAyugjxkotaQKUbDrpk9XsezcBqXo3mhs6F9oS3vxNN5QN4Cc5/TPBJno
zLZrPs9pW7MLxsTbCI6XhXf1piqizdbXQclRm4ZnC/5gHeG4jxLH2o1+CjaEdjDFz3MY728CxBDx
BlJHjeLF23mZPqyi7Ecc3rOFnEwdzzbFni8XXBDswyEPeyAvtfBrqZccReAXN7kNe1ljqU/H1kpy
DF7/qZYXUEIZpEoqo6DFkjEz8psthwPH67D0jQu5HlRc6myaeZ0epG97CzUuzRKy8aqjW544h9Zu
0yw4B0cLXC3+DB5c5jPR19Ix1NeSIoymbRmq5a+61lM85oZ7+l18yt9E4ZarQTlM8lrcBPyF3v3m
uHQwp+gPEHwSBUlutkRaX1P66blJxF0EHo78DPqMLjL9TrR89gSSPOCwp7+QQBHtgOzGYUDGxPQp
zk7VKQUMOSyarIYZJAru253mR+GDUHwvfKIs6UQ1m1ohV0CeC06bbhGBKRll7l5X2r4+7s6Prb/x
PYzmRgvVdMx3qU4O1OpF7xU1o26FEjLbRufYYRoTCqxo6Ohb8Uw1mfRpmueFV9W6RDnIi4pqUl8K
BFNPNPerj0nSPrEEHO0qXqE3/XF4Bcoav4/hl9QWsUV+sb+HlRin7FjXcKD0zH7vQA7gPwuzlvMT
iObmKWY3ZSyBkbRX32pbd7Uq+H+5OYMCIRMlzFCmcYmSSpA8gzyPuLCV5kPa0/Z0olnGFyZQusO4
7VHqT6W/Edc/C2HjRYW8mYBC3FPRpiCIcTa7o/oZYVdGDBKEdVb0Vj6P1RJwRykQ4ZMhYzD9aPHk
xQcRaf606NiWPEe71+r8WJ2WWQidPezR8P+jzqrMMEmm5cxgsT/R7lD8SrDyG1qbW4pTVhzjBrri
Jyy4JaGLkv2Eo5KbvvE1vq0SJkObEY4nMsfZH64cUgGRBkghceooq92Qw/Ny9I2PVuFDUU+zuMgT
y3w9QLRcLWHg9JME9F8yYA/qqnt57rbsYiS9s6xRwMQKYNX6h4P2g81ncchfe0mOyFh78glvRcvO
DMcm7KRE1yq0Vxspam+QhQ7WuWg0H7ZU/LTmeyt5TJvDRz6cUROy3Ifbw5IPJOZrLMkUNEZ1zioj
Ahr9kbS/R91lfGkflhSq7xOTEmcxpCrAd7dWYwjxYFCumkcRMVCr5iTBnYSq8AbVaUAq2JnMDPKW
H2QvYpeyuaUKWKQUtMzmM906KWBiKil2/RjdfrxXWCrdPmq+uKx3lUIeZzOeqo7ZvNGv5crOi1AF
QwPvXJUTOMtjGnOD7aOKHnCi/0375mHKHSxW7+TlLZDrWmduwXlj0++eUjN8LFjkV0TRjY6i/Uqz
/HPNBWT/5g4NjaFC9rAQWtOC2ZuFAhuYjfXQiU8qwjiYL8WSDTfNTGTSGF+lKoo+CXkZgz91YlBh
bd7xdJMLvZ2MZZHRXvMz4spMXUTujk7jOQLeT9EocFIDOyi9ms2wDJ/cboltWOh63q4uAh3LTLNj
OLii97JLTUaXHENXOaZCoBO6PgdLxJjKSpAyJSaI5UQn5J2V0iULdAKIVIhcd4nzjhzYqpcyxmWZ
t/mcVuzF7nsTbVo7E3mi3Jm0v0ldvnWHCvyZwC+dURAFeDKmt3l5sEgwuEAgdqr3ND5Xc/1SWwKa
v/woJzZciNJydD7xz2AFuysUGgkSmSbdnElI2/mBZXMtIH6PUIJIYjQBjegM3SFZTliuQ0iL/DMc
vgDA0N94WmPj5iUYLcqtAYFWCoxYcAid8rwk7w5NYmv0AAh0Z2xvQQWrzp4od7W1twj0WFAFS7uo
FNlsjvKF2vJIt0akt/WvYyDnm9oFCxB2tUzvRJ8g90dWeWC6VI52Ogo6NuA/A9e+IDZjcLSu5sUe
NZG52aoXDTSqnkrK1ytdXb/w200Fqc3WodpYDst3KjBEw+Qdy/4Bs2L4IGsJ2bwUjnaCWNTQZyXX
UfJrLR6fI5JHvhiuhIWNz7U6/lh6SAARwSR/voxMfpsLrXh7cfnVi54nEi+Si2IgnIHGztWcvPfx
xfrrdHZLK+qWPkeMlIInP1fs1yta8VgOTKxg2YN5eH55Rf60PBEYRfAncdYnDHxx5yIAvlHoyzZo
lvYof905cboO9jKWUU+K5df28En615nzATsH2P52lsfCSelHblLBIvrSZI0R8BTup8HhZthceRbL
AYPWLArcbzruxpmrvPNwZCwYetmyf65RZiCEKbwMPEbvpGyKwbI6fjUP3mOJWExGBCAvcOd3m+Wm
QWusy6AL5ZXGtX1/Wp+rD8nDnFxMDwptd3O01cef8YESfGIwjC9FINptr3Lm1U05CfZn4/udSO3m
o4VLm0VbgaiggSqjHb7BN302axy/uJib19iqNYmmgDuus++FlqWHdDFZMGVfav5BHebckIElWEp+
8ZB4nfMRKlBbp7xXy7T6BtPd9j5XPACuXoOA3vXcnFxTWod1eq3AXAR8cxmqDg/2Me8lWtVm20ms
fXdCSdM7DAbPp3tx28LVEJA7Fw6wMqiGMAm0LDeI8hckosuB63rqbcNlCk0sKYUjf5zh2trzVi76
6qzDbC9YbXfb6vydU0gdBQ2AalCDlodBtI6z0c41wAecE3A/h23y/+jfDI6huMPBtVy/dj8e58b7
/Bt5dQoFgQNF7gnFS2uhuLJ/U9qjkbkQ2F8OqnNf4CgqvxucaLLPtm+8BA3c9FAe1/BoaNnw2jBO
UAieRKyAX2JDo/+X+8tVvEbb9Hnsz7bmSnQi1M+yjGvUtbIH+S2vBReyBc7A5SAfucM34UvI/2oF
SxrJ9KPeu0mo/QWu/DOoLo+fAf8+K7mlFY2St4kZPwM3shqy+znpN3USLkbdOpD2A69N6w1qcB01
zZ0wgHA8wXLXDzABWcBDY3tplV47wUHiyvaRmBxsr0nA0IRf2BYOkSbGJ9e4vBP5oI3Q7B2EeMzR
1SmMJBlnv8mR1ImXLxsjk+iSnTNh0BMd+IPYBNUjmgCU+FVK3cOmbYHh9JBhsBq6HZNUWosUjzxt
HGJF7axx1la1E91UVpaJZWkHTJFyqhbwkU5/NFCdMJ7V9goznULUb/rBOPCv34R+i0+u4+XGru7A
G+7VQiP5KHYiggDRxdif2UXfWkpTC0jNwp9NZBp8RntmAM4gqg2fXPCWQyZ0WeYsY2ieWJaYtxta
4s0aBMYEbfajofZ/FTErnp0BHZiugCEy4O+MneldY1E2oAwVcDEhAULO321t8H50SViMStAYghid
aLYhiwjkg448SxxTTQKdyUMgzwnI0G/5k3f88NY0ESA4COLTTHxKHuGWrWqCCM5zn3OBEoCroU9o
A65bIMkn/GtaCXhF8nv/d766uPw/WS1TNGOO8BrgpIiWPYiL8LqI97qKJ+PQQZPUzAFXYja30VI6
uSkZdHt1JWyznHFvmHPjzxILGlZMphibnDpsG/9Gxl9mfHbLBgbwkVE83U6aztzKd8sN80U3qa61
JeYH7Mm2TxcZN8yAXyjF+yJtRXxV1uWPr41MV2+hANzu6W1LcPEtnxbtCuXtyEQ3Fl0VSmq9jAKl
coub1g/1SeEb384AT0HYWb5fYa+1gcoWD1jGLQGKh2DH3KaNijZGKsj8r44p63O6PwAgurtt2zB3
mhTfvRHqnXkYCOHZ7pe91bbncgvki5UEDg1xi/ffwYYF7Qp/ICkU53zs/VxhsB6d8hzRfBQS/Zmv
D0tcn9jSpxLICyGCGyW8QuPO0T5URQV6TIpKqUtyBvlybvOLJ3lcQN9LJLaGKp+41jdIU0NsabnJ
UoOvpB/qqOZ9Vcmj4yzJ0s0EQSFtGsKYpPnwz3ZIV3fIwIfyvCY6Pvs+74VPTri2/EMdsCaVik3u
HbQ5N4EE6xxIkXECoOgteX1qyeOiSlIBHuLQy/SHN7LRhEaUV+U+6usTiUG9RIVcQiMbuPFwxN4T
B2aKBnmTVZo/xXsgJ+vmX/6Dxy0SaGZIi2Urkj+P6B4tNsOxfkCPfGjjTwn48/kUm78UABMxWT3K
gvuDTqHuZtsmz+4wN/MuFIp4Y/nTV8ss1b/zWrnSge8UYXGlZt0yHVjTbaZYyJSQZ7vsBBXbNImC
lnAfrNqWgB3pCwEpShzYCuVjGOj59ro6R4/bEnBcypbPR9zNHGOAu/e2LIQL1/gAgHX+ftDek/EO
p73byY405gsXFaIYsdGQkMgO8Mqa0jK/pQDcM0az0NT9ZP4bi6I3sNM7+vCnGGInMiuBooDu+8JJ
CHhVCQRYdR/B5SF7W8IBsNNGITxFUgxzGL/WAugL0vBUepvXcCezBzCv8fcLwf3EKjI8r6RHrPvk
AOfnMyJ97CmIZL4x69fO5ICzzB7egnJv7+FHFrl9p4StuLXYMbBEaky+8oseLe6le/k2Ho4ohuTi
O42DUwGUS5fOmxWUvu0totPVZjC4lLxHHo+eZsRZRnRMqEtrVnW1bz1MAWwCe/B90+puT8dYLJNc
COIdvypPMHzan1VqBxchtR7exj+CTkLg7tZZAHU9hdnaEgjRQMzAC9VCAl+QhzGAnyj17t83iz5R
JY1udenja2Z9WshBJ6GYUR74dU04EaxjqDg0m/oz33nIaLFjAH411ynVRML7vPV8tq2CX2dHH6An
7olbI+mIXMT09UJ6vcOJqXG7Ln8sVxBYD67nOL6PPrNjBUDoFlvl4ehAmSUquwfrDrjztC4/xVWv
y0hvtuAlFVOZA4SgJHzA1K7jolhFZBc5eANZFmY30DT1OQ72TUrAnUqvLZSM9LKPwOFefjBbcT9Q
LwpfI3L6hE5B/rDskfK43jjGQLGY/gQayFTfbZGg2uKhJ7lxpeEWB5505GKfSispBGj+CHpG8B30
rRxb13lxai9d5OCCD6uc+VTh5JRk5hFVZlfYkNTXz0CXovhbZrxzWAncRM7yxpbR/o7+d3cP6iL5
MB8rhC0C56V4K4dGl3/NdQaLp5isj+tj6KRqAw9FWNYFreTw7KCBmXyNkRsHmODzxOXxpq6YJE71
XLDfRy9wUbw+g1VpP3mcBSeV8A0mx5TUzXIXx1yG6X9N6Ir+jzzwWxA3PFasI6+lQd6Mvs1YNbb/
T/mdrCW9yLGxDpcpsQENQsYO4p5vCDAv+JDQjQztfgQTpSWicVCVYBm+GOROfFNYy9f65jNfin0W
+SPXjeC9pktegecdWDIGIL7OuCEOPpAdStz0fL+vdgFOjdfVr+y/65+QO6mxdpnxsTrNiUlW22Ti
6VhPpeKXEt18hR8BpwYwMnd7PxtOeIxPqdFxXgk6uH0xbmcqnfQ07VgdiwGdcn2Q+YJD9gBjZo1l
RJhiX+9sx/okF1CLGxnLC3DWlPwYLZYLOgfeOc5Eqv+Y1+l2yNv5033xI0FUKL75NraUVce4gYG4
9+lpDVqzhDOifH4oZt4O1t6U/TR+yIqoNMbZBb4vv5/bfxeK8CzdxgKYnSDEgGFH5dXZ2qJNVWnP
t6atx7BdHFoQstCn3IM1Qzx5xZ52tqch01gkVN5SvP7BTr6HXBabooumd/WMZ7sV4EezoMxxYIq9
pbUMXoiDREqbfG5CsnbS64fli6UKTm3s5z3ivj2VZKMgicVhY3K3+NczeDK6TIoDSOCJXpd+f24M
UAGanpQdS7WH5a8R4aKKtfdLiS3kc32Pmkh5Tnl90VMzDqw4CiHs1q1bkXcXdxCah7EcU8mZmsd2
6Ou9FsQLIMJplrBAl+wyKGSgbJUX/wqZgPyOwKtDxpcgmQUga4SUUW3A7LeeFmh9/jUUik/w1fg5
Qe+aaRLCHdC5UQW5FgS1sumRjusk0XK6moMTSZsFQAxmmSO/wr+DBL3WhzW+ls//q5DVFIqQWG3w
B32eO5Ie2W8u6Eu9Yp1Z9Ql9+DbojehqDfGtcneN6B0s3cTjpb2bcFzhqTCcPuZXsLIUipFcgKOr
CbHcPqRjhLO3VRAzOTVyAWp9MA2+xcl38J3ofRrj/balgszy0yg0ywjIUeKJIITK62LfgrizYqAL
JAox/SkQNBMllO3SetlBXMDo/+r6u3e5r+bFDogl7eN4hc5PWfhzdzg9Yui7qD8guSa/PadVOFKc
cxrzP9EfdkIu6pP1hXW2qcsdwBTIkk2Nok5RoJ2FmEWLAKMHm/3NPkQQeWwwWr75UaHG/sDwjPv3
6AbAv5fmvPys17BDd9uDnuiMd8gechR8vG3pcXHTF1MhYHMa/fN9rXnqSg2hzzoDxjWXUo7BZtyg
3jbi06JCdIUQkfzaITVwPpBDRSeD8PchDIUfXU4iRyUlWogQjyvVPSsywEm5Tr10iRHeSberw2GX
0WPcovs5JnrXD7Jl15S3bnouNgc4ujw4aEkNzkh36cr/270tN+Gl4JFdc7v/JZtfyr4z63BtHwpZ
hVrNPdriEwMfGaWkjXLA4Z1q2P+rvFdmdJB4eKNxQSwe8A1NAoJZdA7wYTbWPE7zcenlXdwz5PNx
nmSTJ6kqtFmcWvcKFhnFsuOj3XgQym2Z8qpVB8FoA5ozh8neAaBi7leWCrN9k04K/v/T8QMhGRWi
zyiy7OntAF2S2SdLHPHChdLeZYZfs6xJsa5Yp0+Lh7mw8sQmkXNEW4steimAHZG4QDTXBHVm7E6n
Zg6bfX84mZBqM4YoTk+nZJvY0sl2tOTddepsSLOEfdjKFKgF5uRl58mzT3tQedogk/iygjIqerui
/nIUvVuKHbs/+UoLSLv9/T77JwRHSWOIcEeudE5AQ+LmQqIKTdfheaAMek2iRynJuA4rfRjb9QqO
J7ni0Hdt1dad5VoOql4W6EzZp9sTXIB1BWUbciNv1a5n4NEOcGrhgH0MLXeyxqb+jnCK9/cgH1Ua
3M7P0A8S/tHqhNVXXjvYknpwB5wrq9O3PYr+AuwVVYw5NmoxcucHyjDRmb43IGlh6IpRZeJYlJKm
jVxsZZctj1qzNvt77Kae+e5GIARhIL9LXzTzaxhaDfh56hEZ6gfMYlTmM60b4ICC2zrmCDGMxRfJ
RU5a/1KzgwenUIwLCU4rvfJYNwS3VpynsVij7Y2bzejLBP9i17veylTdesJu/N1xd7UkYZjildee
W+WuUYrXMygpTUtekKRsZKRwin5WdhRda4C+k7yVZmfifcl2Kyzc8Jq97LOeAEzZ4A5PBjE4rAI8
V9xWyoISTStX+LQPaMS0euFnD+F0z957yep/FjoP9XhAUk9WbA8dmYoEKoTIMwT9yOJUzxN7eQWf
JqxYaUG0ZuYDpG/jF2AniZKHc8+UFIi1eSEm1g5tFslANBstNANzRZkZ9Y4+XzUc4+NHCuNPCK2v
tf7/w4JDMCVd3K6Z2iyh+ioWWSGK+iYQrMsXt8yDjRCx64XjxAIvurh4PEuvlhb3MaykkAOkSGeI
GDgmI+Kz5zrjbibo29L807lJ6TnpSKvKqLeYZ5Gd488kOkq0itVugNOIiMYnBGpGqNWz5tPHG94x
eUPusIvIlKHeZkdibYpDOsRElC7f+DvsPosO1OEmPUena0SwvMr+DjRnOOGC3VnRxC2C8p/rjNQb
Cfh0Qh9LuhwxOdl2tbb1sU2K57bK5mcxDhWvaX8FZx+EfX78vfa+UJmii80R6DGKBk1lmEEvVqHw
AJ3kOOecMNh8lV1Zxb6vqLFiRBrUJYkAAn4L8Xo7bzosgvd2xu6A6WvgbxouHBJNUwn256H+ovw3
hYYWcNINYG5hBrD3VUxKzLILtpQL24br1Vmrdp74fwhW3aqwGNQOxODt2mPLeXib12Kk7boC2E7G
oP0bYc5HTqfWuCOj/jW4CslVPKmDIO5GHkdisOtUNQA7W9o5cy6v/hnETYldHn9g38sxYPAD7YId
Uz+EQD4VekPvZvS8oIpFm+zC/FYxt1fpJW/HKyb5I8DkRuCfkRAmxgIZPiT4c/HR15qX5uzhytRy
+vbD3t3qu6YJl8xVRQC/l61ngfgpKLBADQlMFGo1znNGmD++jun8TMZE0OzH3N0WSqeX+wlu3fik
UZHVTQym2XGt9ugKGwIBGcxMTwfI6WBSlg5+UqwCw3W8upF0bx+abUmYuOdtYk6bXc7DoqLc99yw
aXhlJEGnc25rTEn7G76xoWm0gRJVluAlQ7Ob1e2mVboBHtoccMbiHIK8idMMb7QLg4GTCDLMboWB
cn/0E5Vo99LywxDKX3VVBNXDbCRyLY8xe1LbM+VxpS0eYBAGdFSkSQCqXXnVWYC4TwAIV/Lepg+q
83zvJSAFpk1854U83A04sjZEJ5Be3au/nknkMFC3xNbraR4ABvf0h0zACZe84KkRFaXCUrd2GAFH
04IZHdKrj6xwOCgYPMbw3h6ZLSvNLvUiBPtwRJLYFv3qs0/0bSf7k2Sify3l/xfkuKtquACYxN7t
y13MDJrvlqQMbQdb7jpyqqUpFx1+Y2ObpRHVjlAAJTEZ227EettLtgtHundbAynd9HZijH/XviwE
VbwuRZ1g1ifS3PHVNYDYoPJ7eb8tBfNLponWjHNSWNtoJ2KYW0/AkVd6an2RjrpJQE1ymzMaK22I
kz4WEDDQjV+EGjZbcCurNJut+xacQ/qcWGBFjWPPR8YBjnMu0+nEEhRc1nJy0mzXvzWm/8FR3TjO
CKffvhq7g+MkX5y1GsdwG4sSa8AOIcxcJ68fEUUdo2rlZFfefj2IH1+fUfTgYeUxo71wHY2QrF1y
h/bkI++2qKAXOA0pdQQDNeAvxT0Vz+4UNypJkjSKhvpq2vR6ZhX3cMUA14755oq7tSE2L1OT/sC3
dTToOvuKyZIz7/Jnlo4qNtdI7Gq/yJ1Z7LlrZYxQnY998hxCPqrTpr3FnipATnimOvtQPHT7IeL3
FcIAHPMX/4a5+zSWlLGRRTF+j8wYVMnDhy9xb6wTEbrfL7pmiCwlMIS+suVSkHcF2NpLhbRg60qw
d0QDO1kd6WvPtoU3uFkjVrVETnhAJhdTYoGPjySFhCYaApTyU/xJny/dhn9ok49U0+rfQluSVe4Q
QT8nEStW/Bhd+zmOvsKDD1ORMA9m+aqLMEGbpIliV0hmAfKmoabDjn0OAhjUw+0aG89KZoMALbUp
XUQAuDcmQiK3qVtjl0fj0F7eTFiXbCwqTtOab6eEnEgDJfRsgWKc0/+AszEtD0P2P3p5cv8LdCZx
8D0/ZCzuBnB9fb0/vSNhtX6nKExEgnc4OXmgXo+op4R6bFrbB2MyYL80hi+EP6nne9Ar552PhTh2
VT1FZ6Rqw6auq9BHuz9ZeIpqZc4a1GcrnkFZTF1nXx5/1K1Ly0RYF2hfSiF5Zd+r2mh7ujrtrcVW
1hwDUNIqt/XShMP0CBABP58Hd6mhrQK/TOsbgoubm3zk1te/TNQLbh3YrwJu8rv9MvvPtmE8FiKH
UGTOL419z3rvyzesnfVXumExNMXyw/ePmy/oPrAuP6pDin13AgxwmbWmLD2BhOEv2vQnKU+2FHf6
A0dLw/dpuWesMLFUrSE139jh4PuJFCUK+gzXeKxdMO1Rx4SLohyW+dg2quuobWfmT/AZWM4y4u6n
di/UVmLXMCwDjJnQMiB72os8/NK4D7WZ2drQvlhbmRu1HqaKhIXz/mP+QlGq79B3fTCoWC+swtnz
U5L5LzCMNS5vr9GIbY/HytveGuR6ouclgElKgARJWKwtQiSyf7AdbXhEgfIiUCiKdf/b/sLXRFkm
i/Nat8s56nMbY6wWLocf3BOADWOy2cZRbchY5YSTgNPobW4lw02zDAgJ+plL7fwIOao9fudU6yx0
vTSBJ0Zx5z4CtRypHkJYBDF+0ilZ3JYq3PFZbq6EA97g0zSbKzVdjQegGMIBKgrJiSvvtIZjhcQd
C7d1S6pe6fct64H7WtWy8TpOY1ZPWwHPT/ydd4a/q9YsVEPwT2/ZQ7sKEXqSzyZWrzEyQKhOwwnp
UhJiKANmhg7V1WP28GT5qYhQiJzxPbHJsmsgT9XyMNO6XXfRs35CsiDUTI3HQl7eNi0LHpf4czhQ
c7k09WwIBBolq6qYvxu9GrgwCV2KEbkh8jLLJzMxA9goOa0eFKBdtU4RytFGOv3galcRi4d/SWHQ
PMiv6dTTTq0drS1P6Fp6Uwa8HUUo5OmnVNZckahzs3Byzy3cnlme3GSJR15mDdmc+eVAT2ayjJiv
lx1qcxfgyjgSf9RjWC6sserQgjG2TY1s83SQ+tVxGcbGXCkLIZXDSvf2MPtmyHYJ3IcjTmiscvOy
jBmcYmBCCO8L4pPNHnVeCMKHjoteTBEdRpDCebKEYx+Yt6nthL/qKLSyEFlTsCEyNGVg6KP2LQVH
O+ZYeHAp9DIHDuHN4ygkGW9172dz7dbqyo73wPLIh4tqs2n0jy0YFgYQ80Jz0ac1ETrvBfMZPmjq
/S4Pm8DGgsP4Ow7hR/jhqmzwVQ8PfRJeDKDN3Tt8Dp1HfqM1Qt1Zv00nSqWG8wvQN9YbyI7byZR9
pCF976qzcoyXj3aVe8Q0/SWeCh4aDMq5w1ByL57lsng2aYlCUVnA79VfHDCXeFEo/fBRGcTKvpiq
0ihUCW+4PdIYx9Y/NVT1AsWTc8uNHq2tFJHXSRKIRt/DJihrgnhiLcxx769fYVS02k9riMClc5f8
2/4orbqpKyRt7A3/5lB/fjJxfVxZQtha2qMSNvMDBkSJ7UGVc7LOPvhRi7noFJo7tdakeXQM4hA1
Bs2sHoP+BMevk5Clo/db5mOk6ZBEGqy2iBAGP+P6JLB4gWY6CFWwWvGRNNNIKjz1MFaUCfaqEWyp
exJJbwsat/b0YJ6MqfVZr9nHiRgkjWuc8VfKEv/+FvCY1eL2KV+FYBoVStc9dgbJ2gZkqRcx4r+B
4dAV2golNnHrDrUuRYflFEsNP4Lmv72+pIWnbJDcaRi8BtWrzi6oltnQ/kXeftcFHC18GbqTvPEB
C3ZoD/DUWgSYu1FCb5GjpItXsh/EOjCls0fUNnjaX9oEFmBh2pePWjAO/6TwlwfLGI1JFybwE6Bi
tRrhMLiMxLMDE44e4OYiqOxNssY0az2B0SKzK4mx9q7Ms+/jkYPYv2XRfo3CBtjT1bD0b4jGXGV1
e1F1BDVrmNIdBb1IeK6+T0VlUgmjsRclvNo/fIhsUwdEvivjes3fyqWh59JBXTfp4cpOL/vox2BP
xHndo/LB57bjnv/P107CM5AC9gJ2X/Abw/5gCPP0kLYSbXvCnxMSIi6tSygTVxW9yfw7fLB+uIeY
JNC76jtsP/Tj5+93wCqp3DCTt53PYGuH+qgZsR40b9NgL9N4N8dLALjUpz9kOgbuNbqapTKtwNkj
Id/egu5Z45VKnPK74wGO+t9Z5NeaCz4PJJeU63Vdy51kQ0ZrMUwyAFESpGzKFESJgRDrssBM19ZD
nvh+25zVXmzOYhC1753VLyGQV/Rs6LOGtWjzKnQUlTKQ0fiAXkg5aIJyFRoHloA724GNHtyJxB57
j+8FPJhGMVlKH0fBHTyIgKJUY+C7DvzWJOnZzb/6I+AYyYFV5Wj/3jNDAJvsmg6h2imji6RASgjG
/+RFl5/rvFCOzHLwAkEL4k8sksMsOGgnJ9PrkNrXB3bzSKnnWppWgkJgSkLqspcaG9eluFTrTqJk
5coKRv8D/RTcP32xXs83CQ3/9QC5BScHRd+NaPaWI+JN4195nUIdYG05YXbF9BsZwSqnZIZSe1YN
btSshAnWEpmzln1f73cGeElVajbiQ7YDTz+KwmklM+YzgV0ceXO/OprAB1dv5IEssp/0juWUsFa4
fn9Ftpq+nJI9qhm1RAxQV7OqSMrfyUAhFgjIw9PNxbtz3LvJb90d1tAzQAbdozDjLPDjlD037d4C
ZimRZb3XuZU9Jp862rWLrWXXubhIWYchxYJ/Q/CEKNRKMEvJZUg/AFX76XZnXr2JjO1BPPrjfsXB
tQ/mn7vu5hjW7LYX5RcF/He3exSHSSF1Eo/Qc6n6AtOexGnv42xHwCx7BE84rat3kJmju1seZJTu
+tpic64w+a7sgSzdccMpUEsA981/20Q6wDqNXGZGOT8DbBAt//l621EQ6Ae0KaD9gDJIqoDs28M7
Rdp5wbNSialJ3TG1fwVSukaelnE4S/YQCGbH3JtirUIuaKww0k+BhB1YPYeUjno9JNtky2GncPMH
EqlBj2aVXlWns2olHTU+wRzpEokj0oNTQZ8QDscrPrCTYpKeNCJP/byfCLJNAhHF/JsWBLCtJO6M
wWWpDMLkPTuXq9BzG+VvtflHaBxci2135593zt6X2i+CRVbYPH9bypwCRenVZC4TYf+OEWUlfn4A
Bz6N0WHmziIFu08DuXLVz8Lm9NA8aXwa6tugWYMJ3vmH1h1kdfRqMAGzzzRLa6xXWt7Vk9ZaqSWU
kmsQ89gl1bvKDqzv6Rqncja3/FmxOOPJcEeA4kSmyLZ8UFiDDc/apSgdpjIZR7G0qFUiIi0X4tst
TmBE9yL0Rbwx9WumO5YISse4q8QVjkD7DbfWUMd01An3A+6rjuQg75XReZ8WSfSOT1h/tKuaSf7o
8u1PObmMb81bYuceuGCV7M9oDmDrqF7sCci8oBXKcQbzjoAehpPvQQaiZU8Uv2Dya4vlz90D5plX
87ZqDPP9zounC97RB83AqzWEx7r8NdBN3r2NDAgFI0DYm8dbQn16Dfr0lFVnx3VT26dBuwRdx6P8
svaVVpTg7mfVcaWi3FaFzLSI4dT5Muf9Wx0g3HXw3QThJWe65XtGnSGP6sMW2s7OfZVwjWFLI77+
Op74HIEkffSqFR/W3Tn4p2suaS5/XNNoKsth8RxHe/66AXTIPXgp1n7GrYD+SvB42YALD6a76ice
YpopwFknrQmGSGDmeFDB9GAs5aJZqxbr3Br9JmjbWEFrWV6ytMnpauZBaqeFJYUgv6S6tdHrPOkw
afFvuDoe4sZdu9tMkf6Qy0AiWzkVeYIhLj1H0DPzRv2mYvqCa6d5Jq8B8puYLx6VizVolzLPhk+W
TA0qtBmTfHzRNLbID3hrYV7yik5QeECQssNTI24fktXNHYNfZDAhvFGsFg4UML9aUiI3n/FVqDxp
LPVNDa8rGdV3l634r5YwxiIxhVSeWn6JmcbQvMUrITQco9/IN0bMWStBSqbWB0LuizwlScGrb25U
J26jWfFjJR+K0ahtY8EkCDhkMC/Cb41iPLG+LkczcmUWZ6K3l4eUwkleDI65hWkkwlz9PKgK0FU0
8++AiFIOBxP+z3wEnzd5bml1F8PZQPMBoRQKDyxXkOdAHW/kkZDWvqJiqfftIH0jl4u2zAa7HP4y
8X8mhXG28BY6ooyF7Q5cPp9MV5RdSKRvxtoDnl2btTdA97AkGoL4p3TkJISDN5d4ff8g/c98PmY4
iBONXaMrLLL0O4ubqKSgdwWd0WrCs2QhuPxo8bj9Y73uy1pOCSVGB69HeN1LCb0d3i98cTcGAMoO
20wxWurJSKaQq5jA5gRnclJCBwEXY118m1I//BCLoBzhtXOKz1DbC6+9wZnk7B9itLT6vN76QUxJ
IOfQex+6EfpYTI5mIjiBO6+0eAM3EYixfGsxv1ZY++MuncIfqC+JwuD9PN5pd8EzJleEh2oDcGx0
ODIPLfMn7DYxneVP+SpNTwFH3XT468kN+RnrVVs6isIiaq4H6Uxqkd/kUvB1XOgipxOsn+qu855n
x+/875GvlDpuveihya1YX9rf8Pic8AGp3LALS4xxspVA6d9+YAW4bmJKgkM8qOu4QTqqP+aBVJcZ
8jAkS7LsXryauXlbfTzK3Di85jROhx+OlmNqrs8dljOm6RIerAiHEXk/Q59g89uuoattoIgPl434
FVq/4WtoftJxfohfBNvtN50QCa9/kiTaeg2b1QQjzbaVLzgwK3WDGTaAoevp4F4wdEoHs9B5CbKO
fIvALUryO8sWvH9d/H3uTtmcmqYN4Sfk7ciH0Fcox8cY/EeBThcyEaPC0g19bDzf3sN+VihGu8iW
MfS4opWYONbTp5x5Fm3L6Ddh5TDRTuCfkaCzB3oL4e9jyJeqG44Tc1YmIEq2TSLvxIrXTSvNCRp7
Da+sf6H5XxNj9Ud7SVXT34XGFyskhIBhh5TUNGAe8hqOFNmqzDMXHrSut8ghGCsbHzfiOa5SRWgE
yQ41uh9GiyIzyvgsliaFX8BtZnNTTb68zuY3j+AQaLzXzhdhpZf3dYUcA/LJ8AUdmWBz2KEPm9me
iDfvvhYupEnLOxWGhGi3y3GtIIKsGG7M31xUoAEi88g2Jlpo2xnn9b7iee368Wa8i7nqga95K1UC
+9AjhPfidvgBN9jgVwxXMM3ziO+GubbHG9g9lz0/uw/+ts//9jQwSD6zHxhKGrY5e7u3uZrSuYwV
sd1hQDXCuSqmWurrD2oqGHpE+JGuG829WUgvHLJAs/Pv+HhwkwQ52SgVCpUbdQ8zz6o8Y+EK2X+4
2mrXJXpcz2EI9BxawG8epAPaYh2/2iHEnq1fHkx1ty4ytC6iPC3MLx+Z/5N+I+vZLQkpdZWjjPIB
24prBtpll76glntVVdC1fHl9C0j+72AkPEmKHQQPto4n0rU+yKSlfL7sMpxH3ljoAsamZy7KAZH2
0zhgMNMT9eADmPVT+bo77WCW/QmGW1zY0iLk/lZb0/gvrodmvGkKdAiHKXjLtaxp//tY+iI4wSsq
ut8Bo2HZDORmaeZTToXdi6snZHBIrFAeX90kAvi8D39BiAvd1KKfEvsSS19jmbprIop9mNf1+h16
GrVje++ZcJKQ66V7cH1Bktp3kHYobVpqjarfRK1XAG38Va+cniiRLBhdhErCAYrCW/Mw0GFF6cbk
1OoMFkZwTbIunNAYubkjy7k9tXF6yyHx7d06g4fSouGKZyUU81qCq8bYhVBrjFv9q8eIVfK6J1bl
MLsW7xshsOFPjrqlvp1bxMGVLAGQeaYMCOobjc6kEuoF2Gd4ILc0AbgYPQXzLJTKLnpiCKcDOD/6
wHvvgEzaAcjWIsEhPG5QKiwKkAnVUprsIYeMKFfsZsshscOwmPzYwPRENaK8EF+O/cJS1B+zoD0y
O34XSY+R+gafV7lo4k3et2LzmgHEU5VwwLbHFjzA168yybYpn0ccNxbGN3SjSW1ATOQMoPghsAEE
CN9Iv/gy9ZWPccfi83NuVEnJsvOXwgmpyeYALEVJUdpVflCUErSf3I9cgcn0muWbC9tSgNJt6tzN
BHanahzy5qNT/PzwbUIembrQmOLQeH8PSrorDGWit/eFKNyooVlsPBo3GjnPLEXVtA9WCIWw7iI6
Ku8noelk9ALpQ5wMYyrlN336Wozr1yudxynJMj2SxA850wMjyW8ONwLKXAhI2I+DK7G8B2LsadIJ
exyn0LnDPO/enq54EbccEXXqjZCzM6r5Xek9RZl6OSeBYAPvTGiaWAh5cpSCJEIhTZ0sovD4Fizb
fTFBaaSzsoyfzcz/wasMjz6aUQRAWpRw41W3qkYutosl1iGtGaWLmkPF3rDibfcA7avsnvxfxwpY
KDx37xEhyTktSjy38VB3+E1YWebmvz6Dv0HauGBNp3/UocdYOM13L2mAIRm5pkGyr9+acSg9pssy
0+bm7Q+ZOUY9v+uA6XbwScM0DUmXf3oJ8XdLTfQL0wqxXaC/MaecOZPRk+BM6Q0EPod/6TTbmc6L
uj7tW1tK2eCfUILAWWXWFu9x9DWGZ5g+AQXrHPNiSWUBETVlALqJczupg6m5nVFFrS8+tqUhr6g3
yOvq0iYv0UIVRl0/syjDPWp48koZzETKrFHT59gtGO38wwXQwu6O3/+f2mdmZZt75Z/Qt2oM/CpP
f6C/mwwyeHLNhGn3MicF42toHnmF2AtLtY92nxE9XUl4ujdRYNIPZ/fS5dU3aUjtWDcbW7VvvYBw
/s59mJBrcja9cNmvtQWKeu0YIlcIF9sDln3ZM9dDV+zdo5E9Vk7vsLViYdnvdd5mImMWg2zT7+ht
fxvNR4yH7jwx14mj+4Llu5SHzNCqxHLE7EujCdbmmfMyZWntA7XWKAzaqjrJXm+EteKThFSM+KGn
IHccgGhdBlA+25k8Kq4nyXN6e4mmISCGvvaGs4kg63V+BhdOFmE8GUiIxrNRuzwsbssr+apDole5
SGLBLi6zHhOy189d48FNPZKRnsXtEvZ+nSEh17qLoy3UiKPXxvmKGGSskHhoTPH/rC35vGfMMSvQ
R7jLStXE/Gvaw2OB83jAxmGnyxjEV4rxhR24xpHJlCU5TUF0gS1MtvYWvtZPvPpxumCgO2Sl4Pmo
trv21TeFP7Eg6PbxljmSVwSQ8lSxIAYHbk5LmZ6AetUA4ZpE9rSk/Amghqi646aVRIVm4lg81niN
HQ1UJPZwZc882A/3be12xZwcrCs6LEHbfiFmlVycFTNNbBalVCmOpNTDMgg4XSExPfjgG2x8lB4m
v4iCzHuPUaHduaeHtumJQ1WxIrfqBE0bYTcjppIj+kvjzu5+ePij6B8ZSWACOCH+OjPxU3e/Bq9U
PhC8D3l81egTqcg6IxVyNk2HukVSy8R5fLNeJD+BfM/KqinQE4LPzk2mqoxiEnaM1wxNwoCLUQJ4
hRs9UxKOy+2rQLVokRu0auwhwoUrmK3mrM2I0+ReNk5eKdKQSfBjE6uP/oUCuZbYlMQjvJzOrxlA
Y8VAuJsZ9dZyVyy6UqaluypC/Ah3DJKizzafQB7j0L7dT/FDQM/IxuWvpywy963fGCF7yBo0I5v8
3j4QeRVN2Rcfl8tdoAeMl+UA83Df5k9ccVSHWEg07HmN+kdYprNuJGOgK21Zb0DtXeUKYPcuip5X
wzeZS70aTO2mjZClMq/JruSN/97kYg+8zXss6HQmY1vzKVYPqeBRXOQ37199Fn81/P5hEBpuWyqE
Bt3fsfYVD2s6Bh/0OPzCm/1i1AIdSNjNlAN0K04gSengA/bWEfQT7KddMPLrdgvkUwhLZVJgouYg
PvzdbcA4xcNRRyR5qzJQhZbzxEiF5VP/HeknOM8k/pyzsGmMC/aflg1DyEzCRfWnwnM2JYp1AXGu
mwyr8RQ6RqOpsE0bGLaAaK3Zf9tngpe3UiuMBkBCiYSnMrYl1GGLGCr6Q+hFEpLCYNF5iXy/MpzA
3S2OYqqpSG8PbCWZ/ZJ5Wgbmr9Eh/fDelNzeE2Dmfyjuy7oBkax0w85PTasEcNiGWolNUV2AGC/7
xiDCzZHY91O6kU9sVGIco3d4K6BcuvPxgnne7CHqIoCyiAX29XdRUaqGoDhpd7GbSH70FMcaROkd
tLx+7be6BOPSaSpiybnoscDyHiEoUaeRY8Ykm5WMFYV1XZZVbGDJ9MA8Pshh1TVqPRqvSTXE4fp5
RWJ2KVdAtDbOQW0OSe1gBWsIiNEoFrOebnUyq/VkQiOOSiA2dElai7WRlRrpIB81gnG7gI8Qo+A+
BDigF6/KuMgtdFWHjVSJIdOgfFo1Eog+susPa2BFWl4RP3MmYcPmxRIYWv/wLrLphubcTKVKbRVm
KNELe0FhfCRj4F4rOHO4GVP4jcUZl7J5qMGPfuRkCckakp8m79NadNzu/gnHSgxFSe/QnTqFtDZ3
TDZlBjb90MK+m8tC4hyNUG1M+1mtDYuBom2u0R7BRa6RD8Ksyv6OC61IyGdAmVbLKNer78rcSLaX
onmK5l0WL2BZdvzZ1sKZAkqCLDn1QwqNSmwJdL1Lum3FHJKQldxlTMIUhzkf7XkPfowaABvDGWuC
WUwroxnrQOi16i0brEUS4Yh8+yUydwPy3GSIh538wMWqGkd14t6lrAw2SL0KHWEAC2VhdLUV3Vp+
Xc/8IaO5rjGQ+/IsDNXQ1B7IRYm3UU1aN/cKm6lIyBubgetqFsds+zYigaUaxtE1Bj7PSTebAC94
nyeOY+hRF3hvmEtLqCRJCu3VH/8CWsYiu40UP/kerIVio5tDond2Xeo4cD/ZsSWUfZWC0gn2T8Lp
OFmkAY6HB9W/sfZHkxBHCYXvHaOVU0H7a41WnII4tZ6LhNegdmPxA7UGQH7JlPp19IWQMRAQPT7A
TEjkTherPvpjQO1Ty4ytQ1XtrlqhIyvTdldG96anhzm70W2Qe3xclNsW7HqcoZlBmiUghaRY2jOh
RvWNrrPycFkU+3dKJRsQxYbleJrzXm/saUW+KK6vJhmy673K7I3ko5qM+kTR09GoPk1Wdaz963tS
THHvm0jLsK7cgFIg5sCiMMdVyjDXIrROYXCLT/a8Kq7ouXOG3pEKCBXM/fqOQHpeBwLwjj/na4Y+
DT7SvHMPSRHY68xknnSZjZhO6X6L9D/Lw50XymwsKmGvKpg8hwMhwH1ovN8DVWmUfVcLY8RV5fPu
cvYrJ8G9XNy2d7u95sznubRil751Cp9pDSwVZ8JW/oOGxA4zkJB8iQ8eL6h5uwbhvB4u4auZ4NJX
1CPX1Ta1AtTIKhZUKloT5YjwKsNU2svZKlolI1K/g9yI5Azjfq6jUKz0VZ1rzK1rFtcRU95UXR13
bSVs0QDQtTkcwb2U6bmVrQDindiNJCJSVB01lkn7uVxnbFkwlucFZ4gJDKzhpKc4rmtfQ5tvLK87
c/pXijgEDoDb+V8jWAx3hvnFNXAL2PrMqiImcKRU9aEs8NvMzaaFdIESPU43ZPYLhmgibKNHTyRP
dw9BUv07GidQsWY5Jfz9BR1zlrdPdOyii97Z3U50q41ZCQzQBUZLMbSp4T2pzluN37YRGkXuIgvk
CdHSYUR1w6YAF9NpD2V6WFskVZw2U3TBMYZPPJo+lOZKXbtBFYiSuxEXmV/O1JreTfwY39qV8d5+
zG+SLmAcj/tw9eQS7fpcdQUKwtpvUS4yO56tsNObxnq/T99zU0ew04gN7cfTr8cAzYwAmZTcQyB9
Wp/J1Fa5BzKejIPZLdrtvjofqW7QOEX88IeSEJTabmLMksBHo9CY23hvoI4670G+PdVMc61TV7mu
t2+qfCoOrbFiqg7G/jwFGIB5Sx2pUTUqfa2UpJ/fJ6lnDzoY/+TboF32ovWfEHC31GoJL1EqmW+5
aWMq41HFe7vQq/sUvx26qPvSPXxGUgJbi0vaVN2axpvm+nz010BhG7dDQKIL/22Nis8rqb0qcBv8
VgVImfuY2RDDrQHvF8k3Wshklu472cSq8AF16izb0g+6dX8G/A/tl9pdehzkkF2WJrJJNzFMwUSy
Z6gf5jS+r4AW4q/jFvjRK30zyYwIWahHru0vC+VfdsPgmUw6CybX/uwcCkqfbSPqC34dmKHD6lpK
SsyFZSG1z5x6/J4QyWbB6GO9GrTykNXnI4LX50vbdR465MAYMgAc0PW+s1wd7KCMt6VYaIcQwlNB
Nh/oSXczkU75rcP0Ng6UyaS6dD+kv1IrX/4ym5lgO0Mq90fn8RMaIMHrh02KTOPin/UqcV/BLwb7
SGbJTEicfVwda/665scUTP+PomIgN4XDksEmd1lJ7QPPKRauOib4MPQJ2ADZcaCfbT3rfMYDqLuV
YuLS1AaWoMimrbe1t+SSfyjzlBnbD0xSadQ0HDe8Gy3yQ5iamTurznixXKXH+gOGX1kqVUOM6TIV
89feDfSSx0qfujK6lFBwmooJHDpdlhnr61u5N9nROjNI7Vj+zwhsQ+LYW133wuAYEUxfC21OY8E3
pEOJYeX3YpTIsnsZ/Sn0Ow9q9dIsdvL4W96BleBwE3G0p3WLyGYjgBRdV19LWYARQQQRkYxPOyBo
NcTlh5MOzHqcw0cgKpTXur5F3q5Tx1/SwIhwNTWoMOIv+XFjsovcGwSkfZTRHsb0STi2fOk5Pkpa
UdgDn061fUWEG5rTPv2Pi/IHzPXVGcGEHXSQaiJK4lhk1RNYfoLv7gSRPiaXXPeZo44PWZSseUjk
4pJTAUaZtvC8hR7/PchbsIG/8jZV/7bz6JkQ7Q6yy31lrsHXOhNFino9tLnleBZJjPERTW8M/Myh
DC/UlCjPwoWe/VdE0rizjYYVkEswn5CFXuvIzSnuhAD+yngs0e0NUK1lh2Cu8CS5rNO7E0J1JNZq
gnnS4OheJv36ODWV/H1PP0LJM4/x3BWdTNpewMjPAz93n+XoW02ZsTz+foYV8ur7ZQgOwAkNgMmn
wXv9CQvFIkyOTEDdeUMQw0UfxhWz+xBs4m2ffD6p2XARKB7E+osVd/WsQgXhYxOm8cEqn2z87tGk
LZ2X4rZPFtq9oXX7FV1wQwmnc0znfOzef9GA3xuuSebp5O3rmHho9+mfj5JNyKXlQBizcYAn2SQE
bPyWokHR5vlkdQMwmP1kWAYlf5qokDnir2lPWNIVu3sUSYqNNaqlGULrCau2/Eec55l5n1GwF3bf
Yb9aCEOWA5DRtLdqFNgdRctMIcFHxyOitXraVs8Bl9Xe4j+rlW/sakBPV90oQ8cVf0o35nLQF9kN
66Tuzrtcfu697MVteMVKcBas3ZTYte9ua8ryzbZ0w3sIMZ8IHjpjfVIZtidHFNX1tJhohcAcCRdj
vwF+zjD/6dgo55cZoNtoPxjMhrZ6+T83ArBK/UYPyX+Y+hTIrF1B80T2x63aeP7Rj5ENp7nDono1
Bf88Ly5cPgWuT6aR3bSsvS2VlB0Ay4Du7iHl3gB7PVSRfuwOPIsZo+P1K24UmyZdVgq6Mtad1RnG
EUUySbapAZJpfYzHdk9NJ8dU9fbdIjeU+JVM2totfpWMBY4zjfqLomOIC9XInObLBkoQ5W7qfpwo
W2U3/h2hnlK3COtSch+mH0VdsIfA80WkSdKFtXebZcqnxGucgNWIMu97Zq5tr1MmNomtLTOekkfr
pcyIyeygDJJ+RUwfV4gk7NNObJj84CGqasd5c0AGoJytttLQQRYj97vFyvQ3750uuNu6LultdMQ4
tl4WHtLsnysf7jyTfjuCmUGHOB3M57yGei/8C3eHMZaGabC+/vCMl1pJ9+pXW66iNk3qLiya3Gss
qH8dtw2wIOYRRZNAuD5p31gwV84i55q6RCXZmBOjwqtTFIEXn/w/SCChROaaCRVYjfBkqZ6JwS2U
xma72dRL1h7rF1hufkCF3EkdLALj4ByrYlQmM9c0tZCUHoVlrjGKg/n+TOmBfbyhS68naUvDehz8
rwnMDGSNG/pH2Gi4FXyBoFgz1A4rXInu5oG7jtBtBKZkKvMAtUC5MhM2afLKuZ8umxNI1CxYSbfd
MAM1uLqs6LSmWV4ENx/WbjkfZQJl96/ufYJ13E6aPgmn4oZ16VYl8HL3JU5+486nypD5ns0yzsEm
9T1FQUuj9+J8akJDHA8Ts/rhcpnxceb2OZ+TFq4UEV1UkWUIm+GCP0cFzf8A4ub5I+CYA6jxV+Ks
IU1UnCearq0xZAK6SWhiBs/ltjUX/Ac/oQ497t73oafmMieb9fWI3O6cHX1+nZpKRwQUtG1e2VKz
oKhcYgyYeGn7TzvD8KuE8bLjgaj7tyBM/Sd2U9dRtfUiov5q6qvLGnw8YJuvgfbqMKJZXlWVJBIB
7GJRtflfQs1Nr2tVEAylU0QnXKYubwxW+sjGg9/j8NOrDU6Uc5x4r3ZSuy21ts90PrxDS6Ug87C4
9WmfEs81lLMNAXXrYgbpA4ZoWVusEOrYzZNT1vAOICJtxOuRc5Qcn40jpezenTtAb9PvBtu3SkU4
MuAKi9GEjEDvbuhoQUp4QYlyJ6PxmuqKrnqeBm7gGHl6P5k3b24AH4rje9zGBeKRWawIiC40W+vQ
lDuiB4PgEzAKCj608jfcKq43IIcdB98ZpObTm7EVCy8FljuJal/U0R/pE0IPwHQJQrDZ8cTRsLRb
87RLMw==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 95536)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztB/h+4PvAs/N0XI0cN9OT8nV3gs0Dpd/RXDA4Vc3dmwziA
NwElhjRY3VJxDTskfz+mxWNFaf1+mPePrYVqlwPTMBAxpvGimC8dYYQqLJKeeN1ZgTT7hwUkM2z1
Qy84CcCZcArvoNTfBy0dkWCCscLO7FYjYdrltlJMSy8CDdjskSxeftCs1jkCE/tStmrqLGxjbT6f
C92mpUd5YCmVlDJSoyG1Rmk3H90KWuHUMBc4d/nTIqIeHq74s/5YZbg6Itq+omXbAlchsha/ae76
9FWmmOPV5pGgbO9pUb/MAoiGnE0LV3UxmCzxLGMR5z068+xQRaJogr8gIRx4YzXucEDuMm6kq+U/
DJ8q3+UroFofr/QazQtIkbprz4hnKB1pQ9WCRHlWqYPmrTOztTQ4ZG+pAcx0IYfnFhwKTspFW+7y
GVx0kYGoMrgq7RbxX18WgYUZLMUFfRe6xSzxKiK5kNCdSzOH1JhyEU9M4B2sCcF5xcT7K2tFVZhx
cOoGlhAsPEMuJPF65qYCcRfu6UC7PJuefitD/S7Rr62kMcVw6pREvkYzRs+qsbgNnfPabgzwOYLp
olR7zI8hlqAGIZzAnxQDewB8HIRF0Cgw+b9popHU1CVbEfrPyAP2H9rTagex/AtB726oU3NS/Hto
hL3uC69KGFYAENJTVq04Ff518xRZvbDhZk4t7/Zpna6SOSIzrODGUJSP0FvZZ09QlakBg3Wo50tY
pgmp4DoT7CrqwvHOwtpgiLSWvTFKDLrISVTMjwWznwzIhQ773VhYwUgBwfVumnYIA8G6jaBfBGLn
337ecvtYSoD2WCjY57N+HiWBgdUQDQ3NSmVXDdKaQQjU+G8lATwv+bAb0d2har2upRJoeMobJ656
sfolUjfmew0LyjHzcPgiiMXxmQ//k5PhQRSAt8ggHr1+QYtC5Fh8GgB8scvBnTUM1XAO6R+HNs1L
U27gBJbGILSvUpTBZUXNkyoi8+s03L5a+vlwiEGgNBCUxq83tbJM454XJo07BkuS08KsFVnKwFol
BUxHZ12vFrTlJEeYdgyh64SsThJH99ZA6uEJZTSV37DhOLcIz86Z/+PfhZiByqnY0gn+wYCvOaR9
ocdEJsAWit/14k2h20xNDsh7vHErwyFqka7Ply4vS69D1gzEs/cwndFSR1Rm4eG7Zx13Pb2eR91A
vsj2o/4d7k6a8tH+bI8oDZQ/Qik/iGzOxZd3OZ9GvU8W+nKFx374cVoWAVRDAULUwyeFSZ8E+i4q
dROg4VnjRV1scMxi2bcOCuRJbX6vzKu9ao2v6me0KWbJrYk6Pb9VqAXmSAuxX1soQOyX8RLsDiWu
87+V9QkKz3gnZoSnwvxHt1paDTyWjfL4QMWA7yN1HbAvNPVY1XzuiTaKKEsyf9tvN3B/JY124zWT
CwibACdVqWqVFnC6vA4TidGx3yPOC9UhqDqcnqK5yfS7XC/KBwTP61QDQmo+8oWydyiuC+/NKVvt
xxNgeNW5WZL+UPd4qQ4ztuHmm9pfbJYKiuOJ4PkE6fuWkYPIhlX5QNKRqmLlF3jI6g6q2jl/S9KF
osulJvpp9IreJsYUeJoAOUYKglzMoa4rbTolwNg1kaiUPo7l5mXLcK0SujbMFWWGBRaLCfleNqCt
zawyhYjxey/Hi6IAQNbpyV42kQw66RXAvkbnjvc1Q/4UJ5rUo3Y+BfUc/d6QtoQ/MM2DnzZSelhz
wuszJzcVPod7VaEeVJQoYhSX/X+K3VQKZs2qHjRAh3XGV9YuAF3++sWBmfFfgurXmByZIYDa8kG1
7ZqIxa03vBFzHPJOv6aVvwWhnLmhSlVPCIHJxHiCGClZqCwm4y91AzIrXc9bPQNFscMLSg18PeG+
DaO3k99xUA9pn0STbk95TsxkbAAjVNbWBxRf9UedMz2Sj3o8XoBTOQYO2J+U066n+tTbHFYav1rR
9+sxamPEgAx/m5VI7mTLxdi0W2dgRRA4XDWHFWifRPN1KzIxNPHcTykgw/Lm//RZxB8MPUoBtMTv
ZLGrbVtckg65yrTYytUXEVL0eEGX99q4F5ZD7HmggQj/TehQOqyJaeGRkF0iyLX3+6bJxTqZWTkM
E9InS3J5wzbPVE3Pnz95yL45bs7pjKcK5Wq97wYr2xOxkApeasVKwvVSnGdxZ3dD8J71KiH7xG4j
IiU8QzbswZSUR0PukpVOPr7GcqrqOww/EAwXmesEJh0iEamU/ApOkbw8VZz0DcNew0BtRSv4oJn0
YVzugB/ed+9BIWsevE4e4JWi9vIXmUBT/uxNTF4cIDVP8RoxUJyU49US+VYMX+h6zYO0wxW/e/3q
GGFfRTxrDEX4+kwKXlfTe0Ryfled6Hfe25WkbytJZsJO11a+oiZrrrxLilzx9YraiqOSOJ0leUdK
6f6LbYP28aPSZxITy7N37ClpKNEZAsfvjXjI+fU6WItoDfHlnRgUP8kk6pzNyr2cSv4Mlg8S7zvo
ctupzXJVB+2WWab3RwqY3O4WwctcKkE7Mu9IPJjczuTATT/gFi6qOIUy0IeuDBMu7yfxvapNVXUw
x/XHP7kpFa5xaFPZLGgEyZwXZaOFNJ8gpmEjnHVUV8Nhrix4J7xLYfZ6r0+AiYhRCMMbuV46k6ew
DJLx1p3eKNSDagcWjIFx0oFXKM1MYJkymZpAFr+eTGw2up4fXuKo/DLd7vUiZYlt18Xw78+btiEv
VZCl5PS6ecifRQUmuW7wUQLJ5xxXco2P9v96725mgey2TRdWYXLdZQ1V8zsnwpZhINsLIMM1wT2E
Z/4Jlan/b4Zsw+9yMPAEMlN26qzCpzctSH/z5OrlpY49tjCWSpkqPM1l1BpbaAbi5nfYEoXMFOeT
3jTzFbWQ2tmzc3FPkORk9SqZMGl0agAeyQagVZsLeL8FxdQFK3Y5MgwzIOVV9N4/ouRr9BMhJylB
pE47x6S6ncVe3PPCxE1R3CYSUJJWb14e6OnlbSfrR1jTCppWEFUstCgOAU8m+D5GCqWe8zdILdlj
YVMbKliRzjsBZYMiXuBCjZYpJ/hu4pdE+56Km5r72/sGlwpLh0Sp3qFx3/QY60or8+nqNxjRVqk6
9Pu3EvIRyKCuk1fExvo9V5Zs62RrE6CxOL0NpxrYwn7PSChgdL6XSH+DfuTLAaDxXlkaM7r3Sr5k
6FbBdl0Bn4I7rwYV1cA5kPU8rGxOt1WJao5O9kG/TbxPqNPdrG3ZlEwSzi7J4QWmqCjzjzewXt9X
zmletWZ+HZMYVcLf7BB0zap0EO5N0XBbpxu+e+h+OGrXmFH0vlVv6jXXgJVEZhVw/dV72W+J4QvQ
7N5/Y6Hr5kpPZZ01uoNwTFORiT/PwJLbPj2fBb5Gupszp4mlgz5O1srWhwUzJ4ykKwhtQ5tk3ftx
EncTUon2WC0cUTNxeAxJTSs9wFPwNskezNjJ0tnXdwNiJI8kUrRZ9oszqKoasW8PcDueaSwjb2PD
JavrQhmgEOCBAgCnkPTno9NGlcek7DcPaq6uhwb50gYY2l2UYPMAcfrREJFdP8i3XffmUArvDNEA
hAnZbc677LlBoxG39d509+AoCHpo8BYl1DjMsP2+nJqaY56Crq3mip+KpqU20a6GnkZtXvPh6DVO
YUd+d0dSZUBv5Jaf67F96NUK/ZHgjMitGyfJzi1QzZ58EBcqYFCtNnceVpAtoN4bL9dhrzCh0nHg
MIUuDgdLdZg56MsdvfuRWLF8b/1Vh+j0J0VBvAUlBNvU1cM2zvUBkKhgPplG/6+J4+BgY6F3zNs2
E8aTB3D8gLnt4PtbmDbg5tbe4C+2DVb86cTrTGw299kZM+ygqVuiJVLzkM3HoqyCTYi+CnYwTPK/
y/XPY2wobFm0hVk+oUY6bPKxJnrs78fSpKYCsvBkIpmD10jW/Nm01hhpmD0uM3axfPe/99ANehUH
7fpJUTnGpOTayowtnZOrndV6huw2x86n43VyZuL+FXzIcUPYKGIC33W3zZ5/zbGT9xlK1SpYxlnH
/ppFj9iNqzCviDzyau+llMtjcfT6n2bb4gi2xhl9FcFCC/+KvGdaUJbalCRsmC2nUFgVEASgt4y+
q992c+slBpmDw0taTdwawRL5BBzSYHPcW+59Vk5z3x6WPcpKOwhK9wp+yXxcID2zXmFeLpldmL0I
Y4vWB0IFu1Uo65b3V6dmSVgMHCaGvZQ6MJvS80iCf2/oDacpLNOZkqa3DFC4XV0NkQD2EHqS1Bd7
Noj7ZW4mBzeMessx5D/91heXx/RqOy7/pl+B0XfW5qN+QxiwZWFDjCF/5T8+qXxlUdetQuYt43Qt
AdGhtGnd35GYO2bFGES0k7Da0FhfXhFYvkTTKxxDOSQe+uo9iYZmrRVQdW8iYJbqjDWytxfXX0Kx
3y9tB1FTg4/oSo1meuQSvqFourhD62tW0W8CfImuVnMpmgx803NJ/ftSoVsfVaWsKjyLWxWfRl+r
/c9DfsPalq2CZJWdnxy7Co4PtLr1oeDoO6Fh9j7ij5BvsJqhp2dD2Q1Pp4jdcY7GRfx/s6qpYfjF
Qe+EpssNScsqF1DpODQxSWFlVnlkK+s/JobFp+IjSWFUKJ93ppkLcDIzymZQ1YKHLaJLD99JgfYX
RLXBjcqlicOhUntYoWbOq62SvBwrM3+r2JSKS1zfoCW7diS5rKJDairlH6b07Df6sARnHgdtyvvs
wzoA8/6IMp5M/54p1AUnVhHKh8oE9i6raHwMjr4vLijAGWPMOcBYj2eRL3nf8yEzeQu8XrFwSdnp
9soB6+nAGNVBfaYMJRgoINTHd/t80sdsnt0dnc7OfHM1iNWo/XxkeQLX1Z1xYKIz2XxkTQbfjTUE
xV+7BFWCJoboXsmxldrKomYpXCq6iDGhc4m3/x5J7mxNJkFWobhHchcGgjsed5wcsPCJtD3o/Qkf
mPnoh+6FPdiK/pHCChdbGItAyYAMzuGs9moowM0jahLcRGlgQSQbRtUc17x3Jt/JPcj59ROJM9iQ
aToEB1fFa5ALLIMO990eT5C8x/f0txA4cFc+gSDKCpOxA8DgX+Cn1tSto/VVhjpNE3vhpRdWgKDT
QCBO32bUWpGpNSZ2mALB79qTAf1gtX4oS4PW/yqjNkA7vJZ5W1Ep7LbaHT5Kd6K1KvFZ7K4zsCnD
bZB1asu0sCnXOGy4tGDNDu87/W9YKynMVtEDan1nNPZh2MnYo1+0HGnKETiQCPsk9SD0uhlPfGET
GzUd30zy2VdFsYvHIZyc/oc5ShZvVko9KdUkQ2wbUIH1VCvkk01EaWm7JrAVbpno3YzlDMAxcTFY
4iPcZJm/Q6fBXllaUXtqMfKn/cLnJTu8UPqveOFrYWbW++8K15jKnYwmwBFiM8u7V28cWF3vGiPX
JpR1mIcHPRnp7ywMrNWwxxz+LOcaLd0BDeaKUHmmd1mcr9QXopzJ9u0Is+EG6+Y+XqaElZzev470
SbvcF+pk1F9KhDjfJ09zIAdaAa18yWpo2n920VijmiK2Rntt/OXM3MA1/RLDKQWGd1E1akKmHZCQ
2f4+jnSPliZZl/6HNYXqLkaKU3oDEnHZEpIUZDWxPr4ABMHG4vDQHEM+4TRgbvC4eeIX9WdFj3V7
9JQ4FI/fTQtLGMHL3JO/PbRYkcJaCbLayzHV0XRRyrf9H1f293w6M6ssFbExIOMRmgFGwJDsURJb
FMvIjbQhgOCeKxQLnZ0+NHGpU2NmPTnPchyDzCA1H1/b+ZYRr7+gyTXbpvU7eC7ZMZJ2XRpVL012
oAMm+Ap+Oid5SwtFA7qpEsaHLlR/Wex9JmnUFKAj4Do2xCvHIm7+BXkOzQjzXNWYxFGZrU+xtA8B
cCpO4uRc56S2eDWb0JoXv0SKypg/JR99YVnETpC9ZFbb0odtnyYL9Lt+MB3YtqHFsamqAvpmUSJo
gpOupM24T7ED4SU7H5kcB4v3jLQ49hZEOTgafERRw3hazIZktU6bZqJHU8WeC4qMBJZ3OJ0S5wiJ
4sT1FewY4C+E8itTd80OUhYMa/5nUbBozYxNnBheUDfF1L/kfSUnXQstIpO9BTGF30LOPsxEoHrS
TKbn8sSq7YWKdUgNBFNFr7aBhrCkymIvB9YHF5ZDGvJ0zBLAeK5vC59vIKbjx3sO7YVubeSKs6Pv
K53T+7qkHuPULU8r6TksEIfIQwPf0P5WFf9LGqAxv+w5THHUMpAxc978FW0xJ+ATe7ey+rwWmvXi
EepaB1EwshLp45w2tYNzZoNEWKapASif/ojS2VCO8kuw1rLY1obQ9HVA6xPadqu48FBPHQ+74tuK
wOY37WuuyKxSp9ipLLYPtUem0F4B9H5QIGQoY056nz1XffujAGuqtlHOu/VU/egDi7ksi3T848K6
afVhRJVHwyROsV5zaIQgO7j7rOOJxjXj0AL7J6eTOyZQSfpg+lyY/5JL3OA3n67CyAaJPle8F2//
yXF1TMnDWGiz+LJ4/tpKAB+ep7+25zmewAzueWctvyDd81E/+vel/qf1DchiMed6N+zOnmr03lAW
/jH9UKkeDdz0B46MBKOJF3iHsGkeR9XNtMP7NsrBZx+GQSmbOKXxtRROPJZQnnh9TAgyfmvubEN2
oTdk+AYIOtJPiNDnb3/ShalJJowuygg2dCMgfPcFUWWJxYRGhfx1NK2pHz4G6MYl3FjqFI58V5Yu
P2jjlmTfiJM5gsFIMNm2fXyGp/3p/PIDACDrSqDTfza2lc6HsJyStW5rX0XjcMAazq3s0X7UGK35
njjab0JAtar2KvLn7iRtuSVpOHX5TVjSqVVZGLzTz55zM5rqgFmwRK7b1PGwxswDHKU46yj89va+
M72ncoJecdz14w9WaKoTOQSvkijxIYE9PUaSodR/URjiys7WRHYmMatapl/IrM366IouVihpw0gE
29Tqb6mKcaZDuCCkhpvjBlLz575PFUN2A/J/RwlRhTm7R/5cjoT+bZrLVuCdcr+pGea4K7U4LFEk
OW/Wd+DXpuSaOzO8zAttgjTxwnxuiY5yNn0nfCPigCczr2eG5zjBKRjapq5tKn59IX+Fy93RxHHd
niuH8uTMAyBxo3V1e6+6O4Qb3WsEiwGKM4KdCsLvMMOsLu1rQ9FUpJv/OuRdxyH8QleUiMl74kEx
Rdq//sCW5pWbKFrcNTDOzBCOEtzvwiu+ppCwDL3A5GBzzqSlS7Tj1F2nn7pYYQBFRSRVwS0c5Y2Y
xxWfniwfrPuP27l4JewCuzwmIKgAhAnVy5UOf7GTQzksgZrI4VTOXg74GzT8hUv6YYSekgJsLrdT
ADdqiVgdtysoOn0TarcxZemh60uYUE0Mz+X3d7CmPi+PV1oCpAjEgcZC//at+lTlksptnpW4w6Zl
geD1tbQWyTqm9051zQf4tqKTpqlOu9tadafn5+vmnICIty9v02HBRyOZ2uK+vIOEtGCKF78KEmhT
cX4+R2FpikbT6ELjUAR+Wr8nQbFSCirAhNWKx6lFhXLrPX58FL0/fr6iM5BG08HFIHdG1Ofy78Hr
T+khaBwOSxE1E7++jao/IfrYlC7Bj+PijA5ivaC4nBEJVvvBPcouiwTwyh3rO/fsV9BfSsN44Q89
uX8CsJA5/TF9O49W6PQ0+g0WNcC9hHYgqSnKpGF0AQzimofBQc3g0M2DS4+TUDCVQmAJxsIEc7S9
JG2YnesYAaLnR4cUUWcj2FxqFkUNCgEBJRKpjWPZmDbTDgwfRZx0H9NWUzksG4buj1ULbeP7/eCy
4QihsOnTftd6jV/1KZHhvqMKaMt2lkBqBnz9OPH8l+8i/1tscn7JjuFm0B2hlPeEln3ve8PTui0v
O1xoNfnmcvOYS1zXTEsMo946kMiP+XDahoVHYvR29Hz0lkm0dKsNqsIA7Fjh8dB3pMBQ3GPvxQht
1F5DhTR8jFQF15PXinIGZPg6VVjOOQlkA/0AzmC6RQwLvaLEB1ClayDzl3JNs3JR/I38ys2DtHas
KlTJUmJwSKpk20eOu0zG4QM1X10HoxmER4BThMGhF9XfzVetBzNpiDxcY5rypE93ly+JaMxL/YnI
er1AhHiOp+v9PL5+NZ5Irv+biqp1na/tAp+CroxH7jUiq/PkUtq8iajsIyI6x1jlE8QdLgqO21CQ
eAlW0oQd+z43dsOMBX4l9No69p0x5G74X+GtUwAX3QaWvogBeyT8qcPECATrLU66fZFTdW1mGydz
X7spXsQ9VrwMCAoEWk1eHyt/+W7lbd4+5o8o7kSI7V53f9MvWgE5essO4oaw2ODv9qrGsgM5JyVJ
54ZojqFg/b4rxWr9sxkfNeBf/LEPdG815RL/iy9yeZ+yqXxVoWyuV2WsUuFBNkiv0CDOtebdN2qC
PffE9o82SoaKCSilxjcKzfkHobBOOpulHY80AYxraMcq20BpaCpwVXcgkR99bdQcCJsQUhLY9/GW
aMAwob4oKVJ5ZQgMi5uLmP9KL2qSGZkYi/7tyPcsf7mJmDeSxp1GWzQX8E8ZjLtVsd+8Q1/NSRdl
rwypTMi0Cq4Lmu7KuI4P2BB2NHb9Rp0g171FEZwowk1IDQzj9OSqSxmuMrbwnHdMLky6q7FePkUS
+jkeOoXds+5L2mnTMSRsQEeFnCh+mAh3Gjh3JiHcUbSYHwXj9vDM7IvVH2432cDCUAeUnEMZe9BO
OVpC527TtY6WVxAgx2nIrdP5ocF4AFSFvjvGbVRXsBLie+/7wR3dpES4ekCj3PxlQzkU0SU52ega
BdPdlXwQH87nsro92CPzn7BUTmD0RhhSQIcw/ib/4XCo0LiDhBv9Yi8OmrEPgmFWPUB5agMU2fzb
RKYYoYKyXzh7WVEZF7C2R7ZV4XoPgBWa2e3DH2ShHLvFIYaEmmSB/YGkUCcYwEub9m40ly7Wfczs
GpxXHjKvx/U8wBjxvWCZ7FwSYQ/GWDYZGEbw6CJZyX+Y87fCiMdQqsXGLT7AJQufSy8XHvXlPnFA
p+9/v00bZhuRsskGcDf5NhEvaNdpQ54yUTmm8/j07XtybWTqTH13VCxgofciS+MVMx4sO1XJNMd5
Oq/bN0Fh1v2WMCRgTWBGCIGhbqMw/qv2O6UJPOUGtNk8qUCOtBxG8N6m6z14uk+qCzgQFv3zRm6U
017WWQxFl7OlKHe9iwCoRfXoyz4xpq2mWBoAzshnXfzGbBHMvDF/wh0gpcDPqB0iz3VeowRMqEHp
DxXfj17pWu/bFcH+dgWfIQMHwKfYL+6NdCSMgDBFadU0/lUm1CDzfrLa/NwNrBBpJTteKSPKi5sr
xMIK+T6OLB3+jlYBH1d5fjCY8KuUdV6PKCa0FWKOQbN1rByH4vWfFn9YI2vpqemVkNKlWxtw98t3
7YTmA++q9jiA0Y11M4BeLeI7KpVoZf6HglC7ohm3wiczIXAHPljhvVifkz/P0qE6EjTkTBtopYrf
mXeOcjkwpVSMNc3WmZViUiqDsyCdpkMZms+uJ5EqnA9Gtsg8OlyF4DgbaZhqfiffd5yx0UDRVAfv
nxGDfsP3Zdl8jLWG/4n8l/qaGZEhYhoPgFo0fYBs5Hkjp8JRO0t5WFQYdc7/YEhOvYxOCy8T2wOL
+rmoF9E3WWxuCDoIimuXfR2e3mdottzPBYpEu/lU6cqYnL+GLgj9//BFDj191Qb4EAobWzWIFMxX
WyqP1VvvhD8tBwpS07T6LnLV1W6FNjLDYFRFM/3a9c+6DcbGVgu/CaoU0V3W59W8PLgbgRP0H9H7
59xG9vn+JF6KVTemFMnaITTvfeM64HG4Kda0MQ0oItadwlwUuERJmu8nEtC4lHbxMt7h4LUQPkao
cHuVD9NJcuZ1rUWDah/RHB4cuow50hNjJOcxzcKez4u+02lmrx8cOlATOX2ulxG+R4L+EXmYP0GA
HyyCznR9Mjj137uWaYw2NwZ+MBcQuUlbIH2+ghW/NDL1CsnCF7HEwzdyTSBfKNLvouJuwSBksCy1
YQFzs+CwFBHX0+ZtkWBNRPqt/LhLLE/IFbR7L9J5Y+PaVmKrccVwlG6xp5NRMtewV0s4YL/ZTtHK
wjwCeV6zUiP7GjvU034OQwq21A7Ji+kTq8IXQFi+4OC5eE8g2wlftMLeP8MouoUjzqEcMRfxXXLE
xuvDuJedd1PYad79B+7Nf3r9wIH9BY6DAqiaV++QY4n2NVQo8Q2+E44vu5YVMolrgKSq+P1vW+17
JPjb23Dfi0czi7NPrN8JtHStk+QiQdZd0LjT6lVaSCmdI/Ag64PsANMCUvXqzuWHBv0BZkP2G1Qu
ea0eatg4Y/pudRt91Lusr2wHqLekSoIh6EXQzZWcY28O1W1PaE0FTPJ4aa1APknMcG2XrORCNHet
WnDE8a8vGidAe+fjWr/YexFGVYcyHud84wjEXZtYo3ZpGTdg5FplBM0bZqmbxOD0qqog+Df6e3LE
SH0BMCF9I+tMEO7I4rbcjw2cy8dzJuJQFDLI8Xavy+lU6FrkKRWNZjn7rwzZPkBNAsWkXK+Vo2MM
u/V30eXNhkCSnluY4kWdI9+ZAfeZyF/lJ0yVhUJJuY5z8KkD4O+w7wx4iVwLo+kJ+y9KVYkPm0sz
6/CLq+zdlqnkWPkqzuD+ZLQYs2FcRgcBbOd22ssoqOiM9E2MKxWGz8oNpXSQSeIS2RnO99COFBk3
FgwnITLdkaTpSa9R9J5gTwl5OlKDbitvZ/c3L9X5KnRj6x8BDKEtCOUzSH52dJxde7WZcBcJ4RWU
9Z9uuRaQYiDvAjYcQDFeMHtxsdaashYCp5J8HuLkXgB7GLGPKEmsXpUcn95GWavBX6d64jWQtv2O
JUfm1AdqsKL5CqGc9MSSl2mJiB6FhTkipc4NcognZup9LetL7eTaBwsFB7anGaPkQa78AgF7/HbQ
pRtl1jz3q5M5XccdiH9whn+ktL8iWXxRJmho4W+GfQkhrb0pCgjGvC3HMzGxJhPwDIe12kY3a7Zk
mO9hipTjbu8P4kmDQzvYQW+yXJKLgb9blX+SNyA3EUcEpDBzBQvtsH8NJ5RBsEfa7YZB3thUQJQg
csqAGoqHpP2rrUA8GFfNcB40v0BJauwvLrWl/96Z4LokYuAuXnfzQ2EA7pUvmVnf/bojv07qmizn
bIuSl6f4gPDJCCn2BDPJXhFJqFOjSYnWJdnvLauyqOZXMSRhfX33dTmILR6B8l8U+dVSrjDNPgG4
MxZg4hyDdYI1dxlKbAM+GCIN0nfxc0VYCBSC/c6B4/S99AqH6ECw/rHcWnKQHTe8O9KLvUz2LRfG
qLJK4tXxtknGVpqURD+Zmkic+mUwlYNwS3cxIOj0vR1B5RGELLVrwqf60f31TjCUMvRuuK5zrqr5
sQiVFkxkHZEd6IL7k1uX7PGzURaXHNJZAeO0J0iFbUrIivzZKVzOAYdr+WIB7XNF8PcyKHjuR32c
P1xIX65iIFPV+fqreLuGiUknt5rjofjjE8CN/A7yk9LUjptaRJT+Yg1VTwYfK4Ea/+oq7XtvmCTQ
Ch+Q7aw2rgMdw6rqmXwZwd1s00ro5RoE3uDn1RfTITdvEnzA0pq5G7Vi/t01sypXWtK6YuKx9hx2
YEbN0FZOITCdYyhv8epXrM081X1m5TURm46Uipe6HN0gheY9yu0Jr05CMhlSBisqqC7GuL0PaNLQ
IvMO7tfv6W7K8o6QYzK7/jy9LoC4XObLmWctsLRjBp43XRxOGkkrzQbcp1egIQtZHRZmywM7Vo0G
SqiYRP5hFjKfPO0vzN+lY12M0BQqSssj6MJAR85Jc/TtjXNpoR69NiD1JsSZosUi5iGj3lMTvw9o
NOlQIS6SdhvfJT5bebbpq1BNV1Q7pW21jky9my+vi6DXxyBfN8GBsoNeJuKy6FZFQbhyWNZSKegL
HKtEU/j8cSXEYeay7ZBBMUjr6B5Qfab+4ZawIoTbdFDJIJHF1iq+/UX6f6ubszhxRD/C8PgoFneq
ywtNsVsMAq3yuzIjVnHz7YECgy+m9RrEX0+7TtnA065G7wXCmurdOD002QuiBB2PoQJO2PnU3JnR
YYYaVfvvdGtiuJtymvW8cR5SY0BNB0UZC1ctY5YEMbCUAZNsLD/Ac4Va0iTiMA390XrINPp9PRA0
QRQ2BepR3rrbVTGmaqXMvDknGZ7pM2GVn3YNTdtcr7WMjOKv1+wOCtHdW7J1HicKNSJof3qN/YWQ
K3PzLzd+m/yNqRtz9zguRW5jhoiSzLfYFQITcED7NJAUQ9PCsQW7yAPzwUI1noeHUu5n0mWw8Io0
9jaDcg6VrtlcYMlREcGRjFJTFrucgDqwmYucwyT+CWGZp2R9rO6s9429d9IfVwTXJp+WFd7AS91o
jxWXzY5iIKjI6K292dJYoWFnmPN3duRdWa55ALezeowDBeMUk3j6B5B6pbj8L2AqIu689QYY8Z3Z
ofdaVS0NdSfXp3M2AFOcJ2Z8vq7qBWGflZYqVRC+UiAx+C5VTiapu79WXsjsPJSVzOPmpeGEGymE
okQ2azg9EaTHDqxkj/ZZwCFF1Ky2EUb0DNHOy6iTNp//5YBDgrHXWmDO1GNUQVlwf/K4xHIT6eJK
l/IiZ/Xe/cauv7n9NA1h43ZLRcRpFPjH8Y7eWncgOsQ0y6IqUdMQU+weo0nsOsV7oDd4vzf7CLrb
x1eugr1d0K2577CWnfqjA/Z890gmnrHZV8Q4gHTybwH+ux1nXq67J/QptDzg0n+m2XfCBROc7u4u
AJcm253a1ZdHD3nGV8dW2cgmw4o70t2y4yDy8MdhtstsLIVzBMJQrzRIxGykb2+sCFFcBLCpjAXH
bRfNBW6YfbfeO/W410LqEGkXtYphoB2XFPpsDw7ujy1+alnJ1gZPmessMdh5JteCLST7qXk9qpPE
WgKFuN0RIrrjpOAyZsOnLXqslB2qWBoRDiUtanoM1cHC0jEfDOBub0QN/9yVNO+x4hSC9+dvkH3X
hXlhVt3VmBfxAew5OWYwTEVaL3XCbuvp0wf0qTiK+j4FV7TBwxh74Lwfr80R9Dy1DDZ3ZnLX7OKN
G0Dw/f57NgWVcW03pDzQL9x+BUbEwIep3ANwzdROXWQcLZNGI/u/RDbA+qYqbl6CITAEqoESv35b
SCb/fp9dSp6H3oWYkcoX7X0EM/4lcRD+FF6902xyEDkQ3hdSpf5jHF+okafmXtOwdEcQrZY2nUIt
kLFTlriZ8axCnPj9lnoX0quERFQ4rmZMuBQyn/XZi+hhiblmeNz6pf60dPdzSYNqpuMHz2O4T0XO
Xd9gUrmyGndNKePb9jTY4yHnkyyegIplJeibFvFcMfCe2fuy4dK3+VjvH0C9PeHWUZGOn7noGT7L
8Cbegb0cv1PpV2E/yQNe1KpiY1IQZCu/nIv3uRpdNi0dlTIDs9Y3bya4xOeWhZQKwFJ3pAs01BRT
tlfgOyRkI6u7Vwrm2w/mEmOBli1HY3BDE5Hoyr2mr0GCxoBYVMLJZskeP4N3wER+jbIxHnu/A/dG
V3/iVT9shoKQzD77FqqGKuKxKAQjytefetnfPFZ6uZ2l/bWTU2mdCUGAlBLO2RKCjLHZthJjDuK1
LRO2AfxsCI57idVVcZIO8ESjFd77xQLkF6SGxvctCShdOTx8x++Ks4WFzJiMZaSTKl3MoSu4oFpq
4yWXpxCdTr7njznr96YNPLMnh85ENDod5Umc2dZHQdN6uHl2ygkxQQbvQ32AwL8WgcNRlIHfmwoI
TT8r0iYOIA/7baedkWVD6zeFBSqmxwcIqV4XgoidAR7LQs2jWKqJkqKKrPaey87DTyAOYVZFof/R
iiUUuFZWugr4d4MxxQAFrfbHzsqIGCJzhMSx1tLw5qqYWc6RFU5Oj0T7mxqztoDyNzah2eycBjam
LRog5XmaEL4doJDEiuboxnV85qElBk7yXMWLna4unRIAb+B9GrwZAMw0r27DdKjkb30RgMWPYyES
7mR/aaPKkrS356tD186vUPsBaM8kAHuV5vu10jBNCqi2drGjHjqNb4QsMsSXFJ4G1ziiKrQ6XTqT
XbisxDzNGxbM1KEjANG87/PLzHM2WCX5tzLwLX5CYj5Hv905an+K27tMzHj20xbe2ZmuJyobjjco
QbV0nJF/boxcJV8S3d+g8lS+ZhNBVp/szLMVfcoFyI3pUvstUiHJqZhmQfaSMZZgDAMreMa+2fkh
wj+Bv+xIg3RxeNIDX1z0SOYMdY35p9V4B4l7giji5RC9JmLvIHCzpDDL9T+Rak21uxeqE+f1Tuez
L6qmg451FDGGjbDiO4Xw19wWpJhL5Ngb0OVUIZcXpRWoZSvPzy5M/N+mBD7hednKcUee4ccim03U
0t2/Sp3DhFxkUf19m8PgjG48ScmNUBYCtnGVjP+QSVd/l6z9MLy6rDuIgJqu8lBjOu8FXnfvviHb
bvQVC4On3v6r9dz+SAymle622X5n4ZVfJKJz3tZnqdxyv68kck2PAf3cqLtfILzPd2u3ifvtn5Mj
DfTDeEeoG5OUBWD3ipre8R7Ekh5Ipn/IkuTcCzeNftm8iZfi/we+H+VC+PJdUc/tVPM9oxeDf5ph
zze8ZKuz0LXFJhqU5F/4CxH3i6q7mm61JjjUGb10RgQ2eJweaxR81eARI7OUwNJhqKHnk2g0lLlW
2i2ggKUi5MNbPSBX2PpaBveHXgX1sFXlKQqS6bfaWoa5SVADwAoFLrrmaVlzKvYhIcNPsCKKxJ/a
AqAtqS2IW8TPHnWJq9DF15N2EFGcaSJS83crcG0yQrsBe/sb9PxMv3WMH7TXgak77HxBoXP/QN3r
1u6c/tLSbp8JgmHfSSrRxeAgVLUh6SJy8mUqjbb/FZXLY/laoSYOCEvV9ZaOrk7QFsY8dqQJ7I5K
hB7HRrQYpgD3zcvcFiugtLP6p1EER5fJXWb3hPBFH56hKP0cD8GO3/TKgW31KLkyGByrN4Eae5F5
xUhQrKRN/RiwmwJzcG/rOjtci8aUH8JbR6fhxs3/EB7ndoJmC4odaG/43KNXIunlSYqgFIFrj8UL
jhacJwpk+VP2WA7/3ym703OXA7b1XmKdoSie7sX92LUhrgGGHk9Qeu7vn1tiBYCfK2Mt5WWnRCnn
+TPEN0RB/kSWgLPwz+5/rrLdNIcNQvb1GsGYnZv13j77u3jozl54S7yOX5cYZ/dJLhvasBb4LnIt
S7qObJR5xuXgRe6vCNGFlt3lqeoBoft+6EUCVFbBpeWm0qtZioS6l7KDmO3sPtMqZrWPPXp0xkSB
6RdXc81lfkMPciwxLgTFOez1Rbk3n3xUz8fAZGTaac76Ty3qqJVo37fwdGORDxQcyfLrCq4Nd6CP
8eALqcd1aSeJneV8uz06IcM35b0uFSL+WeQhTl5kdZAidKEcWtqkLa7dAcn/kDiG1kCcGmvGHfXa
qn1irjO9qhyO4CFY9s0nhe6/ksILBE6Z1quldWkTOG5DEdSyGFwVbM9GrFPgDgCUNezQiEhSHtYE
LiexJy9/HcUjg0YnUBsFgi0C+SKKzNT+o05GL2vJTD2tcuBlsYNddciBtr3aEHu+AYc6cZb8QTER
q9F7WXcZxWkR7AlktPochgdBrRUw9ZVfhdZHooGufJIbmNsRoXJ/32D9crK9dV8WYtry8PQ9amwL
NbEiYqd364+SCg6UqvHVw4u+QULqXq5jBERGKHcypm7czYPSL79KAzFdgVJFKJPCYvys4jHkbvQ0
7/KKvTwYY4nDkj+oDpsd7jhtA+Y4/bHcWf3CtXlvc9Hmm9OyOUv/6q8Noo+wPUxp3wjKA+xYiasT
fvepHfhPXUjFCDc2OYV/XA7CJnaoDag2POozp9ieok2OV0io2+j4WlYzMRT3YP7TrcUhv/4d818g
qkoO+VK7R4AWi1KTGpXsxAGK5Mk7D78d5hutfgGANT/WLYbShz2C4iy/LnJQPrhQxn9ovXkkwNCI
Glh9J0RZcV8o5e61W4xA79q03Zyw62LElDj/w67F22WeFbezMFrIT5JfKZsZd3DtIyrrslINdkoT
RV6hjgKROquC1vdpL1ZvvDiXbwQGWWjhYCWl3AoISvV72vxOyViceZW9p9eA4Fahu+p3rovuxPvl
SJ0LX0tOduZXw4r50nw4GsWijnpvVOtagdK19x0EEOxo1Lm0v84Qfgp+bamVmL2WGuc8MQ9Od3fa
yRWl/eZBLLqbsPT+BegFmyST6uDZNlkXpKCKL5SgOUKGD8g7Rz6so7i3djobhGWSlLkF9IdfQvfM
TlRsgF9GNvm622P7oafqzVkmSnGnc5OlQRWCPuyvhznoVvXrBU4FNliyB9WkAsQBTOWOxzgtH+jk
Kwlh+6ZYkDDQxuScWaX+cwQY+Tie55ati38u92QDnjhbt1WRfrla+Nl1SHn6m8MpUdqZ+zBL5A4v
e6WfvQcGpo1hFsiue0bwaRM69/8JnAg2pJPgQLuTklwmVXEuLf3p2ZgeNTrmAK/varOnuqkSg1k5
nfjKmUBaJBhFqHH0m4jrX0HFqiQFt8d9vcDFTM8plQeIY2u+S3UHIIeXhTH4xmvWWTo86zPJYY9F
VSb83LM1DDQUZH2G7Ei4bBRJr31tszLdzBX0aVMkdoyPIDoF1Ti36hxbij1O4z/femuvtjYMRXcT
F8XWzmraun5bau0YDtTolverTX1I9QXp7rX7wIl9A/ukg+6nJyGZAf8lMx8ygha4CO+SvP9U071J
ffE3Qdw60RgMINeYAegmAX8X3Eq19fs1r4/LJwa+RFCXRIw5teuDXIhenoFULdSKli4BT0DuPmiA
zVqI5D1+MboPitJQp2aWbpN25+gDGAULsDc786te4qw0+NcSUnqAqX9X7K7r7iSMtOPigPB3xXSi
LoPnagE6C770mM0okHieTZEA5OorsKU0+dhgPQXr31cc/yorByhjaTWmEFwLqY8g3Qug9LksD9+Z
2eEUkwjrR7q03nqpURquplM84th+7LdL1ac3PstmG230MNvWoCVXWu2Ttt/sKtzuk71KDFKH/Qtu
W13L3RO5O8Zd9AKsGGQsRJS6QebFhMb6qry1v9XWKaWfAQhC1D0A1TWWcnNaM/yQXf1TNxmzJm5U
ow/RvCduLwPt/Ax3RxDgGnIzBgr9CKVFjY2m9nJOFWZBtRrPAWtly3coyMcAM5uCbD9wn7DwDjbL
Byxg7J+yzg4qGP5Xs9Q/bpf4NvfoGZWgIPUbGm7Jo4JUvgmlDO89fZMR98Iznb4UIJNlcBkWZbCm
asmRTq3OFKMWzrZof8FYYI/IpzN3gTkJXkTVlWysbCNIoGMYCjDQs/AdmaF815MTOdnMvmXbh+Fc
ETXS5M0PSLdvkESbUpBP4FTMVZ0Y+fT8qpMDpxw9/Bjglxucl9IoTjezNfaYnvw8EJpERHem/ZNI
BXJybuy+BOmZS6Bue8kU7McvHm2BVed4IVhJreY1yawpggPmLj2X6RhXpC58fFRM7L4iN6LYkHFG
NNlFq2oGqiW7hp9JeD6i2BWwbJHAGPs348z5yn3wTxCqdcuGc/WzBINAs6VYY8qzZVdKQmfj5QM/
MnAwofN+QLWLlKbTYXmSdUW68AUp4lDnQFpgMpGPjKhM0B+YVzhNWhD54ByAssV3KU6eV8xaAk0G
8hzTmTEqiHjhSZIQBfez2hWop/aAhqWNLXqCLolQCQiP2hFJEcHeYwaS8coqQtJA5XQISimlBoWE
PMTeiogxyLM4OrZLz2WWyxQPr0ASEgBApawrlXmqo4RjkOqZO6kUYI84PCyqoxZz8xgAGkJ8mC6d
mITN96leA3ZLUz1ZivhAaAQu6wIvKav1k8fvVLAb2LC+5ZPqzZ3F+W3+n5at4iacUj+rImeRX9ky
4kHCWQnrBTuUL6kPCUPwbCGu1ZAlGPWE4lA8q7Lqb+d2+YNP/d/tZX4EhKOGXnZ/YbQITo5ehLU0
Ogu9PQK+gaNzABJ4tzWyzskESKfcb7pAenjAT3jMqJ3FQKm3lGdnsIPsyOwvBPmlG/k8orjGxRGo
Y1hQnS7RUz4wU3g5edgWBxXpJz+IMQZf5sMAJHSKHMZcPNhH57l3vO162ZURVJjzuBMjZ/AAl4U5
nEBa/6vh0C5f5a2o/1ZoTHk2gv2Izr4WyrRKUHIO76/C4H63JIrJiWHv+/K/lKXk+2Y0snXyeAYj
NqGa9Zo3goEbnf71kIvIsWTHW6mYxFD5qhzXXEMY6pPo3+QrMC5M0XQ+44O2v0C60RNhLCKib+qP
teFLxSdGXdtGWsBjlppRYKBriEBA2DjXamxVMFmtlG8hXQ+O3xirfZavSO/I21Kj0UyL/WaAFfW/
IUp4wk8J97pZLq9gvk0BjeOqCpXEhoMaco3L59ViwAjahDbTQOPSvWxQhaLQ14qXv0cVxuwf3aJM
6YvKpRL7xEeJMIyiiEh0AjUVk+ZfEeOTFXRmzPAv+l5m/hz0DFYAyh994gxzVeRqv/2y/SUobsB+
JYYyZaNviBTdvxw45TMs1tmADAQFulU3GIOW3XahXH/G6HlLlq9xSBAXUIj0O78F6nt9X88pr45o
75g1aqDooeplNaUHMwzcS05WxMHt/ohYXuyvHRqZhynnFgSBv5W06qBJqt2o03JTh5HAxPNOUS0M
t4WliZ7z1rSnQ7m88yG3nc/BdGEQR2Wo8219Tn/B4HEQWm74PChGCVNjpIT+ACUxgHf2W2MRcs4s
BcWhgNtAPcvqSHMeo8NE4n46Jy1sg3LxU5bJPb7w70Y5RzZ0EEV/tyUw2NIlGYZ5cKFwt3HVJycq
Jw7jt3kP3E5nxtqb43uYz/5mSxZInBBTIa8rhLgCAognLSnQSl+vC8uiDDh/gMDOldbbsCTrU1EY
y6E8MciYYgVaHFUjx7z1whjA0tBfQ+kRzbZwp4QfgDAHTQ/6KEg99ryM3lWqzRS+2Rmx8Zyse+9S
mY0Zz4vKpFGRm9X8kpFmjdvc+dTzr6CX6LsRmH1E6JawqDpbgIW7FG/u1qbr+V4HhtziOWVXw8vM
0f7b1hJnlEDSThrVDZiMbl9+tmY+XO0djeczofhHvTnLUUV+D2gfk7B8OoCFF2WOFTcUERmL080g
1eMs5FphXnDhoFRfYtAfxMPybnCm+GC09HMP8yoYeVTeyim69Jz7bGzwvhiRXaeJhdkPKJMQbgQN
6VdEQzcokO2jJ+XljpLe3H1ilAf2hU8dRaK7Fm3oj2TD6HCoQsvX2ahmR/2OalXSDNWjm9Sk2rn3
iJmu6KPEkvsn+uTdA3TkBnU9zjXXZnHZpebNMZMCSSk9uYd9IhxS+mGWSmDM3GCysE/GGgqFr4aY
wx9yv4ajCHERFojAlh4kiH9jFGSF5O3bEvwHvwny9yHOp1WiIgzwPg0bs/F4Fxw5Q9kj33WPmP+X
yq87ObIAEEgql6s2+hXVf7LTfMFgilqDKMjPil2jMs5rl4eSuP9mMRDV+BASz2cc82EtmnyzLOUG
1yfysW2M5EeF2gDOf8+3v4LhKhrHCDGZlvBLY/kaB8nWB68/Im5y7lK3UDafleHmsdNHuqj2tLhy
NR/pJ4NPMFkrFkrsxQWHBIyI5s/HqyFu2LfzqpgU5uwi3M/2kU0QLxQb/Jl6bHxKoD2zY0Ktlm9T
rKiuAK1izkUYH8D4b0GaSLJn6UbmCdXNb/lTeUYNfnjVr23dBBoz1ZYA+ebhHn3zaLCWHwzHezw1
Vl2/PewA70oFBLv49Puyf5A7cWasP0YFKFx98VlSaF4VcyVsahRh5dwqvt/djXq8vo5vg4I1DIB4
RIJyV0SQuKpqfu3EcYqQUcImt6Gvci9bP/FN0h/9HxAm0jNAtTKhx3Rsy3lHep2LcE1ecZn6ythE
URYdSWULA2Zn2LFytejdTokGiILfiQlJj/5PoUzD3D4okJmL3ku9Z1PZUwh7lyvY44IAUYjkDs01
FCIJsw2jEWvNseW2QvTrH0bMp8lSu4Hc5oFEEx0OcNaFFTFQjeUTzlsJJmlXUYkA83qVi3FEqpjo
NE7kOH9l3+oNoihe7EUykE91LcqHq7zoKdayUZnGNn8sxLjPDObACihFH4NNfrHQ8PqPKVTwOhXv
1Pw+uZvhYhek+QnKt3sa492iqeJg9h7nXJEsiAxMgzMd72IIoB9sOzBJr4Evgv8Gkg/DaGuiXYtl
ow4mmjFKKiYtgFWFkgkohhLxY6ZYOS1l4YguzAKfX2ngYidKEzY7fqLfI0G7YmgsX9R1LGUt6dxn
KTZP8bgV/mo5RAIoLxrNTVif7N6HhM3TplL0GXz7xvT2+WnwETz4wDCqcX+h4jsFk1WXRzF8j3gv
vAjBrEru3r5wVlETWeP3CUOGxmealEg0WMq7k2mtaUKhs3rr/1Vw02pesY4zbI9RuwcR8+rT9po+
RXYYL6AhMHxaRs2/ypQHd28tqLqNtyNSWm0rMBJxvWGvz2Rll0PlbgovxQ+FXxkhG7C7afChRYPU
1X/D3WeSR8myHzMGpyp2fu77qefl84jYxveOuJkX4uXQJApgX/pt7YqwnS/OPL8H0R6mbdRCwQtD
NQ10hRxOjuW7ZrWIXVQOMrDXS41GQAx19Bk6HTg3Za+HomJy0VUdWLRbD6dBAPhtVIBvgdQEGwoP
B/dmvpOPW+302WPLgKPEt6VFVHXDEFB9ysKr1u2J8w7TMzZzX2QprJczTHVFjeNKPxWr8rQSEB+d
y2vEYDMD6V6jaz2DHC8XLDqKOWjZOi8lywFK4Q3NENKEf1h8WBfJ+U6/9Fyo7HbRE5hRwPRyjulw
wCl7bs8H7NUXgjeAjFx+uc/D+KSqHXovAVlemXlVtCkJ/9fqhgHoyjUfA7T20RomzaTxP5x6iE6z
PleTecrIfWyk/DatK4TgJiVN4dp1DQYAuUk6jXSQcYNyZGfh31wuaLhwaU9n4txM0Paz6bpQAX/G
3wKuqibsKnJJi+CUJ2Idc//2N9sTUxAojsE/I9FgR7Tggyuox/TJrDzd4lyRb3K8kGIN3XqCZ3ph
B9dmIhR3ZiwbFy4MDR4/If5n6/9f9Zs+OCMaBJbL7w9lvU5dUV2uuahboEeShcanQzTpokBndB/4
4AZOerk4ZxiXM62YH5k9NRGt16tXMpNTli7QD20w7/xmY164qrmYktmzdTfIi8vG7Xd5ELVLyHaz
G7CGrllzN3SAARWxewBJT06iVxu9/WZ6yROpOuyAllWZwav1J/MgVcMx/O6LNV75ulgzTlytRHKx
jwhsAdZWpTsWRPpQRRfh0aswvAo4WecQsBilRxWLvwohXzILpp8kH4SXTJ0ZO27SxxFC0CT7guLD
uf/HzUE353GAvaRJpOulCxaWCWnWh22lrllunCqUzI/4M8pkNO67lSgqaZxfhQc88U6brozHv9xW
mmjhievqdVrR4YqTj9xPMATuxCPqQ1MOGw3EZmjO68IdCRZFGTVzEEEJa9SwH2QEzY6QPLpXv51g
1H/kw2M0O/99j7mIYK/H+G2RFshAtercaOnNKo8kU9oQk6d8V3VjBXbEYOzFO5d/hH1xpgwDsGcg
4OFa/tpzudXYAFNWEtlMnXYCrbmEir66UGLn1vrypeMJjaE9ZTfz49jOkso3oLc0kQsU8AVXOaRf
rp3n4W9FLPnL2+de/HYxZQqZZZ5da3NGf8xLp64lNUKykAj1Jh2z4glVrzJmcubSReq8vtYH966F
ouXBAZfNH7TL4lSvrDo9Jl6uePLb2k+TVhSbfOnnwsvPJ4hn1Hcz80LtUFZun9QkHeFigMfjMHGL
48RQ3tSN4nqUGcZiifE8gU1AK48aqleUi3G5CtvsFsS4HYiVRib/bKqxAwz0748UAGuvbeoqYv6x
rNjwxn28qaKzdGBmjlEp52kJg3sB0NsJPKuNf3doR33DpCKbs4bzasIT65sJQ8VetRLG3fatRY3v
gqR+Ir+pRfpNO6u69Du/QUbzsDK6/ojn5zKoNTag9Wr9uU77dUEZbyh4jwPgdLX9D5JcpxDzD7QA
QgLBcWMTsLQM4/6J6yA3U+jAEv27oeyt9QnSRB4DYx/azO8cSH2KNOIc4ygp4deDiFYuaTlkgxZB
FesVy+jIx7NUdzg1EBJNu89puuOkTBLwI2YKb+wja1z2zJ2gv/nJtG+jvQBTkxSMS2QLJ70mk+0F
jqKbHPZZLeWcVBWS3rBrR07xPqmYqyUZepaFdZsdUW+S+FUG7Pk7ANdC4D4KfbHHJkBgzi95iQ9h
L3JV8Ay12taEuWPVL2ui2WGn7D6qj5CBcT/rg3n3pkC/Qj3QgRMUf0isWwmQtKDP7PZ0Tt6DRLvf
fvS/PpuZ/NFgdfmLdlZhHV05uCMpxzwEtzgPD3afR/xa/tyMnaDQ5UZJzD0nujKNLpBDInwM5oJ6
vBH8xaI/GIbTTjGPjX4IttFrb54oVjr2XncVE49i2l1X3CCVtcFMQdFaz7ht0BC+Cn4CYUa+eo53
vDG1d57Dpya5PWslnpt0IydBf6qm65qS2Nmku7VqiJtkNVGk65aCseHMeEktFR96sKQR8WTRzWUe
d1QOFhnlado/cpUN7hBjblxcTM+XyQ3nUQrgYC6ima66ajqe+M+SlDQlBu2zodLJZh8Rh9+w7GTk
j7ec/PJxNlQS83Z8HkZgalUKU1SghFQB/l+AGoKWoiQx239U3DqYzadDqXKGUTMK+S68XFfLZzD5
Sv05IiptZORJzytAHhUY5td5O3QUljxjbLZdafCaFUlqN8/doZwK+sdbsKiYs+C98aBdRoXE1Z4Z
Sac/XeiiSW3xfNEZEVZKJgdjOeESgAnFQu31sgu0o1MdRxKAl1gHjFW8WTZVpiwEbHgLlegAIUlo
thf3OILjZqSqvbnzsntYvRIl5uG8Qd9sZyJhNomGZ9NrgssHhNof7bwj/3Xt0q98eoz1TpGY/tkG
x+1dleFof1NYAnvpstAr0tzdyk+YT3OGZoB1FSo0p0gVFmFil8bd82Ouv1xqKyLBSrWma4mrG6EU
nLcnoeyLRRdSAG+yqQXqyer1VDQB2C9JIQXCvSuqI4z4K7RAutCjKn1pgQKXUSEfkdRprG0XOhYS
920UicJIi4XB28P0Xt8s8+Mu08vGXz4ejtIbnuhXBKkxvjKMUib3Omm5ALKP0RJgRSfpf/zj1utV
Sx8iSwurlvK8ZKMhfkNCELecSFu3PWpe7JAQlyMKdXO7hOYfYXMH/uyXr5L8rJU3JZnR6vpfydJ5
z1WTADdtSBQV4WSch95apgpKPeCW//gb2RYbZ+la7ccKPclKISoiBhCV5DCp/UUClWumdf1CK+Kj
ruglGH8zD4TILPO5r4+WGF9EQA4Hbvh2Jkz1B5YCCr6/HCD1Id/pwVBwoUcU9ndZsjdNlWGHsUiS
uzQtXyowgks7lnYPmYWRad9b08d8U3eVs29icpzACSjz5KXy0noNDs9jU414y+KcSJNxZy1xEQ9b
YW7ZRQXjwlm3LWQydDfHXFd5s7LfzvISAPG9tffghCtkkZyqByxiASICB74TlEw5Dw5tNsmHAsy4
jfMnlOQbajXJN8zbaNBDSLVoU8/sgfTZhBmwXs4omNtAReXcY7zRchDDGAfqITGeUNshnpceMrwW
EK+EiPjMVJVyF+c4aBXHPUerI8dQNi07zkf40geMSbFUmbyedrmAUpDSQuf6RslkZpeY4HWDOm94
g3vQsgaqjNVOVIcLX6Bso63mHXd5KSLelIpUg2WmVb57vNZwRlB+e/bH7mAFOEv5iAWwxMGrtVsk
8zXZb5/NhIImCeH9Ny3FGQUncEfC8krQqWM0tJuyGg2AVCSh4spu8t3HlsO7JNAZ7UgUtMXsxAD+
QXF7zrkEnMhM/MXlmcBVLAeNDYZLewAp2I/t04TPKVHK5hgtSJxm85trqJ2SAHWTnNnXy2uGC0pv
soT/PYkMLOw/c4ri0p3zmQYaekPPHkB6PmvyYXvTOl0BaPbUPvaHwNyPNvFOyZYFYe5gDs0chr9V
SH+LRFdykhSkiJHlX3tR6rgfzC2reWwhpcAgSFcpX2AwU7mIGzAaONFTOyupp2iuFCVALZoXl2HP
dmSLe605TNUaAdBAqaWoRwv4e7RVlebbNP2F29qKCRAqJPwS82q0fNB8A1abxDtB0GfywhkyOdnK
B0bR/fD64+6qiSrxTO21lWmSldu+QEz2NEgtBoNnFxxZSnYQ+xOjpqSnFkfEK8CbNxoQZKFMTzbE
uy7h/eTG4fAAg7vadtXp8OJQVKmQblpZMna4cefnRHhoONX+AjqoYrcq7YJgqigZ+/Dh4z2xQLDS
/gJ/8XzETMukGDzCT3QsEW7oGeLKTiWWfZNJeWA6X39r9t0UsD8NR7eG3RjlrWHrYTcou3PO83Ul
b50JOj1RRWgRLpruQIdYLsb4KdCpEwq0RYTwjoEXezpWD+ySoSBVo6/9SjAIahMLPb9Tcouukgnz
mIAdtuRBYpmlsDRjtnRdSfeqlykiWhTSzYJFDUvNt402gXlFxBEzhwycR/ZiaDd7Lmu1/HMqnlgd
1xNEmmcBTaS3t9k0T1pgJuif/8aBmz9vRF6lgmc69vBbmYNlfUb8//PXE6FhY7S/t3Dgw4FuFvfk
SOn1cTlXw3wa0B19NlI734peWqmv7ZvOzikuslmuyd7psqUj6vmrqR7YcznAnRi0rwMX/A9vLqOL
uuYm/bZdbeqJ6gZGGkkUPaVVgRslis5kVfyR+FmzbN8u/Qao3Z5YY6rH6zaIm54Bj2kX3fRu7y+R
ZzqXtHeT3TXkL6V6R55WD0UD0obVL8UJiOtwuEkSAQp6EjjbCYARUW8N4udU7DowSQx2NJFDYO0e
mMftjxPfOTpAfuSMdfc1GNr+Ex60dfyaYJ2+2kI2zOJHmVHrxTKJY5ELd6Yk7SmnAIOvv1Z6/Ccp
SxaoP0LqWEP/8Oa0Qe08oyBk3w8cWHBa3dG8PB2JDnwkxIAko0sWARIw5BC8L8yTposE91z5vXyi
CbCEYHRdaB7G835eW/pumfz4Ry44wjx6ov2n7tyTBPsz8OzfySvWh7YQfATb5036+sbhxSbuRm2O
qbhUvd6mpDB4yM4t1fF/y8LCYEZy6P7QQXwW8JbT9e3l7TlKe+tFXU+AFO+UFOobATqzXFIOoZ60
qhlUBJ1kb52iKuhPwIGxMv/S4LScMqYyyExs8joi2SfBFHix1+5agrfTUqxmSxe/n83m31zbjMmA
V9spGFVmxXWyc1OF2CVcOTmRlYm9H6KB3CcacKpszLKM2qvul8M5hPfnj/anyWwWvozjFlnMvJL/
4RU0D41NNyL/ulPuK5L3obI/ot9GooPsfaQ9CKrN0xZHp+c4h07ARQxvJur36iZVn40RYxbdrZvQ
ij4S07wi+5UlMkG693DcmmajMI954uGIHYq3Lhm2y/SI+LlEL0xfTXoLyvhSy84H7hgMioxzm4mW
BrR7DhT42cNrU3NvuEVLQ+LuGpkPJFkwsHJvYNKpX4g7X20qeYqwEw+Me1zB918lKp00S3sXGK1a
r9xLXtVfquEsZ6x5xIoBDEm6nncI9Tp2TlzhPpbrt5kKZjTuTegLvqGgloDVK86fbcR+JkKl5AP0
e3jgJH1nbofeYmPb/b6hATHE+atppIf5ao/eXdTFl8o7ZPaFMB37IhIdak609Flegmgz8fJ2bbFM
pBQMFwImWWveifD9pnTEGsUm+oDpOt7+XVbUbla1jlST8BOSBtHffIEJTnLdt9tx7ulzIku/8UAL
T8TxGgjWaT6tZBzMcRDSa/cNG4UxWNnw9Z7YN9GOhO8a9rOjRZXFTca8vOGRDIn/UmPGYUSaWPzg
LFyEwdRNVnGkN5tQSzXVsBg1uax4umZ5qytHrpI1OQTjZESLOCNUkr8qd0nu6ErgIYE0Z/G0LB6+
NYBcinK1Z91fcMIdFdMYrdjNI93Pc0PuzjKQSoxkVEny0cg2KtPQmN+ZfIkE+YCOLQwG4rle5aFX
abxOhgCzTAtC4yt1nSt+8qkIsxlxayeyI8QNqmcCR88UinpVz7phPonyd2TjRzKb+cCDHnSHYM8J
tRDv9JYy9ePuR52bPZ/7PP7ElpM9lg5kA+tXe8aABGBhxQcT90gwHNswCZXFiOP89q6cYRmq/ZoN
AbHwLGxS554mtCUiUnDcK3KKW15PSwEOHYaGgxZfajgbTrJa48hGZ1oo7lI+nyVgJKIX4wA1wvkd
5gywogoh/ihqe91jRdaMHTyUrMgO+Cz1mu+knsWRsMTZ8RPhsS8FGEnPnCuXspOIbZgrAAxRIW+F
idyd8HkjryOGJaWie8L+s0dz1QWGp1tbTG1v26RAE2lO+GmZihf4tYQZfpUGM8/IVdSX7sqB7Xc1
oOqWuujjaN1baZq5984azUxIx9jMGQhbHF6F6G93u9Y7mZREz5h8Rm51spuJr8xNK9f411JudHUs
qpYIDytsEdsbgiIt7a00tkNlX9X6C9/vOFd1v9R2o5K5JjmevktjPM7iaYjZSnmRJA6XlWz4vca2
aUurxKPLECmAaJv5Rci+Y9vOIObgnySZhb7IyojdjqgenoyS4o6s4I0fL+W5vM7PgHybhxUa/tEx
649O0a/9ukZ9kt/Mswr2XT1jQEaemzaz/Vu7xC1dso0LOBEZJ9cDvbkmttpU3ZYI7rdVT8evbAXZ
jEknoZvE6A1gAg5JOq0VsiPtOJANqjCkAoBK4Zd7tWocfedPk/03XxMHsLL2FW192D73bSOJjhDk
Wldna0cHkmatqgYXFYqe+IEqSGa2JE7nqAjCRN9AqNYAYIiOu1aJiBq8cAwT+6HELs0Yg26N6EcE
eSMEifyusJljio+1TIks88DnawaciqpNBx2L6iv96j/rTp5DTvQxX5Lh6nk7eSVeWc4KHPQm2mBF
Nm49vF7kbUkiO1YORAlf36PefsOta3VHSk30HbwjWNXbzU3VSKXOaFCfnKWbl3yoFtJWbJAJWUG1
0GqbhRkCsCI0YkWaTH73atcVrYqYsd0qAkMqbc62kEGzYB1VJNBQ/guPh8J8vf4HY6zxVrxP0vFN
4AhrACpj0vPXMSd0e05j9fCVblog04GbHxBlc7MM0BKYWL7kh3fDCmNwMNQZM1mgpTW+uoTl/vAu
w05oY7I/e0z4mN8JhTJtIXTMqGyTvs4YKZNKksUh+Xdq0RDh6XsG7MCtT+1dNNgJdi3Lu+Ygf0JS
HBk/cx2sjN8iZpcZR/Xm8EdDQVEpRBPHm+bmHx3ddifbeB2yJReGs5ISAJUI5O2ZYGYKiokpol5r
zdHOIoq+TOUkLVEzBXeO3OIVdWS+3lz8tFm+beY9ezuCaO4+Ct0QiMfHybwnMiR182uv+aA2AycG
5W2tuNLkaV8a4nTCP9LszNUCw5TOaa1NfBQMLerqOjH3rOZGSnOOpR9mAE66jMIyceBpedc18P7h
tuXfKOWR1Z6tOE2eXMwH1SKBWCCLEa45LplJ2R2O1WRRi7Z4N4/xKLJbBWpG2lYAKHuuqPijNUMV
XA3ts5kzeYrySbq3m3/5VcB+tK7ZEtG1Zr8isv/eew61YdzGXE3IhKGsJMEf+aTKpXfb4G0DIVTn
k0NQR653uhgdFUoJMMsZuMkafVwfqBNEpwwPedSV6Rpj7WnjkhC6P5We7ib7C/CFo151HALBTj1p
hhDg5a1jEzdICU6v9GBdCDpTlM790rMEKzJIBWDv85llQDggTevOsROAQmfGC4ABH6TU2fVO6+sy
aj46W4zG1cbOIjZWoQHxRp6sqllyqkCqbYiBkjCskWeAl+ApIN42dyP5JiNQSWANyzPv2rrPaq9n
HE0v3n5Y4W0i+Vk8eBukOguqnkb5lkQMWUDg4EEgUjDYPIwoJa60w8uq4i5E/lqhMm2+aYCmca+s
p6MTAQdOQmBzU4oHj9+hdF8r4dNb0NR8gukaDgTO3bG5/2MfcY8vicPPMhA8Lbxiu/A9bH731Rvi
MygBLzeu9A39F+SSrxPVK+suWh5fyKAKbqWN0rxuKDULy/tO79RCjUHBqzlttbAD4+pgISygpFLx
EYd85cYrApg3vFuegn0E2Fp1N6UwKHA10+i/ENS2FqGgVT6rQhcTFAx5tSpntmHP33x4KIH61dfQ
UNjSN1VIncKhc/6uLVPzqvVKzJYuKMAhv+YXS2vNA9YddITgbzbWw783bR4FE/hNEpG/i5tANbIk
yg5qiacIfFsRNcb1kBnyJD9DW2NC4saO/K7sGLRJOKadmMWtUaFW00i6YBDg/4FWbzEQ20W8W0uo
ol7lGbnVRe71pZqBw3UrILBTHKgAxkVXeL4m16tUVA39kQ4G0wVNPVDBq62f9z5AZ9YDb4dXPJtW
1qrvl1nsrYjGz92QVNnuqsjCKqgC4dD2/Z1SL57vXYWuPYQ7rBzFXjdplEucFkYwTPUg36Swe6nG
KBp02Ch2pOj5q46nSQxqA6tMuVOd+Yq3U/KaR8UqN/irKEkn1px1XvDPYVxq3m2n0QaTfDPchkLI
BcNh8cQiAe7Nyl1PMEoRToIQ5Cf0eJfQ6vEpTIlnG91gahMri+Na6EvYWGHPvKfmBPcDI/dZZFBg
2amkrUf26SOAuxTp3sLs75HgZsEPwOGKnHwDyIV30+iwR8EOYLNob6MsF0LJnSDyU+l5PG+Alvj+
ccI7W3VATGRP3A0eSpa8UnBksvlcF1xdJKsLHrcjWlzC7RrkHiqH6nku4+fv3nELXz3zNvT6sB7l
1Dnfg2uHcIz6VWpZ0xG1zcFM+vwRkdZmYCYUqUhJCzNpLeHwf65nfSFJj/f0ucoJt8fY/gQ4yNqM
2y22KyY4va+6wldPidNsuucclcbv3l6cEeLFcT+hyxPCjKcityahJp5Fh/dCcLXZGqXfQseeDxeH
KE00e0rS/rdrKE4oNWo2PvhC5kJEFh+e/Adf1APIuwz1wha3rDRwxeRDIGx9zMDv38WN16gPzL+1
+2eYCFPIHsfQkHvg3E2ufnf20PriRS5LtbKpwxXoXbTb3eYyzsE3axdre3UQECH3AefVZR8v9g/7
95XmRP9IhB2KaGh96CPJIF5poL8XrJFofkOT4fGn9zoXq2IkPwyY+DJ9TLsBBWaDBNGrCnT1We21
kbbpadwVBL55t5EDFcLrn4zW2HihzUdWbUZaV0mY4BgMmZJY52cFhsBa0mawVtdBEayihOsDsUDw
hJWm24X+naDT6mkBx7hoOrETAgleduAyT9uzRPobC1M9zi+LpNQW1Kz0PJiZoja29MF+NiY1oTh7
cU0JXrtH6Y78CnuOWih3RXDNgSDYS52qpg9Rry8Hx+N+7A7dfR7bWLGIPG+/1FOrjSbSBq7q+BPP
ecEO3KDFQoKZHFdprqOSPV+GBNS+/2fFOZ4yiCqAY3qT4WjtKfE9P+je52YKfRC2fJcTf6GVSzSz
Ld4YNd8OtGkQ+btDfHJ12///vSnqiFAauRm6JquUGaoiknZCaPwFXmaKPZTeyiC35AqpGkhgSaTw
gAdoqZgQG7yVOV9NF+lRk06oQF7k7zWcDurXlONJeNZZNNwdkmHW15VjhCZIXQocfwjRtuWMH6ao
fy/9CdNQR5IuVgzAeIxKjwdmLrd1pxpvNTjJ64+GPVtld/595aec6vShsx8Ogui5+8UHE88WSuyE
wxyFqNMI8keEU68suDZE+xkepWycXY7Rn0GEPtRgdsLCoJkoRnT9ugAy4DyU+uriY0BkLYYYJ8Nk
/57Vkl9u20RwcQ38xECRXUm0VMzN74vjgWDBERuHkFZ1qUCxNroWJfnXbnx2aERif540Q93cdcG3
socQLOkKjD+CKGEYIb3fVLFmGp6o9DEgeBvwy+mSLp2J8abI4p7uTKQvwELgN2qWsDSUHiQFtG3c
FbVlVSz0EH8pfUt9bM4v108R2Tt6SSPKlgohTIVjHC/B9RTlA9wGDt9PBQIwlqrlSzVaWJJXOh5n
oGqripWHmnVDD2rg/AkVGIoW4K3DXm3QalDs/C5x+s6dBk8agHsY9PEs3jE0NqXdo1fiHxLlEpUY
oMED+igXZt7/8xxDPeLJpJpbjF/fExx60r4BZikp6XoXjkfQVLpCHyT4bi1NnrDWqC1NEHBMRd5x
nCeaYAxdgEhUft3v3sz9SyAFwQtG4UZpkpl993rN9pZ8I80e5TUEvMQSJ1IQsTwPSOpyhA81VAbi
26p7NqbkWMlXOuf0A2mLfw9xAHVQX250wGukHsMfTo0YVrSGkxXb2pQD6nu/G5ibFoaSSX2ld35P
D+vk1gqSC2i9d7bGmGv6j5fL9jO1lXPrtgTZeKoWvb4qs7yK5/WIx/qoIM65y5S+ZXBO78bpSoza
DABOoOnvSzRcQ3QNJM/URDXJm9J4wWdNJti7TOpDXzuJIg1PFKLTcMyBFIS70JNaU2rIm5wnqkBk
+IStkkqkDvIjAm5hcY/R365rSQOsIhI1b+lxjBd4YrmXh0H3MvuS2CKAICZ+Tc0gzl3GEV5tgnrm
gsuFopTlefOqu4EGt2zqlHrQZGz/y2v6S2EIH6TE3Y0fe/Z767A9lU5lvFj56I/+4SqQbyUtPZcT
FcyE4UxrvtvGg50LjWPi8q9SEhW2BK1kKAjjxW9o/WdcItcImhGsrS8L0cSriiEAKv5PVJHIJROg
huRjkhOcNufW3GSdPh3l207uXhGR7DGmFxxy9arEJJ7yleOky8d8CFhx4mejtL4pZXCRgzK8xXT9
mgAFvDTPM4e1dwGGGyL6Pep1w2nqyUCDd7PvBBiirTr2KBZvSvnxcu740uiSFiUs7UsicOF+QCoN
vntpeea7I1Kn9OTP+dsmE1Q+52lP27285/nFEBu4iyOvxLlwKcG9qIAE81U29Ah6TIQyt285z0LY
kQ91eVNjHGy6wIt2n+50dSDFb8f5PaMxaebOG/7cSr1OXlE3PVngB/96xpEMe4guLnGttwcIFsIB
gSCecvYsFvZIZVVi2gaWBQ5zmOaEkMsu4uDmTgXQGJ3u1Y0tygNwmDWdwyXYNDVTfVuThOvgWgr1
L5soEdK2SGo1l5XP35op0pqA2tZm/trbQEfnlwpenzLvZgUlz0xJTSsiWu6F0kXCPpTORNtjIO66
aAmDmZUUJLx5OpzFDq3cd6A0/iG9QmBZQhMQf1zSI4Ogw3SAYybQ84B/A3Mz/lCVG1UyfthpwM5k
55VfT/SbEdAbowbc+KVWaaK9yMPKEZUIEyYsfv63g4pJXVYlH2zhpmxmIqylS3ZpIz9GB3hy8nI0
M+JrGX3U7bBjQgYcx2/4V2mT9fB1yQbYR4UdY7ukfYCvRWc0omMc8xyGI0XBmgx+Uv5pihDChlHR
/WZgJyQSuAjHt9EpvGsQBEXLbpoEUuKHP7YOkSSvwyLNr9gZK+7JQLBycI2ya56jrdfo0u1zMOG7
RFl1S7xj8g/mfVlhpzw6hoRon1BpcXF9S7owhVEhpfNPzN2iVU+hNnhv+ByFLd69YE0FLoUU4dBi
mtWRf+WNHcFDJbuDok66AcX8d+m6vyzdpIpGaQqQSALkR6HGHbATs3jwYnQFKs684Nwn6TTWcChm
NKqFiUywRybgQ8s56vT9lN3OAVzHcj0vq4l9EwQ1gWc2kHlVpOXjBWFTCVmyqW/P88imwP8nndho
eCmnZzW6UzIrZv9WhUNit1RbHqyE0LaTkOhn6ELaPETrkYY+FA333Qr8enLts7E4DMCHvuk7dgA4
UWihqhNfoCh4bcohnTXc6sQs/CZzkfnznAlb6d3ci30Oq1MlUNteca86mGN4CUd4BPOkglRbKTMj
S6VFdRgdhCsrKvS1MxQswmsYt3NubqQyKCRRSqCPqumqTRG5nZ3TO8PQ5ux5DULpfR+sv5piA1Z+
moEV57Pzzbk3U+uNzmXC+8NU+DrqoyApe6Tj7hmvzBnOv/lg4C+KoomWjkOQZxdHbchTjYHwg2DI
AwjRapoTsijLLWOTyk6AnC83XhP0qFqikFmnypnYSELjCb4ayuz1iK3KYBKSuRofrKaDF3LqYypB
IjchI7u/ZvErFuMN66M6kAmqN0UtE0ZccNjlvmIwbny4FgcwUkbAwg34BeW1EO9EbfgW832gWMVT
X48quDOL6Mgb3/rasK+dITjrtA1XImndtTgUaM2kjYGxqmyxchz1z7+1TxB6UfdbmomO2vKqBYFY
i9JmVxf6EkgkzrPdR2VwVKOijy54AxAHW9fy+s2yXe5U3ZhPoe6W8Hml0zydrMQeAhvVWcDqBtdh
hyxIB69G6kEQeU9iL1DPDM6U5a17kq+6aW6+EQXEeNORUX5izGL0+gRz2jGMC3hJYa5zbSbES/Q8
WMfwlAGCQWxCOD3Fok+rYwVy4h9CaIS1+KTtpEyZ2H5TuWhItJWZ6hbh3D323U3ZWwxHDzJOiZSj
hkNlxyE/SdjE4lgodD2jlfHuAY7eMlRvxxehib5JqUux1iR31EC3/FOWHvpj97znx2ZO27NXJrWr
6ouxadOY3sxYJp1d2T/dNndKC2XhjpO0K/T/1leuip7bzfo2CxRRYUuD90ABnJuRCXmhGRpy2v9U
6dkyAWHMcpfixr2nRQFDEKpfN6NGvGa6gQjChcF1YJj3U3DIJ5tUj9I0NHJurFMLXYOIkvE61nuJ
fx6YNmYsBUbRmPdG3gMbzPlIdsbpBE0J4CGauV5eI9VKLZy8qhD85zco53XGqh7+/kAItnjY6dgd
4VZo+SW2BvlwGA++yefXNPAgNXF+AAUbQsmB/hMbstjEFyGKGrCvSYNPP/cQcxd03c46xg1vrQeZ
rNROJamJNhRGEbxD6gT2Sny1xea2Zv2ABjz5X0EebKCfxZZnU0OqQCpSG29Yv4aoFf8FdpMgdhA0
tt0uQufjuIwyGXk19jPz3Y9FAA/jexzJNZeNzhkCkIwwkxjD76Jr7ffjTJiz0dJ7aYV9N5FG71kN
1du0vDgPwc8jC/cF24KBbwZoD1kOK+dldfujwA35hgtdbd++7xlvPOUbNtpKnJXgUUrn8YeLsqwx
OqoK1YZi05vZn1sENSJ3M1NuIML4XS3l0FzjA4NY6QoMspA7Nd5StRXsIhpcAR2UNBAhJlX2zkxX
my+HVOczmKcb82+MbUK7XNs1UTNIz/zLR+AW7/ioPX0u/hNAbi5aL2nxOENfaQ9TLLqAQK7lS5IA
bYYN2DE6gfUdhkyGU74Yt4McJpS7EHeg5nHjySNJAmMfT2Fs9pER5gLileAHLwsqF3/96B9CIqxs
Bw7D1OZr+QGxUqPdWSuNqsV01ZdZC7D6IW76sruf63w44hbDPBVW87rywe6o0kpVMa1Ci/YqquZi
hXf47cgmZLrDOYpC8X5AB/pxhBGz3+RRvdvSkCWQWGOEGWzevhp+C7UmZhganxwAbCPT4OXIibu/
7vnGiTJXrEP/5tmty7VDDg8xnSpzv4vHkZGRcBRZlYdtFfr8NDVunTmBFYDNtvIICU6efe7FLObg
vfYEqiOkT+ziy9bg6gxtUe2lOlXDeZ2jc0G8ZzmUE7z8S9fsJL0oY6nySdgoDFJVzFKDzSVRpmeb
KJ7qmj5r8zWElIgIgKompvBm2rdHf/5zxlqYEnRNnkMVbi7ecVqpGM+f4aHAIO+kifeeLsryToPM
BRs+G+cFK8uwtKOjYAWtBYD7rV0/NwTny7b1fI7+HzMWxxJ2hlC7dcrQnLER/LlQADmZql7SGwjS
HEOahRB4JE0QP8X5Xp/0Q5C41i5FkKfznzyFKmTkDU8vf7ZuIGrmJ+SNPG29F6KkfxUxl4inu++c
7h4nY7zROQGR3dIt+ZUIHJJtdfEPNRsamWlV0NWm93tfFF//FPMIdI4ZPL56EOj1tFlLgyet31S2
HsRwv6HQbIAUHrN/VzhOIURru2cen/HR9jY4AzTa2XUssaynzYDFkU+Obil1JX/jHkH7mL0qGWdE
hnoU6kgXNjYAU58qGwobutF1g7xQAwMDwXzdprkbC9FozeReX4qRTWHC9rLEhrs0EOuwyDbM2+QE
uPHVUgUz38M4IPAa2xUKRwc28wLjnR7rCOcbmqu97al5pd7rFMWb1+6kPJtdTAoz3kTGpiCboLTu
W9+p19YZSmsNFR+EUO7ApUAXYJttR2ItIpyEd6RJDuGlAt0gZ19/dZsF95w1Zm6nuE+Pf4gNGB7+
jS0PBYMwUP8lMhxfL0JtqZINWeAO6ozv5PWkZbmibNVFXsphbiVyJ/klRo4r2es5jl+6eGj759ij
BHJTVlYJmpkSaEfbN+38VqDL2RdOqxUeUZian84cYiVtx4ZxEVc7/JgW4QNn/BQZYkzhj4jD/E3B
AgMnuDKK77/5oqS77e2iRuvso18BhLnLgAzauAjj6Lv0pQzISFz1DdGD7seSLBC0psm1B91kWqNx
a0AyXKup0Y6CI6NU2ac61wQHrZzbZ33Rmebnc4gIk5ni2JsTZZTDoa9z2fn6OrES4iYXVsaa+xmJ
IfQFTvWOtCRNxFhDXPIT0annNtHA9kxtahDqwGXZu3/PJozpKJPeyy/7u36x4JnP1zsh4ZHsokGk
pEOo4mUhKlR2L5TWz3rU/pCeYVyY/fps6WfgPgndvaVaOlpiZEXxQPtoJDRoJgfLymXVT1pIj1dX
crbvZiEo7nPMhvnoE6ai+8qmmIY+oo6QtsQmrbBk8wbITp+6+VkL1IyzyWccb7wstnUUHWyT9hPL
rbYcokhCGlMP2dU7fT8eihEnHvPRXvjafMzOyOXAX/zclcOwPPvPa3lcT8GCEGOQb9ij66ag8pLB
qljZzIiOtB5qANxGETQK2RyOOvmNs+N2yN+j1zq8NG+1syd7LyZyQ+xnXt4fFTkqD5t20sGQwkf1
qWmFovOSUDIw+Y85Wl5jvuwQtpRoQ46IsA+tsmpMC5E7yMYwe5O++rs1ANyINyxDpQwZAFk7BCc1
SGSU/YOY8TwuZ5hOmCEYzd/vsEC5zQzBm/U4VMUev7IC335qqDc98fFm3olQR91R/ocXbg1Zjs8Z
vf32a5LONVmphJduGAmD8AenJylu9cUttstftOHOQs8Cq9aylBAWWiV/kNeP85KfqEGAPgBJGHM2
2ta1A5Qsw1UuC59vHhZlcAlx32PWYlLJSGRib1mrM0o2r1Qcl/efPr6h1VNfd5LRBAJ2uN66Sq3L
TRuRtM17rSyTtQS5+k4jmdrGTCok7fnVuCFM2R36f8eEhos9HPDTh0pPTwlxzhFFGxJhgCgFcliM
Es/kyTxRK+QMqCH558jouuIbuUVM6Gs3ejUZbhDQ8rXI0ntG1pQKmXlPG7bt0DGl1XEpxegKXVXR
ZErVuMkJmuOse3kMOyUu/8B5ReMp/Gy5ntnNPJhicZhT57K2FpJXAaq3YcF8ZTmLPbfYa76SExoo
fZEx1O7ipEN98JUSUIsQ7AyPbzeQfLLxQax9+jHjCKroIfXStou0RIl8qy+xNr9p6IvbAhdvB/HX
TfYwQ3aicnWLx2YXzmfvEyXCuz1vqOU4+D8PbBVS7ogLWdh+Uor96nwgg1Sx1TN+M6MoZi6yhFqu
98to+5YCQ1AjeoWujWWN/rsKdENxKHtLynFoPaMNjXEanpXFEz04xa6hmwWn99VsOaJSCBz0QlO8
L67cdmnCD6I2zwCkGjIuBxuB7iMAS4Ou7+68rsl3nDDLPa8LIufZnZ5/TEdKcEn8/tzwQKTpDrL8
E71CsswFQ6iuuKcFijo08ixU27kZ9XBvZLZmXu5NMy7RvXHBFyeC8qgUhQBf7EZonwQgrB0p2YKX
j6TdwwkJ1t0VWAV0aQ1aJ2UD9dIctQGDwRBQd8CYcl0U3PV5hQ+a9PD/rtA3akR++mVdFjZuoHzy
rg9sMKvYHVE8xhQH5qfdej8KJEd6mEKmH1n8dr7ItB3hFAjELz+0BKmUnZ9j9IUYtFMEDj03/1Tv
wGyOTOw+pcp073oS02Hydb6CVpKdPz4UaHihUDs78uRxWNS5X4UgT5K2tWWvp6vuXpUiwbhsMeTE
f33P1g9q7P0foKdDOLdOc8Gy4jkEdbJOXevrW6LLZ1NskaILgXrcZKxDHMurnWl7xR6rp7oPjtY0
K7NuvMuFoDahbuWzbvZ4k2DExjE1QeTCVxFRNWuqO7KjOfUWkw6v/mIJ0snRHlY59KE1MMurPnBt
KfkmbUYmzDrrW5+sTxzd+O58QyX0cLeayUMvW42TvC3jpSWA8eTTrRT12q94QXExYtK7trSpM/7l
TMfR1TbI4Odl1Qmg1HbAb8NB3idfnRpO3PuLEp4fX1pnyI0iKPtmsSUSq6WCi7gJo+yYbRAQU3yW
FZUGxyJFAKTSFmzyRpXBy+rlqy3tL5z+nD9I+iRye35dKYYFQudzxTd9QyCrp/eAYKzi1OPgAG8W
UDSY39wMntDDYaGGtcqnyzRXo1MLHa9lMwEmlON+1Z7q5lAWD5U0QB3ro0i6KBr1Kw+CaiTn2gsT
c/sZGv+0tOHxvgtIUYTTCpJuTApGBrRHQmZVeB8t+QTDg5DLQ+G1P7Jhye6mvqwqxiQL3njHSvXB
AMt1VbwFpXsIM+vU7t90g0wnCplC2u7Wc2YBqTTt3kMxS2J39eW6K/MTmN9s+/bijKM09hpCm+X4
14IoWn0M71rtNcckqYKw2nMVNn7flDwuj8MBYRYZJFS1Wq8habQ8MignQHRtwRlaRwhejapiYhh2
amCbPEmCIaBf/D+5S1dQzMyyd/0JGx9CeV8Addu3lrc7v/8Oa+qIEDfQV1VN1dVJN6teLlgclQaW
vg5qfZ0ywnzSbTzNb/ayfy3iOJWd+6a2LTdBmu5xn2lBXSPfDatsy0TEURMZXcoX0oCXX9fpXVEi
VzN1S0/ErESJuXPZS4PHcob3m5YH7gUg8+Bco4ESfYizNaRX5hB6Ta++95zthr1FAIyJ87rRQQdw
9x+Wb5n9AAGT4IKjWfPM30mzy76e9wvEVgFPxZlZu7nrUk24Et3C9d5HeLpTEgyanHrw+0CUeCfB
kvFBnlUqNq2+pNCsqtMy1MNqLmMK9n9qdFnoD91+YoVsiSAk7D6HEzMWFBEw1Rj1EP71KI5T/6O7
qaLlxJ5OPgq1sRydOzA+Tlpmv47a1zsCE7vDbg96PgZVLSuVn8i1uRI1O423bVBOzuB0MCHIDD6V
bcd2EPDN7HTStohpEzIgz3UCsIJ+7xvccmiBkj4EW5jG78F0XiI1E1koBDqMnM1BI9LAvZDL3O04
9czanHzhdvX/8HnFX//BB7TGRnlXp2guELwfWqKbNYP+TMEjyIm6tBGAmJatm3MyvBcL+yi375mn
nMP4GztupOFWhJ4cLsXNdPV/b2HUJeRrawfwKVeJ/Sxq+rVsY++/dcfNCNwxWV0EWajUMs53VE1+
k0pas4olvyuP+lZmXwa96tAlCeX9xgVnV3QIvvvUZ8RBxvYtpCoJG1QWxnmgKrixBvGrmPZfuo/p
BHQ4PepPmqIVXftf5Oxy5RJbBbkm/XmSK21aC9TqSePFFkPTb4rBrYOwM+07IZsdJ8iDmjKLX4sL
1AqDpPrBNgZfcRCpmpqaMg4ypc0tDmN8lHGevShOVSlGZZ2x5ERvC1Wr6xrAHqRFeBipet9lJWZg
+M/OSlNvLgtnrzhXwMzUS9J0vsWJ2a0g/gSaJtWq7tIJaJOIxqMtXzF5SzyZxMvdNvM9xpv7uAVt
gTz6bwf6wu7+18ohLLcvogkybMBznUpLkHqAhmWrzapHzm/D+zAup8kv2cDQHlPTKdcTvF6NG+tK
bRrmahfF3BSsxVbV0bNU24UNVr1BH9pSYYbDSP2C9KxPtOg0Dkl24v7ix4XfneQj9UPVEDVZEEwY
kWthW+qdGlKAe3C1oV39WHdpB5/jtm6sggprWGxnYVMaWm6q8rWu4gGmp4XxCjmMyFBpoyjYm/8x
eHqKL82pE2ZjzxCkKMdAcaYHemiLJS73PAuexOtN2qCFRbzpHekOUfwyzXsZP8bpTX4T1tYKmRE8
vIsQcxew9jaOM//2qRoT82vpB9lZDFODozrgRw5kPJMyH69L3+fnQZHUoGyQKevPbEuCtO96X2nd
J7hZwJDTx98fCtvP6yMTfmlhaNV/pi4ytxYWi2gLL7By1+tayIiUY8hwvKnjmskoWy+62Jk8ip0m
in+K1JuoOknK3kEaIr2BhyWXbZW21jETTFDrafWpeURGQi/MSr5g3tpsH1oYYabdUu6xSBYoF1mT
sdKjqNGdRH4ziCxMLXyLUx+KrDbzzvaq33YBiV5jEN+VNn4dSE0RX5t62bgwrzlYQPQgOkzSlnsp
3Q1JbwLBkvJiAiwfD7Clh1PFOp2X8+yM3cWYJ6ybEq9+AUwZC+UcGU4cSUUVLvIftbkf99zf1QII
5Q43f89SUwyY2YEziMLiVrFyaHYJjIyXDuKM0d4JM9UYQAH2WyE6FA/4/fJvYWxyoU9zG80GtKHg
rghFbn2sfJrSNcRLipjP51Mj7Xf0VjccJKvJR5E1+8n0MaZk3qb/Kr6YsDJvMqqIox/yrn1YjyP8
GYtkYvt9rzUHULBp9eD4JRjepouRUSq4h1URjtrc8ZeWmOz8Vuy/o0/oZZ/N+bb6SCxmp+lv8oBS
D8x+YfE7Ep8MfW7SngI+QA3NnvymxKUhdH6CJkqY+/32OjFXhF/8iYKilBBYu6v1+Wq6re5kJgl3
36o7MBI1SUSydxtrVAtwHBnwbUHTRpwmXmMgYJCp0HrwmPujSXS/oHheUZAH4FXRWwhWyRNaCsr7
5c+ZRJgwVpZj3kgtIkdSfhbBz4nMFypgG7/lWvAX2UIuhBRPMVNHmKjnl7eTbjII/u/1PUJbdMlP
iz17Wxx8lYgUZ+ZSi1ajH+8sVYzKhzhgW0lnJmtY1x0wJtoMw0Qh2hblDkXl3EWtomJchm61UlRB
qmeEGrKuje5iHGHo6GjlKfyz3zsl0BGAzSaH9SKqhEqpNfgp6W9ddjLUnKgzIJN6pDs/4FD8Ej6o
JZiv0+FYJX0bALpFtRvvktcO+KIyMAmdZTl9uTBMI9b+LhT68Pxr3Fls2KX5Ygy9Kv6yVPEsFGJ3
n5VTgFYfIk9ehvN5xpcxmQnkQguHPQAkK5HaOm7TWZ7h7hP9kd/FyDY1oOvynYQyxuUxZhGALZHe
KVBwAUdu8rwtqY47Q6xLgeSHHhtdFQvCmnmUfMt0gSZ9btEtV6vjP+G5P4HxgS9npnkETEfBEYew
qsUJnQbRvk9ZedGw2MGQftN1AeUctv89URu7symUa6PisR9RRbw922tzFi0C6q4J4rPBVA232u9+
QdRmhH2Vo8LLxDZfO6DggYE0g65mn1QmBHXOEdKOHZqYuSZrqpxHKZ73MhkoCOJR2waNdGo2No6t
gwxk5z1rexFDBXPoX9AOa6anDMvMYWiPrQUGhD4lJZrt+Iv1r8GniQDePnOhrzCOKl5619RkfYHs
IxeqU36dmMZQNeZVL30uBd6BO4/8nBJJxbrH0kk4vKEOptIS8P8XwXpiDivW2NR6Dcu2OhzRSLmq
7sULpfYYCzZmgG6VNCC8oImAEyLYWkNEVac/EkYL7YIyf2gTPPmbfKBs1lRpxbcKOXj6PwY8RfWU
wai8x2RbkowaETPvPJGsvaQcSfBQDpPu8JG8c1RFwq0kWp/s1r6ifmIQsWvBg3PHpJJu61AH1XfL
y2BvSBXERnZJHCz4YxBpMTYhk+sG+KUPvoRYlaOt0iQTkxmsuBjaj3WebNUaMqOlYpvhfxHAbCT2
RfqLPOSKAnmiryCairwTDzWLTv75JnEDKYVXGzB7RBgyutuamV1j3b2CreKOwkqwRDjAlq7rcgqu
BS+mDT/Q9cpKXcfEJRjU7eUKgA710YfBLDuvHBNPT7iMhlnLJ8ayspf62mkRoKwBwzpFOA0doy7U
UhY3KLsDbJ+nTU9Cp6+oYQYxLaQd9jznICVyRNJUgEhkmZh6AwrodIR2bL3zDufwS0hRGPURQORb
l69FlG9c/BiCPjWcuqNsFbnTO0YSEI+1elRpJNTlG/CLlYo2oLfGUds4nQClEyDosalFea+TS+5X
4v7/hUobBdNCldrtvFIoZzNcC9CNExTe8+fkZ3ttWIxuk+CiymnZMA04a0dPz+j6Y+O+UFGhZdpV
fPlZ6BdegbV+ZEnXZiuojivU+aa2qTKYExKAIn1aE7NGU0k5wfCfnhHoAPFwqbMownezklXiYyWr
2/eP5e+39lkN5IP0GbUc2hZT7uVwwKfWuEG+l0oFl3i8hqXsRVNKqwQdN7TDBTSCA29Xh+OxLiJ4
WIgA+mzhsrX90IbPP89mWpqGNrTrK+VzxBZJP24hyuDwMRCQhAdNtbKgCB0iON4vvcAK+LLaoesh
MA6X8vFLZrNMkWFsai8DFfW8sdaRsHDoLUhZFKK6tBCkb04SdqdRjva423jKPtYVwVmaVnf8WdXt
NfQmhPu8qgR5JkxPEF91mEhK2sXwnMTGYtxHRtUcnihFxN00rQ49D/xZPD8CtEPxPwtztZoj5GeP
hFhDVvA/oen432znWAP2itRFZxQd5l55C88CP94l1b+V06oGWd/8RQyZ/E5L66ycZ80yhGnMCvev
Ve1AZYsAi0E22+bS0N2/qwlwkrpN+z+vI497q8INwTWkqHPtFu0hNwSYyf07KTVAMSccvzpJS4t0
qIlEj4gOd7MaJsaWRlhW5Hkx62bXxF6c6wUDSO1OvqHAvrWQym5M4l0vquT4KlpNbqLtxa/iJD3b
0DfPXsbpOGAS5HoMA50hn65ZmGKDJz+DsULuMhoQBCOvH4T5SXUUwTbSgCOpgPWWiZKAEg6kaw+G
IwU12885XsJtpeNAKTRewFgDGkBEzX8yyLgjf6FqaOqXJsc7X7vXX3f4MLuBhSsNY56oHALCMl4V
yJn0zu5ob+vGwooJKmCq0LMMIV+p6VgiU6VcQXVkgSR6kdKWLKNjUDSO2KZTwu6h+zxulLS8TQP4
+/uhVAjR01v7dNJRIorwoijR/oGLd22JkQha+qyb2bSYWkSqQ+SRsVWvwHnExkismrmU/SKQI7aJ
TqrLZF2B+Ry2p1aqwi0mMGmR3CVVXepEyrOMRnfZltd3D2wLO9gR2rJcYsoo2B1w+D8PYFDOYTQn
YJgJRQz31Hq+bMuGJ4JuLSHfK+d6N0PmB6q9Dc6jPfuKVfOBP+6kI7cN7N3E9SHBJ7VDuXCT7OVH
YC0z6bmI9nRW1+Z+u+NgZjyc7M3dI1MSGY4aPH6MeI29g5hS7rJnPLvRfP511RGO6gPNy1jA0QJV
vn/0UF/noafNlPud+kT+TnSk670OFSuHixsWHt5DMk63N11I6jr3/c3bX7hgCyq46UgxUbeb/7iD
Ggx1+TV/BIz+juJirHhCComVVklrj4PWYcPM5FhyjRPx4GqZ7uOQ3pTKNxFWc4hXPPdiKGAjz3Mf
UN28j/ryWPJZJRJ3/5Lk5QWRv8osMDFmmSYff9KxJ2H/C4sWhyDG5iX+O4JjGyvEiKFKz568Omfk
S6i5qIAHQ1pXkukrbtrt9rk6ntNDUlLWqc+bp8aJtNFjhvidh7/EVfuwGKU1ab2XCGHmDF8Q8Ibk
gn2b0owGkEJvIJ4QRx2JGhIzHG2KJo2fxXDYRBIgveOivM4HeO31aZgsjfc3POM+P4GEGVPk2+tD
+3aipEYICJGrlGTpBTw+Rgq2Zy0uRRXy9QFMfFl/dqr3y/PR7MAZw4ke+BSiTjpq77UcD+ZUHt/o
r5IThMyU9uwH6hetHqkcb1df8JuG3eFWuB/9lUJmgXl7jsvAACLazrXb4+XU3+SQ+L/u+FQtCesX
+lLV/nJzuVzfIIqIIPkKYOSm+SA3uZ3KQbreWCRfTQhoW6Kc1zyjL/JR6mxsQNp61z/SuaYBdAn9
Qz1X4oWyhtGloor+1kkSUr8NCZ2B7PIF+oElyQPGbeVlDE/0iRzvYRDoBbCxiEUb4MtjJkmS6h4b
geGMTVWGy36Tg7N4fL4qZt07qp2wawuEmyr80U5b+4gPGjpoZjTgBWINokTAEQweDvByx+DQrLP7
TkQGJVR8uS8jR0OMfuukcO+lsAgwhYFQwILHZFOlPRIJwtHtf3q5FWMdHGhm8IrQSHgcxY2lqIdu
es91AyqcDdXd9lfjY9Xfj9Zf5Uu61SGXRRzwyxDjEu3Lnt2oJSp8clbrgiclH6n6IXCYcWor+/gW
xdbWP+LYsgOlqiwmSDhtTO5OHVtdZzrgMhWq+gmFbrxrbCTS88aitOeaPqXgXULJgWjqMcRFxKr2
Mn8UYFUjLHBLrHNBMD10+++EquB6qAV+fEvUTWxUjvyqdboQkjCQAlSkkLwfljDXhVd6YrNvPFof
qJo94bmgfhKX6wolRW2ezoUU4Be3x/WiYKiWvEHkJHH2yw3yS6RBGwBfHIoVk2RtkyrZGHwSpjah
SlTJeBHM57pEUnYoa5Q4zTPfPY55tQZ0Qs/z3Uef0RnEB2heoWugWNUwf5Jx+ihciCxgUeIkVpyk
a6H/RqOxUfeTRgG80j8X5zeFobbEEOO+hGUqgCNkIQkCBR+awFK0qP1Fgj8+pazgEgU6KQ+PKM+V
nNrkB280dL0dPBb4nyDZun61IG7nxz46tryJmOtitDVboKADwHvMdfhPXhHA+2HHZOSwh608clrh
27cChwROmvp8kTGMk/PXaQrA2cAEfFEBeDCks30vcYvTesb7icGR9PmjlGamYm7tjSoynvfMiTgY
4eRlt9zReML0Ey9rARUfPTKHQT1y5QyCC9rtcut0dukTJDOXlN2hxk9nSdoryLjQ2/0UPB3BsLym
032qQZQGQuvUbpPvrB3I2shODi8djMcptvmwRQ4T25VWHIgicrDPwe5HVEy6I1gTB6e27eiuIfuy
T7/raNKZt8GjeiEgGXwsTvRw9qcRI8XuPTO7qjowfLSEZR32jQQy11HAolL9v+OB2vvVI28M9g5Q
Jf+E3z9p5mhqd4XEU6GaTS+srdsER+oVzOUcBsKWPYOyccCdRkqicS4QAmwm24Qlx6Do8QaBoQSk
+S+g2lJuDYfUSUZhrOJpEXiI4tq/q3ypx2azl9mgpSZzKKysFsyqBdjBqT2aAUx+dvK3VLsRZPE6
V/7RWJEkbliJz2suDnqHOhySLJQEu+V38UJSgdCr+5D4OTZAEwi+FT1t88B9tIXDQLHFMnQJOLd8
amCnOso5CctFtxiIozoJ/cyL+OQ9J26+MLFgvizEWLv8yagQJH1m6T94vktq8bAVV2fgviS8EUdd
fCeqh3ensVnOcZJpkHwNGd+d/eyT6MswQHJXHSI+xPT8HxTzmt9LL9/Ld4WpvmJzO2vxNOKY/VWx
/GuUpOkxS9K/s7nMaLl0EkjEeN1PcJAz7nNheXWcejP+ZHG4ZeyLJz9bYiLPc6DKjV86Ody6xu3O
CW4Rgc/US6rC8mOqStDUgMNk2ur+PU49mHfUAWp1F6aI0RTklPA6NKadoZkzt+mAtdhUMJyjkqu/
jLQZATbezuH4JdUih/8ex6PJ5UfA9ynSmpdgY5/9es7oRtBjrEWXok/znvEtrpI5Z1UciLrt2N6Q
FUpRXV9OGvBKGqhG+Qog+wOMCD99BIe6sCwwS5rpGkbXU51xiGeFZrBJVHvjS1lMZrGPFj1jI6vB
tbpmhRogeV1kjPGFf1OauxJ4SHbyaQNl88EFZnjQcHLl6rxe5E2IoGHng3AM0VH6ktm1FJySsNBU
vighP8F/VsWHcKQlWx5+yNwYWVMUkZV61awxTDgM1/B8ZfhrCPbqzDDU278P5Eu1oQCaEBvUW+cZ
d0RwGyyrWuph/5jH2gmOjXQ3SbsmE7QE+2kfg8xXmjAQBNOCHOBdOINHMWuaHjsfddk35IXxEue5
x/tCueJbLhLMcbspYq/7BrFll1CAFLjpgp5rwYfK/OQFbkqqhy2TsoXuRZv8zdCW+1kuayDBeQ8S
SyP6YnAwcvMK/xfHIPP+UiF3/FU9juboiIZBnv7dUfSs3w4LcbTeT6vDDhT8xv56uEQNB5RXSr6r
Z6TDx6HypWo4aaHe5zyk29DBVNfCwxm1/6N1mvoOUZGez+v4pG1vHMgLWKm6a5oFEiMLeuaYVCMg
p2AyTIRqnniVyIOfplOAKOf4D7wu14PhC8KquuYNwrEeRkfv2PjXMMrD9qkDmeRXTIlqS/rblubs
gB4di+qHHMLkL1uP0an9kJGeyQnmvp/J2ovcDo8+AAMz5bn5r/a6behg5rEKY53JAqmQifrrxpfO
8h94+k2fwEL02OEciBIxMsi75vPtr4YCX5odZRptEnVx91pjss7H2ehQ8MSOIUtW4cxri4qg/XmQ
wHcN9Y+XVneXxJHY5HryiwhThTvmcaoBKkNm67JlS4J9HgX/B29Xh0cXOPfDm7tXG1quV7OTHpXR
UrTZ1/jg96QnfSV/62VxU3lGz7tzldVFGZ0N+Vv2OgBeFwRlWMQ0sm5UzWlUPiKyzDPh/vIvkStz
/J/tP7y5C4wLoSwVaCnJflRHjpIW142RqHfPclObZBvvrcxH6BCCtIyEkPudpW2ja0n8C/M076M5
bJHotJga1L8kOfv5zOghPX+5SaWSLFFgCh1uZyTw5G6f2fhV/MZAvWfyNX2OjYL4QQfjSYmboSc8
AAoeQ6EXyu9cgekD6ASUhII/cu7ek/vSdbddSFGddkq6jeN3VAQmJvgxCLcqbwNH10mg38jxNa9y
ONRReWdM+6sKWBn6OWxpKVfLYbnHpw0/EN8rYD0Ku8GUuV5BesCDRAc63kJtRlw6WD3DYdqhHLg+
dUg1784xPjdWWsB+os8v2QGdNJ5odWlp9wHN75NME3k5OOTFjfcVBIh66O8FhSJazmWvCKEYfpWB
/DpZn2KOJyuWZxI7vag+rabK4R7q7dzdogrx1dQ+5EnXeCj+aEQ/pZlwO9Jw7wuDrB6PXcCVm5qJ
vEGSevHvGTpCwo6OM2Xz64DnPPPRXEcSjEbMfvv8tdQ8gEbHiaH1eh8Q/qFjaR4JnM95Gj3NbPEC
bJ6GzNdiKhKspVy6+qZrN5+xc7w4gNaSwn29Le7wtUy+HtDnD6BCgb8NNvx6Ca3DFLA5g5sEaG7h
1D+e2/9v8/A93D8KwMpvGBxEGUne6eXULjMyPnQuHKtltNsHAgxvYuXcpJPgC/pEPQLMhMeGHCry
bDVVLYWwQCHv957Jg6Fb9NRwdXMtCxTz/sFpocY/R1sytIul6L/1J5HmBssygExV69Vj6MtrG/r0
1LdUJwpifoUHdEEyJ7JIT7Kuo8qLJ3ugqVYXZ8wq47jXGcZUbF8ChSG/wOLRpbFUaPqjARQy6wUu
d/c4ZaJ364xin3HFqTwAPi/XlG8k2nQaMbHT2UCXk+Gxs/h4891FMhI82/HMGBdMVJ9q+k+MIoXa
lWJndlJ7W/8CrvYU9Z6GcfUPBytXdjbbva7laGsbej8OHEh690/0t0pzqZJKLyMP8yxOSuvZg0xX
NNlSfotAK7PRgQT1bY8yL6NBjfbmFm5+53TXpL8Fd+RXgCwZ6UM1LeUlHz5Jz+3nShx4uYodEdWm
nXPHGcWXpc/5VBRWrlQI2Rp2JN1Rk4zkHWqWeVY5xAMAfyxiu6zZTm31L9e9MzGZ6fHgBqeMhsKk
C//SHmpOta7bLsuGV8m0949o/k2VLhTAbGPy4Q6PGTf9f9u2a1hh1Dm4JQQDGqLq7At7UoxAImZL
5Nr3u6oy/+pLAQiWEtsmn8QFd5m7DzQ4ceAegW/m4sQPgTDSX5ZwMCrJ/0R+ZB5C9sPGF/Tsnn9z
YE7EWM+Yz3gePW2ChxId28d5VyWUpkgJIPRVjYuKxQ36VkrvgcV7H2h+A5KHJV/gP3NI7kjzic4O
7J/9xGOhTWFARFdHEMErK6Hn4W0v6kHgC+i+CVlIl9Vah4NxOmKlDVPngAHXHRk+09OaErSegfbZ
4WMLWgPQfNj0rfPosEOee5iF9MoSN8f3Gevz1/TLXQ75zU7M89mv8eg2/eSwxc8lFK2M72OK1Rb9
BgTlFK9Sp+xPUzVlcjPFkFK/mpTxOV8dnS6yQklC0H4nt6s+kqU1OK6eDEDHXn9TOto+w3fmU690
c59Ohos+3AP0eKtUU8uS9L9jrscYjQ8FuQU2REizq0EBlhh/D9dj8jLjrN4BzQEUAw9a0bgN4zxp
xymrCQzyfsyzOUkzg2H6gMmW7aY+Itwv0wFlPY+dv29UxriacV7Roa5x/9cF7EGetnvniK+U4FOG
XrYHGt2rC0Txn41o2TVDEHcPHrDjRQ4ZS6N0CsAPxWKsSy3XW3NxYcQaI9j9LoZxm5Up1hYiTuV4
E/gZeDQEHkR99BgrAMwFi853C552psEj0l5DInUwPST1X/j2wkaG1UujUkm7+tfUBaffmcnv2UNW
9K17arl2bKv6K8GpLTjo4p7BgcBxxcyqMPkR77gjTZjtuIE3J4iITTTHgeGD4CaYOU1QEJNurXsL
Mr9cQvS6n29qX/dvqNIc4i8BdHA3aylnVO/6cJH0ef+ab7JNdJ0ahKSjiljEFNqDPXpAEKwmZRWG
0G+IenMF+l94vFS+vJ82WQecLCu4JjLcacdtMy3yzjCmXneAqL9fHmLbL8DnvISCf53tJdHQ14/M
N0D0k+1uuE1cDYy0IIkOXRd4fiakh0crREjjbHZud1Sh0gNR8tlIp1B5hR8qQrqvjyLQM2cIYcTp
3BeCD0wz8MH41jcHeSLPNY8ni/Ia/wjEaf6ibNMlCvCoEPnqbtLvPZko5fN0YwKkzPlIzaTGLi4c
RgnssEGlayN6IC82ZQttghJhLmvlJwUsGIaoE9q3cx7sgb1wRmR/xQbcBac2dvlZG8b0aIjr6kYx
4Xz1/4Dq/pKbXLKpITsR0hkHKRC35aY/6EHcEtayv+FovvgqSL6b/6uY18MXQY7RN0HZ7jaAakf5
Yvl/bUd2wx4XEbnibR7ZIRVKRiqwCY/7gOYFIGv4+j0/L5e5RMDwhLaLg692oreEhIKh2hxPU051
18eiI6RlsYqhXbUT8kWiDtelU4L5Wfas5ETZVzAkATqqKVvNfxfup7Hk+71fK9okxLoU+qGd0yy8
bFXXW1WSPDv/CS+ia0OMBAI6ELLy8pgvgtgNuIWxEUPNa5IESYwznzlPplZY4DdQ3MRND/Meye+g
36w02QeINPz5KL80FjUUEnKEtNOCJZrsRlcaRNC4iMD60d35oaxDpWbhcv8Oury86+x+aAds1M1B
dvo4IKRP9GHPNY7HYezBsVyRGS6+GXyw9E147+pZbCyzUmOUBWUd0UQkRCCFoULQUcbbtRUtqk+w
dFf2L5iURZ/6DMaUeIwK9z76SzYmTt4JveDEgmhHg0bJTBRvBgbZrQNpIq/jGOuku0+gl/2Gv/Dl
AGzzaQniAM8fcYLP7gCM84FNZifXWVUunWqiCWMg4sRkJr0as2zdHHxIvoQ322t+dNEYKk5dbVST
j1jnWKp+U8uPvWxMK8MW96kd0VLRzLv97ii7K3IzxpQfYZjy+pO/IYIR9LnX8eGKM9oeQgMlEenx
JhkbpZWvj7owsFkxPfp4v3Otje0HVInulKgbHmXU7I3Jp62OQY/h6yTVzeoq68GLN/A8oe8T6Rz5
IJmYvhQ45OfF8/glNb46gAcjyDb8ghQyngTvC2KXq7DTesPshpdbkr5pfpGzVUltgWZiZDJvU+RX
lK2dzQMcwvqYl4v29KCu7tpFPUUSUwr+17osmRlOPr2zOWXCGWobAmqmNzdho7IjEa4QBRcIg/Vg
1g92Zaza+HOkrQ88X1gPMrE1/NKC8kdtd+L24ArQA+r9RnljTRpitVsegklnOH57NPjZe/vc/iTg
U513oyCA7s3aWn1U0oD3pLKeXM/uOZ7qkNSvMQ4vMPgJu4iH9rcVa9WVZ0tEU8TWioEAzo44JjH+
kiuf84jsrVNzw7qYwBUFz5PJXNG6yLvK/a60AqGd4aJ4hM9u1193+YrRPWEEo0a7QLwGZX5WSvK9
xNkvrHwxcSnFhrHGa1Tl94DNidk/hDQ5MC9+oevVX7v3HgvZ/IvdxHpYYfwMRjSvd+4ejE7hhJXm
qyD0LgHJIQ1aNYPRPC/2Wr/dNoBzs8BrNwTgqxzbhZ/WC+gkFSZ+s/IkUPY2B14zHbyzfj/oGL74
FdAVo0ewjDi3QSO0xuW3+sAsqAf31QDGxSa4UvxVlKUeteydmA1iFa9KE85TKj0xtCtgykHMj6ot
XMHvcAw5MDGbNtMsTkV96ychhkm12ITx2L3xz0zv2j4S3tlGB8bi+UimBnK2H41keKbT6vbhtdn3
sZQztrG3lZsBZ4RTAW29nD/FnoSNPjCLk2CSPP9zLvZSpwyBpvf0EjWa/ZqKRdHthhFh7XCNqlwZ
PCTlaqOig5GlsJ1enMqDyRFUj5GpOlS3XYRI5owSaS1PSK7K68OlGEsSNK5zZrk+RUby5TdptLrW
FrMFfw3URjPiAhiODWMXFMxxcEbxDbfLU8HlotEdjCNwkrMhRPyE/uUpxw4/uCEl4O06lteKGVYz
7WmPrbWj40Q4bmWPm4xLY0i2B4a4VGpW8LLwcU7d8x7kiQ+ZZfUmEXGaklVfoWZmSEFg3PUhLiUz
8xSMGeWAUIoJhuQAC7f+kClwIKaM4jGkdo/1Q/XWoJyEeNnuCjNWqTXmt+Bau7aU5RfbASuy5x4d
5FMYGbRhOTCNupajdrChShY1lzKd8VlmBOAYdKTOGzULqjJUPRqTnVVBxoExuuZ80Gh5egGPr6+9
5OLKsZXZlo0HcMc9DIKdLMMs2yhCRoVbnaRMnnZ+kQjUIk/y2ROyWDMb/cki+sidU2Y53OGbPYYg
z19DvO0DPsDLpuCWBqGyJ/LKBhVdvZfoTzgT0nCRb6SIHkro3jXILjFpZTHP0MXcOSlFWLuXUzz5
zgeMH5rA7MibTgmN9/q/KDwyZO6v5cWK5RQjSCZgYATw5Zp/RyDMNGB0ZmMIMClLku2ZrCg3Ae7K
PYvM562XtfthYRrJP2AvJW8Heg/DT4JHLKBwWKX+AgQBn8c6xbaAaAEDYpkBUcc1jf97r9eZWseG
ajou57OAHhvaVw+I1RYLZVXmo0IQjYx8bThSvFnXAIjVZ6loMlpo1KGGmF9CcXJ9IrYOvLwS4C8d
Il6KFkmQgP7lEsIbfygBQTiAG6YXD0hTNUfQoFBQGaIGs3ol8/bS6bZY3GM1fFrIhQ0opVdzSdYh
BbOrsoz0BTLUcpzmM3jdSnbi3q8fmje+cC1nRqCKQD7q37G2TwWcYUWnDHXy5gN5G7+KJg3nFYwC
K9+PJ/GVhdDe/zBH741HWM3t7D1G2jq+QCEGiBKqN6sXEc3a2TCCN/8ALEiUimxYNnW9ncFX+H9+
fl6VarD2RsT7LP58i/+zkA7zPGH9Cu3TFRmImt/jOo4f+ZMhHh/UfZuXt5YA+fnT5xTniIMjPl64
O+DSOYcBWvwHDwg7hRMaoIXByFmSC1ARim4CX/gnmlXrOi5brnt46d7oSlR80W5wJsqPE66gVmHk
0jbSCEBW2Kc4o/8NeBnH5XdtQbwtjJYdzoKNAbDWFZL0e41auQ3LM9v9QffLY7ILgHJn5nM1Mb+D
U6v/FvbohAhjO7Jmyxf3OzkpXmTZZ9mAV4NuYe6LCZ+3rU8i79126Z+WONJ8xh7Hb5o99QOzdy+J
wFo1To+blNSJWgGYX3mX2JydBMJuOiV3fxRa+Q9ZMJd7KFqmavtz+CHvS9c2ypjQW2BnfAZJ71if
PDiZ0peGC0QKPBRN3f9xOXfrA6lMGm3K6dDlX9ZCXs2TfpDlakIK2Zd5J4kEJAMsarwyyO4VK7BY
GJNAKq0iuAL3INXSzVncyKXYi7zix7TN7HXSWKgs5ZBpn2VAbUzdRIyImOu5GX9nYmj/SjLQURA2
9+6dHzJC+z67tNroCtoFSIJnBun8rfIOIvyRrupL9iCsoh0O317pFlWTOFSYy+czqlMoZ+fi+rAy
9VGA+PjgOFoXQKOO1h+RRauRHM16F4s4wNaI0uVJNPiSZj8eF6JjrYOvpn9fOU68u57DKQi50lgx
cm373KF3Nssl6uuzX9oZi6octDQArks53l0A9KgW3rn08JfyXdqN20wTGfoB1vZxCzAaGdxHuv1S
FDL8rWFBdrWv9h4mbMQoLnoj0Kt3nEnibVqQVVxnjBSTFKTJK4/FcSIHsVCeRoGZH4RHKQ0DVCa8
ef7NGEqZJtD9DvDErCUoLTE+Z/NT1td3rrOqWzL7fVXwywkyrhd7x9CwUHD/liV+uK+tsh22vlMG
OT7C9s0+hg+8cYN9YZPIgewQjiLJ8a4q+9Q7WWnlt+f1wCSGrfnQ9raxoSnfDFnaqN1X1R6Lp+DL
gBkqDvL7G8HX408TRkoAnAUO/AqIwJQzaU604eKG0I0/Rk4dQH0B7YMxm/Ar3sptS8/05aqvwFjf
Vvc+/LGz2NDiJ4ocqjjRigG6s6Dv4sfdNdTFy6UmRS2J8NEZYOKTpAoVeQJ3ynQkBXgjzRmpUiV4
SpsygJsZMXKoJrJ+wSKNWGs6Bmy9DcLGvBj8r1mkXTyVpGKfyqM06CN/zv1TsJEPem6RL49lA/fn
mpmGi9MI8eupmncNlexl2Ve5jtW+31OOzarStjsBZ/VHqRL+DCjBFykP1Wydc8ZoPlUUH4bTZk4p
ZT8RJR9DhFK0DcOXhcFikcWNrLaJ0RXN+3QoVn9zaV0axoNDVYnxB8b8llk+bdk26yUkBurKNuH1
/CetMpVAhAWbdTexIdHt1Lc2jm3QzIL5+BMdw6l9iHm3v8vqH8lI5QT2IPwhGji70iYgPYhaUyr0
ur1Eg+FVe4CksTjOTA99bdSnZa8+MfqqweQ37DFUg7sIpnUFe+rtkw5PpgbdVTriRQGgcVMJGHPE
w74yFW985inpN1J83e3eOHb9SKbpy4OCnBCde/4i0N1go0paQfT8CeePWEn+0ZwEkgAP/ot4VAYu
wDi3q28NS7qGYK4duxEHeCSAsdkdRn79dlDati2/Rj5QX4sD9+48OGTjM5Z7w7lIFCIeP2fbSFX+
HjM66UgmPXAwwReO/WrpziI3sbRFPHAI492uwkofC1aPtwRBpUG+nI9STYqavYmaDXjI01MIKPtl
kmmRS/80sORyrKODJ67tX965qlGyTXi32/K96jkmum1pB8bKQ40wKNdVTpnAzLm1Ogb7VNXelJ63
Rii8vlNtMlRqvmuMywX08QNzihF95/hlJAMtc99dpznM0kFJVPIebyvMaFZkIJOFDvoagpfA/6Nw
0LQoY3kdiqZsq2qqyzzEbXPG/2ZvnAevN4RJIdj4mUnPlMBe7oVvmNUQT0tADZ/yXYmfut6fV0Jg
EUcui3rELzeGYGvx3/sLeMqBsMb6wnuQVa3DGOQLQtIGxB8DYZ43mhjkQWMMzuHHRvrVbzccbSjm
idPutbcBBGdxr8jSE0vKEfQ5XteVnbU/Z7RcullHwmGkw0ur+DPimr9DGf9G+fkVdDiFKgGhNxlr
5CaFmZ65jDOEqCCvDOUu6nw9qrHCEI7v3RladEE/A6WeoljM+M61NafrEoWZ/6f6LU/dm1C9L4Lo
O7mPKXQe/Yp7AtyDeu29zV1K2F9WLQlNbb1Q3FdXFBBg4kj6nMjEqATX77BlHw6pi7FoZRt9kzkX
MAeacmrFBz+fpGQ3tR9028h5bhpo050v6JX2iLDEIbBz2kp6t9M75KKNg8hiKhbByCFuxWuxG/RI
I0YwvKOoX4eecJZn1aw52gotCNOYHurLu0Zt1NKq4DXv/5ECr4ZlQMTqwdhmEjcH0+ca3SUqhM3f
EoiN8iNCYKl37j9Wc83H34LGonf8loVWYeZf4uzoVTa2zNqGtF0++IQsfqIszO2dQ6m/GjWVez/r
nhFmuoqMCH01R7zAUNyy1gzfyZqOSV5p4aOA8dJIxE427BSQMs14EmvgBV7iCMzU7tDjhlBVJZjT
1Y0jT+gT2Y/6KQx18/xhUPGWvJADpin8p5YCtSCnz4iH+/BLQXvAC++RcszNLgvWSrwo7bykcrpY
Xy1SMYXCEqioKl4ZJunYeuoNM/QtbTc0QR732DT8+w6v2n2QwvwmMtIxViFoORhUIlNiQcgN1cVr
oueMn1868g4S5+b+hNFefYwkqK5IrBdy5BZg50NfHfWv0J6gxVAZvYyZWqOxcxXC55yTSdgaCiwI
1+uL4RDiMk/fTX65EYFtMg9N8VN92tFqvxUgnFPbkgDLjYNIgYIZK3NBFWZTkV2axZT+CCJ1Zul6
oiO47h5wNuZJCUVczqC58NwQb07OX0oZ4Ao3nIe6PNkiJlHOC5xCRrXKLu5ymoexbzgIH2E6CQpH
FW0nKeKZtwww0jeDW6jCdp3MMtWAnUGJZHvrYMeqkw7tP4QQPe7/+df3YeCeRyfJbUR7IyMLjKi6
u8QuvSdSq7IXg3KHAxfIwSldfsARomrdXDm9dCBmuCV29Hc7OEEAm0JiKGFq7Fe0c6bycCkx1lIV
P3fjBvhEJfvMCc1ZUSbAgPcQvtrr9+hZh9DQH+PE8eNvnqCedwTGKLcFKhWmA5PeLVSL9yIHP1QP
ok5VXHJkqBkZ9Dj8bsa/5FZWXlJyI7YhfDedSkRgOtM/hlJBjtIhkTQwAit0/aCyQFHKEU9H6rFS
LD5xZXfW7A0N9rLBVZzEvoo7TNGquCGa+Lqd7IuVFt+R/xhPAThNSltaKTfMJuvMOIyrfSpIGlq8
xkWbGqJhc2KV8G0Pu2HUQtznxj3gcBuiPg9ZIeOZrIDrsGJFu72Sd+/k4li4ZeCIMAZMocllcL+e
cmcxVMW1xXoCOQ5bnXZec4t2P0qWOQV27pcPmswok5yvh/m6k18JDPH9+4Az1F1eTEoZlyz8UxYA
38yh1NqIbKzDp6IS1Rhx5e3jQTCswNuNf/ViuaEDcvSImFJJ4s7KMZavy/bsv1OLAqQBhwGzph+0
NNI2lvSC0j53SqcVC0WE+rnaFo9xncLBYsIdt23S8e+6txqAK9FhBmYmmNX1WXeTPK/FQWaAkx0A
hkMiZ2v/D17ebg58MUWVnrmeezJWrVlBS7elSjnsXVxdkzA25y3yzQcCGVZBI5kgcqNpyms/9O8x
7Q37IlnZzmFw9NCICUDNWCfmLlsilw9I59pZhsdIGzUkF1KNoQQeLlPZfXQk+Uo5lnLU/9pnEisC
rrqol0sCwPMiR+nk+gB6WeO4APIHi1zcQwLnEsZv2OzQjY3oifCSOxWrynPwLvU6L133xEd4VXoO
rGrQYOeQrt8u8bhUMcNbu4GXRQ46L6DJ/MhfvFfQMK3cmRGCsZda5cOD+McAZqnhvXxiQl0L++G8
Uo1rWsPMoFxTGMLgfs+w3lSiMRVdr2TmraX7tlP/n85hitp6tHjSPAgZEH9OtmmpPJHe9B+vWht0
FfFy6BYMPl+HuPbL+Cg32A+lERTj4vsMGGlacNp15XtobZ3Jgr7BkdECRM1g5k/z7peM2L2W6mOx
mqgJEjqT5G9NdcVkVnwxiNdNNkc99yOrTgzw7/lhz4AAHxuzIzRAPkQvMHcrJT9CtDaHPEflIMTz
Xx8U+Jv6BPKs+hZ2FnhV7Eq7lOrK0JQj8bLVQiwxPo0o8yDzwVaMvUoQVAykqmHVnNVtRGGfnK4Q
tJyJBFYNI5gjuPD/XmdKky8qa5cczz321+VjNpj/RgcIA25rzmOqaRZ0KJsQoHOA/52PpUYX3T+J
g05voPwzSWlJktWJQIRCTcaTjDWUiDMDa4eATlWqQlySb3rINH61sEl+ZeIdNhW/X9Tf1FiMFh16
knYvSG5NXjwNJMyCzlyo/nHh/VmkO88Gr/dhuY0u3XMXJxNKh6ZH+hUUelCWLYWJnnjSF5JpkDYw
3gzfBQrxYRJ3gFNMIyoPKncXnMlZdvz1Kco8k17+m/AFLEPEobS16W1M+FwaztiUPqTwb/W3pUQ9
kqpvJZbRTeTsyV78Q764ovbVkKXlzLEXGN4tPej61SDVa2/P8AArRonfaqnbQIn9AEyCfTq9N0Vy
7fmVLJ3mLEZa5GeLg9haAz824IUJhKOUSTnMLNej1qVtyxjZ6M/rHjIYOVgRxl+Mwb3Go8z8dx/i
A0w2XKZ3omA6hPycDcwgk27sclK5khhy1geoy/N/ecwiTP93CrG20N+Cd+hN1uU03B0WCBfDOFS+
gd8N5xo7+VNLgJR1Dq88saDgncCSj+xDIvzkCumCiJtvgHDsMMKaNk6VtHieBDczCYLFUfPzogXn
pNyH+e3wLEkHjsxsa1wtY0HGD2c7e8dKLtJsDjiA7UfKhNs3agstoJvvyaCzbl6ys20tDLEaxt6c
DVJ/Ou5WOVk7NSTx5umvBbsF544R3YsINkBiQ7IVSPXgpjuw9KIvRdQloyIM7yJdiJ1G3pxszmCt
En70yj1gcvgNcgCXM3iKULl6IuCtf3bkSZdH6pHCU+YTD91zFaHLEqXfrPsMOFPyRC813MrOwaWK
CTQ66mM6qat7wKASrovjtJ0QQ3KHrWz2pjA5duxp1BAUYkQDvKUuAZsGFX9OBYUEV0qJDXNRFR+B
TuMpf6tCk8NCAE7F+g01EvudVeZExnVz0yPXmilZT+N0fbFdruWarhuXyOnN/OJnCNQAEN8L7kQc
oTlsdxSHdZYfeZnQssGjpiwmOWzyZpg7i98h+iH7WT6sIrvSdA8GoT0m3lC1epKkv0PJmiNbNoXx
R+ypWOKROx4dDrw28koHWSrm1fVZL/f4lkOzP0zZsXDhupiVLnpqEKvdB010ZY4lS3yvgaHkd/js
RSrUUFdqHWlajJBZ16EyJsP9xOJDC14vvJATJ7jJs/ImcUk2UqVbEJCZjE7MLf8ZxESiyqsVxl2i
bHQxyvVbEud7eVwyex2uvAzHdO3gE93X+R1HAUXnZpeSr8MSaX6A8SSjajW0PcHhj2SRBZW1jlcP
t9BAB9IqrdhuF3CP8xkKRXU8jrWzm5kSQ4iApjV66Wb6rCbYFvbgVaYiZjFp0CPMn4l9bPz3u5OM
0fco1Wnf1fiQudxH5wK8nria2Ly/n5qNVHjusBK1Co9Cgov82ZiLgKc/GHyTqSG+xCd4iCtjxUvv
3GKwjvBzaSFAkb9zye+2xkFv/ckCzThFkTTeoSkvIQEmpCHanEvVu22HfEtvWMQDvRn9jmWLfVN7
JHYnfzJyPxn8nI05BXxs9hGHUyw5t5CFZ6jxdHu62gUuXzfKQGGTYSRRHUx6aT8o/pbmpZd7t5Mm
n9WEoCDlVYjBk7+aJOWYcTfcDmG7Xtu5rVFOv8VaoDEZw9dd5KR/hwrr+ueVNQhnikOERfGQk2fl
aPpe87eDxFTq8IC/zVVQcVHMshnFkr7oqicMib832lAGypvZFN/Vh30ojYu0niEdreNdIdJaYbXt
ydPNW9SxJ5FDyXMtmc22EhkHvXzV8vTrKs417tZs4xL+MVq5mZ1E6JXdD7XTJkTeCiWl4K05nmIX
D01bBN6v0IcSdZlxapOjvvoKqfE8e140OzJxIBYMSbEd/ZGJxZMTdm82fSewB9xqxiwQsMwhfHwp
ZO7iyvF6aLrn7T/nXnsPyCXpOsb1yE9Z3WbFKQBvr2Pk4PM750CBY/uy/zF1+uo8VVmyL4RzjSJU
Bw09+p6xTt1LIAKLPLLEBZfVEN3n1uSMj/dpBMAFlWh5frAT/vtVf0oyLKqE37DMsx/2XHjJenqe
Dy3I5dxeyKLLGEu45N9suP0a9PtjCEkfg7nbLMnlpY4qMfrLxbBIhz5paT1SwgeBRbuHiC/daJzm
S8N6QyJaYTyhtCJ4OUWmYc8SCQmgHvKGjxgbqjBFpi1H7G+OSR8DE4afJmDixpFpC/g5douXxOLh
TzJAKpWbw2IxHfKtRl0I23a7dSS56SbLo5LPm4By7d5ZTiIKXG2v79mRvGJzYiTZZl7GJjDvH+lO
q/snZHqFP8ITcDOTEzPvK+MoG2ZvrUh+XZoPXb0UcIHEjUI/Z2S/VTYbOzaBcS9sQiXBnkU8DfIR
OjhJ6BtSiMXD2g93nh1tkt3e9EjKKNjN2e9v6ZAptKuMaeYPV5QoIkWAebleZjQmj0Yc/E+dQVaw
atsgyV6YOD+BopqYrZKe6kXka7y06pPzi8zs068XOA9HYWlzrjtr0oO7LRmB9Y7CuJWFYTUStzKE
JtVKHuqo1uhNvxWJ1foKIU1b75R0Wa6kamWKKPO3XtZwYzxnxePIJNi1O/lq+R/sc9CZFSjr+K4D
ZOCnAdCRrrzcLuikBX4A3XDZBcG06Kfm6WKbmVxGu43QFn/kZQXlshP7io9FHJzaMApleoX4NCxs
BgnkL1OStREMk85Iged5O+wK6jFDVlXyFRZjfU5UxTR912vMmvr3SSzcbKNUyqKmQ01LEqdhne7M
p6AARaYnmOS0j9qL9Ju5o5+jdbJBqrNY/CZ+xbLA52g8apmGYmZlYDNUxdlUKHm3j2N0jyh9ok+j
KHMDhzya+Tx7PHi+FBBBeeqoB6wm79YP01URJjZNAgo97R7kQTur338ib+O++gaCx4ytGwMXjxuz
pOGnpCmcMk7CkxiM6rBdyuTNm2W+Q1XPtaJZIYtw4K29S+QmAaMrZ0XOSzKT7SucToDWeo9+DpxJ
kMA2Afgd05olx+Qj45ngBB4PQ03MhIlS+Yader9aR85Ok8e9S7zUjgO3vJt5eyiajoBQZFMv1sz4
5efK4UPcF2jKv4IPl9T7uG2VfSXoXdAkCTUFjql6fZKNGDDRN7U7iaAL8Z2p/GHlsRh97GR8KfHE
iAa8rSVGqL/wC/yeUI61b7pvzN44v18QTTLa7ZOEByERO54YDaUFySNGDqCTmRz1XjRt7wY6UtRZ
Gg2vQoOIHOh2JkB9rbBXq+QHM9MI+6YIzs4mWj50yp8oO064+O5maOsGe770VhFB1c7N7Qc5r+v7
P7veUPnAgVUoDloe+dWWbKQpBGGk9IAGl8J2TDVlEiWdzLwOtmT4npuusHJDPZr59axilk0YxArq
1UeH8UWwdwOmAe7uvmfLLQI8EcAp5UjDtpG25Gx2zLtEXe9A+umTSacEfPbSS3mIpTDnM2vKzokd
QxGoJzHpyZz4YFQjwKC07+QRZiyXdQzOul/AiFCS8LQ+VBMKGaxmVSPgwC0UxkNfdSvqvyXj5P1c
Uth9jWACwHpNXK+mqmVANp5MhUtGSLoigqvBb+1JANvo/+CSKsANlyRGGhmhuif6CBikFM8B8Pgg
/khgFozYkGpxxvugswkvUP+vbFno3I+G2irrBg0iYxj5nMQHNGGNyIRixxfKLloGDPYDz7cR5JeU
N/T4bYmVHdVOUkH93P0Xza3gd3xNHBptQyYBSq25cMp4MueYPkGxbPOat9rVvoSzo5qq73cK0v80
L+qSbZ55qRQxWyiGNFUPFB/O1p7DvhIiOkVnQW4umjd/hXRPgSDIasMkkvJO6mQQnvtEsRXyxTJU
6zyIEl2CWyMta63JHB87DfeDNwRzyFYjcO2r8GwRDQqKAPSoRhDqZA3sb+0XyWRy8Q3IqtQGA7aZ
1kUE0eOZTY21qW3uIJB3CTDVzi+s8aNMvR3Q4feI/V70r87lox4SyFzAyb9gNWz6cBJkhX6dWOtD
9ffT7I1quGXVkBWVKjM3RVYq7Q7Bt9HXXpMr3bW5ghpwcbKiQvvVq8VCS+E6UDfTzukWstS/Wx3S
LwNbFd4hBfAW/ItxjivlL5SOxKfKHzGHdRZLOi9QIEJl/LO7TSr2r5UUXebsW7ACOipaMptoRZt/
3JrlsHMczZswvRKdOaoN++uoyyNEJ8RWZkpNN9iOoMtYMkAecaFFCcc1Qj8lpOQ/tkQP1vTQ000o
58UbURsdrZBSkmKgijUUFKwUMjnxzyj8ABABNHn9pNWbOBFMAaGtr1xgbeov7PIqzjncplrT2v11
EqulqKA8Ztb+LJlnnKYinDJCeMqI6mfI0xwdc5IQ4uaKUPyH5eR8DGpSb8Qp4e98FPzKJ5sI5tVl
C3r1SmqDey7/2vlLP4mFS8zFCnNYuyxIFBFX0YJbvTglkVMxjDzEG8GlEZvVEny12e4V4TQObngQ
k8TAIJhp5kfynVsIpNnCl/evn6vEyPy+M93qI0s5TrvDt6Jkfii3G4ix0Ma2iKUqtAKXYPAYCZV1
XkaUV92czRBS9v2zhJs3bzlYP/NLSgjCyeXP0MmFgTbFcri19DpeL+QeankxLYFG9mnD4CQKOlmb
Wyo/DJ1Rt5k0LHP6Kfu7IwJIKPTcyrPOvNZt8XPibCbjAdvqIy79AicnlhbSFr5kFqL2+Qd34fwG
GHVO8N4lFCr9LL5MZ7VkVCcWfGLp39p5b+P0n2bZo025Q4ZhmCMZNui9nHBu2n6sDIDG2E1VYX8a
5c99vb7gdsB1WVcgegbkMs5Jq/BfytjvG9FEASNjdLacPIdnP9NVz4fT/Ea9o2Syv76DqHfb+S2H
1Q94+LVV0/IjUxzy5hCdJG8aaf+dibn0bM9In/Z8B4Ns9/Jb6iGArAjuAQ/Gs0HeUhvoKrnPs5aP
sC+G4CwChQn1jdhlA2vlcumX+msCX+l63lrU39u3Aq2tyhlm3aAtrMTgjhpJrfuTMOYhp9Rkm/+e
JbqD5AAuuYw36//mA+y3e6YEL9gHSOAvIXcANZdxPKu8M1iCpSWfgWNtuRo3NjpVY8N99Qt+KFUd
6bH6V06ea1VzxDhgpvN2kQKbdiEDq/A/xDg1f30DCwzzIA4ZHg1C9ewrhlt3EX6YUkQPLlPRtY1E
cj19VWapJ4Ce9PT2l8CN45zNNXcNiNcees7w1HQg/avM1/Z3ZIqZgjorxiMoJq9PEjpTl8LN5mrD
2YW2M4/K/fmZuypSILzMWj55QXO0JDpTn9jIb7ByaWqzjgFE0j/Z8YFBAjUzbizguxz6oNQ2Bdqz
fpEXr01msf6gNgZG7SLFpm9QCKmxoSb/LmK4kJSL5iXSWf5AVLKMeNwmoqvprA4OsvQtGSS+6k+L
TWtqiFUov3RvyLspAteOcVImj2KLnjpuBN5N2TWPSwxChfFK6A5VW1XbyG0r+0xwLgOXBnP5rUgl
RuXqgLNR31hA91E7PbmYJea+Sr5mOWknC5j7HcwJdJuaZCW92PEQqSR/fDg41CAu7YC5mLdF2Dhj
zUlEpZDdp3ArHTOaqcxfOm0ctQ/vF+Q4eAYV263f/wShJsPt2vpf42ThKOFA83WX/HhiqxgYy3a3
hGp2FKS5eMod6mlL4Rf9OoWFKeOWHEhCjnIEdQQ22q5mzjQvMQn8wr26fnzU7Szcyt9nG/QhF+zU
tYlIrRN61SKOGBT1pDzNWxnfr4+ECArG3tNfDBZozm6Zpry/JY5smlYcYzdQAgozguL32ispBCpJ
rKihyMOexk6pnqZnwW2VYy7A/oeNggwl+ct5O4CCMEUfg5jxzkqfhL9fLKHRO2DcD4iA2cXCKyL9
+clpZZ32pnVAJ6NSW4dRYP/bPLOs85P0dXr8fBf5GLJqftdGA7XBF/QbUWc7yYsmdJ73a+3sIyD3
Qp7Wn0Qh5rk718CnY3xtCcItM5QQvDjI9AfkfJwapZT+1jv5V/IDlrtqJ/8rO68vS+HA7S27GKJ0
XMvFzZdaFMBdo1suaInwF5gwwiZuKYiymFj9pTaZnqAD/8DZfSxYUhzvq28cOnc7mZ1iqNubYEny
NlahiHYsMtVbvzzn61TRBiIkUIQlU+i90no7P+rwm9g3bBNXrfOxduiWB+iWsSEukEjKxNo3wmlX
NzynIz5J+7fS9HnIGU1KtC+nC1s1ijhWOMl92JUnKd20R6hidZynGwyJHcGlso0YITuSy2uoDrdT
W/50n6KLF9q2+fT6wqivO3bncGPRah1NxAIIwfBgZ4YqBL1DwCnDFzVG20zsUNePQ+o39BPaXK45
oiMTSBdEwUq7fE3WUgBaQtMQrolOBG+yJm1hgO6mpXzNS7XSQg0LwOF8nsj/luOhShC4UxD+KAvM
z71NBeRpi8IloSiIpQB1DOYa2lvLBxxv+0AhXO7/GWn8bEzKVV9lm3C8WtndrbLA7WNfP+Wo9Z1a
v1AUBLLePfEujr8nTbiwKxBypnMuVAhBNCeBbShEDdAOWkWw+g4hlSC9ivqsuKA1bKTJUjLh58BL
ivM5dQUjwJO2pamP/uBP6vAFRHDsdltBGy3FurfMHbEOQ9nXmLl4oEdCVTVqdKZtDLt2IKISbSaL
0rOuPJF+hnXUrnR9uPRzpmx51xYw7hZKhHUgOgttd6qKcbaRRr1cI+6Znmz0usr53yX0nAX9yLmD
6fZ4U2YFxS4ZFA5+c+ZW8jCycFkz6Z2exTklD4gh0xLYBYaxrPBckueKtC+4meHuR/yNx7RD2QNu
IPaPT1mBtG0OwLtEiIwzXrxWbg+nvEkAK2/659+xtcDrfIMwtScQSxOqcMNhVUA2xvOyg5FLOMjJ
IMgKORZPu++mzguB08qMVvQiPUNnU2rqY7sZWUDBhdVyYu4HS22UU6NBllX3O7y/OSekHUZ3WI/H
wktDRmvKy1vF5AAR7C6J1tueYITdzdhMynaNM6/TRhHuKP0f2XgFOQmsV+973RKQe160s25ZR5AH
XiVjL13+E8vz8sf84qLo5eLtUVBnVYClCW6nWuOC8H5GcLmVDE7izcZnrBeoX/uByciZhnXbAfm8
HDoDIyx6uGlG80uzJXj+IK2Cled3/rvIlnI9tyjMDYX3wzzrMX5oY6ccWDU4oFNcDiAtnnFa5xBG
X+gMh8DqQN2i8im37ripIBJ4b9uXHoAveZvtAr7goIIImYk34DPBdOONnDFQzT22ce4+2SgTutcR
N2ngS9bLrY1CL8mZ1GWh9XHDZrVO7zuKYPMmxEgCmA8uIoBfscRITAfmlFLfdaKg+bmvPruPCnBC
ZSa2Ss/OHE7F5fZ8jiu1VdfrRQovpY7ii1mYX2lY5PNhtMSE2VbXqFVt/s4hh3CvdDqWerg9GE80
veIlXfHX5mxs3W7A7cjrcCmhIO57EGgIdN2T/YoYQYytCICaieka/5MlG2qK7bIkn5ngkNsrjUYv
qjCMleA32PrkZhbdlQGmm6VlCeszFE4zPX4ui2AlNohkxb5GTJRxv8hRGMj1UEPk7TnacE+VBRmu
dK/ZIHE1cOytw83Z9lOzeEwTP50LSTTKFGSQmBd1KSvMeGpg3gZa39zawQyzbizL4fj9S3O1CCfs
D8Q6vizOIhzlwx/QpBTXta5Pao+L1AfThO5sJjifSobhS+5ivuIMDhmAdN5ZCm6K3X2fN+nZHeE/
Z4EB12O+9qYbJzzM87xveBFqfhsuY0erTn86JjcwA+f5pLC2LkQ5nRSjBUdM1lGArG52ZeS8jeHP
WowFDa2c4Ahn4ejsemZ5puMHLsV4BhvQxCYdda4qSW285A4cPFb/9yiMZDrRIa7YJqVbEnuzXh8Y
W+pMG+1K9ix/+9aF2k+HJ4fb7b0VCcGrhzLq0+OrDmUOijesQhW3Nmym/uZFohgIVMDLN6jkZhzW
PA7hUWxjMlWXs008U3JV9ZCBo3OhF4ZJB1thuB+VI2CGVNASMdzet9g08F72Hed4H1yVsP5H41ry
Cmx7nn0abV0F5I+twKSqCg66Rthmu3itnOQoP5uyCHhTbtgoNReG23nsND3zQtHIKyUWG80esjUG
GgJCv4kG882Ax0jkAbxNsLUTZZNNzXqi7cZygKuZz7cAXDh5+p+r1g3IJvvfAaDhvXK5I98iNfRT
9FEj2Am9vlbnC5BZUCe48zTAT+cPRxODH6lpWjN1HRx2K8A4DdqP9wWnianOnmluB0VjMgNH2tlQ
WVkYpQrSz/Ar5XsvFDeLbxJxZ7FbWEgq2SgaNp1A5hugupTcZnzfwco7EsD9Su9oq/PZNXks2s7Y
NjVxYWq5ma3s84IaInhtqevwCZ557m83zcj/r/WI3aJxzJGjeft7IdA7OKwxQDhmOD160ByL5lO3
mFgb0aNMCYRnR0+xfhC6pWjN2nawyjWjRzPbkcfQZD8az3kMLLQ2UNh2Zw+J12ElsF75BNiW++/7
TM2E+b/KlewQTr0XGVAOEDbPPaMiwVKPAG6SmQ2/sBeFoaMwkNYvA+oj6UTIdFrmSr0qKNRsflNT
AARbkNgRzJY0XBDqGWf2JN+qQ3xr3aO/EfsVw8Rwu4qfQ+q9yc0XqO6In8k1r7ka2GRLKh63/ZQM
42sOWQMUwv+pXGUHZ1U+8ctKQyN2oSf6WpA0ikQZklsKfrUelk2cNS6gaoTf/PO/nO2/8Ck7RYuR
j8ZEO1xAZac9poTxSQVfVDb2oZUqGmDJ4B4AadyEB73BIRqqruyOw3ZWlB+StXEY7l90rp5onA0I
FRuQyhlJ21E5i/XOKy8ZSs6OS5hDu53PxC+x8wYHuJGFMkPzL/T6ldia+eQWAdFNDJkAuh3aUpPW
mTKDiEKruwulrUPj8SIdXGym0WDIX56rM5aktjgHCBxlS7A4nEMMqhnqF3dBQL7Hh68Lvz+LlFw6
wFJC96fMyCfqlcaY3r3fblXymS9/iaHAAUbyG1lXYN9IzGsZMJA25Ded3E5EGs9BsHLe2PAP6K6w
h6UFNODAscV8YH6UaORCB607lxOkXbXPvh+vdTTWyaT7m6u9z51NqcO7/JW5KyGr5IXzSHo8KbUH
upVTG3dHDTBnoUv0YBBakmD0u00BmPuCBc9qkP3pigyhAp7r83c7t6RgcZQL2M5gTeD0pqiIr6D2
HYpGm34lX6/kj67p+X+NifHyDWwA8OTmNV442wMidfSkfcL/9ttz4aAPeYPp+pXYCAhgl4u7cnSn
/fp+izpsNAoSMxgZKnAwB3pOQtS5jL7TrdXWMnKT5GIUKj0Q5/U1TnhRo6TU50rpHjiAC3H4Tmp6
tV5lt7d5EOGRF2tEEVY8e7AiNtbwnuErY2co8iwPDGNohe2hW2znCc7WynTsEP7Emd5UXNoDMDKT
psKsoPnUvPEk1rT9rKb9wMTOtsNAPj0MRQML5p1Xis1uwDPWf8elZy+LVnaJ5SgEFun8ozukCbLB
CyIGvSYtZBXknA1Xrck83rs7lo1O4V/uBVL7BTslwQrj0sShw3AyYQB4fXtfwv75fk/aewAD2Pfj
GaAh3crUJzO1o/pWFB61XI32WLNnp7Q0P6mRGNYvAjd1w3ymIGwgHWmDzYEKsEvSrAsA4gPJ1Jp3
AMJwYOIgzJJYnSzUxzRpa/l4IshtrfM8dahtoFHU/exiTtAPvs7tnhU0vZY5yflnxx+S5K3K6R64
1UHli5uEHLjWQCacj8Cl66eYeUSYy86JE7+K8knkLXEz0NErGww7Uk7DgFP7ZbfX7Xax4aMBCapb
wyaABgCQ7BB/eHnLPN9tJUEBZ7joCD5a/yVHdJ442IEavKZvfYvW3ZNpXuzuCUDWPlPPZSS9MwKC
BhQTKClrFKRv5pmgXIRQo/TftFewFW7eUKTvkVFRQnySocfIwMMy0MyYwBwIFwLjdICtGZ4uhp0t
3hcvApBiUqzkq2/6czI/m2iybgqVZw8Bc3sN3KPDKKrZpbRNK1Tsy08AG+mX/1PnyGx54KLkyHOd
KPm38xJID9Pf+csFEK3heHRCIMFHY/HoRYCWBP9Kshb1kTgi1yYhHN7ApjLr9OaRjc36MHRsmlz/
RZ5USNytHDPFagT9xW526ye9cKcOiuQuiEDhDk6BNgMSOWXU7/iJDHhQXw+V0evnEt83JqC4XloJ
whMsXfZXXL8bsGofCu61XJY8/MPmYhVMmli/687K8rGA5syRrF3gmi6kOok9zYCKHJw/mHBC2/Ej
nbKf58aAlNhQsiViTP0WIBlpaoKRZZ/Mv2LUr55/RclO10IqPmfQ72RPLdHt2HdtfZcCq7Tu1XpS
7wmQmBGu88xeVP65ys+lDeM9GPFReGq6S1gnWhKTRwkzZUz6Y8jR+MNIK5Qh9XvxXA1qsICz6K0O
SomwKcIwToBGkZZSwJNMDGU0orai9Bqd3WXHe8uVjlaJyC/Z9bLapt7r0/PWypjblsaxq75LGtRs
TNrFY4ryoAyYualnLDWaNokUpD9VuuBTGyPr5PwdtPlUd4Dqp8riS/bWwKYTdJhQjV9vDwSgs+Ez
Esj6h9vsedaaQf/mwPI0vC+Nu7zXcwlesDK+aGZ6ulyhmuYHlrW0NMlmdZN28ct59OPlQkJ7mVH9
MRX9U9A6km4XUwjheKOJux8FDmWeG39EIMvzvPDVwo3yomh8F/+xj8hqd8luiW8gIJDYZAzq1CKo
6ypbKmrwr+icHTuLiNj2lbd4vOzVDNMz/4rW5lNjg4NvWPuyvzR7wLTNaXqeHKi8kWXCS6BeSIeI
X1tJDc8DSCV9qCcb1AJGuAC2gHjbKtbupJC7Jtsu1PhR7IR4ZX4rF5UJKsqCiUf78eex9gg8oYGz
8xjkyEexGVy9+uyk1M3FxmCOOGXHFjYOPQvHeADICMRxnW5fJ/P4tF78uK+rbW2iwicqlDgdzuMg
3Ydc35PP95jv32Wigw7uZx3z+hxGa1H3AYEW9i+ZXSKiQZ7+x71+K7eqhv+h0JXRgbHFSxoqPEFf
DxenyKsU1dFtbQCGX52r5DAV3hJB0///ZOcIWNfZuyhvgmV6zn0mYyhlLn9H3cZPOJEzLHxhJU23
QSZTmVxQNtx9DxI9SdKo2KBcqaRcbtk44Qp+Zy5/2zZ+M8FS1Y50QUFuCyR33amrtdw++oo3aHvJ
dKyhtNBgaBkzihpGOBRU5oVS4PQUc+uQd/FqKcGN/hhJf1Kma2VcVYNtYAr3TMcrz2P4SVRI70ds
Ea0c7YXLCJHdbxIHNRDCytljR3CmMv0kKLXMSyqet7qvFDMCOXfjAmOS2JMman7ziQ+4OPOWSBlM
jycwcnJ+vdQ1tQdcLRVdHi5PdGa2rJFWCqoVPEye4rqYT1QA1JnD8IrBXGeuN+SrLICE8/L9YuX4
E+yV95sTNEQM7TPxm6LXyLNE2cL5n5W/IBl7Rq9IqqUGM1eJyKXEzHJxZUrpOUN42LG70ViVmUGp
3mZ98F6ThaZxRNN06GtfKGcKS+SPjUDWIdUmyWC2mPCbJH8aO+CBnV0W3Sy9pKqPJTo9duYIgFyU
BY81bJc/oDi6eERxAkrQ5OzvIgASGvF2b74HMuHVKUH4kceFJAviFJHFoDJo/+ZDsf4tyunLd3vA
dlBd0zlDzkGnUul65+7DPa2YaDbIY2tQF2ZOMDEwQG29kXLNQen7pQmm91agINK8xxIt7Z6MDXfk
rIcnoV1IbCkf0FmVnbNPcQLCwABHPF8/SL0Loq8xS7VoKXxhaiWAfrua+XOzslpdFoa+6BlBThRS
pqZ/A9ZI0ggN8JeGfmlYVYulUFhIOmHmRTYqInRI8CY8JeHYDlVmSyhdCkC3M4g+/JYt+GCPC143
hJ48cfgtZ+UN7qwQl72ECEvSaqUEZu22NmzPpTU+l3thTgvvOxYOkG69lBkRF4n0ds7agp74g6WJ
9lt4SRFt8Gv1MouKPu6mXtATjdL7/OZukTw7DHj511uPk9BkW9rV49ZyzObfTwLRMO72b2o3JJTO
DCfbqcJgedYQkPNPTK/5E9KvJv5Gf6eX/oWduYG/LVlNYb7fXcp+U1P9DQDvFtKKBUUa6NzSZpDU
ERL89p7VT6+9FfSDq8niVErrCK475XEBs04ZQ/UMxEZOVbkdx03we9QArVFhpUU8QDayHlFpKlb5
4uB917WwI8rvs90H4HhFUidzaP650NUhhx6P3RGkdvajee8XcpW33QznKbRnS1uRlup1KcSw6G42
JnFEgXGimUubFFdW4mGQvGqEe5Az/c9qryfiieDxYAPNaOWrLnB1LVX9zhtESd/t6bkV5ZAcR3Ft
ZA1oXF6dlgX5SQr6QZR9u7s8O+UeVkQ+EsnZnJCzq7NhkO0U/e8Xq5NBweghtsHNx7HGDrRzf/En
Pio+J/yOUBrmOk9yepVE1SU+jC7sVfatkoR57FKxk1aDB8A64yN7RSmcvFE6Cmxfp3q4sziN0uvk
yIlOJAt8BbHP/8Cs2L6Urtk9hV9MIKffx9LFg4wp1Oszu40X38PasESXhN7/N+sPcVbvpwqRhEzk
/o71uxRxRio4q+yBlPj/hnMYV437i5fNqwxXtWUBt19bVl3WxrM9ChCEpopmH7LsbjksTkCxvCey
dG1t27GqiPeYzgWHV1/lM07n/KtOLDckPTwoGA95xrf8zjZ9ZoHlDiIb7OPNnwc7jWg+UtMX1cW1
OPeiJTCgGIWBIy1R6/dVIoGrZlxrjj1Bzd89fzU8D0SPCZCXTxOm+h3g7ffhm3ZUkO2TnVJuqdPC
oB9C9Rd/W8awsymopeP5AD/EsNyya2ZrmJSeiAfCRIZPGstsKHwrQJ7EzZ1grTfC/YaRiOPoONwf
aq/3miqNNOtlf9wXQ/B/7dWe+dVBghPAXqufacR/vND+gUKr33MeMy8xEJOWqMFLldEYeRMK2ksI
e/WxvljLCgol2peL7L/2BHH8zA4oHmGN3CnoCBO16WNwkMprkW0v2xPOkKxLQ2m9bwxgVL+h98mR
xuHbOKooXsaOWGQnOxJhSM5VtS4P8svQU/DRgJf9JGPn1th9Jqbp30doL9ArftsNhmMk0qnCqSvZ
t+OIO+JOC5CaU2sAi1av6DyJjGx7db4Exgk90qRJKgcj9/cwIjYHgPLnwlaG7jlCBqx/PNen6hBA
Z0hTyat2cLISWuNgZw+zcbzepI9RWEj3K5ZuR2HMfiWVd1/K/msMBlxda555z8bWIX2nJIKBOoXS
DeZiDbxNafIlozIjEaNJdAUyBT3H7FXRWVO4qwoSgOG5YseVMuokdPXsqZ30wRHI1kXl5/pFc9f4
o6XpaxK7EP5vstXOKPVh1pwSqSCYtJS+JkQ2TzEkC7Hr3VBzQfkjOgaHtcOQe92XW43Bm2zIslDz
dNZuRaJY4cgXQ6raAbhXzmDs6z3YGgaqUtNH4lfm/QsFO39IZ1NYWKW3CjbV7OxTSfrfjLn2R4St
27iIMQh1aWHlxQpbtOXbCO4nZfr6rEhLPUT1CgRzHnlSaUyqFuCqn0e6IRWsY9rt683gGLE/6BKv
QJaFcnbECHZ5Lu02gIE3efOHJ5syGcbbmKpAfLLJLmPzjQIuQyDi3ggIx4JKRT3XjygHF3WjL65P
gCFjLBacQk/6rv3uEpQ+nl99f3rLek4a/DSnC89HW9sIJqMJ+a6fwjHG16fEu7ymasu2vMX0cxGW
lhmkvsujbL6Fr4P4DcIJU43XTcUSgojF5a4wh/AKgUw2J5IpoTHAjuHc/ZIB8yK1vaLOxDTd9eyo
yIz2zHKcJYTtmt7oDWvpDVKP9uOOq7Zi+cOE6wiB053UTbsT+YLY9ccmP1KMzICrEehQOpcQ8o30
E/8eWLLpJr0u85qGPs+AxeMOApWkFe50XUE+BE7J6TH7HOO8mHabocRlUb9MCLm1KLuVHXHdrL8L
5ON36hXLo+b5R7vAvbMk+ESNu4l+QZoHX6QE0S0ZI5LAobXpUU1VUESLSeJiZJ+xYsxXdT1wyBRz
TC10LJJcqQ67U5UdwC15UExEDuCOKoKA3kE2xSVVjyzIUDrKZlFEdAcSQRpbQP38fqNaxT/2JSw7
UN6gWY6CNWhuPJab+pZ+d4AyWEGLpndATthH04p9q55Y8gZJM7ivCQlKPQSjSTUv4u6HytQXSH1L
EjIWvXMtQiRI1bsgnOyzm/Rqb7KRwjcrHF3162VnGD/kTVDFUv6HRla5dNtZDzmPLBf4PiWZ2vLy
W1pRl4Rjv/IORqlHbTuQwbcZgbx8bkKMN5yGs8IyiHJ1tt92Sc4UZBque7/DvFUtvBMuHAuObouB
qSLGE/qr2iu48ot/sSez8623cSdBes6lHzZL0m8uuDrDti6QNeaeRQgqOOTJQS9Rr3LRt7feh0qp
nViijbrTPvUkkseWgUMadF+SmkiR8wpmRHCQbOZdXsxxRsybgqeqXIqBvcvFg6Huh+7oUaEgS/Mn
e3P8Ug9CJyme67MJSi4OIWhSj18dhyogysqfnX5dtTmAjkcTC4yIU5VXZdSMmqkR8wB2S6imR7UW
1jtfJaXR9Mx142afQIokdzn0UYWQTgO3NEqJxqoZG0PminbWwG6JhxnhRlpS7TOrR5a25xz8vFYk
K92l2pRV6cWhkTfU+9nQFfm0KjgRxNObnfW/K8hxF7VL2opc500xFlCjpHnXwIpgzHhbsoWgXA37
wKiFj/yKPcxBX12+VxMgOs8DxPLrGhUZsLnDzF0cTU+QgCkwpMDVTTkRf1aIUqfC0Zc+SsSIC5qZ
DJBv6u9QeFORzXKmxumw8SWI9EnPhiOpPlabMXgVR66JTazGd1a3VQfhaWdDEM9373nP2TXYB3CN
+x4fsUi6tmiPgi84I5CHWEMQLEiWHUMTjd8qR2ND1owxJtALXmzSCcdhuDTegrJYArpcAEZcgKwJ
OsZwneo+vIzy+Y6W3Pr79H/y2zdUKELHlGQZEcooGwba8FNJnPkQTaAiai2XoVVVvuhkN135e3I1
veL1Fnni/HmYh1ytA8g2fVYgs3r7ZyZpqGD7aMxRg5whME3XjBBSbB6iej9VoRxOeaYRpJK680mM
JJeh5TzROV+SIPAF5gvEd6DOjj0+lDec82/W9AXNtHsHZQHPuc0/9f7e5Es+NyNj7vyqBNcSxZ8+
Hg+8XGsUG3hyCoqxbl6/eXd4rRExHhhtDGRZjlZzuEyCPx6adsqbTAZEcvdubsSw4xZLUtgmK8EU
i5XsjvFJ5AzDdggh0DMIBChPjDbES9ehjCJJcZVxQiwjrXywuZjBfeR1ltcdPItDDsYCPYCQ1bbv
0cbwzKsgQa1Tkg6vkUY3ZSBEemyZOz3FpmWxQ5pvd49en9uolIzffoOmXFnpeGggN5uhwq1D+Cbq
0XaiYBtOmCakYJi4/mGFv5UHjUnj1pvU5rrxly9c/EgxAM5LF4tYByshDnVD9U0m9u+LtL/799lS
CkB0ELlHdOohl4kBKiIKXfKzrDWQeGIYhOYd617jNPCn8iqpfNkwYKFrNacR5ngMrgdHRLq7QsU0
mkXx+ktNcTMcxelWVNxl8aeelA/ypxyRStfXyr7sjSoyJKjX+UQajui+ODN9PmoLGW1wEb/S/Kxl
qGXFEfOX7aXST9aV0NScs0LlSYAenxSHJyTHqZO0QVSqj6GuzNw+4973UWXTqMlrGLxAdG+rUit9
nbEMPL2lfQ4OVkXa+or9n7n8eDgM0acJLUP9OUyIZYHWT+3aPsD5Ehfr4t+Y5Wep8BCuc2vGCsNy
bNcPDHk85qjkZHMrvkAjWCNLN9O5x46XACXSkymr9yJRaefhpTUQFvCeVTqo27PHttWT7I7SVyPs
4QKEW/0hVsFZOpnFPR5nVHjzj+rxLRP57fm4Ijpvp3rJz7yNHf8A/vzqKBX0TmouDw57IRKeZos6
U6nQXb8uWG5yBIBUmy3tFOLQBm6gJT99VuxHK3S99eLZfklCuyI+kTieSq1iUffYR6byfEA2KXKm
kphHGbVjSHjySzN5k1d/weJmRpFug+kvnAPgxcjHeKaVFLIBtks14/xshXp1Xwssraei8PdkEVd6
9Pmy8lIrBOx4vD1IdZ/x579wPinmmqQlPnlQSwBpmfV5yJas6k6vrspfKqRZENL40xdJpFnxSdd1
uiav11FtrziuzpmAoEB5DIVl56ElOM5hEXPPjYvUlv0sR2mUpAvKRu332VCfCxbNm06oqmD7BOP7
1x9DipEvCHHXV/kbmV0qjRLcBftLtUBux0UoGPqEfxlg2Txs7nFcOci/RReVKZxn0YuFatBmfv6Y
9AYahekvpCkXNbm8+JWIqlt6+GmqbpdBqzGQPt0yu28cMqj0vAW+UFXPEFmYO+t+cCXcPpCMbVbV
fwHKpUld6hORx84vGzQuIMbvJcwKlEqxMcf4bQ+qkkn3kqqbptVvSeJ1Ipl3fqbaj4ct1oPB9bkD
jGcrqxza8HQDPXeDpNRLxx6nxKkOFmraU2YpW4WhS/PEERVZBuzCcqpKXQ3ZlZ2uHGwim8dKHwV1
+n/RjZOIkYcVoOlhcHx0qTo6xTi6J6g+e2wLSw95mRfvEq1BxNuTB85O9Q+EkRtq0TRU+LoSqSGe
h+AvUbJUft7/M2zeVqYM5vo25Ue1KqH0P6igo+6YUPYuMq47plii1u5061yDJfdaXoa1Sd8uLtX5
bYhdliTozCdxFtu+7GERoMnYaThw5suqcs0QcT66SOm8qO9fnhLNPWoch1JVzELscCIvwTvg74Or
UvLQU+h6ilmHs4LkROIRbTBNLEuzXgTR3LrTNAAaz3tv06cTdHRg1hYPaoAF+OvzBnzXxuwpmDfT
dpJC3hb7RlAcCO8WKYJhuMvmLCqumLusMg6y0KDRhdG/JRcYUtIblFjhNEtqXsElGmn0ZCRC8YPu
CUDGQzTWABcKfSM21+YiK7QApwzIoDPZy2dfJjMAbqukjgp/QfLV1h4oOJJHvU51BhTJ2UIbvVc5
Sw79eQ/5gd1ZNSLMvwChOqXzEnFWIRM2T5z8kWuwAh4ncwPQJpAKSCEycoawQwx/pk3LuN0Ebtrf
8c9HjwVWjUV+aT5tklMH42OOFS+f4rLJE930gDPUN9yaez/z7DCqPKNFSQHVKMedMjpkBkGoEm7Y
zKOCqlfFj+GALcs6SO2NCN9VFUiV7h1oZI88O7PESuXjaL3Y1Cx2k4q55c57tcC+WT0PuWkP/f75
B0oWiFPFG3b1oY95nG2cVfWwgB/rY4zA9HlSa0dMnrp73bULNiPFQCiiFo6bfhjmdqp9GCTFDSUv
Qgwu6aqiYqC6IHNwHXuzk0Ad5UnbvqVZ1DuENbtRA2sr2Ubu5qxtJGR1kWnVsRFp+pK4z9KUjPb6
96+jq2hawBXminz0i4qdG/99/BeMS1Pj/k6KNQnSycMy+ASnF1/GwWWL8I/6CiDD2ng5L3ec0bWo
VPiiiOh8vdSx5UTHdBG3ithW61HHGZtmgzZhF6oXpJNPE5cjN9Fd6lpMGjzYfGE0E8EV/LOm6YyM
j6PxRPom0FoBNYGzkplcQk/3VvnXlYjPgdED7Qutn3Km6uIb29su8ULb8GAey2laLEAZDwUbD1M5
yHvxJ+klboxRtIdYz+tkVjUw0MfWCcuYzGotMsvKDJATc7jE9fJRb5ttDyRB45f+5KOsZTu5DoOy
12B5a947bRJdilSN9drC9qb9hABf9vR28tfgnHPF0AWopkhQac6xDuuGYqxRFc2K5+5TROY/9lL9
j00qIumGrPul/kNWDoZPYgEmm3Abti5klUjKhznWRGobawjBBHIrcMgCv/zrG3JyhpE2Mh8eBkqb
BPzJ1oOcxUiN6HPRUXf+WJD7n4bKRu8hjyMF864ebX55ZWcdIzQvHoxAIQ61grcNvyFxHaIzyUqj
2cYimYZqPAo6hCdyirWf4z13n/durv1uVxgFh+5/kWazWevRD1RDOzJYDWrwptyaM7cS6q22XTVp
jyYqBCq35rlCf0VrY4N3XSc/v7T43t2/n21C3DZuSb3MbCb2U5XdSph8QDVxIbV4xn5kwTyQ2JER
ApD2BcZVYGW/lgROyi14Mm8Q3ufvXbIDUBLabuuIdXT1/b5MMRWpSLX6OW8uHISl+urVDgbVHP40
jf+caJCX3Hn07Wl4QhemVu2uyit87LQ2OmFHyrLgMy+cdHWv8iIYqFrrgizruo3A0jOZuw7qdBH7
Vzyv9pW8uKy0NTH5T57rzHxO88+6Zt5+RgVbVjAZwErgS3d6O7OyuW86NWVgqc0N2PLRHmZh5Nhf
lsz5yqyH67Fx30CCxk6zO61nwB+wBWmAdW66uV7N4GS/W72aR98557W7dp0z3RfsO4G2PzgG3ttk
j7Tg1jLMD/HyfiR8WvRiXPUhlqsvvrzRPo397k8mitOgcGJ5eFLXMbu589amOJMt05kDIFEQUvIl
jEB3dxE1hu3HOiy3LXWmI7a7vuTtsnK1mU9EUfAcryOGKKbMaeR6U6QdjPC+XO4RdhJ/juC2YsjQ
pWoEHLOgveA0z46D0Ju5IHDUfd/KtQPtzi1EnID0meEXhfVdY0rfT2WhwOf/PWcWPSrR39tqGGlY
Cp+ex7FTI8m0ASRwzvQwzJGxpeyW2O9twgFttn62XrxJjWvsHjHQjeFsvbsYumRGiuJATvVTj53d
N4LRssbGNiLJ8JUZdudc5w664V0IUYktB9kcykedzCPPb0SJbbqqVD9Q7wyU0gTzHsAEcQEDQTg4
4HDZm/NsmxPyz7+aM3FJHPCzdQcfEDCFlLfSxUK4qqggmddrmRNwhC2ef6rpH/NnuloY08S5r2cP
toJzP08Bq2iXzuptbNbDP+h7QII6FkHrKvEbGeFFEsEKtjwi1hLnQhHU2lFmeAKEZFpo2Q4ShF6q
g7FqeeLXNs5ZkCNfXTBA53ccv9dXRSxU8CaoqoJ13kmwPszZqV7RKxs32rsNJOqVISx3lZzPhlxG
FxzuOEEyr8cGdIBxe21OHG2T5pCNyWNXNTGNxPFX8O8lfa4jj0JeiN5rUwsis1a7W5r2QJSbPMy6
UTcvYQo8rmOwHlr1y94dFKogN3U4BZbV3fhXitjT3yhD/xF3MM6gjOARFs19GgZVyOXOQqJyF2ja
+rOkguJo81MgePpiEIiwBPWMMBa2PBLx+1PazhhxK4V55QztCqd0ErfgvLvl5HXlCmFdcntRhY18
xBElfErrtBPROdFI3SjXp6/e9/zJpFfQG+FFhpdh6bdiu5l2utxxxgB0BWvdnmmEsUPEjLmN1SvP
anxw4ut4apAE/dtOPPwqmQfqeiyI3tkKxNCSzz2fhM/hUaNoEs/xLIfG54XfVGmQcRmKgpkNLyMQ
xBoBbqNU918A3sgbMmKSQmPQqdfxnqBDJMoke72BKmfdEBU6ku/Cck19OJBzRi/RWeMsoMTPX44/
pSXuh4UG4BOXmxzN939ZwyJv+9hYE6cP8KzkaHC6yLiak38OKWYUkWWmc/YnHWsGYbpTHQpAUZ9t
VCF/vyhNL6HamPQBOlbj7do/T5lWbWw42dUB9HiiWBkNIMfxdBWu5vUF+2uFjaZ0GkUBT7RFgzX2
y5DWNlG0ycJomogXcmG7EP8h+m6kD8EB4pzdn1cLnp8QSEI2rblzi3j8D+aIRI1HSXRmitZYJPHQ
zRiQK7ZL0fob3w/Crr2FHVHZswRo59+3nN83fpX+CaqJMvXsD/hnSR0250g4AAraJ+5upl1qqVRl
A9+UAfyhII32M3RU6gl6SOE4CLtXly809Ru4iGnw4V0XXMBNQTXAQRE4mZ8GXZqexGyPZudjUqZq
VnEKOOrVRlV6oJ0S9xZQfofi7XHo/nZdmrdw6ab4diXkAU/8eIEdNxCDvSVDhpzZ39tZEfaesPVU
mkahrRm4bB4/Nm6s3ijedMe1HU2wOa9DoxxtyCAb6xON/XVJhwwKZFHYaW0HdUgpU+eWjBIQ+QYQ
MaF8D+RU8frutZb3/xNhm1cN5PPoxiBYKAIpjtcSxnKn5HKlp8LYYlu/99htMNHmAs8VlPlErO3H
xethceVqvUbx4iH0k+Zp7lAsBBvOJn8LtZJXCQ2FJlSOhjAmVxoKD6KMsz5v4Cb6WNqlBBUjiXRw
+0LYSyQ2OnPdMlx37AeUTDM3W2UfUUzdqj1PCPRV6XD7OdlbiN/hp+IdVLbHUMu0+oGAO82wcJQB
jJk6cTdvAdiEjmfA27kK02nsAlOsxufLDlasJQF2IOQo6Mp2Z60kfnAnlgFq1LVBgl2rH5yrOZAy
mvNMgQZK4RPelu7IW9la/gni7CTBl03pCajBwPdJ8UjgU+KblJABA0l9J36Qr4tMxgLkYBRyYnUn
iaVKP3eTH/+2hRCBC4ZJmp4ICTnvKuf43rT6tEBKZ4bkDvJWPcRJ00lA7iGLYza91crEFKChBSH6
QrJFEq2ceWuynjv0TRE2hhbJksBqK4CdQJhoCoUzrJ64X/7o6VGWRH5GlPaUEBu2QLdbt2YydG/r
7DgJT4dG+ngmxGaTwn8WS8lKbBGAXy5Li9dhdugiOaqPJT2nlNDRu0L/z8W3Zd3ZZHQaWTHiGUIh
Vfnm1UfCJSkCaQ+cyBpe8cO1qCNOtqKG7ey52RLR3mS4yNr7kJqfriOMntv0hBIXlYhQLMwdgzxT
GCjgw+yaDoVG5qT8/tHtlNDIV6t27+MCDMFcea/wW7us9VEDW1Wm2vURid6PcMdLwybmv0gpGICq
1r+tUGuKQ6R05NPk48TwWsTNW2T2b/Iw0Swa1w9BqcaHPGWnu90KdZYI1L3kw7k8vt2KjzvDKDlT
da/yZqmNikKv5vO9yGJPfcoHPd2L0Al8P9KeUKyROFQuvHdqSwN7d2kDni9umxY5xx+ErFNHWFcM
UGFIzdtu5rkyQKNtFWMe95UjiVEwjr+TD0IjLZwdH2HR9k0KvJcDBqb9P8+3dDCZUStERkkKXAIx
yTiWuliC5QP3FH/dVC9QkX/s1GAYB+IS6VZVEtaQV3OZjJNJ2x1x7XcDPTeNuU4OZQ2YeuNa18eg
Lc7ro6SaYuxkdaE/T0zkXzlMuVm6lERh1kkc4kstZKBIfoL51N4Nvoatj94OAjCgB3T+c34r7dA3
XeNZryjYAYazSdvy3wXz+I1A/FyGZLMwqjXygFpg1LlG3AVJQtibTYVwltx/nSqPwqnA0uKkc9QO
FY+pA1F3IjYfaBklApF/jmi/1NqVvv+B6GONANRt17Cb57kKPevQin4W+HtFwMWJn53B+ph5ioFy
QEB/QWHPw0iX+cnTUyNzQZ/wdKxM3PvGnn38rvme/x/wtqL74vmkYOdsJBmzZa+O9y8MbeG2E30v
+9jts6ruud4qFJ0Lb7VEIB6ZefOt7qSZyB3aiAHpqJx4F13pzGMUwaXJooTGi+dHMH0rq7WW2GnU
2tyYpwkNlK78JWIU3ABtsyMHIJ/eLrMd6FkDr0lBhBHNr0ZMCb30814pa2HBtMgsdElEWZacDh7c
nTGGA4K8qaoND7ZJd6KJptgwvNXeGESaqdZoSJuGB68kgBWY4iQYSIWbMiyTkkGqhtBBpU68CRkm
sKYJC2kEmWWC7JVZL4fBkF1Hzn6KtRHEEBkJpVD4XzsskiFeBhNKH4R66IE73drZu52Z1xIq+Ix4
LfGspCNVT0ulF7YSMaZRKrMCdXx9TWVwRUv1zRfil6seigvfz9+NZ+1u7r1fOJiipk9eekB/6ZK5
iigkIkPcIO5fGL53+r2k4QY/gx8336YlBn5sk9NNxxL8DZ/UwrHjy8HX5ASID/qG4/nccjH63qUY
UoNZiItos1pdcrwUldPD0dMC2VB3ttygqcd9BAywfNFjB4vLtr3B3WmTEPNo5uMJHmsZIEhvv72Y
63eBGjNjC+aU5VPvGHJPMpWi9DTfgUkLHQv4gZ0wQ2ncFeYaahXYZbV38A4pf/n7SjE7NHsaQo/B
tUKwOkOKiyN3YEhzwF2QPbE4QngR2tTfuZ8NBnfouXLr6jZkMFNc3ByOEU8OuVb3BI2VnHT6cyO9
IPEd5ZiL9LAKpG2NTWUmCXupOn+CBEepyzbWc9o5ZT/pT4deYkI2hzfRwlPttj+oo3l9/eh9MUAE
o7ODpombkYx+1AnJgc5AAlIYgUqffCnCftaBumolKH4QBuEnneyVo3vp102T51woa3AaMIbtV2u0
3KwOHH3IlW42lcy3fvBo5RqjX0d2VuNtS1M22S0+RdBXCC1H2eTJXIFa+EOxRPs6NT/hfYEEfk8A
StN7SLJ/3Hbx0M31dqbnfmcJoemVjReFVRo+PFllO5Ba+eoQHvFBHEuCLry8Stx8+riI3e50y9wJ
BfjivWpx1wjdJ72+V1XUlXSA0KhRWm05ex/Yh2aAizrqsNOzVK3hW/jVWvxWWhLQEyp48WxQPYCo
SZfHLf3CaMMor/EPSo0yEbL4k5nRUm9SnH9w76Zqm4L1EXkdil/3pyR4X2eEtUu8s1uTdEyqFdzB
i3i/tJgKgU4up5XALaYqmqPwTmJnndZFCCmSaouyssKjquS02x+5gsyrOu0bLj6ydNSDExB0HnnU
POI1mL8nOkag9KXf7EvEqrFwnicySpCGzjZjNXKNV2Ao4S1d4+BXgB9nS5ObchtigdMFsYWaOqUJ
PYbIqgTObTHVqKk/QFXHfyx/xR3EXwDIUs8+F4Q6cKOJwYCCiTiQkq/h9+zD70YsRvpGJFUgec0c
nVFxry6QHbM6v3bJmBsNCCt3VhPgqNO8wTE7ijVEsEOCkYKunXCaT3XjNI3yd7PiIa0NM8av86le
wx/Sx+89GR1KhGvIgSNjbJACk8tQqFQX6Gz7fCAupOJnfDj1+1GVWXm3rTVZ6WT69ubak9coMNjU
XlabHK0tdOQRU+Cy3Xo0ILSUfBGJwpYyfZDZcTmoBNK5l3WANoGwCc+vyQ+VJgQiuT0u9Ynd+Ztw
lJ+JAsH8rLCsNC2hkVPuo1Bw7Nn/K5eZp8Eboow1S0D7m7cxBltSt8Z2ZsvnolW97svNeZg1fsZD
LixWUVSaFKqjmfomfutOrqbkXYBFpRrsD/c8UGq5s3FWxp2/jwU4DKaaLSqMeQgnsrdirF9Iwtr9
w/6xO0QY/UiNvGjwqQTIXd1jhUCl6A4IVB3EDzWG8PbaPxTANodtsCgAgPSDXHtNebvgr/5/67VY
2sY0Fxi68MbuYPttSU0ehM0KmDGkcSrILUrqWdp/y49NSfD2t4cGmm5VRVeg4yySD85uXKJ/HugV
UjFDeTrSr5Cbg+hcsF/M3TRvYcuW6MmHzPUz+V9dj3V71yHjqSgW7c9zhGJA9Sr36RLHdEqYYhLc
ewl60CdOzx2+TsI7ooPfFE02lkbRCsJYtQw0WqkWdBb2+zkaa6EWlbMPNTyf8RYkIYYNMiS1v8b0
Ol+ZutYaEjQiU0mei/7HompWbK6p+HNh0/NpruYRaUepbHknD/1QYkm9nZtZHDz6voZGIsryQRka
z1ItTDmi2CHDfCX1tdsqBV7vPw34VuJx1E/YEWuzsiavozFMih+w0pdegOkJLm6+u3GvsBxz1V6g
A+QYzJwzi/cqwQrO80UWKTsoLo0sdZHb2P7aqq95kgTvdC9IeT9jMQR72R9aDh9RaLiYDj8oYRkO
X3Tkm1nUl7M8+65i95k1yCMHnb3qZpikChaktLS3QW3WBGJ6gqM1My4GX/Fy9snnpUVtWLnXxIjF
jJ/o5RLaoCP5zOha4etHOOjvTz6Fp7TnnHW1kXBKLnEER/dc8B7JPd57zCDqmHofL373r6VNv1Vt
lgKQ5vZT++YKDrhFT+HACeu1R28j55Vs9OtXUWJffcGL3mUNmMtPvenuTmgb5EeEOy4DBhH0R4fR
LSRdw4+V56OBIFvWaspqKevbqynN0pMwRaoVFtTD6/nkz3XOL8fnHHDhcj9Sg4IhJWwOmwyRWp/U
nimUyTqMS+gfyrTzHZhc3pYuEIgD4GpPmR3jI0YVlpWaLbny1p/oLKS1YrVEJ3ILUYb8f8u0BTRb
A11Eb2NEJhyqH6Ifzo3l7c5r12c3hC3K/9lPLLVQG5K+51ZfhgF6D+ct+7MW/z+VwrlLk09qbR6Z
bJ8Ug9CbL3E4R7S5m1+4UrM/b/l5mbPhN1nuv6rFL6s8ztKJELIMBjuKdmTse+q547cQ7p1QQnhZ
Gb8nYRaIArIVEYqOHxUWPKgmabq4KG7yw8EArzdk20Mxje7zOwWrPjBRUHi7p+UWVbfKM/DhKTxI
jC9/ywV/DuvMZ7GFY0ylKpK4ds3dpEsyL0MpkV4gvMvHrcME1As+XaQo+eML+gwDk+D2rgb/9iPC
gR6RHHL+h4OW8uRUDuGVHXKlWDvInj7dr3ZnDPpsUYoo1scsPb4EaeMXeSvgnrAwYivKzm54b5dp
Kss3zirqI+mAYGtN6I2fFxZ4W1fx+KQv/oGRz/8scfimL6ebAGZi0A2TUxbt+bI4+Guv9LZ9Gwlj
AunXkQ5VSvQjlYJugn7JihUk/sYH+VdcPmvDSq23bRYA8apgYsMc+hCvAl6qU5c8GLAAWwAo815U
RSoVQl9xJKG3GnPUfwN19uhuczSDZIG5fr0ovH6Cc3idOdp1IXGuz0ehgsH+tlYk3B55TLFb4X3h
qv5IG3q2PiYuKewEy0Dp9PeEE5s+rpi/AAc9zF6vssSjH07+xx0uC9S276A4jRJWt277cFq118Xk
VELQGb+4CVyULbZE55Vv2uZRjt2WTaQP/gz6prqWU9PoV3jmOa6N+Mnh/7kQ3c9Ahd8qdwn9fz/a
HD9eftuYgcFqgtres2AEaCdTYA1EiccGuu01ct9q+nfCqRVpe8T+bN3i+dyEbUioZLwG+FxjXf3m
2YnSeROIK6A6nB6hiW+oPu8mVUCsL5FvpwsSSmcMGACkhkmUSa7m7yHnv4r3yrO8hNqC9Qr0OGrd
wiC04LrjO3lXIx9coZi3o9A+Xe8WuyP52MacAcQqrMALC01sgT1QIsSEl3PcIGIdYBXiOoPNZnoq
yLrsrUJOst6aUf6M/6KX/L94QPNqNYwKRfDQ+ExphSLYXlWzN60eGoTHNSiYWehYWeSLNKAenKMM
hJrLC2boMRsfqIbP/sjjxOGoSOy+YTEQ+6/fF9UtG90wy+KBCFd855C0p7qA+8igvG0/6NN4D147
TzN9jIh6TmB7mrGsBLOvpReDl7FAIgNwgeVBMiTFvu9h4V/Z4rQZQa0gpR2IkSB1lpRlG9DyZU1M
rn2NdjoP8sl9S6nKBJpcu1QYucstkNxS1yFuKasYDrr2oGEuQ2Cqf6zJ55vZxfCVOdhygfZSFBAo
z6hq3SNY8/uNhSlLPn0Oy4/o6jAP/qVRbXLRlYbttGUfGRIcq+zpkG0VFjUh3dv/EEVxiCIpFSCX
uxgpkRs2ClzDhfTQ0l5Jr4EtVFaNXCe5Ileynj7Aylt1b6brK7nH3Wc9mrs2ZWOshq++LhCGHlmR
VzSPdF5k2bDABw8ZNsy7zJXwYm+Z1wGaN+C3Bt7eiyVTsKOX4u8qGLSQsgXnGDcmDE3B4QCV6RoF
Dhowztc4Ky8BzUM1KzU7sfaMw36ml9xikmnkhVVhRNlNBKrRd+88VL4GWz+dpMe95y7vRZ4nWiN6
kv3+n3jFb5GXzglGipS/RtGA51Vt5rVUcZngLozrjKTPL0cmgbQCKFXw/wmJpuzUMnzuwTtJq1h6
fZhB9FJmE+hn8+NBs4PMtVKgpjKQe1RxTBDptIpLrB+8KRdvJLluZ8A1C/5qFNifGNkDCd1M4Wkz
ya5Az9IK1vDnOE3USbST+DqZpbQ7BczR1V3itKUyoT2YrpNakSVrYJC4quevaeTocHodhJEIi9aN
oRdhyW9MoCZXDVdrQ3neFOotPiP6aBm40YN/9oc0xAwLLMOkpI7EBnQ3piZOep+oRFMi/RYldxEB
3TIIUp1tGPa2z3/f7ETN54SPaqCMCBp1m3wsD1AO6l/O1Q+fRpoMOZHUmt3cbuZm9wXDkedF1gJK
ROXs8xHcnn92X/5LmGkWccRw86CeUmAjPNW26fml2gA5kHA2uwbuzvcCx+2BVVRLiqpY5vIv9Y8c
rKj2+yBPo7E/+sv5NxhdiahAatIlmPm+2tGRaR3t0BL+XzJ4NuS8m53I9Yfi0ZpJcMu2s8Umykhx
WMK+NNbv59QNQoOjWhIRc7I3cVko3OuyJt05pB4OxVxQ1ikpc1DJsZgKEO3CVNs1rFdEsL3vg1s6
KpCjijqDMA32K5OWe/1DvfwhlGVX7Vq+PuF0BhFzf0bJ+S0bHx4nw4bpcIjN/v3keWt71Bbmz/OR
JeQ9Qtbx3glx+rlEhRyAHzWR1VSI2X5A1Qixq7hfqS91Q+GdJHMAKqUwgi6C5m0GkCkx7lrREQAc
BYn4y7rcUXynj1wN5QWzbe+yhBJ+ks49I57HCZnNSIExqNaStE35RBdXS/0YsZbV5mySBm2mG1bM
4jObjV4mOuDgFMmB8dr/PfXgp43tt7ZWZsTdSOxLRQpFlKrdkpx2Saofy8ezcwQ3QWyyXbZPAjAP
vR2nqMx3HbtwDV0g3nSoEjy7TT6H8oPCkZQ8BjZDDTWHeY+Q5L5sE0K2smiPnyeiiqCL2coRXlct
ZNFLP/nzDzwh1mlzJ15p2sBas/uttC0OGCFsqxsEg3+v8zeY9WYrB8nj+m9klrkdGhVHqxgtabPy
iLlulUMprVFzW8sRZo+X6SzMqHmkOT8590bLWIoRagVzbchwNX7IFvbcprQJNMPUiv2mXdTW70Tx
PkBJ6rZeSEi09LCG4Bd7XqtrVZm6hn8UNl7C4IQpGP9frJZA3uW046fKuJP56KrmMHSZQF9ne25e
W4oWBM1mFphMO9fgh9c5SXpndZ/uOAbcYVM4WSIe+3cOWQOLgz/c5aCN39Uahsaq+zdOCYiRzkgh
4LAsjTYWb/l4DZ1fqya1YTKuc3MwcY7hLUuBzDaQty5BwHN7ZwzcG+QELxIgKA+l7dBiqGfHRmIT
SWkiv+R2fJ0Tm0HcOdYVigTzz2N5unN7BlAymOjG+ZFILimEtJyFeSeZGYvmiMdjAHQPouUG1xYp
mo6hfBaza9gEa3RR4xiMMAp9jlpXrnjcSRNeCACyLj0GJia0rsSFVZAxG/fEuQFTkEVeJliIa/1X
VhmWDilZmXLCcHM2K3OD98VqKhMeI2/nypDDsOD4FkyCWr0TpdQ+cVep2yf1HLZhAQtSz5UdMAkO
SxHkpkMObsPG9AnDbNpRfAoTq15hN66kjqXHh1vXuD1jhlqqTqEqCVs6mwmim6jb5GtgwAkZENJF
CyTODBsW5zP3Ex02qfRUHA0r23lOPKR3gnqUkrQf5IRTz/FWA78X2Y2GBxK2wmCCvEDhI1fgzolx
6yIRgu4JUsgTWckUTSCceRKFX6oBwvDUQyiI1Habhx/a+jKN2IwcUDd+iYyoU+m9HxLq9z4AThqt
4DNL0moU01Wn2SLRzjNCgUFNd9Nh8W7jGR2cWfNRumEOSUDVaJC/2H889qht4ZSVfruVTj3BKkmA
6ET8qMoDcNsJDIZaUlk0+MfiTcDPb+JglPFKCPNKEuXgbujuZAPUFa2+QoA1eWXeSK4XOquNtxKX
qOCedBI+qCiyG5n+JLAmo+mCKlGLL4ksHauzCoJUjFbox9a1kHHY3PvFMZhElk24nCi2CstyneGT
0D/4JyR2fd7nB0uujj9Pvd6UY1p1zaL1Obe6pOS0Y4efxuDRTVXx+7VBYxgNhlG4Z2mYXx7U0Ge9
0jiEYzamlcfRVHLVzbjriAmZUfhVxdw0bTiY67VFXJan5tJ7h/f8CT9jVPo/3MinWFp1ICeIkodK
Ucxq10VV8qgFXEtSq9zLeAjGWy53GEb78GGPsx8+4Z9YToN7JLjMlefcZaV0KLM1ASPQ+GB28K9V
us6jphIkZfL5iIUv4hgo5qiO5ksFKgRd7M2VQrP4Vx3bGOjvWwk/Wtxri2xokDAm3KujC5J/PjKc
dCUcpazCHKegW5DcVUJIeZguaXleLwAbIe2Dm/Rsr+qNVzMeiO5rSXO8PKQSu24YAPvnpAhQFKEd
c2CCDDtpPdIcVUVJQBk8km3gzGKHq6RH1YS9ax4TLFeq62vw+teLUlzViFybM/qkXRhmFMnblxwT
xjYushKjB3fDGKgDSgp34KoN88SPgnZdGDmbgfLw8cD8sFS/5SbAINR+xoWF6xbVA3QPl9qeobDb
O3fnrA4ELM91a/fUIs4aWxmyZ8An18YSR+AwsGZCsajXu96vMwHwEq0qPcbNglkJ+kYhaGmDYSTl
R3lkx31s99EP9tVbb5m3ypbJbI+Zagjb9umKbJorkTH/4fpAGs3qPh2CPmcmcgFAEAW48QT+y8DE
31SgTJNf6XI42hYexAXvSUq70KQiociEoFBR1/15om6yWKPtGKVR/aEtoHMNiOtaSatTr9HGyoTQ
t/Yb09gkbswaoJmtEcbZPyyUfUH0X8GY6h9gMa36jtSzzCx4d70DY6oUCOTsbLZY3XwJK8qhaQ8C
k/Sv9uujYpfGfOuiwl+a5yYUzpnAe40KU4nwIIKqRtCriZiwFRD7b6KdpUzj3NYQx2GZIdso10nY
I/vJUVupq5nhWjBE3W0eQCRkhrCUPBZ4CJbsji0NskGvInD2Rd7DyreUQK+ry/tQnt8Sq2kC7AQX
JmSiKyjXyyU987Ro6C55E6y45Xber2SlI0rKrNk7B/JG45XRagzufl55OlrD1HQSdy2P8kQ95dib
U2oVR8scvJGlf7+GlQNsQvqzvuGbECG+46t0Pvzi8ujzy4IAV3IXLOLrHthnM/gAXwKsRrOKn0kO
gWZzv7sxIB51eodkBeRsU0IFKdpfJbe+rHXY9zjCBO3rGxCviVsOlQhP20R72NYx7EhrF2cUP2PD
ZfO8icyP7z9gIN7kAB8+GiiPTgRQw7wqX9dIVE6ax3Cc6UhJ7uKgzirlTrIVg5h0pwBADkbH6sSZ
9p+WeGRczAlXmJOI395TCAHK4koxfALn2M3e1RqJ0WiGJblUUNQbpZuc1c3pxFs7kH6FzU5WbmZ2
lDCj+We6b4Q24E+T85W2U+zg8c2dtwfC2hsx6IwRhpqGjcuVHxvWHyUFhRwqJT68UsqhR85454xd
pDqxq1AyJGxr2/8PS5bdKmRQA+xV6HxyNHnMA0ZQs4q9AeQ1q9Z/CEtDFegC0z0d22cYMw4lQncv
URUhiGKUzwO9t10+jL98f4152TN/VGZPs9+tHlN6EVqksSuc/wjtNZkpAJivOHVQd1U4q6P5a0Bl
IkL95LSN77wcpQtol3FahE5hEHcpkLwmtuJWI44ie170OfQ8P6Kpoc90lvTG9py1pY41rtAIZLm1
xI4ptWCDkvt9P4Y/y54v2/k0xvdlMFbuKWIGQUGGDw68F78NAgW81+qvqXPg9CHHxEX0c31KOShQ
wONoFqQYkNzREoD+2gU1rH85pMYtV5Ggvk4Yt+9cifxka7iD4jnuTzolu5G4sciLFLuKrFP/zajd
HcRRE86ea56qMZMRzJ2k9hgB8SqT8Ll1tJ3y4EwUCf/Xegxihmqhr4+grBZpXs/Yf1zvYyfE4Z5G
xUD8WfLJER//MPMq0yF3OVkTBhkA3MTfR/TK7WWz3T4D6sJlrX4Vj5/dBxrhe9ycnNc5VrfK8K/y
5HwkRCdo4u0imwvmesygiTJfLfIskwzOmX//tBV2g2rtBNqKHk9CuIsmi22V5PCAB8busQ6Fozq2
jkfQmvbukxML8Xt39QgYJpYxa47X785Iz/wX9hD5hf/+kNOfrHnXmffr+Up2sQHwC7D54zcn6WLW
qYIQ6Q2JJcemYPPPIRECMgNleVv1ISQEhIA6K8u9GZxvqGwzoRSm6EpwC1Q8qsvj6hkYsEAp55jy
hCAYpDcovqXAik+e7TPd0mceXINXJRP72Ppfjh1l9YmiNVOclcWCTQB82nYDnfFC0ZDBrxg72Ov8
rch6CxlNPG7js8U7c5R1oXgCxS6qvrXPg17Qj6E1ICfVpe90jylPcN+FpdJYm2HUySP8d5bYgesg
KKkV1qwupC+WV/qD7imznvwwL6wfSEDB0GzodVp08+CdgoOh++NuHi/3iobuQ1l2Jlv905m26wnv
7TvrioAk6YJaBZrw++2ZzhXl+TbYTd8Up68QJDe8CdSdARBdheiFzD5ZdfsRowTvF5GvlbyYyyFW
9hJfAQBjrrc13lpvMCfEhEnhzCkM+ZhC6ZjHxyaEB8qnv3SGJ180jWFYsBZORO2CLp4hZO7lgAVW
j2rKqSOAPuS4DPhdSvzWCidf9rUf9qPj05AIBmtWvuZIuX6pduuvj0F9cu7ZN9462h6CgYMbLSu+
Oi788EwXwjtchoy42EyTPoe/g/CJV92XoxRWlDToyX/k1HmCS2yK2Gum6zeG/ln6s+TOmgi0e0qO
IkQPGvPqvyH0KqZufVeQLWB33ugRw19SC61p2pn6pVjVN+iDvhpINYgAaunlA0XsE35XdE/91w63
+OfVbOFXsDE2+nB4azfHJbkUqs8HYO+z3t8uNSBXX+mX/fx9LOmWfR3pBzHMRAP1q0QP+D7CSUMw
YhBCNI9sHIAqANYcdn2FzewPv1jU1RKfiv85GNx64768bNj7urg0PwyOkiYgEgMMKPTzZUr971WO
QC7zVvsydXVXZyWSePZMuxTDeVTOldxCc1zftOlUkEmGXss9PRcvz0oJFd0tXS0AYTHL2Zy0eqjo
DEb4C6eHbeq6dX2o6fbSFdTz72u6FhYRZt6fSvNnPVduqHyxOZ2AVjWdXa7AR+y/F065fgeS748H
9cFYEye0Qqw27zpW5BL7I9Mti3i2ya52EqQRrHIbezv2enE+IBSMdektyTcMRHV07wCWF0Ch19Tf
MQ700rhmWVPSrWzwainmUyGnmB/pMLS1iYePRhXBycAYqilZqCnu4kfYNVdxnlShdxeU1/z5f6GA
b/A25BS8w6FUsgACY3TZXnvUXMzo6vNiYhVDp0opOgX6dNNKlXe3oOHrbYS6hkDuZFfouenKnF4A
h2VKXa69l9d7931pBPsw4pyPCiqP9PSV/yBuEgznTccfKOHjWiCuOClj29o8Lfs+62MsbuUiNa28
MPxEIL2oN5iQiglzRmXpkb97YHrafndOgl1fnEyDrg9vNe2YujnmmyONnjWyzhY5JJ/PLzlAZKJv
A9/wTMRea57NpyxHOsu9iAdnRGPAX/xBFRegUUOY8487tjB+wmET7mw8vHNWPup9h0xkiK7/r1uw
5wBPQ/g+/0skhhCBCeF8SEhIv4Kqv54zN+HPvBq/7rOfs+CW7wd7eI9AEDuLwEOlFhLQvXn6z2+S
0Ij4jD2k3X/oANV0RedZoPLor3WdbPVEJQMvucaIEWi3Q6DKKxDWpHxgNUE78/BIK0Sc3TxLyrZM
UUA5SKGvJJ41DbYJ4fDtqI0HIDgTPbj0CRgbWqRWY/omGdES+aWp90kspaMR8vnTf/X3Y027qBbN
mhEtPTpYOnn6nVwEau6eicycn3EdXBQxkHl7CS/lveUJAWMNi7fn3d6mRqlRdst1k3NpkZoEJjzX
xHSFipxRFnps4v0ePE/TxUDdXRB9ZvWLqyQEaKekemE3iLCjctvp0sCPu/+Jw09zA2k8/nNshv6h
8FF4tsAivvijhocxan0Crr8j5InoPp0DtNCaBMhfAFUU545ifEcgI94KkSvMMBELViWvmjaajK8Q
OwQFau/qLIlWMnQXs6t76aal66zC2o7xqPv+06cVBIifEnOiTjbhYS+sOtoPAbrOVGMns5GRo9wG
js7V0w6MXNme/Kk2zB8mQ8GVxei1kBylH3OVVwP4Xe/JC7s5C9L5iA17YM9cu4x6gmeC5EZ5Mn8i
/ZYd8mdRXaFKdHKIkt0gNHsIFROtcstepjonJ9uPY6S6JP5YCHpw9pU586OJUIy7WO0eDy8NbDew
FQ1Rq5QM3okVbDFrxTeYcxDGoanV6oI8nuGxFJjqBB+ysHXyl4MoLkv8WFCZYtFznb8w3Wr696+j
/2nDVjRIuRaGRVFKln75/OJ9V6SOJN9w4bYdb2hklugyT4GmR7AkJTgZhAZuqnYW4oPfH6jKU01h
XwSwRkeZFyF4cqQObwwehcLCMHeBgC5AqZwRFl5RFoP6lMEzTEpC0ZzgxSnDgjCmNhcGr4S8rU42
asm7NlfGJuVuLg9FFZu3+5gBm13qD7yABfaDPXMdgv3wNYGSE0AMbtI0etqypMiviHv5tT6usq+i
91R6dhAf1oM1TOsPH9L8mKumnLHl0Ma7GWnq3Mqfamr6DZYTEKn9v0Zo4n9ZUh/HoJKhclgvwW3h
tQW+L7GZ6np2LUka99v/6TVVE0yX6fFjHA8aYX49OqqQvdxkF6IAdJ10b5t56FWWFVMDdWjYXJIe
aWwxhxu0zQt+c3d/jCeu0M+uWfez4AUGj8zZfqWV7VFAfxIuUVTC1m/uUcb6OKnALAYpPj1VS73N
m+ajBmr0uv0I3AUC4ZNzozi2lprOiBCaTNj0IZlFj2LAF37a44aktYSmL+qybabFi628P3+Pyc+B
lAbAVKvbN0XIy0XEIXm5+2UX4ItagK2STNIIy8b/BnryVRL5ZF289AlY2ShIO8S24I4sjWhR6/iW
ToI/3EBeb3Tt5Kn2la/oBFfRR/z+lAeD8jwBh0Qi/UjQj8IsJStXq0RtO8dQmHYKF3yu6BjYkmrE
LKGkJK/KogH5vNIK8eDKtPG7s9pZKv7N7KY0t2BilDsTGD9bKRLgLakT+PdCMOuxJd5VS4wrAMo2
FMxUz+3m9ZDZIqZb3H355+mfeLjXRXi/L/0cm3zW+ecfm66kqo2lQmEFa5CdZTiA1MCV662jaQ3c
oId+dtWDOJMrd6ZBtsej1xGwfrZdHm3TRwYAW/TzPrvGAeKs5Jsu/9tPyH1ZzwztPZcksglM6v3S
92QuLIoUyq5TZw5K62o3nI1Jc5JgjXzl8JYhtsdbM1201v/mliNyL3DH3uWFuPvQH38QgN7IHrVw
ZYTvp+jWVH2ykDMl0Mxa8NCODvAoKi9nWY7m28x85Ye0t5LvnRD1pymCdkGmswtcP4FPfe3GYCHa
GHsPBJD3vx26MuqyTdFDLHZ/Q0yw1196sEKLkpMvtugA7VNMa9KUJxIoqLgwrCNIzd7Nme4pjilj
XFWqZxa3EAWyEh5N3gIEF//6s0Zl2ncAavd1YWzy0Dq+RlPXJ16FP3ENkDh5JXWntfzAoRdbM6v6
ayd3U0OgxE9adKnRw8PoSoun0jhRwpUayUY0yxQNeypSIG/2ZauLJXE7nhXwK+Lo8ABngEA4Ktzw
v7Fj16UHq1KTMf5R5SQlNBAKosdp3B4XWmJjjSi9V71TmVXSla0Qum9G3wNMchGiBv/7mtoJmwyn
GYEnoFF84G8yY5Qq56uG5CZeeyRTZ8zCMtJ18atBqWEDG0FbLxsS01fZ5jHM4mrncVDobYhcc3M9
oTQJxJcHk6lp8oPqfZu3Lyk7hShMIqoM5FdfLnjOJUe25LF8lmCYim814R255LQYgdIb6Y7ancEL
is1S3VDTvsZoXNtL2E2S3ZCwvWekfVMVNI1HfouMLBo2vQ610jeJUq8RQ6dZBkHHOpb0KjkqCm97
MhUubQkvNVfp+of0APHf+4888jAyTFrDOHOTof1JokSwfhEKGMyu2nIZR3BVImJAD3uq78Fa8TUn
owZWl25qy88aE3GOtUexLMVv0zsVjUHE5IEJL7/EiYjIBlaxEyoJuxtMizveJq6Cnlr1Tw/anOH3
btbBvWqbSFlWv1VZKvnUx95B1frbN37IW7Le3KWB81Wemo7gm0omI7A3ZaQ4oh3mMsytV7lCYfhW
xblBxsuNp2ImeiBCuuBmSKXxnWw93jGUCbrkSXstB/rV8xBC5tJaP5jteQDSgt2fgIfHEoe0M3uZ
XmMy6qwweoYufzpAQ96GSK6AdckKaVKa13kWis+IQ/uZQyxtvKbo+g+CoRBqdNlaksYwsdxN7dB/
plnr+MxCi+KMonz9RF+Lf3KsIuyfzkItQSmlOEYWcPTXPxCy05VmftjrxF8NCt8Oq9bIPvTHSKQ/
eoFvnxi0N8mdUI9HoI2V7QGCI7vlkSNNIYuxTbTjFMmUI7Dv81RhNfrMw5OqMsbrQwcJxxj3wvba
h09th0pwYdkH5WlJonHJuRDGcfZtVkFO9tcBcktRGtVyHRqPKW3WPOhlJ1CRxT1q3rm7nTuHdaoX
JS3SZn+f9LusJGZDFrs0vUkwYu03wlvWGu4Lr5L79L/o6X5kRfqYFAZvyz0XxWQ1kq6NSLndu7D4
Uwg9IrpKT9QfYsuyhGiyV9PtOAJNGcM9stxR+ksXcyL3SPGKSRl4/XsXUFWui4SUMm1NnPkEfmF2
mDT9U54uhlXtb8cqLB6ZwBLfgdgT7PPFNlxKvEs5CL6SwqLxuUNn5QkUgtwjLghZi8TwbE3TWX4B
yfSAsI95TtQh6m0kh/LlHxCqOO4GclfJcpvqY33il5VgQkP7BLkYD2wTHK8RZkqXUq8nrCCTKlBK
L+e1bPyerXJ4H87S4mCtuUkbtEJOT2gY4LFg8CBK8FR/bk6gWWC5na5obQ4te+9eQhbqoiBs07rS
iu8RkQKgc3cdknhM7hgZmOPoFgOvEv/FmQHpMbU3yfEmJyJC3mGsFTapvqFOTZx1nhPsZe2/oxOz
1M2D49Fs7UncbHZ6e/0o0gK946eMVsGYbOoB3/jLKLFf0D2rhlsfeRbiBR396WlR9QXHV7z+og22
wLB0thgMpS0TMvermjBmkPUPl3n3Q8868avqZxyA5uJRvPAASHvXty4IedETyOtMs7JrtoQc6jFm
2//LfKacx/IuxFwAk01NFbrpCakSjJ327TRGKxXhpfvntTVC6MaCGg7s9DOKpusxorl+LDB1jLdy
mdLb2JFIULscvpy3iCLyOXcFfA9q+wgtxEzGwPJlBmFT5buocW4DO9Jq16ugtduAXqc1hExZLxth
LdvnrkIOHMX80VWka3+fNclFj+HBeH6nsa1Lxkjzw946N6KTIrzWFMhjezNrpPaAsd4uhSt/Do5v
6Xzcr7IdPtsn3sS04cvcRQ/2s7db3zFV6yv3jizVcLCiyLSKFb2wrMjvnS2WguhRjn3KMGrOzgjb
Oajtu1nISPL6Kd2bGUjPoQS/rG/HJDtXVWJm1er89Vu5Pss8MoZQoojZuuqkUlCEhJ/DDQbOxkJ3
Ggfl9rS++kVqLX6YQGbVTSxayDOxW9x7uuAFjZYurUcCtAxHk5fHUd5pXLXB6CynvNdFI20KTLZ3
eHIFRyoTT92uJ+APkMQeroomwYcFDkxlgkHmbordW1RPkre1rwlJbHrWXJ7KDfNIvfKAqVF9s1n8
38RbocQcUcDSiHpnwuMUCbQwe4Aic/TWKDjeEidYZCBuX9u5RcKnuOhwjuUALmk0NtzrxOSQBkDx
Tx9OzYhGGOYsxoOLzaM4B64D7HZ0yFan6QvHZQgO52PQqWjubcnw9NQNKRxcPB/qr2CuUY4Np6g6
QghAVZL5c0xIh+DASQ81xGHcYYO+xFxsbDdJNRrtAWifyLyx3WLHJm1xSxajTQRIH7eXkeklk8N6
2j88OUvFe0WgEMUMCAgS14w4n2zybnWnRA0Y0615RLenrQmiVU3icpTtEPNZ9/x/TiWlzej58Go3
H80HJw50YzvhUaIx8EjgdQtN6CarZ01EGxdN+PKMABW6WXU44FmAJJPcYMlAMT7CjAv3QNHTL9T1
rnoIu6FjdqHvfVGvtphzVjcncBfqyhe1uPaBV+E1M8cUI3e9QqmaRMbg+yeH9u+qqKhEOtqtUCOR
LkoP8AV2/cXyrPlaT5XVaiE1JrjED+t7wLjtixTtPKeCZaDsBpUEHGgDcQig4yNAaXtWimGECJal
JbXLyDsajDcQkHAq1LlVFlJhFXGkcOIWgoU7fUIvtec2S5/dqrCkhc2Kq2NNVtFGyN4x/xstugGg
1kiFaOb91c2aximvRO1bePnejRcf2AR2OMbqI17ynv+MjteTWTQds71AwTjo9gnDa6RKtadafMjk
jtHgEKS9XCl+s05E1UpzFTKROXnKqaDCrO0cb1MT0qITNyvH18Z4Cvfs4lvY93AE09NSB8a4YqHQ
knRgsgQxH8Eeb92E0ivqEBUHm3crV0Ih7hqXOdvd/K3WhNre2aEeQqc9beXyK+UL8s8VOjfT74Gm
mxWqdu4TJbTCj6Qu2KAtVzoGVcZIE2R65QCpJHz5zBQvL5rdxwRqPH3pcgO3nQJj7S1xLn0AB4Mq
ppJgH2XUoIT1QTJr2Qvx+Syp8p47KRLWPRkJ7vKKIj6rb1nm0foUY3OBrsgOlM8qzWr3oBXAC73u
gEYY4a4ZH6kakTbn04TmgP3bID+RiUjFTHo7ti5m7E7btSqury0Y056QgnGbJfzo3O4MDwm73f2u
4o6zGq+ESmk1z9YstONZKsonCixcQoIQdz7AGX3EGfasLzM33kOxhdasoPozwL7L9xTBK20Ct3dj
I9QvngBJusMf2ZV8J8o8BGUZLgol7ylzKm1icaA55KCb3LdXapQCyoTJs5hYTVRf0QVZSLsIHieV
iqkJUpjFJ4cfWh3GxiSxFz3D1CK32d0OCWia/vLobNMfZw28cG2nJoYLm3Q1OkrTVIqzkrC0yMUs
W+ZpUy7rgYwBB9pza+wSNkQh0gfg1F0IX9zdRvAr1bZ9IXeN+MmjJJTVVxDx+tbbA9/ZeU0jYmTM
DZstOiwUUv3PJruQb8uLyfYP8UL/e+RiGsFBs6K0Wi8HpE6VSM52TcnGje534PjzBVhvYKZzvidl
FGIArU+gXPzsbm3hYC2VeFZRrlWAKHVialDyksqfdg1VggPm700VOaHDGo1TN96ssIGCyOMTpteB
GlA8huY5aP/o6/hpF6bI4CqTKtBLIzms0Eaw/robm/7zvuh7YE4TU8comcxuqHjpXyWFXy87SViL
xiwfYGqFPAUWurrSFpa8/cGLdEtaVewIK9J9a6pU1VNfOnaYH6SHBidja3INJ3QW0aPs2VdMgNPk
XxYJUoqV24EZ1NsJRsRv2ITECd3tCG/YgJ2ce/uilKywLj0FDGduQ2d+k0AsEqN734tfUyzdu+yH
WUtxG3gu42rk+Wv4t5zWpfsxEJRIsVLZYKUvGJC2RgTKXbhCEJ9gE9Kn1OUlGZo95cl66MDk3bhz
NaJukrJzOPZL8yhGQNZnMQkhdeKVrleaNdq3nRebA6sPKTwCftqCwCibYjalf7xr8Vc2s+Xo5who
00RZUi45LrW3jpmPBlhNoAxHr3BwmvYYaRHdnwGZVWCufh78eda3IyYN5q2H65tRoQIY28ZoWmxz
Th17PGMS3mdOro6bAiMmdXTXdeL+vnDTZXiI0pxq0ywtS0xbEMh8N7Gi6ylQNwRpXPBIt9O/LCek
le++PeCG5EktTJMeLFdRB0pwfAGmIFy5cLgXE4MsHvo8rOyFtBfxSg1tWGLZE+BYy3XBD9vGX2qb
48EKbsLi4WPfugppR+J7lrt070wastWyykZy+tAMrFc5Y8N4mN6cd7mhA1GvhS/lOfgJnhSntoMV
9r1oRPug28FHjAvlpOt/Q29TsVM2d648fW626eUc0A6479nkQr2zIsKrTY9AjSXO2kCnNqV1N999
Q57q2Y0OFut9w5YzlZMFAS306EaJgFWmDSU7lq6WHeKT04XXfAm5QENSFOocSZ6ogHEwDAZmOZ4q
3ufBJcxX45ZduUS6tJFhJYkvQbYGXpYF38KxVhnwVY/Sz1OpMfrL4w+0lI/6oCXuAzSa0HMVw+t0
wGxC6Grk1nIH8tHrMlA41OQeIsAOCKI6hcDt6DbRlm57yQNTcf+c2baRSwnsr2InbpQ0nHoLTxsr
zqFmWDj/QjOru6QWnqaOvLHJpbmLh9P65BxVL52Kg6u/MU9ZuPsnM7jMejay2q0kuZ+th+2RzyJc
OW2T/GYoZdlYZjAG/NvLWUdBraRVs3t4ErLxDFoVSQkAD8dJ+HRSPrQwmtYHpllB/42m/oVhYmos
DbCyx3vH3cX0+zI0vpGAH4Zo5NKrLtuG4w//dbUNFCVWLt3H2mtWdHW5ygGudIz6T0nwqFPj6ZBk
fojgF0OjrXVuCA1wnhoK7MC8QbG0Afdfi5imwyKnXuZ7BnZ5BPcj88JFlcHM/wRVIIZ7CR4eqna5
crJqZVj2GOgMfx+nq7gMPM12U0VyfjGaLs3FKyle62+F5s8wNpopTrgoj1wFqr+ZwxVEmL6Mxwd/
LkmusnbZr7WhvGGuHWXpUmD27/awDBzVyvtkccVZ5VDFl1Tslk2j89YvyxZOZkFPxq5sk83sxlXk
ov0JqanH14Nr+y+snIzBQ3kVrl4RcfSgj9wjS6WJucRRaXw2/aax8/UhV5Pu4vqitzJevGChi69f
pBEJ2q6+rxQvZfSf20XA6DfoD48/m4V3ofTuT9UqHykiGMBmLPxkyVsyeeuosrmw2Zkd1GrORvlp
4S2x+0IHfzBp28Ykd7I8b6vjLp1MkLLGuPLJ5IYL8C5/S4rAyXsuTRfnUkMQ0GPnPS5O/EyK2hci
qZ1JlIJww7ePu9aA32fznjZMWZHSAV2NbTrHqijeUz7kMpV6Xtqz2ZCWsqv/qKf7tZRNdAOMb/58
JIncMUCfKJrGNyh00xs3y/TY4uiuedjkW4ylNArTBM6OmwZBYDWqVV1qhjR02+82DHk+LOHAZrSe
wpIXxCvN7o/gGKT0zTmlfLOL11u3jZNMP8fBkzWlbMHwspfnwJ2zqb9t71xSNiVHTLpMcEKMODbJ
LcvW7CO0tDpzTooRPHl4REDILA46OuuJAORPsrHxb7mH5uPShllVcQNyPyvZRVQFbfOhNdoZ7L0Q
9QvrWSrhFdG6iYMgSL3n/EVjjoaeoa2XMPDf3ST+1BSiDsUjFUOlC4M1jBsJHo56fQ4kqE7Wubf+
TaguNyLF3dvnmClE5X7Prb+tBhgSctmFYndul++uMZSoXSZZQ5hjeBOuUKhWGses/ikMpWSE6Sq8
94GMHHVUJXngWohLXO6z+UDOIM6D6SLMaiuhPtvRCWdz7Iq84mfYSonBejK4FEbpwVRglYJ1dsVg
KundW3wa0RV8tr5GOpgoMmgY52kUN/+cX050tM6JT09UcmA5adLlUaXNlxrb6VIZ3SWwpBs/kgyz
3Oa2OC9bgWDYVcKdIR2XL0HJQfv/UWZSEge+trNk59dzslrdVVqD8Jv32GD3HXKuKRH1Ly1Qo59z
kJNAyMl6fyT4PDwR067ctq5Vv/PvNgTunIFadz2gYvUQyBEc3K7xpaYRoszK19gAZt5tyBTDQ9yZ
t5UuiK77eaD+6X08oCrD37DbdtF8RaKjEZ6zf0Py1Ps7k4eQAuaf7yWK++Vb3Bos4j70PUyU2gZE
hbtwzXujeLyT1vlP5Wt/s7Pq+5ZKaR9Lbv2MUpUkClsTjUr/J9/tMyYl6flV1wkeb8kPBTMPMFEu
oFwfCA+lwxMke0mjzEvEpHDSWBGzdvYRTLP1L42p9l4jLQapJyOUf9iLfccJdYBzkTn7wqQuL8XE
l2Cxdsx6vd2V6Fvye8dsBI4En7WKPcKQDxIh9cw2XAqxrZbiOhLXdlLD2emT1RwqrBHsq/GC+NQ2
TZUeGT/zCkTlpDKJ7PuQtr2/kzmNZxKiR5pTszHGZAvsHK43V3Mdv2V9PKAxqg8x0YBYfdDgAsbc
EZvJowZc6D/lM1XQuu8VM41cx+0Gjz1He9yT3PhI9XWRJoMlR9BH8YvExcTxbx3udS1ETj6kLWPO
AFcMthZafr8BAD+83j3U6Iego540tGOCFn2u/OyEXiZwc5HE2pyF94HtGSDQiSctA/wblhAYK4s0
53YmdKiCaDB3xEs7QgPlx24u4iUNqjIsvhQgQf2qsOAVSjjR4kpvFXyiJVhAZcw3yH8xZKJI3fng
gGYI5b1HNJCt1gErtUz7TXcLCACn58DpNPvDDwU2JMcEHrga0gcLeI9nzu+L0o3PjwkQjZmP403/
R+rB8IVLLUWCVvAa16VPJOH2rhfpwS5V9mO0Yv5Y2er5GcH23uyflDl6A4U8Fh2L71vGXktyQjSp
nmLzBL0citpx+iCmeZxXlE6J0/rDiogXyaY3n32+P0OengrY+u7oineUx4SqEhDg6rOnkUGT+0mc
SosYZs3gtMYjewh2PuXH+5IBiVrL7dZ3Neh9lF3T0hWQBovdONqE4uipGiE3JeC5q7BgnJQqcOtr
LI25CpwvRaRDncougFAXq0ren7mc5ZJNzB7NtIt6Ehlrf2K0tjFYfFVNUDlQgIIutD07wneF2QJ0
LKCcQfFbXLm74HW1HiyG4tCn19R26/L37UoFiKqlnuWrZgXM/IMDFJulf7qmiT7dMaU8489s1qQN
rWewfTtrMNvA76ob0ruzk/23XDMiddLKPoWSfnidALD+KGd1z5Wzc0ux9E5Zy23cZylMhowOEGWK
6zh3ONVT+ozYy6sIdeA6hg4/QGyPyFT6mP7ZxkX8vS2Mn7WKx4nQ0hZspVC6YitRsERnmuRtjkXD
g3BPWKPWyqqTTSlxshji4mN9GwNLJy0EZONchEN2gq8WoCzgDQA6PDSgjDwsUBVVuwCsSh8RBYfa
CLKywyCC5Q9ipXpQmf0rP9iNlZeHRwWBtmvUalewzQPARjrZ01aKlHELUNsV8JNa9nKL+2wYeuxE
zPNUt2NOoPWeOuvlq+0js35DHES0s3ltRt9OTHcF7Gruh/63nzZVn/bUGEKZ/NcObfXJAzCUB98F
eK+c/TViwz0bhMePPejI9sfMH457YpSDGTvKlLsvmYhINeD0Hnr1yL9Ouet2A8LFCRwL0AWAByPO
4M4tjPYHWFYmNnaXSoJo32Ejn0DpEMYXHE4+3MIyNytAyUh/ZnmGBTG1VDNVtDA93q5xGW0sDZc+
gvlKDNHr4dBVEp6xsYQiOhH4reUOsao+Y9FPxBwJQAA6KfO4f/stybMO56RbnEHOm+kxbOCj4Qzn
xvQNd/RNTmR/um5gnw1GIQ0VYUsGmELk6x93B28ieQp3g+hNUtDz2Vu/NDA4/jqU8Y4RgOJgcOdJ
mPfwDmkWFfsJ0z6gIHmhVmfJQeIAalovckxvV9jY8gbt16C0hqKJuv1UynIHVSqmH8rWOVKx0oPT
iBTzC66elVwYvhQxYbu5Dt4Zah4KWDcCfzNHeYAXEhOXH2ohUo/8KIMllS4AtVmRBeHtbPcY1ugt
DFc/CDlfB5F5IQJIFnkVhfggnktmqFT2tJRyLmJUs8lDxg0dnFXoNB+k/1FGyBBS6Ha5C/q2QOSv
WgepisVsb7Bvhb5oW62CSaYyYo9a/SFCcvsXaMWobDyI9YaZfMlEs4OVWBhMSQMkxgCM/LlV9Mxj
k82WDI/vz36XHunorORJ880rUvMxZp64XvrNtOEa02+7ct2FkNzbFSEDEyVDQ/EzXzC/KA8JFssl
8A1S77hWbZHw5LPNGBHBAQByK4OCMZuRghjAg37C4fGNV674ZMldBY5JMIcF92+jgbFLYPrcLeTp
482tDy/zU3X3Lp0i8P8BppIn/rfloLjeeH8XtMGfpNDhF5b78SclrWCgGuEuKcU41m0osWWnXVFG
dnQSlAysC8KIODKl87TL/eNW7twd39JFzKuqQcDkIeVy7HjV4pP2wV/0x59YCccAiD6DOp8ZGsUf
Go4wTefcte0qm0v08rVYObJ+dLBfDtwZlPhUTvwrm7l1WoOX1OG+q0VuNLo6PF3KYx5X8prgBlNp
HZUhy5/vj5vKxufEdiUAPXldUWtNAwpdgwoMM0dMeAc0ZVgKLwscNYxHYgpPAahXhuTIme59NfY2
s4ktLA7E2UY+rypEXA+qNFmEiRe2lh4jDSt/H5N+VLp1NQD/+1SziqmTX2DKXO84XJTRa1UUMQTE
BGyd1f/FjFePoR3y/rD+IBsuzsQfq7cgWHpStOjs7X/xLOh0HfHGaTiTElY08EhzuQzhDiBx7fOw
QfT4JJmyRMMq1sWHQB5fYOAV9Tkhbo9ECtGYAHBSy86iLKOIIyD2rji5gxGht1etwkPmxyenTYCz
Xmq6HSc35+KUg9vJTY4tzDz0KchPrAlBzII1zLxAatDkdpGRJPmziYZCtXelcchuTH/1YuTThoJ7
f0ZdD1ox1jMXJFFYZFIQFYyHZz8hsLvcdeI7D0QANYRmRT89K3N3KOAP8Jd7Y96RTXjiO+PApl38
RxIn8V5M4+wfc+a4MkbwBEsuqXqTtH2jVvQTOYBTa6oYf4cshW0/mMkppFXndHW2X74Q2Dc2OljZ
gyLQ31M1p5dSkbTvmi+Rr1SQ42oaSRFQ8qDzzlQ97+gQP1/q141X17jvR4VdkZwo9g23xKgQlvM0
3AGJB9r5kXGzXqOHqco0//NS6T4ZtlSBQ8vUzhTcd8AM3dBkn23eQS+7hSlW14p/h5uYAlpGA13j
q7O+04S6Myp+mbmJoG2SDjQ/zUHjFfahgKHCaQdU6LYzZ8/7UD7eRnJCMVCy4vL1BaJHW5ONTlv4
uBXjW/mYtcEC1kcu1QRXiMaSIOMW7H0C94hBcbexUwLLjz2ZNFIlKHD8iMK/ad5EJ/TXb6kbrId1
pOEY/2JCcWJsLBMxZhv6VcFui7YJ0F9zKGNb23L2JFI2Z0fTkgqs/UOGTQlZzx07Cc4pw4ZHg+4x
krw0EYgD+P6qE8VGoGkh9HTGW6oplcRrwtrtSpctPU9cy8TAOe8Zf9XLkfgyELOWNBviANFkFKj1
zVSb8HHUOSdMlVHdSyBR33SEvb90CSFVTQWgfVIwdH+NtAx2rp0ri8w9Nq07lCDkZz5+CMCJlYfZ
6jTQbeu/uWGKZvH/BaNLF0viSZSGWIAHgMaUA/LVK+//cJlmU674vMGAmBCC0qO6AEIP9Ouaq8+j
u3rwUxlBF7HSXAtxoO6fwWXm4vm7d9X7V4vyv5TejMU4X+kDxlo4jMQrjvUEgRfeEH41DPQfKuoU
XHEbEzJSqb3MwPly1m8QT6xHOsfd6MYiTJU6qxyQlbz2rk4RH/Zp5s+pFq8e3k27KiaddXtbs0Jh
ny5ymV7LV6znxPlh/8XrgYa7samye6vRgFHK3rlXRq9FirxvKyz53BaA3WQmy4VR2ijnw46DawgJ
Wc4zPg6BFdX/L0OeCudvWsItz6WngnhFvYx6aCFxxL78trzIeMhbxJsB19UujB1bXKgaxcx5EZh3
wW8DuEhloPSLiN1ovvYeX+mC/Z+ZlZXrWDLFcV7Q9aB8X0TFcJAPJvdHNxO1v4cnqWpjqKL0AFzD
zhjDdFXNdOX61qLUJX8qCfHfKZraDlgqNXHQCMFNElA8+RzrA2dwJUR2gffd5xvrhha2/AwssbK+
FWyxeA9K4kdyJoP/AXJbczOIKMRq/IgHpt0PIIdQYXwLisJ+ZvN7FNdAh3G1xQ2nl/8snhm6gw1O
k4cgsj30cj/D6Lbg+OzM7ocJGDnT1Qo0sYErs+c/KW5GPXRLycskB6xnAoIFq1JLLvXN1AVhsUhl
DJEvt0eWCwvVtRQ5OFcarNIO+OBaO23SqyKWKeBhqcWmTAaPMpzE2PBldrl6VzXl8G8UUtdEKaNg
C5DzRGgSQbnZR+zmG+/iVVtOsW9or6rWetSzyanp2gEG39MgGmtOKuhPsMKVEC2b6iiva+6BAm1z
ijb6MVLhsTEHU+U5A+kkXlh7tgF4qsWR8S5jIuTRxsm47QFdFBccR/isNkJiilRGmZw4N/iX3Urs
hzgvS6twm0cF+WGsoebwfb6j0gQIYZxluHZZQKtPb8ulROsGFLVLSrl8VnYZSHSaRnFag3gzVg7m
Mm1N2i49m8+rJ+wU53r+GS7bFVlbthgMe4QWhjuOl2b3rMSxUB3211K9cyLC4lKr1V7njLqSnGLS
95RI0YnxVJnKfb8c/l23xDtvvnIuQ/NrwtzPrYGq7F5zedIiUbF/9rAmeR5uCSccKtYGzHukW9F6
RUSICthZ6p3SeQzfMsxcu5s2BQfZlPpX+2b98lsgZG305dv9MTEyZgv3tdpxpsR5C6fj5P3eO2Gg
eprpbQe3GFMRKfxhoJBFj525EUCXPqIUV029/p2xC8ZAodQA3pol5Qx7VQNpsbOLCWZ4VPECGuZb
LnnKS4TKaxkazcxhlHwpsUNrXFhbnQ+iMxR2hp3b+poeFUUciCjeJer2WyXYFPf6EAIMa7KXAwyN
3y3kNgu1jnxHE2wNUVX9D/CTlZjJKDLoL9jcH7T4eSSoVZYzWd10ki5gXbzYVLutAbjj6YijzVhS
flQI/083/izwu/mDHVKALIggPl99cyxdg/EmWP7y+PFdo+d5EIgIwQFPFfcUILb4CeeOELjyENaM
SUHAdYCt81FCad874yBdH0GG+OJbx/ClcEhfD4+ZKvnGfoHeSvKO0PUqEU5DheipXz23RQIZZz9C
BRIH+i0LPAFuu4h5IZaCBzWxL5S6Jz2k3ndzXmIu4USenPGbKmQ14QafdQqMZYPdScOfO09+YODY
DOAYpJN8p88r9P2ZW4zOhrHw0WS8mmfYpJQvJZVqy/FPzpDpYP6EifgvG4raLEvwCSql94+pFi4A
11ZWAOL2dfInu8ROS59jutFXNDoguYZNiY9gP4iQSt0R8b+Unok0+eyWp8x4DUGSAXROwku8embZ
7clF6sOUZ51SAA0yDB2Bj7BO7ZMBU4GEIs5dFgfsgfYUO+RmSvKxHx3LurT0v2CSQ0GQ6Y/26iYT
KlAkafSyTDAC4G0xX0ekxrAZmx2wDVrFRuu1TRy4S5JHz7QuReP6r74UHpXh5W9ZVDW75Sd0b9tp
/7CgsdoaNnYogv4xmbPUKBSgQj0xT6eF2DfOTejm7J2qR085aXPr8uafAvF6hiIBLSbwZpEwzSS7
UHBQG1cl1Zz659U+fMS/kbq2pFUL+iZulafjfxVNjVu1q8Cw1h1dqzpoIkdNJ+qlaDW9Q4GB17XR
kz9eXJ6fogV84GOhBWhw7nCbhI9pAdcVukq3X+e77LhbxHRjdC3vs4wVbe1Pl2M+35sccXENUaHX
w3MtQ+8z6/TlY0RWObw45BgpiSH5xWuY9VirGjP1aoSUNajuGiPd3zuaHkwb7ud8LNyITz49t1M4
M0QO2JoajemH/WaieCFjmnv5yKBTdGie+jkCKqg3wsQSGd1H7tL9yeq/mET428mGha3xZbK6SS2y
/W07hT/0iaDavW4bo6LZ6AuOhjy2V6yJM3u52evZCDKlTZ8SnadgX1MnQGkQy2lz0QYJbJUfPbO2
1ktzsPlDAQSLP09eW+o+Xb/lzZg0OMIsoPjwjjUvcvsYbRwVVPlVFjmB5u4rbbpVryJdIvwHg04M
WgdYSEDryIEjYx18dDNFV8/grdhB2KfH6p4NS78wKdlE3VMe6/TashF0XsBmYhRcfcy/gDnRaMO+
kbO5lbr8LlVXp4sOn3YJRhKGw+eL+RI+D+WIUGQ/oMJ2wswCIqO6EGRlMo8JOlT3bLWOsGZ9oZDx
hJWNvEkM74f3rtVIc9v8mEXcdIOX6zulLtl5GyenA0hWuobOVLkxyK/R4Jzegl0ePh5wzKPBXmS6
h94Pqddn/xFEOlOK9ztpoa7EE0vomtrtqKmvDqGZ7+gLYVduztjNL+PYoB36Cyr6IK2u1dVwK/52
JDBtROIThDZPj/tJ6WF5t6q2+I8QiufP94Ji8CmXoM4aIgkDhq033FAILKemv8E3lWb29nQwg6U5
CI7737rOlmxlo43tf9aDouzrbRO+KtNDr2S6L9a3W1g6TRZ41ezQLoi1GGZ7r3lTcWw5XpIcc7nX
kxfNthyGCvTjUKM1vrBpOhh0FAWn3P3gTZmgVILx9xvg1HlzZ3PwKCYZdBhxvVKwNTpOsLtjML0f
aCVXxxL1Uufd0XahCPI8BFlKE5zNc3YF8OIC6QzeGenbLCuxVBIno0tCYKvUisFWmOFNXJ+ydEOc
o6MfZXLX0YyP1pMDT9YBmoa0RMFg0MNWiGqzv7mTgYqXADbEFz1tnQF0u9Y4NCPboC2nasuXJGA7
87xdwv9IauY8ZULgxchNOPp8NCZ9GDFJwwEzpHfwIE3v+VKW1Rn++7bPkU1oKn8Z8x+pg3za2q/0
YF5b/24/hspJk3S8Ll5qTczSrZd/4285K1SOwRICbz5G7jIzXy1bxcq6Xr3TrNpk9YXhklQa/EPd
nCpSTSPPH7sHy+WmiO9cSJpviAiK9o3pbPJ6rqBGgHsXRoJQvFP+3ib2cx1aRdHVEPclapXwxue0
b1O0hgs1BcD3lRbWVlIugtWwgUnB819JkoD1YpzHLdJgQ2UNsPe28mZeBEZbGUDS7VIYUefbog+y
M9Gi+lNOY9tTvRCb6eghS17kT/UTg06tckdd+BlKwHmTFdcNcWotTiNABf1pFahZBbe4sfzWKpFe
l0gqxmcVnWTOqBXq0vsywnphG/20fCKrVs5pAQWMxFJzY2+QEqioWnhRT7vR3CXRode9YO1iAte6
gG3hDEGUywCHyNJ9/6TtSp2LUealLvqo/R3m8NjVXofixzwvMJcX7o8+P0q6IzqGWh282n0JEGYI
4h0ZwASUL7ij/6zNxWlLIPFbtcqDuNeLLkUCe6ddKcgmjG7JBFmGh05E26le4ZkTm+QJsiRDmnzN
xCLstMYFXN/GNzec8go5cWrnXX/zYL7oBNkt5y6x6zqwPw1kiDlIQInajTyZHWFehLZaTrY8uJUJ
6vXl2CVRfW3c1GKsMq//i6Ie1D/gblyE+YmF1Q+YlSNVPEsgYVKah+tcpk6waZogzRSdbNtTZIYF
pxbKkw0KjWSCSgbnmrGrgBod3K0PrN3cMgQzplcygC97wwQHD+TkIQWNEFadO+ridDuI/NnTS+k5
FXc0/9S3aCsYU78J6xSFYoaDhXe4RenYu4gChs3gCZM+2gAXZ24ttGAyVnkabi765pO+Z/ix5dS+
jd90wgg6K5BtndBelrmU/2aWLJ5Udi2oZlQiJ2lrqy/gCvyFGcwjHp0zIbhHCky9Szc/h8LTS+Yf
+rNh5TAEj3JBLOYlPD+95JUKR0l1oBvvLoc3XK3QvDLXjpYr6EteHlhmv/txjYpx6ER9U5FHCWFT
bGSov4fvZsEEH6N0HDN6PrXRkfv9Y86CLXyyZN4hYIMN6qcZ4hI4N3SmPHMEfN7k26csa7TuZMsj
Qf3vB+jelmQBPzN3ts6dQRn+CPqg6jbQA6lR3xgPhV0eQbwJ5wUvwKJAsYOZImowl2lwyVgrZ9Rr
ekOMI9iPxATz+nNCV5taFhdVxHnrfWZFIdGkTXjEh4jMLrfEvZPEgQE3eL/ypSm0a3EX8n3I0jWx
7tamnH0x60ij40xVQzHMHxQXrpjYtVwEM8mjWwEG4Q3EwLBw9R+nChIl7AB4qFoFt3WiJjtsG2yW
j0MyOJa8JUWteMN3Rx/2W8CZIw2TL6hzZ474nYoYlvjBAsp3Mwi5MMJR8/jPl7a+xzvOtXMI4h7M
8JltU6qZ3DYLfJfD7WUSVeMQ7Ae3bRxhnq6lSUhzUGr1sTDpikDEpraxUwekgdGoeg1wau/L0Lh/
iEVbP72uDuLawQR/rDXNmTUDQTXC57llyVvPqZzam3k8dKpLiO5b296rw5+M3/4RzGAmkyeBEi8s
yVOVwxbdXMwqZmjGmNVNj5Tm/RLoPEIqnp9p+M3wTwDqetBCucS2No38YhkV5wXRlwHl6s8l489U
2YnYaPhiIzfQ0kfTVjwPlJjE8e0BVlGfQyKTyccnt/I0dY+VTVbKrPE5OSiOssajWNoJ25xoB+Hv
5EQv7Z5rVhmIMpx9gsZYpk8fzs+VYKIwbSOOxaLmUiS2D4pacYpCPDRC+5XsRbCZb0d+I+PFLiXm
mv9XOzD1tHNbZpjMnRGyGCStqjXuALtGHX7NUdQ17zovs+ppm6tE2kkYfMAkkRJ8M2HeP45UCMxo
MZS3mCsbl6TjZBoNSqBBIMHCE5INNhctAcDzl+AaRkXpmYxgLm5Dm0ih9flZCe0RvVVnW0Iyb+dP
QUUrTUuXtK5ZXDmlZeXoen1/Egp8S8xTl+OFsdwq6RVPBP8poEkqj8DYvgCVpcnUQXYd3SimxGs3
0IYSLEHWxGGwtFT2bY5QyDOTETVJVtWODwkTyPxQsp2mFsAoPexXGgtaMj7CdBodAlvYmjQUhcaW
RT2cXQmgMwFp62xzRG7ir2IDYA0CJYnN87IegOKa9BVPjin1Y5Rxbnrs3a0UONix4fSTn49OTnil
7ZwWmcJmMo6MBC1XpviF9q5Q+3zBdWF01ALxh7OQeI0hxMtNci7OeXj6/RvZQa/3z0Y4SijmUpfb
N18dDI4iyK+4ercMRndSeqGFlx69R0+qXwBsbE3saYY5KNTIDNg2PZORCv3KbgrGSigDxxZsf3J1
FPGwb1jOMSQtAhnBwjGuWrjhb9QJttWZ3boIkWFGMOrnWde0DzCMH5CSLecUCDfOwZYb5e3GvlXV
bfBXx6AT+zPalB5Mo6F6Fx/7RgMB+Eycs1kdwotah5lChq3ErqUi5Sl3kNWE0BC1t/ofHisntgPD
Zfv9rrg5XY/ChS5SmNKf7iJzdV2eCGsE0zvcmf3Rt19DYnJzyFUeUIvT5OICyhjLjFpzu0O0YVNO
GxqLcQ4dKDQ0774qV2UAmn7BHUkG9FNdc9QfiPRRiRkZHhmEfpp+THrEEQXOjPlVVfER9aF8Tg0q
vWcC/jV0rpqLu+kB98F19SASUm2k41UJRRbdu7TvygjTthZajuhIys1REHHhLB84XwnNX2zLEt3Q
TiO+AKs80zmHJC4PczFvstaBgq42vuv/zkRPuD84VNcRL94zzdVCXSI2EAdMTsAF4b/F5s7i6H8Z
fAlCZGo3nJJ7yZ89b4UO0D8E7X4n2dFmLRtXqji3Ex9KFPSu8LCJCvzgx6xSlgMLmEovlM/C2OEz
CTLAjOUou6JCPF++VF1kKJsDumMQ2yr7KRztVgAzimyubfQT/UufNy3Ayw9uQIW/5Xg0idA75D0V
En7B5HSNaVBezOs14xtIdCavSUoZxEoT0mt8v7BfRIz2UDCj9P/sUnfAFQe7UJvIjMnAyaJ2yiJI
trnq2wktx4kzaZHaeJrQX9nMCKyCINjedlW7aUNEw7s+xzbq4MyOwBo7tnQ6XUeL1yGMUk7uSQ5d
pYgQq/pXP34E7AueoDd1KmvcH0tGYBeSMro/WZX4xOaLJGpyqoEXrT1NmZUfbslkYpWU+3aWVakn
KyEAAWtToBttGVLibmWOVSDwH0N1jB2fKuZ6TdFLvfq8fe2WSBUdTyzKlHad4Bk/xeX4ywSdC7X7
pGgmkKVjKqqsvSoXv/C6pUPeQeYQhpJhjj5XhCXywNe8V/Lfz1eOetoRno6YK5yid/fAq8cy1Ka1
OXUoT/8oDt3LK5n6rVBB9l6hpCPKKfNc9u1jXIB5Sgg9soyT82f7IcJ5lOxmjsP9phMkTVXBIoUT
KgwnL+H6MCD/lPdPBpHKU1wv8dHzKEkLiMJYZCiPWKGx1eLtc0rrQZmpu2dZS1ANiYONENpD0tFD
NXkA0KF+hZkHIWVi2rrwO9MPjGeir0D+LRrpplP/pCF9Gk5Fa/qZR+KXa19cjz8Icw/ksv1UJETe
i2oyfk6n7wIzPhKW+URhdmFh1uS9dQZs7bTJ3UtCO0zIUcgwKkmEAw+neAu4bR4L2N5t3Iu3PxRH
8IfJF6ISyW+qjvXU5mxxZUZkd43Ib+UXcQJTpFTJ+YlPCwRw5HU7bOJofc5FiGvJsrZt+dUTJnnR
5rX4P9yQBO/0me1IC9FtOBRuQs4sMDAnSEQ9UcUErP/Iq7YykqMb0uC+Kj1KEnj39/oOSfYHTsf0
6Mq4FzemajCmeSZvXthLnVy1NiDBCpM2xRBixSg33ds0CZeFxe207+9nCB+0QOo0tBc0hf7PR59P
WGbzihR9FnnzKU5psrqa8HDYf5G4dEMZHNwYQwfLyYSaO2BTnudVNGJsCrxLnbURV/likQtFwhaj
U+p51h6sZpNq/wybWyxG3ZtyvsGdqdXcB8+jC3iKbPPC9qQPKjfOKL8+xMdeym2dlhF+hXfra0W6
0GOUmbI+xURWUHP4aj6Rn1XH1b7Rg6iLSJsrxIO2u3p+uvZa/+hvm0xFVQHZfan3DHkDlufZdOC9
v4tD32T+frV9YFAFI3EzylHjqNfyLE/xURRVBrDPL3pfZU0SrCLuCRERJwM0/ZKjIdyi+oxzcJZ6
7Vh3J6yMra/vklguZQRk9bCaABrHqwW2duEvQom190fHn4+73kESPZ95rGvxPWyLngnEgkzlJAIy
od5N4MNBKqEjFRg2PrLxuI5vw338gRI6DipGpw1vZ08/rbN5InnemcFcUMPVrF9SrB510ofiqvFP
qi9qc15sqHd/uX4rxoj/y802uc4uI5H1JWqvQ2GxSTt/mc++hC4aJL7DvWMiigyfziPKGGBV4+VV
v4YU8QrpObsm023tgrtpbZI4ZYNZgAFkF7D7Fr5tisLp8C0t1ohKYVeOnJmaeXI7w0XV+rodWOkS
7o96SSZbjEimiU2jEc5K3TB6uNStRZ4ey/49SZaP5Q2rL2N+7NfrSbSJUoeVjgCeaM8tpeNZTSfE
ZekeG4qH/utVte3QZWQe3qKpM/DqJi5aL6/1zTdgiVgEoN7b9Z8Qkq3sYNCag6Qg48i0Zzh/Zgco
V2GKi5o8eND1s6H/HhkFhONsLlMiHpMRI1fNMO73lyVkD3KLplhdAxS9JWMpRbSMbWuYeb9defGn
hEu+oQp9yQO3og7FDE+MsvCv/sK+CBXP6Nem816WWc9H5fT+HSXsGBYEQYamsmXBv2c/8A4kFFFp
cwCENmoWdeL6YlO9IcRU6XCpEasiEjSLPhjz0gHdDt5W9nGHWoB0Gceo8aG9wFKIlWBuTUPpq11X
E9nGkzGBlfN8de9lf21sYyAHOsEw++LoUYpuUzdHwkcKBWI2sxRMs1DWizlbS7cY1uYUZWSrdw6f
QVA+OAnym+LL0F+q6p/Wy29lhgGGB5625rUyengieb+hxQVXhB/MGIyId6WNYrUshPNnI2EHpppX
29kLUGTHdsmbbYRuLeL0MvaAx3vXyzeNChRDcQkeNghTPfdGV8czGbtwH6PtCRaTP/lAlraVez4s
pwup8kifVmfl2QCajEoigH8VLlwL1a+SyvsItcven2M+Z1M5DsobgmwCZ5vc5ocUQNO6vw37bDrW
vyz67biR5Kc1pBKU+WubLMSxW7djEW46TMxa2FDOyGB7Yy5RY4bSnQ4n74F6TDdIPjJBgh3+ZcZz
9PZ7DERVKLSQhItbYjhHm2EVRvR9s7qAqeNcq4K/9qUcZ0a/PZYv17mTJLnE3RU5Uv1F1x2HMqZL
oZNZSsKN3sWbAmM2LuI9XBE8IzdbCBnz6JZGFW28zLHU28SZNcwFP+WJe2TWv5uFasnjuNTm39qj
bDTBxRGezMZGqL3QT+YnE40/DxahKpUb95lUIsF6AKsS/ptHc2bSw/Jv/AzxoNAnKYbsmFJVvaZP
W3k5or9u9pZg6V01z5Puztpl8vp1KkIRr6vDYKqXzudLcM29XLHXQXcC2TLDsyYm/A082fCXdUi0
9yJzSmMXaGG5tCk6iTEXj6vz/xi/2lK3Ay1WTwSHBFQ2Mwt0TNpxdSa/9+pS3YsPkpPBWXthu/8J
nXp5ucTb8I+H2Q+rabTCRTW/AcZss5swjQ35EvBXU3R6Xk1ZHWxTptgnKpgeW2ruiuQ4UD/QqPGd
7KGLWl3XZr6FnAROw0XOe6C2BlsM8aGp+Xjt4TomTdAzg6EaVQfh0V/BWpPE6vA9dNYvi6fQ+4YT
9rmL6CggE6RiagYrgzGRP7ay2VeMBXoGH7r/Yzsg/vA27n8YH13VXg7EBHFFppREoelNpXFD4zjN
PI0M2ov0py4wHtoRT3oXQ7EprzJ7i3sC71INRxhhSfENDIqeHaR6xxxEiWQo9kZ0BuJQiNT64y5i
fx6Syq2RS5+6wDVVqgSfeEJkUYSxA/Vz+WBJFRHqTfxfpuqvD2N0UHiRovPN0iDII9wouvgxkQu1
7j8hqdNjmIALmRU+NNAyoDRW9G0irvoJyEuk5tcZzlz5Z6imeMbeVs0BjoDdaWU8eaha49HCYq9b
YCexYtMcf7DbZC+sO7+tDeMJgPDxN5p8wpyN3LAYmXKA/8G1Q3p0GPTNyKXMGGl4SGIfWdJudNv0
v70D+JM8URiuu0cXcihjkggGHfzmlxS047AXUktcgufIG9UXFjfiQLlaPATIRsHO/bIIrZoTXsnd
OVZf3pcUZ4hgjCX3QMSmpJQQXkmqupMgvMUEw4BGgXE5vTU9flyna6MYp8+YGVm2c+t/cKqS7dQl
avjDgv1eQZBfxdASOy4lQPfsonTnWkI4Jufp6Yxnu1WXk/eveMNkt3QZM5FRR/dogtFLq6lXSqDe
m0DeNRVOgR5dO6aYXC5mt7jvzcJOyw4GnLXN+BfqkubJYiUNACIXQx5yZHxmHrL4otf3B9lE1KQf
Tv5xugyKrzFIIH10uOZToWCPSJ/7ZNDQYUzw9vYxXU7h+/qLEgoylXhoqNe7iCWUuC+WCKD7qdM8
rKztcJN5ZCFhFaJzDwZaAyugjxkotaQKUbDrpk9XsezcBqXo3mhs6F9oS3vxNN5QN4Cc5/TPBJno
zLZrPs9pW7MLxsTbCI6XhXf1piqizdbXQclRm4ZnC/5gHeG4jxLH2o1+CjaEdjDFz3MY728CxBDx
BlJHjeLF23mZPqyi7Ecc3rOFnEwdzzbFni8XXBDswyEPeyAvtfBrqZccReAXN7kNe1ljqU/H1kpy
DF7/qZYXUEIZpEoqo6DFkjEz8psthwPH67D0jQu5HlRc6myaeZ0epG97CzUuzRKy8aqjW544h9Zu
0yw4B0cLXC3+DB5c5jPR19Ix1NeSIoymbRmq5a+61lM85oZ7+l18yt9E4ZarQTlM8lrcBPyF3v3m
uHQwp+gPEHwSBUlutkRaX1P66blJxF0EHo78DPqMLjL9TrR89gSSPOCwp7+QQBHtgOzGYUDGxPQp
zk7VKQUMOSyarIYZJAru253mR+GDUHwvfKIs6UQ1m1ohV0CeC06bbhGBKRll7l5X2r4+7s6Prb/x
PYzmRgvVdMx3qU4O1OpF7xU1o26FEjLbRufYYRoTCqxo6Ohb8Uw1mfRpmueFV9W6RDnIi4pqUl8K
BFNPNPerj0nSPrEEHO0qXqE3/XF4Bcoav4/hl9QWsUV+sb+HlRin7FjXcKD0zH7vQA7gPwuzlvMT
iObmKWY3ZSyBkbRX32pbd7Uq+H+5OYMCIRMlzFCmcYmSSpA8gzyPuLCV5kPa0/Z0olnGFyZQusO4
7VHqT6W/Edc/C2HjRYW8mYBC3FPRpiCIcTa7o/oZYVdGDBKEdVb0Vj6P1RJwRykQ4ZMhYzD9aPHk
xQcRaf606NiWPEe71+r8WJ2WWQidPezR8P+jzqrMMEmm5cxgsT/R7lD8SrDyG1qbW4pTVhzjBrri
Jyy4JaGLkv2Eo5KbvvE1vq0SJkObEY4nMsfZH64cUgGRBkghceooq92Qw/Ny9I2PVuFDUU+zuMgT
y3w9QLRcLWHg9JME9F8yYA/qqnt57rbsYiS9s6xRwMQKYNX6h4P2g81ncchfe0mOyFh78glvRcvO
DMcm7KRE1yq0Vxspam+QhQ7WuWg0H7ZU/LTmeyt5TJvDRz6cUROy3Ifbw5IPJOZrLMkUNEZ1zioj
Ahr9kbS/R91lfGkflhSq7xOTEmcxpCrAd7dWYwjxYFCumkcRMVCr5iTBnYSq8AbVaUAq2JnMDPKW
H2QvYpeyuaUKWKQUtMzmM906KWBiKil2/RjdfrxXWCrdPmq+uKx3lUIeZzOeqo7ZvNGv5crOi1AF
QwPvXJUTOMtjGnOD7aOKHnCi/0375mHKHSxW7+TlLZDrWmduwXlj0++eUjN8LFjkV0TRjY6i/Uqz
/HPNBWT/5g4NjaFC9rAQWtOC2ZuFAhuYjfXQiU8qwjiYL8WSDTfNTGTSGF+lKoo+CXkZgz91YlBh
bd7xdJMLvZ2MZZHRXvMz4spMXUTujk7jOQLeT9EocFIDOyi9ms2wDJ/cboltWOh63q4uAh3LTLNj
OLii97JLTUaXHENXOaZCoBO6PgdLxJjKSpAyJSaI5UQn5J2V0iULdAKIVIhcd4nzjhzYqpcyxmWZ
t/mcVuzF7nsTbVo7E3mi3Jm0v0ldvnWHCvyZwC+dURAFeDKmt3l5sEgwuEAgdqr3ND5Xc/1SWwKa
v/woJzZciNJydD7xz2AFuysUGgkSmSbdnElI2/mBZXMtIH6PUIJIYjQBjegM3SFZTliuQ0iL/DMc
vgDA0N94WmPj5iUYLcqtAYFWCoxYcAid8rwk7w5NYmv0AAh0Z2xvQQWrzp4od7W1twj0WFAFS7uo
FNlsjvKF2vJIt0akt/WvYyDnm9oFCxB2tUzvRJ8g90dWeWC6VI52Ogo6NuA/A9e+IDZjcLSu5sUe
NZG52aoXDTSqnkrK1ytdXb/w200Fqc3WodpYDst3KjBEw+Qdy/4Bs2L4IGsJ2bwUjnaCWNTQZyXX
UfJrLR6fI5JHvhiuhIWNz7U6/lh6SAARwSR/voxMfpsLrXh7cfnVi54nEi+Si2IgnIHGztWcvPfx
xfrrdHZLK+qWPkeMlIInP1fs1yta8VgOTKxg2YN5eH55Rf60PBEYRfAncdYnDHxx5yIAvlHoyzZo
lvYof905cboO9jKWUU+K5df28En615nzATsH2P52lsfCSelHblLBIvrSZI0R8BTup8HhZthceRbL
AYPWLArcbzruxpmrvPNwZCwYetmyf65RZiCEKbwMPEbvpGyKwbI6fjUP3mOJWExGBCAvcOd3m+Wm
QWusy6AL5ZXGtX1/Wp+rD8nDnFxMDwptd3O01cef8YESfGIwjC9FINptr3Lm1U05CfZn4/udSO3m
o4VLm0VbgaiggSqjHb7BN302axy/uJib19iqNYmmgDuus++FlqWHdDFZMGVfav5BHebckIElWEp+
8ZB4nfMRKlBbp7xXy7T6BtPd9j5XPACuXoOA3vXcnFxTWod1eq3AXAR8cxmqDg/2Me8lWtVm20ms
fXdCSdM7DAbPp3tx28LVEJA7Fw6wMqiGMAm0LDeI8hckosuB63rqbcNlCk0sKYUjf5zh2trzVi76
6qzDbC9YbXfb6vydU0gdBQ2AalCDlodBtI6z0c41wAecE3A/h23y/+jfDI6huMPBtVy/dj8e58b7
/Bt5dQoFgQNF7gnFS2uhuLJ/U9qjkbkQ2F8OqnNf4CgqvxucaLLPtm+8BA3c9FAe1/BoaNnw2jBO
UAieRKyAX2JDo/+X+8tVvEbb9Hnsz7bmSnQi1M+yjGvUtbIH+S2vBReyBc7A5SAfucM34UvI/2oF
SxrJ9KPeu0mo/QWu/DOoLo+fAf8+K7mlFY2St4kZPwM3shqy+znpN3USLkbdOpD2A69N6w1qcB01
zZ0wgHA8wXLXDzABWcBDY3tplV47wUHiyvaRmBxsr0nA0IRf2BYOkSbGJ9e4vBP5oI3Q7B2EeMzR
1SmMJBlnv8mR1ImXLxsjk+iSnTNh0BMd+IPYBNUjmgCU+FVK3cOmbYHh9JBhsBq6HZNUWosUjzxt
HGJF7axx1la1E91UVpaJZWkHTJFyqhbwkU5/NFCdMJ7V9goznULUb/rBOPCv34R+i0+u4+XGru7A
G+7VQiP5KHYiggDRxdif2UXfWkpTC0jNwp9NZBp8RntmAM4gqg2fXPCWQyZ0WeYsY2ieWJaYtxta
4s0aBMYEbfajofZ/FTErnp0BHZiugCEy4O+MneldY1E2oAwVcDEhAULO321t8H50SViMStAYghid
aLYhiwjkg448SxxTTQKdyUMgzwnI0G/5k3f88NY0ESA4COLTTHxKHuGWrWqCCM5zn3OBEoCroU9o
A65bIMkn/GtaCXhF8nv/d766uPw/WS1TNGOO8BrgpIiWPYiL8LqI97qKJ+PQQZPUzAFXYja30VI6
uSkZdHt1JWyznHFvmHPjzxILGlZMphibnDpsG/9Gxl9mfHbLBgbwkVE83U6aztzKd8sN80U3qa61
JeYH7Mm2TxcZN8yAXyjF+yJtRXxV1uWPr41MV2+hANzu6W1LcPEtnxbtCuXtyEQ3Fl0VSmq9jAKl
coub1g/1SeEb384AT0HYWb5fYa+1gcoWD1jGLQGKh2DH3KaNijZGKsj8r44p63O6PwAgurtt2zB3
mhTfvRHqnXkYCOHZ7pe91bbncgvki5UEDg1xi/ffwYYF7Qp/ICkU53zs/VxhsB6d8hzRfBQS/Zmv
D0tcn9jSpxLICyGCGyW8QuPO0T5URQV6TIpKqUtyBvlybvOLJ3lcQN9LJLaGKp+41jdIU0NsabnJ
UoOvpB/qqOZ9Vcmj4yzJ0s0EQSFtGsKYpPnwz3ZIV3fIwIfyvCY6Pvs+74VPTri2/EMdsCaVik3u
HbQ5N4EE6xxIkXECoOgteX1qyeOiSlIBHuLQy/SHN7LRhEaUV+U+6usTiUG9RIVcQiMbuPFwxN4T
B2aKBnmTVZo/xXsgJ+vmX/6Dxy0SaGZIi2Urkj+P6B4tNsOxfkCPfGjjTwn48/kUm78UABMxWT3K
gvuDTqHuZtsmz+4wN/MuFIp4Y/nTV8ss1b/zWrnSge8UYXGlZt0yHVjTbaZYyJSQZ7vsBBXbNImC
lnAfrNqWgB3pCwEpShzYCuVjGOj59ro6R4/bEnBcypbPR9zNHGOAu/e2LIQL1/gAgHX+ftDek/EO
p73byY405gsXFaIYsdGQkMgO8Mqa0jK/pQDcM0az0NT9ZP4bi6I3sNM7+vCnGGInMiuBooDu+8JJ
CHhVCQRYdR/B5SF7W8IBsNNGITxFUgxzGL/WAugL0vBUepvXcCezBzCv8fcLwf3EKjI8r6RHrPvk
AOfnMyJ97CmIZL4x69fO5ICzzB7egnJv7+FHFrl9p4StuLXYMbBEaky+8oseLe6le/k2Ho4ohuTi
O42DUwGUS5fOmxWUvu0totPVZjC4lLxHHo+eZsRZRnRMqEtrVnW1bz1MAWwCe/B90+puT8dYLJNc
COIdvypPMHzan1VqBxchtR7exj+CTkLg7tZZAHU9hdnaEgjRQMzAC9VCAl+QhzGAnyj17t83iz5R
JY1udenja2Z9WshBJ6GYUR74dU04EaxjqDg0m/oz33nIaLFjAH411ynVRML7vPV8tq2CX2dHH6An
7olbI+mIXMT09UJ6vcOJqXG7Ln8sVxBYD67nOL6PPrNjBUDoFlvl4ehAmSUquwfrDrjztC4/xVWv
y0hvtuAlFVOZA4SgJHzA1K7jolhFZBc5eANZFmY30DT1OQ72TUrAnUqvLZSM9LKPwOFefjBbcT9Q
LwpfI3L6hE5B/rDskfK43jjGQLGY/gQayFTfbZGg2uKhJ7lxpeEWB5505GKfSispBGj+CHpG8B30
rRxb13lxai9d5OCCD6uc+VTh5JRk5hFVZlfYkNTXz0CXovhbZrxzWAncRM7yxpbR/o7+d3cP6iL5
MB8rhC0C56V4K4dGl3/NdQaLp5isj+tj6KRqAw9FWNYFreTw7KCBmXyNkRsHmODzxOXxpq6YJE71
XLDfRy9wUbw+g1VpP3mcBSeV8A0mx5TUzXIXx1yG6X9N6Ir+jzzwWxA3PFasI6+lQd6Mvs1YNbb/
T/mdrCW9yLGxDpcpsQENQsYO4p5vCDAv+JDQjQztfgQTpSWicVCVYBm+GOROfFNYy9f65jNfin0W
+SPXjeC9pktegecdWDIGIL7OuCEOPpAdStz0fL+vdgFOjdfVr+y/65+QO6mxdpnxsTrNiUlW22Ti
6VhPpeKXEt18hR8BpwYwMnd7PxtOeIxPqdFxXgk6uH0xbmcqnfQ07VgdiwGdcn2Q+YJD9gBjZo1l
RJhiX+9sx/okF1CLGxnLC3DWlPwYLZYLOgfeOc5Eqv+Y1+l2yNv5033xI0FUKL75NraUVce4gYG4
9+lpDVqzhDOifH4oZt4O1t6U/TR+yIqoNMbZBb4vv5/bfxeK8CzdxgKYnSDEgGFH5dXZ2qJNVWnP
t6atx7BdHFoQstCn3IM1Qzx5xZ52tqch01gkVN5SvP7BTr6HXBabooumd/WMZ7sV4EezoMxxYIq9
pbUMXoiDREqbfG5CsnbS64fli6UKTm3s5z3ivj2VZKMgicVhY3K3+NczeDK6TIoDSOCJXpd+f24M
UAGanpQdS7WH5a8R4aKKtfdLiS3kc32Pmkh5Tnl90VMzDqw4CiHs1q1bkXcXdxCah7EcU8mZmsd2
6Ou9FsQLIMJplrBAl+wyKGSgbJUX/wqZgPyOwKtDxpcgmQUga4SUUW3A7LeeFmh9/jUUik/w1fg5
Qe+aaRLCHdC5UQW5FgS1sumRjusk0XK6moMTSZsFQAxmmSO/wr+DBL3WhzW+ls//q5DVFIqQWG3w
B32eO5Ie2W8u6Eu9Yp1Z9Ql9+DbojehqDfGtcneN6B0s3cTjpb2bcFzhqTCcPuZXsLIUipFcgKOr
CbHcPqRjhLO3VRAzOTVyAWp9MA2+xcl38J3ofRrj/balgszy0yg0ywjIUeKJIITK62LfgrizYqAL
JAox/SkQNBMllO3SetlBXMDo/+r6u3e5r+bFDogl7eN4hc5PWfhzdzg9Yui7qD8guSa/PadVOFKc
cxrzP9EfdkIu6pP1hXW2qcsdwBTIkk2Nok5RoJ2FmEWLAKMHm/3NPkQQeWwwWr75UaHG/sDwjPv3
6AbAv5fmvPys17BDd9uDnuiMd8gechR8vG3pcXHTF1MhYHMa/fN9rXnqSg2hzzoDxjWXUo7BZtyg
3jbi06JCdIUQkfzaITVwPpBDRSeD8PchDIUfXU4iRyUlWogQjyvVPSsywEm5Tr10iRHeSberw2GX
0WPcovs5JnrXD7Jl15S3bnouNgc4ujw4aEkNzkh36cr/270tN+Gl4JFdc7v/JZtfyr4z63BtHwpZ
hVrNPdriEwMfGaWkjXLA4Z1q2P+rvFdmdJB4eKNxQSwe8A1NAoJZdA7wYTbWPE7zcenlXdwz5PNx
nmSTJ6kqtFmcWvcKFhnFsuOj3XgQym2Z8qpVB8FoA5ozh8neAaBi7leWCrN9k04K/v/T8QMhGRWi
zyiy7OntAF2S2SdLHPHChdLeZYZfs6xJsa5Yp0+Lh7mw8sQmkXNEW4steimAHZG4QDTXBHVm7E6n
Zg6bfX84mZBqM4YoTk+nZJvY0sl2tOTddepsSLOEfdjKFKgF5uRl58mzT3tQedogk/iygjIqerui
/nIUvVuKHbs/+UoLSLv9/T77JwRHSWOIcEeudE5AQ+LmQqIKTdfheaAMek2iRynJuA4rfRjb9QqO
J7ni0Hdt1dad5VoOql4W6EzZp9sTXIB1BWUbciNv1a5n4NEOcGrhgH0MLXeyxqb+jnCK9/cgH1Ua
3M7P0A8S/tHqhNVXXjvYknpwB5wrq9O3PYr+AuwVVYw5NmoxcucHyjDRmb43IGlh6IpRZeJYlJKm
jVxsZZctj1qzNvt77Kae+e5GIARhIL9LXzTzaxhaDfh56hEZ6gfMYlTmM60b4ICC2zrmCDGMxRfJ
RU5a/1KzgwenUIwLCU4rvfJYNwS3VpynsVij7Y2bzejLBP9i17veylTdesJu/N1xd7UkYZjildee
W+WuUYrXMygpTUtekKRsZKRwin5WdhRda4C+k7yVZmfifcl2Kyzc8Jq97LOeAEzZ4A5PBjE4rAI8
V9xWyoISTStX+LQPaMS0euFnD+F0z957yep/FjoP9XhAUk9WbA8dmYoEKoTIMwT9yOJUzxN7eQWf
JqxYaUG0ZuYDpG/jF2AniZKHc8+UFIi1eSEm1g5tFslANBstNANzRZkZ9Y4+XzUc4+NHCuNPCK2v
tf7/w4JDMCVd3K6Z2iyh+ioWWSGK+iYQrMsXt8yDjRCx64XjxAIvurh4PEuvlhb3MaykkAOkSGeI
GDgmI+Kz5zrjbibo29L807lJ6TnpSKvKqLeYZ5Gd488kOkq0itVugNOIiMYnBGpGqNWz5tPHG94x
eUPusIvIlKHeZkdibYpDOsRElC7f+DvsPosO1OEmPUena0SwvMr+DjRnOOGC3VnRxC2C8p/rjNQb
Cfh0Qh9LuhwxOdl2tbb1sU2K57bK5mcxDhWvaX8FZx+EfX78vfa+UJmii80R6DGKBk1lmEEvVqHw
AJ3kOOecMNh8lV1Zxb6vqLFiRBrUJYkAAn4L8Xo7bzosgvd2xu6A6WvgbxouHBJNUwn256H+ovw3
hYYWcNINYG5hBrD3VUxKzLILtpQL24br1Vmrdp74fwhW3aqwGNQOxODt2mPLeXib12Kk7boC2E7G
oP0bYc5HTqfWuCOj/jW4CslVPKmDIO5GHkdisOtUNQA7W9o5cy6v/hnETYldHn9g38sxYPAD7YId
Uz+EQD4VekPvZvS8oIpFm+zC/FYxt1fpJW/HKyb5I8DkRuCfkRAmxgIZPiT4c/HR15qX5uzhytRy
+vbD3t3qu6YJl8xVRQC/l61ngfgpKLBADQlMFGo1znNGmD++jun8TMZE0OzH3N0WSqeX+wlu3fik
UZHVTQym2XGt9ugKGwIBGcxMTwfI6WBSlg5+UqwCw3W8upF0bx+abUmYuOdtYk6bXc7DoqLc99yw
aXhlJEGnc25rTEn7G76xoWm0gRJVluAlQ7Ob1e2mVboBHtoccMbiHIK8idMMb7QLg4GTCDLMboWB
cn/0E5Vo99LywxDKX3VVBNXDbCRyLY8xe1LbM+VxpS0eYBAGdFSkSQCqXXnVWYC4TwAIV/Lepg+q
83zvJSAFpk1854U83A04sjZEJ5Be3au/nknkMFC3xNbraR4ABvf0h0zACZe84KkRFaXCUrd2GAFH
04IZHdKrj6xwOCgYPMbw3h6ZLSvNLvUiBPtwRJLYFv3qs0/0bSf7k2Sify3l/xfkuKtquACYxN7t
y13MDJrvlqQMbQdb7jpyqqUpFx1+Y2ObpRHVjlAAJTEZ227EettLtgtHundbAynd9HZijH/XviwE
VbwuRZ1g1ifS3PHVNYDYoPJ7eb8tBfNLponWjHNSWNtoJ2KYW0/AkVd6an2RjrpJQE1ymzMaK22I
kz4WEDDQjV+EGjZbcCurNJut+xacQ/qcWGBFjWPPR8YBjnMu0+nEEhRc1nJy0mzXvzWm/8FR3TjO
CKffvhq7g+MkX5y1GsdwG4sSa8AOIcxcJ68fEUUdo2rlZFfefj2IH1+fUfTgYeUxo71wHY2QrF1y
h/bkI++2qKAXOA0pdQQDNeAvxT0Vz+4UNypJkjSKhvpq2vR6ZhX3cMUA14755oq7tSE2L1OT/sC3
dTToOvuKyZIz7/Jnlo4qNtdI7Gq/yJ1Z7LlrZYxQnY998hxCPqrTpr3FnipATnimOvtQPHT7IeL3
FcIAHPMX/4a5+zSWlLGRRTF+j8wYVMnDhy9xb6wTEbrfL7pmiCwlMIS+suVSkHcF2NpLhbRg60qw
d0QDO1kd6WvPtoU3uFkjVrVETnhAJhdTYoGPjySFhCYaApTyU/xJny/dhn9ok49U0+rfQluSVe4Q
QT8nEStW/Bhd+zmOvsKDD1ORMA9m+aqLMEGbpIliV0hmAfKmoabDjn0OAhjUw+0aG89KZoMALbUp
XUQAuDcmQiK3qVtjl0fj0F7eTFiXbCwqTtOab6eEnEgDJfRsgWKc0/+AszEtD0P2P3p5cv8LdCZx
8D0/ZCzuBnB9fb0/vSNhtX6nKExEgnc4OXmgXo+op4R6bFrbB2MyYL80hi+EP6nne9Ar552PhTh2
VT1FZ6Rqw6auq9BHuz9ZeIpqZc4a1GcrnkFZTF1nXx5/1K1Ly0RYF2hfSiF5Zd+r2mh7ujrtrcVW
1hwDUNIqt/XShMP0CBABP58Hd6mhrQK/TOsbgoubm3zk1te/TNQLbh3YrwJu8rv9MvvPtmE8FiKH
UGTOL419z3rvyzesnfVXumExNMXyw/ePmy/oPrAuP6pDin13AgxwmbWmLD2BhOEv2vQnKU+2FHf6
A0dLw/dpuWesMLFUrSE139jh4PuJFCUK+gzXeKxdMO1Rx4SLohyW+dg2quuobWfmT/AZWM4y4u6n
di/UVmLXMCwDjJnQMiB72os8/NK4D7WZ2drQvlhbmRu1HqaKhIXz/mP+QlGq79B3fTCoWC+swtnz
U5L5LzCMNS5vr9GIbY/HytveGuR6ouclgElKgARJWKwtQiSyf7AdbXhEgfIiUCiKdf/b/sLXRFkm
i/Nat8s56nMbY6wWLocf3BOADWOy2cZRbchY5YSTgNPobW4lw02zDAgJ+plL7fwIOao9fudU6yx0
vTSBJ0Zx5z4CtRypHkJYBDF+0ilZ3JYq3PFZbq6EA97g0zSbKzVdjQegGMIBKgrJiSvvtIZjhcQd
C7d1S6pe6fct64H7WtWy8TpOY1ZPWwHPT/ydd4a/q9YsVEPwT2/ZQ7sKEXqSzyZWrzEyQKhOwwnp
UhJiKANmhg7V1WP28GT5qYhQiJzxPbHJsmsgT9XyMNO6XXfRs35CsiDUTI3HQl7eNi0LHpf4czhQ
c7k09WwIBBolq6qYvxu9GrgwCV2KEbkh8jLLJzMxA9goOa0eFKBdtU4RytFGOv3galcRi4d/SWHQ
PMiv6dTTTq0drS1P6Fp6Uwa8HUUo5OmnVNZckahzs3Byzy3cnlme3GSJR15mDdmc+eVAT2ayjJiv
lx1qcxfgyjgSf9RjWC6sserQgjG2TY1s83SQ+tVxGcbGXCkLIZXDSvf2MPtmyHYJ3IcjTmiscvOy
jBmcYmBCCO8L4pPNHnVeCMKHjoteTBEdRpDCebKEYx+Yt6nthL/qKLSyEFlTsCEyNGVg6KP2LQVH
O+ZYeHAp9DIHDuHN4ygkGW9172dz7dbqyo73wPLIh4tqs2n0jy0YFgYQ80Jz0ac1ETrvBfMZPmjq
/S4Pm8DGgsP4Ow7hR/jhqmzwVQ8PfRJeDKDN3Tt8Dp1HfqM1Qt1Zv00nSqWG8wvQN9YbyI7byZR9
pCF976qzcoyXj3aVe8Q0/SWeCh4aDMq5w1ByL57lsng2aYlCUVnA79VfHDCXeFEo/fBRGcTKvpiq
0ihUCW+4PdIYx9Y/NVT1AsWTc8uNHq2tFJHXSRKIRt/DJihrgnhiLcxx769fYVS02k9riMClc5f8
2/4orbqpKyRt7A3/5lB/fjJxfVxZQtha2qMSNvMDBkSJ7UGVc7LOPvhRi7noFJo7tdakeXQM4hA1
Bs2sHoP+BMevk5Clo/db5mOk6ZBEGqy2iBAGP+P6JLB4gWY6CFWwWvGRNNNIKjz1MFaUCfaqEWyp
exJJbwsat/b0YJ6MqfVZr9nHiRgkjWuc8VfKEv/+FvCY1eL2KV+FYBoVStc9dgbJ2gZkqRcx4r+B
4dAV2golNnHrDrUuRYflFEsNP4Lmv72+pIWnbJDcaRi8BtWrzi6oltnQ/kXeftcFHC18GbqTvPEB
C3ZoD/DUWgSYu1FCb5GjpItXsh/EOjCls0fUNnjaX9oEFmBh2pePWjAO/6TwlwfLGI1JFybwE6Bi
tRrhMLiMxLMDE44e4OYiqOxNssY0az2B0SKzK4mx9q7Ms+/jkYPYv2XRfo3CBtjT1bD0b4jGXGV1
e1F1BDVrmNIdBb1IeK6+T0VlUgmjsRclvNo/fIhsUwdEvivjes3fyqWh59JBXTfp4cpOL/vox2BP
xHndo/LB57bjnv/P107CM5AC9gJ2X/Abw/5gCPP0kLYSbXvCnxMSIi6tSygTVxW9yfw7fLB+uIeY
JNC76jtsP/Tj5+93wCqp3DCTt53PYGuH+qgZsR40b9NgL9N4N8dLALjUpz9kOgbuNbqapTKtwNkj
Id/egu5Z45VKnPK74wGO+t9Z5NeaCz4PJJeU63Vdy51kQ0ZrMUwyAFESpGzKFESJgRDrssBM19ZD
nvh+25zVXmzOYhC1753VLyGQV/Rs6LOGtWjzKnQUlTKQ0fiAXkg5aIJyFRoHloA724GNHtyJxB57
j+8FPJhGMVlKH0fBHTyIgKJUY+C7DvzWJOnZzb/6I+AYyYFV5Wj/3jNDAJvsmg6h2imji6RASgjG
/+RFl5/rvFCOzHLwAkEL4k8sksMsOGgnJ9PrkNrXB3bzSKnnWppWgkJgSkLqspcaG9eluFTrTqJk
5coKRv8D/RTcP32xXs83CQ3/9QC5BScHRd+NaPaWI+JN4195nUIdYG05YXbF9BsZwSqnZIZSe1YN
btSshAnWEpmzln1f73cGeElVajbiQ7YDTz+KwmklM+YzgV0ceXO/OprAB1dv5IEssp/0juWUsFa4
fn9Ftpq+nJI9qhm1RAxQV7OqSMrfyUAhFgjIw9PNxbtz3LvJb90d1tAzQAbdozDjLPDjlD037d4C
ZimRZb3XuZU9Jp862rWLrWXXubhIWYchxYJ/Q/CEKNRKMEvJZUg/AFX76XZnXr2JjO1BPPrjfsXB
tQ/mn7vu5hjW7LYX5RcF/He3exSHSSF1Eo/Qc6n6AtOexGnv42xHwCx7BE84rat3kJmju1seZJTu
+tpic64w+a7sgSzdccMpUEsA981/20Q6wDqNXGZGOT8DbBAt//l621EQ6Ae0KaD9gDJIqoDs28M7
Rdp5wbNSialJ3TG1fwVSukaelnE4S/YQCGbH3JtirUIuaKww0k+BhB1YPYeUjno9JNtky2GncPMH
EqlBj2aVXlWns2olHTU+wRzpEokj0oNTQZ8QDscrPrCTYpKeNCJP/byfCLJNAhHF/JsWBLCtJO6M
wWWpDMLkPTuXq9BzG+VvtflHaBxci2135593zt6X2i+CRVbYPH9bypwCRenVZC4TYf+OEWUlfn4A
Bz6N0WHmziIFu08DuXLVz8Lm9NA8aXwa6tugWYMJ3vmH1h1kdfRqMAGzzzRLa6xXWt7Vk9ZaqSWU
kmsQ89gl1bvKDqzv6Rqncja3/FmxOOPJcEeA4kSmyLZ8UFiDDc/apSgdpjIZR7G0qFUiIi0X4tst
TmBE9yL0Rbwx9WumO5YISse4q8QVjkD7DbfWUMd01An3A+6rjuQg75XReZ8WSfSOT1h/tKuaSf7o
8u1PObmMb81bYuceuGCV7M9oDmDrqF7sCci8oBXKcQbzjoAehpPvQQaiZU8Uv2Dya4vlz90D5plX
87ZqDPP9zounC97RB83AqzWEx7r8NdBN3r2NDAgFI0DYm8dbQn16Dfr0lFVnx3VT26dBuwRdx6P8
svaVVpTg7mfVcaWi3FaFzLSI4dT5Muf9Wx0g3HXw3QThJWe65XtGnSGP6sMW2s7OfZVwjWFLI77+
Op74HIEkffSqFR/W3Tn4p2suaS5/XNNoKsth8RxHe/66AXTIPXgp1n7GrYD+SvB42YALD6a76ice
YpopwFknrQmGSGDmeFDB9GAs5aJZqxbr3Br9JmjbWEFrWV6ytMnpauZBaqeFJYUgv6S6tdHrPOkw
afFvuDoe4sZdu9tMkf6Qy0AiWzkVeYIhLj1H0DPzRv2mYvqCa6d5Jq8B8puYLx6VizVolzLPhk+W
TA0qtBmTfHzRNLbID3hrYV7yik5QeECQssNTI24fktXNHYNfZDAhvFGsFg4UML9aUiI3n/FVqDxp
LPVNDa8rGdV3l634r5YwxiIxhVSeWn6JmcbQvMUrITQco9/IN0bMWStBSqbWB0LuizwlScGrb25U
J26jWfFjJR+K0ahtY8EkCDhkMC/Cb41iPLG+LkczcmUWZ6K3l4eUwkleDI65hWkkwlz9PKgK0FU0
8++AiFIOBxP+z3wEnzd5bml1F8PZQPMBoRQKDyxXkOdAHW/kkZDWvqJiqfftIH0jl4u2zAa7HP4y
8X8mhXG28BY6ooyF7Q5cPp9MV5RdSKRvxtoDnl2btTdA97AkGoL4p3TkJISDN5d4ff8g/c98PmY4
iBONXaMrLLL0O4ubqKSgdwWd0WrCs2QhuPxo8bj9Y73uy1pOCSVGB69HeN1LCb0d3i98cTcGAMoO
20wxWurJSKaQq5jA5gRnclJCBwEXY118m1I//BCLoBzhtXOKz1DbC6+9wZnk7B9itLT6vN76QUxJ
IOfQex+6EfpYTI5mIjiBO6+0eAM3EYixfGsxv1ZY++MuncIfqC+JwuD9PN5pd8EzJleEh2oDcGx0
ODIPLfMn7DYxneVP+SpNTwFH3XT468kN+RnrVVs6isIiaq4H6Uxqkd/kUvB1XOgipxOsn+qu855n
x+/875GvlDpuveihya1YX9rf8Pic8AGp3LALS4xxspVA6d9+YAW4bmJKgkM8qOu4QTqqP+aBVJcZ
8jAkS7LsXryauXlbfTzK3Di85jROhx+OlmNqrs8dljOm6RIerAiHEXk/Q59g89uuoattoIgPl434
FVq/4WtoftJxfohfBNvtN50QCa9/kiTaeg2b1QQjzbaVLzgwK3WDGTaAoevp4F4wdEoHs9B5CbKO
fIvALUryO8sWvH9d/H3uTtmcmqYN4Sfk7ciH0Fcox8cY/EeBThcyEaPC0g19bDzf3sN+VihGu8iW
MfS4opWYONbTp5x5Fm3L6Ddh5TDRTuCfkaCzB3oL4e9jyJeqG44Tc1YmIEq2TSLvxIrXTSvNCRp7
Da+sf6H5XxNj9Ud7SVXT34XGFyskhIBhh5TUNGAe8hqOFNmqzDMXHrSut8ghGCsbHzfiOa5SRWgE
yQ41uh9GiyIzyvgsliaFX8BtZnNTTb68zuY3j+AQaLzXzhdhpZf3dYUcA/LJ8AUdmWBz2KEPm9me
iDfvvhYupEnLOxWGhGi3y3GtIIKsGG7M31xUoAEi88g2Jlpo2xnn9b7iee368Wa8i7nqga95K1UC
+9AjhPfidvgBN9jgVwxXMM3ziO+GubbHG9g9lz0/uw/+ts//9jQwSD6zHxhKGrY5e7u3uZrSuYwV
sd1hQDXCuSqmWurrD2oqGHpE+JGuG829WUgvHLJAs/Pv+HhwkwQ52SgVCpUbdQ8zz6o8Y+EK2X+4
2mrXJXpcz2EI9BxawG8epAPaYh2/2iHEnq1fHkx1ty4ytC6iPC3MLx+Z/5N+I+vZLQkpdZWjjPIB
24prBtpll76glntVVdC1fHl9C0j+72AkPEmKHQQPto4n0rU+yKSlfL7sMpxH3ljoAsamZy7KAZH2
0zhgMNMT9eADmPVT+bo77WCW/QmGW1zY0iLk/lZb0/gvrodmvGkKdAiHKXjLtaxp//tY+iI4wSsq
ut8Bo2HZDORmaeZTToXdi6snZHBIrFAeX90kAvi8D39BiAvd1KKfEvsSS19jmbprIop9mNf1+h16
GrVje++ZcJKQ66V7cH1Bktp3kHYobVpqjarfRK1XAG38Va+cniiRLBhdhErCAYrCW/Mw0GFF6cbk
1OoMFkZwTbIunNAYubkjy7k9tXF6yyHx7d06g4fSouGKZyUU81qCq8bYhVBrjFv9q8eIVfK6J1bl
MLsW7xshsOFPjrqlvp1bxMGVLAGQeaYMCOobjc6kEuoF2Gd4ILc0AbgYPQXzLJTKLnpiCKcDOD/6
wHvvgEzaAcjWIsEhPG5QKiwKkAnVUprsIYeMKFfsZsshscOwmPzYwPRENaK8EF+O/cJS1B+zoD0y
O34XSY+R+gafV7lo4k3et2LzmgHEU5VwwLbHFjzA168yybYpn0ccNxbGN3SjSW1ATOQMoPghsAEE
CN9Iv/gy9ZWPccfi83NuVEnJsvOXwgmpyeYALEVJUdpVflCUErSf3I9cgcn0muWbC9tSgNJt6tzN
BHanahzy5qNT/PzwbUIembrQmOLQeH8PSrorDGWit/eFKNyooVlsPBo3GjnPLEXVtA9WCIWw7iI6
Ku8noelk9ALpQ5wMYyrlN336Wozr1yudxynJMj2SxA850wMjyW8ONwLKXAhI2I+DK7G8B2LsadIJ
exyn0LnDPO/enq54EbccEXXqjZCzM6r5Xek9RZl6OSeBYAPvTGiaWAh5cpSCJEIhTZ0sovD4Fizb
fTFBaaSzsoyfzcz/wasMjz6aUQRAWpRw41W3qkYutosl1iGtGaWLmkPF3rDibfcA7avsnvxfxwpY
KDx37xEhyTktSjy38VB3+E1YWebmvz6Dv0HauGBNp3/UocdYOM13L2mAIRm5pkGyr9+acSg9pssy
0+bm7Q+ZOUY9v+uA6XbwScM0DUmXf3oJ8XdLTfQL0wqxXaC/MaecOZPRk+BM6Q0EPod/6TTbmc6L
uj7tW1tK2eCfUILAWWXWFu9x9DWGZ5g+AQXrHPNiSWUBETVlALqJczupg6m5nVFFrS8+tqUhr6g3
yOvq0iYv0UIVRl0/syjDPWp48koZzETKrFHT59gtGO38wwXQwu6O3/+f2mdmZZt75Z/Qt2oM/CpP
f6C/mwwyeHLNhGn3MicF42toHnmF2AtLtY92nxE9XUl4ujdRYNIPZ/fS5dU3aUjtWDcbW7VvvYBw
/s59mJBrcja9cNmvtQWKeu0YIlcIF9sDln3ZM9dDV+zdo5E9Vk7vsLViYdnvdd5mImMWg2zT7+ht
fxvNR4yH7jwx14mj+4Llu5SHzNCqxHLE7EujCdbmmfMyZWntA7XWKAzaqjrJXm+EteKThFSM+KGn
IHccgGhdBlA+25k8Kq4nyXN6e4mmISCGvvaGs4kg63V+BhdOFmE8GUiIxrNRuzwsbssr+apDole5
SGLBLi6zHhOy189d48FNPZKRnsXtEvZ+nSEh17qLoy3UiKPXxvmKGGSskHhoTPH/rC35vGfMMSvQ
R7jLStXE/Gvaw2OB83jAxmGnyxjEV4rxhR24xpHJlCU5TUF0gS1MtvYWvtZPvPpxumCgO2Sl4Pmo
trv21TeFP7Eg6PbxljmSVwSQ8lSxIAYHbk5LmZ6AetUA4ZpE9rSk/Amghqi646aVRIVm4lg81niN
HQ1UJPZwZc882A/3be12xZwcrCs6LEHbfiFmlVycFTNNbBalVCmOpNTDMgg4XSExPfjgG2x8lB4m
v4iCzHuPUaHduaeHtumJQ1WxIrfqBE0bYTcjppIj+kvjzu5+ePij6B8ZSWACOCH+OjPxU3e/Bq9U
PhC8D3l81egTqcg6IxVyNk2HukVSy8R5fLNeJD+BfM/KqinQE4LPzk2mqoxiEnaM1wxNwoCLUQJ4
hRs9UxKOy+2rQLVokRu0auwhwoUrmK3mrM2I0+ReNk5eKdKQSfBjE6uP/oUCuZbYlMQjvJzOrxlA
Y8VAuJsZ9dZyVyy6UqaluypC/Ah3DJKizzafQB7j0L7dT/FDQM/IxuWvpywy963fGCF7yBo0I5v8
3j4QeRVN2Rcfl8tdoAeMl+UA83Df5k9ccVSHWEg07HmN+kdYprNuJGOgK21Zb0DtXeUKYPcuip5X
wzeZS70aTO2mjZClMq/JruSN/97kYg+8zXss6HQmY1vzKVYPqeBRXOQ37199Fn81/P5hEBpuWyqE
Bt3fsfYVD2s6Bh/0OPzCm/1i1AIdSNjNlAN0K04gSengA/bWEfQT7KddMPLrdgvkUwhLZVJgouYg
PvzdbcA4xcNRRyR5qzJQhZbzxEiF5VP/HeknOM8k/pyzsGmMC/aflg1DyEzCRfWnwnM2JYp1AXGu
mwyr8RQ6RqOpsE0bGLaAaK3Zf9tngpe3UiuMBkBCiYSnMrYl1GGLGCr6Q+hFEpLCYNF5iXy/MpzA
3S2OYqqpSG8PbCWZ/ZJ5Wgbmr9Eh/fDelNzeE2Dmfyjuy7oBkax0w85PTasEcNiGWolNUV2AGC/7
xiDCzZHY91O6kU9sVGIco3d4K6BcuvPxgnne7CHqIoCyiAX29XdRUaqGoDhpd7GbSH70FMcaROkd
tLx+7be6BOPSaSpiybnoscDyHiEoUaeRY8Ykm5WMFYV1XZZVbGDJ9MA8Pshh1TVqPRqvSTXE4fp5
RWJ2KVdAtDbOQW0OSe1gBWsIiNEoFrOebnUyq/VkQiOOSiA2dElai7WRlRrpIB81gnG7gI8Qo+A+
BDigF6/KuMgtdFWHjVSJIdOgfFo1Eog+susPa2BFWl4RP3MmYcPmxRIYWv/wLrLphubcTKVKbRVm
KNELe0FhfCRj4F4rOHO4GVP4jcUZl7J5qMGPfuRkCckakp8m79NadNzu/gnHSgxFSe/QnTqFtDZ3
TDZlBjb90MK+m8tC4hyNUG1M+1mtDYuBom2u0R7BRa6RD8Ksyv6OC61IyGdAmVbLKNer78rcSLaX
onmK5l0WL2BZdvzZ1sKZAkqCLDn1QwqNSmwJdL1Lum3FHJKQldxlTMIUhzkf7XkPfowaABvDGWuC
WUwroxnrQOi16i0brEUS4Yh8+yUydwPy3GSIh538wMWqGkd14t6lrAw2SL0KHWEAC2VhdLUV3Vp+
Xc/8IaO5rjGQ+/IsDNXQ1B7IRYm3UU1aN/cKm6lIyBubgetqFsds+zYigaUaxtE1Bj7PSTebAC94
nyeOY+hRF3hvmEtLqCRJCu3VH/8CWsYiu40UP/kerIVio5tDond2Xeo4cD/ZsSWUfZWC0gn2T8Lp
OFmkAY6HB9W/sfZHkxBHCYXvHaOVU0H7a41WnII4tZ6LhNegdmPxA7UGQH7JlPp19IWQMRAQPT7A
TEjkTherPvpjQO1Ty4ytQ1XtrlqhIyvTdldG96anhzm70W2Qe3xclNsW7HqcoZlBmiUghaRY2jOh
RvWNrrPycFkU+3dKJRsQxYbleJrzXm/saUW+KK6vJhmy673K7I3ko5qM+kTR09GoPk1Wdaz963tS
THHvm0jLsK7cgFIg5sCiMMdVyjDXIrROYXCLT/a8Kq7ouXOG3pEKCBXM/fqOQHpeBwLwjj/na4Y+
DT7SvHMPSRHY68xknnSZjZhO6X6L9D/Lw50XymwsKmGvKpg8hwMhwH1ovN8DVWmUfVcLY8RV5fPu
cvYrJ8G9XNy2d7u95sznubRil751Cp9pDSwVZ8JW/oOGxA4zkJB8iQ8eL6h5uwbhvB4u4auZ4NJX
1CPX1Ta1AtTIKhZUKloT5YjwKsNU2svZKlolI1K/g9yI5Azjfq6jUKz0VZ1rzK1rFtcRU95UXR13
bSVs0QDQtTkcwb2U6bmVrQDindiNJCJSVB01lkn7uVxnbFkwlucFZ4gJDKzhpKc4rmtfQ5tvLK87
c/pXijgEDoDb+V8jWAx3hvnFNXAL2PrMqiImcKRU9aEs8NvMzaaFdIESPU43ZPYLhmgibKNHTyRP
dw9BUv07GidQsWY5Jfz9BR1zlrdPdOyii97Z3U50q41ZCQzQBUZLMbSp4T2pzluN37YRGkXuIgvk
CdHSYUR1w6YAF9NpD2V6WFskVZw2U3TBMYZPPJo+lOZKXbtBFYiSuxEXmV/O1JreTfwY39qV8d5+
zG+SLmAcj/tw9eQS7fpcdQUKwtpvUS4yO56tsNObxnq/T99zU0ew04gN7cfTr8cAzYwAmZTcQyB9
Wp/J1Fa5BzKejIPZLdrtvjofqW7QOEX88IeSEJTabmLMksBHo9CY23hvoI4670G+PdVMc61TV7mu
t2+qfCoOrbFiqg7G/jwFGIB5Sx2pUTUqfa2UpJ/fJ6lnDzoY/+TboF32ovWfEHC31GoJL1EqmW+5
aWMq41HFe7vQq/sUvx26qPvSPXxGUgJbi0vaVN2axpvm+nz010BhG7dDQKIL/22Nis8rqb0qcBv8
VgVImfuY2RDDrQHvF8k3Wshklu472cSq8AF16izb0g+6dX8G/A/tl9pdehzkkF2WJrJJNzFMwUSy
Z6gf5jS+r4AW4q/jFvjRK30zyYwIWahHru0vC+VfdsPgmUw6CybX/uwcCkqfbSPqC34dmKHD6lpK
SsyFZSG1z5x6/J4QyWbB6GO9GrTykNXnI4LX50vbdR465MAYMgAc0PW+s1wd7KCMt6VYaIcQwlNB
Nh/oSXczkU75rcP0Ng6UyaS6dD+kv1IrX/4ym5lgO0Mq90fn8RMaIMHrh02KTOPin/UqcV/BLwb7
SGbJTEicfVwda/665scUTP+PomIgN4XDksEmd1lJ7QPPKRauOib4MPQJ2ADZcaCfbT3rfMYDqLuV
YuLS1AaWoMimrbe1t+SSfyjzlBnbD0xSadQ0HDe8Gy3yQ5iamTurznixXKXH+gOGX1kqVUOM6TIV
89feDfSSx0qfujK6lFBwmooJHDpdlhnr61u5N9nROjNI7Vj+zwhsQ+LYW133wuAYEUxfC21OY8E3
pEOJYeX3YpTIsnsZ/Sn0Ow9q9dIsdvL4W96BleBwE3G0p3WLyGYjgBRdV19LWYARQQQRkYxPOyBo
NcTlh5MOzHqcw0cgKpTXur5F3q5Tx1/SwIhwNTWoMOIv+XFjsovcGwSkfZTRHsb0STi2fOk5Pkpa
UdgDn061fUWEG5rTPv2Pi/IHzPXVGcGEHXSQaiJK4lhk1RNYfoLv7gSRPiaXXPeZo44PWZSseUjk
4pJTAUaZtvC8hR7/PchbsIG/8jZV/7bz6JkQ7Q6yy31lrsHXOhNFino9tLnleBZJjPERTW8M/Myh
DC/UlCjPwoWe/VdE0rizjYYVkEswn5CFXuvIzSnuhAD+yngs0e0NUK1lh2Cu8CS5rNO7E0J1JNZq
gnnS4OheJv36ODWV/H1PP0LJM4/x3BWdTNpewMjPAz93n+XoW02ZsTz+foYV8ur7ZQgOwAkNgMmn
wXv9CQvFIkyOTEDdeUMQw0UfxhWz+xBs4m2ffD6p2XARKB7E+osVd/WsQgXhYxOm8cEqn2z87tGk
LZ2X4rZPFtq9oXX7FV1wQwmnc0znfOzef9GA3xuuSebp5O3rmHho9+mfj5JNyKXlQBizcYAn2SQE
bPyWokHR5vlkdQMwmP1kWAYlf5qokDnir2lPWNIVu3sUSYqNNaqlGULrCau2/Eec55l5n1GwF3bf
Yb9aCEOWA5DRtLdqFNgdRctMIcFHxyOitXraVs8Bl9Xe4j+rlW/sakBPV90oQ8cVf0o35nLQF9kN
66Tuzrtcfu697MVteMVKcBas3ZTYte9ua8ryzbZ0w3sIMZ8IHjpjfVIZtidHFNX1tJhohcAcCRdj
vwF+zjD/6dgo55cZoNtoPxjMhrZ6+T83ArBK/UYPyX+Y+hTIrF1B80T2x63aeP7Rj5ENp7nDono1
Bf88Ly5cPgWuT6aR3bSsvS2VlB0Ay4Du7iHl3gB7PVSRfuwOPIsZo+P1K24UmyZdVgq6Mtad1RnG
EUUySbapAZJpfYzHdk9NJ8dU9fbdIjeU+JVM2totfpWMBY4zjfqLomOIC9XInObLBkoQ5W7qfpwo
W2U3/h2hnlK3COtSch+mH0VdsIfA80WkSdKFtXebZcqnxGucgNWIMu97Zq5tr1MmNomtLTOekkfr
pcyIyeygDJJ+RUwfV4gk7NNObJj84CGqasd5c0AGoJytttLQQRYj97vFyvQ3750uuNu6LultdMQ4
tl4WHtLsnysf7jyTfjuCmUGHOB3M57yGei/8C3eHMZaGabC+/vCMl1pJ9+pXW66iNk3qLiya3Gss
qH8dtw2wIOYRRZNAuD5p31gwV84i55q6RCXZmBOjwqtTFIEXn/w/SCChROaaCRVYjfBkqZ6JwS2U
xma72dRL1h7rF1hufkCF3EkdLALj4ByrYlQmM9c0tZCUHoVlrjGKg/n+TOmBfbyhS68naUvDehz8
rwnMDGSNG/pH2Gi4FXyBoFgz1A4rXInu5oG7jtBtBKZkKvMAtUC5MhM2afLKuZ8umxNI1CxYSbfd
MAM1uLqs6LSmWV4ENx/WbjkfZQJl96/ufYJ13E6aPgmn4oZ16VYl8HL3JU5+486nypD5ns0yzsEm
9T1FQUuj9+J8akJDHA8Ts/rhcpnxceb2OZ+TFq4UEV1UkWUIm+GCP0cFzf8A4ub5I+CYA6jxV+Ks
IU1UnCearq0xZAK6SWhiBs/ltjUX/Ac/oQ497t73oafmMieb9fWI3O6cHX1+nZpKRwQUtG1e2VKz
oKhcYgyYeGn7TzvD8KuE8bLjgaj7tyBM/Sd2U9dRtfUiov5q6qvLGnw8YJuvgfbqMKJZXlWVJBIB
7GJRtflfQs1Nr2tVEAylU0QnXKYubwxW+sjGg9/j8NOrDU6Uc5x4r3ZSuy21ts90PrxDS6Ug87C4
9WmfEs81lLMNAXXrYgbpA4ZoWVusEOrYzZNT1vAOICJtxOuRc5Qcn40jpezenTtAb9PvBtu3SkU4
MuAKi9GEjEDvbuhoQUp4QYlyJ6PxmuqKrnqeBm7gGHl6P5k3b24AH4rje9zGBeKRWawIiC40W+vQ
lDuiB4PgEzAKCj608jfcKq43IIcdB98ZpObTm7EVCy8FljuJal/U0R/pE0IPwHQJQrDZ8cTRsLRb
87RLMw==
`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity sld_signaltap is
generic(
SLD_CURRENT_RESOURCE_WIDTH: integer := 0;
SLD_INVERSION_MASK: string := "0";
SLD_POWER_UP_TRIGGER: integer := 0;
SLD_ADVANCED_TRIGGER_6: string := "NONE";
SLD_ADVANCED_TRIGGER_9: string := "NONE";
SLD_ADVANCED_TRIGGER_7: string := "NONE";
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY: string := "basic";
SLD_STORAGE_QUALIFIER_GAP_RECORD: integer := 0;
SLD_INCREMENTAL_ROUTING: integer := 0;
SLD_STORAGE_QUALIFIER_PIPELINE: integer := 0;
SLD_TRIGGER_IN_ENABLED: integer := 0;
SLD_STATE_BITS : integer := 11;
SLD_STATE_FLOW_USE_GENERATED: integer := 0;
SLD_INVERSION_MASK_LENGTH: integer := 1;
SLD_DATA_BITS : integer := 1;
SLD_BUFFER_FULL_STOP: integer := 1;
SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH: integer := 0;
SLD_ATTRIBUTE_MEM_MODE: string := "OFF";
SLD_STORAGE_QUALIFIER_MODE: string := "OFF";
SLD_STATE_FLOW_MGR_ENTITY: string := "state_flow_mgr_entity.vhd";
SLD_NODE_CRC_LOWORD: integer := 50132;
SLD_ADVANCED_TRIGGER_5: string := "NONE";
SLD_TRIGGER_BITS: integer := 1;
SLD_STORAGE_QUALIFIER_BITS: integer := 1;
SLD_ADVANCED_TRIGGER_10: string := "NONE";
SLD_MEM_ADDRESS_BITS: integer := 7;
SLD_ADVANCED_TRIGGER_ENTITY: string := "basic";
SLD_ADVANCED_TRIGGER_4: string := "NONE";
SLD_TRIGGER_LEVEL: integer := 10;
SLD_ADVANCED_TRIGGER_8: string := "NONE";
SLD_RAM_BLOCK_TYPE: string := "AUTO";
SLD_ADVANCED_TRIGGER_2: string := "NONE";
SLD_ADVANCED_TRIGGER_1: string := "NONE";
SLD_DATA_BIT_CNTR_BITS: integer := 4;
lpm_type : string := "sld_signaltap";
SLD_NODE_CRC_BITS: integer := 32;
SLD_SAMPLE_DEPTH: integer := 16;
SLD_ENABLE_ADVANCED_TRIGGER: integer := 0;
SLD_SEGMENT_SIZE: integer := 0;
SLD_NODE_INFO : integer := 0;
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION: integer := 0;
SLD_NODE_CRC_HIWORD: integer := 41394;
SLD_TRIGGER_LEVEL_PIPELINE: integer := 1;
SLD_ADVANCED_TRIGGER_3: string := "NONE";
ELA_STATUS_BITS : integer := 4;
N_ELA_INSTRS : integer := 8;
SLD_IR_BITS : vl_notype
);
port(
jtag_state_sdr : in vl_logic;
ir_out : out vl_logic_vector;
jtag_state_cdr : in vl_logic;
ir_in : in vl_logic_vector;
tdi : in vl_logic;
acq_trigger_out : out vl_logic_vector;
jtag_state_uir : in vl_logic;
acq_trigger_in : in vl_logic_vector;
trigger_out : out vl_logic;
storage_enable : in vl_logic;
acq_data_out : out vl_logic_vector;
acq_data_in : in vl_logic_vector;
acq_storage_qualifier_in: in vl_logic_vector;
jtag_state_udr : in vl_logic;
tdo : out vl_logic;
crc : in vl_logic_vector;
jtag_state_e1dr : in vl_logic;
raw_tck : in vl_logic;
usr1 : in vl_logic;
acq_clk : in vl_logic;
shift : in vl_logic;
ena : in vl_logic;
clr : in vl_logic;
trigger_in : in vl_logic;
update : in vl_logic;
rti : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of SLD_CURRENT_RESOURCE_WIDTH : constant is 1;
attribute mti_svvh_generic_type of SLD_INVERSION_MASK : constant is 1;
attribute mti_svvh_generic_type of SLD_POWER_UP_TRIGGER : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_6 : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_9 : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_7 : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_GAP_RECORD : constant is 1;
attribute mti_svvh_generic_type of SLD_INCREMENTAL_ROUTING : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_PIPELINE : constant is 1;
attribute mti_svvh_generic_type of SLD_TRIGGER_IN_ENABLED : constant is 1;
attribute mti_svvh_generic_type of SLD_STATE_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_STATE_FLOW_USE_GENERATED : constant is 1;
attribute mti_svvh_generic_type of SLD_INVERSION_MASK_LENGTH : constant is 1;
attribute mti_svvh_generic_type of SLD_DATA_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_BUFFER_FULL_STOP : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH : constant is 1;
attribute mti_svvh_generic_type of SLD_ATTRIBUTE_MEM_MODE : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_MODE : constant is 1;
attribute mti_svvh_generic_type of SLD_STATE_FLOW_MGR_ENTITY : constant is 1;
attribute mti_svvh_generic_type of SLD_NODE_CRC_LOWORD : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_5 : constant is 1;
attribute mti_svvh_generic_type of SLD_TRIGGER_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_10 : constant is 1;
attribute mti_svvh_generic_type of SLD_MEM_ADDRESS_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_ENTITY : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_4 : constant is 1;
attribute mti_svvh_generic_type of SLD_TRIGGER_LEVEL : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_8 : constant is 1;
attribute mti_svvh_generic_type of SLD_RAM_BLOCK_TYPE : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_2 : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_1 : constant is 1;
attribute mti_svvh_generic_type of SLD_DATA_BIT_CNTR_BITS : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of SLD_NODE_CRC_BITS : constant is 1;
attribute mti_svvh_generic_type of SLD_SAMPLE_DEPTH : constant is 1;
attribute mti_svvh_generic_type of SLD_ENABLE_ADVANCED_TRIGGER : constant is 1;
attribute mti_svvh_generic_type of SLD_SEGMENT_SIZE : constant is 1;
attribute mti_svvh_generic_type of SLD_NODE_INFO : constant is 1;
attribute mti_svvh_generic_type of SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION : constant is 1;
attribute mti_svvh_generic_type of SLD_NODE_CRC_HIWORD : constant is 1;
attribute mti_svvh_generic_type of SLD_TRIGGER_LEVEL_PIPELINE : constant is 1;
attribute mti_svvh_generic_type of SLD_ADVANCED_TRIGGER_3 : constant is 1;
attribute mti_svvh_generic_type of ELA_STATUS_BITS : constant is 1;
attribute mti_svvh_generic_type of N_ELA_INSTRS : constant is 1;
attribute mti_svvh_generic_type of SLD_IR_BITS : constant is 3;
end sld_signaltap;
|
-- -*- vhdl -*-
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.pyvivado_utils.all;
entity CombMinimumGeneric is
generic (
WIDTH: positive;
N_INPUTS: positive;
INPUT_ADDRESS_WIDTH: natural
);
port (
i_data: in std_logic_vector(N_INPUTS*WIDTH-1 downto 0);
i_addresses: in std_logic_vector(N_INPUTS*INPUT_ADDRESS_WIDTH-1 downto 0);
o_data: out std_logic_vector(WIDTH-1 downto 0);
o_address: out std_logic_vector(INPUT_ADDRESS_WIDTH+logceil(N_INPUTS)-1 downto 0)
);
end CombMinimumGeneric;
architecture arch of CombMinimumGeneric is
constant LARGEST_CONTAINED_POWER_OF_TWO: positive := 2 ** (logceil(N_INPUTS+1)-1);
constant REMAINDER: natural := N_INPUTS - LARGEST_CONTAINED_POWER_OF_TWO;
constant TEST: integer := logceil(N_INPUTS);
constant TEST0: integer := logceil(0);
constant TEST1: integer := logceil(1);
constant TEST2: integer := logceil(2);
constant TEST3: integer := logceil(3);
constant TEST4: integer := logceil(4);
constant TEST5: integer := logceil(5);
constant TEST6: integer := logceil(6);
begin
single_input: if N_INPUTS = 1 generate
assert(logceil(N_INPUTS) = 0);
assert(o_address'HIGH = 1);
o_data <= i_data;
with_input_address: if INPUT_ADDRESS_WIDTH > 0 generate
o_address(INPUT_ADDRESS_WIDTH-1 downto 0) <= i_addresses;
o_address(INPUT_ADDRESS_WIDTH downto INPUT_ADDRESS_WIDTH-1) <= (others => '0');
end generate;
no_input_address: if INPUT_ADDRESS_WIDTH = 0 generate
o_address(0) <= '0';
end generate;
end generate;
no_remainder: if REMAINDER = 0 and N_INPUTS > 1 generate
no_remainder_inst: entity work.CombMinimumZeroRemainder
generic map (
WIDTH => WIDTH,
N_INPUTS => N_INPUTS,
INPUT_ADDRESS_WIDTH => INPUT_ADDRESS_WIDTH
)
port map (
i_data => i_data,
i_addresses => i_addresses,
o_data => o_data,
o_address => o_address
);
end generate;
with_remainder: if REMAINDER > 0 and N_INPUTS > 1 generate
with_remainder_inst: entity work.CombMinimumNonZeroRemainder
generic map (
WIDTH => WIDTH,
N_INPUTS => N_INPUTS,
INPUT_ADDRESS_WIDTH => INPUT_ADDRESS_WIDTH
)
port map (
i_data => i_data,
i_addresses => i_addresses,
o_data => o_data,
o_address => o_address
);
end generate;
end arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
LOrXUPjF5IFoLR0AYJN+dt4yr/8PqcmGKyTL4CgFcGvIQ/aJ3vGk36Cz00TRq+Nqo45GnHt/1m6E
UtRjBvwscw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WJKji58llb2KFFsN3Cd7W+Zzki2XT+kR6uYjuhoIbWbNBY6QIL2EpnimDuG57wFXeXyygvWr7yZK
VfWkOmEzAoMkw8hRi8Go7bMDERt9P5yhKxDIWNswSFLZMI88xgrYUluTl7zN1MvivA6Gt/XVbvPv
3GGjWUoqFlxi7f+DFPI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Jcs3+SQtGSLXFw6cEFOru8HjLAfKHwfQq8uBjCuKKtwRK/yAJwHRNjL9vc812moIiB8SgQ6pgBcS
Krk8XWqTViUhh08+bhuqDoOZqOhRUnVe2KU5bPOaP2D9D28MoI3jEqKcN09ui/jOIGo4bQMOEbtB
wlRhrV0ZlM8hz+dOMrE9TqEKY7v79uyDjoJxh4nhEugl6X+2H2jvq2cqqzDTFfzkrid/WPga5bbx
KkG4eEks3DZVdZv7b+yNIRKNuVxxfwkCok9M3MxHhufe74MBfVoppTGm+9M1T3tJNnRZ2GXItBK0
1RYRkOuPxTXDLegfYLeDZsAuhH9IEIshQelv1w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
yofNydq+Hv2ft429NgFsYlO9b8jA1NAsY+uUYJMnIovXFAwZsz1Ox60jgGkg5M7evNESBTbZBPcI
PTWxb5rdOnK4575N4uhSw3MITRy7m1hlZM7NFQn2iS9e+tLlKFKKUrsejS1G3PgGgo8fR5P/7VYQ
oqNlDT9rFqWM2kjqfZw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
MNqDEnqKF5nNQQLZKl12k5g6EvteYCdq0RTqoAuouDXi4v48X86esK/4i/V+9HB3NeqF6RV2fE85
W5pzBBXr37jp0pzu3JoqwausCaAEJZMx641TszLj7JMKRrTVGZcgpWD+M2cay4Spk0Q93SkdU9zg
z2jTkDt1oYIAU0Lj8C3F4lDHk3itQkKVEDkczOPNS2iw+YeASIrN/QVRJynOQKfHbfIa4TsYzxAh
mI0k6aWPaN6Ed4QbFNsEMPvtduaur4tT93LN/4AigwrZKqQUkO4JP12H1+L2+eLhx5WQl/MF21Zy
ykaSn6yKqF6ZSA5d08POimRDuEDdjAIUFc6TZA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 36096)
`protect data_block
Jay0qZlyG04qyslfbjmu1/PefK58a1bAtzIU4O3B621tSZs6uZb560Gj40HzQmBC5guZu/HZNXpk
vxqrOoIdiV19ysXXCQgvDav2CLc1JQfaD7MO8lM+3RzVgA5/4XBaB1Mxjb3LoG2ypsLw2paMea4I
CKH0J5e5259Hk6gWXGBHwMe4C+DuVqJv55l4WjiIgqbbnzzosYTVcsZFHp2iZLjYZmiFcvLK+C+s
YM8KrlQmNuqLBtlMva2lzejLuYpxhT1OBdR577Y6iBRZqR3PjyEYRf/9CdEB0Ozv2PZyhO5wqYvi
CYKVcXLCmAYMTErMD4iOoKiDTCF7BkO3thY5m7jq0IpYnxVKNFvcnRd8LsSpzuTAUHZTtlQBYhmR
UrGLqAaXqUqFEGUw9mt5DiflA9JReczFr6QfMqVRDEJ5+mdLlajI38MaiIFztLwdb3LvWyKGUF2h
fRBFgH5vJRx8mfWr25Mp2w3A45NudrqUgoToO3YgPGfL+n9lqx8iItP6DTaZUu45aRKeNO5W540M
VqWQEJIZOPsP8WXJ8clvUAVecQZoudMVwImD2IpfE+XBtwOO2pWJ8bgo1Hl7v6kAWLffu3D9TfOX
OQapmXk85Jxt+1vavpMpExqdzBLfJEuSBGjKCucJfiDZbmoBnN/cksXN5vTUsdn7OY7MQtNXqKBd
YWfu/jl4DNhMxVRncGcJXb1PElxl97/RavPWTnQsdzfdBNXhpXi280qwlOK3xiLoAEBfYaz1uis3
uOFeHp75JwW6oji9AqW4YOIzKxzNdtwUV50+gEd/qt0/Zx4oCDPV/78Bkft7QUkpNY6b7qjwppfj
i5yG3i4BWL7vfLb+rLtKgqKXSL+GYshHHvk6nZQqmfADndqdPlncIYyk92muGbPsWY4iSjy4C+l0
39fXs4sJ3rfAs1S7P0FJXf/YlpITtl+9gSM1HqBd+z46+OjDX8UaQ3le6QJBwGPy4xQqclpTnpxp
zqe0Ke1vD0MChhmXJa+SyBbTWtNTH5n2u+pKy2R8esIjPTgciOpbpX/KxzdzEx1+dSruXVW54xe7
JUpcVe0/aBKu2k+QOv7JRA/A3ypHZofMwrQGnyMtFv1Ui8KcELhRc5UzpsM+emYQH4XekOXYrUfG
5jAD35RCHFTZKKig42l23fJ18Wi+0z4+2gxGX9WP0F5+xL2IC6gmqNIFb+ClWILZnqHRdXvXmfhH
//c+s8KVsKOkPPzplo08wKOtdQwtTzbm8IACRfCkqLAyQM3WWnnl6sDUQAp63rOU/4bFDHpIZgn9
6v1t7jJpMk9W40O7X14+N+33QyTkRHTO+6AwUU+voW+NdFKfzUBqC5ipKansg+TQA1ySjMMk1dHf
77OgL0D4KtGQj9dEHk1q6MyLY1kVhqkWVgKajkz6/YZ9ewJV7JzyFDkqL/RywkOEc/KjvBC9g6WH
YbomdvIAWKYwfrkfXqRYT4nLBIoYwsBgcUISM12USI+al4qnaGbaKYQxrnHvfZS7vmD+dPdhnpw+
Knbsr6C5fBh7e33AJsxMjXB4y3xMb080um1MB5QeMVJJJmrfp5AeaVri7GzVTaT+b7QLKAvFREEt
p0VoudklRvCkicArcLkFN4xuPs/LuJZFQhX2PjXQXhSWjCjTmijc+20PDxu0vSV6UQTG/OvWIeCJ
D+0idv3ZrDWpz5ikktANTclHyzNwiFVArf95ES4nWx0LN+ODiUgaQ3NWKKKnP6cNmeQM0oAjBB+V
l0Ept/17YpONRc3ZMkMwm5TjyrAwxje0ms252wKTNRXX/AIr6vyRjXuNpzf3xh4brfpGqkK2dXtU
XD7oifKQCMUKkDV9qU0iT++9hn3f6oow9ksk2wR4LxgIsv6VC/zMSl1oK0jmBgpVj4wq8SDN2u2D
vhB1UVskGEvKqZdn/qXCHN/II0cVeirCjNxB6/DuNoj9AJ84R3tWnqSH7BelhFgJ5s3umiqHBeHq
IDQDfbz37SLrqWOnp5GBUb9Rh8tFbjOI+TTXWOpdkHxRcllpWPRwXdAOX3aKGKTjP9V5ZW6v9HBM
PFxp/w1LUo8HtIVnwbRycbJjh8IqVytqJbDnePMnBPZTk3hO+0PLe62dx5OIQ10Yhyc2LjViSoNP
KRSk2ExSdUTDZk4N1+O+35MFwzklX5R5e5w3dSzFbf5N8X9Y89UlXlTNrPq/YK7yz+QSNbS15Hd9
XFaM1RFnZh+IIE7zjKFQY1y7tET1Fuf+rh9630HxFah6HXmzAHkyv2PpdbvO+eMxg5h0/3uAJ9jl
v3W979F33x8l1URufVk+Qf/b/WzR4i6ou4P4vMreIcdzfohz+I1UdcmTxCI3k0xvwcxmiLuX5Gyv
PNLBZ6G5ab9Tx683rhkr1JrNhFyaya+YtyTfs9oQSdQSjX4jVn+OgUrfsP2pwSrarxEr08nJVtj/
LTREd3qcPuicM2SPHP6LN4KXtgsk0I0USWpIRJysSuGmlTujxw1XR9fKEOMzNlFTXvm9jNMJ0z/S
F9J4/XS8rOJM4tbogxuGZsmKC4oZfdBdeXsIMVm3X96x9g2VxTlLVz1etfL7+Y2P6DSg6VnpdCC+
LVW3gyCmvzbOfKvBVuE+yCWIrHPDxnktznhF6u3F4TDYl1wcMvjV9+FdgFwtr8+vWo3nzrfqg3ph
WU+AhJJV+Uk+moIJC4X9exypHIeUcEmu8qlWYpOyRit56Oc3RpxvdiaWqAwBM7LCR/9yIyZKcmjF
JyRqo9H7Zdsfk7EDd6En8KR68Qi57ylNohJr2Fo05T8AgCWpBgjKSTpV/1aKefdv0SlRK9gO36Mp
9m0Maw4dX3xm/9t16ABGBPE/+heQEu7bceeen60i7JXnhZmPUAiNKlf4vyK7jjx/S82PUfmpzWNt
uBl5ppoG1o7QUcpm66AgvoBi9X5/s92o8OvLQ3NCjsPRqYpXjTfaCIYKh5+Rx+D22XKbij+ju6rb
YeFnGZ4y5UPa9kZ9mDnB95AKcypxQCrWO3RQH2zRfV2PMKfQ2iFqj5v8cwGO9dn6fZq3t5B5H8UK
o4YLJB/5XLgk5hkIuD9GubYfnGxijOC97LHhdTq63l+mXQYXHwZjCC+86H/uLvrZ9KvXAQQAJAbh
q/QaI56gXD3e6MvmV6a/ZILgBRdNN602rw50wX9v60kWZa7jCMFPOJToISdTwGReYZnr8SOZQZFL
eyH+hEVdRSK0FNBiEwP0nOF1eedKjYwGncRAYbc3n8hWV141D43c2EmeS6vWHhr7ezruABdtMj2y
XbFcjCfO0nTJgthubHIIDItv6DuSlO4t8fkzMl0loVvdaPSsSjcOVSBVDJiacW43GmL6sCTcQune
tIIj/0tq9T1kJB4SKA5oa1rS7+emZAtXToMX0vh4al4O/9lRmElrDQULT38pHxJ5517BxMLBh2QE
O4hAC9f3+dWKqjnBMiDQAfOFGcqdc58XC9VkKxES0LyabQnnWnzokuHKMMCN6f9r5ago+pLEM3Fv
R4dSN10EPOkhrXOxodFV6t9ksV5kx3Th6v4zqf8kclnCccAkI7fYwb4JX1SsymqWE12t0vsKLrw4
lUqN6hkbIUs3Sas9HiZrXsV22nl2CXV3hV2UUfE60tMhm8vbXUzt5ghLq41PrZtIn4DiIRA5okIq
9TkghcZoOqqqae8Vw8ttYBA1Ja+LIBUydVn4t24N/rcwvfE9ASmFWKwmw+bZGVMlwVag790JAgQq
hlgalgWOr3C+rlV+PE2vkUkKiY4jUFRfjpHXCw8lwZnr9iOo2Yo0DHxAvho4+j6el7lCSdod67RK
vVUIIlor3/31Jl2WXnFNcwyai3rnasUOEv+lsbaiFuv+GwBbuBZk5qZYEVQJWk9ZoDMy9+kihYG4
M4/qBb6bV6IX+p2YCP9Sm4g35uOZ62351n3vjxS7NA3UJE0Ejs90uCZwQ/qEjXqnJSEC2VVeNmUq
8UmSO7Y4gsAobe6XTty9XPLVs6141Y0DTYmwp0InG51XsEqaLESIstJL8E+49kdj6+fpGM7T57nt
16p9Ts/yX1ZHx1D7ORH6UN56doV6wvh+c5iEh1DjT2V9diHndDECSi3E+zQAn1MDQicMYUz9FCHZ
QmjVy+rxXYH0nuygHEH5jT8XhG5cExILO+insYZw+KeUDcSpvNcSVc3nyaYu4ct8OyPB7x18kubx
uLENYer+5oJ4rCydPAU995+CdTpljyxjHzLuf0nMs5pOtJVxmiTndUmNWMGEJUF2rQ/cHGYh7/4c
CFTyfv7PfG/JjOfgcjrYgHn3Tbh8sC1Rt/aWTYbxhFMeBMLAKR2mhXL2yZF7wbps6K/kuQrjYuov
YevrgkXKhH2JycYmznTG1qjLOiRo0lRlg0+T3dJv46u5oe0yY6cjuQEMzCaQbP+i6nflgsLTrtSM
6rRVJCE6olyFuLxRNaDGhM17y+J76H7uBcdmQgWgEIqUHEM4JZARRi33jYvcUb/hKQFzXVVaGHfy
o7szEqynSR+ArXYxTsNFGAxIoAc1UicRkoxNwEXnsGD1ISxyEsayBcd76agIZpe8fPPrYgX0pDAw
27xRGz6BfHTMTbIH7iBT4Oqa1BwuyYgVrJ82ocYBjv6Ipfgq6cplYwCE2eQEpETDkdol1JEILkAE
0F7qvdzCNnQXWgPeI4/WkdnE+YTxqz8dBbUD3sUKr+jJjfnNv6kFwvojq5gsBEL9ddTh8LM8QFjH
OtAP09F8Gu2yDzKodOqCvAPJZbTbxN75y7Sdmc+Be6EVu7KskbRmnuetLtk6ME4HNu1FkiuW+HDt
L/DBocQRMmXn9yuAxBIFeNtuA9a7p1yZrV6DCs+VQcBNNCx9kt+JZ+zWqB/dEuZ4ibJkVPQgw8XR
AChPDtIUx/BcOKVK9ZbTRKPe0ZOZc/fesjSG4jIt0TfAT+ykUinvMFMOfSWI8niujDOrkXRwrsod
zt4+uTCV5+HYWbY+DxVpj0kRbkCuHyVk+HtuhGrgq/nfBzJafwa6rk9zMvjbM2Rb+wHgEbgmyQ58
UkamR7KpCpn9tnC0+UmQhOQ9XMkx/+V6fsoD26dAD4VrizmtCTEHudfC0crbikRweptalzpO9w8j
9MA1pU7cT0VBVqPAFnc/bM/ezES/+p7FYscqpqxJ4TRXPxfItWpD8lVUnASOvmx2efkLEdXF5Hk6
z+Bwljkns8w/LXq3BgCP1DaLZqyqdqdVC9yiMoknRKEXagDTOCqsoNQfocLJCQoPmHxRh2GeSYyi
GB8sJkVgCUpL2zH7rdnbtS1zzNAoynHmPNSEHTNJE5eFuRvRcY2e7sLOuqvYMyHB0d3mkMDFUFre
FIGL0I5eeDSPBQZD2bg/cFIi4xZsBPx+e6ftNpTIfHfgKUf+tDPOMSu6chUVlM9Ppl8yJs+/HcjC
jIP6eqg1Ev+EisS+4CoTgZLsrdIaf2IXzmBNwsklFNBdVLpx9Ghz/gzthgCSCRmHvq9wig5v71Ff
tlrNvsswI/wc2/riCPg1FB3jZjqoNbit2ka9Dwt73QLHgHXdalcmxwELKWSCio4Q4KtL2oImamWH
YU7i/T/APyjw3cIz7IiwMSHOK6zKdUe5gfKmFzUbAb8V8k5Frf70554LjFE7KprNd87tsiwB2RDL
E2oaNIeizDNo1Pm5eMB772tlk6Up/vs1k0va5pGOn46GSpLZL2bJflnPdV0U7OJPLC1jbRcvBV/d
9C6UftvaeC2dviYAm9qB3ygbauyA0+VfY6JKR5hm4pGGHnAqfo6yzHQ+tsQArPik0kPdqQq8Ghtp
xzU5Utx05sTOLu4CK/d3hPq5WA5RW/wrhLcMdIKDOrn1YCWG+UXhiisfg2+PkGkAy+udAKQS/Gmg
AOsrPvBLU+LH2NGl5Wpkrwa49fWy/CnmR0HHya2uTdJCfSqR+x8u2YrQ9Tv86upCEAlapiYBZrRa
klZeGGwjMp6NBBju72sMyDI//lr4pG9wTrt1fifV9l4BGPFgxj43SJ6c1e2PIsFKikvt0SPoUxtG
lQlYxfeuxD9viRI6cGsKyOy5Ij2G2kcuSyPKJ6foCw4oXGQ6w1t4pR/iX524xca7fAadtqBa1MTB
G0qjj1x5l8rkG3sKApz82mpanf/YzzmxrsSiFHImCfMEg1XZ/cIP3ARPrzw/zLz5Dyw/YWysHXBi
ZULXkwt76E5DZVxoPBZbUcIkVAievub527ftAlGTvHCRorAaccSyi+0SYrlY24pihoL44xFy9AOb
4B7u2qGxUgzcRhSywNoZB7spoWYVEgc/2ozOWaa/jhhiIpXk45wTAFer1Xepx4dCgZknLfNXHElg
08aIZnmXB5o4ttTwEXnTxOTeTlf0svkmDswdP1RguN0FDs+Chp4zzKrZBfIpY1IridckP1aTvLbI
4zwcZ6uS18tl18sEhlnl1aJ9xVd+k2zyn9ClENl8THp8K5Qx5AedZVGwzgCHZab4+ZVdVXAborKg
p7Yk7/CuPeG/VETD7ey+01IxmMDXgU+Ds3IIoHnjNZGcvpf7FbVhMaDGCuU0kJPouW9hS06/0ZdI
aYDkXF9C95m4tdUQqpVYWv7kCtM237pj0CRnY1Z7zA+tCmmjq30Fk5vhlxYcENQDYphxDHCeg+nX
ez86848fS0zajqs0SneVwZw07/jeaJEAMIXuo7oMrD5g96OaOCZ3VvHQ0SY0dx5hGjT+BGCWtXq5
R/kpaCzy/SMNFQKLgRPEhX0zL4QWfIfDS+asBLYXtDN8tGiQ8bCMiA8PwbGyF9E+GZK3oyh5SL2h
eFs9TnubgKZTF/X/L1FZ5YduuCZlu/ePmnIwloEg6mRtetRxFE4h6BY3qfDGV9KbHZG9VuCmR/MQ
CxdYLbVGcNX7se6ZsGfatS4UvyIQAwXoqdbgqeOjUTg2wnQAvbgWcehN5nO0kyuPnf+xkNlz9lCk
P3JAhwxeVVfXouzPi8OMDKp4d3RJUiJlioOM2hr07jB2936k1JUNGm1rS7WAcu/2Nbf7Cs4VUASG
L1uOdzWfIeruaHrsgQy0GF99XVQqMfsQ0Z+p6L5dzNrfcN3wSncnMTBHzPJkcOPM+/PIP8PJfaEW
43bm0nRrdZLqMlfoNUMuxUTBz62BAzAZOFUJFo8vh2l13xcncLw8iutvesaaQEv7VC9XAWNFLaeS
70L4av4vLRmDxy7Kb7o1PdmFbbvxXplt6wSFRJM0oL3vjZ/cxnut9aMfU/dNaAscEHnPasDs2tcl
tm3hQdUii8Uv8S2G12cQkYTG99Sr8HIwp2NwlahxCXE70mEh9tpRgyzmSglQ6afoMF3WtuC1baV6
uvr7mnzmNJJkPffFRvrQ7PmhYS7Epjhe06Nwx7G3oTNNJm8/oiIMSZRVPGjmXuLpXTYta0O/dac2
+x+iwxTweVqiSiC5++IK5FWIIn/jcge3ipSjlycCo5cE0Cyjtw626WBmZFsNSk+8ETWxNYxCbD4x
fqKDB0XzQrwCJEwg5rQy0WGp6vOXVAKxL5mJBSSEwtQhPO2iTgfQvv5bt7Lzk+D7YLTorLXVRZCv
0CXRAOAuBn2PC7rCwnCu/rYnUdaQ6wSws7VpSz9+gbsOODW17ATu4txNQGDzO44Qf4zJia2YRGpB
HUAsXQWGX9cy1qH9LyPodwLdM67HZ294tGLUMaiLiHN3xy1NycfNy70iMQ11T928nRPKUR1iIMHu
OPJCPE6Wuzn2TDXII9WCdUcucQeDsTPldxRPuh5VoMGAmPTsm3PkzPc/Oro/n8PBrbR4GxLIiz/y
CzMIPGVDVpMaY3zrsHLvuVcfEyRICpi+YOZJq3BU3qCMIm4EXuN1c6vl1MTF9YWYMYdf3OrPe+6H
LCyp27WwYleX2xZzwd2PAYlSsTy2vCnDA71RTng46Ws+VO884qIo9/zztIX9DVW4TraRvDil9C47
E2kTjrX+YCe3VN6C2+wdZ3sQguJGO2S4edyfCY3RTBe8fa7yMSy5SvT+S9rs8hAbNpooS5u7zK2s
poSxiwxqB3uN6vzVQFMY0FkBKqvG3MGcnyNRLbTNJSej10DhO7avP5zIi7rWKPdqOQ+1JEKDnn7d
MSJA0XU10u+JI6p6bKK24IzSCrbCu54KK/+rLKbapUzcl3Fe/3jqkM22XbZ/UkCpzKAHyQGNXxer
q0U+YOPWFYbH4H/3/UvYMmaPifJJeT4OjvGB3BJeCD1i4aSxR6k2kMrKZo3Wg0M1X/dFxSUSL2II
clcjiin/kMhvEBolaaZvAn2uODxnl8d0tD2ghZaoDHNgVoZb2N/cJkolQr/rex2Uq/39YXEK4tor
zIia7AaTSSGMZzE1fsNEjBYrF/TNVY6A5P2eHA+0Gg5VucFsYcUX/5hBgsqLH562IOzO83iT7fdT
nIz5K1PzI+QadwKpVnEeY9JlSQkiWIL8zBt+TWZwlZjCnprx/Cm0yxuzaC7MIQG9JrBykeK+wfKV
7pMLKTphuE5mfLWbK3N7K51+cjZN/evhymw/gIUQE4Wv8k8VL2gkyr1vFiayF8PCM5i0ia3CW6BB
ZZGAwX8NfF+vfu78dr0UbmYp+S1VUiF3AmdyFgrjxHZlA7s/CsCD2z/zycJB5u0teLrJcreSXcMh
pWt5CzoWFlYSlO3komimx1fgFnoE9qCKqQh6OtzwRxPTofU3V6VJ0fEgaB8s3KOtWvM/gCgILN3R
uiMcNArqYHH+JKsz7TTkR+b6K47UK4tnh+qqYKRrYNkvPF+xx59Kf7mYGTak7su4b+RqgqHUiPEF
JBBCH5/ULZ7tiUiin5rDlG73PyxFJamkueYer7u1As6B3V2Ti7CYIJV8orhn77U8N/v6HYh0dQn9
LI9O2QPBqqr+mLq09QLpoHF+akm9pnULKInAZTUNNkFr1fyDX8XIZdCIqklngyK2H//MaSjei7E/
4OO6cp2i7+VdPv/pN/t0EgX7BMUnl1etmuAQnULCB+LcQkUilheKMohI1Cvr4ZbMgF9HZu3d+rHO
YvqUYs6qL2qSz3RxglDFJFfVjU+zPX8RjfxEBUwFxzaXy8w3k/1IgTfWHg2HVEnl/x3+7huZ3ppA
eoOATRwLNBd1R7VwkWRu7+/NwRGezYZjzgX6ddqF4q9ILdLuMQQKe3UGjNpcVUxQTK5OodK8FonK
JQdLWcKg+IcB/fwoenpiJqRhYxAiiegExxcUXJGAzkrf/gshpGlOKXBky2FB6RFi5PiI1cxF9K9d
oD4ZZ2Hc0Cy+Is5hYvZuy+eb+d1vP/O8M0TzNv5XDkrJws121nxms0OPRbSE5aQT0JeYbWu/LDhY
2QnSoCILadQT+wmDJlJtg4lu1hYlKRVyhynOBw+R+kSxAZo7DIpKzqSl4Z+ebFDq8KpyloJFZUIb
qxpSn0eu/KV5VumEttVEUdXelLKmPYSSHgRm661NLFgQesUUmP2pRdTRc3Xdh0eI7HoPzK3QoPm7
IumNL+/OSQwGxenlD64i6Q61DjlH+EK4t4o/NtoBaCJ02tWiqxgPKPBYaWALIsQ6n1YGP78bjAl7
9aG8A52xpROoiW/spkOWGavdFWx9MjJEsuQf5zbw3+bzx5RMATXe+9LaLmsVlfqjgTlAlCVxG5Wd
llZYx+MjHLEuPutCT9iRrYaXYd5pS83HpYTm6n4fX9FrV9O/z24lhsUSa4VwnDQi4bsJmbxegmV8
1ZM3ije5dPmma93k/ciuDPjUhP+/3aQhIyzdKHdxxTY0t947dluMtbBtSl497A7ID8BDD5a8qh/N
jnmUluXuWBsgkLDq9IzeWjQe12I+JflPC9FIP5+qntLEH/bd/FAAcb41b1qmEON03sYS+iANEQa7
QI7vRo3PMViU9ClbqQBbUQJdbq0IwR31xKg8VDNhnzy2OxynK699FnosNDri2WTn6jFhpkMg8clp
uBt31eCIeRBeQZisAglezsRkpPhZOqxtt3AbDt6T1K5TO198gUUEU7XbRVb+9htNatMfyDABntDm
hatEVvYuzoaFjAhLWA58kUSi6T6SJl3fs2qf3iKDDzDSIZrVbl48imWITtfAm3kGISn6D+r/bLqE
wThg2iOEYmH98JqQoZ9SgR34E6CO1sAndubE4FtHXvI7FlbHqSrDKzbtofTexVFyBaofUOMe9nqp
9qnpLEo9uICs/dLkhGa7Sy88OCNGlboiaYZBk5sFkh4PYSxD7n2g1N4L/2tXMpb3aLheYNUzfEoi
p6TYQJWxfAxhllWBr88nxZiP7eteWuvquMX/nIjoX9hCVO6CLoSUeRRaRr58wcC2Qu8aH+yHPvHe
fDq/LSjNtGyTE8MYLwLrTX/ruiTnHxicpYE8BS7eUiOf6yjNxrRlfXzirMsRIyw3aUbgo1sNX5FQ
tVIaiAnsGppjO3eU/1CQOHOz8+wUnroSpg65TEu7wqC68Su7TYIe6lnstoRvQQK7SwQRzjKBlj7m
15QpZxIOqp1ZyVRgBQbwwCme45XPVHSC2UqODteOTbGkBLOC1R6mWuTjOB2xZD6zVNiH7w+rHOGO
PbCCRFYynIOk+313+MLxCMDDNI/Yn78cLzXuF8odmM0tfaIpZzC75I5HOggt7oepsgHqtOS/pAIt
ZhyYYo4byKOqJe6bwnOZCJcQ3Vbk83hMAaIxhBQ79uxG3vbHrpHjviJ5TEnXYn2rWTImp2BpIm7Z
baksycTBvu6sO5gjnttnSC3lpGopOWsIXFx/Tj8VoKeGs28pDY2sBdgBjuNM8mizFUbbCNavGemA
WVQB9M1RchOEMi6MOSPzNMcmqfRRgMYpqVTqO+BWNu7LkTA4RZ6doNcGM/04Bn95PGi9Dgc+nNV2
kzl3Lb0ddBW7D8r2uKocR0nQgk8R/W/zqWwv+Kwth1XsPUuVBfwk/RtBFRwZtJnow+DZBpKKgknr
Xd2faRO4mxyJVRYF8M1CmfAKhiIjIzdE/UxBwxyLX+TAiXznYRl3r9pM3j0rzf7x/DXwb8l4kpkh
YacJsaDjWtyLuFWWa6okEQAuWwYG6Rts1g4xNQ+UwoHj97p1JNkmP2wIePQb8GgEy8abiLTScx86
Vmj67jfICjSY3YPQOJVfqAZbPBvGtEsY5aae7WI6+y3f+j7M5j1gKpKyvXyE/nJzkb5Sqmni0ZWB
89tmZ59xEXLu/I2c5IDIYuYGaqzJOME61DZMOo03QGIbh9DTMvAeQBsBEKYMLMSK/+WUxLMkepn2
BD880n28sovbZrDQwLh+72vzwu0xDoCdv/3F6KNaBIMsrK2vzPqComCnm8rnGxkLn7I7On6WmQXd
NVdWBQK0tEoVSW6jg9q6JVAZpSMPr0R9dvwivJwAc0f3daTYddiyuJ988zwtL8K3HPC7FH3nYvVk
mM+opOHOZWiEV+mawJDsWiPBjo3qYHV6iAwCduOPgswCzOknWOZrdbaIpnrm+eNobbNS4iTvwjg/
O17pVyhKEiLuZUBZKAtbulFLA8KoJgAxkjFJNz28zc8rj8U75r5fVhb5b13C5KRe/kGrqW/w9H52
Hbk3gnQtmUJYWLcZywEmCiGhfDrzpKkkYpl/ljJkcMbmjP9O3uYWzX2J875h0FFGpdIzoVHM6P08
t4pA4z3dYmrS5qz2AEDGv6QKyAHKlEEXf9lCQIwh6RTcUb5mM6hRmnULG+XoUcag3M2NnrPGZZms
wneBMpwcKP59YQh1D+kSlnGAMGaNK5IO7dNc3bxgKUZUiCJfUn5cXiDTv3Q1CpcAAzsNK0sFnqT4
pqhtoAVnXNflcnB6jSRNB/ILRA7Cy3Td7C+4otVTGwpOHC5Ov8tcVv29p1qhhm8AyULILIlMvcwP
Wp2oB0Suzhg4zW8AeRFJ9TiLDMyOv2i1vVyM6jLLe+8AFNOnlbe4cTBB/QVMWBoIQKsiEeXW5Uqd
RuLYVxYuxMgrr6/XpXQm6n9ca5JnqsXinfd3Yq8ZEgbJRS1XzUZMmC9NAcrRw6NG4/vfBpBEj1fT
nyJcAhX2DCRNrbZkHf8BZeWYoy+PIEY2vhb7hBBNdJ3jhgpfsoIkUcoks7tD0pveEayrz1rW2niA
Z6oxYEDrnzQbT+7eaLb4Jqa6i1B5stAxQZPemqbkK2pXs0pmLLgbQC7umcuHoExkBuknl/eG+eXT
cxMyQk18QcnFT5rE/7yt+Y3hdKRBQU0CwbzoSKYBnDk/ZCTLwxZkArmAJfb2UiKNgIDJZIWPK82K
Pkfyev20OR3fFqTk907HfwXjKryTx3hqoe5J9X/mHmRTq/l1sQpLT2eGAamsGb6vZJVKbgWq7Cs5
8ubU5mnTjow/JVJIAzPXRDqP5EewEqH0AldmWT+thJazGcRKyLhu8pBQhP8WXCEqVOmamnOBFeUj
CEuNI5/RUH9WlICmEVR8+Vq/HDtSivhDaHIDh28blWYgJkVHFyoQo/802LT4KxXowxWHDIR3RvjV
frZS1heBhHpsaEXbT+uDOKmKc8NTx84rBSvS/1vCNOaCC+iuc0kwJWvSPSDcDB7unjPE/Ph88Lga
EHnkaOmPYvJA1SIcOh8g/oGc4kDU44ZBBvvD315VC/k/SS7WWqDELS/F8SlFihbnX+TxNCHgczgw
Ozfipd1IMb62JTqnVksdamWuqk+DcziWp72K7dtd0wiXBkZVi4aDVyn+tZ+LGF/22NU0udoegp79
lElzA2Ky4Kg69Esj4T/0jvmVDOKLlzeekZWCau63MVP4LKFYtK3bRKSRklQgfchv7XXLLCdZnDAY
WbGR4FjqJkMii9QzQr8pYOKQ/aDzVB9YSh83lJLyhdCN7f8hy4o9T7+bnqeZhMG7o8LguX9+5t3t
jKgf8EHz6a6dnZnKjPKa8UYe0+0aHVIs8cjNHS1uR8DM0CQ9dW8syIsz657OJl07SBiAuda2pfOQ
FC8XlkpyQ0I8X9M8c3J41wFJLXie6ssfai/S5EY3qaA27KerDv1jRtXKYwSUWozAURX0R/3Lwwap
yt1YmCKesrWqjQ8G94BKWKdq1qM5TGn/Lc22VN1fYpZZtGH7+34L1fxmHqK+R2zhrKvh9b6Ihq4B
hyRcDRUQ3JnWcFq8gtcN6yj7zsvS7vn9XZLVu6EUjl3JOF/j8ZwwXXVmWP5RDLYdhrwBUhw1nzBU
/P9163UpV/cDncwL+QsTIWVVH8aar9c52yRdXAoaavcFmWHuXxQWTHc6jeCWwgf83hWVSm+MR57k
xpQGOxVpX7Rq5esRKDcxga1aBX9XtYFYSrLuoTPkb4T1OdvV017gTNopApfLHBHxucKBUWms+6v0
C6o3wy45A6bcy4aJNRL9jDpgqIPyfLRCfI0Q5jKFQbak6Ax/bRuIL6G79htiJRQqfR6TZFTAq+LA
GCQ+iyFpbIcC+73xmoUKA4S+DYztZZQkc0A2M2eY7gvwq1yPaj6u4QDjCHMR9cy3vu3IYwi8Gv6Z
dsCuWckDa+ajOYF6QhcbKzs+/3Zv0QKsGWcOiAqJwoQcPSTVXWzXayq6Ij9qE55v5Q2lg7ArMCCN
kUrHyRbNtamuOLh4gLxXx8RiXjj1l03bCpeDU21LKfnRiY8dLfYUdcj39FuKdER6H+y8Wks3UQ9j
3UFEiOIBw5NNSQoKQZk1tm/9x2LyUTQPWsMPymT35dOYcPKUVf0aiKFk0nLB2WjDMz6PV0v4J9jZ
LXPe/qUm/tB9yGvFRIxy18x9RV8YC35Uz33o9D/rkEtOn0ab4zkCTjPqegvOcILpljkZ2TcOPn9a
BL+WffLcaBW0+T6sDifdVMmZLfQuJO6j+Y4LQvvfOz/F8f+oUUsVPYtJmniifW+j9leKT6RWkq7r
O+Gcfh03wQbpqheMoTdwSdJiH35qg0eibNYQne0+W3v6u7is4L7CDOMFwxBl8H03CnvnsiFE9BkF
2oHfXd9q9A1S94gp1aP/J5G5PK7WvylS1nQeyt6RQwGtfvWkJS1UQ5JAsS5BLh/1oDUy6PlhzCj/
Behiff91BzyBgwKyZdtCUJiTjXdW+06FNss4EGWm+6bHRwiqk/nWfpTgONRUUzLdVPT7LU1J7NhJ
py17rJaHIYLWfpKVJ14wtcFFYVteuMIEXB5xVD+XHKdfZxwm6I7cGI1uBJA01yvLDKNP4V5sGHgJ
PN4R7ZditZrLzzo3U09Gqc6+jzCx41CALX8GRpgu1pEWtd2jIRGMdgjL+ynUYlVzWeYT6BoyoDO5
EB+wiRWk7w3L/Nwe2CN963LlF/PUA7XksGDuXD7xArmgtAOquYuZMIbN6mhz3wejddsFBzsB8llz
f9M3hofYFEgEPTS4aWvKRiWifj6pUy3ZTE25/ILhvhAe/yJnNGMDeChg61gE7+auCQgCkVt4O39Z
PH2siP0UNog3yuk0ahZEUHXTWcw/hwVr15APvy9qSCJ7ciC+xSz1C8bHsfi02IZgFgG0LxiqpyTb
l5syDS2kpYitb0Mu3CG5JQDqpNss8T4aQ5WuW5Kk0XKM0RWZbkmYDBsrtaYe8iY0Z6PN2WpLPyGV
cCCB/Mp7+/HRvIQvMFFzy3Sj0NPmyxPx+1amG2rlOQEsSFW2vpL0RX3LEBW+gHvZKHD9kLwfiRuK
WKVcFwT6x7vyePU1543JX8oCslHGBD8lfyASZKEFJjNJ3fxwG22Fwx8BOryVQ3MYfPhm2Ct7AD28
2NYriBHmRjcLxhKB0veZx9qmAARTfzo1rsG6esb3xk9P/hViECDhbB52bqJKewflVQm3YO6CSXXJ
YY7uuxLpD83agh96N2KCItdS5AWKdXv/KB6c3mirNCpigL4Gr4mOA4Mk8Zm60JBvd3vdPffSrh2w
A/DaKVl5g86Lbkblyi1ZYMFOjTfYfvaGLYcrrvZO32QfCf18DO7x1R6VPejKxaitDQL5rO6OTSAt
ENXIdsBpfwQDEO0TkuNCctR1lEFuKPZtfCYmrgqIOH4Q5S4EFEXHkZi0TeNkYgZLB4jFryIf9yk6
M5KTsV4zd5MUR0NjYAn44d7K1E9GHSHYK0hBQAYHchaFEK91baz96kTstI5UH+U9DGQZKzvmisW9
8SvNauxUqDIW/cupX04iK+mJCjGMj1Jw5e+d4UQ9DGuhNmeBXc3UXqNcv6eDMvTKqxu6UHtDb2jo
Diz79FDoaVG6FrEa0B6gNQOONg+s3oli71DP1p4HLvOTYHzrAqr9txYHu+oBsnnMl7hVvBiSDOuU
X+DrVSASNhmq+awBO7azCvCB+mHv1Z7gUmyeodABBgdQFRdw52ObSinLMOT6wY+chp29Zr4hWTtJ
68Dyor+LwSX7Y1tlDVMj6GqYl886rxc4DRQwvI3d0wE5b85mSw2FEv3Ki4AZkA63McDdZsjI8mPy
Wy7H0+SRRa2QTT0PCcog+UOY+Paqi+CllkvJbrsyjMZb0KdvAXsBOSLgJ4DjrHIOHWhMbWNlPCdq
jGuQBDVxoRd06lSyN5gECZGCx2CK0RTvc7J/KCi0hdmwez8VT880TLrFmK7fDoNHQRwyOmc7hr5Y
HCyeu3Vc0IgfCzhT3ZR3nEcv3l96LiYyisr7SWdPOQ/pt0vq6t9Hvs6HvanLC95bq+ch2DSwtFP6
uoHHZQ4jxm5v5RGTmc5Kq4CRKViLBWnD9S9J5DPdSGQwRlR+KomAriGRpaaVz7V50+PXLp2t7KZQ
OleadEPajWg2S9JyhF0JkJGYHsjl+PVkIVzxWS62vUKBRrIldUMpkLiqLCND8NnMVp5LIYWV77fO
h3OOtzVdASDneNqYfFPbO+7zN5rTXXPEEOq7vJMfQL8PLH+6KRZl4Wz00wdBSWrQgXwCsOXSdVVU
4A0AX8wmnQsC3woILDRaw3Zroiw3B6WPZaCLg3DqP29MoOg7Bkb1d33WnQFdWNAedjFjfrCozVFb
PEKwbzsbiPJh6g/KtVrZsTpUO0+E+6pe5vtYYoLpThBnHTTaXw4XlVzHE9JU+8ip7pu+Ji1ckPjc
e8OAlrJJU+S/76l8shDnq0QzdSOdnyOiR5bj0QR+WZ9fdcvLvIpiiKtVThG3SzmAwpcoTb7k9bm7
74tc7YnKWxYv7ch0Qn0yQGhElsUNmqwUCqHjEavjQVLFfdheAi+uJSNEXZbGHfXTNEgUjqidaOy+
DehXzVpbvoRoJVUGwZJxm5/BqdTiL7eODIFSwNIi45wzcPLP4ntrvIYC2kUWcRMS2KGupNsUue8F
RBGd2Xlefcp4bDdnzos/nPmtgiabD2Dl70VspmBMSBgSBYCt2cxrIItt9zVFRcBut4BHcid7QI6a
36tLVm9F4xV5bfz5jJKY8P98X3ejTq8/OgYVzugcJn7qfWZgPs9y8UmINcFNLIdOiL9chtUVtOH8
ZChgg6hdXosI2T6gpIMMxMfqOgyHp8hAPi2OxdL9Z4usVEVMnqcGM8unvXT9U85fGYhvWTN1AyCw
eGWo9PHiZlZiPV3BpWlgnec8FOwukI0SEDggoiGtV0UUC/MUxW4iikoAQCw7tcRTCCJau9pvTx7C
QZkZ5lU/H3eSvE3Qip1oVmYOTyLurB5XLUQgehxGIJ3bZp8CYslRb1/YH62czqYsJc7RCBpr/UXp
DHyhV4ujcJnGh/VythWrulpq4q0OXGNb4BcVD3RKu3fHKJJCoxniPShuihxP/ZRffAvX3OH6IXAj
ZoqoLwDvwvEo4UIXylO69E0M96LTulG2fOn9VKjfZrXKYtMAaBWbhL1Tqk8/z0iJ5e7FPoCs00O5
vgICbboyQH5iPwEhXcKHhzgnolymddFiQu6PVQzZ0lotqDHdEP6eONxztAA4BERvwRkqoKXHiJsd
+pzEGGfGU84R4MLc4z0sA0Li3S3SBdm6V3NDrgDzmWQzS0Pse0jf7jUtFr5Hq242x+3k8lIPn2Ga
3UvJJoPuQYZEUXj5Dt1REj5+iXJ9j+ep8yfii+KWPUA0xUs3VasX9FiL2I7uvgIsfrYpfK0hVo84
Kpu7fEqL8KuA+t+L1JE/9R8XvI16ywDI4Po86AOEAC0Gb338BcbyJ5limr+I/4YWtaZg352UG9U5
4RC49JA+/KmaHhuvvsZuj2eJ5FE6l99nUg9EoP1J1QfARuBmNVUXkvOP/0Z0qa5RclyMJ4uZb+2u
wRDoo2j4i1/YpHDZOaIdR0UvmSXGpU1RgoRZAVggH1wJPy9B3r6/DuCTaKAk5gaPJo0UTeoXhPMQ
nWSEhide8gZaIWqiL/lTc7tmKjhVTzxa1Cl5EIUXHDkoXBq3DtmHOo4V8QaCrGVdC9qXOB1ucyPX
lstac1luNMPSPgCCK8KjussE1nmkyRq8n48LYnNzUQavStWVXgIFmG97mMX0LOFYQMPTVAPzOvvg
BQUmcmuiOQYnPOBkASeWmNzhuVrKVSJuWJwpE232llLax0BHLPOqbLNBRnyvAAKoRF/yi/ZoGCFr
ijczA42G6yTN2eRrLTnI41LmZoWerFq/RbdM/sDsx8oUD3S8GGPLwNfgBN00g0pnteeixhW8xm8y
BT4Pz+P28mwK6OcuTYDguDh2bOfebV3zXU+jVLa1etuq4yFbPhHO0d16HqrTgU7QRJC5e+ApbIhn
eVR1Av6WkLV5rpmKIMH6pc2B22Iq0iF+M+ctR0lphRlpsiBv3fBmbPzClVOeI8CX7iPS3yCUx1uZ
LsQ+cGYu5x3WH9uGdZOlP+gquSV6DTCnDFHHyA4KWDytyxZprvRXx1vZ3b9D3ZxbIz+CcWUz7Ljf
6PrWP/UunFiZlDKoFTqvV6FI/kOpC7X1ruOuJETApIQ4drukQuKNoCoQ4cHTtz7TrB1PoKtv5hjM
VI5e10+gfkJUezpz8vvvn8NrIvsCnhY0KkY3VM5rx+WB6TZIO4LbGoNfQr7KNusxwzqfKq25u0iv
ydxDBCmpYEFEZLEl7y1QwtSjKuA38Lo01g6ikPDMl83NvOLvEeSzwp0y14EfN3c42tELf8tqUP0I
QGG+O3Z1Kh/SV6dOoz5n2c3uNwxxf/aqnsE+3pdI9imi0atP6Lsx3zUVzjPxzHFwAWZYz2uxd2Wi
GPK5QbUxuPvPNeF9xkiUq9DUAMaqEwH9Cq+U7TRWlcORkWwcGv/PxnI7UFWHimxG/T1aLZB7QF9A
QuY9/G2lYo+LPZvvOIWyYMI2eU6O9yED7coYfxfAvmQIo57ZVxWnc2hf/+b2Gk0WCC8G0GD19T0/
p8VRSQ4DmZk7sSrx3HA8WD6TEujOMk7T14YKDvUGDRbbIhpvXWli0Ag0orY+5z8dcDShxwgEUFYc
U3HzkQso4GpmUTtbmXqn/b/r6N9XGYWppXxv+Sk1u8sQbOU5R+dp3N8ycqAVkzAXD5YIAUllD3Au
eOKWgLovriRmwclg7kaJUu+Y4tIL8TZLpZnbf//pOE4a21bhZBRk2a5tAeYutL02/8VYwVywpLlp
iNL4b2ZoWPCJiZXmvA06lDcxONObqRTXT0iYxqjUMzVhYQqMu4uPW3QsEYS7mrmd2NEK0OGQuQgV
1TehLALtH850DLGJUA/2te+nlOLAgtNItVmnwX9rg73C8rRPgN8/uIRjU8UHwWY0gzk4CHCQ/pGy
qxvJJzq1oVEC2NbKEYmI4X6EKm7f+WNx6UN57G2QJU4i6mGaTGZsqXBvdVNdHICzzp5kw7S7LvWc
zEjjkfHutkYgin11RoVb7vbTdtf5/LQFP5eQBMz87Mi6qRB2/Ii6X9zbWvDDbHRhkfHdKlQYsJjl
laUVAcFU5B8QQXUwTU++k5nAhquMpkvIVgnZL90P0LNHmFmWpKL0VLR4Cs9OC69OT7g89Doxli8J
XpkhF0hEnMQfx4NLwKpgFKm8K7XhG2lNRYHzaUI3X6oKf+kIyTewPMrgXJ/gudVvNMhGPzWWgF4Q
aTA+a7ApTVxiJ2WqsJ1rfc60wZNr39WOlGgsN0EAdM57s/VQIrGbmwamv2jMckJRbM7xPfurzUfv
sDe5+A9AJkqctqgIP8G+TPqMcR9ucs1InYid+yWn+rIQlvFoVTNe8+bKb9okpZ/eR0qcN+8RMylz
J/EwBBqrAPmdpFOt9g6/fG0cpnpaj0VcNMpzckSKaG6Huxf6Iwz/JMFsyjlzHwAKYq7s1zmYbP19
+TM776W6ynGZAGm9XPP13/pVyUuODnw+uxiel0tlvEuQ2FRYiGtXDeYzn6SUmWgPi5ZjOydvP/Rw
FS068LdCYYA0iR2Q0LUwMsygWZ2WvjgP234/dJ3+hr0WEhkF0CZBX+CvbIjiA26yVr67qLJt127z
8mTerqUz/SeNIGgo9u+3CiZhtqUzOe98H0taN3sc8LaDW3gv7j8ZbMP7p/jBcZ9muwH9s/+WTB+5
QdtNmKXQWsXfpSRilc8CxLZzuOo1mKdiOE/gfo5Ji72yNqdvzb5aCnWlN35jyPYTpd53j78AGzD/
6qnHnX7v65Xlv/10+g3b9y2sZxF8fcvQG7mLyompk0GvWmg64vr9Qt8JscZKkm/qo3OLAYG15dqn
gNt2KTITjZi2B5WeZAS5HvCVoDYqC2alDpSWdXPTcuU9ByVF2A007HjOvrQztj6zgmPX3dp5NDZy
lyaawoTCAe5tTJ9uML70qa+H9t2yOQRPeOtoe4InEECQu3hVskS657LlrqHHlQlZtUnGNis+GxHF
OxG48TSSeCOUkuIrTVamwiW5pWu484EYFKCP47AAi58J3ssQ17sSNHa/CSPNlDWjzc+Rk111APgp
zu/oKbWW9BVzHhj7bZfJEQepAtZPqbG8V9CW/qnVDs15eBXhLUUUCON1qh2dKurstpfl9h0i/jE5
/uOIFy/EzpY4122pk3Li2VaAgRt/RFLIS+zTa5TbxkGpNLIOYY0WmzBXqyEPKhYlUUiXXUqJ7aN3
PwNKi3Zhjef1zSmfDrvBExZkGJq6YYGA9wCiA/3brcZf3qDefSP55ICsD+dUt+v5rW8k/E/G7lnL
DmEw1oKAur57vKu9Rz2GPN3k2sNV0xvdhOSUHH5Jh6UxtponYCKPPwxF6ubE1x7vnJJcNwXqzWA2
JBqjWaRSWqHt239aDeXObhqrVCCrqlDmxcGtnxIa5Amjm2g2vWQ0IYwAo+9BtFJKviE4KtdXHIPg
R1ljbyDP77ZPEuq4X4BmSFmeJFsAfrLc8pYHmkFdo+P1MxrRcTddM5Os3hkHKXir1EtNNMuCoPKa
jT3qv84YHBAkw6WjZxbBfic3gKmFb/lmSFaowSIgCMRQuZgx5QixVDzQX0a1pzy44luXSJm1XQXX
SKGiXG144d7yS4P+hWXzFJ52ZFIQHMca0+6b8gxR2On81n8C5k2e9qZYD1UENFIqIjwf/s32u9/d
aU7SysZxy0vXXVqBIl5/oDsW3iz1bejDiJZ15N3FikbPzx0Pi3i0WMcalcjAfx4j1DD6HKF3ssVO
Wvyg4F5QtkfHNCYU6MoSH3bjnzWGyDZoQg7k1MJ0e/uAg3lWOYvrtQBDp8s3h0zl+essjqSnSR0E
2GeRi7WBakGVxQpx+6Xq4jQSNb8lXxw39AJ5zViJrEhfz0Vkjzj5fPM6nRTfQ/IWJn/ZSHr3J8VX
i2sYre3VeiOAJXp1viW9K4WA/nkoOynW1okJiparDa3BT3QWXvO1JbEsEgxU0vI9rKi2I3aENwzf
rlDlrGXYJk2UsaPYm+E16v2LtrYOHxMiCmKlMneMWx+CRgBJVsJ1WlDBaDVF2flCjifPgECh//CK
aJJnPsW5sqm1saXwsEqAVhYj3paIc7/BfaaGFh2FmKnmt7yUM2bqHxiU9ECNa/Sz4E9Aoz1b2xdm
qhODcj/axtNk22ReuL8RsoZTup4tPtQUE7f//M1wQksbWRayww2I5XZXG3bI3UFIwMM4RF/U6Uj7
PaNrrprjxoxcJXvi6ex0EGK1I6BNkgL4JEnjSZrWGG3B7Tmbm7yftKbhQacG+ur+nBqxBYFgspOH
8eCvT3T2hwQ1uykya/6bRpKoB7AV0kDm53R8JHC7d3lq0oJRfWYmXJIfRxC1xBUD3uwc+1H9SuhX
s96Lf5R1I99CUx6SMUbF8R8sl/VxXS++V4sJCQCtZpxFLlLVq+WPv5BLY90ZgMYIB6boU2NMgVER
rEWuVMKG1pQS16OajCClD6/++8KRIIwJ6dhSJ76rUTtIrvW/iSNKd/zspPX9PWix37PH74sCDMOM
g9irzaApMm3CIueu8l85dYDcUf9jfg4LTEroMnRB0cI5TktWMn+Mf7AzgvRwfZegs54OfnibW0Hl
emKtMyBseqfusGLQUcsQKmTvGbtFPYYwL3IxLrK7heyrI9XRl9QRnZmqR0FB2S9tFzf+LNI5SEwp
amoCoMTsMAWM+VcHeCPwplwwlxKO0UmoxfkvG3fxpD43y6ZKgP8zsDV4MBESc9lwBFte1fg/4c0I
lkgBikTSDmv2StMK8zJZclaFXNCSTMqSTCX+ulErqIMa4gD0/bMOJ7V01xEu7ChsHmgNCIMZEZWP
4a4stK2uTHOaO2Ghyr+lH04QimFgX8dCuVoMALh/bon+VCSXQGUlG3xdQLa8q7wVRTzukyrrNBkh
6XkXHNDkgAiMZvwGxt0luP9P9XUYLL1jF7je02qf0R45ntUF91TZdQV6VrTkuoLKuH/ESbWyAgty
Gh/yRSwNsUNhpgttlp65YFRYEgmItNtk+oGb+d5Zov6jnlaaoeLyAAhMgGvcrxoB2LUCirsRBfeh
Kc8cxAKJVH/Y5Gv+UDkK2HO/036OTeetKFYtBDkzrSKQdikj6Gl2dp+vJoqzlUA3oI/pdHbjoKu1
o9VfVUn4ZVQ0jHLwSVEvBB2b/OPsvIw68XNDoSbt95hm0iXHOjcoHlRsJ/pDqsndgO2P4Fo6zDol
FHGcYRXytNcYQQ5WHdW1A02yDVj0v76OumN5y0yECYeMF3nno63dsytJbFM58sbzvJD2K+MPTctC
uLjLJ5ntso9c6kNei1g53Imf23XgObYCOe3KK7mhJrcyM3JwVBVnfyDeeokm2xAfj5H57eSHZVbe
rwdeEFvBPnrk12u0pgY16gh2u+08mzsX2fx4PW0cgZM9XWP3GdftVaWFHP639KXUHK77T2g5ehDi
UH5cT7VDhguo38uwx30aN7YCHcP6JUnKPxQvNKD7GzYkqKWrr8uu34bbryX06uHsW1NnhXF7ZxYM
YJYB76L1o+B7j40ljFKSoB3JUzM4sOj42fwXKrm3jBoaTBAi48Xm9L5+dUUraDoEGTwuyrDPECSj
mJ4QN99Mwr/guNJT7LSPlVWSoXRCAxc2lxoReChp3q8p572J7/2O1+brrUkGhwiR9GcNoi7b7SeB
1uEI6rktDOw0YkXL+psqbYokfuVuK29p4k5vtdDWo7h+ZNAicV12MhVT5OFDeDlhoY9BhC6zZNKO
HV7WiPs2G4NpwGK6QznSkacCPbZ+gqVMjFZGf9BTUO47hUEUnfnGEihTjLB9fMfQnslWsO31qfHU
faurfcxjf+q+B5GLQA66dCETeMVQ/xCzaJxYBXKpyL81ZifWNimSD5kK2ux0Y+39rC/XI061EZwo
opR8CEw0S1cwLgKRiCjiNd4S8GP/Oof4NXLVcFqLDCXtJghNHmjeTwTo6vvlqhl3553sqto3BXxp
BmDUed6yCEszuFt0APus2URLLwoRy26TxkwnXnFQuObtNCoHb1DYyr41DixItH2cVLyPLfFcE7PY
7B2jh6TDKMd68hnpV0v6X5N+Kblm119kjyAvlYs92ze77fKDZu2w8ivBbj4Sm8z8oox0JaMHYxNL
XurC2RNGDe3r0MIcHjg1RJ/HpVfXwKG0RMQUuU8sPAjkT5jV+DitPS0UEQxKepREKh3mzR6fiBWH
IupddHFIt/uynU2tFXk2HLFalzDxkLL3/tSvrAoQ0/K6PTE5vVM8VkCNC0UPwuV1Dht0mod+xrD9
yxhfDodQCsW0mdF8zGhWXum+HXg1ddHmW+vkp+bWMcdofR60qr3mvWBDi1tOGviLOikOvk6uizO0
byq40Jygz/TmSZy0GCPWzXDdIT6l6ZxussQxU3HFJLLNR5y1/Mbq4cwC8bNzV0aC6o2Mx4+HclCL
FP7YiYNPgLgKfmhhXOkvWQ/bfzMRFhHvEsloreFEWGEEYIa/NqIn7GywDxev1GcN1WsXtNJzGB08
OxAtYl8FM1hMnrHPB/b6gFkyfi9tIkDJjuZcrqBL9bZj8ImKX0YRnhCK9IFWsfWXXqEnCVWI9k4t
YoqmMqE6EqSEpUCjcaHmNhuWwMy0ZhgfxpEmrqWEu4xbRrHLqo/LivOLbcK3Snr/EzUzMwbWptsV
uplQ8UiwnT6k0keG1+sOqWCGAs0qoqZ5B7Cip1Px7L167+mjbV6mJITXVYkKrJiBuES5Ng0Efhbf
fY6f0sgUF0NWUwkSb9CUmbnYQbmjDxCN6IMTfwU1RfX6H1YOB6MFTQNWTyTL1VjO67f2fNr/EkVO
1Vkses5lrWdg15RKuPjyQz5vLXI0YQCidxbIPXynnBjiXk7omEJIcJjnPLmUq9dYc2rJX3l9g93e
yzkhKVm9cYB0kJ20eqfK9UQrrIeQFvgEAh5a9gopd1CUbiem58qsVH1batZOh9sKFPJW7mt6NNiE
2vSEwkw/Omih2AGBCXJEVf93vYqbkskRyWScKxPjfYBa+XBO0cD/3M4ZQncfSDBUz1pyHWhr41f9
XUA999IOVoCP+09Y++cGb65LJsqgcnzoYPuAIrugOz77qq+K8vMKrp7W0KhxHZc0GA8Bx+bOQBLo
iVFHyK61A3ziZWbQP7PfYiQAg0/y5L/uzZ8XCgXfhKICGnKMkROS1XD9oV169Nj6Zup5wcWUrqup
0s/TeEJjHL35epV3RpU30AGYW09Lvo8+42VOJl6TWDatpad+au8LBz3F1P7cJaqECyQy0j1zSrx1
f11LAOVQJLKGIzicqFiQN51BSA0v+HHr5+21vPRqz1oAhfaYvEUs1ONd1v7RvgEwgU45jf7OXfd1
OSRNrNdpqmhM9XF++/8ZERsN+2kQKWu6j6pR9bm9oB8a7IvyTk3gOqrzlX7Oh8dEl5+UFVd5QQf6
InJ7BxN+Rmcft2+YVEye5aA0WI3UByOA8gOa8aqvzGxMJ3CSSVHeIj6shFcXMXR1CvpyHdNMDkzF
HNDAlGlr568sZm6R9sM/wFtgWL7Fcmgkc3QLWT/jJVLtZxZe7Ixbl/hdduU0wqhe06Nlzv6qt6iL
EckcukO/Ot6n9XPWGBuy6+N0bM1PIFe1wGripIrv3Z/XfkYK3JpWp2I73t8WqR48dSOh3VeleB0s
/mI2+mLNEVjRQFsHil5QL3vwVof9oKDp+qjNyoVgvIWokbn6nwasnPDo6TZwD/Q3EAGuR1kvbQK1
WLRlxiMKAHkOHsU6Dh33FM2plU1bq2ulm//BnFNhepmK9j1rU1gfqycc5GVXAMa3B4OeZDqrDDnP
zetCJBNCgwrLBoV1WW6TFOKfbsQKE+FPJvpsUhqiRDdw8yIw2MzcT+sK0o3fgx2e8HIt2raYaeiT
E6ts6CgxHOandedrAf9AtPRrc7Q50uWZiOXJGoo4U2K1P6sJWl0nbuxt4krtKTEXXzk1y3MzGxEh
ZCYBnk19BK2E1zEui6zH8kRr+R+T3skL/O6OS2zPk5G7JkOaEB4xBhdnh6B8W7FVrsk7IAhCNBpx
j7DZ28hPKmnvSdDQx4fRW+KCq3ogPk09Snz1m3DR7ZnCDVd0UjBKpJrGpqnb1W+dOO0rnGYc+Usk
h8dLxzS0bByJ6/yzO7zHMlSj+8JTWm/qSXTXN8WxNs8MPZ1DgOQbTmwnwCMREUWHlsI4IMgItHgh
yi8QNtYRJIfv8yqi15KhGW5CjgJfuCQIYgeqf8VF7X9rn5/jlCrIIgSb6Xa3z9pUmIBZedUJLyS6
k1ujI6oKj2yf4SVGJ6LKAHawoHO3TirqqANaemqGQTCRAgkHB140C0mu1DuQyBxBPGVL5GMz4T71
G6YQNwXHNN2mfYx7IOdSQ3FIIvIa4uCQShL4AJLweSGWsu6oX6CjTLzrNPmWvdxGw3qmAD3Ij7+W
gtikoBTxTfnSCOiuEqY1nE4ZVy+n9GZehOdPYZz2SJdTHdzo0Vp1nwySHmP9DSUTq+VWQ5vNoR9m
zBYPCEmh7YNet5K/A5ieTbtENJYTMd0nYy+u10sSW5rsALHiwtiwOSg+NgvZOi7zLiqzfnfblhmS
g3ajzjzmHU16cUce6xN2bl9dOx2PsTRzbjbS8SRRGHmVaEquikiC0iCipsEdrTsJIc2uZ5tR5AGz
zNOhprZWfpQK3vPNVz6eT4d7rPnmSyivoaYFPk14PeNx9XtmkOItkWzc8j4dbzIfjgRai5ptA6PI
FIqA9oRclSWis52gXpOdNgRR5Afv1MM8ENe8GzyxdHlSgMzvMvzBYV3ZN63iqVknMVra/t/SmBjb
4xnryWZ3JruoWiEv2PrBOGoeZj3ocrDjsvaR4FdxgcFKO2qU9CfEP6hS3J+ySUtGVOnkM+kvMv9D
/aafhAZc4JWEEO2PFydfi/SEcPtJSiKIe0IEpJgkgWSNqHoj0a2lBj+HhBmXUBd3ZKJqKVx6vZ78
T0l9JrKOjyIoP8I0ElndyReGeJntgJQHrqLTfbJjfOPBDOV+01FB95qGry755QvIU/PmtrrQyWMW
NcRRaEJVrJRAHOnOT4aoKkwgRLKg2X9czfeVkT0MajH2oAhHbOKwhfSDi1CHj+MgCbCheWH73Z3v
KOmTzlNEVrV644V/k0U6xZGMjwu1Le40miEOSwNfwhqI4ggXGIdahRQmc2AaoFYi0jdv4yHdib+L
nBJtLyGcxJVhbnU8pszeyxPt8BehLbTMdMCMatVAfSghR/q5+A8Ndzjy11IIIwBOk1W4eMH4+a51
bP8p+q1+VWpeDzCbBfyAk/KPKG/KJjN1PA2bHNlGNYnYhGxauPCPsumwfm7PGHhAtN0ey7CCDOSk
G5vLdC2ZRfJ4B2TDLHp8wXKmB8qzGGNHN8JBB0SQmpsRjF74pRTbs5MLcltzXGEW7DHTqh8jHoB4
XAOOVcriOjG666QefiTUYvwx4b1Mvq0xeNCKpeZuzEwmuQdNAmQjCxpGgnckdGNGO77a3IPtCmdO
UX21AlFdTRIDMyPg/VB8ZoxRD/GVlqU43DaSVSemW+mpQw2tCC/FrRPSOTjndwPI6skie25bx7AD
VUZ23gBh7wbMvgzzlcfX3cGfMtiNKGs5cmsqf+R8laTeYmD6dRIEyB18YYE02iykGSMT53XKVwvG
j8j3i61jTKUjO1/4ncEHj1+/0mwovYxuJ69y19kP9mJehQR3B2C7bAeQ6yBn7Q/g90dxg/LOdsE2
BFgOxER1/PbTy+URIqo6cJj91YPuj0pqQuva0C6mi1LEWeyCrjlOe0B6HCRHwXdCmk4/HsCsKjPp
C33l6/YIxekOyiqlR9SdQQH7zyZQH6uk6hGhbxyEz4+guTMBGeZIrnCuitt0SmZrackPRvH/lke1
4JmwL+45gl4GDJZV6HzNouPEmMVJsfCViBv4PY0FqpccTszUFaUQEjZuNV3kd+7eO8nnjQz9Yk1c
eFv7+l4qyIOJiHz1LTx8xRwsraQNrTuOE215Emripz0Y23V1L0aA+RoWp85+lWRxkepoeKAzBxYO
1/YDq4VMzVZo8L22XoojajO3KtTbsXrrDl3pwSUsNuPE+gdL6SLMpAG/Fg9NwQxOrJIq0+7YWm2P
Nb4pbsYNC+/ge5RFxaW8BJtpwqdLdbuQFoBpZJkGKSGixlzlvJUC87up03UEVRimBI0gpeSgL3/B
/W13DwiqSqe0R8GujEHR/QbRYqzHZ7lv6X807uK4wRCoieZxD8DeI+l+LXOL5dZgvAQA89mwsrXb
qxhvQwGs0/KFWJGTPWlwsDv9Zq524wIX2lakIwxBHCaMpaaJVSUG810kiMUqO3Ox9eYcpjAyolvF
+PDfqCQ707yVaT3rISJlnMgTbUFlId0gZxBeuLhQyFiNaQCl2wv/IvjiAdNvN1etMNG/86K31pdh
xL1chkc9cq4VfxtuXjHA/tdU81bnFBhMax1CKXFgVW/V5iFgTZNkD4MOvvsrCivJsKxCSA6n7el1
KPrjvbt01ZOF/RdBB9hV7fs8t5SM5OLjtsKUJvdlG53EMtYkxqC0DAkokAc47Gn6JUWj622kdySN
ktc9R29068jx2aFh3/dAsGzkPlYj+kOlJSaFGlo9zQAi3KzpIkf2v1e5lo9IEMlvolZAOonad8ih
1hmrUEWYK48JVwxC+HGoKePkoAFrQ7jk244pNaXq2dvtc0DUxlkze9dj7i6X7BW2xk0BNqqlvSxc
4c24qZ9Ye7GUdks5aNKydXjjGkdOdseqfnK1+ivv/7Rs/xWh4WuOchkCcFFSBi3M7pdYbcdTaqL3
dANB7twSRqt5CLhao1iL7fgGDkp1BQJoIcQwv3/3nBKzak7y78XDdRdzSWE3TqjKrU88RUiNOtNH
ZV3veAljluiRETnJhjsPJZL0tvbMfcj3khcR6kuv1dIzQPVA/zPoUP5qDEZiP6gkhMzH4ui6CWYr
9SOXky6KW9UZr+tV/uyI5B/6jrYwahf6SbxKJxDW7uzJEL0UypfFBBN2zh/VSBH/hJj9jcKYUT7i
mFDFVb8Jf+lPmu4JFfeb2WKzodlym6jnfVHuVABbRt3nL3Ld8vdP7nTgesBXr5qKBAyPuGW1itgC
jTaNa925puL8qLR4pk/++z2cTkxFWCoqyxAwFDzWlTynMJjqx2adC9a7fQR28SSIxSXZgGeL+NIp
x+XVu5S7J9B6/V0QOLu8X/h89kD/oZrC+oQzM5JVs6zVfWlFRmN1ZsF85Yw9aov1rV2OSM1/1YXV
VcNCbUEDyacJVJ5OCgzFemI5hvZoefCMez/4Acx+S5/CPRylMZhIhQvzhOC2Ws7SnvnYwDIcTKRq
pIyo9zp2C4xiE+XiqE5dpPspjKIroDQ0oebGExueh+x0mJO8Ss2deUoxd/AssKFfsIrc2K0+oMRw
IemThFZIk86rCo356XTFdyNM5LEsaXXKH9HN95T+B3MliGkD+NfB4d0PMpAbv/nIJP+DhEbwfYmJ
Gzh/06Ov/B7daYPIsd9+Cddj3hH0gGwPNoVUht86p8d2rPSf9EGPlL8VZg84i0ygnJePn86vnI7R
YDokwBVCCOiI67BLyeigytIgIISnes9BilKyJcF5QvCAeuqoiB0LjOiT/tTQ+jl4+vNjOrKZOW8b
CHwIchn2noBEADIjgyP5ccckRPq5Xu4IwWpwDlX1qFsFUqNwn5basG/H41FOqXilNIwmKdFwZ4nD
GnyBJ+5s8usKXuw80865bGjNNSNFa62lnfKpJB0G+/kV/LgnucxGQRiuKN5MyFmrfHwUafhKwHMF
aFl92LzSwA84tNVQGSVx+cx7HascSMb+fezxLthfG7ux/4H57CfLm4YMbVs4jzii8Kd14W1Ln9bj
jHZDbXAF+jPZMvP0W8ahDdS0yUawHEfQ1I2roL6Q6qygpagVuKGLZ5tmndQV6MUhlaxpr6XlZosZ
j1bn/XapXfXQyDFME6+j3ScrARPC0JbZBhLiMNKYwSXeAwnPSo3JGjvvDcSMyCDLdAPa+XNf1Qm9
cBDXK5r10n7vOtBJQDltMdbw0/OF+86ZgRJVjuaCl6mfuUKfd4DF8cPCrGz1Ud6SJKpCoshJFPOF
cztI2Cvd0CX/i4OZ95/f6WHqD4Qg3cDpruXvDzX72UOYwt2eWFFWUCxHgjy6w3Ser8FxLGDy/pzC
R4S0+VM4xiiLAsnTyKz9d9zt87lewReoBDkTFWL/G+69992aXPKLkad0U82kQ8RdXjaa7vAlRxt5
oHDnwMEKKg52dfUdGnUmA2krSSZHZG3bg91IAO26rTYlSIQOARAOpDpXh4dwbU8dZWsBdescJgrr
Gcx4+E9/Rs/tX6h+A0V5CQingwoMxIni+61q1vh0l/zfANznL3cFM2P3coLFVzi2/jokcsY6nAbb
MqiIuSXIS6gkJk9cWHstTHRixdHZf8NWwBBSTVdAfa2VfUC3d7efH10bAcidETwkJAKnqEAAE3PE
rNOWah9VKaVI6YsyyS0IIsSdQDUr9CamNiDH/OLN913qyFNHwL059XI2kAxQu+WwiYoFw5Z24Tba
ssFV1bkPZvJMkN36exuqHwxktxEWpQ6rNrG/Z+QQNUnY3aYAb70d+EFp/EXaHkBiTdQFEm274QmM
ih9cGV/be+9xjTjaiDQdgcn/FXjFZZW3GGU+EjF2Kt/+IMGu+eTzzfIIuK8fYjrwDrAEPTdadIX/
1D1IwZdti2GlsGOmoz1yKqaF/bKgX77gDxNRazqZNcDMuX3Eaj37uv9xejJ40jrtEYcZpxAJ4eKm
7QRK5i2WfA45ykH1eXYhZ0ylxaB0hAyITW2APrr/r5fiHoVza9azBgRtCLBy1H6arYPz6PCtfW66
aRtlDTT/4NS2uIAugWF9OWmXdNYph5UG3BGdxV153M7VLbljAA0pAIDvMogiMm0lVKQcx96Nt4oj
IC+6Hp5a/PlQLYRbjupcK/GevIDeaGPyzG47+SFHv9Bt/GnV62oBup7VBruRZhoth5J60BoA8WJs
hWcnhfsrxijwO0TEcYOYw4GGoRyUy6jx0SCo4t+AARgAAavWtBJcc4iS5Pk+lWZjd78s7eF7r66D
3RXJPTHU6kX47Yq3K9P0RQuZhC1tMqlq1ifWKQ0dUfJ3fXk2OxCZtzotXhIDIW5xpQkUA68Fl78S
mC/2f09Ch8zy/9/+7ncA0w7QqOWxAEmYU4fvEO1kmKPSlJ1UR4jkWzY72j6BTV0M2A5XyDYBemXa
ptZoOWVl6pQwfoMuYLmAIZhLostPvRfogmrw8su2U/7+NyOi3i7f1Vshn1sDfQNQbGId+H0G3xHR
4HN6AJdxT6lTiM9VwJhBL1lDLlik8fPXWjUiP5jIfBV5UM//AyGDLEMRMHKotvZs4eUOOWskFT4P
wTNOUTKoRonUhe6elwounTSHeO+qguIVcfCEuL+ufFslskiQy9AfmrzkFwcp7FcidV5gVbcLE1/G
AZE+TBtsQQ1/6iHussZN83ABjDjtVbCh/mZqeKzCnbyvYWLNxCRUBEJDxuW3T23PF4kmnFeZG/i9
8WTVwWg41kcGClj7qRboERYnxR/2C+ikDeZPt0CyCXPP14zr1UKjh/8kdjVjoZ+DZLs9zeAHl1vM
1DduBJgzMxmX54lSnVfnnJu5eKco0X9h4319sGph1kSSvSkjF9X/2JeUCYgEd5V/q/ZxL7ExgISA
avG24pGQT0+MDlknOpGmh23v5F0FMIakmm3/f4j4x5E+CxKhp0Mr51IQL17Aom7PrCOC9APzjxNV
GpXjn+IVpssJ+BeaYzt5KqpamXGcfrD7b7A+8GEJuC/jPVNWsGoB/d445vfo6UWLP1HNk2jpB6U8
Wslr4g2zD1nIPvxLLPTYi1ShJHGwIxKWfz/AeY+fqL9S261e8QEpcDalaFXqj4xpshoCKT9lDZHf
6RAhpd9PkBACwr+9+4hr7cSLfmTyUGZrbFqK4S9NwVPcpLEbcicEu0qmAgFZ4chkxPVylJeVqrgC
HE/nkhpwzCCGDG1X+sC8Ly0h1/aCTl0pQDm/zqNOT3C6pKFkJz4AUTzO7xXsyz8j7l1l3C2wCtKF
Hl0+8r4LP7nEt26D8946axkjUjoGfBB0ax+0wZGSryYdJJrONakKGjsTNymUtY3326Zg3d1GHq6g
6LhDM6rw0EyfivwRz7KzlWlvc2WKsWmrRDCC8w+qHQMIV7khMPtVfqTzjeXnnjwRlAwKpH2iy4Sd
H96Aq6gvTLGlgGDkCKINbfAeCKbgrmTfhq/o8ftlqaI7l8z+Ka44sPwxvfMzS9kFtZy3J6ajOViZ
QXCbT23QWR54qmHeHVyn+jRgChgmMgGk5QFXD0LWiXAlfy9RdRqQpCbvt4y0MzUqeUZOGCxOXZzV
qMNVZRdtx2KZLHBhF2PZ5pQsDOb5u8P7eDbC6pZe5teQsNnBquT6/cjhB6i9RU45ns3A1EMM/6OS
b4WS0SWSTHgNdltvBqA2jvtYivsBNNoJ9jp3St1JPCAXd0a5BFxqsIgvkLVWBJfGQvu7xCyRhhJg
Jti3+4/60q04YpHhDOMYXXzu9y6F4GYQjoD2zITIA889HTcj2y71NqY+46WKawW32jchXzGlvnhB
sV1NGvUwBrSkdaj3Az7owG9abCmaGe9jmUaBMg480OdBJxGHLud6erihatt+byBAAeSAzHwj9sFf
OzVgX0hI6DmdGwuqBVcc4LJJ80wRyv+ecRGjFgZb7+NA1U43spV5Zb6cvrHh3MHQNtPaNOebaeFU
uAGhGoKwN0X4o6nHbi0lGBZQHNEdtAkl0kHj90NpFHxHRyu71OJYvlyNFC9xwyDrn0YVvnuCzZ0n
FV/gFw+hO48IbJz2MhqGB4fA7Wdf+y7HFXfbYbRnJcJx8pw4o7WXmJx592CROV/SfAQLsRzijgjk
vEvFDlPGGdSQvjpmxL/WlATPknFLwpXOYF8uhtDYknT+2fDkAJ/G1EjtFRUPFoDcaF3DoNMPlMbG
HBr44SIR64nTPYN2UvCosh3tq+1JjNUlOy/yHTfQ4kMVrgCsBaY0hBl83y/k6Tv0ynRyoDDiuxFF
qgyGw33SKaHSh7DAB3tsFCuS+a37k3JTCI0aJYNcW7qE1R42/kfRbZMaFg/TWNo+p2MdUiTfYLnI
U62Swyno40Gz4jfZtGoSt+lDZnSloZ0fwkLclb2HbdgrwsxE5+FxsTct5MCIBgGr5qQp35UE4qky
TcT1WvDGRxUYgNnxa8G/Wq1xReKiZ+x3UJJwcxE38SmCCK+jcFDeBPgthzRvb003PRzMrPEA9TeD
zVNX1eO1lYXAWvBsFaoDgPHVdChXYe63rFK1z3GdEwP4kXcL34wi/guXtVdKP8ExiGIXdRf9bopT
mpvj+WWvrvWj54R8SsaZ3QYzckfysVe4vt6uAh6JWCq2i0a+VvVLZgDPlXhEZyGicLnqz1fnF9sZ
FKX++Wi96vzabXb+LVrvxbvFAkKrhG649Oa8xfV85fy4X8TjTk5fhAVP87McJ2yBwFps7Dy/33Cx
4R2EUoEGoqSwvfvNlkZ1aQFMKREfCcPiJhtYWIg9S+ZGHhHp90llVHM9qY2RVLtiVZuENYQL5ftu
cBxbac9oq9b3g6eiH/E66rZ+P+HLr0VvTE6GgFAZbaSyonSH/RiQ0RWv2DTk/zA3nCWsZeHWj7t/
hhm4B6aJ17kGvbKXJsba0WlKpUwgJLlAANyCm77WopA4vBCGn5HBbexxOe0ffgzlH268CqnL+1aF
4wYgBwhOlLitJ0kukydJzVnbGIGLM7Ka+8XSTwmD+dnteDAlMfv517SqNXTUHox5F3vGQ8bKMwp9
8mCSJtgaw7vpRJxkWtdva/aU03smU9cQZa7d4Y2Ky/J0dxraPmSjRuRTciBWtPM2UGP6UiewtFn2
CVA63pLVmwgO6PfH7S7KVpOq8FshiUCi5YVwfRRHnDyuaIBQwAh5AePDfT2/lUPLqFwxaO39Al6/
JwvpuoEalfjo8Eg4/7+GYeu29y/1+yGlFbBZPHKGKD9eiO2OpejOnQs4kl4EE9rKZQE8YRmbFTrC
f49ZRi6HsbSDe5LA256i01PQRp4UdET2RvEQFkvyIrf+gmwx/CpdHoE80PmLMe92r4LayFbXOvCY
8PEF0bfucyfFP5NvH0sk3zu52zO1aeQ26d81f6YvTcEQVHlLAl9Taex0xt3addnxQFwwPul2GA3x
7OuTVFEjWZsh7h3qGY+5G8LD4tkHiRxH281MHLWJ5arh9TtnyWV5c4t8act75Lfkw05OqKV/lqFr
2HH1LQvfQZwzuWwUgoctPnWWMVBE/3+hnCIEpckH3IEDxvaBfGiGgzSI2guuu9rogQmmv4S3Pwpc
aD/vtlXrYCBx0VljAvo/2EPehAaFDbcie14kMDWPLCskfXpjuBGHSUsojeeJbTQ5kmVxliS6Bbvb
jlw2+HWZBlxJjmIP7iNnX/gSQp5fP3/sSFXtU0Zk1Hzc5JHnH6Qo/v32Vmar8jpmnDG8z4tpwizm
CQE4Gc8rZL0HtPrqmhxHp8HAzjPZHB4VCLq4mYHpf0DcEsjit5fV6viQ6tJmwLyteVMTQO3jMPuH
ufYeYK4pVe7llfe22oZi0whAnCWAakzcsS/gx4ZDdN4B3D5i1ThZamvuIHQ02CcXhz9qvlgTxudo
HosGpFLbpAVutAWCkjZcpYFXnhe9GdT65btgY4PwR58nzjKWgSHG1OPjQ5XaweZD4/3ZHXqwBh0X
6lq6/7Eo5l8rKhDhCJaISHIcwN3aIGm3vBUPa2+yn5eV4uYLu+j06FefoQ6wHoOefwFY9ZBxSK7f
NLfG+cvkcW8GJpiiZSKU0IRuwm6EvOxgtbxowONNy4+uudufgSZ7xZd3asOsvuuXZQgNosukfk0Q
o8QR5tycskmr0RmKOFVpD6K9LR+x1S1RzNkZdXfM+dVDot2m4aN76iRS8zAztssPGQCLvo5Af18K
F16wUevewpAQ1wOkH6zCLe0hcFlH5aYaS5ol8VhxULtH0aq2AxFheW+KXT4Voc+yRSE7F+O5RwpK
6LBe2qj7/ZJFOtZSFLGonzPYNiBQ1ZK6ougAdxjab32ClQXSIvO8Pa5zXG1t/9Nk6UMQm9ENYhEZ
X4C2UrXAKsvDKmlj8MjwLPO6ix+Yb7PRUHAVWfql9LWmjvLEywnsi1dqf7syn9DHiWwRKzcoN3+S
5MkuOUP345HhpVYiDykFXzKmLMhrxgYGoj/qldEAV+yubmIz5xpbwWJgE2xNNRNmP8C7/yvUsoCC
vGyHcbZaA/wOnpGoPQt0hFJi9u37F9uQhlq62a5zdnrBLgm7U5pmWZas8AOf/bZp1eZpAhFpRIvu
3vhE+LmJTCm7l917wza6RQgZFHMogcceJx99NKflPFqtYHXNutS/v/YmpkR7+V35QKxbEJCbgSBh
fRDFTexiGspa8kV4qZpC/XstTx1HnzBwsxadu2Jswi+8p5syjIshYaUGmq0AMBfJwvTAQdSEW+TF
VdObhAuJyuZBRoIs4PxnjZ+PU4X8KwrfQhQCZEu0hb2Mc1iz5dGXNTNkchaAeJkbe4yHo3p7ecyv
chyFj900lcDfNvW2tcXaOYqhkosrtZyv8Pro+JvkYm543Bc4eImOT/w7dj8vF8pyj/zl50qOk5Ib
eXwob2iTSEfXFDgHHjv8t2SdYXvGUaK1HyvXKO5SS5rCFUzGo5R2aAQM4aTeTQX/QAk0y3w9u1zd
nvJDuU8qd6Qk+HZTuwwes862/ZoIeX+Xug5GOzg26Y0cdZLhDEND0FjBjiRTC14kcGrtUN40uHnU
NPjtvjSbhavZV/wLJNv89aF2SoeSHb9KWnjNwddX6TW4jBPptM22rlpP5WWH2Sz3Idv5N7QqMfqk
R2wDZuhBNikSjAM+n1fueB5Od0U+ZgByHO0eggXUxHIgi8CUiEYb5TXhjwzzJFhEWaPUU2GoyX6d
6lluM6EjZ9GQRAm5vpfG6BrSWZkXpH27B6PSqlvE1G0u2svs+VBRqeoTZD+xT1cJEaeV6y9FLNPO
SowqQnYymJoLpcc0MSp5dqOKEA8fWynlJGItxZ9GcUKzIQTOmy8hQv4fA0v0sHqYs39JN+yEciA0
4xqnnLC5gh7mSieU20egmZUCy4G250OTd/X5VNZvOnsxs+3vEls+SV8sO1BMSG1JNjU/LySkF1zZ
Z54vfTExe4DhlslfHn2/nskJPlX4y3tIsvV9W3fqoVAAUMv5TApWq9stUspV8Wt1Tqy8Mt26euGd
8tfEzaHms9HgPZDGNfSeDoQB/P/tca+7XDF4A1abhwufeBpPooDCyBG8haAr9RuiGC/OI3M7Fo7U
IcHOBMqiw1EWsiNFhhsTYf0jnmwx77+btWPaoseNvE7I+4vEoyv/rw9OSviKmLWym1BbFCtDumU/
u1eybngctSKdLBKW7CsfZVALztbLIpm2drRI2jAB8kMKo4Aditx4/9sSXQQ1NYg4VSOFu3dAF/Mq
W02TBKPMHq0hAGXng9+YopfDMG25RNS/R+bAiOmNWRg1TWHH9fV/HSIXt0A5GcnMrG7NXcnCx52p
m+5rSTEDLg0pT+MygDZG30cAjOs01hPBsmCNPSEwrtHX7Rcn2RwF18x1Z8gHZWVnqdRO7dKGIoel
t3zKkM3zi49UBtyHxUVUqktSOUEJ/LULjIMyZ3QNa9VtYqhVPstAQrouwQQcUW/crX/JaLLQNLLz
3nO0zwhwWBoa04BBt/vkf4ldQq2sCVpyYuMFTQJWl779K8KR2FUeM6yl/QQRVGW8+VZ0w33kXJmm
EO8TQ97OO20LSwjdh4b9b3HIDBUpHD9dvqFf2ZUtnL6s4frlKG2bJQSzMdbzlWbyOfRJBPJmIh48
R1V4wCpAF3e3HutoADusiqBcJvyzZQks+3qpWp7U12bx98S6lXgG94QBU8/eoELfIrB2TGSrzViF
8vLBiD1jlbSh/+SKMl9CGiRgrOH0cz8TH7k0s5RSgTjzqaH3Oo5kpuW2NCCvYFphYbZmQvabb/Mz
F7Thb0IUF26DOSq/rkjkJJHaQjNX7mpvq0bImMgR9PMBAr2RJfIutujg9iVYeWTD5zhlPJZxD7qO
GJEiaX1Ra0NmtXI3IiZ2ygWkL81nmPblG3KCIWLXs+1eFXPY/0FtC+28Qw45eFuWCYnOSz9InX+e
ElLyvPj03OTD8E0QHPC5HeyITEPGZh4wMPVf2EtK2SX+cChA9HZTMfzwbUyEU7fqe3P4u+OTxC0v
+98v3oxbLXcsmJdhbS/C2Kvg0iBiQ7ilvQlUkzodSeGLmL5iAAuzm6j8VpUG9sEIbE194Cmq++km
5FFXS/uHikNEUffGCQH9041hFuqTqdaB3mnF67xqac1enUnZEgzc7d8ZUm5TcHtUKaNvVm8wFgjq
qI9fi1cM9NpirFcku/v8/f4NF6XiWxP5fyDIbXZ5a1hu11qaDaNjgw4dQpC1sFd+wHf6XTu9CcLf
P3ewvcz5+r+HIhxCkDtPiV8gAGkzfM1Jc9CIKkuGY9GoNlGHeqtVJWD/c/V01EWMiXMTMnwVAHKr
3XDtG0i6IeAPAFSRFIOoXpkWBs6B99zCsJAmqFnIAYswxZkMeVoXZ2CnPUhgUTFN3k/gJADsbrEX
iydDbhxPueBK4UqoIlX3AygxqDVAdA13l/SqQkmiSksIJyh9oleTcPHYj6AKaknUAwsHfU/p6J8M
SjQjnk6DECOXopCetBv0ogtf++70A2BtiVLYVXPHjS0NIXoZhZ9ark9JnaNp3Af/4/HNpC/NM9Og
k3vGZiAEV5QgbR7kMhpTP0W3YicoXtEDUFvAwHPOi0dLl3Ui/EYQiYuhFiICJB12aFx44L23wOC1
FKnm+o+l5ZnTgQYeovNzqlvb0Ut4V9cAs94+xOWwdBsk8XdsQd5SPglbtusWIgeYkMOhf3E5qevR
LCuYsgSQA3FD0rSJjMAPcASGY9l2x5jhYYQ/FS/QdPGBZKO1/B0nCdSQk66+3IQaGTag+3uyI9L3
qrC+A6hPaYfzJ/88AQ8qUKNZLzOFUIjLZjsL4YGXPuoZDBMAXLOBg5J+JT/i+eoIKzClRVGbFgt1
x6OynY8YdKtIgVWeP20g7tGZzEbF/sBy7QftbYtuwRirwfng6h43Xz7gbzeZR0Niq53atByoFhyr
7Nmg9gcAxaQz0ADvgg+PJBip/Ll2g3gydwRFL6unev3MfP6Gc5DbW/Ko/1jpcuWZdpqKuSFsTAio
ySqpo2gr3Iyuj0pGyydX6QrlmXqDijcv6HNQ/CruoTu+Xkh+aiesAQXrqHtz2awJdNt9maQ0J3fm
/K6ZrmT0j8gzbLgaR86kB6k4TNVWFSC/qv9lwGWqxAC7ul/0rOACEqGZGr57QSP4oohe0JH8zyqD
XfCiRSZMapIAH9l4Y/BlEtChGs3Gjhx33FF5OnaKWWQo5WMhLjKdAfL9qZtQ8muoc489CnwmjSG8
3wVw+ZQfa8bsETTx7P1YEdWEuSYAY7m+G1wOS0/ac3tA5dLmRCEkKkc3cW3mfXe27G4uj51Mn85T
vPblXAY1HCorynJAleevdIh7zkB6MbwHxB3gr3Re3WmKmOODDZC+qFcbsM5THE6QDyUe+XSr/h4O
3y+yJ+epYAMV8nMuHT5NoLQcaWHZ183pN1lWEGrkQZ4IOLSkE/WodapYexClKRiRGgEr1Kg+bM7p
DHf8M4VAgBjY23oUUP1fPyOOXeU4eHrRU/ju+VaPwtyTigYQFQ3hNm6hVSVBGRLxLS9ew9s6Fgs7
j4jxdapKM0Auex7QNttR9hbWlXxhtUic3tCgefgsfXZ2+Fdy+Ba2YuO3/3242zAzyiNfcVkc0rXb
e6DCjnsCK0RNkEFhf5E2Bv8mzYSX0ARIHDHMJy2WGCHdBDlt5+OSQc45EdJ1PeBmLuxHgAd/JPJ5
Ep4mYmeJPuiC0dhW9LR1+Rmwjb64uJxDgXYF6ZkSE7gPwgRi+NznM9NsXzDmgiRsWkSmuzxLCNlK
d8x243B4vnXdwZceNfDZ4E/LXljNXRQXfP/ykh66KKcaYop0cMN9uvbyZPjuBWsIpsaP5fzWXL6b
c1GDGRkeGIP0Cq/hwP4oXVfAAFHSdJ47AnoIt7tUlVe19gc5xDHdhbITCAmlD9fqR8pqdNkXxUpU
9xKUSV4L0UogP0/dEUw6VzgrIl5eBppt4A9EuyfS2vw30AxjD3VLfJ5mu5sIgM80Yq5j6ZakDKI3
/NczuTc6RFBg99Pe+Q8pNRwzHJ+E7tTywjx2W4D1liwGraA3NLI4Ec9b/z2udo0jsWvvTFbm5Wy6
GWZWRc1QPdtFwxtwQvxtFv1xmpfrnxuMgfQPfPd2ZnvIi3Y6EBmZ17HMyYXW9raYCZtLjq/wYEoG
lRuz4eHCIpqmprLUyDwJHy+XGUgTo8P6LRydHqXacH5enF0GWsyuIVd5BZ7bhkT8M770ljt9b1HR
KIJl/iMkivGZHUa/1PnHZFMGgpgu1BeHwdFeOg6hNQTwR+Mx2l80wNYtfC3azRYMExDR+aXJ41zn
cPT9h9XfQZyM96xImCeo6pcufHTuFTWa/yfpuEYRILmLZvdywSqbo5fuFbPAoVQhXjKT7wXsrfC2
3OFf/z2+aogpeLjkc8xRt3O1YL0OwI3ESVizxQwlESSgcvQo+mRNUhh6gKk/y1AHnSF0K5bNY6Kd
STMSJRTFgLxDxwLWFoCY2ra16DBKfjr2BR/7ALIe8wnVogClNV57h75y0gS2ZNMxWQrtbrw3++Mm
sskrpBWcAG1iOedKJAIrKZa+5LFt9VinWmVv/IwdfAwvvNZioRbgVYfV9xtQHYx8X2IpDqE7RObl
/KQR57+0Bt6nYF57LeWfMspyTQ+s4JaIVf+ZfNa6xsOervolBE7sv59C51dq6d5rBaccAZJwcNxl
WfgiD8jFSDlbRhdXds3k+d6tTISTZyoZ+cATjBxNlBA8jnR+spsYfvCt5uY1OtIwOrWPxS1YzPYL
rhvBBQb5CQADElX8yGLEUl9NO8DtdP3iIgT+e2xrvqGJoF24yC1W/Y2FnjyJaoLRNsVcG9CPKtEn
w5Mto3Jc92NecJVuADvh844ZzOUGzDVmtvGiNJknzEVE8TLY6YMr/iLO6FGtoOz4LtpPS4Ul54eX
yS6ZZDa4D5+T/M2zJI0Wq09YzXjQCF51lbbxAnoN9DC8oKrgm2zvMWDflkjavFlD6BKiw/f7xvUx
VPlIyFqIC1FtpjevTOm1g7Cz95en74G9XpVrRqbbBr4EiCqPcGF70uH44aXSo+/ZbThyK1JX6H5e
JLsP7BAR87gHEN7/R+ZqqQDEwK0mRl5cpKp4BVDDXkRhyqfHCBQqgiyzHYTd4qX8ifPZVECakRxD
AtcMFkh5fw1PNDqWO+3mm+PZCRT4ye3WhzOWG2Ilrb+bKeTlfhVtm0+1vxmQcfrFJSyhnwhxzeka
NVftAq2OoyyTfU3OYk9hKTqM2lIKyNtxvuWqQiAt9TwtfH3XSFRc25TXOvu8ljjy1RKnCXkRxysg
rE/QX3wpLTOMNoDJa3t7/rmiQfWOhdZfQCSfiJV+27NudVA5UtzkGkhZW36afxdlK24wHAJREIgU
mo7bMpDm03K+7yhzC/9s9U3q9pOZQMJxwn5F26i7YF/BRtltP91dsA/zzryu8no8IDQG1Qq2dVJE
WMsUtpP3Sr1zuGKB8fuEzK/rHGdQNG+g5SWOCd/o4ywTUEyaX+80ZbdShFPXlPqZBBgDA10zQ9/U
Mdi06iR1PmLd7l98RIMpTdjr+Tgk88OYhBAMTsDdyNvr2dw84YW2hDjuUXQisJk1Xf7et2Pab0ox
/ivKJdDb793sAWh9YJHEcFMbeMv2Fne99hN987UG69KbORGnrN2v24krXE0+XlbZ/eKm898tJS6z
4QrCSAojgdg+sTq6D6XC6q+BSBaZh1Bq0WyX4Q2iC7oFVfLDJu5LecmfWmwH2tWoMS+BC0wcLkPL
Lk3sVRplE4OyabbBPBGMusc5g+3uU5EAx7NOGgfw7UcJevgrr0MaEWkPwa/zPwhMzBQbyb38S0Qc
2IZ/dhYkOqEaqteHj+AJQ4ZXLAT/TYi+iV+wOIubaW/0w5Z7yLBxfdER+M5YKDnXxWdRvK2qcQny
XbwuJ0kMHhdmmKqKmi2/FOFuj1NursfzVU3BXIQN/GBy+AGqXItALG+7rLq3z7GxnWpUaXoscNv6
V8RqbO+cDazOhu4ZnQwtv6XjctZj+SF5aejJ7sDxfe6JR1apf5QBc2Io5iEoVrA1juGaeJsN6MNT
JGzYZpTC0UpbIuFIndOZd+69+3Oj6MEuw3w5Q5ZHk9btKuFYWxmg/MM92EG1mCcTann5gceZxgT0
FuZKO9vTGm6QIHZHuUdfGOYaDuJiAuoo+2m9PQRpCsG2k5+aNaKVRgPuM75O3QDY+Z3659e0vKst
EnhH4gAl3pmNbbjZZALBVlC30hQXc8IxIzu6YVi5zcN5JV/WU1Jh1zafVB4NEtb6EDjKsBPzQYV0
ebt084A3NmjuD33RZDbLa5g82sN5MtdPriXXWXpI3L4eeOsz0g+MQ0IyHHChSQRGZd/nO6PK+Hyd
bjLr4JJZkKcEttvcLNhmM4JyynNxwr2i0W4OAMFr5QMOsileHWQ3VQS7ARXiuO+eWHP34NAfJLDm
n/ETowwUYDxnCZTBQx6+cjtUF53478AcN7F7kvkqVBFKZo2KgtGF1YxWQoqIM0tebt4zOKbtOW/p
oG27QSXtBwuCdXk7DVTKu4sCNCarsXH1mWe0FZwr++k9X6Z4EXPhezms7Wsj7QtEmy74QgAvkYqL
OS6se3+UE0gKNfkyi1AHeVv6fqZlQ9uUyMdJp88zQ044SGcgNjBJtOlvV+YUwNrAvefdvnfuslkX
KX4MDplCYBnXUVv5Gt1n7x9LyCGDdulaTA3etzy1G7luM/WryvB8X9TqSs9yMdyGG1wGCtKxc5VK
NS2tKdJE5ANWAaaYphfe5yvH9O6VWlhajDR0k9gL39qDR4FQ29GWKRnhtnaAzpv1M2k1/FmssGjw
lQ1lhnoRMXstaKaqoEqL2AiABmxzpMy+RsfwUBMu1MuXC3xIE8w/KRjjJoC9euk7GOt36tk7CU4I
6Xom0cioCum47wI1WDDJ96dNkZ7otlVGyEoJpbkO5cKBx086Xp4qcmj9hJKnO1w68D096HalwofR
W/6+xrvFCCg8egetfBuLysLLkAaDkMuzjwZToYmArtZKGTWXI7RSOJpxPa0inkyksWSAGVj/m00Y
1d48Ku89tIht3RnJS3muaAu1YtUDSa0wBchbrWn9ZYPq4CezN7o2IzyVt94VmlGuNVwWe12WQ6BK
1kwg4HiCR5wcaw+feOxmxpFiGJReV1fFVutrvWVPgJjdwmelSsuf9IiUsIhXKKYsdldZ2QH84w5f
nfh3Hj+wKAZC6gwx17X7PjXAUVhAlgrpVTsR0nZrobwwJ8dVKp9tIntnq3EnG1HoXDpmqSMG4qJn
Pz+lhZR/MGT06UF6sWnVrwSOg4QsBg2b+TOHWZWgwD8mZiPnSd5sHGIw6+dZ1q1wr5XbFRM2ZRo2
w/Dwsh6Vl71cns+OSWt/5dMdnNzlCvHlzNnLyyoEt8N0t0/gkqdYiuKaJnQXmcGhMVCZG4h29h6W
umT1hp2LbLdOaUm9NqE1sqabFk0W36HB2eA4fZmk427GmXv0GY3XeYTrEgVsKL/K9/suMY9q5bL6
awA/eofB2Gn4KwAJzxx2JSZqobcfMAJyyoic1ZfGQ5VgeGQk3E3pryxQndVKIAhGMAggv1vztv6U
dHkcv/OwEdhlKBJpT/aLTGPZks80ie2w0OEYSKQA5w5pjdnyqmyD6H5I/9DvVkjLc21Krakhbp0O
GiRKKPdwFwajGP0bAl7agRAJ66SZxCNLFk58V1ztTtbo4CR5c8cYq4zFKcpKU4gADRxe/go3/txO
lrVxdvdky1zdtWM18K7VEgoWxpR1FzxRI3ruPBq4h4IFx8dPTJeRY9s5k8Xnoh74CHZB1aoynGSU
CXS/VEnEuZR8tNgmINSdO4QHEkJWx7pSQbFwKxzAYUspoced3YOdy2lqL6wuSD86BKVZNRZZuiOq
NLxSxae3mp4px7KcGFDUdQVJvYlKfMt2WNEpEhcO000blBMz/vPRlKPeM8mUwAMWSGdX3zvI59XU
QYWLHZ/mf/SN5mzVzLcHnwd73LG1DGG6i0DmpsSdjXb74AOvQIikWLO2BK2q8MLLEnR8guG51IT9
XCuP75psO4SwYxrJYIFGfOdmRlS4NsMod79aXLgYdK0qrhToeUs0pRAYc13iKmEtJPVDcywQKWde
VSoRZg8i/HDNXX89AO+vYb/P+FhCli1V9NGclsvL4oK/EJwuEOw9l2Sa0hDSw4ojjRCCZ1FZA5qu
Fw4NWucVdFfHc+zgvfn4m3ZO30wpjLTb7dd4pm8YcklePXor4GemMr1xs+eVr496/SSmMEBazBBa
jUtYo2AGV7r6oEdXnUeWSEzCAxwfLuAEVk437AJzP4yj9ui40/698tn4XZDonSVj+GyLiWSirlBr
+dI0KeUoBTEN4yguskq9uom2b5scs6+nJMIj8ACCv+8kOyKlFqeXo3I+aRIwKItwA2Cb1IvYvEeK
5qggKJjB31s2PAjIXGfCaRu1drytaMNlH6J1exgs7bE6PjW/R/HN5ljwg6nc3KHncQ35v04pcIgB
KZC3qdzxTNguM/6TfY7iIo3zZzeAC061jKZFmX84V3sIuKJJ2q9vhtotjtQPc7GN3xRK35bqyXdq
XBcK4xgiGRcC9oqxjRJwGsznLqxEaM7xMibLiDm7z6A7M5mFM3+HOa5H8/F7giD//WxLEec/93TR
pSZyg2VHcj1vQL6lEcdxMtgAwKYLIwHjxuTkTyXEcKNXjmjay+U/fh9vxbXCiHcCH0KEp+iB6T0i
0mn6cAeCV7dbyb3PvgqaZERkazq9wQ4BFNtwS7/4t5WN9ZxXdzOkqvuIyXuOW2hKn+4nDtk1plkT
7Fu6E+VGYhjX1DufkawRArlPPXg60W8xwNjqg1cuU16WrSi4YMl2xrHxnD/Y7z0gNkt7UvDnctWY
cpkoJdwfe5uPGDdHSb/LnsuF/hSPFkcWLAA4qRSf3dIfCLYWT12LE9ZhkcxY19fC09nBfIksPER+
77q1VpNMdMJsf4AfV32zKjtlif2VSVKHgAD38neCWMlCJtU526sah5DuHgW1gKEyxtwSDkmUzctt
RBAOTU18gc4JN0T2Rpiljy7mnQ3p09D0jOvIdumFUNcO9SIEHh9cTC/D+iJaS5dKtHMygxaiGm1M
7358AgBiXKBCF2rmyUcIVkvkD7fgb26onk+QGheDKIH8hulsBq55XrRj1hTX12LasY9/KkpuRbdg
UqkB5Ds4H9bLSMM5ygfsKVaWz3X/yBiRn/03V57Lw/GWPKiX+0N4ciNremQVVcgy5L8bnbESyFNf
cfzGk9LOo98U8B03WVzY4+TNM8208ZjeG/RiE12WykLnVjzM9R0XB4WuxBJZ6+Qc8+HAxK/2O946
Ba/6kCPCaGM50H0wTOEsrItZh7mYAteqNE8WEJ9AFPWwfCA9T3LEeTN5Qg57oVCrbQzyMpJ0B616
m1dsTMQcpbVhinyezDilS3dGHBObHnFQkrHlyKlsmpB+tRa68iEQkl233Nx5IO/vyO7SOJCHD+Fi
wjQhPATzJ0AsEk2972RTDKy6MbWVq/8qot0pfihDFNcA8cHfN87uJxyj7SEjhqZ0VGLc42Me4ht5
3by152sqyqL+/s5XIx+9dj54GJ/TmrxzAbrhkLKjgetl5BKA04omy+K3yuc9wuZpP3bWyxAqgVo/
6gnizOCUa5/IhfSL0DJRBuIFWtk9tGYn3aXlhkU0n1pa1T/JuIeOPS/AJ43mWJnGqK8SwPiWZXJo
ybAnU8bh9ygbLQpeKYYE0fCN5sKPKQVxl2ZDXSmrty64jr6/3sPMrc4SP0tzkTgd+OoMRfY1dJtV
3d/E3ehBC9PYadK4sOJGD+7Z7sj/xKGA6+eRkO+Nl/HZY4UangKIZgZUxW/+iNukMmOTSc38lqcq
KM0oVwIAa6sMJV8bqmehUAPtV7vMhizE6tqG6d2aEvTtrzsGSzSdeZ9q6jTBraJpr4bK03N7t8Eu
f1ltvvM4UjMG+jcy+0a36A22VEtQoHzBfX0rNaIGX4hyhFmXnTFT4EvDVX7/EnuBZ6ucl4EOMTzZ
ArcuqC/0c41fxjTiNXMH+WltBNrtmCCilhEbVzXjJWCCcRO9LZBqZYMMCbn2YhUbrluNE40TNmIQ
tyMoY/Fw5Uim6Zkdh8lkdbA2dRRzpsn4KH55XsIuH/06+eI0QWK80ytKkqlEScdeEBi4Fe5Vgq1c
03uiQcvgaDygeuMA4qDq5qEs7sJTxZEJvJselSSEgue1QOsQI+ou8HMrq0c3PKYCgv047fpLcv5E
k9GqUaFBXfLiNDdgI9raeVhfEva7aRVY1ks02BkdxPDDGWQQj3VqDdbDEdkAgBmfNSIf6lMtZvHf
Nzr18t43bnzZV86IAz20CUE+kXicP2+pXWtVn5cHhp4jNic8xSk988h4shuhUiuexqys992CnEpC
F3rEZClnP8j5RmafNRcAHOUDKvlCurq4EbYy2st7DkwynT+XPP1iRakvQp+Uw/TqW4uBjRNQBAKs
yf3P1fdU2YTjt1gPGMH3Y4+ieqUP2gOQ5Aa8ZkmdQVd/2SY2Bq10JGJTl4jbvBuAqOkftxIiXlqV
Gq+aHSNjoWhTuUkRxuq3axIX7EghYP2T1LzLmnIzdRDt+nmRxEoUxUgOg4XVEbbGWcePsOMk6acj
XrHYJq6sGGhVYImywen+lGVA0zvRL3kfAgbGTkDEOLs5OTpUDhf8YaiZC950jwl7ihPr66lOcUbm
UI5FCGNSASCoUC9F/g+9XhiZMby3IE2aqbOK56SQh/ioOpGNBcouttMnkrIEx0S06j4abxlsKb8f
POWAbFY4swu1qcdUod6gLeBl4pTKsCCGqVoaT6J2RS3T9MdTJRRUJyJ7kFQZGM5gbPNhaUxtUlkx
AEKBJwOEgsiWrUITytJ1rGI9je11BBMbmv073VKR7DJQcuoMolNvc4Swq0ecfSiYrPJgKMb9jTMc
AR9HjwS2VuOuNlkflU3JLL9zG+TuSQsdQwhtOHcCExJbN57k6ad2mHVAmwTcOKLQwotwBd1TccxF
tios1Z1Itp4XdUyQiqMsE0p3fcG6zESTRwjhrGJrdoWBhFcoGIvg3jP6wwzo3WE/UV4szqBG261I
ZABaAsS9PEpfzpI8+JFxwR5jna4M+5OTI2a7+Ke8sRdHxsSFKk56WUErhRh72y9F17WJ89PC55ho
wRsdk7ljJkyTJSlRTtlOAkuRKLn4pcRKxbEcYUUQy2Xueie7YrF6sxDznhOKIcpLpLK23GhikOHD
y+cOC1Tsa5hmNrK1Vg1xvsas+eQRdRVSGaM5bSpSBwek3q1cXeR0unK+M/CiukwmBCmx3zSR1c2V
QFZgr25cVHTD6+X/XMzGTgSxt25RQBylwRSyHPbP+kIv5Y6nw34SsDTTpeY56Sdx5TggIYr0ucMZ
NPVNcO9sbzGwKVWm8hO9zZvW/zaegavbUeSEkVpqzwiZ1dxRU0wJqPj6yV7okikxSJrSN10xpnQi
SE9MmZzMCdbvm7i4ngmppwxpE54iczBXk6z9xQRXmt3i3EcEAGo9hbSOmEsTIb3VCLd9+dGi+UqP
ircKCFKEB7bC9ECh6Z6UBty2twK/JnIC3QUTRc+UxMf+50bkEOb8utEx++aNmicJsEZST/SR+JBU
Tw3V8g2YpsO4rrY8FjaEJ0uqOzwqBt6D3WoyR4BMcQ6kGrw7Oggn2KrBQ038msGgu5GkWyys2aNp
p99o1GavlLoUz7I2q+N4y9o3HrChQvV9nYo8aBH+6Hwrnh1FtZ1SKGMAqQMGHrj86lDnxI5wbOES
CAkMPdz9jf0YAAQM6jXQjeu3OXhI67N/iCIjcvyL3rEiJtiVWARNQ+lYgB14wUSaWKyBCfx+CMI8
fL9D6Xrug/9nWtyuBzLi1i7yYAW0FXcSLxmQ5FUwC+SdubQ9KvEhxwO5NrFWunCInM6df51nW7wR
Fw9ZezRvbTISOwZp0RoGPd0JcgPTf44VSBJ0A4t3+bfdepM1vH4WJcIKJYXo93AZ65eEZSJuofsG
sg5XqLkywEHqYRac/hkFUKxDSTnlxzG5ekoZw2nuAOofhV3bU4oGcA0fFwsaZzhSn6iLCrKf1zkY
gyfbgSQiYYkk+t4bs0Yr6opz1FYTbkNtInVJ0gWoHtIZCyb0HikZ3nfJm1DFS0QUBl27IgeHhAsr
mnL4h3vALFF2zcT2d3H+PxFyiiUzEs5D6eo37OiKg55EQKD5Q9/FblWrnO0PbIrdFnfX35kpQgf6
bC4xyOUHSgR+VWCjo5h9r7eKtOmkCGyTkbSfYfdofCXV7L5WZT+cMZ1oXcHP6WFUysLsTpgpVh8b
AgJgHI8FnLg9A6GYY/FljMmxbCqU2hJGPJ29fKaV2lBNsvWF2qTRUwLXrjiegNG4zhEjkYgCPAfI
zi740h77/liZeJnZM2C3Jj6rjecZ+GyHL32rCqnW7HpXZaZirS80V+/WrA/UVRMx1VPeu7gq1Dev
odHgGZFP0TyrCW+J9O2g2+WSle2V0v+g+9MxMPRvvy2DzJ59k81JAjLzp4tntSULN7/vuU8RHqBb
BA8MH/Yftdn5YKE/D6NVjGh+7PgbJhtZmVNyr4tvCTNBRvGe3R0EvG7iBpTIeYAKHm/84ORiLYh8
QP7lMD+H4zWOdzB6MUQiZEgZuWoC5XNXF7r9phj0+v5oBcc/Xe7mDYxqeERpMD2e8s0Bpc1I5QAL
BighLJpm6GgonOjq4Xb+hQyvvH580Yzo+avtijfzU0SRCXtzDn4LrBhULsospODE3iR+pavFcQCz
00cHtsyz/NoZ6+PrLXw3Mi7vmT11TDDDXP5RJuzYbJXpxoRE5e5CjB2MIxLFypcUExpdl71s25ry
jGGW1ZlFBZ5PDj6VVId1S6Oz7TKsxXUBxdjTEsQkYo1KyILfiXNYkXQSwZeR+InktQS8ROhsjLHJ
KvY/ni+6OYtY/+nii8bquf6DBLqNKj63U5LAcf2qKqBYLAUvhfmviXfxmCclhmqZ+ZNnUC//JTwC
ji7LnLQj1/Qrq27iYMzRSt8ZR9OCYKbh2/zJl/8ASbo1gpVRQ5Q9/PE2o9HtWeOWf497daxb6nyN
T8qLuBnPyIEckp7fXLwHpu2j11lhwD5MIj5ytll59Qt41JKMrwrT4Z7QKnfDURi65dhYIX8tzEiX
yO2aT4zxoXat+V+lM1IjWUU+NQ/CdohZUMmeS7zqnoEvKZHkdPXhlxGlDOUj+E+uZAT/BDoHlpAr
x7Va5FLaL7o+0kJLaHkfVQy0t8iTA5kOS5f9RLZoZKtIVEpttaYIJmcLUJRXVSTASCkIIrmMuXle
MV1oELWLT3OvRw86D8UJ1GDoH0CEuRpv5OqVSCN6cPDwuK/yK6hkYRIqoFYSrSIVn3hbE1df3nru
JP1CouJOMiLSV9z6Eq5tQ8o34GxWEYUM+M+HYkOPYJI6cQ70YyAONmSDy5nrQRpXkdtmqbOH6pVr
R8AHaFsEK3JAfUThHJ/h1PrNd5br0r7cc2hdIaknH0STFlylDT3yXi5d+CLum5n1ME6RtJiSGW4D
1vT7w4fOoteUvmKTP9PIUNrw8Q4bpu5nPgd7s6NDMA2bfBdqbb0biNwqplbtxEtnvsYvK3B0vd5G
CZG4A2X56ijC1eYrbdzfr/pIfQVELBDYV30yGnvPP4UUpinpXlzDQkoSkTzJItQNOpvGtS3Pjyap
Nozy90YRLzQjCmxi1gxDkwp9gMba4Qj5EhwpMuQ+z/d9MYAhAkCo3Ocl8SwsdTNwIIVw+Z50I2Dl
FEa7FvuBAlX8dWeuL+6H1cC66+FBmu1+DHan34WDv01ryuVJ89JPf/A1Jw8HA3BpWjA2IH/VN6XC
2rc1scsas4jhsjfOjCV6s/dtPzNaC+RYRWVK9msr10NPQ1usKxvvYA58FLTmDUs+WHb2tLy85G8j
euZv6kTXJH79wLVOKLvpckeEh6qZ+SzVvdIPtTHlQO/iOAHQNTQ8VJk0Ouudr0+LGGZM93Qndjzc
q7jEC2l6ZWf/pST5hWs4CQsQ8a9KbOVZYvf60r2jAjIWTfn6o+Oj8OvKeQFZ9pzUYxs7f3djcHbt
cY8KReaL9IG9hEOW8QS6MkR7olCD1I7R92eNUZoWrIu8TPMMPGkXX0QvXo/v4xPXd096f9O1whVW
E6GDRlOGXodDhvJEhwLFmsOWKYyy9tP3ZseQCqoEsgdkGYZX22pFhYfUVpnNt+rMi5NL/NR2kZVO
C78mZekt0SIe0xpPe64Dk+Ivfusoq6LHA3eG4ACqdi+awLMh1FSxYIxH9LoKzGNGiII6mIOZrV/A
Fc6Rkm7slsG1x4dtqusovtCsg75lZzhU3gZ6YBjVHdSWUQ/qzSacAPLfo0lajDf6ohnNvSZV5yFy
j7PHSFl7fg1St5sJAZK3iS4HDVhAiJ275448+6HpayGwcI96fqhvSMzIvj1vO5yYkJAkMeythIjq
V3kNd8GBO/9/9XWwfQGA
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
LOrXUPjF5IFoLR0AYJN+dt4yr/8PqcmGKyTL4CgFcGvIQ/aJ3vGk36Cz00TRq+Nqo45GnHt/1m6E
UtRjBvwscw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WJKji58llb2KFFsN3Cd7W+Zzki2XT+kR6uYjuhoIbWbNBY6QIL2EpnimDuG57wFXeXyygvWr7yZK
VfWkOmEzAoMkw8hRi8Go7bMDERt9P5yhKxDIWNswSFLZMI88xgrYUluTl7zN1MvivA6Gt/XVbvPv
3GGjWUoqFlxi7f+DFPI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Jcs3+SQtGSLXFw6cEFOru8HjLAfKHwfQq8uBjCuKKtwRK/yAJwHRNjL9vc812moIiB8SgQ6pgBcS
Krk8XWqTViUhh08+bhuqDoOZqOhRUnVe2KU5bPOaP2D9D28MoI3jEqKcN09ui/jOIGo4bQMOEbtB
wlRhrV0ZlM8hz+dOMrE9TqEKY7v79uyDjoJxh4nhEugl6X+2H2jvq2cqqzDTFfzkrid/WPga5bbx
KkG4eEks3DZVdZv7b+yNIRKNuVxxfwkCok9M3MxHhufe74MBfVoppTGm+9M1T3tJNnRZ2GXItBK0
1RYRkOuPxTXDLegfYLeDZsAuhH9IEIshQelv1w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
yofNydq+Hv2ft429NgFsYlO9b8jA1NAsY+uUYJMnIovXFAwZsz1Ox60jgGkg5M7evNESBTbZBPcI
PTWxb5rdOnK4575N4uhSw3MITRy7m1hlZM7NFQn2iS9e+tLlKFKKUrsejS1G3PgGgo8fR5P/7VYQ
oqNlDT9rFqWM2kjqfZw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
MNqDEnqKF5nNQQLZKl12k5g6EvteYCdq0RTqoAuouDXi4v48X86esK/4i/V+9HB3NeqF6RV2fE85
W5pzBBXr37jp0pzu3JoqwausCaAEJZMx641TszLj7JMKRrTVGZcgpWD+M2cay4Spk0Q93SkdU9zg
z2jTkDt1oYIAU0Lj8C3F4lDHk3itQkKVEDkczOPNS2iw+YeASIrN/QVRJynOQKfHbfIa4TsYzxAh
mI0k6aWPaN6Ed4QbFNsEMPvtduaur4tT93LN/4AigwrZKqQUkO4JP12H1+L2+eLhx5WQl/MF21Zy
ykaSn6yKqF6ZSA5d08POimRDuEDdjAIUFc6TZA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 36096)
`protect data_block
Jay0qZlyG04qyslfbjmu1/PefK58a1bAtzIU4O3B621tSZs6uZb560Gj40HzQmBC5guZu/HZNXpk
vxqrOoIdiV19ysXXCQgvDav2CLc1JQfaD7MO8lM+3RzVgA5/4XBaB1Mxjb3LoG2ypsLw2paMea4I
CKH0J5e5259Hk6gWXGBHwMe4C+DuVqJv55l4WjiIgqbbnzzosYTVcsZFHp2iZLjYZmiFcvLK+C+s
YM8KrlQmNuqLBtlMva2lzejLuYpxhT1OBdR577Y6iBRZqR3PjyEYRf/9CdEB0Ozv2PZyhO5wqYvi
CYKVcXLCmAYMTErMD4iOoKiDTCF7BkO3thY5m7jq0IpYnxVKNFvcnRd8LsSpzuTAUHZTtlQBYhmR
UrGLqAaXqUqFEGUw9mt5DiflA9JReczFr6QfMqVRDEJ5+mdLlajI38MaiIFztLwdb3LvWyKGUF2h
fRBFgH5vJRx8mfWr25Mp2w3A45NudrqUgoToO3YgPGfL+n9lqx8iItP6DTaZUu45aRKeNO5W540M
VqWQEJIZOPsP8WXJ8clvUAVecQZoudMVwImD2IpfE+XBtwOO2pWJ8bgo1Hl7v6kAWLffu3D9TfOX
OQapmXk85Jxt+1vavpMpExqdzBLfJEuSBGjKCucJfiDZbmoBnN/cksXN5vTUsdn7OY7MQtNXqKBd
YWfu/jl4DNhMxVRncGcJXb1PElxl97/RavPWTnQsdzfdBNXhpXi280qwlOK3xiLoAEBfYaz1uis3
uOFeHp75JwW6oji9AqW4YOIzKxzNdtwUV50+gEd/qt0/Zx4oCDPV/78Bkft7QUkpNY6b7qjwppfj
i5yG3i4BWL7vfLb+rLtKgqKXSL+GYshHHvk6nZQqmfADndqdPlncIYyk92muGbPsWY4iSjy4C+l0
39fXs4sJ3rfAs1S7P0FJXf/YlpITtl+9gSM1HqBd+z46+OjDX8UaQ3le6QJBwGPy4xQqclpTnpxp
zqe0Ke1vD0MChhmXJa+SyBbTWtNTH5n2u+pKy2R8esIjPTgciOpbpX/KxzdzEx1+dSruXVW54xe7
JUpcVe0/aBKu2k+QOv7JRA/A3ypHZofMwrQGnyMtFv1Ui8KcELhRc5UzpsM+emYQH4XekOXYrUfG
5jAD35RCHFTZKKig42l23fJ18Wi+0z4+2gxGX9WP0F5+xL2IC6gmqNIFb+ClWILZnqHRdXvXmfhH
//c+s8KVsKOkPPzplo08wKOtdQwtTzbm8IACRfCkqLAyQM3WWnnl6sDUQAp63rOU/4bFDHpIZgn9
6v1t7jJpMk9W40O7X14+N+33QyTkRHTO+6AwUU+voW+NdFKfzUBqC5ipKansg+TQA1ySjMMk1dHf
77OgL0D4KtGQj9dEHk1q6MyLY1kVhqkWVgKajkz6/YZ9ewJV7JzyFDkqL/RywkOEc/KjvBC9g6WH
YbomdvIAWKYwfrkfXqRYT4nLBIoYwsBgcUISM12USI+al4qnaGbaKYQxrnHvfZS7vmD+dPdhnpw+
Knbsr6C5fBh7e33AJsxMjXB4y3xMb080um1MB5QeMVJJJmrfp5AeaVri7GzVTaT+b7QLKAvFREEt
p0VoudklRvCkicArcLkFN4xuPs/LuJZFQhX2PjXQXhSWjCjTmijc+20PDxu0vSV6UQTG/OvWIeCJ
D+0idv3ZrDWpz5ikktANTclHyzNwiFVArf95ES4nWx0LN+ODiUgaQ3NWKKKnP6cNmeQM0oAjBB+V
l0Ept/17YpONRc3ZMkMwm5TjyrAwxje0ms252wKTNRXX/AIr6vyRjXuNpzf3xh4brfpGqkK2dXtU
XD7oifKQCMUKkDV9qU0iT++9hn3f6oow9ksk2wR4LxgIsv6VC/zMSl1oK0jmBgpVj4wq8SDN2u2D
vhB1UVskGEvKqZdn/qXCHN/II0cVeirCjNxB6/DuNoj9AJ84R3tWnqSH7BelhFgJ5s3umiqHBeHq
IDQDfbz37SLrqWOnp5GBUb9Rh8tFbjOI+TTXWOpdkHxRcllpWPRwXdAOX3aKGKTjP9V5ZW6v9HBM
PFxp/w1LUo8HtIVnwbRycbJjh8IqVytqJbDnePMnBPZTk3hO+0PLe62dx5OIQ10Yhyc2LjViSoNP
KRSk2ExSdUTDZk4N1+O+35MFwzklX5R5e5w3dSzFbf5N8X9Y89UlXlTNrPq/YK7yz+QSNbS15Hd9
XFaM1RFnZh+IIE7zjKFQY1y7tET1Fuf+rh9630HxFah6HXmzAHkyv2PpdbvO+eMxg5h0/3uAJ9jl
v3W979F33x8l1URufVk+Qf/b/WzR4i6ou4P4vMreIcdzfohz+I1UdcmTxCI3k0xvwcxmiLuX5Gyv
PNLBZ6G5ab9Tx683rhkr1JrNhFyaya+YtyTfs9oQSdQSjX4jVn+OgUrfsP2pwSrarxEr08nJVtj/
LTREd3qcPuicM2SPHP6LN4KXtgsk0I0USWpIRJysSuGmlTujxw1XR9fKEOMzNlFTXvm9jNMJ0z/S
F9J4/XS8rOJM4tbogxuGZsmKC4oZfdBdeXsIMVm3X96x9g2VxTlLVz1etfL7+Y2P6DSg6VnpdCC+
LVW3gyCmvzbOfKvBVuE+yCWIrHPDxnktznhF6u3F4TDYl1wcMvjV9+FdgFwtr8+vWo3nzrfqg3ph
WU+AhJJV+Uk+moIJC4X9exypHIeUcEmu8qlWYpOyRit56Oc3RpxvdiaWqAwBM7LCR/9yIyZKcmjF
JyRqo9H7Zdsfk7EDd6En8KR68Qi57ylNohJr2Fo05T8AgCWpBgjKSTpV/1aKefdv0SlRK9gO36Mp
9m0Maw4dX3xm/9t16ABGBPE/+heQEu7bceeen60i7JXnhZmPUAiNKlf4vyK7jjx/S82PUfmpzWNt
uBl5ppoG1o7QUcpm66AgvoBi9X5/s92o8OvLQ3NCjsPRqYpXjTfaCIYKh5+Rx+D22XKbij+ju6rb
YeFnGZ4y5UPa9kZ9mDnB95AKcypxQCrWO3RQH2zRfV2PMKfQ2iFqj5v8cwGO9dn6fZq3t5B5H8UK
o4YLJB/5XLgk5hkIuD9GubYfnGxijOC97LHhdTq63l+mXQYXHwZjCC+86H/uLvrZ9KvXAQQAJAbh
q/QaI56gXD3e6MvmV6a/ZILgBRdNN602rw50wX9v60kWZa7jCMFPOJToISdTwGReYZnr8SOZQZFL
eyH+hEVdRSK0FNBiEwP0nOF1eedKjYwGncRAYbc3n8hWV141D43c2EmeS6vWHhr7ezruABdtMj2y
XbFcjCfO0nTJgthubHIIDItv6DuSlO4t8fkzMl0loVvdaPSsSjcOVSBVDJiacW43GmL6sCTcQune
tIIj/0tq9T1kJB4SKA5oa1rS7+emZAtXToMX0vh4al4O/9lRmElrDQULT38pHxJ5517BxMLBh2QE
O4hAC9f3+dWKqjnBMiDQAfOFGcqdc58XC9VkKxES0LyabQnnWnzokuHKMMCN6f9r5ago+pLEM3Fv
R4dSN10EPOkhrXOxodFV6t9ksV5kx3Th6v4zqf8kclnCccAkI7fYwb4JX1SsymqWE12t0vsKLrw4
lUqN6hkbIUs3Sas9HiZrXsV22nl2CXV3hV2UUfE60tMhm8vbXUzt5ghLq41PrZtIn4DiIRA5okIq
9TkghcZoOqqqae8Vw8ttYBA1Ja+LIBUydVn4t24N/rcwvfE9ASmFWKwmw+bZGVMlwVag790JAgQq
hlgalgWOr3C+rlV+PE2vkUkKiY4jUFRfjpHXCw8lwZnr9iOo2Yo0DHxAvho4+j6el7lCSdod67RK
vVUIIlor3/31Jl2WXnFNcwyai3rnasUOEv+lsbaiFuv+GwBbuBZk5qZYEVQJWk9ZoDMy9+kihYG4
M4/qBb6bV6IX+p2YCP9Sm4g35uOZ62351n3vjxS7NA3UJE0Ejs90uCZwQ/qEjXqnJSEC2VVeNmUq
8UmSO7Y4gsAobe6XTty9XPLVs6141Y0DTYmwp0InG51XsEqaLESIstJL8E+49kdj6+fpGM7T57nt
16p9Ts/yX1ZHx1D7ORH6UN56doV6wvh+c5iEh1DjT2V9diHndDECSi3E+zQAn1MDQicMYUz9FCHZ
QmjVy+rxXYH0nuygHEH5jT8XhG5cExILO+insYZw+KeUDcSpvNcSVc3nyaYu4ct8OyPB7x18kubx
uLENYer+5oJ4rCydPAU995+CdTpljyxjHzLuf0nMs5pOtJVxmiTndUmNWMGEJUF2rQ/cHGYh7/4c
CFTyfv7PfG/JjOfgcjrYgHn3Tbh8sC1Rt/aWTYbxhFMeBMLAKR2mhXL2yZF7wbps6K/kuQrjYuov
YevrgkXKhH2JycYmznTG1qjLOiRo0lRlg0+T3dJv46u5oe0yY6cjuQEMzCaQbP+i6nflgsLTrtSM
6rRVJCE6olyFuLxRNaDGhM17y+J76H7uBcdmQgWgEIqUHEM4JZARRi33jYvcUb/hKQFzXVVaGHfy
o7szEqynSR+ArXYxTsNFGAxIoAc1UicRkoxNwEXnsGD1ISxyEsayBcd76agIZpe8fPPrYgX0pDAw
27xRGz6BfHTMTbIH7iBT4Oqa1BwuyYgVrJ82ocYBjv6Ipfgq6cplYwCE2eQEpETDkdol1JEILkAE
0F7qvdzCNnQXWgPeI4/WkdnE+YTxqz8dBbUD3sUKr+jJjfnNv6kFwvojq5gsBEL9ddTh8LM8QFjH
OtAP09F8Gu2yDzKodOqCvAPJZbTbxN75y7Sdmc+Be6EVu7KskbRmnuetLtk6ME4HNu1FkiuW+HDt
L/DBocQRMmXn9yuAxBIFeNtuA9a7p1yZrV6DCs+VQcBNNCx9kt+JZ+zWqB/dEuZ4ibJkVPQgw8XR
AChPDtIUx/BcOKVK9ZbTRKPe0ZOZc/fesjSG4jIt0TfAT+ykUinvMFMOfSWI8niujDOrkXRwrsod
zt4+uTCV5+HYWbY+DxVpj0kRbkCuHyVk+HtuhGrgq/nfBzJafwa6rk9zMvjbM2Rb+wHgEbgmyQ58
UkamR7KpCpn9tnC0+UmQhOQ9XMkx/+V6fsoD26dAD4VrizmtCTEHudfC0crbikRweptalzpO9w8j
9MA1pU7cT0VBVqPAFnc/bM/ezES/+p7FYscqpqxJ4TRXPxfItWpD8lVUnASOvmx2efkLEdXF5Hk6
z+Bwljkns8w/LXq3BgCP1DaLZqyqdqdVC9yiMoknRKEXagDTOCqsoNQfocLJCQoPmHxRh2GeSYyi
GB8sJkVgCUpL2zH7rdnbtS1zzNAoynHmPNSEHTNJE5eFuRvRcY2e7sLOuqvYMyHB0d3mkMDFUFre
FIGL0I5eeDSPBQZD2bg/cFIi4xZsBPx+e6ftNpTIfHfgKUf+tDPOMSu6chUVlM9Ppl8yJs+/HcjC
jIP6eqg1Ev+EisS+4CoTgZLsrdIaf2IXzmBNwsklFNBdVLpx9Ghz/gzthgCSCRmHvq9wig5v71Ff
tlrNvsswI/wc2/riCPg1FB3jZjqoNbit2ka9Dwt73QLHgHXdalcmxwELKWSCio4Q4KtL2oImamWH
YU7i/T/APyjw3cIz7IiwMSHOK6zKdUe5gfKmFzUbAb8V8k5Frf70554LjFE7KprNd87tsiwB2RDL
E2oaNIeizDNo1Pm5eMB772tlk6Up/vs1k0va5pGOn46GSpLZL2bJflnPdV0U7OJPLC1jbRcvBV/d
9C6UftvaeC2dviYAm9qB3ygbauyA0+VfY6JKR5hm4pGGHnAqfo6yzHQ+tsQArPik0kPdqQq8Ghtp
xzU5Utx05sTOLu4CK/d3hPq5WA5RW/wrhLcMdIKDOrn1YCWG+UXhiisfg2+PkGkAy+udAKQS/Gmg
AOsrPvBLU+LH2NGl5Wpkrwa49fWy/CnmR0HHya2uTdJCfSqR+x8u2YrQ9Tv86upCEAlapiYBZrRa
klZeGGwjMp6NBBju72sMyDI//lr4pG9wTrt1fifV9l4BGPFgxj43SJ6c1e2PIsFKikvt0SPoUxtG
lQlYxfeuxD9viRI6cGsKyOy5Ij2G2kcuSyPKJ6foCw4oXGQ6w1t4pR/iX524xca7fAadtqBa1MTB
G0qjj1x5l8rkG3sKApz82mpanf/YzzmxrsSiFHImCfMEg1XZ/cIP3ARPrzw/zLz5Dyw/YWysHXBi
ZULXkwt76E5DZVxoPBZbUcIkVAievub527ftAlGTvHCRorAaccSyi+0SYrlY24pihoL44xFy9AOb
4B7u2qGxUgzcRhSywNoZB7spoWYVEgc/2ozOWaa/jhhiIpXk45wTAFer1Xepx4dCgZknLfNXHElg
08aIZnmXB5o4ttTwEXnTxOTeTlf0svkmDswdP1RguN0FDs+Chp4zzKrZBfIpY1IridckP1aTvLbI
4zwcZ6uS18tl18sEhlnl1aJ9xVd+k2zyn9ClENl8THp8K5Qx5AedZVGwzgCHZab4+ZVdVXAborKg
p7Yk7/CuPeG/VETD7ey+01IxmMDXgU+Ds3IIoHnjNZGcvpf7FbVhMaDGCuU0kJPouW9hS06/0ZdI
aYDkXF9C95m4tdUQqpVYWv7kCtM237pj0CRnY1Z7zA+tCmmjq30Fk5vhlxYcENQDYphxDHCeg+nX
ez86848fS0zajqs0SneVwZw07/jeaJEAMIXuo7oMrD5g96OaOCZ3VvHQ0SY0dx5hGjT+BGCWtXq5
R/kpaCzy/SMNFQKLgRPEhX0zL4QWfIfDS+asBLYXtDN8tGiQ8bCMiA8PwbGyF9E+GZK3oyh5SL2h
eFs9TnubgKZTF/X/L1FZ5YduuCZlu/ePmnIwloEg6mRtetRxFE4h6BY3qfDGV9KbHZG9VuCmR/MQ
CxdYLbVGcNX7se6ZsGfatS4UvyIQAwXoqdbgqeOjUTg2wnQAvbgWcehN5nO0kyuPnf+xkNlz9lCk
P3JAhwxeVVfXouzPi8OMDKp4d3RJUiJlioOM2hr07jB2936k1JUNGm1rS7WAcu/2Nbf7Cs4VUASG
L1uOdzWfIeruaHrsgQy0GF99XVQqMfsQ0Z+p6L5dzNrfcN3wSncnMTBHzPJkcOPM+/PIP8PJfaEW
43bm0nRrdZLqMlfoNUMuxUTBz62BAzAZOFUJFo8vh2l13xcncLw8iutvesaaQEv7VC9XAWNFLaeS
70L4av4vLRmDxy7Kb7o1PdmFbbvxXplt6wSFRJM0oL3vjZ/cxnut9aMfU/dNaAscEHnPasDs2tcl
tm3hQdUii8Uv8S2G12cQkYTG99Sr8HIwp2NwlahxCXE70mEh9tpRgyzmSglQ6afoMF3WtuC1baV6
uvr7mnzmNJJkPffFRvrQ7PmhYS7Epjhe06Nwx7G3oTNNJm8/oiIMSZRVPGjmXuLpXTYta0O/dac2
+x+iwxTweVqiSiC5++IK5FWIIn/jcge3ipSjlycCo5cE0Cyjtw626WBmZFsNSk+8ETWxNYxCbD4x
fqKDB0XzQrwCJEwg5rQy0WGp6vOXVAKxL5mJBSSEwtQhPO2iTgfQvv5bt7Lzk+D7YLTorLXVRZCv
0CXRAOAuBn2PC7rCwnCu/rYnUdaQ6wSws7VpSz9+gbsOODW17ATu4txNQGDzO44Qf4zJia2YRGpB
HUAsXQWGX9cy1qH9LyPodwLdM67HZ294tGLUMaiLiHN3xy1NycfNy70iMQ11T928nRPKUR1iIMHu
OPJCPE6Wuzn2TDXII9WCdUcucQeDsTPldxRPuh5VoMGAmPTsm3PkzPc/Oro/n8PBrbR4GxLIiz/y
CzMIPGVDVpMaY3zrsHLvuVcfEyRICpi+YOZJq3BU3qCMIm4EXuN1c6vl1MTF9YWYMYdf3OrPe+6H
LCyp27WwYleX2xZzwd2PAYlSsTy2vCnDA71RTng46Ws+VO884qIo9/zztIX9DVW4TraRvDil9C47
E2kTjrX+YCe3VN6C2+wdZ3sQguJGO2S4edyfCY3RTBe8fa7yMSy5SvT+S9rs8hAbNpooS5u7zK2s
poSxiwxqB3uN6vzVQFMY0FkBKqvG3MGcnyNRLbTNJSej10DhO7avP5zIi7rWKPdqOQ+1JEKDnn7d
MSJA0XU10u+JI6p6bKK24IzSCrbCu54KK/+rLKbapUzcl3Fe/3jqkM22XbZ/UkCpzKAHyQGNXxer
q0U+YOPWFYbH4H/3/UvYMmaPifJJeT4OjvGB3BJeCD1i4aSxR6k2kMrKZo3Wg0M1X/dFxSUSL2II
clcjiin/kMhvEBolaaZvAn2uODxnl8d0tD2ghZaoDHNgVoZb2N/cJkolQr/rex2Uq/39YXEK4tor
zIia7AaTSSGMZzE1fsNEjBYrF/TNVY6A5P2eHA+0Gg5VucFsYcUX/5hBgsqLH562IOzO83iT7fdT
nIz5K1PzI+QadwKpVnEeY9JlSQkiWIL8zBt+TWZwlZjCnprx/Cm0yxuzaC7MIQG9JrBykeK+wfKV
7pMLKTphuE5mfLWbK3N7K51+cjZN/evhymw/gIUQE4Wv8k8VL2gkyr1vFiayF8PCM5i0ia3CW6BB
ZZGAwX8NfF+vfu78dr0UbmYp+S1VUiF3AmdyFgrjxHZlA7s/CsCD2z/zycJB5u0teLrJcreSXcMh
pWt5CzoWFlYSlO3komimx1fgFnoE9qCKqQh6OtzwRxPTofU3V6VJ0fEgaB8s3KOtWvM/gCgILN3R
uiMcNArqYHH+JKsz7TTkR+b6K47UK4tnh+qqYKRrYNkvPF+xx59Kf7mYGTak7su4b+RqgqHUiPEF
JBBCH5/ULZ7tiUiin5rDlG73PyxFJamkueYer7u1As6B3V2Ti7CYIJV8orhn77U8N/v6HYh0dQn9
LI9O2QPBqqr+mLq09QLpoHF+akm9pnULKInAZTUNNkFr1fyDX8XIZdCIqklngyK2H//MaSjei7E/
4OO6cp2i7+VdPv/pN/t0EgX7BMUnl1etmuAQnULCB+LcQkUilheKMohI1Cvr4ZbMgF9HZu3d+rHO
YvqUYs6qL2qSz3RxglDFJFfVjU+zPX8RjfxEBUwFxzaXy8w3k/1IgTfWHg2HVEnl/x3+7huZ3ppA
eoOATRwLNBd1R7VwkWRu7+/NwRGezYZjzgX6ddqF4q9ILdLuMQQKe3UGjNpcVUxQTK5OodK8FonK
JQdLWcKg+IcB/fwoenpiJqRhYxAiiegExxcUXJGAzkrf/gshpGlOKXBky2FB6RFi5PiI1cxF9K9d
oD4ZZ2Hc0Cy+Is5hYvZuy+eb+d1vP/O8M0TzNv5XDkrJws121nxms0OPRbSE5aQT0JeYbWu/LDhY
2QnSoCILadQT+wmDJlJtg4lu1hYlKRVyhynOBw+R+kSxAZo7DIpKzqSl4Z+ebFDq8KpyloJFZUIb
qxpSn0eu/KV5VumEttVEUdXelLKmPYSSHgRm661NLFgQesUUmP2pRdTRc3Xdh0eI7HoPzK3QoPm7
IumNL+/OSQwGxenlD64i6Q61DjlH+EK4t4o/NtoBaCJ02tWiqxgPKPBYaWALIsQ6n1YGP78bjAl7
9aG8A52xpROoiW/spkOWGavdFWx9MjJEsuQf5zbw3+bzx5RMATXe+9LaLmsVlfqjgTlAlCVxG5Wd
llZYx+MjHLEuPutCT9iRrYaXYd5pS83HpYTm6n4fX9FrV9O/z24lhsUSa4VwnDQi4bsJmbxegmV8
1ZM3ije5dPmma93k/ciuDPjUhP+/3aQhIyzdKHdxxTY0t947dluMtbBtSl497A7ID8BDD5a8qh/N
jnmUluXuWBsgkLDq9IzeWjQe12I+JflPC9FIP5+qntLEH/bd/FAAcb41b1qmEON03sYS+iANEQa7
QI7vRo3PMViU9ClbqQBbUQJdbq0IwR31xKg8VDNhnzy2OxynK699FnosNDri2WTn6jFhpkMg8clp
uBt31eCIeRBeQZisAglezsRkpPhZOqxtt3AbDt6T1K5TO198gUUEU7XbRVb+9htNatMfyDABntDm
hatEVvYuzoaFjAhLWA58kUSi6T6SJl3fs2qf3iKDDzDSIZrVbl48imWITtfAm3kGISn6D+r/bLqE
wThg2iOEYmH98JqQoZ9SgR34E6CO1sAndubE4FtHXvI7FlbHqSrDKzbtofTexVFyBaofUOMe9nqp
9qnpLEo9uICs/dLkhGa7Sy88OCNGlboiaYZBk5sFkh4PYSxD7n2g1N4L/2tXMpb3aLheYNUzfEoi
p6TYQJWxfAxhllWBr88nxZiP7eteWuvquMX/nIjoX9hCVO6CLoSUeRRaRr58wcC2Qu8aH+yHPvHe
fDq/LSjNtGyTE8MYLwLrTX/ruiTnHxicpYE8BS7eUiOf6yjNxrRlfXzirMsRIyw3aUbgo1sNX5FQ
tVIaiAnsGppjO3eU/1CQOHOz8+wUnroSpg65TEu7wqC68Su7TYIe6lnstoRvQQK7SwQRzjKBlj7m
15QpZxIOqp1ZyVRgBQbwwCme45XPVHSC2UqODteOTbGkBLOC1R6mWuTjOB2xZD6zVNiH7w+rHOGO
PbCCRFYynIOk+313+MLxCMDDNI/Yn78cLzXuF8odmM0tfaIpZzC75I5HOggt7oepsgHqtOS/pAIt
ZhyYYo4byKOqJe6bwnOZCJcQ3Vbk83hMAaIxhBQ79uxG3vbHrpHjviJ5TEnXYn2rWTImp2BpIm7Z
baksycTBvu6sO5gjnttnSC3lpGopOWsIXFx/Tj8VoKeGs28pDY2sBdgBjuNM8mizFUbbCNavGemA
WVQB9M1RchOEMi6MOSPzNMcmqfRRgMYpqVTqO+BWNu7LkTA4RZ6doNcGM/04Bn95PGi9Dgc+nNV2
kzl3Lb0ddBW7D8r2uKocR0nQgk8R/W/zqWwv+Kwth1XsPUuVBfwk/RtBFRwZtJnow+DZBpKKgknr
Xd2faRO4mxyJVRYF8M1CmfAKhiIjIzdE/UxBwxyLX+TAiXznYRl3r9pM3j0rzf7x/DXwb8l4kpkh
YacJsaDjWtyLuFWWa6okEQAuWwYG6Rts1g4xNQ+UwoHj97p1JNkmP2wIePQb8GgEy8abiLTScx86
Vmj67jfICjSY3YPQOJVfqAZbPBvGtEsY5aae7WI6+y3f+j7M5j1gKpKyvXyE/nJzkb5Sqmni0ZWB
89tmZ59xEXLu/I2c5IDIYuYGaqzJOME61DZMOo03QGIbh9DTMvAeQBsBEKYMLMSK/+WUxLMkepn2
BD880n28sovbZrDQwLh+72vzwu0xDoCdv/3F6KNaBIMsrK2vzPqComCnm8rnGxkLn7I7On6WmQXd
NVdWBQK0tEoVSW6jg9q6JVAZpSMPr0R9dvwivJwAc0f3daTYddiyuJ988zwtL8K3HPC7FH3nYvVk
mM+opOHOZWiEV+mawJDsWiPBjo3qYHV6iAwCduOPgswCzOknWOZrdbaIpnrm+eNobbNS4iTvwjg/
O17pVyhKEiLuZUBZKAtbulFLA8KoJgAxkjFJNz28zc8rj8U75r5fVhb5b13C5KRe/kGrqW/w9H52
Hbk3gnQtmUJYWLcZywEmCiGhfDrzpKkkYpl/ljJkcMbmjP9O3uYWzX2J875h0FFGpdIzoVHM6P08
t4pA4z3dYmrS5qz2AEDGv6QKyAHKlEEXf9lCQIwh6RTcUb5mM6hRmnULG+XoUcag3M2NnrPGZZms
wneBMpwcKP59YQh1D+kSlnGAMGaNK5IO7dNc3bxgKUZUiCJfUn5cXiDTv3Q1CpcAAzsNK0sFnqT4
pqhtoAVnXNflcnB6jSRNB/ILRA7Cy3Td7C+4otVTGwpOHC5Ov8tcVv29p1qhhm8AyULILIlMvcwP
Wp2oB0Suzhg4zW8AeRFJ9TiLDMyOv2i1vVyM6jLLe+8AFNOnlbe4cTBB/QVMWBoIQKsiEeXW5Uqd
RuLYVxYuxMgrr6/XpXQm6n9ca5JnqsXinfd3Yq8ZEgbJRS1XzUZMmC9NAcrRw6NG4/vfBpBEj1fT
nyJcAhX2DCRNrbZkHf8BZeWYoy+PIEY2vhb7hBBNdJ3jhgpfsoIkUcoks7tD0pveEayrz1rW2niA
Z6oxYEDrnzQbT+7eaLb4Jqa6i1B5stAxQZPemqbkK2pXs0pmLLgbQC7umcuHoExkBuknl/eG+eXT
cxMyQk18QcnFT5rE/7yt+Y3hdKRBQU0CwbzoSKYBnDk/ZCTLwxZkArmAJfb2UiKNgIDJZIWPK82K
Pkfyev20OR3fFqTk907HfwXjKryTx3hqoe5J9X/mHmRTq/l1sQpLT2eGAamsGb6vZJVKbgWq7Cs5
8ubU5mnTjow/JVJIAzPXRDqP5EewEqH0AldmWT+thJazGcRKyLhu8pBQhP8WXCEqVOmamnOBFeUj
CEuNI5/RUH9WlICmEVR8+Vq/HDtSivhDaHIDh28blWYgJkVHFyoQo/802LT4KxXowxWHDIR3RvjV
frZS1heBhHpsaEXbT+uDOKmKc8NTx84rBSvS/1vCNOaCC+iuc0kwJWvSPSDcDB7unjPE/Ph88Lga
EHnkaOmPYvJA1SIcOh8g/oGc4kDU44ZBBvvD315VC/k/SS7WWqDELS/F8SlFihbnX+TxNCHgczgw
Ozfipd1IMb62JTqnVksdamWuqk+DcziWp72K7dtd0wiXBkZVi4aDVyn+tZ+LGF/22NU0udoegp79
lElzA2Ky4Kg69Esj4T/0jvmVDOKLlzeekZWCau63MVP4LKFYtK3bRKSRklQgfchv7XXLLCdZnDAY
WbGR4FjqJkMii9QzQr8pYOKQ/aDzVB9YSh83lJLyhdCN7f8hy4o9T7+bnqeZhMG7o8LguX9+5t3t
jKgf8EHz6a6dnZnKjPKa8UYe0+0aHVIs8cjNHS1uR8DM0CQ9dW8syIsz657OJl07SBiAuda2pfOQ
FC8XlkpyQ0I8X9M8c3J41wFJLXie6ssfai/S5EY3qaA27KerDv1jRtXKYwSUWozAURX0R/3Lwwap
yt1YmCKesrWqjQ8G94BKWKdq1qM5TGn/Lc22VN1fYpZZtGH7+34L1fxmHqK+R2zhrKvh9b6Ihq4B
hyRcDRUQ3JnWcFq8gtcN6yj7zsvS7vn9XZLVu6EUjl3JOF/j8ZwwXXVmWP5RDLYdhrwBUhw1nzBU
/P9163UpV/cDncwL+QsTIWVVH8aar9c52yRdXAoaavcFmWHuXxQWTHc6jeCWwgf83hWVSm+MR57k
xpQGOxVpX7Rq5esRKDcxga1aBX9XtYFYSrLuoTPkb4T1OdvV017gTNopApfLHBHxucKBUWms+6v0
C6o3wy45A6bcy4aJNRL9jDpgqIPyfLRCfI0Q5jKFQbak6Ax/bRuIL6G79htiJRQqfR6TZFTAq+LA
GCQ+iyFpbIcC+73xmoUKA4S+DYztZZQkc0A2M2eY7gvwq1yPaj6u4QDjCHMR9cy3vu3IYwi8Gv6Z
dsCuWckDa+ajOYF6QhcbKzs+/3Zv0QKsGWcOiAqJwoQcPSTVXWzXayq6Ij9qE55v5Q2lg7ArMCCN
kUrHyRbNtamuOLh4gLxXx8RiXjj1l03bCpeDU21LKfnRiY8dLfYUdcj39FuKdER6H+y8Wks3UQ9j
3UFEiOIBw5NNSQoKQZk1tm/9x2LyUTQPWsMPymT35dOYcPKUVf0aiKFk0nLB2WjDMz6PV0v4J9jZ
LXPe/qUm/tB9yGvFRIxy18x9RV8YC35Uz33o9D/rkEtOn0ab4zkCTjPqegvOcILpljkZ2TcOPn9a
BL+WffLcaBW0+T6sDifdVMmZLfQuJO6j+Y4LQvvfOz/F8f+oUUsVPYtJmniifW+j9leKT6RWkq7r
O+Gcfh03wQbpqheMoTdwSdJiH35qg0eibNYQne0+W3v6u7is4L7CDOMFwxBl8H03CnvnsiFE9BkF
2oHfXd9q9A1S94gp1aP/J5G5PK7WvylS1nQeyt6RQwGtfvWkJS1UQ5JAsS5BLh/1oDUy6PlhzCj/
Behiff91BzyBgwKyZdtCUJiTjXdW+06FNss4EGWm+6bHRwiqk/nWfpTgONRUUzLdVPT7LU1J7NhJ
py17rJaHIYLWfpKVJ14wtcFFYVteuMIEXB5xVD+XHKdfZxwm6I7cGI1uBJA01yvLDKNP4V5sGHgJ
PN4R7ZditZrLzzo3U09Gqc6+jzCx41CALX8GRpgu1pEWtd2jIRGMdgjL+ynUYlVzWeYT6BoyoDO5
EB+wiRWk7w3L/Nwe2CN963LlF/PUA7XksGDuXD7xArmgtAOquYuZMIbN6mhz3wejddsFBzsB8llz
f9M3hofYFEgEPTS4aWvKRiWifj6pUy3ZTE25/ILhvhAe/yJnNGMDeChg61gE7+auCQgCkVt4O39Z
PH2siP0UNog3yuk0ahZEUHXTWcw/hwVr15APvy9qSCJ7ciC+xSz1C8bHsfi02IZgFgG0LxiqpyTb
l5syDS2kpYitb0Mu3CG5JQDqpNss8T4aQ5WuW5Kk0XKM0RWZbkmYDBsrtaYe8iY0Z6PN2WpLPyGV
cCCB/Mp7+/HRvIQvMFFzy3Sj0NPmyxPx+1amG2rlOQEsSFW2vpL0RX3LEBW+gHvZKHD9kLwfiRuK
WKVcFwT6x7vyePU1543JX8oCslHGBD8lfyASZKEFJjNJ3fxwG22Fwx8BOryVQ3MYfPhm2Ct7AD28
2NYriBHmRjcLxhKB0veZx9qmAARTfzo1rsG6esb3xk9P/hViECDhbB52bqJKewflVQm3YO6CSXXJ
YY7uuxLpD83agh96N2KCItdS5AWKdXv/KB6c3mirNCpigL4Gr4mOA4Mk8Zm60JBvd3vdPffSrh2w
A/DaKVl5g86Lbkblyi1ZYMFOjTfYfvaGLYcrrvZO32QfCf18DO7x1R6VPejKxaitDQL5rO6OTSAt
ENXIdsBpfwQDEO0TkuNCctR1lEFuKPZtfCYmrgqIOH4Q5S4EFEXHkZi0TeNkYgZLB4jFryIf9yk6
M5KTsV4zd5MUR0NjYAn44d7K1E9GHSHYK0hBQAYHchaFEK91baz96kTstI5UH+U9DGQZKzvmisW9
8SvNauxUqDIW/cupX04iK+mJCjGMj1Jw5e+d4UQ9DGuhNmeBXc3UXqNcv6eDMvTKqxu6UHtDb2jo
Diz79FDoaVG6FrEa0B6gNQOONg+s3oli71DP1p4HLvOTYHzrAqr9txYHu+oBsnnMl7hVvBiSDOuU
X+DrVSASNhmq+awBO7azCvCB+mHv1Z7gUmyeodABBgdQFRdw52ObSinLMOT6wY+chp29Zr4hWTtJ
68Dyor+LwSX7Y1tlDVMj6GqYl886rxc4DRQwvI3d0wE5b85mSw2FEv3Ki4AZkA63McDdZsjI8mPy
Wy7H0+SRRa2QTT0PCcog+UOY+Paqi+CllkvJbrsyjMZb0KdvAXsBOSLgJ4DjrHIOHWhMbWNlPCdq
jGuQBDVxoRd06lSyN5gECZGCx2CK0RTvc7J/KCi0hdmwez8VT880TLrFmK7fDoNHQRwyOmc7hr5Y
HCyeu3Vc0IgfCzhT3ZR3nEcv3l96LiYyisr7SWdPOQ/pt0vq6t9Hvs6HvanLC95bq+ch2DSwtFP6
uoHHZQ4jxm5v5RGTmc5Kq4CRKViLBWnD9S9J5DPdSGQwRlR+KomAriGRpaaVz7V50+PXLp2t7KZQ
OleadEPajWg2S9JyhF0JkJGYHsjl+PVkIVzxWS62vUKBRrIldUMpkLiqLCND8NnMVp5LIYWV77fO
h3OOtzVdASDneNqYfFPbO+7zN5rTXXPEEOq7vJMfQL8PLH+6KRZl4Wz00wdBSWrQgXwCsOXSdVVU
4A0AX8wmnQsC3woILDRaw3Zroiw3B6WPZaCLg3DqP29MoOg7Bkb1d33WnQFdWNAedjFjfrCozVFb
PEKwbzsbiPJh6g/KtVrZsTpUO0+E+6pe5vtYYoLpThBnHTTaXw4XlVzHE9JU+8ip7pu+Ji1ckPjc
e8OAlrJJU+S/76l8shDnq0QzdSOdnyOiR5bj0QR+WZ9fdcvLvIpiiKtVThG3SzmAwpcoTb7k9bm7
74tc7YnKWxYv7ch0Qn0yQGhElsUNmqwUCqHjEavjQVLFfdheAi+uJSNEXZbGHfXTNEgUjqidaOy+
DehXzVpbvoRoJVUGwZJxm5/BqdTiL7eODIFSwNIi45wzcPLP4ntrvIYC2kUWcRMS2KGupNsUue8F
RBGd2Xlefcp4bDdnzos/nPmtgiabD2Dl70VspmBMSBgSBYCt2cxrIItt9zVFRcBut4BHcid7QI6a
36tLVm9F4xV5bfz5jJKY8P98X3ejTq8/OgYVzugcJn7qfWZgPs9y8UmINcFNLIdOiL9chtUVtOH8
ZChgg6hdXosI2T6gpIMMxMfqOgyHp8hAPi2OxdL9Z4usVEVMnqcGM8unvXT9U85fGYhvWTN1AyCw
eGWo9PHiZlZiPV3BpWlgnec8FOwukI0SEDggoiGtV0UUC/MUxW4iikoAQCw7tcRTCCJau9pvTx7C
QZkZ5lU/H3eSvE3Qip1oVmYOTyLurB5XLUQgehxGIJ3bZp8CYslRb1/YH62czqYsJc7RCBpr/UXp
DHyhV4ujcJnGh/VythWrulpq4q0OXGNb4BcVD3RKu3fHKJJCoxniPShuihxP/ZRffAvX3OH6IXAj
ZoqoLwDvwvEo4UIXylO69E0M96LTulG2fOn9VKjfZrXKYtMAaBWbhL1Tqk8/z0iJ5e7FPoCs00O5
vgICbboyQH5iPwEhXcKHhzgnolymddFiQu6PVQzZ0lotqDHdEP6eONxztAA4BERvwRkqoKXHiJsd
+pzEGGfGU84R4MLc4z0sA0Li3S3SBdm6V3NDrgDzmWQzS0Pse0jf7jUtFr5Hq242x+3k8lIPn2Ga
3UvJJoPuQYZEUXj5Dt1REj5+iXJ9j+ep8yfii+KWPUA0xUs3VasX9FiL2I7uvgIsfrYpfK0hVo84
Kpu7fEqL8KuA+t+L1JE/9R8XvI16ywDI4Po86AOEAC0Gb338BcbyJ5limr+I/4YWtaZg352UG9U5
4RC49JA+/KmaHhuvvsZuj2eJ5FE6l99nUg9EoP1J1QfARuBmNVUXkvOP/0Z0qa5RclyMJ4uZb+2u
wRDoo2j4i1/YpHDZOaIdR0UvmSXGpU1RgoRZAVggH1wJPy9B3r6/DuCTaKAk5gaPJo0UTeoXhPMQ
nWSEhide8gZaIWqiL/lTc7tmKjhVTzxa1Cl5EIUXHDkoXBq3DtmHOo4V8QaCrGVdC9qXOB1ucyPX
lstac1luNMPSPgCCK8KjussE1nmkyRq8n48LYnNzUQavStWVXgIFmG97mMX0LOFYQMPTVAPzOvvg
BQUmcmuiOQYnPOBkASeWmNzhuVrKVSJuWJwpE232llLax0BHLPOqbLNBRnyvAAKoRF/yi/ZoGCFr
ijczA42G6yTN2eRrLTnI41LmZoWerFq/RbdM/sDsx8oUD3S8GGPLwNfgBN00g0pnteeixhW8xm8y
BT4Pz+P28mwK6OcuTYDguDh2bOfebV3zXU+jVLa1etuq4yFbPhHO0d16HqrTgU7QRJC5e+ApbIhn
eVR1Av6WkLV5rpmKIMH6pc2B22Iq0iF+M+ctR0lphRlpsiBv3fBmbPzClVOeI8CX7iPS3yCUx1uZ
LsQ+cGYu5x3WH9uGdZOlP+gquSV6DTCnDFHHyA4KWDytyxZprvRXx1vZ3b9D3ZxbIz+CcWUz7Ljf
6PrWP/UunFiZlDKoFTqvV6FI/kOpC7X1ruOuJETApIQ4drukQuKNoCoQ4cHTtz7TrB1PoKtv5hjM
VI5e10+gfkJUezpz8vvvn8NrIvsCnhY0KkY3VM5rx+WB6TZIO4LbGoNfQr7KNusxwzqfKq25u0iv
ydxDBCmpYEFEZLEl7y1QwtSjKuA38Lo01g6ikPDMl83NvOLvEeSzwp0y14EfN3c42tELf8tqUP0I
QGG+O3Z1Kh/SV6dOoz5n2c3uNwxxf/aqnsE+3pdI9imi0atP6Lsx3zUVzjPxzHFwAWZYz2uxd2Wi
GPK5QbUxuPvPNeF9xkiUq9DUAMaqEwH9Cq+U7TRWlcORkWwcGv/PxnI7UFWHimxG/T1aLZB7QF9A
QuY9/G2lYo+LPZvvOIWyYMI2eU6O9yED7coYfxfAvmQIo57ZVxWnc2hf/+b2Gk0WCC8G0GD19T0/
p8VRSQ4DmZk7sSrx3HA8WD6TEujOMk7T14YKDvUGDRbbIhpvXWli0Ag0orY+5z8dcDShxwgEUFYc
U3HzkQso4GpmUTtbmXqn/b/r6N9XGYWppXxv+Sk1u8sQbOU5R+dp3N8ycqAVkzAXD5YIAUllD3Au
eOKWgLovriRmwclg7kaJUu+Y4tIL8TZLpZnbf//pOE4a21bhZBRk2a5tAeYutL02/8VYwVywpLlp
iNL4b2ZoWPCJiZXmvA06lDcxONObqRTXT0iYxqjUMzVhYQqMu4uPW3QsEYS7mrmd2NEK0OGQuQgV
1TehLALtH850DLGJUA/2te+nlOLAgtNItVmnwX9rg73C8rRPgN8/uIRjU8UHwWY0gzk4CHCQ/pGy
qxvJJzq1oVEC2NbKEYmI4X6EKm7f+WNx6UN57G2QJU4i6mGaTGZsqXBvdVNdHICzzp5kw7S7LvWc
zEjjkfHutkYgin11RoVb7vbTdtf5/LQFP5eQBMz87Mi6qRB2/Ii6X9zbWvDDbHRhkfHdKlQYsJjl
laUVAcFU5B8QQXUwTU++k5nAhquMpkvIVgnZL90P0LNHmFmWpKL0VLR4Cs9OC69OT7g89Doxli8J
XpkhF0hEnMQfx4NLwKpgFKm8K7XhG2lNRYHzaUI3X6oKf+kIyTewPMrgXJ/gudVvNMhGPzWWgF4Q
aTA+a7ApTVxiJ2WqsJ1rfc60wZNr39WOlGgsN0EAdM57s/VQIrGbmwamv2jMckJRbM7xPfurzUfv
sDe5+A9AJkqctqgIP8G+TPqMcR9ucs1InYid+yWn+rIQlvFoVTNe8+bKb9okpZ/eR0qcN+8RMylz
J/EwBBqrAPmdpFOt9g6/fG0cpnpaj0VcNMpzckSKaG6Huxf6Iwz/JMFsyjlzHwAKYq7s1zmYbP19
+TM776W6ynGZAGm9XPP13/pVyUuODnw+uxiel0tlvEuQ2FRYiGtXDeYzn6SUmWgPi5ZjOydvP/Rw
FS068LdCYYA0iR2Q0LUwMsygWZ2WvjgP234/dJ3+hr0WEhkF0CZBX+CvbIjiA26yVr67qLJt127z
8mTerqUz/SeNIGgo9u+3CiZhtqUzOe98H0taN3sc8LaDW3gv7j8ZbMP7p/jBcZ9muwH9s/+WTB+5
QdtNmKXQWsXfpSRilc8CxLZzuOo1mKdiOE/gfo5Ji72yNqdvzb5aCnWlN35jyPYTpd53j78AGzD/
6qnHnX7v65Xlv/10+g3b9y2sZxF8fcvQG7mLyompk0GvWmg64vr9Qt8JscZKkm/qo3OLAYG15dqn
gNt2KTITjZi2B5WeZAS5HvCVoDYqC2alDpSWdXPTcuU9ByVF2A007HjOvrQztj6zgmPX3dp5NDZy
lyaawoTCAe5tTJ9uML70qa+H9t2yOQRPeOtoe4InEECQu3hVskS657LlrqHHlQlZtUnGNis+GxHF
OxG48TSSeCOUkuIrTVamwiW5pWu484EYFKCP47AAi58J3ssQ17sSNHa/CSPNlDWjzc+Rk111APgp
zu/oKbWW9BVzHhj7bZfJEQepAtZPqbG8V9CW/qnVDs15eBXhLUUUCON1qh2dKurstpfl9h0i/jE5
/uOIFy/EzpY4122pk3Li2VaAgRt/RFLIS+zTa5TbxkGpNLIOYY0WmzBXqyEPKhYlUUiXXUqJ7aN3
PwNKi3Zhjef1zSmfDrvBExZkGJq6YYGA9wCiA/3brcZf3qDefSP55ICsD+dUt+v5rW8k/E/G7lnL
DmEw1oKAur57vKu9Rz2GPN3k2sNV0xvdhOSUHH5Jh6UxtponYCKPPwxF6ubE1x7vnJJcNwXqzWA2
JBqjWaRSWqHt239aDeXObhqrVCCrqlDmxcGtnxIa5Amjm2g2vWQ0IYwAo+9BtFJKviE4KtdXHIPg
R1ljbyDP77ZPEuq4X4BmSFmeJFsAfrLc8pYHmkFdo+P1MxrRcTddM5Os3hkHKXir1EtNNMuCoPKa
jT3qv84YHBAkw6WjZxbBfic3gKmFb/lmSFaowSIgCMRQuZgx5QixVDzQX0a1pzy44luXSJm1XQXX
SKGiXG144d7yS4P+hWXzFJ52ZFIQHMca0+6b8gxR2On81n8C5k2e9qZYD1UENFIqIjwf/s32u9/d
aU7SysZxy0vXXVqBIl5/oDsW3iz1bejDiJZ15N3FikbPzx0Pi3i0WMcalcjAfx4j1DD6HKF3ssVO
Wvyg4F5QtkfHNCYU6MoSH3bjnzWGyDZoQg7k1MJ0e/uAg3lWOYvrtQBDp8s3h0zl+essjqSnSR0E
2GeRi7WBakGVxQpx+6Xq4jQSNb8lXxw39AJ5zViJrEhfz0Vkjzj5fPM6nRTfQ/IWJn/ZSHr3J8VX
i2sYre3VeiOAJXp1viW9K4WA/nkoOynW1okJiparDa3BT3QWXvO1JbEsEgxU0vI9rKi2I3aENwzf
rlDlrGXYJk2UsaPYm+E16v2LtrYOHxMiCmKlMneMWx+CRgBJVsJ1WlDBaDVF2flCjifPgECh//CK
aJJnPsW5sqm1saXwsEqAVhYj3paIc7/BfaaGFh2FmKnmt7yUM2bqHxiU9ECNa/Sz4E9Aoz1b2xdm
qhODcj/axtNk22ReuL8RsoZTup4tPtQUE7f//M1wQksbWRayww2I5XZXG3bI3UFIwMM4RF/U6Uj7
PaNrrprjxoxcJXvi6ex0EGK1I6BNkgL4JEnjSZrWGG3B7Tmbm7yftKbhQacG+ur+nBqxBYFgspOH
8eCvT3T2hwQ1uykya/6bRpKoB7AV0kDm53R8JHC7d3lq0oJRfWYmXJIfRxC1xBUD3uwc+1H9SuhX
s96Lf5R1I99CUx6SMUbF8R8sl/VxXS++V4sJCQCtZpxFLlLVq+WPv5BLY90ZgMYIB6boU2NMgVER
rEWuVMKG1pQS16OajCClD6/++8KRIIwJ6dhSJ76rUTtIrvW/iSNKd/zspPX9PWix37PH74sCDMOM
g9irzaApMm3CIueu8l85dYDcUf9jfg4LTEroMnRB0cI5TktWMn+Mf7AzgvRwfZegs54OfnibW0Hl
emKtMyBseqfusGLQUcsQKmTvGbtFPYYwL3IxLrK7heyrI9XRl9QRnZmqR0FB2S9tFzf+LNI5SEwp
amoCoMTsMAWM+VcHeCPwplwwlxKO0UmoxfkvG3fxpD43y6ZKgP8zsDV4MBESc9lwBFte1fg/4c0I
lkgBikTSDmv2StMK8zJZclaFXNCSTMqSTCX+ulErqIMa4gD0/bMOJ7V01xEu7ChsHmgNCIMZEZWP
4a4stK2uTHOaO2Ghyr+lH04QimFgX8dCuVoMALh/bon+VCSXQGUlG3xdQLa8q7wVRTzukyrrNBkh
6XkXHNDkgAiMZvwGxt0luP9P9XUYLL1jF7je02qf0R45ntUF91TZdQV6VrTkuoLKuH/ESbWyAgty
Gh/yRSwNsUNhpgttlp65YFRYEgmItNtk+oGb+d5Zov6jnlaaoeLyAAhMgGvcrxoB2LUCirsRBfeh
Kc8cxAKJVH/Y5Gv+UDkK2HO/036OTeetKFYtBDkzrSKQdikj6Gl2dp+vJoqzlUA3oI/pdHbjoKu1
o9VfVUn4ZVQ0jHLwSVEvBB2b/OPsvIw68XNDoSbt95hm0iXHOjcoHlRsJ/pDqsndgO2P4Fo6zDol
FHGcYRXytNcYQQ5WHdW1A02yDVj0v76OumN5y0yECYeMF3nno63dsytJbFM58sbzvJD2K+MPTctC
uLjLJ5ntso9c6kNei1g53Imf23XgObYCOe3KK7mhJrcyM3JwVBVnfyDeeokm2xAfj5H57eSHZVbe
rwdeEFvBPnrk12u0pgY16gh2u+08mzsX2fx4PW0cgZM9XWP3GdftVaWFHP639KXUHK77T2g5ehDi
UH5cT7VDhguo38uwx30aN7YCHcP6JUnKPxQvNKD7GzYkqKWrr8uu34bbryX06uHsW1NnhXF7ZxYM
YJYB76L1o+B7j40ljFKSoB3JUzM4sOj42fwXKrm3jBoaTBAi48Xm9L5+dUUraDoEGTwuyrDPECSj
mJ4QN99Mwr/guNJT7LSPlVWSoXRCAxc2lxoReChp3q8p572J7/2O1+brrUkGhwiR9GcNoi7b7SeB
1uEI6rktDOw0YkXL+psqbYokfuVuK29p4k5vtdDWo7h+ZNAicV12MhVT5OFDeDlhoY9BhC6zZNKO
HV7WiPs2G4NpwGK6QznSkacCPbZ+gqVMjFZGf9BTUO47hUEUnfnGEihTjLB9fMfQnslWsO31qfHU
faurfcxjf+q+B5GLQA66dCETeMVQ/xCzaJxYBXKpyL81ZifWNimSD5kK2ux0Y+39rC/XI061EZwo
opR8CEw0S1cwLgKRiCjiNd4S8GP/Oof4NXLVcFqLDCXtJghNHmjeTwTo6vvlqhl3553sqto3BXxp
BmDUed6yCEszuFt0APus2URLLwoRy26TxkwnXnFQuObtNCoHb1DYyr41DixItH2cVLyPLfFcE7PY
7B2jh6TDKMd68hnpV0v6X5N+Kblm119kjyAvlYs92ze77fKDZu2w8ivBbj4Sm8z8oox0JaMHYxNL
XurC2RNGDe3r0MIcHjg1RJ/HpVfXwKG0RMQUuU8sPAjkT5jV+DitPS0UEQxKepREKh3mzR6fiBWH
IupddHFIt/uynU2tFXk2HLFalzDxkLL3/tSvrAoQ0/K6PTE5vVM8VkCNC0UPwuV1Dht0mod+xrD9
yxhfDodQCsW0mdF8zGhWXum+HXg1ddHmW+vkp+bWMcdofR60qr3mvWBDi1tOGviLOikOvk6uizO0
byq40Jygz/TmSZy0GCPWzXDdIT6l6ZxussQxU3HFJLLNR5y1/Mbq4cwC8bNzV0aC6o2Mx4+HclCL
FP7YiYNPgLgKfmhhXOkvWQ/bfzMRFhHvEsloreFEWGEEYIa/NqIn7GywDxev1GcN1WsXtNJzGB08
OxAtYl8FM1hMnrHPB/b6gFkyfi9tIkDJjuZcrqBL9bZj8ImKX0YRnhCK9IFWsfWXXqEnCVWI9k4t
YoqmMqE6EqSEpUCjcaHmNhuWwMy0ZhgfxpEmrqWEu4xbRrHLqo/LivOLbcK3Snr/EzUzMwbWptsV
uplQ8UiwnT6k0keG1+sOqWCGAs0qoqZ5B7Cip1Px7L167+mjbV6mJITXVYkKrJiBuES5Ng0Efhbf
fY6f0sgUF0NWUwkSb9CUmbnYQbmjDxCN6IMTfwU1RfX6H1YOB6MFTQNWTyTL1VjO67f2fNr/EkVO
1Vkses5lrWdg15RKuPjyQz5vLXI0YQCidxbIPXynnBjiXk7omEJIcJjnPLmUq9dYc2rJX3l9g93e
yzkhKVm9cYB0kJ20eqfK9UQrrIeQFvgEAh5a9gopd1CUbiem58qsVH1batZOh9sKFPJW7mt6NNiE
2vSEwkw/Omih2AGBCXJEVf93vYqbkskRyWScKxPjfYBa+XBO0cD/3M4ZQncfSDBUz1pyHWhr41f9
XUA999IOVoCP+09Y++cGb65LJsqgcnzoYPuAIrugOz77qq+K8vMKrp7W0KhxHZc0GA8Bx+bOQBLo
iVFHyK61A3ziZWbQP7PfYiQAg0/y5L/uzZ8XCgXfhKICGnKMkROS1XD9oV169Nj6Zup5wcWUrqup
0s/TeEJjHL35epV3RpU30AGYW09Lvo8+42VOJl6TWDatpad+au8LBz3F1P7cJaqECyQy0j1zSrx1
f11LAOVQJLKGIzicqFiQN51BSA0v+HHr5+21vPRqz1oAhfaYvEUs1ONd1v7RvgEwgU45jf7OXfd1
OSRNrNdpqmhM9XF++/8ZERsN+2kQKWu6j6pR9bm9oB8a7IvyTk3gOqrzlX7Oh8dEl5+UFVd5QQf6
InJ7BxN+Rmcft2+YVEye5aA0WI3UByOA8gOa8aqvzGxMJ3CSSVHeIj6shFcXMXR1CvpyHdNMDkzF
HNDAlGlr568sZm6R9sM/wFtgWL7Fcmgkc3QLWT/jJVLtZxZe7Ixbl/hdduU0wqhe06Nlzv6qt6iL
EckcukO/Ot6n9XPWGBuy6+N0bM1PIFe1wGripIrv3Z/XfkYK3JpWp2I73t8WqR48dSOh3VeleB0s
/mI2+mLNEVjRQFsHil5QL3vwVof9oKDp+qjNyoVgvIWokbn6nwasnPDo6TZwD/Q3EAGuR1kvbQK1
WLRlxiMKAHkOHsU6Dh33FM2plU1bq2ulm//BnFNhepmK9j1rU1gfqycc5GVXAMa3B4OeZDqrDDnP
zetCJBNCgwrLBoV1WW6TFOKfbsQKE+FPJvpsUhqiRDdw8yIw2MzcT+sK0o3fgx2e8HIt2raYaeiT
E6ts6CgxHOandedrAf9AtPRrc7Q50uWZiOXJGoo4U2K1P6sJWl0nbuxt4krtKTEXXzk1y3MzGxEh
ZCYBnk19BK2E1zEui6zH8kRr+R+T3skL/O6OS2zPk5G7JkOaEB4xBhdnh6B8W7FVrsk7IAhCNBpx
j7DZ28hPKmnvSdDQx4fRW+KCq3ogPk09Snz1m3DR7ZnCDVd0UjBKpJrGpqnb1W+dOO0rnGYc+Usk
h8dLxzS0bByJ6/yzO7zHMlSj+8JTWm/qSXTXN8WxNs8MPZ1DgOQbTmwnwCMREUWHlsI4IMgItHgh
yi8QNtYRJIfv8yqi15KhGW5CjgJfuCQIYgeqf8VF7X9rn5/jlCrIIgSb6Xa3z9pUmIBZedUJLyS6
k1ujI6oKj2yf4SVGJ6LKAHawoHO3TirqqANaemqGQTCRAgkHB140C0mu1DuQyBxBPGVL5GMz4T71
G6YQNwXHNN2mfYx7IOdSQ3FIIvIa4uCQShL4AJLweSGWsu6oX6CjTLzrNPmWvdxGw3qmAD3Ij7+W
gtikoBTxTfnSCOiuEqY1nE4ZVy+n9GZehOdPYZz2SJdTHdzo0Vp1nwySHmP9DSUTq+VWQ5vNoR9m
zBYPCEmh7YNet5K/A5ieTbtENJYTMd0nYy+u10sSW5rsALHiwtiwOSg+NgvZOi7zLiqzfnfblhmS
g3ajzjzmHU16cUce6xN2bl9dOx2PsTRzbjbS8SRRGHmVaEquikiC0iCipsEdrTsJIc2uZ5tR5AGz
zNOhprZWfpQK3vPNVz6eT4d7rPnmSyivoaYFPk14PeNx9XtmkOItkWzc8j4dbzIfjgRai5ptA6PI
FIqA9oRclSWis52gXpOdNgRR5Afv1MM8ENe8GzyxdHlSgMzvMvzBYV3ZN63iqVknMVra/t/SmBjb
4xnryWZ3JruoWiEv2PrBOGoeZj3ocrDjsvaR4FdxgcFKO2qU9CfEP6hS3J+ySUtGVOnkM+kvMv9D
/aafhAZc4JWEEO2PFydfi/SEcPtJSiKIe0IEpJgkgWSNqHoj0a2lBj+HhBmXUBd3ZKJqKVx6vZ78
T0l9JrKOjyIoP8I0ElndyReGeJntgJQHrqLTfbJjfOPBDOV+01FB95qGry755QvIU/PmtrrQyWMW
NcRRaEJVrJRAHOnOT4aoKkwgRLKg2X9czfeVkT0MajH2oAhHbOKwhfSDi1CHj+MgCbCheWH73Z3v
KOmTzlNEVrV644V/k0U6xZGMjwu1Le40miEOSwNfwhqI4ggXGIdahRQmc2AaoFYi0jdv4yHdib+L
nBJtLyGcxJVhbnU8pszeyxPt8BehLbTMdMCMatVAfSghR/q5+A8Ndzjy11IIIwBOk1W4eMH4+a51
bP8p+q1+VWpeDzCbBfyAk/KPKG/KJjN1PA2bHNlGNYnYhGxauPCPsumwfm7PGHhAtN0ey7CCDOSk
G5vLdC2ZRfJ4B2TDLHp8wXKmB8qzGGNHN8JBB0SQmpsRjF74pRTbs5MLcltzXGEW7DHTqh8jHoB4
XAOOVcriOjG666QefiTUYvwx4b1Mvq0xeNCKpeZuzEwmuQdNAmQjCxpGgnckdGNGO77a3IPtCmdO
UX21AlFdTRIDMyPg/VB8ZoxRD/GVlqU43DaSVSemW+mpQw2tCC/FrRPSOTjndwPI6skie25bx7AD
VUZ23gBh7wbMvgzzlcfX3cGfMtiNKGs5cmsqf+R8laTeYmD6dRIEyB18YYE02iykGSMT53XKVwvG
j8j3i61jTKUjO1/4ncEHj1+/0mwovYxuJ69y19kP9mJehQR3B2C7bAeQ6yBn7Q/g90dxg/LOdsE2
BFgOxER1/PbTy+URIqo6cJj91YPuj0pqQuva0C6mi1LEWeyCrjlOe0B6HCRHwXdCmk4/HsCsKjPp
C33l6/YIxekOyiqlR9SdQQH7zyZQH6uk6hGhbxyEz4+guTMBGeZIrnCuitt0SmZrackPRvH/lke1
4JmwL+45gl4GDJZV6HzNouPEmMVJsfCViBv4PY0FqpccTszUFaUQEjZuNV3kd+7eO8nnjQz9Yk1c
eFv7+l4qyIOJiHz1LTx8xRwsraQNrTuOE215Emripz0Y23V1L0aA+RoWp85+lWRxkepoeKAzBxYO
1/YDq4VMzVZo8L22XoojajO3KtTbsXrrDl3pwSUsNuPE+gdL6SLMpAG/Fg9NwQxOrJIq0+7YWm2P
Nb4pbsYNC+/ge5RFxaW8BJtpwqdLdbuQFoBpZJkGKSGixlzlvJUC87up03UEVRimBI0gpeSgL3/B
/W13DwiqSqe0R8GujEHR/QbRYqzHZ7lv6X807uK4wRCoieZxD8DeI+l+LXOL5dZgvAQA89mwsrXb
qxhvQwGs0/KFWJGTPWlwsDv9Zq524wIX2lakIwxBHCaMpaaJVSUG810kiMUqO3Ox9eYcpjAyolvF
+PDfqCQ707yVaT3rISJlnMgTbUFlId0gZxBeuLhQyFiNaQCl2wv/IvjiAdNvN1etMNG/86K31pdh
xL1chkc9cq4VfxtuXjHA/tdU81bnFBhMax1CKXFgVW/V5iFgTZNkD4MOvvsrCivJsKxCSA6n7el1
KPrjvbt01ZOF/RdBB9hV7fs8t5SM5OLjtsKUJvdlG53EMtYkxqC0DAkokAc47Gn6JUWj622kdySN
ktc9R29068jx2aFh3/dAsGzkPlYj+kOlJSaFGlo9zQAi3KzpIkf2v1e5lo9IEMlvolZAOonad8ih
1hmrUEWYK48JVwxC+HGoKePkoAFrQ7jk244pNaXq2dvtc0DUxlkze9dj7i6X7BW2xk0BNqqlvSxc
4c24qZ9Ye7GUdks5aNKydXjjGkdOdseqfnK1+ivv/7Rs/xWh4WuOchkCcFFSBi3M7pdYbcdTaqL3
dANB7twSRqt5CLhao1iL7fgGDkp1BQJoIcQwv3/3nBKzak7y78XDdRdzSWE3TqjKrU88RUiNOtNH
ZV3veAljluiRETnJhjsPJZL0tvbMfcj3khcR6kuv1dIzQPVA/zPoUP5qDEZiP6gkhMzH4ui6CWYr
9SOXky6KW9UZr+tV/uyI5B/6jrYwahf6SbxKJxDW7uzJEL0UypfFBBN2zh/VSBH/hJj9jcKYUT7i
mFDFVb8Jf+lPmu4JFfeb2WKzodlym6jnfVHuVABbRt3nL3Ld8vdP7nTgesBXr5qKBAyPuGW1itgC
jTaNa925puL8qLR4pk/++z2cTkxFWCoqyxAwFDzWlTynMJjqx2adC9a7fQR28SSIxSXZgGeL+NIp
x+XVu5S7J9B6/V0QOLu8X/h89kD/oZrC+oQzM5JVs6zVfWlFRmN1ZsF85Yw9aov1rV2OSM1/1YXV
VcNCbUEDyacJVJ5OCgzFemI5hvZoefCMez/4Acx+S5/CPRylMZhIhQvzhOC2Ws7SnvnYwDIcTKRq
pIyo9zp2C4xiE+XiqE5dpPspjKIroDQ0oebGExueh+x0mJO8Ss2deUoxd/AssKFfsIrc2K0+oMRw
IemThFZIk86rCo356XTFdyNM5LEsaXXKH9HN95T+B3MliGkD+NfB4d0PMpAbv/nIJP+DhEbwfYmJ
Gzh/06Ov/B7daYPIsd9+Cddj3hH0gGwPNoVUht86p8d2rPSf9EGPlL8VZg84i0ygnJePn86vnI7R
YDokwBVCCOiI67BLyeigytIgIISnes9BilKyJcF5QvCAeuqoiB0LjOiT/tTQ+jl4+vNjOrKZOW8b
CHwIchn2noBEADIjgyP5ccckRPq5Xu4IwWpwDlX1qFsFUqNwn5basG/H41FOqXilNIwmKdFwZ4nD
GnyBJ+5s8usKXuw80865bGjNNSNFa62lnfKpJB0G+/kV/LgnucxGQRiuKN5MyFmrfHwUafhKwHMF
aFl92LzSwA84tNVQGSVx+cx7HascSMb+fezxLthfG7ux/4H57CfLm4YMbVs4jzii8Kd14W1Ln9bj
jHZDbXAF+jPZMvP0W8ahDdS0yUawHEfQ1I2roL6Q6qygpagVuKGLZ5tmndQV6MUhlaxpr6XlZosZ
j1bn/XapXfXQyDFME6+j3ScrARPC0JbZBhLiMNKYwSXeAwnPSo3JGjvvDcSMyCDLdAPa+XNf1Qm9
cBDXK5r10n7vOtBJQDltMdbw0/OF+86ZgRJVjuaCl6mfuUKfd4DF8cPCrGz1Ud6SJKpCoshJFPOF
cztI2Cvd0CX/i4OZ95/f6WHqD4Qg3cDpruXvDzX72UOYwt2eWFFWUCxHgjy6w3Ser8FxLGDy/pzC
R4S0+VM4xiiLAsnTyKz9d9zt87lewReoBDkTFWL/G+69992aXPKLkad0U82kQ8RdXjaa7vAlRxt5
oHDnwMEKKg52dfUdGnUmA2krSSZHZG3bg91IAO26rTYlSIQOARAOpDpXh4dwbU8dZWsBdescJgrr
Gcx4+E9/Rs/tX6h+A0V5CQingwoMxIni+61q1vh0l/zfANznL3cFM2P3coLFVzi2/jokcsY6nAbb
MqiIuSXIS6gkJk9cWHstTHRixdHZf8NWwBBSTVdAfa2VfUC3d7efH10bAcidETwkJAKnqEAAE3PE
rNOWah9VKaVI6YsyyS0IIsSdQDUr9CamNiDH/OLN913qyFNHwL059XI2kAxQu+WwiYoFw5Z24Tba
ssFV1bkPZvJMkN36exuqHwxktxEWpQ6rNrG/Z+QQNUnY3aYAb70d+EFp/EXaHkBiTdQFEm274QmM
ih9cGV/be+9xjTjaiDQdgcn/FXjFZZW3GGU+EjF2Kt/+IMGu+eTzzfIIuK8fYjrwDrAEPTdadIX/
1D1IwZdti2GlsGOmoz1yKqaF/bKgX77gDxNRazqZNcDMuX3Eaj37uv9xejJ40jrtEYcZpxAJ4eKm
7QRK5i2WfA45ykH1eXYhZ0ylxaB0hAyITW2APrr/r5fiHoVza9azBgRtCLBy1H6arYPz6PCtfW66
aRtlDTT/4NS2uIAugWF9OWmXdNYph5UG3BGdxV153M7VLbljAA0pAIDvMogiMm0lVKQcx96Nt4oj
IC+6Hp5a/PlQLYRbjupcK/GevIDeaGPyzG47+SFHv9Bt/GnV62oBup7VBruRZhoth5J60BoA8WJs
hWcnhfsrxijwO0TEcYOYw4GGoRyUy6jx0SCo4t+AARgAAavWtBJcc4iS5Pk+lWZjd78s7eF7r66D
3RXJPTHU6kX47Yq3K9P0RQuZhC1tMqlq1ifWKQ0dUfJ3fXk2OxCZtzotXhIDIW5xpQkUA68Fl78S
mC/2f09Ch8zy/9/+7ncA0w7QqOWxAEmYU4fvEO1kmKPSlJ1UR4jkWzY72j6BTV0M2A5XyDYBemXa
ptZoOWVl6pQwfoMuYLmAIZhLostPvRfogmrw8su2U/7+NyOi3i7f1Vshn1sDfQNQbGId+H0G3xHR
4HN6AJdxT6lTiM9VwJhBL1lDLlik8fPXWjUiP5jIfBV5UM//AyGDLEMRMHKotvZs4eUOOWskFT4P
wTNOUTKoRonUhe6elwounTSHeO+qguIVcfCEuL+ufFslskiQy9AfmrzkFwcp7FcidV5gVbcLE1/G
AZE+TBtsQQ1/6iHussZN83ABjDjtVbCh/mZqeKzCnbyvYWLNxCRUBEJDxuW3T23PF4kmnFeZG/i9
8WTVwWg41kcGClj7qRboERYnxR/2C+ikDeZPt0CyCXPP14zr1UKjh/8kdjVjoZ+DZLs9zeAHl1vM
1DduBJgzMxmX54lSnVfnnJu5eKco0X9h4319sGph1kSSvSkjF9X/2JeUCYgEd5V/q/ZxL7ExgISA
avG24pGQT0+MDlknOpGmh23v5F0FMIakmm3/f4j4x5E+CxKhp0Mr51IQL17Aom7PrCOC9APzjxNV
GpXjn+IVpssJ+BeaYzt5KqpamXGcfrD7b7A+8GEJuC/jPVNWsGoB/d445vfo6UWLP1HNk2jpB6U8
Wslr4g2zD1nIPvxLLPTYi1ShJHGwIxKWfz/AeY+fqL9S261e8QEpcDalaFXqj4xpshoCKT9lDZHf
6RAhpd9PkBACwr+9+4hr7cSLfmTyUGZrbFqK4S9NwVPcpLEbcicEu0qmAgFZ4chkxPVylJeVqrgC
HE/nkhpwzCCGDG1X+sC8Ly0h1/aCTl0pQDm/zqNOT3C6pKFkJz4AUTzO7xXsyz8j7l1l3C2wCtKF
Hl0+8r4LP7nEt26D8946axkjUjoGfBB0ax+0wZGSryYdJJrONakKGjsTNymUtY3326Zg3d1GHq6g
6LhDM6rw0EyfivwRz7KzlWlvc2WKsWmrRDCC8w+qHQMIV7khMPtVfqTzjeXnnjwRlAwKpH2iy4Sd
H96Aq6gvTLGlgGDkCKINbfAeCKbgrmTfhq/o8ftlqaI7l8z+Ka44sPwxvfMzS9kFtZy3J6ajOViZ
QXCbT23QWR54qmHeHVyn+jRgChgmMgGk5QFXD0LWiXAlfy9RdRqQpCbvt4y0MzUqeUZOGCxOXZzV
qMNVZRdtx2KZLHBhF2PZ5pQsDOb5u8P7eDbC6pZe5teQsNnBquT6/cjhB6i9RU45ns3A1EMM/6OS
b4WS0SWSTHgNdltvBqA2jvtYivsBNNoJ9jp3St1JPCAXd0a5BFxqsIgvkLVWBJfGQvu7xCyRhhJg
Jti3+4/60q04YpHhDOMYXXzu9y6F4GYQjoD2zITIA889HTcj2y71NqY+46WKawW32jchXzGlvnhB
sV1NGvUwBrSkdaj3Az7owG9abCmaGe9jmUaBMg480OdBJxGHLud6erihatt+byBAAeSAzHwj9sFf
OzVgX0hI6DmdGwuqBVcc4LJJ80wRyv+ecRGjFgZb7+NA1U43spV5Zb6cvrHh3MHQNtPaNOebaeFU
uAGhGoKwN0X4o6nHbi0lGBZQHNEdtAkl0kHj90NpFHxHRyu71OJYvlyNFC9xwyDrn0YVvnuCzZ0n
FV/gFw+hO48IbJz2MhqGB4fA7Wdf+y7HFXfbYbRnJcJx8pw4o7WXmJx592CROV/SfAQLsRzijgjk
vEvFDlPGGdSQvjpmxL/WlATPknFLwpXOYF8uhtDYknT+2fDkAJ/G1EjtFRUPFoDcaF3DoNMPlMbG
HBr44SIR64nTPYN2UvCosh3tq+1JjNUlOy/yHTfQ4kMVrgCsBaY0hBl83y/k6Tv0ynRyoDDiuxFF
qgyGw33SKaHSh7DAB3tsFCuS+a37k3JTCI0aJYNcW7qE1R42/kfRbZMaFg/TWNo+p2MdUiTfYLnI
U62Swyno40Gz4jfZtGoSt+lDZnSloZ0fwkLclb2HbdgrwsxE5+FxsTct5MCIBgGr5qQp35UE4qky
TcT1WvDGRxUYgNnxa8G/Wq1xReKiZ+x3UJJwcxE38SmCCK+jcFDeBPgthzRvb003PRzMrPEA9TeD
zVNX1eO1lYXAWvBsFaoDgPHVdChXYe63rFK1z3GdEwP4kXcL34wi/guXtVdKP8ExiGIXdRf9bopT
mpvj+WWvrvWj54R8SsaZ3QYzckfysVe4vt6uAh6JWCq2i0a+VvVLZgDPlXhEZyGicLnqz1fnF9sZ
FKX++Wi96vzabXb+LVrvxbvFAkKrhG649Oa8xfV85fy4X8TjTk5fhAVP87McJ2yBwFps7Dy/33Cx
4R2EUoEGoqSwvfvNlkZ1aQFMKREfCcPiJhtYWIg9S+ZGHhHp90llVHM9qY2RVLtiVZuENYQL5ftu
cBxbac9oq9b3g6eiH/E66rZ+P+HLr0VvTE6GgFAZbaSyonSH/RiQ0RWv2DTk/zA3nCWsZeHWj7t/
hhm4B6aJ17kGvbKXJsba0WlKpUwgJLlAANyCm77WopA4vBCGn5HBbexxOe0ffgzlH268CqnL+1aF
4wYgBwhOlLitJ0kukydJzVnbGIGLM7Ka+8XSTwmD+dnteDAlMfv517SqNXTUHox5F3vGQ8bKMwp9
8mCSJtgaw7vpRJxkWtdva/aU03smU9cQZa7d4Y2Ky/J0dxraPmSjRuRTciBWtPM2UGP6UiewtFn2
CVA63pLVmwgO6PfH7S7KVpOq8FshiUCi5YVwfRRHnDyuaIBQwAh5AePDfT2/lUPLqFwxaO39Al6/
JwvpuoEalfjo8Eg4/7+GYeu29y/1+yGlFbBZPHKGKD9eiO2OpejOnQs4kl4EE9rKZQE8YRmbFTrC
f49ZRi6HsbSDe5LA256i01PQRp4UdET2RvEQFkvyIrf+gmwx/CpdHoE80PmLMe92r4LayFbXOvCY
8PEF0bfucyfFP5NvH0sk3zu52zO1aeQ26d81f6YvTcEQVHlLAl9Taex0xt3addnxQFwwPul2GA3x
7OuTVFEjWZsh7h3qGY+5G8LD4tkHiRxH281MHLWJ5arh9TtnyWV5c4t8act75Lfkw05OqKV/lqFr
2HH1LQvfQZwzuWwUgoctPnWWMVBE/3+hnCIEpckH3IEDxvaBfGiGgzSI2guuu9rogQmmv4S3Pwpc
aD/vtlXrYCBx0VljAvo/2EPehAaFDbcie14kMDWPLCskfXpjuBGHSUsojeeJbTQ5kmVxliS6Bbvb
jlw2+HWZBlxJjmIP7iNnX/gSQp5fP3/sSFXtU0Zk1Hzc5JHnH6Qo/v32Vmar8jpmnDG8z4tpwizm
CQE4Gc8rZL0HtPrqmhxHp8HAzjPZHB4VCLq4mYHpf0DcEsjit5fV6viQ6tJmwLyteVMTQO3jMPuH
ufYeYK4pVe7llfe22oZi0whAnCWAakzcsS/gx4ZDdN4B3D5i1ThZamvuIHQ02CcXhz9qvlgTxudo
HosGpFLbpAVutAWCkjZcpYFXnhe9GdT65btgY4PwR58nzjKWgSHG1OPjQ5XaweZD4/3ZHXqwBh0X
6lq6/7Eo5l8rKhDhCJaISHIcwN3aIGm3vBUPa2+yn5eV4uYLu+j06FefoQ6wHoOefwFY9ZBxSK7f
NLfG+cvkcW8GJpiiZSKU0IRuwm6EvOxgtbxowONNy4+uudufgSZ7xZd3asOsvuuXZQgNosukfk0Q
o8QR5tycskmr0RmKOFVpD6K9LR+x1S1RzNkZdXfM+dVDot2m4aN76iRS8zAztssPGQCLvo5Af18K
F16wUevewpAQ1wOkH6zCLe0hcFlH5aYaS5ol8VhxULtH0aq2AxFheW+KXT4Voc+yRSE7F+O5RwpK
6LBe2qj7/ZJFOtZSFLGonzPYNiBQ1ZK6ougAdxjab32ClQXSIvO8Pa5zXG1t/9Nk6UMQm9ENYhEZ
X4C2UrXAKsvDKmlj8MjwLPO6ix+Yb7PRUHAVWfql9LWmjvLEywnsi1dqf7syn9DHiWwRKzcoN3+S
5MkuOUP345HhpVYiDykFXzKmLMhrxgYGoj/qldEAV+yubmIz5xpbwWJgE2xNNRNmP8C7/yvUsoCC
vGyHcbZaA/wOnpGoPQt0hFJi9u37F9uQhlq62a5zdnrBLgm7U5pmWZas8AOf/bZp1eZpAhFpRIvu
3vhE+LmJTCm7l917wza6RQgZFHMogcceJx99NKflPFqtYHXNutS/v/YmpkR7+V35QKxbEJCbgSBh
fRDFTexiGspa8kV4qZpC/XstTx1HnzBwsxadu2Jswi+8p5syjIshYaUGmq0AMBfJwvTAQdSEW+TF
VdObhAuJyuZBRoIs4PxnjZ+PU4X8KwrfQhQCZEu0hb2Mc1iz5dGXNTNkchaAeJkbe4yHo3p7ecyv
chyFj900lcDfNvW2tcXaOYqhkosrtZyv8Pro+JvkYm543Bc4eImOT/w7dj8vF8pyj/zl50qOk5Ib
eXwob2iTSEfXFDgHHjv8t2SdYXvGUaK1HyvXKO5SS5rCFUzGo5R2aAQM4aTeTQX/QAk0y3w9u1zd
nvJDuU8qd6Qk+HZTuwwes862/ZoIeX+Xug5GOzg26Y0cdZLhDEND0FjBjiRTC14kcGrtUN40uHnU
NPjtvjSbhavZV/wLJNv89aF2SoeSHb9KWnjNwddX6TW4jBPptM22rlpP5WWH2Sz3Idv5N7QqMfqk
R2wDZuhBNikSjAM+n1fueB5Od0U+ZgByHO0eggXUxHIgi8CUiEYb5TXhjwzzJFhEWaPUU2GoyX6d
6lluM6EjZ9GQRAm5vpfG6BrSWZkXpH27B6PSqlvE1G0u2svs+VBRqeoTZD+xT1cJEaeV6y9FLNPO
SowqQnYymJoLpcc0MSp5dqOKEA8fWynlJGItxZ9GcUKzIQTOmy8hQv4fA0v0sHqYs39JN+yEciA0
4xqnnLC5gh7mSieU20egmZUCy4G250OTd/X5VNZvOnsxs+3vEls+SV8sO1BMSG1JNjU/LySkF1zZ
Z54vfTExe4DhlslfHn2/nskJPlX4y3tIsvV9W3fqoVAAUMv5TApWq9stUspV8Wt1Tqy8Mt26euGd
8tfEzaHms9HgPZDGNfSeDoQB/P/tca+7XDF4A1abhwufeBpPooDCyBG8haAr9RuiGC/OI3M7Fo7U
IcHOBMqiw1EWsiNFhhsTYf0jnmwx77+btWPaoseNvE7I+4vEoyv/rw9OSviKmLWym1BbFCtDumU/
u1eybngctSKdLBKW7CsfZVALztbLIpm2drRI2jAB8kMKo4Aditx4/9sSXQQ1NYg4VSOFu3dAF/Mq
W02TBKPMHq0hAGXng9+YopfDMG25RNS/R+bAiOmNWRg1TWHH9fV/HSIXt0A5GcnMrG7NXcnCx52p
m+5rSTEDLg0pT+MygDZG30cAjOs01hPBsmCNPSEwrtHX7Rcn2RwF18x1Z8gHZWVnqdRO7dKGIoel
t3zKkM3zi49UBtyHxUVUqktSOUEJ/LULjIMyZ3QNa9VtYqhVPstAQrouwQQcUW/crX/JaLLQNLLz
3nO0zwhwWBoa04BBt/vkf4ldQq2sCVpyYuMFTQJWl779K8KR2FUeM6yl/QQRVGW8+VZ0w33kXJmm
EO8TQ97OO20LSwjdh4b9b3HIDBUpHD9dvqFf2ZUtnL6s4frlKG2bJQSzMdbzlWbyOfRJBPJmIh48
R1V4wCpAF3e3HutoADusiqBcJvyzZQks+3qpWp7U12bx98S6lXgG94QBU8/eoELfIrB2TGSrzViF
8vLBiD1jlbSh/+SKMl9CGiRgrOH0cz8TH7k0s5RSgTjzqaH3Oo5kpuW2NCCvYFphYbZmQvabb/Mz
F7Thb0IUF26DOSq/rkjkJJHaQjNX7mpvq0bImMgR9PMBAr2RJfIutujg9iVYeWTD5zhlPJZxD7qO
GJEiaX1Ra0NmtXI3IiZ2ygWkL81nmPblG3KCIWLXs+1eFXPY/0FtC+28Qw45eFuWCYnOSz9InX+e
ElLyvPj03OTD8E0QHPC5HeyITEPGZh4wMPVf2EtK2SX+cChA9HZTMfzwbUyEU7fqe3P4u+OTxC0v
+98v3oxbLXcsmJdhbS/C2Kvg0iBiQ7ilvQlUkzodSeGLmL5iAAuzm6j8VpUG9sEIbE194Cmq++km
5FFXS/uHikNEUffGCQH9041hFuqTqdaB3mnF67xqac1enUnZEgzc7d8ZUm5TcHtUKaNvVm8wFgjq
qI9fi1cM9NpirFcku/v8/f4NF6XiWxP5fyDIbXZ5a1hu11qaDaNjgw4dQpC1sFd+wHf6XTu9CcLf
P3ewvcz5+r+HIhxCkDtPiV8gAGkzfM1Jc9CIKkuGY9GoNlGHeqtVJWD/c/V01EWMiXMTMnwVAHKr
3XDtG0i6IeAPAFSRFIOoXpkWBs6B99zCsJAmqFnIAYswxZkMeVoXZ2CnPUhgUTFN3k/gJADsbrEX
iydDbhxPueBK4UqoIlX3AygxqDVAdA13l/SqQkmiSksIJyh9oleTcPHYj6AKaknUAwsHfU/p6J8M
SjQjnk6DECOXopCetBv0ogtf++70A2BtiVLYVXPHjS0NIXoZhZ9ark9JnaNp3Af/4/HNpC/NM9Og
k3vGZiAEV5QgbR7kMhpTP0W3YicoXtEDUFvAwHPOi0dLl3Ui/EYQiYuhFiICJB12aFx44L23wOC1
FKnm+o+l5ZnTgQYeovNzqlvb0Ut4V9cAs94+xOWwdBsk8XdsQd5SPglbtusWIgeYkMOhf3E5qevR
LCuYsgSQA3FD0rSJjMAPcASGY9l2x5jhYYQ/FS/QdPGBZKO1/B0nCdSQk66+3IQaGTag+3uyI9L3
qrC+A6hPaYfzJ/88AQ8qUKNZLzOFUIjLZjsL4YGXPuoZDBMAXLOBg5J+JT/i+eoIKzClRVGbFgt1
x6OynY8YdKtIgVWeP20g7tGZzEbF/sBy7QftbYtuwRirwfng6h43Xz7gbzeZR0Niq53atByoFhyr
7Nmg9gcAxaQz0ADvgg+PJBip/Ll2g3gydwRFL6unev3MfP6Gc5DbW/Ko/1jpcuWZdpqKuSFsTAio
ySqpo2gr3Iyuj0pGyydX6QrlmXqDijcv6HNQ/CruoTu+Xkh+aiesAQXrqHtz2awJdNt9maQ0J3fm
/K6ZrmT0j8gzbLgaR86kB6k4TNVWFSC/qv9lwGWqxAC7ul/0rOACEqGZGr57QSP4oohe0JH8zyqD
XfCiRSZMapIAH9l4Y/BlEtChGs3Gjhx33FF5OnaKWWQo5WMhLjKdAfL9qZtQ8muoc489CnwmjSG8
3wVw+ZQfa8bsETTx7P1YEdWEuSYAY7m+G1wOS0/ac3tA5dLmRCEkKkc3cW3mfXe27G4uj51Mn85T
vPblXAY1HCorynJAleevdIh7zkB6MbwHxB3gr3Re3WmKmOODDZC+qFcbsM5THE6QDyUe+XSr/h4O
3y+yJ+epYAMV8nMuHT5NoLQcaWHZ183pN1lWEGrkQZ4IOLSkE/WodapYexClKRiRGgEr1Kg+bM7p
DHf8M4VAgBjY23oUUP1fPyOOXeU4eHrRU/ju+VaPwtyTigYQFQ3hNm6hVSVBGRLxLS9ew9s6Fgs7
j4jxdapKM0Auex7QNttR9hbWlXxhtUic3tCgefgsfXZ2+Fdy+Ba2YuO3/3242zAzyiNfcVkc0rXb
e6DCjnsCK0RNkEFhf5E2Bv8mzYSX0ARIHDHMJy2WGCHdBDlt5+OSQc45EdJ1PeBmLuxHgAd/JPJ5
Ep4mYmeJPuiC0dhW9LR1+Rmwjb64uJxDgXYF6ZkSE7gPwgRi+NznM9NsXzDmgiRsWkSmuzxLCNlK
d8x243B4vnXdwZceNfDZ4E/LXljNXRQXfP/ykh66KKcaYop0cMN9uvbyZPjuBWsIpsaP5fzWXL6b
c1GDGRkeGIP0Cq/hwP4oXVfAAFHSdJ47AnoIt7tUlVe19gc5xDHdhbITCAmlD9fqR8pqdNkXxUpU
9xKUSV4L0UogP0/dEUw6VzgrIl5eBppt4A9EuyfS2vw30AxjD3VLfJ5mu5sIgM80Yq5j6ZakDKI3
/NczuTc6RFBg99Pe+Q8pNRwzHJ+E7tTywjx2W4D1liwGraA3NLI4Ec9b/z2udo0jsWvvTFbm5Wy6
GWZWRc1QPdtFwxtwQvxtFv1xmpfrnxuMgfQPfPd2ZnvIi3Y6EBmZ17HMyYXW9raYCZtLjq/wYEoG
lRuz4eHCIpqmprLUyDwJHy+XGUgTo8P6LRydHqXacH5enF0GWsyuIVd5BZ7bhkT8M770ljt9b1HR
KIJl/iMkivGZHUa/1PnHZFMGgpgu1BeHwdFeOg6hNQTwR+Mx2l80wNYtfC3azRYMExDR+aXJ41zn
cPT9h9XfQZyM96xImCeo6pcufHTuFTWa/yfpuEYRILmLZvdywSqbo5fuFbPAoVQhXjKT7wXsrfC2
3OFf/z2+aogpeLjkc8xRt3O1YL0OwI3ESVizxQwlESSgcvQo+mRNUhh6gKk/y1AHnSF0K5bNY6Kd
STMSJRTFgLxDxwLWFoCY2ra16DBKfjr2BR/7ALIe8wnVogClNV57h75y0gS2ZNMxWQrtbrw3++Mm
sskrpBWcAG1iOedKJAIrKZa+5LFt9VinWmVv/IwdfAwvvNZioRbgVYfV9xtQHYx8X2IpDqE7RObl
/KQR57+0Bt6nYF57LeWfMspyTQ+s4JaIVf+ZfNa6xsOervolBE7sv59C51dq6d5rBaccAZJwcNxl
WfgiD8jFSDlbRhdXds3k+d6tTISTZyoZ+cATjBxNlBA8jnR+spsYfvCt5uY1OtIwOrWPxS1YzPYL
rhvBBQb5CQADElX8yGLEUl9NO8DtdP3iIgT+e2xrvqGJoF24yC1W/Y2FnjyJaoLRNsVcG9CPKtEn
w5Mto3Jc92NecJVuADvh844ZzOUGzDVmtvGiNJknzEVE8TLY6YMr/iLO6FGtoOz4LtpPS4Ul54eX
yS6ZZDa4D5+T/M2zJI0Wq09YzXjQCF51lbbxAnoN9DC8oKrgm2zvMWDflkjavFlD6BKiw/f7xvUx
VPlIyFqIC1FtpjevTOm1g7Cz95en74G9XpVrRqbbBr4EiCqPcGF70uH44aXSo+/ZbThyK1JX6H5e
JLsP7BAR87gHEN7/R+ZqqQDEwK0mRl5cpKp4BVDDXkRhyqfHCBQqgiyzHYTd4qX8ifPZVECakRxD
AtcMFkh5fw1PNDqWO+3mm+PZCRT4ye3WhzOWG2Ilrb+bKeTlfhVtm0+1vxmQcfrFJSyhnwhxzeka
NVftAq2OoyyTfU3OYk9hKTqM2lIKyNtxvuWqQiAt9TwtfH3XSFRc25TXOvu8ljjy1RKnCXkRxysg
rE/QX3wpLTOMNoDJa3t7/rmiQfWOhdZfQCSfiJV+27NudVA5UtzkGkhZW36afxdlK24wHAJREIgU
mo7bMpDm03K+7yhzC/9s9U3q9pOZQMJxwn5F26i7YF/BRtltP91dsA/zzryu8no8IDQG1Qq2dVJE
WMsUtpP3Sr1zuGKB8fuEzK/rHGdQNG+g5SWOCd/o4ywTUEyaX+80ZbdShFPXlPqZBBgDA10zQ9/U
Mdi06iR1PmLd7l98RIMpTdjr+Tgk88OYhBAMTsDdyNvr2dw84YW2hDjuUXQisJk1Xf7et2Pab0ox
/ivKJdDb793sAWh9YJHEcFMbeMv2Fne99hN987UG69KbORGnrN2v24krXE0+XlbZ/eKm898tJS6z
4QrCSAojgdg+sTq6D6XC6q+BSBaZh1Bq0WyX4Q2iC7oFVfLDJu5LecmfWmwH2tWoMS+BC0wcLkPL
Lk3sVRplE4OyabbBPBGMusc5g+3uU5EAx7NOGgfw7UcJevgrr0MaEWkPwa/zPwhMzBQbyb38S0Qc
2IZ/dhYkOqEaqteHj+AJQ4ZXLAT/TYi+iV+wOIubaW/0w5Z7yLBxfdER+M5YKDnXxWdRvK2qcQny
XbwuJ0kMHhdmmKqKmi2/FOFuj1NursfzVU3BXIQN/GBy+AGqXItALG+7rLq3z7GxnWpUaXoscNv6
V8RqbO+cDazOhu4ZnQwtv6XjctZj+SF5aejJ7sDxfe6JR1apf5QBc2Io5iEoVrA1juGaeJsN6MNT
JGzYZpTC0UpbIuFIndOZd+69+3Oj6MEuw3w5Q5ZHk9btKuFYWxmg/MM92EG1mCcTann5gceZxgT0
FuZKO9vTGm6QIHZHuUdfGOYaDuJiAuoo+2m9PQRpCsG2k5+aNaKVRgPuM75O3QDY+Z3659e0vKst
EnhH4gAl3pmNbbjZZALBVlC30hQXc8IxIzu6YVi5zcN5JV/WU1Jh1zafVB4NEtb6EDjKsBPzQYV0
ebt084A3NmjuD33RZDbLa5g82sN5MtdPriXXWXpI3L4eeOsz0g+MQ0IyHHChSQRGZd/nO6PK+Hyd
bjLr4JJZkKcEttvcLNhmM4JyynNxwr2i0W4OAMFr5QMOsileHWQ3VQS7ARXiuO+eWHP34NAfJLDm
n/ETowwUYDxnCZTBQx6+cjtUF53478AcN7F7kvkqVBFKZo2KgtGF1YxWQoqIM0tebt4zOKbtOW/p
oG27QSXtBwuCdXk7DVTKu4sCNCarsXH1mWe0FZwr++k9X6Z4EXPhezms7Wsj7QtEmy74QgAvkYqL
OS6se3+UE0gKNfkyi1AHeVv6fqZlQ9uUyMdJp88zQ044SGcgNjBJtOlvV+YUwNrAvefdvnfuslkX
KX4MDplCYBnXUVv5Gt1n7x9LyCGDdulaTA3etzy1G7luM/WryvB8X9TqSs9yMdyGG1wGCtKxc5VK
NS2tKdJE5ANWAaaYphfe5yvH9O6VWlhajDR0k9gL39qDR4FQ29GWKRnhtnaAzpv1M2k1/FmssGjw
lQ1lhnoRMXstaKaqoEqL2AiABmxzpMy+RsfwUBMu1MuXC3xIE8w/KRjjJoC9euk7GOt36tk7CU4I
6Xom0cioCum47wI1WDDJ96dNkZ7otlVGyEoJpbkO5cKBx086Xp4qcmj9hJKnO1w68D096HalwofR
W/6+xrvFCCg8egetfBuLysLLkAaDkMuzjwZToYmArtZKGTWXI7RSOJpxPa0inkyksWSAGVj/m00Y
1d48Ku89tIht3RnJS3muaAu1YtUDSa0wBchbrWn9ZYPq4CezN7o2IzyVt94VmlGuNVwWe12WQ6BK
1kwg4HiCR5wcaw+feOxmxpFiGJReV1fFVutrvWVPgJjdwmelSsuf9IiUsIhXKKYsdldZ2QH84w5f
nfh3Hj+wKAZC6gwx17X7PjXAUVhAlgrpVTsR0nZrobwwJ8dVKp9tIntnq3EnG1HoXDpmqSMG4qJn
Pz+lhZR/MGT06UF6sWnVrwSOg4QsBg2b+TOHWZWgwD8mZiPnSd5sHGIw6+dZ1q1wr5XbFRM2ZRo2
w/Dwsh6Vl71cns+OSWt/5dMdnNzlCvHlzNnLyyoEt8N0t0/gkqdYiuKaJnQXmcGhMVCZG4h29h6W
umT1hp2LbLdOaUm9NqE1sqabFk0W36HB2eA4fZmk427GmXv0GY3XeYTrEgVsKL/K9/suMY9q5bL6
awA/eofB2Gn4KwAJzxx2JSZqobcfMAJyyoic1ZfGQ5VgeGQk3E3pryxQndVKIAhGMAggv1vztv6U
dHkcv/OwEdhlKBJpT/aLTGPZks80ie2w0OEYSKQA5w5pjdnyqmyD6H5I/9DvVkjLc21Krakhbp0O
GiRKKPdwFwajGP0bAl7agRAJ66SZxCNLFk58V1ztTtbo4CR5c8cYq4zFKcpKU4gADRxe/go3/txO
lrVxdvdky1zdtWM18K7VEgoWxpR1FzxRI3ruPBq4h4IFx8dPTJeRY9s5k8Xnoh74CHZB1aoynGSU
CXS/VEnEuZR8tNgmINSdO4QHEkJWx7pSQbFwKxzAYUspoced3YOdy2lqL6wuSD86BKVZNRZZuiOq
NLxSxae3mp4px7KcGFDUdQVJvYlKfMt2WNEpEhcO000blBMz/vPRlKPeM8mUwAMWSGdX3zvI59XU
QYWLHZ/mf/SN5mzVzLcHnwd73LG1DGG6i0DmpsSdjXb74AOvQIikWLO2BK2q8MLLEnR8guG51IT9
XCuP75psO4SwYxrJYIFGfOdmRlS4NsMod79aXLgYdK0qrhToeUs0pRAYc13iKmEtJPVDcywQKWde
VSoRZg8i/HDNXX89AO+vYb/P+FhCli1V9NGclsvL4oK/EJwuEOw9l2Sa0hDSw4ojjRCCZ1FZA5qu
Fw4NWucVdFfHc+zgvfn4m3ZO30wpjLTb7dd4pm8YcklePXor4GemMr1xs+eVr496/SSmMEBazBBa
jUtYo2AGV7r6oEdXnUeWSEzCAxwfLuAEVk437AJzP4yj9ui40/698tn4XZDonSVj+GyLiWSirlBr
+dI0KeUoBTEN4yguskq9uom2b5scs6+nJMIj8ACCv+8kOyKlFqeXo3I+aRIwKItwA2Cb1IvYvEeK
5qggKJjB31s2PAjIXGfCaRu1drytaMNlH6J1exgs7bE6PjW/R/HN5ljwg6nc3KHncQ35v04pcIgB
KZC3qdzxTNguM/6TfY7iIo3zZzeAC061jKZFmX84V3sIuKJJ2q9vhtotjtQPc7GN3xRK35bqyXdq
XBcK4xgiGRcC9oqxjRJwGsznLqxEaM7xMibLiDm7z6A7M5mFM3+HOa5H8/F7giD//WxLEec/93TR
pSZyg2VHcj1vQL6lEcdxMtgAwKYLIwHjxuTkTyXEcKNXjmjay+U/fh9vxbXCiHcCH0KEp+iB6T0i
0mn6cAeCV7dbyb3PvgqaZERkazq9wQ4BFNtwS7/4t5WN9ZxXdzOkqvuIyXuOW2hKn+4nDtk1plkT
7Fu6E+VGYhjX1DufkawRArlPPXg60W8xwNjqg1cuU16WrSi4YMl2xrHxnD/Y7z0gNkt7UvDnctWY
cpkoJdwfe5uPGDdHSb/LnsuF/hSPFkcWLAA4qRSf3dIfCLYWT12LE9ZhkcxY19fC09nBfIksPER+
77q1VpNMdMJsf4AfV32zKjtlif2VSVKHgAD38neCWMlCJtU526sah5DuHgW1gKEyxtwSDkmUzctt
RBAOTU18gc4JN0T2Rpiljy7mnQ3p09D0jOvIdumFUNcO9SIEHh9cTC/D+iJaS5dKtHMygxaiGm1M
7358AgBiXKBCF2rmyUcIVkvkD7fgb26onk+QGheDKIH8hulsBq55XrRj1hTX12LasY9/KkpuRbdg
UqkB5Ds4H9bLSMM5ygfsKVaWz3X/yBiRn/03V57Lw/GWPKiX+0N4ciNremQVVcgy5L8bnbESyFNf
cfzGk9LOo98U8B03WVzY4+TNM8208ZjeG/RiE12WykLnVjzM9R0XB4WuxBJZ6+Qc8+HAxK/2O946
Ba/6kCPCaGM50H0wTOEsrItZh7mYAteqNE8WEJ9AFPWwfCA9T3LEeTN5Qg57oVCrbQzyMpJ0B616
m1dsTMQcpbVhinyezDilS3dGHBObHnFQkrHlyKlsmpB+tRa68iEQkl233Nx5IO/vyO7SOJCHD+Fi
wjQhPATzJ0AsEk2972RTDKy6MbWVq/8qot0pfihDFNcA8cHfN87uJxyj7SEjhqZ0VGLc42Me4ht5
3by152sqyqL+/s5XIx+9dj54GJ/TmrxzAbrhkLKjgetl5BKA04omy+K3yuc9wuZpP3bWyxAqgVo/
6gnizOCUa5/IhfSL0DJRBuIFWtk9tGYn3aXlhkU0n1pa1T/JuIeOPS/AJ43mWJnGqK8SwPiWZXJo
ybAnU8bh9ygbLQpeKYYE0fCN5sKPKQVxl2ZDXSmrty64jr6/3sPMrc4SP0tzkTgd+OoMRfY1dJtV
3d/E3ehBC9PYadK4sOJGD+7Z7sj/xKGA6+eRkO+Nl/HZY4UangKIZgZUxW/+iNukMmOTSc38lqcq
KM0oVwIAa6sMJV8bqmehUAPtV7vMhizE6tqG6d2aEvTtrzsGSzSdeZ9q6jTBraJpr4bK03N7t8Eu
f1ltvvM4UjMG+jcy+0a36A22VEtQoHzBfX0rNaIGX4hyhFmXnTFT4EvDVX7/EnuBZ6ucl4EOMTzZ
ArcuqC/0c41fxjTiNXMH+WltBNrtmCCilhEbVzXjJWCCcRO9LZBqZYMMCbn2YhUbrluNE40TNmIQ
tyMoY/Fw5Uim6Zkdh8lkdbA2dRRzpsn4KH55XsIuH/06+eI0QWK80ytKkqlEScdeEBi4Fe5Vgq1c
03uiQcvgaDygeuMA4qDq5qEs7sJTxZEJvJselSSEgue1QOsQI+ou8HMrq0c3PKYCgv047fpLcv5E
k9GqUaFBXfLiNDdgI9raeVhfEva7aRVY1ks02BkdxPDDGWQQj3VqDdbDEdkAgBmfNSIf6lMtZvHf
Nzr18t43bnzZV86IAz20CUE+kXicP2+pXWtVn5cHhp4jNic8xSk988h4shuhUiuexqys992CnEpC
F3rEZClnP8j5RmafNRcAHOUDKvlCurq4EbYy2st7DkwynT+XPP1iRakvQp+Uw/TqW4uBjRNQBAKs
yf3P1fdU2YTjt1gPGMH3Y4+ieqUP2gOQ5Aa8ZkmdQVd/2SY2Bq10JGJTl4jbvBuAqOkftxIiXlqV
Gq+aHSNjoWhTuUkRxuq3axIX7EghYP2T1LzLmnIzdRDt+nmRxEoUxUgOg4XVEbbGWcePsOMk6acj
XrHYJq6sGGhVYImywen+lGVA0zvRL3kfAgbGTkDEOLs5OTpUDhf8YaiZC950jwl7ihPr66lOcUbm
UI5FCGNSASCoUC9F/g+9XhiZMby3IE2aqbOK56SQh/ioOpGNBcouttMnkrIEx0S06j4abxlsKb8f
POWAbFY4swu1qcdUod6gLeBl4pTKsCCGqVoaT6J2RS3T9MdTJRRUJyJ7kFQZGM5gbPNhaUxtUlkx
AEKBJwOEgsiWrUITytJ1rGI9je11BBMbmv073VKR7DJQcuoMolNvc4Swq0ecfSiYrPJgKMb9jTMc
AR9HjwS2VuOuNlkflU3JLL9zG+TuSQsdQwhtOHcCExJbN57k6ad2mHVAmwTcOKLQwotwBd1TccxF
tios1Z1Itp4XdUyQiqMsE0p3fcG6zESTRwjhrGJrdoWBhFcoGIvg3jP6wwzo3WE/UV4szqBG261I
ZABaAsS9PEpfzpI8+JFxwR5jna4M+5OTI2a7+Ke8sRdHxsSFKk56WUErhRh72y9F17WJ89PC55ho
wRsdk7ljJkyTJSlRTtlOAkuRKLn4pcRKxbEcYUUQy2Xueie7YrF6sxDznhOKIcpLpLK23GhikOHD
y+cOC1Tsa5hmNrK1Vg1xvsas+eQRdRVSGaM5bSpSBwek3q1cXeR0unK+M/CiukwmBCmx3zSR1c2V
QFZgr25cVHTD6+X/XMzGTgSxt25RQBylwRSyHPbP+kIv5Y6nw34SsDTTpeY56Sdx5TggIYr0ucMZ
NPVNcO9sbzGwKVWm8hO9zZvW/zaegavbUeSEkVpqzwiZ1dxRU0wJqPj6yV7okikxSJrSN10xpnQi
SE9MmZzMCdbvm7i4ngmppwxpE54iczBXk6z9xQRXmt3i3EcEAGo9hbSOmEsTIb3VCLd9+dGi+UqP
ircKCFKEB7bC9ECh6Z6UBty2twK/JnIC3QUTRc+UxMf+50bkEOb8utEx++aNmicJsEZST/SR+JBU
Tw3V8g2YpsO4rrY8FjaEJ0uqOzwqBt6D3WoyR4BMcQ6kGrw7Oggn2KrBQ038msGgu5GkWyys2aNp
p99o1GavlLoUz7I2q+N4y9o3HrChQvV9nYo8aBH+6Hwrnh1FtZ1SKGMAqQMGHrj86lDnxI5wbOES
CAkMPdz9jf0YAAQM6jXQjeu3OXhI67N/iCIjcvyL3rEiJtiVWARNQ+lYgB14wUSaWKyBCfx+CMI8
fL9D6Xrug/9nWtyuBzLi1i7yYAW0FXcSLxmQ5FUwC+SdubQ9KvEhxwO5NrFWunCInM6df51nW7wR
Fw9ZezRvbTISOwZp0RoGPd0JcgPTf44VSBJ0A4t3+bfdepM1vH4WJcIKJYXo93AZ65eEZSJuofsG
sg5XqLkywEHqYRac/hkFUKxDSTnlxzG5ekoZw2nuAOofhV3bU4oGcA0fFwsaZzhSn6iLCrKf1zkY
gyfbgSQiYYkk+t4bs0Yr6opz1FYTbkNtInVJ0gWoHtIZCyb0HikZ3nfJm1DFS0QUBl27IgeHhAsr
mnL4h3vALFF2zcT2d3H+PxFyiiUzEs5D6eo37OiKg55EQKD5Q9/FblWrnO0PbIrdFnfX35kpQgf6
bC4xyOUHSgR+VWCjo5h9r7eKtOmkCGyTkbSfYfdofCXV7L5WZT+cMZ1oXcHP6WFUysLsTpgpVh8b
AgJgHI8FnLg9A6GYY/FljMmxbCqU2hJGPJ29fKaV2lBNsvWF2qTRUwLXrjiegNG4zhEjkYgCPAfI
zi740h77/liZeJnZM2C3Jj6rjecZ+GyHL32rCqnW7HpXZaZirS80V+/WrA/UVRMx1VPeu7gq1Dev
odHgGZFP0TyrCW+J9O2g2+WSle2V0v+g+9MxMPRvvy2DzJ59k81JAjLzp4tntSULN7/vuU8RHqBb
BA8MH/Yftdn5YKE/D6NVjGh+7PgbJhtZmVNyr4tvCTNBRvGe3R0EvG7iBpTIeYAKHm/84ORiLYh8
QP7lMD+H4zWOdzB6MUQiZEgZuWoC5XNXF7r9phj0+v5oBcc/Xe7mDYxqeERpMD2e8s0Bpc1I5QAL
BighLJpm6GgonOjq4Xb+hQyvvH580Yzo+avtijfzU0SRCXtzDn4LrBhULsospODE3iR+pavFcQCz
00cHtsyz/NoZ6+PrLXw3Mi7vmT11TDDDXP5RJuzYbJXpxoRE5e5CjB2MIxLFypcUExpdl71s25ry
jGGW1ZlFBZ5PDj6VVId1S6Oz7TKsxXUBxdjTEsQkYo1KyILfiXNYkXQSwZeR+InktQS8ROhsjLHJ
KvY/ni+6OYtY/+nii8bquf6DBLqNKj63U5LAcf2qKqBYLAUvhfmviXfxmCclhmqZ+ZNnUC//JTwC
ji7LnLQj1/Qrq27iYMzRSt8ZR9OCYKbh2/zJl/8ASbo1gpVRQ5Q9/PE2o9HtWeOWf497daxb6nyN
T8qLuBnPyIEckp7fXLwHpu2j11lhwD5MIj5ytll59Qt41JKMrwrT4Z7QKnfDURi65dhYIX8tzEiX
yO2aT4zxoXat+V+lM1IjWUU+NQ/CdohZUMmeS7zqnoEvKZHkdPXhlxGlDOUj+E+uZAT/BDoHlpAr
x7Va5FLaL7o+0kJLaHkfVQy0t8iTA5kOS5f9RLZoZKtIVEpttaYIJmcLUJRXVSTASCkIIrmMuXle
MV1oELWLT3OvRw86D8UJ1GDoH0CEuRpv5OqVSCN6cPDwuK/yK6hkYRIqoFYSrSIVn3hbE1df3nru
JP1CouJOMiLSV9z6Eq5tQ8o34GxWEYUM+M+HYkOPYJI6cQ70YyAONmSDy5nrQRpXkdtmqbOH6pVr
R8AHaFsEK3JAfUThHJ/h1PrNd5br0r7cc2hdIaknH0STFlylDT3yXi5d+CLum5n1ME6RtJiSGW4D
1vT7w4fOoteUvmKTP9PIUNrw8Q4bpu5nPgd7s6NDMA2bfBdqbb0biNwqplbtxEtnvsYvK3B0vd5G
CZG4A2X56ijC1eYrbdzfr/pIfQVELBDYV30yGnvPP4UUpinpXlzDQkoSkTzJItQNOpvGtS3Pjyap
Nozy90YRLzQjCmxi1gxDkwp9gMba4Qj5EhwpMuQ+z/d9MYAhAkCo3Ocl8SwsdTNwIIVw+Z50I2Dl
FEa7FvuBAlX8dWeuL+6H1cC66+FBmu1+DHan34WDv01ryuVJ89JPf/A1Jw8HA3BpWjA2IH/VN6XC
2rc1scsas4jhsjfOjCV6s/dtPzNaC+RYRWVK9msr10NPQ1usKxvvYA58FLTmDUs+WHb2tLy85G8j
euZv6kTXJH79wLVOKLvpckeEh6qZ+SzVvdIPtTHlQO/iOAHQNTQ8VJk0Ouudr0+LGGZM93Qndjzc
q7jEC2l6ZWf/pST5hWs4CQsQ8a9KbOVZYvf60r2jAjIWTfn6o+Oj8OvKeQFZ9pzUYxs7f3djcHbt
cY8KReaL9IG9hEOW8QS6MkR7olCD1I7R92eNUZoWrIu8TPMMPGkXX0QvXo/v4xPXd096f9O1whVW
E6GDRlOGXodDhvJEhwLFmsOWKYyy9tP3ZseQCqoEsgdkGYZX22pFhYfUVpnNt+rMi5NL/NR2kZVO
C78mZekt0SIe0xpPe64Dk+Ivfusoq6LHA3eG4ACqdi+awLMh1FSxYIxH9LoKzGNGiII6mIOZrV/A
Fc6Rkm7slsG1x4dtqusovtCsg75lZzhU3gZ6YBjVHdSWUQ/qzSacAPLfo0lajDf6ohnNvSZV5yFy
j7PHSFl7fg1St5sJAZK3iS4HDVhAiJ275448+6HpayGwcI96fqhvSMzIvj1vO5yYkJAkMeythIjq
V3kNd8GBO/9/9XWwfQGA
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
LOrXUPjF5IFoLR0AYJN+dt4yr/8PqcmGKyTL4CgFcGvIQ/aJ3vGk36Cz00TRq+Nqo45GnHt/1m6E
UtRjBvwscw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WJKji58llb2KFFsN3Cd7W+Zzki2XT+kR6uYjuhoIbWbNBY6QIL2EpnimDuG57wFXeXyygvWr7yZK
VfWkOmEzAoMkw8hRi8Go7bMDERt9P5yhKxDIWNswSFLZMI88xgrYUluTl7zN1MvivA6Gt/XVbvPv
3GGjWUoqFlxi7f+DFPI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Jcs3+SQtGSLXFw6cEFOru8HjLAfKHwfQq8uBjCuKKtwRK/yAJwHRNjL9vc812moIiB8SgQ6pgBcS
Krk8XWqTViUhh08+bhuqDoOZqOhRUnVe2KU5bPOaP2D9D28MoI3jEqKcN09ui/jOIGo4bQMOEbtB
wlRhrV0ZlM8hz+dOMrE9TqEKY7v79uyDjoJxh4nhEugl6X+2H2jvq2cqqzDTFfzkrid/WPga5bbx
KkG4eEks3DZVdZv7b+yNIRKNuVxxfwkCok9M3MxHhufe74MBfVoppTGm+9M1T3tJNnRZ2GXItBK0
1RYRkOuPxTXDLegfYLeDZsAuhH9IEIshQelv1w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
yofNydq+Hv2ft429NgFsYlO9b8jA1NAsY+uUYJMnIovXFAwZsz1Ox60jgGkg5M7evNESBTbZBPcI
PTWxb5rdOnK4575N4uhSw3MITRy7m1hlZM7NFQn2iS9e+tLlKFKKUrsejS1G3PgGgo8fR5P/7VYQ
oqNlDT9rFqWM2kjqfZw=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
MNqDEnqKF5nNQQLZKl12k5g6EvteYCdq0RTqoAuouDXi4v48X86esK/4i/V+9HB3NeqF6RV2fE85
W5pzBBXr37jp0pzu3JoqwausCaAEJZMx641TszLj7JMKRrTVGZcgpWD+M2cay4Spk0Q93SkdU9zg
z2jTkDt1oYIAU0Lj8C3F4lDHk3itQkKVEDkczOPNS2iw+YeASIrN/QVRJynOQKfHbfIa4TsYzxAh
mI0k6aWPaN6Ed4QbFNsEMPvtduaur4tT93LN/4AigwrZKqQUkO4JP12H1+L2+eLhx5WQl/MF21Zy
ykaSn6yKqF6ZSA5d08POimRDuEDdjAIUFc6TZA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 36096)
`protect data_block
Jay0qZlyG04qyslfbjmu1/PefK58a1bAtzIU4O3B621tSZs6uZb560Gj40HzQmBC5guZu/HZNXpk
vxqrOoIdiV19ysXXCQgvDav2CLc1JQfaD7MO8lM+3RzVgA5/4XBaB1Mxjb3LoG2ypsLw2paMea4I
CKH0J5e5259Hk6gWXGBHwMe4C+DuVqJv55l4WjiIgqbbnzzosYTVcsZFHp2iZLjYZmiFcvLK+C+s
YM8KrlQmNuqLBtlMva2lzejLuYpxhT1OBdR577Y6iBRZqR3PjyEYRf/9CdEB0Ozv2PZyhO5wqYvi
CYKVcXLCmAYMTErMD4iOoKiDTCF7BkO3thY5m7jq0IpYnxVKNFvcnRd8LsSpzuTAUHZTtlQBYhmR
UrGLqAaXqUqFEGUw9mt5DiflA9JReczFr6QfMqVRDEJ5+mdLlajI38MaiIFztLwdb3LvWyKGUF2h
fRBFgH5vJRx8mfWr25Mp2w3A45NudrqUgoToO3YgPGfL+n9lqx8iItP6DTaZUu45aRKeNO5W540M
VqWQEJIZOPsP8WXJ8clvUAVecQZoudMVwImD2IpfE+XBtwOO2pWJ8bgo1Hl7v6kAWLffu3D9TfOX
OQapmXk85Jxt+1vavpMpExqdzBLfJEuSBGjKCucJfiDZbmoBnN/cksXN5vTUsdn7OY7MQtNXqKBd
YWfu/jl4DNhMxVRncGcJXb1PElxl97/RavPWTnQsdzfdBNXhpXi280qwlOK3xiLoAEBfYaz1uis3
uOFeHp75JwW6oji9AqW4YOIzKxzNdtwUV50+gEd/qt0/Zx4oCDPV/78Bkft7QUkpNY6b7qjwppfj
i5yG3i4BWL7vfLb+rLtKgqKXSL+GYshHHvk6nZQqmfADndqdPlncIYyk92muGbPsWY4iSjy4C+l0
39fXs4sJ3rfAs1S7P0FJXf/YlpITtl+9gSM1HqBd+z46+OjDX8UaQ3le6QJBwGPy4xQqclpTnpxp
zqe0Ke1vD0MChhmXJa+SyBbTWtNTH5n2u+pKy2R8esIjPTgciOpbpX/KxzdzEx1+dSruXVW54xe7
JUpcVe0/aBKu2k+QOv7JRA/A3ypHZofMwrQGnyMtFv1Ui8KcELhRc5UzpsM+emYQH4XekOXYrUfG
5jAD35RCHFTZKKig42l23fJ18Wi+0z4+2gxGX9WP0F5+xL2IC6gmqNIFb+ClWILZnqHRdXvXmfhH
//c+s8KVsKOkPPzplo08wKOtdQwtTzbm8IACRfCkqLAyQM3WWnnl6sDUQAp63rOU/4bFDHpIZgn9
6v1t7jJpMk9W40O7X14+N+33QyTkRHTO+6AwUU+voW+NdFKfzUBqC5ipKansg+TQA1ySjMMk1dHf
77OgL0D4KtGQj9dEHk1q6MyLY1kVhqkWVgKajkz6/YZ9ewJV7JzyFDkqL/RywkOEc/KjvBC9g6WH
YbomdvIAWKYwfrkfXqRYT4nLBIoYwsBgcUISM12USI+al4qnaGbaKYQxrnHvfZS7vmD+dPdhnpw+
Knbsr6C5fBh7e33AJsxMjXB4y3xMb080um1MB5QeMVJJJmrfp5AeaVri7GzVTaT+b7QLKAvFREEt
p0VoudklRvCkicArcLkFN4xuPs/LuJZFQhX2PjXQXhSWjCjTmijc+20PDxu0vSV6UQTG/OvWIeCJ
D+0idv3ZrDWpz5ikktANTclHyzNwiFVArf95ES4nWx0LN+ODiUgaQ3NWKKKnP6cNmeQM0oAjBB+V
l0Ept/17YpONRc3ZMkMwm5TjyrAwxje0ms252wKTNRXX/AIr6vyRjXuNpzf3xh4brfpGqkK2dXtU
XD7oifKQCMUKkDV9qU0iT++9hn3f6oow9ksk2wR4LxgIsv6VC/zMSl1oK0jmBgpVj4wq8SDN2u2D
vhB1UVskGEvKqZdn/qXCHN/II0cVeirCjNxB6/DuNoj9AJ84R3tWnqSH7BelhFgJ5s3umiqHBeHq
IDQDfbz37SLrqWOnp5GBUb9Rh8tFbjOI+TTXWOpdkHxRcllpWPRwXdAOX3aKGKTjP9V5ZW6v9HBM
PFxp/w1LUo8HtIVnwbRycbJjh8IqVytqJbDnePMnBPZTk3hO+0PLe62dx5OIQ10Yhyc2LjViSoNP
KRSk2ExSdUTDZk4N1+O+35MFwzklX5R5e5w3dSzFbf5N8X9Y89UlXlTNrPq/YK7yz+QSNbS15Hd9
XFaM1RFnZh+IIE7zjKFQY1y7tET1Fuf+rh9630HxFah6HXmzAHkyv2PpdbvO+eMxg5h0/3uAJ9jl
v3W979F33x8l1URufVk+Qf/b/WzR4i6ou4P4vMreIcdzfohz+I1UdcmTxCI3k0xvwcxmiLuX5Gyv
PNLBZ6G5ab9Tx683rhkr1JrNhFyaya+YtyTfs9oQSdQSjX4jVn+OgUrfsP2pwSrarxEr08nJVtj/
LTREd3qcPuicM2SPHP6LN4KXtgsk0I0USWpIRJysSuGmlTujxw1XR9fKEOMzNlFTXvm9jNMJ0z/S
F9J4/XS8rOJM4tbogxuGZsmKC4oZfdBdeXsIMVm3X96x9g2VxTlLVz1etfL7+Y2P6DSg6VnpdCC+
LVW3gyCmvzbOfKvBVuE+yCWIrHPDxnktznhF6u3F4TDYl1wcMvjV9+FdgFwtr8+vWo3nzrfqg3ph
WU+AhJJV+Uk+moIJC4X9exypHIeUcEmu8qlWYpOyRit56Oc3RpxvdiaWqAwBM7LCR/9yIyZKcmjF
JyRqo9H7Zdsfk7EDd6En8KR68Qi57ylNohJr2Fo05T8AgCWpBgjKSTpV/1aKefdv0SlRK9gO36Mp
9m0Maw4dX3xm/9t16ABGBPE/+heQEu7bceeen60i7JXnhZmPUAiNKlf4vyK7jjx/S82PUfmpzWNt
uBl5ppoG1o7QUcpm66AgvoBi9X5/s92o8OvLQ3NCjsPRqYpXjTfaCIYKh5+Rx+D22XKbij+ju6rb
YeFnGZ4y5UPa9kZ9mDnB95AKcypxQCrWO3RQH2zRfV2PMKfQ2iFqj5v8cwGO9dn6fZq3t5B5H8UK
o4YLJB/5XLgk5hkIuD9GubYfnGxijOC97LHhdTq63l+mXQYXHwZjCC+86H/uLvrZ9KvXAQQAJAbh
q/QaI56gXD3e6MvmV6a/ZILgBRdNN602rw50wX9v60kWZa7jCMFPOJToISdTwGReYZnr8SOZQZFL
eyH+hEVdRSK0FNBiEwP0nOF1eedKjYwGncRAYbc3n8hWV141D43c2EmeS6vWHhr7ezruABdtMj2y
XbFcjCfO0nTJgthubHIIDItv6DuSlO4t8fkzMl0loVvdaPSsSjcOVSBVDJiacW43GmL6sCTcQune
tIIj/0tq9T1kJB4SKA5oa1rS7+emZAtXToMX0vh4al4O/9lRmElrDQULT38pHxJ5517BxMLBh2QE
O4hAC9f3+dWKqjnBMiDQAfOFGcqdc58XC9VkKxES0LyabQnnWnzokuHKMMCN6f9r5ago+pLEM3Fv
R4dSN10EPOkhrXOxodFV6t9ksV5kx3Th6v4zqf8kclnCccAkI7fYwb4JX1SsymqWE12t0vsKLrw4
lUqN6hkbIUs3Sas9HiZrXsV22nl2CXV3hV2UUfE60tMhm8vbXUzt5ghLq41PrZtIn4DiIRA5okIq
9TkghcZoOqqqae8Vw8ttYBA1Ja+LIBUydVn4t24N/rcwvfE9ASmFWKwmw+bZGVMlwVag790JAgQq
hlgalgWOr3C+rlV+PE2vkUkKiY4jUFRfjpHXCw8lwZnr9iOo2Yo0DHxAvho4+j6el7lCSdod67RK
vVUIIlor3/31Jl2WXnFNcwyai3rnasUOEv+lsbaiFuv+GwBbuBZk5qZYEVQJWk9ZoDMy9+kihYG4
M4/qBb6bV6IX+p2YCP9Sm4g35uOZ62351n3vjxS7NA3UJE0Ejs90uCZwQ/qEjXqnJSEC2VVeNmUq
8UmSO7Y4gsAobe6XTty9XPLVs6141Y0DTYmwp0InG51XsEqaLESIstJL8E+49kdj6+fpGM7T57nt
16p9Ts/yX1ZHx1D7ORH6UN56doV6wvh+c5iEh1DjT2V9diHndDECSi3E+zQAn1MDQicMYUz9FCHZ
QmjVy+rxXYH0nuygHEH5jT8XhG5cExILO+insYZw+KeUDcSpvNcSVc3nyaYu4ct8OyPB7x18kubx
uLENYer+5oJ4rCydPAU995+CdTpljyxjHzLuf0nMs5pOtJVxmiTndUmNWMGEJUF2rQ/cHGYh7/4c
CFTyfv7PfG/JjOfgcjrYgHn3Tbh8sC1Rt/aWTYbxhFMeBMLAKR2mhXL2yZF7wbps6K/kuQrjYuov
YevrgkXKhH2JycYmznTG1qjLOiRo0lRlg0+T3dJv46u5oe0yY6cjuQEMzCaQbP+i6nflgsLTrtSM
6rRVJCE6olyFuLxRNaDGhM17y+J76H7uBcdmQgWgEIqUHEM4JZARRi33jYvcUb/hKQFzXVVaGHfy
o7szEqynSR+ArXYxTsNFGAxIoAc1UicRkoxNwEXnsGD1ISxyEsayBcd76agIZpe8fPPrYgX0pDAw
27xRGz6BfHTMTbIH7iBT4Oqa1BwuyYgVrJ82ocYBjv6Ipfgq6cplYwCE2eQEpETDkdol1JEILkAE
0F7qvdzCNnQXWgPeI4/WkdnE+YTxqz8dBbUD3sUKr+jJjfnNv6kFwvojq5gsBEL9ddTh8LM8QFjH
OtAP09F8Gu2yDzKodOqCvAPJZbTbxN75y7Sdmc+Be6EVu7KskbRmnuetLtk6ME4HNu1FkiuW+HDt
L/DBocQRMmXn9yuAxBIFeNtuA9a7p1yZrV6DCs+VQcBNNCx9kt+JZ+zWqB/dEuZ4ibJkVPQgw8XR
AChPDtIUx/BcOKVK9ZbTRKPe0ZOZc/fesjSG4jIt0TfAT+ykUinvMFMOfSWI8niujDOrkXRwrsod
zt4+uTCV5+HYWbY+DxVpj0kRbkCuHyVk+HtuhGrgq/nfBzJafwa6rk9zMvjbM2Rb+wHgEbgmyQ58
UkamR7KpCpn9tnC0+UmQhOQ9XMkx/+V6fsoD26dAD4VrizmtCTEHudfC0crbikRweptalzpO9w8j
9MA1pU7cT0VBVqPAFnc/bM/ezES/+p7FYscqpqxJ4TRXPxfItWpD8lVUnASOvmx2efkLEdXF5Hk6
z+Bwljkns8w/LXq3BgCP1DaLZqyqdqdVC9yiMoknRKEXagDTOCqsoNQfocLJCQoPmHxRh2GeSYyi
GB8sJkVgCUpL2zH7rdnbtS1zzNAoynHmPNSEHTNJE5eFuRvRcY2e7sLOuqvYMyHB0d3mkMDFUFre
FIGL0I5eeDSPBQZD2bg/cFIi4xZsBPx+e6ftNpTIfHfgKUf+tDPOMSu6chUVlM9Ppl8yJs+/HcjC
jIP6eqg1Ev+EisS+4CoTgZLsrdIaf2IXzmBNwsklFNBdVLpx9Ghz/gzthgCSCRmHvq9wig5v71Ff
tlrNvsswI/wc2/riCPg1FB3jZjqoNbit2ka9Dwt73QLHgHXdalcmxwELKWSCio4Q4KtL2oImamWH
YU7i/T/APyjw3cIz7IiwMSHOK6zKdUe5gfKmFzUbAb8V8k5Frf70554LjFE7KprNd87tsiwB2RDL
E2oaNIeizDNo1Pm5eMB772tlk6Up/vs1k0va5pGOn46GSpLZL2bJflnPdV0U7OJPLC1jbRcvBV/d
9C6UftvaeC2dviYAm9qB3ygbauyA0+VfY6JKR5hm4pGGHnAqfo6yzHQ+tsQArPik0kPdqQq8Ghtp
xzU5Utx05sTOLu4CK/d3hPq5WA5RW/wrhLcMdIKDOrn1YCWG+UXhiisfg2+PkGkAy+udAKQS/Gmg
AOsrPvBLU+LH2NGl5Wpkrwa49fWy/CnmR0HHya2uTdJCfSqR+x8u2YrQ9Tv86upCEAlapiYBZrRa
klZeGGwjMp6NBBju72sMyDI//lr4pG9wTrt1fifV9l4BGPFgxj43SJ6c1e2PIsFKikvt0SPoUxtG
lQlYxfeuxD9viRI6cGsKyOy5Ij2G2kcuSyPKJ6foCw4oXGQ6w1t4pR/iX524xca7fAadtqBa1MTB
G0qjj1x5l8rkG3sKApz82mpanf/YzzmxrsSiFHImCfMEg1XZ/cIP3ARPrzw/zLz5Dyw/YWysHXBi
ZULXkwt76E5DZVxoPBZbUcIkVAievub527ftAlGTvHCRorAaccSyi+0SYrlY24pihoL44xFy9AOb
4B7u2qGxUgzcRhSywNoZB7spoWYVEgc/2ozOWaa/jhhiIpXk45wTAFer1Xepx4dCgZknLfNXHElg
08aIZnmXB5o4ttTwEXnTxOTeTlf0svkmDswdP1RguN0FDs+Chp4zzKrZBfIpY1IridckP1aTvLbI
4zwcZ6uS18tl18sEhlnl1aJ9xVd+k2zyn9ClENl8THp8K5Qx5AedZVGwzgCHZab4+ZVdVXAborKg
p7Yk7/CuPeG/VETD7ey+01IxmMDXgU+Ds3IIoHnjNZGcvpf7FbVhMaDGCuU0kJPouW9hS06/0ZdI
aYDkXF9C95m4tdUQqpVYWv7kCtM237pj0CRnY1Z7zA+tCmmjq30Fk5vhlxYcENQDYphxDHCeg+nX
ez86848fS0zajqs0SneVwZw07/jeaJEAMIXuo7oMrD5g96OaOCZ3VvHQ0SY0dx5hGjT+BGCWtXq5
R/kpaCzy/SMNFQKLgRPEhX0zL4QWfIfDS+asBLYXtDN8tGiQ8bCMiA8PwbGyF9E+GZK3oyh5SL2h
eFs9TnubgKZTF/X/L1FZ5YduuCZlu/ePmnIwloEg6mRtetRxFE4h6BY3qfDGV9KbHZG9VuCmR/MQ
CxdYLbVGcNX7se6ZsGfatS4UvyIQAwXoqdbgqeOjUTg2wnQAvbgWcehN5nO0kyuPnf+xkNlz9lCk
P3JAhwxeVVfXouzPi8OMDKp4d3RJUiJlioOM2hr07jB2936k1JUNGm1rS7WAcu/2Nbf7Cs4VUASG
L1uOdzWfIeruaHrsgQy0GF99XVQqMfsQ0Z+p6L5dzNrfcN3wSncnMTBHzPJkcOPM+/PIP8PJfaEW
43bm0nRrdZLqMlfoNUMuxUTBz62BAzAZOFUJFo8vh2l13xcncLw8iutvesaaQEv7VC9XAWNFLaeS
70L4av4vLRmDxy7Kb7o1PdmFbbvxXplt6wSFRJM0oL3vjZ/cxnut9aMfU/dNaAscEHnPasDs2tcl
tm3hQdUii8Uv8S2G12cQkYTG99Sr8HIwp2NwlahxCXE70mEh9tpRgyzmSglQ6afoMF3WtuC1baV6
uvr7mnzmNJJkPffFRvrQ7PmhYS7Epjhe06Nwx7G3oTNNJm8/oiIMSZRVPGjmXuLpXTYta0O/dac2
+x+iwxTweVqiSiC5++IK5FWIIn/jcge3ipSjlycCo5cE0Cyjtw626WBmZFsNSk+8ETWxNYxCbD4x
fqKDB0XzQrwCJEwg5rQy0WGp6vOXVAKxL5mJBSSEwtQhPO2iTgfQvv5bt7Lzk+D7YLTorLXVRZCv
0CXRAOAuBn2PC7rCwnCu/rYnUdaQ6wSws7VpSz9+gbsOODW17ATu4txNQGDzO44Qf4zJia2YRGpB
HUAsXQWGX9cy1qH9LyPodwLdM67HZ294tGLUMaiLiHN3xy1NycfNy70iMQ11T928nRPKUR1iIMHu
OPJCPE6Wuzn2TDXII9WCdUcucQeDsTPldxRPuh5VoMGAmPTsm3PkzPc/Oro/n8PBrbR4GxLIiz/y
CzMIPGVDVpMaY3zrsHLvuVcfEyRICpi+YOZJq3BU3qCMIm4EXuN1c6vl1MTF9YWYMYdf3OrPe+6H
LCyp27WwYleX2xZzwd2PAYlSsTy2vCnDA71RTng46Ws+VO884qIo9/zztIX9DVW4TraRvDil9C47
E2kTjrX+YCe3VN6C2+wdZ3sQguJGO2S4edyfCY3RTBe8fa7yMSy5SvT+S9rs8hAbNpooS5u7zK2s
poSxiwxqB3uN6vzVQFMY0FkBKqvG3MGcnyNRLbTNJSej10DhO7avP5zIi7rWKPdqOQ+1JEKDnn7d
MSJA0XU10u+JI6p6bKK24IzSCrbCu54KK/+rLKbapUzcl3Fe/3jqkM22XbZ/UkCpzKAHyQGNXxer
q0U+YOPWFYbH4H/3/UvYMmaPifJJeT4OjvGB3BJeCD1i4aSxR6k2kMrKZo3Wg0M1X/dFxSUSL2II
clcjiin/kMhvEBolaaZvAn2uODxnl8d0tD2ghZaoDHNgVoZb2N/cJkolQr/rex2Uq/39YXEK4tor
zIia7AaTSSGMZzE1fsNEjBYrF/TNVY6A5P2eHA+0Gg5VucFsYcUX/5hBgsqLH562IOzO83iT7fdT
nIz5K1PzI+QadwKpVnEeY9JlSQkiWIL8zBt+TWZwlZjCnprx/Cm0yxuzaC7MIQG9JrBykeK+wfKV
7pMLKTphuE5mfLWbK3N7K51+cjZN/evhymw/gIUQE4Wv8k8VL2gkyr1vFiayF8PCM5i0ia3CW6BB
ZZGAwX8NfF+vfu78dr0UbmYp+S1VUiF3AmdyFgrjxHZlA7s/CsCD2z/zycJB5u0teLrJcreSXcMh
pWt5CzoWFlYSlO3komimx1fgFnoE9qCKqQh6OtzwRxPTofU3V6VJ0fEgaB8s3KOtWvM/gCgILN3R
uiMcNArqYHH+JKsz7TTkR+b6K47UK4tnh+qqYKRrYNkvPF+xx59Kf7mYGTak7su4b+RqgqHUiPEF
JBBCH5/ULZ7tiUiin5rDlG73PyxFJamkueYer7u1As6B3V2Ti7CYIJV8orhn77U8N/v6HYh0dQn9
LI9O2QPBqqr+mLq09QLpoHF+akm9pnULKInAZTUNNkFr1fyDX8XIZdCIqklngyK2H//MaSjei7E/
4OO6cp2i7+VdPv/pN/t0EgX7BMUnl1etmuAQnULCB+LcQkUilheKMohI1Cvr4ZbMgF9HZu3d+rHO
YvqUYs6qL2qSz3RxglDFJFfVjU+zPX8RjfxEBUwFxzaXy8w3k/1IgTfWHg2HVEnl/x3+7huZ3ppA
eoOATRwLNBd1R7VwkWRu7+/NwRGezYZjzgX6ddqF4q9ILdLuMQQKe3UGjNpcVUxQTK5OodK8FonK
JQdLWcKg+IcB/fwoenpiJqRhYxAiiegExxcUXJGAzkrf/gshpGlOKXBky2FB6RFi5PiI1cxF9K9d
oD4ZZ2Hc0Cy+Is5hYvZuy+eb+d1vP/O8M0TzNv5XDkrJws121nxms0OPRbSE5aQT0JeYbWu/LDhY
2QnSoCILadQT+wmDJlJtg4lu1hYlKRVyhynOBw+R+kSxAZo7DIpKzqSl4Z+ebFDq8KpyloJFZUIb
qxpSn0eu/KV5VumEttVEUdXelLKmPYSSHgRm661NLFgQesUUmP2pRdTRc3Xdh0eI7HoPzK3QoPm7
IumNL+/OSQwGxenlD64i6Q61DjlH+EK4t4o/NtoBaCJ02tWiqxgPKPBYaWALIsQ6n1YGP78bjAl7
9aG8A52xpROoiW/spkOWGavdFWx9MjJEsuQf5zbw3+bzx5RMATXe+9LaLmsVlfqjgTlAlCVxG5Wd
llZYx+MjHLEuPutCT9iRrYaXYd5pS83HpYTm6n4fX9FrV9O/z24lhsUSa4VwnDQi4bsJmbxegmV8
1ZM3ije5dPmma93k/ciuDPjUhP+/3aQhIyzdKHdxxTY0t947dluMtbBtSl497A7ID8BDD5a8qh/N
jnmUluXuWBsgkLDq9IzeWjQe12I+JflPC9FIP5+qntLEH/bd/FAAcb41b1qmEON03sYS+iANEQa7
QI7vRo3PMViU9ClbqQBbUQJdbq0IwR31xKg8VDNhnzy2OxynK699FnosNDri2WTn6jFhpkMg8clp
uBt31eCIeRBeQZisAglezsRkpPhZOqxtt3AbDt6T1K5TO198gUUEU7XbRVb+9htNatMfyDABntDm
hatEVvYuzoaFjAhLWA58kUSi6T6SJl3fs2qf3iKDDzDSIZrVbl48imWITtfAm3kGISn6D+r/bLqE
wThg2iOEYmH98JqQoZ9SgR34E6CO1sAndubE4FtHXvI7FlbHqSrDKzbtofTexVFyBaofUOMe9nqp
9qnpLEo9uICs/dLkhGa7Sy88OCNGlboiaYZBk5sFkh4PYSxD7n2g1N4L/2tXMpb3aLheYNUzfEoi
p6TYQJWxfAxhllWBr88nxZiP7eteWuvquMX/nIjoX9hCVO6CLoSUeRRaRr58wcC2Qu8aH+yHPvHe
fDq/LSjNtGyTE8MYLwLrTX/ruiTnHxicpYE8BS7eUiOf6yjNxrRlfXzirMsRIyw3aUbgo1sNX5FQ
tVIaiAnsGppjO3eU/1CQOHOz8+wUnroSpg65TEu7wqC68Su7TYIe6lnstoRvQQK7SwQRzjKBlj7m
15QpZxIOqp1ZyVRgBQbwwCme45XPVHSC2UqODteOTbGkBLOC1R6mWuTjOB2xZD6zVNiH7w+rHOGO
PbCCRFYynIOk+313+MLxCMDDNI/Yn78cLzXuF8odmM0tfaIpZzC75I5HOggt7oepsgHqtOS/pAIt
ZhyYYo4byKOqJe6bwnOZCJcQ3Vbk83hMAaIxhBQ79uxG3vbHrpHjviJ5TEnXYn2rWTImp2BpIm7Z
baksycTBvu6sO5gjnttnSC3lpGopOWsIXFx/Tj8VoKeGs28pDY2sBdgBjuNM8mizFUbbCNavGemA
WVQB9M1RchOEMi6MOSPzNMcmqfRRgMYpqVTqO+BWNu7LkTA4RZ6doNcGM/04Bn95PGi9Dgc+nNV2
kzl3Lb0ddBW7D8r2uKocR0nQgk8R/W/zqWwv+Kwth1XsPUuVBfwk/RtBFRwZtJnow+DZBpKKgknr
Xd2faRO4mxyJVRYF8M1CmfAKhiIjIzdE/UxBwxyLX+TAiXznYRl3r9pM3j0rzf7x/DXwb8l4kpkh
YacJsaDjWtyLuFWWa6okEQAuWwYG6Rts1g4xNQ+UwoHj97p1JNkmP2wIePQb8GgEy8abiLTScx86
Vmj67jfICjSY3YPQOJVfqAZbPBvGtEsY5aae7WI6+y3f+j7M5j1gKpKyvXyE/nJzkb5Sqmni0ZWB
89tmZ59xEXLu/I2c5IDIYuYGaqzJOME61DZMOo03QGIbh9DTMvAeQBsBEKYMLMSK/+WUxLMkepn2
BD880n28sovbZrDQwLh+72vzwu0xDoCdv/3F6KNaBIMsrK2vzPqComCnm8rnGxkLn7I7On6WmQXd
NVdWBQK0tEoVSW6jg9q6JVAZpSMPr0R9dvwivJwAc0f3daTYddiyuJ988zwtL8K3HPC7FH3nYvVk
mM+opOHOZWiEV+mawJDsWiPBjo3qYHV6iAwCduOPgswCzOknWOZrdbaIpnrm+eNobbNS4iTvwjg/
O17pVyhKEiLuZUBZKAtbulFLA8KoJgAxkjFJNz28zc8rj8U75r5fVhb5b13C5KRe/kGrqW/w9H52
Hbk3gnQtmUJYWLcZywEmCiGhfDrzpKkkYpl/ljJkcMbmjP9O3uYWzX2J875h0FFGpdIzoVHM6P08
t4pA4z3dYmrS5qz2AEDGv6QKyAHKlEEXf9lCQIwh6RTcUb5mM6hRmnULG+XoUcag3M2NnrPGZZms
wneBMpwcKP59YQh1D+kSlnGAMGaNK5IO7dNc3bxgKUZUiCJfUn5cXiDTv3Q1CpcAAzsNK0sFnqT4
pqhtoAVnXNflcnB6jSRNB/ILRA7Cy3Td7C+4otVTGwpOHC5Ov8tcVv29p1qhhm8AyULILIlMvcwP
Wp2oB0Suzhg4zW8AeRFJ9TiLDMyOv2i1vVyM6jLLe+8AFNOnlbe4cTBB/QVMWBoIQKsiEeXW5Uqd
RuLYVxYuxMgrr6/XpXQm6n9ca5JnqsXinfd3Yq8ZEgbJRS1XzUZMmC9NAcrRw6NG4/vfBpBEj1fT
nyJcAhX2DCRNrbZkHf8BZeWYoy+PIEY2vhb7hBBNdJ3jhgpfsoIkUcoks7tD0pveEayrz1rW2niA
Z6oxYEDrnzQbT+7eaLb4Jqa6i1B5stAxQZPemqbkK2pXs0pmLLgbQC7umcuHoExkBuknl/eG+eXT
cxMyQk18QcnFT5rE/7yt+Y3hdKRBQU0CwbzoSKYBnDk/ZCTLwxZkArmAJfb2UiKNgIDJZIWPK82K
Pkfyev20OR3fFqTk907HfwXjKryTx3hqoe5J9X/mHmRTq/l1sQpLT2eGAamsGb6vZJVKbgWq7Cs5
8ubU5mnTjow/JVJIAzPXRDqP5EewEqH0AldmWT+thJazGcRKyLhu8pBQhP8WXCEqVOmamnOBFeUj
CEuNI5/RUH9WlICmEVR8+Vq/HDtSivhDaHIDh28blWYgJkVHFyoQo/802LT4KxXowxWHDIR3RvjV
frZS1heBhHpsaEXbT+uDOKmKc8NTx84rBSvS/1vCNOaCC+iuc0kwJWvSPSDcDB7unjPE/Ph88Lga
EHnkaOmPYvJA1SIcOh8g/oGc4kDU44ZBBvvD315VC/k/SS7WWqDELS/F8SlFihbnX+TxNCHgczgw
Ozfipd1IMb62JTqnVksdamWuqk+DcziWp72K7dtd0wiXBkZVi4aDVyn+tZ+LGF/22NU0udoegp79
lElzA2Ky4Kg69Esj4T/0jvmVDOKLlzeekZWCau63MVP4LKFYtK3bRKSRklQgfchv7XXLLCdZnDAY
WbGR4FjqJkMii9QzQr8pYOKQ/aDzVB9YSh83lJLyhdCN7f8hy4o9T7+bnqeZhMG7o8LguX9+5t3t
jKgf8EHz6a6dnZnKjPKa8UYe0+0aHVIs8cjNHS1uR8DM0CQ9dW8syIsz657OJl07SBiAuda2pfOQ
FC8XlkpyQ0I8X9M8c3J41wFJLXie6ssfai/S5EY3qaA27KerDv1jRtXKYwSUWozAURX0R/3Lwwap
yt1YmCKesrWqjQ8G94BKWKdq1qM5TGn/Lc22VN1fYpZZtGH7+34L1fxmHqK+R2zhrKvh9b6Ihq4B
hyRcDRUQ3JnWcFq8gtcN6yj7zsvS7vn9XZLVu6EUjl3JOF/j8ZwwXXVmWP5RDLYdhrwBUhw1nzBU
/P9163UpV/cDncwL+QsTIWVVH8aar9c52yRdXAoaavcFmWHuXxQWTHc6jeCWwgf83hWVSm+MR57k
xpQGOxVpX7Rq5esRKDcxga1aBX9XtYFYSrLuoTPkb4T1OdvV017gTNopApfLHBHxucKBUWms+6v0
C6o3wy45A6bcy4aJNRL9jDpgqIPyfLRCfI0Q5jKFQbak6Ax/bRuIL6G79htiJRQqfR6TZFTAq+LA
GCQ+iyFpbIcC+73xmoUKA4S+DYztZZQkc0A2M2eY7gvwq1yPaj6u4QDjCHMR9cy3vu3IYwi8Gv6Z
dsCuWckDa+ajOYF6QhcbKzs+/3Zv0QKsGWcOiAqJwoQcPSTVXWzXayq6Ij9qE55v5Q2lg7ArMCCN
kUrHyRbNtamuOLh4gLxXx8RiXjj1l03bCpeDU21LKfnRiY8dLfYUdcj39FuKdER6H+y8Wks3UQ9j
3UFEiOIBw5NNSQoKQZk1tm/9x2LyUTQPWsMPymT35dOYcPKUVf0aiKFk0nLB2WjDMz6PV0v4J9jZ
LXPe/qUm/tB9yGvFRIxy18x9RV8YC35Uz33o9D/rkEtOn0ab4zkCTjPqegvOcILpljkZ2TcOPn9a
BL+WffLcaBW0+T6sDifdVMmZLfQuJO6j+Y4LQvvfOz/F8f+oUUsVPYtJmniifW+j9leKT6RWkq7r
O+Gcfh03wQbpqheMoTdwSdJiH35qg0eibNYQne0+W3v6u7is4L7CDOMFwxBl8H03CnvnsiFE9BkF
2oHfXd9q9A1S94gp1aP/J5G5PK7WvylS1nQeyt6RQwGtfvWkJS1UQ5JAsS5BLh/1oDUy6PlhzCj/
Behiff91BzyBgwKyZdtCUJiTjXdW+06FNss4EGWm+6bHRwiqk/nWfpTgONRUUzLdVPT7LU1J7NhJ
py17rJaHIYLWfpKVJ14wtcFFYVteuMIEXB5xVD+XHKdfZxwm6I7cGI1uBJA01yvLDKNP4V5sGHgJ
PN4R7ZditZrLzzo3U09Gqc6+jzCx41CALX8GRpgu1pEWtd2jIRGMdgjL+ynUYlVzWeYT6BoyoDO5
EB+wiRWk7w3L/Nwe2CN963LlF/PUA7XksGDuXD7xArmgtAOquYuZMIbN6mhz3wejddsFBzsB8llz
f9M3hofYFEgEPTS4aWvKRiWifj6pUy3ZTE25/ILhvhAe/yJnNGMDeChg61gE7+auCQgCkVt4O39Z
PH2siP0UNog3yuk0ahZEUHXTWcw/hwVr15APvy9qSCJ7ciC+xSz1C8bHsfi02IZgFgG0LxiqpyTb
l5syDS2kpYitb0Mu3CG5JQDqpNss8T4aQ5WuW5Kk0XKM0RWZbkmYDBsrtaYe8iY0Z6PN2WpLPyGV
cCCB/Mp7+/HRvIQvMFFzy3Sj0NPmyxPx+1amG2rlOQEsSFW2vpL0RX3LEBW+gHvZKHD9kLwfiRuK
WKVcFwT6x7vyePU1543JX8oCslHGBD8lfyASZKEFJjNJ3fxwG22Fwx8BOryVQ3MYfPhm2Ct7AD28
2NYriBHmRjcLxhKB0veZx9qmAARTfzo1rsG6esb3xk9P/hViECDhbB52bqJKewflVQm3YO6CSXXJ
YY7uuxLpD83agh96N2KCItdS5AWKdXv/KB6c3mirNCpigL4Gr4mOA4Mk8Zm60JBvd3vdPffSrh2w
A/DaKVl5g86Lbkblyi1ZYMFOjTfYfvaGLYcrrvZO32QfCf18DO7x1R6VPejKxaitDQL5rO6OTSAt
ENXIdsBpfwQDEO0TkuNCctR1lEFuKPZtfCYmrgqIOH4Q5S4EFEXHkZi0TeNkYgZLB4jFryIf9yk6
M5KTsV4zd5MUR0NjYAn44d7K1E9GHSHYK0hBQAYHchaFEK91baz96kTstI5UH+U9DGQZKzvmisW9
8SvNauxUqDIW/cupX04iK+mJCjGMj1Jw5e+d4UQ9DGuhNmeBXc3UXqNcv6eDMvTKqxu6UHtDb2jo
Diz79FDoaVG6FrEa0B6gNQOONg+s3oli71DP1p4HLvOTYHzrAqr9txYHu+oBsnnMl7hVvBiSDOuU
X+DrVSASNhmq+awBO7azCvCB+mHv1Z7gUmyeodABBgdQFRdw52ObSinLMOT6wY+chp29Zr4hWTtJ
68Dyor+LwSX7Y1tlDVMj6GqYl886rxc4DRQwvI3d0wE5b85mSw2FEv3Ki4AZkA63McDdZsjI8mPy
Wy7H0+SRRa2QTT0PCcog+UOY+Paqi+CllkvJbrsyjMZb0KdvAXsBOSLgJ4DjrHIOHWhMbWNlPCdq
jGuQBDVxoRd06lSyN5gECZGCx2CK0RTvc7J/KCi0hdmwez8VT880TLrFmK7fDoNHQRwyOmc7hr5Y
HCyeu3Vc0IgfCzhT3ZR3nEcv3l96LiYyisr7SWdPOQ/pt0vq6t9Hvs6HvanLC95bq+ch2DSwtFP6
uoHHZQ4jxm5v5RGTmc5Kq4CRKViLBWnD9S9J5DPdSGQwRlR+KomAriGRpaaVz7V50+PXLp2t7KZQ
OleadEPajWg2S9JyhF0JkJGYHsjl+PVkIVzxWS62vUKBRrIldUMpkLiqLCND8NnMVp5LIYWV77fO
h3OOtzVdASDneNqYfFPbO+7zN5rTXXPEEOq7vJMfQL8PLH+6KRZl4Wz00wdBSWrQgXwCsOXSdVVU
4A0AX8wmnQsC3woILDRaw3Zroiw3B6WPZaCLg3DqP29MoOg7Bkb1d33WnQFdWNAedjFjfrCozVFb
PEKwbzsbiPJh6g/KtVrZsTpUO0+E+6pe5vtYYoLpThBnHTTaXw4XlVzHE9JU+8ip7pu+Ji1ckPjc
e8OAlrJJU+S/76l8shDnq0QzdSOdnyOiR5bj0QR+WZ9fdcvLvIpiiKtVThG3SzmAwpcoTb7k9bm7
74tc7YnKWxYv7ch0Qn0yQGhElsUNmqwUCqHjEavjQVLFfdheAi+uJSNEXZbGHfXTNEgUjqidaOy+
DehXzVpbvoRoJVUGwZJxm5/BqdTiL7eODIFSwNIi45wzcPLP4ntrvIYC2kUWcRMS2KGupNsUue8F
RBGd2Xlefcp4bDdnzos/nPmtgiabD2Dl70VspmBMSBgSBYCt2cxrIItt9zVFRcBut4BHcid7QI6a
36tLVm9F4xV5bfz5jJKY8P98X3ejTq8/OgYVzugcJn7qfWZgPs9y8UmINcFNLIdOiL9chtUVtOH8
ZChgg6hdXosI2T6gpIMMxMfqOgyHp8hAPi2OxdL9Z4usVEVMnqcGM8unvXT9U85fGYhvWTN1AyCw
eGWo9PHiZlZiPV3BpWlgnec8FOwukI0SEDggoiGtV0UUC/MUxW4iikoAQCw7tcRTCCJau9pvTx7C
QZkZ5lU/H3eSvE3Qip1oVmYOTyLurB5XLUQgehxGIJ3bZp8CYslRb1/YH62czqYsJc7RCBpr/UXp
DHyhV4ujcJnGh/VythWrulpq4q0OXGNb4BcVD3RKu3fHKJJCoxniPShuihxP/ZRffAvX3OH6IXAj
ZoqoLwDvwvEo4UIXylO69E0M96LTulG2fOn9VKjfZrXKYtMAaBWbhL1Tqk8/z0iJ5e7FPoCs00O5
vgICbboyQH5iPwEhXcKHhzgnolymddFiQu6PVQzZ0lotqDHdEP6eONxztAA4BERvwRkqoKXHiJsd
+pzEGGfGU84R4MLc4z0sA0Li3S3SBdm6V3NDrgDzmWQzS0Pse0jf7jUtFr5Hq242x+3k8lIPn2Ga
3UvJJoPuQYZEUXj5Dt1REj5+iXJ9j+ep8yfii+KWPUA0xUs3VasX9FiL2I7uvgIsfrYpfK0hVo84
Kpu7fEqL8KuA+t+L1JE/9R8XvI16ywDI4Po86AOEAC0Gb338BcbyJ5limr+I/4YWtaZg352UG9U5
4RC49JA+/KmaHhuvvsZuj2eJ5FE6l99nUg9EoP1J1QfARuBmNVUXkvOP/0Z0qa5RclyMJ4uZb+2u
wRDoo2j4i1/YpHDZOaIdR0UvmSXGpU1RgoRZAVggH1wJPy9B3r6/DuCTaKAk5gaPJo0UTeoXhPMQ
nWSEhide8gZaIWqiL/lTc7tmKjhVTzxa1Cl5EIUXHDkoXBq3DtmHOo4V8QaCrGVdC9qXOB1ucyPX
lstac1luNMPSPgCCK8KjussE1nmkyRq8n48LYnNzUQavStWVXgIFmG97mMX0LOFYQMPTVAPzOvvg
BQUmcmuiOQYnPOBkASeWmNzhuVrKVSJuWJwpE232llLax0BHLPOqbLNBRnyvAAKoRF/yi/ZoGCFr
ijczA42G6yTN2eRrLTnI41LmZoWerFq/RbdM/sDsx8oUD3S8GGPLwNfgBN00g0pnteeixhW8xm8y
BT4Pz+P28mwK6OcuTYDguDh2bOfebV3zXU+jVLa1etuq4yFbPhHO0d16HqrTgU7QRJC5e+ApbIhn
eVR1Av6WkLV5rpmKIMH6pc2B22Iq0iF+M+ctR0lphRlpsiBv3fBmbPzClVOeI8CX7iPS3yCUx1uZ
LsQ+cGYu5x3WH9uGdZOlP+gquSV6DTCnDFHHyA4KWDytyxZprvRXx1vZ3b9D3ZxbIz+CcWUz7Ljf
6PrWP/UunFiZlDKoFTqvV6FI/kOpC7X1ruOuJETApIQ4drukQuKNoCoQ4cHTtz7TrB1PoKtv5hjM
VI5e10+gfkJUezpz8vvvn8NrIvsCnhY0KkY3VM5rx+WB6TZIO4LbGoNfQr7KNusxwzqfKq25u0iv
ydxDBCmpYEFEZLEl7y1QwtSjKuA38Lo01g6ikPDMl83NvOLvEeSzwp0y14EfN3c42tELf8tqUP0I
QGG+O3Z1Kh/SV6dOoz5n2c3uNwxxf/aqnsE+3pdI9imi0atP6Lsx3zUVzjPxzHFwAWZYz2uxd2Wi
GPK5QbUxuPvPNeF9xkiUq9DUAMaqEwH9Cq+U7TRWlcORkWwcGv/PxnI7UFWHimxG/T1aLZB7QF9A
QuY9/G2lYo+LPZvvOIWyYMI2eU6O9yED7coYfxfAvmQIo57ZVxWnc2hf/+b2Gk0WCC8G0GD19T0/
p8VRSQ4DmZk7sSrx3HA8WD6TEujOMk7T14YKDvUGDRbbIhpvXWli0Ag0orY+5z8dcDShxwgEUFYc
U3HzkQso4GpmUTtbmXqn/b/r6N9XGYWppXxv+Sk1u8sQbOU5R+dp3N8ycqAVkzAXD5YIAUllD3Au
eOKWgLovriRmwclg7kaJUu+Y4tIL8TZLpZnbf//pOE4a21bhZBRk2a5tAeYutL02/8VYwVywpLlp
iNL4b2ZoWPCJiZXmvA06lDcxONObqRTXT0iYxqjUMzVhYQqMu4uPW3QsEYS7mrmd2NEK0OGQuQgV
1TehLALtH850DLGJUA/2te+nlOLAgtNItVmnwX9rg73C8rRPgN8/uIRjU8UHwWY0gzk4CHCQ/pGy
qxvJJzq1oVEC2NbKEYmI4X6EKm7f+WNx6UN57G2QJU4i6mGaTGZsqXBvdVNdHICzzp5kw7S7LvWc
zEjjkfHutkYgin11RoVb7vbTdtf5/LQFP5eQBMz87Mi6qRB2/Ii6X9zbWvDDbHRhkfHdKlQYsJjl
laUVAcFU5B8QQXUwTU++k5nAhquMpkvIVgnZL90P0LNHmFmWpKL0VLR4Cs9OC69OT7g89Doxli8J
XpkhF0hEnMQfx4NLwKpgFKm8K7XhG2lNRYHzaUI3X6oKf+kIyTewPMrgXJ/gudVvNMhGPzWWgF4Q
aTA+a7ApTVxiJ2WqsJ1rfc60wZNr39WOlGgsN0EAdM57s/VQIrGbmwamv2jMckJRbM7xPfurzUfv
sDe5+A9AJkqctqgIP8G+TPqMcR9ucs1InYid+yWn+rIQlvFoVTNe8+bKb9okpZ/eR0qcN+8RMylz
J/EwBBqrAPmdpFOt9g6/fG0cpnpaj0VcNMpzckSKaG6Huxf6Iwz/JMFsyjlzHwAKYq7s1zmYbP19
+TM776W6ynGZAGm9XPP13/pVyUuODnw+uxiel0tlvEuQ2FRYiGtXDeYzn6SUmWgPi5ZjOydvP/Rw
FS068LdCYYA0iR2Q0LUwMsygWZ2WvjgP234/dJ3+hr0WEhkF0CZBX+CvbIjiA26yVr67qLJt127z
8mTerqUz/SeNIGgo9u+3CiZhtqUzOe98H0taN3sc8LaDW3gv7j8ZbMP7p/jBcZ9muwH9s/+WTB+5
QdtNmKXQWsXfpSRilc8CxLZzuOo1mKdiOE/gfo5Ji72yNqdvzb5aCnWlN35jyPYTpd53j78AGzD/
6qnHnX7v65Xlv/10+g3b9y2sZxF8fcvQG7mLyompk0GvWmg64vr9Qt8JscZKkm/qo3OLAYG15dqn
gNt2KTITjZi2B5WeZAS5HvCVoDYqC2alDpSWdXPTcuU9ByVF2A007HjOvrQztj6zgmPX3dp5NDZy
lyaawoTCAe5tTJ9uML70qa+H9t2yOQRPeOtoe4InEECQu3hVskS657LlrqHHlQlZtUnGNis+GxHF
OxG48TSSeCOUkuIrTVamwiW5pWu484EYFKCP47AAi58J3ssQ17sSNHa/CSPNlDWjzc+Rk111APgp
zu/oKbWW9BVzHhj7bZfJEQepAtZPqbG8V9CW/qnVDs15eBXhLUUUCON1qh2dKurstpfl9h0i/jE5
/uOIFy/EzpY4122pk3Li2VaAgRt/RFLIS+zTa5TbxkGpNLIOYY0WmzBXqyEPKhYlUUiXXUqJ7aN3
PwNKi3Zhjef1zSmfDrvBExZkGJq6YYGA9wCiA/3brcZf3qDefSP55ICsD+dUt+v5rW8k/E/G7lnL
DmEw1oKAur57vKu9Rz2GPN3k2sNV0xvdhOSUHH5Jh6UxtponYCKPPwxF6ubE1x7vnJJcNwXqzWA2
JBqjWaRSWqHt239aDeXObhqrVCCrqlDmxcGtnxIa5Amjm2g2vWQ0IYwAo+9BtFJKviE4KtdXHIPg
R1ljbyDP77ZPEuq4X4BmSFmeJFsAfrLc8pYHmkFdo+P1MxrRcTddM5Os3hkHKXir1EtNNMuCoPKa
jT3qv84YHBAkw6WjZxbBfic3gKmFb/lmSFaowSIgCMRQuZgx5QixVDzQX0a1pzy44luXSJm1XQXX
SKGiXG144d7yS4P+hWXzFJ52ZFIQHMca0+6b8gxR2On81n8C5k2e9qZYD1UENFIqIjwf/s32u9/d
aU7SysZxy0vXXVqBIl5/oDsW3iz1bejDiJZ15N3FikbPzx0Pi3i0WMcalcjAfx4j1DD6HKF3ssVO
Wvyg4F5QtkfHNCYU6MoSH3bjnzWGyDZoQg7k1MJ0e/uAg3lWOYvrtQBDp8s3h0zl+essjqSnSR0E
2GeRi7WBakGVxQpx+6Xq4jQSNb8lXxw39AJ5zViJrEhfz0Vkjzj5fPM6nRTfQ/IWJn/ZSHr3J8VX
i2sYre3VeiOAJXp1viW9K4WA/nkoOynW1okJiparDa3BT3QWXvO1JbEsEgxU0vI9rKi2I3aENwzf
rlDlrGXYJk2UsaPYm+E16v2LtrYOHxMiCmKlMneMWx+CRgBJVsJ1WlDBaDVF2flCjifPgECh//CK
aJJnPsW5sqm1saXwsEqAVhYj3paIc7/BfaaGFh2FmKnmt7yUM2bqHxiU9ECNa/Sz4E9Aoz1b2xdm
qhODcj/axtNk22ReuL8RsoZTup4tPtQUE7f//M1wQksbWRayww2I5XZXG3bI3UFIwMM4RF/U6Uj7
PaNrrprjxoxcJXvi6ex0EGK1I6BNkgL4JEnjSZrWGG3B7Tmbm7yftKbhQacG+ur+nBqxBYFgspOH
8eCvT3T2hwQ1uykya/6bRpKoB7AV0kDm53R8JHC7d3lq0oJRfWYmXJIfRxC1xBUD3uwc+1H9SuhX
s96Lf5R1I99CUx6SMUbF8R8sl/VxXS++V4sJCQCtZpxFLlLVq+WPv5BLY90ZgMYIB6boU2NMgVER
rEWuVMKG1pQS16OajCClD6/++8KRIIwJ6dhSJ76rUTtIrvW/iSNKd/zspPX9PWix37PH74sCDMOM
g9irzaApMm3CIueu8l85dYDcUf9jfg4LTEroMnRB0cI5TktWMn+Mf7AzgvRwfZegs54OfnibW0Hl
emKtMyBseqfusGLQUcsQKmTvGbtFPYYwL3IxLrK7heyrI9XRl9QRnZmqR0FB2S9tFzf+LNI5SEwp
amoCoMTsMAWM+VcHeCPwplwwlxKO0UmoxfkvG3fxpD43y6ZKgP8zsDV4MBESc9lwBFte1fg/4c0I
lkgBikTSDmv2StMK8zJZclaFXNCSTMqSTCX+ulErqIMa4gD0/bMOJ7V01xEu7ChsHmgNCIMZEZWP
4a4stK2uTHOaO2Ghyr+lH04QimFgX8dCuVoMALh/bon+VCSXQGUlG3xdQLa8q7wVRTzukyrrNBkh
6XkXHNDkgAiMZvwGxt0luP9P9XUYLL1jF7je02qf0R45ntUF91TZdQV6VrTkuoLKuH/ESbWyAgty
Gh/yRSwNsUNhpgttlp65YFRYEgmItNtk+oGb+d5Zov6jnlaaoeLyAAhMgGvcrxoB2LUCirsRBfeh
Kc8cxAKJVH/Y5Gv+UDkK2HO/036OTeetKFYtBDkzrSKQdikj6Gl2dp+vJoqzlUA3oI/pdHbjoKu1
o9VfVUn4ZVQ0jHLwSVEvBB2b/OPsvIw68XNDoSbt95hm0iXHOjcoHlRsJ/pDqsndgO2P4Fo6zDol
FHGcYRXytNcYQQ5WHdW1A02yDVj0v76OumN5y0yECYeMF3nno63dsytJbFM58sbzvJD2K+MPTctC
uLjLJ5ntso9c6kNei1g53Imf23XgObYCOe3KK7mhJrcyM3JwVBVnfyDeeokm2xAfj5H57eSHZVbe
rwdeEFvBPnrk12u0pgY16gh2u+08mzsX2fx4PW0cgZM9XWP3GdftVaWFHP639KXUHK77T2g5ehDi
UH5cT7VDhguo38uwx30aN7YCHcP6JUnKPxQvNKD7GzYkqKWrr8uu34bbryX06uHsW1NnhXF7ZxYM
YJYB76L1o+B7j40ljFKSoB3JUzM4sOj42fwXKrm3jBoaTBAi48Xm9L5+dUUraDoEGTwuyrDPECSj
mJ4QN99Mwr/guNJT7LSPlVWSoXRCAxc2lxoReChp3q8p572J7/2O1+brrUkGhwiR9GcNoi7b7SeB
1uEI6rktDOw0YkXL+psqbYokfuVuK29p4k5vtdDWo7h+ZNAicV12MhVT5OFDeDlhoY9BhC6zZNKO
HV7WiPs2G4NpwGK6QznSkacCPbZ+gqVMjFZGf9BTUO47hUEUnfnGEihTjLB9fMfQnslWsO31qfHU
faurfcxjf+q+B5GLQA66dCETeMVQ/xCzaJxYBXKpyL81ZifWNimSD5kK2ux0Y+39rC/XI061EZwo
opR8CEw0S1cwLgKRiCjiNd4S8GP/Oof4NXLVcFqLDCXtJghNHmjeTwTo6vvlqhl3553sqto3BXxp
BmDUed6yCEszuFt0APus2URLLwoRy26TxkwnXnFQuObtNCoHb1DYyr41DixItH2cVLyPLfFcE7PY
7B2jh6TDKMd68hnpV0v6X5N+Kblm119kjyAvlYs92ze77fKDZu2w8ivBbj4Sm8z8oox0JaMHYxNL
XurC2RNGDe3r0MIcHjg1RJ/HpVfXwKG0RMQUuU8sPAjkT5jV+DitPS0UEQxKepREKh3mzR6fiBWH
IupddHFIt/uynU2tFXk2HLFalzDxkLL3/tSvrAoQ0/K6PTE5vVM8VkCNC0UPwuV1Dht0mod+xrD9
yxhfDodQCsW0mdF8zGhWXum+HXg1ddHmW+vkp+bWMcdofR60qr3mvWBDi1tOGviLOikOvk6uizO0
byq40Jygz/TmSZy0GCPWzXDdIT6l6ZxussQxU3HFJLLNR5y1/Mbq4cwC8bNzV0aC6o2Mx4+HclCL
FP7YiYNPgLgKfmhhXOkvWQ/bfzMRFhHvEsloreFEWGEEYIa/NqIn7GywDxev1GcN1WsXtNJzGB08
OxAtYl8FM1hMnrHPB/b6gFkyfi9tIkDJjuZcrqBL9bZj8ImKX0YRnhCK9IFWsfWXXqEnCVWI9k4t
YoqmMqE6EqSEpUCjcaHmNhuWwMy0ZhgfxpEmrqWEu4xbRrHLqo/LivOLbcK3Snr/EzUzMwbWptsV
uplQ8UiwnT6k0keG1+sOqWCGAs0qoqZ5B7Cip1Px7L167+mjbV6mJITXVYkKrJiBuES5Ng0Efhbf
fY6f0sgUF0NWUwkSb9CUmbnYQbmjDxCN6IMTfwU1RfX6H1YOB6MFTQNWTyTL1VjO67f2fNr/EkVO
1Vkses5lrWdg15RKuPjyQz5vLXI0YQCidxbIPXynnBjiXk7omEJIcJjnPLmUq9dYc2rJX3l9g93e
yzkhKVm9cYB0kJ20eqfK9UQrrIeQFvgEAh5a9gopd1CUbiem58qsVH1batZOh9sKFPJW7mt6NNiE
2vSEwkw/Omih2AGBCXJEVf93vYqbkskRyWScKxPjfYBa+XBO0cD/3M4ZQncfSDBUz1pyHWhr41f9
XUA999IOVoCP+09Y++cGb65LJsqgcnzoYPuAIrugOz77qq+K8vMKrp7W0KhxHZc0GA8Bx+bOQBLo
iVFHyK61A3ziZWbQP7PfYiQAg0/y5L/uzZ8XCgXfhKICGnKMkROS1XD9oV169Nj6Zup5wcWUrqup
0s/TeEJjHL35epV3RpU30AGYW09Lvo8+42VOJl6TWDatpad+au8LBz3F1P7cJaqECyQy0j1zSrx1
f11LAOVQJLKGIzicqFiQN51BSA0v+HHr5+21vPRqz1oAhfaYvEUs1ONd1v7RvgEwgU45jf7OXfd1
OSRNrNdpqmhM9XF++/8ZERsN+2kQKWu6j6pR9bm9oB8a7IvyTk3gOqrzlX7Oh8dEl5+UFVd5QQf6
InJ7BxN+Rmcft2+YVEye5aA0WI3UByOA8gOa8aqvzGxMJ3CSSVHeIj6shFcXMXR1CvpyHdNMDkzF
HNDAlGlr568sZm6R9sM/wFtgWL7Fcmgkc3QLWT/jJVLtZxZe7Ixbl/hdduU0wqhe06Nlzv6qt6iL
EckcukO/Ot6n9XPWGBuy6+N0bM1PIFe1wGripIrv3Z/XfkYK3JpWp2I73t8WqR48dSOh3VeleB0s
/mI2+mLNEVjRQFsHil5QL3vwVof9oKDp+qjNyoVgvIWokbn6nwasnPDo6TZwD/Q3EAGuR1kvbQK1
WLRlxiMKAHkOHsU6Dh33FM2plU1bq2ulm//BnFNhepmK9j1rU1gfqycc5GVXAMa3B4OeZDqrDDnP
zetCJBNCgwrLBoV1WW6TFOKfbsQKE+FPJvpsUhqiRDdw8yIw2MzcT+sK0o3fgx2e8HIt2raYaeiT
E6ts6CgxHOandedrAf9AtPRrc7Q50uWZiOXJGoo4U2K1P6sJWl0nbuxt4krtKTEXXzk1y3MzGxEh
ZCYBnk19BK2E1zEui6zH8kRr+R+T3skL/O6OS2zPk5G7JkOaEB4xBhdnh6B8W7FVrsk7IAhCNBpx
j7DZ28hPKmnvSdDQx4fRW+KCq3ogPk09Snz1m3DR7ZnCDVd0UjBKpJrGpqnb1W+dOO0rnGYc+Usk
h8dLxzS0bByJ6/yzO7zHMlSj+8JTWm/qSXTXN8WxNs8MPZ1DgOQbTmwnwCMREUWHlsI4IMgItHgh
yi8QNtYRJIfv8yqi15KhGW5CjgJfuCQIYgeqf8VF7X9rn5/jlCrIIgSb6Xa3z9pUmIBZedUJLyS6
k1ujI6oKj2yf4SVGJ6LKAHawoHO3TirqqANaemqGQTCRAgkHB140C0mu1DuQyBxBPGVL5GMz4T71
G6YQNwXHNN2mfYx7IOdSQ3FIIvIa4uCQShL4AJLweSGWsu6oX6CjTLzrNPmWvdxGw3qmAD3Ij7+W
gtikoBTxTfnSCOiuEqY1nE4ZVy+n9GZehOdPYZz2SJdTHdzo0Vp1nwySHmP9DSUTq+VWQ5vNoR9m
zBYPCEmh7YNet5K/A5ieTbtENJYTMd0nYy+u10sSW5rsALHiwtiwOSg+NgvZOi7zLiqzfnfblhmS
g3ajzjzmHU16cUce6xN2bl9dOx2PsTRzbjbS8SRRGHmVaEquikiC0iCipsEdrTsJIc2uZ5tR5AGz
zNOhprZWfpQK3vPNVz6eT4d7rPnmSyivoaYFPk14PeNx9XtmkOItkWzc8j4dbzIfjgRai5ptA6PI
FIqA9oRclSWis52gXpOdNgRR5Afv1MM8ENe8GzyxdHlSgMzvMvzBYV3ZN63iqVknMVra/t/SmBjb
4xnryWZ3JruoWiEv2PrBOGoeZj3ocrDjsvaR4FdxgcFKO2qU9CfEP6hS3J+ySUtGVOnkM+kvMv9D
/aafhAZc4JWEEO2PFydfi/SEcPtJSiKIe0IEpJgkgWSNqHoj0a2lBj+HhBmXUBd3ZKJqKVx6vZ78
T0l9JrKOjyIoP8I0ElndyReGeJntgJQHrqLTfbJjfOPBDOV+01FB95qGry755QvIU/PmtrrQyWMW
NcRRaEJVrJRAHOnOT4aoKkwgRLKg2X9czfeVkT0MajH2oAhHbOKwhfSDi1CHj+MgCbCheWH73Z3v
KOmTzlNEVrV644V/k0U6xZGMjwu1Le40miEOSwNfwhqI4ggXGIdahRQmc2AaoFYi0jdv4yHdib+L
nBJtLyGcxJVhbnU8pszeyxPt8BehLbTMdMCMatVAfSghR/q5+A8Ndzjy11IIIwBOk1W4eMH4+a51
bP8p+q1+VWpeDzCbBfyAk/KPKG/KJjN1PA2bHNlGNYnYhGxauPCPsumwfm7PGHhAtN0ey7CCDOSk
G5vLdC2ZRfJ4B2TDLHp8wXKmB8qzGGNHN8JBB0SQmpsRjF74pRTbs5MLcltzXGEW7DHTqh8jHoB4
XAOOVcriOjG666QefiTUYvwx4b1Mvq0xeNCKpeZuzEwmuQdNAmQjCxpGgnckdGNGO77a3IPtCmdO
UX21AlFdTRIDMyPg/VB8ZoxRD/GVlqU43DaSVSemW+mpQw2tCC/FrRPSOTjndwPI6skie25bx7AD
VUZ23gBh7wbMvgzzlcfX3cGfMtiNKGs5cmsqf+R8laTeYmD6dRIEyB18YYE02iykGSMT53XKVwvG
j8j3i61jTKUjO1/4ncEHj1+/0mwovYxuJ69y19kP9mJehQR3B2C7bAeQ6yBn7Q/g90dxg/LOdsE2
BFgOxER1/PbTy+URIqo6cJj91YPuj0pqQuva0C6mi1LEWeyCrjlOe0B6HCRHwXdCmk4/HsCsKjPp
C33l6/YIxekOyiqlR9SdQQH7zyZQH6uk6hGhbxyEz4+guTMBGeZIrnCuitt0SmZrackPRvH/lke1
4JmwL+45gl4GDJZV6HzNouPEmMVJsfCViBv4PY0FqpccTszUFaUQEjZuNV3kd+7eO8nnjQz9Yk1c
eFv7+l4qyIOJiHz1LTx8xRwsraQNrTuOE215Emripz0Y23V1L0aA+RoWp85+lWRxkepoeKAzBxYO
1/YDq4VMzVZo8L22XoojajO3KtTbsXrrDl3pwSUsNuPE+gdL6SLMpAG/Fg9NwQxOrJIq0+7YWm2P
Nb4pbsYNC+/ge5RFxaW8BJtpwqdLdbuQFoBpZJkGKSGixlzlvJUC87up03UEVRimBI0gpeSgL3/B
/W13DwiqSqe0R8GujEHR/QbRYqzHZ7lv6X807uK4wRCoieZxD8DeI+l+LXOL5dZgvAQA89mwsrXb
qxhvQwGs0/KFWJGTPWlwsDv9Zq524wIX2lakIwxBHCaMpaaJVSUG810kiMUqO3Ox9eYcpjAyolvF
+PDfqCQ707yVaT3rISJlnMgTbUFlId0gZxBeuLhQyFiNaQCl2wv/IvjiAdNvN1etMNG/86K31pdh
xL1chkc9cq4VfxtuXjHA/tdU81bnFBhMax1CKXFgVW/V5iFgTZNkD4MOvvsrCivJsKxCSA6n7el1
KPrjvbt01ZOF/RdBB9hV7fs8t5SM5OLjtsKUJvdlG53EMtYkxqC0DAkokAc47Gn6JUWj622kdySN
ktc9R29068jx2aFh3/dAsGzkPlYj+kOlJSaFGlo9zQAi3KzpIkf2v1e5lo9IEMlvolZAOonad8ih
1hmrUEWYK48JVwxC+HGoKePkoAFrQ7jk244pNaXq2dvtc0DUxlkze9dj7i6X7BW2xk0BNqqlvSxc
4c24qZ9Ye7GUdks5aNKydXjjGkdOdseqfnK1+ivv/7Rs/xWh4WuOchkCcFFSBi3M7pdYbcdTaqL3
dANB7twSRqt5CLhao1iL7fgGDkp1BQJoIcQwv3/3nBKzak7y78XDdRdzSWE3TqjKrU88RUiNOtNH
ZV3veAljluiRETnJhjsPJZL0tvbMfcj3khcR6kuv1dIzQPVA/zPoUP5qDEZiP6gkhMzH4ui6CWYr
9SOXky6KW9UZr+tV/uyI5B/6jrYwahf6SbxKJxDW7uzJEL0UypfFBBN2zh/VSBH/hJj9jcKYUT7i
mFDFVb8Jf+lPmu4JFfeb2WKzodlym6jnfVHuVABbRt3nL3Ld8vdP7nTgesBXr5qKBAyPuGW1itgC
jTaNa925puL8qLR4pk/++z2cTkxFWCoqyxAwFDzWlTynMJjqx2adC9a7fQR28SSIxSXZgGeL+NIp
x+XVu5S7J9B6/V0QOLu8X/h89kD/oZrC+oQzM5JVs6zVfWlFRmN1ZsF85Yw9aov1rV2OSM1/1YXV
VcNCbUEDyacJVJ5OCgzFemI5hvZoefCMez/4Acx+S5/CPRylMZhIhQvzhOC2Ws7SnvnYwDIcTKRq
pIyo9zp2C4xiE+XiqE5dpPspjKIroDQ0oebGExueh+x0mJO8Ss2deUoxd/AssKFfsIrc2K0+oMRw
IemThFZIk86rCo356XTFdyNM5LEsaXXKH9HN95T+B3MliGkD+NfB4d0PMpAbv/nIJP+DhEbwfYmJ
Gzh/06Ov/B7daYPIsd9+Cddj3hH0gGwPNoVUht86p8d2rPSf9EGPlL8VZg84i0ygnJePn86vnI7R
YDokwBVCCOiI67BLyeigytIgIISnes9BilKyJcF5QvCAeuqoiB0LjOiT/tTQ+jl4+vNjOrKZOW8b
CHwIchn2noBEADIjgyP5ccckRPq5Xu4IwWpwDlX1qFsFUqNwn5basG/H41FOqXilNIwmKdFwZ4nD
GnyBJ+5s8usKXuw80865bGjNNSNFa62lnfKpJB0G+/kV/LgnucxGQRiuKN5MyFmrfHwUafhKwHMF
aFl92LzSwA84tNVQGSVx+cx7HascSMb+fezxLthfG7ux/4H57CfLm4YMbVs4jzii8Kd14W1Ln9bj
jHZDbXAF+jPZMvP0W8ahDdS0yUawHEfQ1I2roL6Q6qygpagVuKGLZ5tmndQV6MUhlaxpr6XlZosZ
j1bn/XapXfXQyDFME6+j3ScrARPC0JbZBhLiMNKYwSXeAwnPSo3JGjvvDcSMyCDLdAPa+XNf1Qm9
cBDXK5r10n7vOtBJQDltMdbw0/OF+86ZgRJVjuaCl6mfuUKfd4DF8cPCrGz1Ud6SJKpCoshJFPOF
cztI2Cvd0CX/i4OZ95/f6WHqD4Qg3cDpruXvDzX72UOYwt2eWFFWUCxHgjy6w3Ser8FxLGDy/pzC
R4S0+VM4xiiLAsnTyKz9d9zt87lewReoBDkTFWL/G+69992aXPKLkad0U82kQ8RdXjaa7vAlRxt5
oHDnwMEKKg52dfUdGnUmA2krSSZHZG3bg91IAO26rTYlSIQOARAOpDpXh4dwbU8dZWsBdescJgrr
Gcx4+E9/Rs/tX6h+A0V5CQingwoMxIni+61q1vh0l/zfANznL3cFM2P3coLFVzi2/jokcsY6nAbb
MqiIuSXIS6gkJk9cWHstTHRixdHZf8NWwBBSTVdAfa2VfUC3d7efH10bAcidETwkJAKnqEAAE3PE
rNOWah9VKaVI6YsyyS0IIsSdQDUr9CamNiDH/OLN913qyFNHwL059XI2kAxQu+WwiYoFw5Z24Tba
ssFV1bkPZvJMkN36exuqHwxktxEWpQ6rNrG/Z+QQNUnY3aYAb70d+EFp/EXaHkBiTdQFEm274QmM
ih9cGV/be+9xjTjaiDQdgcn/FXjFZZW3GGU+EjF2Kt/+IMGu+eTzzfIIuK8fYjrwDrAEPTdadIX/
1D1IwZdti2GlsGOmoz1yKqaF/bKgX77gDxNRazqZNcDMuX3Eaj37uv9xejJ40jrtEYcZpxAJ4eKm
7QRK5i2WfA45ykH1eXYhZ0ylxaB0hAyITW2APrr/r5fiHoVza9azBgRtCLBy1H6arYPz6PCtfW66
aRtlDTT/4NS2uIAugWF9OWmXdNYph5UG3BGdxV153M7VLbljAA0pAIDvMogiMm0lVKQcx96Nt4oj
IC+6Hp5a/PlQLYRbjupcK/GevIDeaGPyzG47+SFHv9Bt/GnV62oBup7VBruRZhoth5J60BoA8WJs
hWcnhfsrxijwO0TEcYOYw4GGoRyUy6jx0SCo4t+AARgAAavWtBJcc4iS5Pk+lWZjd78s7eF7r66D
3RXJPTHU6kX47Yq3K9P0RQuZhC1tMqlq1ifWKQ0dUfJ3fXk2OxCZtzotXhIDIW5xpQkUA68Fl78S
mC/2f09Ch8zy/9/+7ncA0w7QqOWxAEmYU4fvEO1kmKPSlJ1UR4jkWzY72j6BTV0M2A5XyDYBemXa
ptZoOWVl6pQwfoMuYLmAIZhLostPvRfogmrw8su2U/7+NyOi3i7f1Vshn1sDfQNQbGId+H0G3xHR
4HN6AJdxT6lTiM9VwJhBL1lDLlik8fPXWjUiP5jIfBV5UM//AyGDLEMRMHKotvZs4eUOOWskFT4P
wTNOUTKoRonUhe6elwounTSHeO+qguIVcfCEuL+ufFslskiQy9AfmrzkFwcp7FcidV5gVbcLE1/G
AZE+TBtsQQ1/6iHussZN83ABjDjtVbCh/mZqeKzCnbyvYWLNxCRUBEJDxuW3T23PF4kmnFeZG/i9
8WTVwWg41kcGClj7qRboERYnxR/2C+ikDeZPt0CyCXPP14zr1UKjh/8kdjVjoZ+DZLs9zeAHl1vM
1DduBJgzMxmX54lSnVfnnJu5eKco0X9h4319sGph1kSSvSkjF9X/2JeUCYgEd5V/q/ZxL7ExgISA
avG24pGQT0+MDlknOpGmh23v5F0FMIakmm3/f4j4x5E+CxKhp0Mr51IQL17Aom7PrCOC9APzjxNV
GpXjn+IVpssJ+BeaYzt5KqpamXGcfrD7b7A+8GEJuC/jPVNWsGoB/d445vfo6UWLP1HNk2jpB6U8
Wslr4g2zD1nIPvxLLPTYi1ShJHGwIxKWfz/AeY+fqL9S261e8QEpcDalaFXqj4xpshoCKT9lDZHf
6RAhpd9PkBACwr+9+4hr7cSLfmTyUGZrbFqK4S9NwVPcpLEbcicEu0qmAgFZ4chkxPVylJeVqrgC
HE/nkhpwzCCGDG1X+sC8Ly0h1/aCTl0pQDm/zqNOT3C6pKFkJz4AUTzO7xXsyz8j7l1l3C2wCtKF
Hl0+8r4LP7nEt26D8946axkjUjoGfBB0ax+0wZGSryYdJJrONakKGjsTNymUtY3326Zg3d1GHq6g
6LhDM6rw0EyfivwRz7KzlWlvc2WKsWmrRDCC8w+qHQMIV7khMPtVfqTzjeXnnjwRlAwKpH2iy4Sd
H96Aq6gvTLGlgGDkCKINbfAeCKbgrmTfhq/o8ftlqaI7l8z+Ka44sPwxvfMzS9kFtZy3J6ajOViZ
QXCbT23QWR54qmHeHVyn+jRgChgmMgGk5QFXD0LWiXAlfy9RdRqQpCbvt4y0MzUqeUZOGCxOXZzV
qMNVZRdtx2KZLHBhF2PZ5pQsDOb5u8P7eDbC6pZe5teQsNnBquT6/cjhB6i9RU45ns3A1EMM/6OS
b4WS0SWSTHgNdltvBqA2jvtYivsBNNoJ9jp3St1JPCAXd0a5BFxqsIgvkLVWBJfGQvu7xCyRhhJg
Jti3+4/60q04YpHhDOMYXXzu9y6F4GYQjoD2zITIA889HTcj2y71NqY+46WKawW32jchXzGlvnhB
sV1NGvUwBrSkdaj3Az7owG9abCmaGe9jmUaBMg480OdBJxGHLud6erihatt+byBAAeSAzHwj9sFf
OzVgX0hI6DmdGwuqBVcc4LJJ80wRyv+ecRGjFgZb7+NA1U43spV5Zb6cvrHh3MHQNtPaNOebaeFU
uAGhGoKwN0X4o6nHbi0lGBZQHNEdtAkl0kHj90NpFHxHRyu71OJYvlyNFC9xwyDrn0YVvnuCzZ0n
FV/gFw+hO48IbJz2MhqGB4fA7Wdf+y7HFXfbYbRnJcJx8pw4o7WXmJx592CROV/SfAQLsRzijgjk
vEvFDlPGGdSQvjpmxL/WlATPknFLwpXOYF8uhtDYknT+2fDkAJ/G1EjtFRUPFoDcaF3DoNMPlMbG
HBr44SIR64nTPYN2UvCosh3tq+1JjNUlOy/yHTfQ4kMVrgCsBaY0hBl83y/k6Tv0ynRyoDDiuxFF
qgyGw33SKaHSh7DAB3tsFCuS+a37k3JTCI0aJYNcW7qE1R42/kfRbZMaFg/TWNo+p2MdUiTfYLnI
U62Swyno40Gz4jfZtGoSt+lDZnSloZ0fwkLclb2HbdgrwsxE5+FxsTct5MCIBgGr5qQp35UE4qky
TcT1WvDGRxUYgNnxa8G/Wq1xReKiZ+x3UJJwcxE38SmCCK+jcFDeBPgthzRvb003PRzMrPEA9TeD
zVNX1eO1lYXAWvBsFaoDgPHVdChXYe63rFK1z3GdEwP4kXcL34wi/guXtVdKP8ExiGIXdRf9bopT
mpvj+WWvrvWj54R8SsaZ3QYzckfysVe4vt6uAh6JWCq2i0a+VvVLZgDPlXhEZyGicLnqz1fnF9sZ
FKX++Wi96vzabXb+LVrvxbvFAkKrhG649Oa8xfV85fy4X8TjTk5fhAVP87McJ2yBwFps7Dy/33Cx
4R2EUoEGoqSwvfvNlkZ1aQFMKREfCcPiJhtYWIg9S+ZGHhHp90llVHM9qY2RVLtiVZuENYQL5ftu
cBxbac9oq9b3g6eiH/E66rZ+P+HLr0VvTE6GgFAZbaSyonSH/RiQ0RWv2DTk/zA3nCWsZeHWj7t/
hhm4B6aJ17kGvbKXJsba0WlKpUwgJLlAANyCm77WopA4vBCGn5HBbexxOe0ffgzlH268CqnL+1aF
4wYgBwhOlLitJ0kukydJzVnbGIGLM7Ka+8XSTwmD+dnteDAlMfv517SqNXTUHox5F3vGQ8bKMwp9
8mCSJtgaw7vpRJxkWtdva/aU03smU9cQZa7d4Y2Ky/J0dxraPmSjRuRTciBWtPM2UGP6UiewtFn2
CVA63pLVmwgO6PfH7S7KVpOq8FshiUCi5YVwfRRHnDyuaIBQwAh5AePDfT2/lUPLqFwxaO39Al6/
JwvpuoEalfjo8Eg4/7+GYeu29y/1+yGlFbBZPHKGKD9eiO2OpejOnQs4kl4EE9rKZQE8YRmbFTrC
f49ZRi6HsbSDe5LA256i01PQRp4UdET2RvEQFkvyIrf+gmwx/CpdHoE80PmLMe92r4LayFbXOvCY
8PEF0bfucyfFP5NvH0sk3zu52zO1aeQ26d81f6YvTcEQVHlLAl9Taex0xt3addnxQFwwPul2GA3x
7OuTVFEjWZsh7h3qGY+5G8LD4tkHiRxH281MHLWJ5arh9TtnyWV5c4t8act75Lfkw05OqKV/lqFr
2HH1LQvfQZwzuWwUgoctPnWWMVBE/3+hnCIEpckH3IEDxvaBfGiGgzSI2guuu9rogQmmv4S3Pwpc
aD/vtlXrYCBx0VljAvo/2EPehAaFDbcie14kMDWPLCskfXpjuBGHSUsojeeJbTQ5kmVxliS6Bbvb
jlw2+HWZBlxJjmIP7iNnX/gSQp5fP3/sSFXtU0Zk1Hzc5JHnH6Qo/v32Vmar8jpmnDG8z4tpwizm
CQE4Gc8rZL0HtPrqmhxHp8HAzjPZHB4VCLq4mYHpf0DcEsjit5fV6viQ6tJmwLyteVMTQO3jMPuH
ufYeYK4pVe7llfe22oZi0whAnCWAakzcsS/gx4ZDdN4B3D5i1ThZamvuIHQ02CcXhz9qvlgTxudo
HosGpFLbpAVutAWCkjZcpYFXnhe9GdT65btgY4PwR58nzjKWgSHG1OPjQ5XaweZD4/3ZHXqwBh0X
6lq6/7Eo5l8rKhDhCJaISHIcwN3aIGm3vBUPa2+yn5eV4uYLu+j06FefoQ6wHoOefwFY9ZBxSK7f
NLfG+cvkcW8GJpiiZSKU0IRuwm6EvOxgtbxowONNy4+uudufgSZ7xZd3asOsvuuXZQgNosukfk0Q
o8QR5tycskmr0RmKOFVpD6K9LR+x1S1RzNkZdXfM+dVDot2m4aN76iRS8zAztssPGQCLvo5Af18K
F16wUevewpAQ1wOkH6zCLe0hcFlH5aYaS5ol8VhxULtH0aq2AxFheW+KXT4Voc+yRSE7F+O5RwpK
6LBe2qj7/ZJFOtZSFLGonzPYNiBQ1ZK6ougAdxjab32ClQXSIvO8Pa5zXG1t/9Nk6UMQm9ENYhEZ
X4C2UrXAKsvDKmlj8MjwLPO6ix+Yb7PRUHAVWfql9LWmjvLEywnsi1dqf7syn9DHiWwRKzcoN3+S
5MkuOUP345HhpVYiDykFXzKmLMhrxgYGoj/qldEAV+yubmIz5xpbwWJgE2xNNRNmP8C7/yvUsoCC
vGyHcbZaA/wOnpGoPQt0hFJi9u37F9uQhlq62a5zdnrBLgm7U5pmWZas8AOf/bZp1eZpAhFpRIvu
3vhE+LmJTCm7l917wza6RQgZFHMogcceJx99NKflPFqtYHXNutS/v/YmpkR7+V35QKxbEJCbgSBh
fRDFTexiGspa8kV4qZpC/XstTx1HnzBwsxadu2Jswi+8p5syjIshYaUGmq0AMBfJwvTAQdSEW+TF
VdObhAuJyuZBRoIs4PxnjZ+PU4X8KwrfQhQCZEu0hb2Mc1iz5dGXNTNkchaAeJkbe4yHo3p7ecyv
chyFj900lcDfNvW2tcXaOYqhkosrtZyv8Pro+JvkYm543Bc4eImOT/w7dj8vF8pyj/zl50qOk5Ib
eXwob2iTSEfXFDgHHjv8t2SdYXvGUaK1HyvXKO5SS5rCFUzGo5R2aAQM4aTeTQX/QAk0y3w9u1zd
nvJDuU8qd6Qk+HZTuwwes862/ZoIeX+Xug5GOzg26Y0cdZLhDEND0FjBjiRTC14kcGrtUN40uHnU
NPjtvjSbhavZV/wLJNv89aF2SoeSHb9KWnjNwddX6TW4jBPptM22rlpP5WWH2Sz3Idv5N7QqMfqk
R2wDZuhBNikSjAM+n1fueB5Od0U+ZgByHO0eggXUxHIgi8CUiEYb5TXhjwzzJFhEWaPUU2GoyX6d
6lluM6EjZ9GQRAm5vpfG6BrSWZkXpH27B6PSqlvE1G0u2svs+VBRqeoTZD+xT1cJEaeV6y9FLNPO
SowqQnYymJoLpcc0MSp5dqOKEA8fWynlJGItxZ9GcUKzIQTOmy8hQv4fA0v0sHqYs39JN+yEciA0
4xqnnLC5gh7mSieU20egmZUCy4G250OTd/X5VNZvOnsxs+3vEls+SV8sO1BMSG1JNjU/LySkF1zZ
Z54vfTExe4DhlslfHn2/nskJPlX4y3tIsvV9W3fqoVAAUMv5TApWq9stUspV8Wt1Tqy8Mt26euGd
8tfEzaHms9HgPZDGNfSeDoQB/P/tca+7XDF4A1abhwufeBpPooDCyBG8haAr9RuiGC/OI3M7Fo7U
IcHOBMqiw1EWsiNFhhsTYf0jnmwx77+btWPaoseNvE7I+4vEoyv/rw9OSviKmLWym1BbFCtDumU/
u1eybngctSKdLBKW7CsfZVALztbLIpm2drRI2jAB8kMKo4Aditx4/9sSXQQ1NYg4VSOFu3dAF/Mq
W02TBKPMHq0hAGXng9+YopfDMG25RNS/R+bAiOmNWRg1TWHH9fV/HSIXt0A5GcnMrG7NXcnCx52p
m+5rSTEDLg0pT+MygDZG30cAjOs01hPBsmCNPSEwrtHX7Rcn2RwF18x1Z8gHZWVnqdRO7dKGIoel
t3zKkM3zi49UBtyHxUVUqktSOUEJ/LULjIMyZ3QNa9VtYqhVPstAQrouwQQcUW/crX/JaLLQNLLz
3nO0zwhwWBoa04BBt/vkf4ldQq2sCVpyYuMFTQJWl779K8KR2FUeM6yl/QQRVGW8+VZ0w33kXJmm
EO8TQ97OO20LSwjdh4b9b3HIDBUpHD9dvqFf2ZUtnL6s4frlKG2bJQSzMdbzlWbyOfRJBPJmIh48
R1V4wCpAF3e3HutoADusiqBcJvyzZQks+3qpWp7U12bx98S6lXgG94QBU8/eoELfIrB2TGSrzViF
8vLBiD1jlbSh/+SKMl9CGiRgrOH0cz8TH7k0s5RSgTjzqaH3Oo5kpuW2NCCvYFphYbZmQvabb/Mz
F7Thb0IUF26DOSq/rkjkJJHaQjNX7mpvq0bImMgR9PMBAr2RJfIutujg9iVYeWTD5zhlPJZxD7qO
GJEiaX1Ra0NmtXI3IiZ2ygWkL81nmPblG3KCIWLXs+1eFXPY/0FtC+28Qw45eFuWCYnOSz9InX+e
ElLyvPj03OTD8E0QHPC5HeyITEPGZh4wMPVf2EtK2SX+cChA9HZTMfzwbUyEU7fqe3P4u+OTxC0v
+98v3oxbLXcsmJdhbS/C2Kvg0iBiQ7ilvQlUkzodSeGLmL5iAAuzm6j8VpUG9sEIbE194Cmq++km
5FFXS/uHikNEUffGCQH9041hFuqTqdaB3mnF67xqac1enUnZEgzc7d8ZUm5TcHtUKaNvVm8wFgjq
qI9fi1cM9NpirFcku/v8/f4NF6XiWxP5fyDIbXZ5a1hu11qaDaNjgw4dQpC1sFd+wHf6XTu9CcLf
P3ewvcz5+r+HIhxCkDtPiV8gAGkzfM1Jc9CIKkuGY9GoNlGHeqtVJWD/c/V01EWMiXMTMnwVAHKr
3XDtG0i6IeAPAFSRFIOoXpkWBs6B99zCsJAmqFnIAYswxZkMeVoXZ2CnPUhgUTFN3k/gJADsbrEX
iydDbhxPueBK4UqoIlX3AygxqDVAdA13l/SqQkmiSksIJyh9oleTcPHYj6AKaknUAwsHfU/p6J8M
SjQjnk6DECOXopCetBv0ogtf++70A2BtiVLYVXPHjS0NIXoZhZ9ark9JnaNp3Af/4/HNpC/NM9Og
k3vGZiAEV5QgbR7kMhpTP0W3YicoXtEDUFvAwHPOi0dLl3Ui/EYQiYuhFiICJB12aFx44L23wOC1
FKnm+o+l5ZnTgQYeovNzqlvb0Ut4V9cAs94+xOWwdBsk8XdsQd5SPglbtusWIgeYkMOhf3E5qevR
LCuYsgSQA3FD0rSJjMAPcASGY9l2x5jhYYQ/FS/QdPGBZKO1/B0nCdSQk66+3IQaGTag+3uyI9L3
qrC+A6hPaYfzJ/88AQ8qUKNZLzOFUIjLZjsL4YGXPuoZDBMAXLOBg5J+JT/i+eoIKzClRVGbFgt1
x6OynY8YdKtIgVWeP20g7tGZzEbF/sBy7QftbYtuwRirwfng6h43Xz7gbzeZR0Niq53atByoFhyr
7Nmg9gcAxaQz0ADvgg+PJBip/Ll2g3gydwRFL6unev3MfP6Gc5DbW/Ko/1jpcuWZdpqKuSFsTAio
ySqpo2gr3Iyuj0pGyydX6QrlmXqDijcv6HNQ/CruoTu+Xkh+aiesAQXrqHtz2awJdNt9maQ0J3fm
/K6ZrmT0j8gzbLgaR86kB6k4TNVWFSC/qv9lwGWqxAC7ul/0rOACEqGZGr57QSP4oohe0JH8zyqD
XfCiRSZMapIAH9l4Y/BlEtChGs3Gjhx33FF5OnaKWWQo5WMhLjKdAfL9qZtQ8muoc489CnwmjSG8
3wVw+ZQfa8bsETTx7P1YEdWEuSYAY7m+G1wOS0/ac3tA5dLmRCEkKkc3cW3mfXe27G4uj51Mn85T
vPblXAY1HCorynJAleevdIh7zkB6MbwHxB3gr3Re3WmKmOODDZC+qFcbsM5THE6QDyUe+XSr/h4O
3y+yJ+epYAMV8nMuHT5NoLQcaWHZ183pN1lWEGrkQZ4IOLSkE/WodapYexClKRiRGgEr1Kg+bM7p
DHf8M4VAgBjY23oUUP1fPyOOXeU4eHrRU/ju+VaPwtyTigYQFQ3hNm6hVSVBGRLxLS9ew9s6Fgs7
j4jxdapKM0Auex7QNttR9hbWlXxhtUic3tCgefgsfXZ2+Fdy+Ba2YuO3/3242zAzyiNfcVkc0rXb
e6DCjnsCK0RNkEFhf5E2Bv8mzYSX0ARIHDHMJy2WGCHdBDlt5+OSQc45EdJ1PeBmLuxHgAd/JPJ5
Ep4mYmeJPuiC0dhW9LR1+Rmwjb64uJxDgXYF6ZkSE7gPwgRi+NznM9NsXzDmgiRsWkSmuzxLCNlK
d8x243B4vnXdwZceNfDZ4E/LXljNXRQXfP/ykh66KKcaYop0cMN9uvbyZPjuBWsIpsaP5fzWXL6b
c1GDGRkeGIP0Cq/hwP4oXVfAAFHSdJ47AnoIt7tUlVe19gc5xDHdhbITCAmlD9fqR8pqdNkXxUpU
9xKUSV4L0UogP0/dEUw6VzgrIl5eBppt4A9EuyfS2vw30AxjD3VLfJ5mu5sIgM80Yq5j6ZakDKI3
/NczuTc6RFBg99Pe+Q8pNRwzHJ+E7tTywjx2W4D1liwGraA3NLI4Ec9b/z2udo0jsWvvTFbm5Wy6
GWZWRc1QPdtFwxtwQvxtFv1xmpfrnxuMgfQPfPd2ZnvIi3Y6EBmZ17HMyYXW9raYCZtLjq/wYEoG
lRuz4eHCIpqmprLUyDwJHy+XGUgTo8P6LRydHqXacH5enF0GWsyuIVd5BZ7bhkT8M770ljt9b1HR
KIJl/iMkivGZHUa/1PnHZFMGgpgu1BeHwdFeOg6hNQTwR+Mx2l80wNYtfC3azRYMExDR+aXJ41zn
cPT9h9XfQZyM96xImCeo6pcufHTuFTWa/yfpuEYRILmLZvdywSqbo5fuFbPAoVQhXjKT7wXsrfC2
3OFf/z2+aogpeLjkc8xRt3O1YL0OwI3ESVizxQwlESSgcvQo+mRNUhh6gKk/y1AHnSF0K5bNY6Kd
STMSJRTFgLxDxwLWFoCY2ra16DBKfjr2BR/7ALIe8wnVogClNV57h75y0gS2ZNMxWQrtbrw3++Mm
sskrpBWcAG1iOedKJAIrKZa+5LFt9VinWmVv/IwdfAwvvNZioRbgVYfV9xtQHYx8X2IpDqE7RObl
/KQR57+0Bt6nYF57LeWfMspyTQ+s4JaIVf+ZfNa6xsOervolBE7sv59C51dq6d5rBaccAZJwcNxl
WfgiD8jFSDlbRhdXds3k+d6tTISTZyoZ+cATjBxNlBA8jnR+spsYfvCt5uY1OtIwOrWPxS1YzPYL
rhvBBQb5CQADElX8yGLEUl9NO8DtdP3iIgT+e2xrvqGJoF24yC1W/Y2FnjyJaoLRNsVcG9CPKtEn
w5Mto3Jc92NecJVuADvh844ZzOUGzDVmtvGiNJknzEVE8TLY6YMr/iLO6FGtoOz4LtpPS4Ul54eX
yS6ZZDa4D5+T/M2zJI0Wq09YzXjQCF51lbbxAnoN9DC8oKrgm2zvMWDflkjavFlD6BKiw/f7xvUx
VPlIyFqIC1FtpjevTOm1g7Cz95en74G9XpVrRqbbBr4EiCqPcGF70uH44aXSo+/ZbThyK1JX6H5e
JLsP7BAR87gHEN7/R+ZqqQDEwK0mRl5cpKp4BVDDXkRhyqfHCBQqgiyzHYTd4qX8ifPZVECakRxD
AtcMFkh5fw1PNDqWO+3mm+PZCRT4ye3WhzOWG2Ilrb+bKeTlfhVtm0+1vxmQcfrFJSyhnwhxzeka
NVftAq2OoyyTfU3OYk9hKTqM2lIKyNtxvuWqQiAt9TwtfH3XSFRc25TXOvu8ljjy1RKnCXkRxysg
rE/QX3wpLTOMNoDJa3t7/rmiQfWOhdZfQCSfiJV+27NudVA5UtzkGkhZW36afxdlK24wHAJREIgU
mo7bMpDm03K+7yhzC/9s9U3q9pOZQMJxwn5F26i7YF/BRtltP91dsA/zzryu8no8IDQG1Qq2dVJE
WMsUtpP3Sr1zuGKB8fuEzK/rHGdQNG+g5SWOCd/o4ywTUEyaX+80ZbdShFPXlPqZBBgDA10zQ9/U
Mdi06iR1PmLd7l98RIMpTdjr+Tgk88OYhBAMTsDdyNvr2dw84YW2hDjuUXQisJk1Xf7et2Pab0ox
/ivKJdDb793sAWh9YJHEcFMbeMv2Fne99hN987UG69KbORGnrN2v24krXE0+XlbZ/eKm898tJS6z
4QrCSAojgdg+sTq6D6XC6q+BSBaZh1Bq0WyX4Q2iC7oFVfLDJu5LecmfWmwH2tWoMS+BC0wcLkPL
Lk3sVRplE4OyabbBPBGMusc5g+3uU5EAx7NOGgfw7UcJevgrr0MaEWkPwa/zPwhMzBQbyb38S0Qc
2IZ/dhYkOqEaqteHj+AJQ4ZXLAT/TYi+iV+wOIubaW/0w5Z7yLBxfdER+M5YKDnXxWdRvK2qcQny
XbwuJ0kMHhdmmKqKmi2/FOFuj1NursfzVU3BXIQN/GBy+AGqXItALG+7rLq3z7GxnWpUaXoscNv6
V8RqbO+cDazOhu4ZnQwtv6XjctZj+SF5aejJ7sDxfe6JR1apf5QBc2Io5iEoVrA1juGaeJsN6MNT
JGzYZpTC0UpbIuFIndOZd+69+3Oj6MEuw3w5Q5ZHk9btKuFYWxmg/MM92EG1mCcTann5gceZxgT0
FuZKO9vTGm6QIHZHuUdfGOYaDuJiAuoo+2m9PQRpCsG2k5+aNaKVRgPuM75O3QDY+Z3659e0vKst
EnhH4gAl3pmNbbjZZALBVlC30hQXc8IxIzu6YVi5zcN5JV/WU1Jh1zafVB4NEtb6EDjKsBPzQYV0
ebt084A3NmjuD33RZDbLa5g82sN5MtdPriXXWXpI3L4eeOsz0g+MQ0IyHHChSQRGZd/nO6PK+Hyd
bjLr4JJZkKcEttvcLNhmM4JyynNxwr2i0W4OAMFr5QMOsileHWQ3VQS7ARXiuO+eWHP34NAfJLDm
n/ETowwUYDxnCZTBQx6+cjtUF53478AcN7F7kvkqVBFKZo2KgtGF1YxWQoqIM0tebt4zOKbtOW/p
oG27QSXtBwuCdXk7DVTKu4sCNCarsXH1mWe0FZwr++k9X6Z4EXPhezms7Wsj7QtEmy74QgAvkYqL
OS6se3+UE0gKNfkyi1AHeVv6fqZlQ9uUyMdJp88zQ044SGcgNjBJtOlvV+YUwNrAvefdvnfuslkX
KX4MDplCYBnXUVv5Gt1n7x9LyCGDdulaTA3etzy1G7luM/WryvB8X9TqSs9yMdyGG1wGCtKxc5VK
NS2tKdJE5ANWAaaYphfe5yvH9O6VWlhajDR0k9gL39qDR4FQ29GWKRnhtnaAzpv1M2k1/FmssGjw
lQ1lhnoRMXstaKaqoEqL2AiABmxzpMy+RsfwUBMu1MuXC3xIE8w/KRjjJoC9euk7GOt36tk7CU4I
6Xom0cioCum47wI1WDDJ96dNkZ7otlVGyEoJpbkO5cKBx086Xp4qcmj9hJKnO1w68D096HalwofR
W/6+xrvFCCg8egetfBuLysLLkAaDkMuzjwZToYmArtZKGTWXI7RSOJpxPa0inkyksWSAGVj/m00Y
1d48Ku89tIht3RnJS3muaAu1YtUDSa0wBchbrWn9ZYPq4CezN7o2IzyVt94VmlGuNVwWe12WQ6BK
1kwg4HiCR5wcaw+feOxmxpFiGJReV1fFVutrvWVPgJjdwmelSsuf9IiUsIhXKKYsdldZ2QH84w5f
nfh3Hj+wKAZC6gwx17X7PjXAUVhAlgrpVTsR0nZrobwwJ8dVKp9tIntnq3EnG1HoXDpmqSMG4qJn
Pz+lhZR/MGT06UF6sWnVrwSOg4QsBg2b+TOHWZWgwD8mZiPnSd5sHGIw6+dZ1q1wr5XbFRM2ZRo2
w/Dwsh6Vl71cns+OSWt/5dMdnNzlCvHlzNnLyyoEt8N0t0/gkqdYiuKaJnQXmcGhMVCZG4h29h6W
umT1hp2LbLdOaUm9NqE1sqabFk0W36HB2eA4fZmk427GmXv0GY3XeYTrEgVsKL/K9/suMY9q5bL6
awA/eofB2Gn4KwAJzxx2JSZqobcfMAJyyoic1ZfGQ5VgeGQk3E3pryxQndVKIAhGMAggv1vztv6U
dHkcv/OwEdhlKBJpT/aLTGPZks80ie2w0OEYSKQA5w5pjdnyqmyD6H5I/9DvVkjLc21Krakhbp0O
GiRKKPdwFwajGP0bAl7agRAJ66SZxCNLFk58V1ztTtbo4CR5c8cYq4zFKcpKU4gADRxe/go3/txO
lrVxdvdky1zdtWM18K7VEgoWxpR1FzxRI3ruPBq4h4IFx8dPTJeRY9s5k8Xnoh74CHZB1aoynGSU
CXS/VEnEuZR8tNgmINSdO4QHEkJWx7pSQbFwKxzAYUspoced3YOdy2lqL6wuSD86BKVZNRZZuiOq
NLxSxae3mp4px7KcGFDUdQVJvYlKfMt2WNEpEhcO000blBMz/vPRlKPeM8mUwAMWSGdX3zvI59XU
QYWLHZ/mf/SN5mzVzLcHnwd73LG1DGG6i0DmpsSdjXb74AOvQIikWLO2BK2q8MLLEnR8guG51IT9
XCuP75psO4SwYxrJYIFGfOdmRlS4NsMod79aXLgYdK0qrhToeUs0pRAYc13iKmEtJPVDcywQKWde
VSoRZg8i/HDNXX89AO+vYb/P+FhCli1V9NGclsvL4oK/EJwuEOw9l2Sa0hDSw4ojjRCCZ1FZA5qu
Fw4NWucVdFfHc+zgvfn4m3ZO30wpjLTb7dd4pm8YcklePXor4GemMr1xs+eVr496/SSmMEBazBBa
jUtYo2AGV7r6oEdXnUeWSEzCAxwfLuAEVk437AJzP4yj9ui40/698tn4XZDonSVj+GyLiWSirlBr
+dI0KeUoBTEN4yguskq9uom2b5scs6+nJMIj8ACCv+8kOyKlFqeXo3I+aRIwKItwA2Cb1IvYvEeK
5qggKJjB31s2PAjIXGfCaRu1drytaMNlH6J1exgs7bE6PjW/R/HN5ljwg6nc3KHncQ35v04pcIgB
KZC3qdzxTNguM/6TfY7iIo3zZzeAC061jKZFmX84V3sIuKJJ2q9vhtotjtQPc7GN3xRK35bqyXdq
XBcK4xgiGRcC9oqxjRJwGsznLqxEaM7xMibLiDm7z6A7M5mFM3+HOa5H8/F7giD//WxLEec/93TR
pSZyg2VHcj1vQL6lEcdxMtgAwKYLIwHjxuTkTyXEcKNXjmjay+U/fh9vxbXCiHcCH0KEp+iB6T0i
0mn6cAeCV7dbyb3PvgqaZERkazq9wQ4BFNtwS7/4t5WN9ZxXdzOkqvuIyXuOW2hKn+4nDtk1plkT
7Fu6E+VGYhjX1DufkawRArlPPXg60W8xwNjqg1cuU16WrSi4YMl2xrHxnD/Y7z0gNkt7UvDnctWY
cpkoJdwfe5uPGDdHSb/LnsuF/hSPFkcWLAA4qRSf3dIfCLYWT12LE9ZhkcxY19fC09nBfIksPER+
77q1VpNMdMJsf4AfV32zKjtlif2VSVKHgAD38neCWMlCJtU526sah5DuHgW1gKEyxtwSDkmUzctt
RBAOTU18gc4JN0T2Rpiljy7mnQ3p09D0jOvIdumFUNcO9SIEHh9cTC/D+iJaS5dKtHMygxaiGm1M
7358AgBiXKBCF2rmyUcIVkvkD7fgb26onk+QGheDKIH8hulsBq55XrRj1hTX12LasY9/KkpuRbdg
UqkB5Ds4H9bLSMM5ygfsKVaWz3X/yBiRn/03V57Lw/GWPKiX+0N4ciNremQVVcgy5L8bnbESyFNf
cfzGk9LOo98U8B03WVzY4+TNM8208ZjeG/RiE12WykLnVjzM9R0XB4WuxBJZ6+Qc8+HAxK/2O946
Ba/6kCPCaGM50H0wTOEsrItZh7mYAteqNE8WEJ9AFPWwfCA9T3LEeTN5Qg57oVCrbQzyMpJ0B616
m1dsTMQcpbVhinyezDilS3dGHBObHnFQkrHlyKlsmpB+tRa68iEQkl233Nx5IO/vyO7SOJCHD+Fi
wjQhPATzJ0AsEk2972RTDKy6MbWVq/8qot0pfihDFNcA8cHfN87uJxyj7SEjhqZ0VGLc42Me4ht5
3by152sqyqL+/s5XIx+9dj54GJ/TmrxzAbrhkLKjgetl5BKA04omy+K3yuc9wuZpP3bWyxAqgVo/
6gnizOCUa5/IhfSL0DJRBuIFWtk9tGYn3aXlhkU0n1pa1T/JuIeOPS/AJ43mWJnGqK8SwPiWZXJo
ybAnU8bh9ygbLQpeKYYE0fCN5sKPKQVxl2ZDXSmrty64jr6/3sPMrc4SP0tzkTgd+OoMRfY1dJtV
3d/E3ehBC9PYadK4sOJGD+7Z7sj/xKGA6+eRkO+Nl/HZY4UangKIZgZUxW/+iNukMmOTSc38lqcq
KM0oVwIAa6sMJV8bqmehUAPtV7vMhizE6tqG6d2aEvTtrzsGSzSdeZ9q6jTBraJpr4bK03N7t8Eu
f1ltvvM4UjMG+jcy+0a36A22VEtQoHzBfX0rNaIGX4hyhFmXnTFT4EvDVX7/EnuBZ6ucl4EOMTzZ
ArcuqC/0c41fxjTiNXMH+WltBNrtmCCilhEbVzXjJWCCcRO9LZBqZYMMCbn2YhUbrluNE40TNmIQ
tyMoY/Fw5Uim6Zkdh8lkdbA2dRRzpsn4KH55XsIuH/06+eI0QWK80ytKkqlEScdeEBi4Fe5Vgq1c
03uiQcvgaDygeuMA4qDq5qEs7sJTxZEJvJselSSEgue1QOsQI+ou8HMrq0c3PKYCgv047fpLcv5E
k9GqUaFBXfLiNDdgI9raeVhfEva7aRVY1ks02BkdxPDDGWQQj3VqDdbDEdkAgBmfNSIf6lMtZvHf
Nzr18t43bnzZV86IAz20CUE+kXicP2+pXWtVn5cHhp4jNic8xSk988h4shuhUiuexqys992CnEpC
F3rEZClnP8j5RmafNRcAHOUDKvlCurq4EbYy2st7DkwynT+XPP1iRakvQp+Uw/TqW4uBjRNQBAKs
yf3P1fdU2YTjt1gPGMH3Y4+ieqUP2gOQ5Aa8ZkmdQVd/2SY2Bq10JGJTl4jbvBuAqOkftxIiXlqV
Gq+aHSNjoWhTuUkRxuq3axIX7EghYP2T1LzLmnIzdRDt+nmRxEoUxUgOg4XVEbbGWcePsOMk6acj
XrHYJq6sGGhVYImywen+lGVA0zvRL3kfAgbGTkDEOLs5OTpUDhf8YaiZC950jwl7ihPr66lOcUbm
UI5FCGNSASCoUC9F/g+9XhiZMby3IE2aqbOK56SQh/ioOpGNBcouttMnkrIEx0S06j4abxlsKb8f
POWAbFY4swu1qcdUod6gLeBl4pTKsCCGqVoaT6J2RS3T9MdTJRRUJyJ7kFQZGM5gbPNhaUxtUlkx
AEKBJwOEgsiWrUITytJ1rGI9je11BBMbmv073VKR7DJQcuoMolNvc4Swq0ecfSiYrPJgKMb9jTMc
AR9HjwS2VuOuNlkflU3JLL9zG+TuSQsdQwhtOHcCExJbN57k6ad2mHVAmwTcOKLQwotwBd1TccxF
tios1Z1Itp4XdUyQiqMsE0p3fcG6zESTRwjhrGJrdoWBhFcoGIvg3jP6wwzo3WE/UV4szqBG261I
ZABaAsS9PEpfzpI8+JFxwR5jna4M+5OTI2a7+Ke8sRdHxsSFKk56WUErhRh72y9F17WJ89PC55ho
wRsdk7ljJkyTJSlRTtlOAkuRKLn4pcRKxbEcYUUQy2Xueie7YrF6sxDznhOKIcpLpLK23GhikOHD
y+cOC1Tsa5hmNrK1Vg1xvsas+eQRdRVSGaM5bSpSBwek3q1cXeR0unK+M/CiukwmBCmx3zSR1c2V
QFZgr25cVHTD6+X/XMzGTgSxt25RQBylwRSyHPbP+kIv5Y6nw34SsDTTpeY56Sdx5TggIYr0ucMZ
NPVNcO9sbzGwKVWm8hO9zZvW/zaegavbUeSEkVpqzwiZ1dxRU0wJqPj6yV7okikxSJrSN10xpnQi
SE9MmZzMCdbvm7i4ngmppwxpE54iczBXk6z9xQRXmt3i3EcEAGo9hbSOmEsTIb3VCLd9+dGi+UqP
ircKCFKEB7bC9ECh6Z6UBty2twK/JnIC3QUTRc+UxMf+50bkEOb8utEx++aNmicJsEZST/SR+JBU
Tw3V8g2YpsO4rrY8FjaEJ0uqOzwqBt6D3WoyR4BMcQ6kGrw7Oggn2KrBQ038msGgu5GkWyys2aNp
p99o1GavlLoUz7I2q+N4y9o3HrChQvV9nYo8aBH+6Hwrnh1FtZ1SKGMAqQMGHrj86lDnxI5wbOES
CAkMPdz9jf0YAAQM6jXQjeu3OXhI67N/iCIjcvyL3rEiJtiVWARNQ+lYgB14wUSaWKyBCfx+CMI8
fL9D6Xrug/9nWtyuBzLi1i7yYAW0FXcSLxmQ5FUwC+SdubQ9KvEhxwO5NrFWunCInM6df51nW7wR
Fw9ZezRvbTISOwZp0RoGPd0JcgPTf44VSBJ0A4t3+bfdepM1vH4WJcIKJYXo93AZ65eEZSJuofsG
sg5XqLkywEHqYRac/hkFUKxDSTnlxzG5ekoZw2nuAOofhV3bU4oGcA0fFwsaZzhSn6iLCrKf1zkY
gyfbgSQiYYkk+t4bs0Yr6opz1FYTbkNtInVJ0gWoHtIZCyb0HikZ3nfJm1DFS0QUBl27IgeHhAsr
mnL4h3vALFF2zcT2d3H+PxFyiiUzEs5D6eo37OiKg55EQKD5Q9/FblWrnO0PbIrdFnfX35kpQgf6
bC4xyOUHSgR+VWCjo5h9r7eKtOmkCGyTkbSfYfdofCXV7L5WZT+cMZ1oXcHP6WFUysLsTpgpVh8b
AgJgHI8FnLg9A6GYY/FljMmxbCqU2hJGPJ29fKaV2lBNsvWF2qTRUwLXrjiegNG4zhEjkYgCPAfI
zi740h77/liZeJnZM2C3Jj6rjecZ+GyHL32rCqnW7HpXZaZirS80V+/WrA/UVRMx1VPeu7gq1Dev
odHgGZFP0TyrCW+J9O2g2+WSle2V0v+g+9MxMPRvvy2DzJ59k81JAjLzp4tntSULN7/vuU8RHqBb
BA8MH/Yftdn5YKE/D6NVjGh+7PgbJhtZmVNyr4tvCTNBRvGe3R0EvG7iBpTIeYAKHm/84ORiLYh8
QP7lMD+H4zWOdzB6MUQiZEgZuWoC5XNXF7r9phj0+v5oBcc/Xe7mDYxqeERpMD2e8s0Bpc1I5QAL
BighLJpm6GgonOjq4Xb+hQyvvH580Yzo+avtijfzU0SRCXtzDn4LrBhULsospODE3iR+pavFcQCz
00cHtsyz/NoZ6+PrLXw3Mi7vmT11TDDDXP5RJuzYbJXpxoRE5e5CjB2MIxLFypcUExpdl71s25ry
jGGW1ZlFBZ5PDj6VVId1S6Oz7TKsxXUBxdjTEsQkYo1KyILfiXNYkXQSwZeR+InktQS8ROhsjLHJ
KvY/ni+6OYtY/+nii8bquf6DBLqNKj63U5LAcf2qKqBYLAUvhfmviXfxmCclhmqZ+ZNnUC//JTwC
ji7LnLQj1/Qrq27iYMzRSt8ZR9OCYKbh2/zJl/8ASbo1gpVRQ5Q9/PE2o9HtWeOWf497daxb6nyN
T8qLuBnPyIEckp7fXLwHpu2j11lhwD5MIj5ytll59Qt41JKMrwrT4Z7QKnfDURi65dhYIX8tzEiX
yO2aT4zxoXat+V+lM1IjWUU+NQ/CdohZUMmeS7zqnoEvKZHkdPXhlxGlDOUj+E+uZAT/BDoHlpAr
x7Va5FLaL7o+0kJLaHkfVQy0t8iTA5kOS5f9RLZoZKtIVEpttaYIJmcLUJRXVSTASCkIIrmMuXle
MV1oELWLT3OvRw86D8UJ1GDoH0CEuRpv5OqVSCN6cPDwuK/yK6hkYRIqoFYSrSIVn3hbE1df3nru
JP1CouJOMiLSV9z6Eq5tQ8o34GxWEYUM+M+HYkOPYJI6cQ70YyAONmSDy5nrQRpXkdtmqbOH6pVr
R8AHaFsEK3JAfUThHJ/h1PrNd5br0r7cc2hdIaknH0STFlylDT3yXi5d+CLum5n1ME6RtJiSGW4D
1vT7w4fOoteUvmKTP9PIUNrw8Q4bpu5nPgd7s6NDMA2bfBdqbb0biNwqplbtxEtnvsYvK3B0vd5G
CZG4A2X56ijC1eYrbdzfr/pIfQVELBDYV30yGnvPP4UUpinpXlzDQkoSkTzJItQNOpvGtS3Pjyap
Nozy90YRLzQjCmxi1gxDkwp9gMba4Qj5EhwpMuQ+z/d9MYAhAkCo3Ocl8SwsdTNwIIVw+Z50I2Dl
FEa7FvuBAlX8dWeuL+6H1cC66+FBmu1+DHan34WDv01ryuVJ89JPf/A1Jw8HA3BpWjA2IH/VN6XC
2rc1scsas4jhsjfOjCV6s/dtPzNaC+RYRWVK9msr10NPQ1usKxvvYA58FLTmDUs+WHb2tLy85G8j
euZv6kTXJH79wLVOKLvpckeEh6qZ+SzVvdIPtTHlQO/iOAHQNTQ8VJk0Ouudr0+LGGZM93Qndjzc
q7jEC2l6ZWf/pST5hWs4CQsQ8a9KbOVZYvf60r2jAjIWTfn6o+Oj8OvKeQFZ9pzUYxs7f3djcHbt
cY8KReaL9IG9hEOW8QS6MkR7olCD1I7R92eNUZoWrIu8TPMMPGkXX0QvXo/v4xPXd096f9O1whVW
E6GDRlOGXodDhvJEhwLFmsOWKYyy9tP3ZseQCqoEsgdkGYZX22pFhYfUVpnNt+rMi5NL/NR2kZVO
C78mZekt0SIe0xpPe64Dk+Ivfusoq6LHA3eG4ACqdi+awLMh1FSxYIxH9LoKzGNGiII6mIOZrV/A
Fc6Rkm7slsG1x4dtqusovtCsg75lZzhU3gZ6YBjVHdSWUQ/qzSacAPLfo0lajDf6ohnNvSZV5yFy
j7PHSFl7fg1St5sJAZK3iS4HDVhAiJ275448+6HpayGwcI96fqhvSMzIvj1vO5yYkJAkMeythIjq
V3kNd8GBO/9/9XWwfQGA
`protect end_protected
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 00:43:54 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_ov7670_controller_0_0 -prefix
-- system_ov7670_controller_0_0_ system_ov7670_controller_0_0_stub.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_controller_0_0 is
Port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end system_ov7670_controller_0_0;
architecture stub of system_ov7670_controller_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,resend,config_finished,sioc,siod,reset,pwdn,xclk";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_controller,Vivado 2016.4";
begin
end;
|
library verilog;
use verilog.vl_types.all;
entity analog_mux_F060 is
generic(
WARNING_MSGS_ON : integer := 1
);
port(
CHNUMBER_I : in vl_logic_vector(4 downto 0);
AV01 : in vl_logic_vector(63 downto 0);
AV02 : in vl_logic_vector(63 downto 0);
AC0 : in vl_logic_vector(63 downto 0);
AT0 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_0 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_1 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_2 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_3 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_4 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_5 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_6 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_7 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_8 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_9 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_10: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_11: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_12: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_13: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_14: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_15: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_16: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_17: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_18: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_19: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_20: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_21: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_22: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_23: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_24: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_25: in vl_logic_vector(63 downto 0);
DAC_VECTOR : in vl_logic_vector(63 downto 0);
MUXOUT : out vl_logic_vector(63 downto 0)
);
end analog_mux_F060;
|
library verilog;
use verilog.vl_types.all;
entity analog_mux_F060 is
generic(
WARNING_MSGS_ON : integer := 1
);
port(
CHNUMBER_I : in vl_logic_vector(4 downto 0);
AV01 : in vl_logic_vector(63 downto 0);
AV02 : in vl_logic_vector(63 downto 0);
AC0 : in vl_logic_vector(63 downto 0);
AT0 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_0 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_1 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_2 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_3 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_4 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_5 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_6 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_7 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_8 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_9 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_10: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_11: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_12: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_13: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_14: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_15: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_16: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_17: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_18: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_19: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_20: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_21: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_22: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_23: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_24: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_25: in vl_logic_vector(63 downto 0);
DAC_VECTOR : in vl_logic_vector(63 downto 0);
MUXOUT : out vl_logic_vector(63 downto 0)
);
end analog_mux_F060;
|
library verilog;
use verilog.vl_types.all;
entity analog_mux_F060 is
generic(
WARNING_MSGS_ON : integer := 1
);
port(
CHNUMBER_I : in vl_logic_vector(4 downto 0);
AV01 : in vl_logic_vector(63 downto 0);
AV02 : in vl_logic_vector(63 downto 0);
AC0 : in vl_logic_vector(63 downto 0);
AT0 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_0 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_1 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_2 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_3 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_4 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_5 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_6 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_7 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_8 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_9 : in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_10: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_11: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_12: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_13: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_14: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_15: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_16: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_17: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_18: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_19: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_20: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_21: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_22: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_23: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_24: in vl_logic_vector(63 downto 0);
ADC_IN_VECTOR_25: in vl_logic_vector(63 downto 0);
DAC_VECTOR : in vl_logic_vector(63 downto 0);
MUXOUT : out vl_logic_vector(63 downto 0)
);
end analog_mux_F060;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ShiftRegister is
Port ( CLK : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR); -- missing `(7 downto 0)` here
end entity;
architecture Behavioral of ShiftRegister is
signal Q : STD_LOGIC_VECTOR (7 downto 0) := "10011000";
begin
Output <= Q;
process (CLK)
begin
if (CLK'event and CLK = '1') then
Q(7 downto 0) <= Q(6 downto 0) & Q(7);
end if;
end process;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity TMP421_tb is
end TMP421_tb;
architecture behavior of TMP421_tb is
component TMP421
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
I2C_ReceiveSend_n_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(7 downto 0);
I2C_StartProcess_o : out std_logic;
I2C_Busy_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_Data_o : out std_logic_vector(7 downto 0);
I2C_Data_i : in std_logic_vector(7 downto 0);
I2C_Error_i : in std_logic;
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValueL_o : out std_logic_vector(15 downto 0);
SensorValueR_o : out std_logic_vector(15 downto 0)
);
end component;
component tmp421_model
port (
scl_i : in std_logic;
sda_io : inout std_logic;
local_temp_i : in std_logic_vector(15 downto 0);
remote_temp_i : in std_logic_vector(15 downto 0));
end component;
component ExtNames
port (
I2CFSM_Done : out std_logic
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Enable_i : std_logic;
signal CpuIntr_o : std_logic;
signal I2C_ReceiveSend_n_o : std_logic;
signal I2C_ReadCount_o : std_logic_vector(7 downto 0);
signal I2C_StartProcess_o : std_logic;
signal I2C_Busy_i : std_logic;
signal I2C_FIFOReadNext_o : std_logic;
signal I2C_FIFOWrite_o : std_logic;
signal I2C_Data_o : std_logic_vector(7 downto 0);
signal I2C_Data_i : std_logic_vector(7 downto 0);
signal I2C_Error_i : std_logic;
signal PeriodCounterPresetH_i : std_logic_vector(15 downto 0);
signal PeriodCounterPresetL_i : std_logic_vector(15 downto 0);
signal SensorValueL_o : std_logic_vector(15 downto 0);
signal SensorValueR_o : std_logic_vector(15 downto 0);
signal I2C_F100_400_n_o : std_logic;
signal I2C_Divider800_o : std_logic_vector(15 downto 0);
signal SensorValueL_real : real;
signal SensorValueR_real : real;
-- look into the ADT7310 app
-- alias I2CFSM_Done_i is << signal .adt7310_tb.DUT.I2CFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the I2CFSM_Done_i signal.
signal I2CFSM_Done_i : std_logic; -- directly from inside I2C_FSM
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- I2CFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal I2CFSM_Done_d : std_logic; -- sightly delayed
signal I2CFSM_Done_a : std_logic; -- I2CFSM_Done_i and I2CFSM_Done_d
-- SlowADT7410 component ports
signal I2C_SDA_i : std_logic;
signal I2C_SDA_o : std_logic;
signal I2C_SDA_s : std_logic;
signal I2C_SCL_o : std_logic;
signal LocalTemp_s : real := 23.7;
signal RemoteTemp_s : real := 23.7;
signal LocalTempBin_s : std_logic_vector(15 downto 0);
signal RemoteTempBin_s : std_logic_vector(15 downto 0);
-- I2C Master generics
constant I2C_FIFOAddressWidth_g : integer := 4;
constant I2C_ReadCountWidth_g : integer := 4;
constant I2C_DividerWidth_g : integer := 16;
-- I2C Master component ports
signal I2C_FIFOEmpty_s : std_logic := '0';
signal I2C_FIFOFull_s : std_logic := '0';
signal I2C_ErrBusColl_s : std_logic;
signal I2C_ErrCoreBusy_s : std_logic;
signal I2C_ErrCoreStopped_s : std_logic;
signal I2C_ErrDevNotPresent_s : std_logic;
signal I2C_ErrFIFOEmpty_s : std_logic;
signal I2C_ErrFIFOFull_s : std_logic;
signal I2C_ErrGotNAck_s : std_logic;
signal I2C_ErrReadCountZero_s : std_logic;
signal I2C_ScanEnable_s : std_logic := '0';
signal I2C_ScanClk_s : std_logic := '0';
signal I2C_ScanDataIn_s : std_logic := '0';
signal I2C_ScanDataOut_s : std_logic := '0';
-- 10MHz
constant ClkPeriode : time := 100 ns;
begin
DUT: TMP421
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Enable_i => Enable_i,
CpuIntr_o => CpuIntr_o,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n_o,
I2C_ReadCount_o => I2C_ReadCount_o,
I2C_StartProcess_o => I2C_StartProcess_o,
I2C_Busy_i => I2C_Busy_i,
I2C_FIFOReadNext_o => I2C_FIFOReadNext_o,
I2C_FIFOWrite_o => I2C_FIFOWrite_o,
I2C_Data_o => I2C_Data_o,
I2C_Data_i => I2C_Data_i,
I2C_Error_i => I2C_Error_i,
PeriodCounterPresetH_i => PeriodCounterPresetH_i,
PeriodCounterPresetL_i => PeriodCounterPresetL_i,
SensorValueL_o => SensorValueL_o,
SensorValueR_o => SensorValueR_o
);
LocalTempBin_s <= std_logic_vector(to_unsigned(integer(LocalTemp_s *256.0),16)) and x"FFF0";
RemoteTempBin_s <= std_logic_vector(to_unsigned(integer(RemoteTemp_s*256.0),16)) and x"FFF0";
SensorValueL_real <= real(to_integer(unsigned(SensorValueL_o and x"FFF0")))/256.0;
SensorValueR_real <= real(to_integer(unsigned(SensorValueR_o and x"FFF0")))/256.0;
ExtNames_1: ExtNames
port map (
I2CFSM_Done => I2CFSM_Done_i
);
I2CFSM_Done_d <= I2CFSM_Done_i after 1.0 ns;
I2CFSM_Done_a <= I2CFSM_Done_i and I2CFSM_Done_d;
i2c_master_1: i2c_master
generic map (
ReadCountWidth_g => I2C_ReadCountWidth_g,
FIFOAddressWidth_g => I2C_FIFOAddressWidth_g,
DividerWidth_g => I2C_DividerWidth_g)
port map (
Reset_i => "not"(Reset_n_i),
Clk_i => Clk_i,
Divider800_i => I2C_Divider800_o,
F100_400_n_i => I2C_F100_400_n_o,
StartProcess_i => I2C_StartProcess_o,
ReceiveSend_n_i => I2C_ReceiveSend_n_o,
Busy_o => I2C_Busy_i,
ReadCount_i => I2C_ReadCount_o(I2C_ReadCountWidth_g-1 downto 0),
FIFOReadNext_i => I2C_FIFOReadNext_o,
FIFOWrite_i => I2C_FIFOWrite_o,
FIFOEmpty_o => I2C_FIFOEmpty_s,
FIFOFull_o => I2C_FIFOFull_s,
Data_i => I2C_Data_o,
Data_o => I2C_Data_i,
ErrAck_i => '0',
ErrBusColl_o => I2C_ErrBusColl_s,
ErrFIFOFull_o => I2C_ErrFIFOFull_s,
ErrGotNAck_o => I2C_ErrGotNAck_s,
ErrCoreBusy_o => I2C_ErrCoreBusy_s,
ErrFIFOEmpty_o => I2C_ErrFIFOEmpty_s,
ErrCoreStopped_o => I2C_ErrCoreStopped_s,
ErrDevNotPresent_o => I2C_ErrDevNotPresent_s,
ErrReadCountZero_o => I2C_ErrReadCountZero_s,
SDA_i => I2C_SDA_i,
SDA_o => I2C_SDA_o,
SCL_o => I2C_SCL_o,
ScanEnable_i => I2C_ScanEnable_s,
ScanClk_i => I2C_ScanClk_s,
ScanDataIn_i => I2C_ScanDataIn_s,
ScanDataOut_o => I2C_ScanDataOut_s
);
I2C_Error_i <= I2C_ErrBusColl_s or I2C_ErrCoreBusy_s or I2C_ErrCoreStopped_s or I2C_ErrDevNotPresent_s or I2C_ErrFIFOEmpty_s or I2C_ErrFIFOFull_s or I2C_ErrGotNAck_s or I2C_ErrReadCountZero_s;
I2C_SDA_s <= 'H'; -- weak 1 -> simulate pull-up
I2C_SDA_s <= '0' when I2C_SDA_o = '0' else 'Z';
I2C_SDA_i <= to_X01(I2C_SDA_s) after 0.2 us;
tmp421_1: tmp421_model
port map (
scl_i => I2C_SCL_o,
sda_io => I2C_SDA_s,
local_temp_i => LocalTempBin_s,
remote_temp_i => RemoteTempBin_s);
-- constant value for reconfig signal
I2C_F100_400_n_o <= '0';
-- constant value for reconfig signal
I2C_Divider800_o <= "0000000000001100";
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
Enable_i <= '0';
PeriodCounterPresetH_i <= "0000000000000000";
PeriodCounterPresetL_i <= "0000011111010000";
-- Check constant values of dynamic signals coming out of the application modules
wait for 0.1*ClkPeriode;
wait for 2.2*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
LocalTemp_s <= 23.7; -- degree C
RemoteTemp_s <= 21.3; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
Enable_i <= '1';
for i in 1 to 5 loop
-- query local temperature
assert CpuIntr_o = '0' report "CpuIntr should be '0' during querying the local temperature" severity error;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after the first I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert I2CFSM_Done_d = '0' report "I2CFSM_done should be '0' directly after I2CFSM is done" severity error;
-- check SensorValueL_o
assert SensorValueL_o = LocalTempBin_s report "SensorValueL_o doesn't match LocalTempBin_s" severity error;
wait for 3*ClkPeriode;
-- query remote temperature
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
-- check SensorValueR_o
assert SensorValueR_o = RemoteTempBin_s report "SensorValueR_o doesn't match RemoteTempBin_s" severity error;
wait for 3*ClkPeriode;
-- new temperature
LocalTemp_s <= LocalTemp_s + 1.23;
RemoteTemp_s <= RemoteTemp_s + 1.23;
end loop;
wait for 1 ms;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:48:47 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_ethernetlite_0_0/system_axi_ethernetlite_0_0_sim_netlist.vhdl
-- Design : system_axi_ethernetlite_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_axi_interface is
port (
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
\reg_data_out_reg[31]\ : out STD_LOGIC;
reg_data_out0 : out STD_LOGIC;
\reg_data_out_reg[31]_0\ : out STD_LOGIC;
\reg_data_out_reg[3]\ : out STD_LOGIC;
\reg_data_out_reg[1]\ : out STD_LOGIC;
\reg_data_out_reg[1]_0\ : out STD_LOGIC;
\reg_data_out_reg[0]\ : out STD_LOGIC;
\reg_data_out_reg[5]\ : out STD_LOGIC;
\reg_data_out_reg[2]\ : out STD_LOGIC;
\reg_data_out_reg[3]_0\ : out STD_LOGIC;
\reg_data_out_reg[6]\ : out STD_LOGIC;
\reg_data_out_reg[6]_0\ : out STD_LOGIC;
\reg_data_out_reg[6]_1\ : out STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : out STD_LOGIC;
tx_intr_en0 : out STD_LOGIC;
\ping_pkt_lenth_reg[15]\ : out STD_LOGIC;
\reg_data_out_reg[3]_1\ : out STD_LOGIC_VECTOR ( 10 downto 0 );
\reg_data_out_reg[4]\ : out STD_LOGIC;
\reg_data_out_reg[15]\ : out STD_LOGIC;
\reg_data_out_reg[14]\ : out STD_LOGIC;
\reg_data_out_reg[13]\ : out STD_LOGIC;
\reg_data_out_reg[12]\ : out STD_LOGIC;
\reg_data_out_reg[11]\ : out STD_LOGIC;
\reg_data_out_reg[10]\ : out STD_LOGIC;
\reg_data_out_reg[9]\ : out STD_LOGIC;
\reg_data_out_reg[8]\ : out STD_LOGIC;
\reg_data_out_reg[7]\ : out STD_LOGIC;
\reg_data_out_reg[6]_2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\MDIO_GEN.mdio_wr_data_reg_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
rx_intr_en0 : out STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_44_out : out STD_LOGIC;
p_19_out : out STD_LOGIC;
\MDIO_GEN.mdio_reg_addr_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\MDIO_GEN.mdio_data_out_reg[11]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[15]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[3]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[11]_0\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
reg_access_reg : out STD_LOGIC;
\MDIO_GEN.mdio_en_i_reg\ : out STD_LOGIC;
gie_enable_reg : out STD_LOGIC;
\TX_PONG_REG_GEN.pong_soft_status_reg\ : out STD_LOGIC;
ping_soft_status_reg : out STD_LOGIC;
tx_intr_en_reg : out STD_LOGIC;
enb : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : out STD_LOGIC;
web : out STD_LOGIC_VECTOR ( 0 to 0 );
rx_intr_en_reg : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[15]_0\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[15]_1\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[14]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[13]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[12]\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[11]_1\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[11]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\MDIO_GEN.mdio_data_out_reg[11]_3\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\reg_data_out_reg[31]_1\ : in STD_LOGIC;
pong_soft_status : in STD_LOGIC;
p_21_in144_in : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\reg_data_out_reg[1]_1\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
\reg_data_out_reg[0]_0\ : in STD_LOGIC;
p_33_in182_in : in STD_LOGIC;
\reg_data_out_reg[2]_0\ : in STD_LOGIC;
p_17_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
ping_soft_status : in STD_LOGIC;
p_5_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\ping_pkt_lenth_reg[15]_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\ : in STD_LOGIC_VECTOR ( 14 downto 0 );
p_15_in : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_tx_status_reg : in STD_LOGIC;
p_9_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
pong_rx_status : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
reg_access : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
mdio_en_i : in STD_LOGIC;
mdio_rd_data_reg : in STD_LOGIC_VECTOR ( 4 downto 0 );
\MDIO_GEN.mdio_wr_data_reg_reg[15]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_axi_interface : entity is "axi_interface";
end system_axi_ethernetlite_0_0_axi_interface;
architecture STRUCTURE of system_axi_ethernetlite_0_0_axi_interface is
signal \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.bvalid_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.read_in_prog_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.read_req_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.rvalid_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.write_in_prog_i_1_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[11]\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[11]_0\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[15]\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[15]_1\ : STD_LOGIC;
signal \^rx_pong_reg_gen.pong_rx_status_reg\ : STD_LOGIC;
signal \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\ : STD_LOGIC;
signal \XEMAC_I/reg_access_i\ : STD_LOGIC;
signal arready_i1 : STD_LOGIC;
signal arready_i2 : STD_LOGIC;
signal bus2ip_rdce : STD_LOGIC;
signal gie_enable_i_2_n_0 : STD_LOGIC;
signal \^p_19_out\ : STD_LOGIC;
signal p_2_in : STD_LOGIC_VECTOR ( 12 downto 2 );
signal \^p_44_out\ : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal \ping_pkt_lenth[15]_i_3_n_0\ : STD_LOGIC;
signal \^ping_pkt_lenth_reg[15]\ : STD_LOGIC;
signal ping_rx_status_i_3_n_0 : STD_LOGIC;
signal read_in_prog : STD_LOGIC;
signal read_req : STD_LOGIC;
signal \^reg_data_out0\ : STD_LOGIC;
signal \reg_data_out[0]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[0]_i_3_n_0\ : STD_LOGIC;
signal \reg_data_out[0]_i_4_n_0\ : STD_LOGIC;
signal \reg_data_out[0]_i_6_n_0\ : STD_LOGIC;
signal \reg_data_out[15]_i_11_n_0\ : STD_LOGIC;
signal \reg_data_out[15]_i_7_n_0\ : STD_LOGIC;
signal \reg_data_out[15]_i_8_n_0\ : STD_LOGIC;
signal \reg_data_out[15]_i_9_n_0\ : STD_LOGIC;
signal \reg_data_out[1]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[1]_i_3_n_0\ : STD_LOGIC;
signal \reg_data_out[1]_i_4_n_0\ : STD_LOGIC;
signal \reg_data_out[2]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[31]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[31]_i_3_n_0\ : STD_LOGIC;
signal \reg_data_out[31]_i_4_n_0\ : STD_LOGIC;
signal \reg_data_out[31]_i_5_n_0\ : STD_LOGIC;
signal \reg_data_out[3]_i_2_n_0\ : STD_LOGIC;
signal \reg_data_out[3]_i_3_n_0\ : STD_LOGIC;
signal \reg_data_out[3]_i_4_n_0\ : STD_LOGIC;
signal \reg_data_out[5]_i_3_n_0\ : STD_LOGIC;
signal \^reg_data_out_reg[1]_0\ : STD_LOGIC;
signal \^reg_data_out_reg[31]_0\ : STD_LOGIC;
signal \^reg_data_out_reg[3]_0\ : STD_LOGIC;
signal \^reg_data_out_reg[3]_1\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^reg_data_out_reg[6]\ : STD_LOGIC;
signal \^reg_data_out_reg[6]_0\ : STD_LOGIC;
signal \^rx_intr_en0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal \^tx_intr_en0\ : STD_LOGIC;
signal xpm_memory_base_inst_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.awready_i_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.bvalid_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.read_req_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[10]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[10]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[10]_i_5\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[15]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[3]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[7]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_en_i_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of gie_enable_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ping_pkt_lenth[15]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ping_pkt_lenth[15]_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of ping_rx_status_i_3 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of ping_soft_status_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of reg_access_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \reg_data_out[0]_i_3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \reg_data_out[0]_i_6\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \reg_data_out[15]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \reg_data_out[15]_i_7\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \reg_data_out[15]_i_8\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_data_out[15]_i_9\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \reg_data_out[31]_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \reg_data_out[4]_i_3\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of rx_intr_en_i_1 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of tx_intr_en_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_2__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_2__2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of xpm_memory_base_inst_i_3 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_3__0\ : label is "soft_lutpair10";
begin
\MDIO_GEN.mdio_data_out_reg[11]\ <= \^mdio_gen.mdio_data_out_reg[11]\;
\MDIO_GEN.mdio_data_out_reg[11]_0\ <= \^mdio_gen.mdio_data_out_reg[11]_0\;
\MDIO_GEN.mdio_data_out_reg[15]\ <= \^mdio_gen.mdio_data_out_reg[15]\;
\MDIO_GEN.mdio_data_out_reg[15]_1\ <= \^mdio_gen.mdio_data_out_reg[15]_1\;
\RX_PONG_REG_GEN.pong_rx_status_reg\ <= \^rx_pong_reg_gen.pong_rx_status_reg\;
p_19_out <= \^p_19_out\;
p_44_out <= \^p_44_out\;
\ping_pkt_lenth_reg[15]\ <= \^ping_pkt_lenth_reg[15]\;
reg_data_out0 <= \^reg_data_out0\;
\reg_data_out_reg[1]_0\ <= \^reg_data_out_reg[1]_0\;
\reg_data_out_reg[31]_0\ <= \^reg_data_out_reg[31]_0\;
\reg_data_out_reg[3]_0\ <= \^reg_data_out_reg[3]_0\;
\reg_data_out_reg[3]_1\(10 downto 0) <= \^reg_data_out_reg[3]_1\(10 downto 0);
\reg_data_out_reg[6]\ <= \^reg_data_out_reg[6]\;
\reg_data_out_reg[6]_0\ <= \^reg_data_out_reg[6]_0\;
rx_intr_en0 <= \^rx_intr_en0\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_wready <= \^s_axi_wready\;
tx_intr_en0 <= \^tx_intr_en0\;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BBB7"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(2),
I1 => \XEMAC_I/reg_access_i\,
I2 => \^reg_data_out_reg[3]_1\(0),
I3 => \^reg_data_out_reg[3]_1\(1),
O => \^mdio_gen.mdio_data_out_reg[11]_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(0),
Q => s_axi_rdata(0),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(10),
Q => s_axi_rdata(10),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(11),
Q => s_axi_rdata(11),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(12),
Q => s_axi_rdata(12),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(13),
Q => s_axi_rdata(13),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(14),
Q => s_axi_rdata(14),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(15),
Q => s_axi_rdata(15),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(16),
Q => s_axi_rdata(16),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(17),
Q => s_axi_rdata(17),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(18),
Q => s_axi_rdata(18),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(19),
Q => s_axi_rdata(19),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(1),
Q => s_axi_rdata(1),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(20),
Q => s_axi_rdata(20),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(21),
Q => s_axi_rdata(21),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(22),
Q => s_axi_rdata(22),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(23),
Q => s_axi_rdata(23),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(24),
Q => s_axi_rdata(24),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(25),
Q => s_axi_rdata(25),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(26),
Q => s_axi_rdata(26),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(27),
Q => s_axi_rdata(27),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(28),
Q => s_axi_rdata(28),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(29),
Q => s_axi_rdata(29),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(2),
Q => s_axi_rdata(2),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(30),
Q => s_axi_rdata(30),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(31),
Q => s_axi_rdata(31),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(3),
Q => s_axi_rdata(3),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(4),
Q => s_axi_rdata(4),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(5),
Q => s_axi_rdata(5),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(6),
Q => s_axi_rdata(6),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(7),
Q => s_axi_rdata(7),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(8),
Q => s_axi_rdata(8),
R => SR(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => arready_i1,
D => D(9),
Q => s_axi_rdata(9),
R => SR(0)
);
\AXI4_LITE_IF_GEN.arready_i2_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => arready_i1,
Q => arready_i2,
R => SR(0)
);
\AXI4_LITE_IF_GEN.awready_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I2 => \^s_axi_wready\,
O => p_8_out
);
\AXI4_LITE_IF_GEN.awready_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_8_out,
Q => \^s_axi_wready\,
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(8),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(8),
O => p_2_in(10)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(9),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(9),
O => p_2_in(11)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I1 => s_axi_arvalid,
I2 => bus2ip_rdce,
I3 => s_axi_awvalid,
O => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(10),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(10),
O => p_2_in(12)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(0),
O => p_2_in(2)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(1),
O => p_2_in(3)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(2),
O => p_2_in(4)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(3),
O => p_2_in(5)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(4),
O => p_2_in(6)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(5),
O => p_2_in(7)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(6),
O => p_2_in(8)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_araddr(7),
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => s_axi_awaddr(7),
O => p_2_in(9)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(10),
Q => \^reg_data_out_reg[3]_1\(8),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(11),
Q => \^reg_data_out_reg[3]_1\(9),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(12),
Q => \^reg_data_out_reg[3]_1\(10),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(2),
Q => \^reg_data_out_reg[3]_1\(0),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(3),
Q => \^reg_data_out_reg[3]_1\(1),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(4),
Q => \^reg_data_out_reg[3]_1\(2),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(5),
Q => \^reg_data_out_reg[3]_1\(3),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(6),
Q => \^reg_data_out_reg[3]_1\(4),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(7),
Q => \^reg_data_out_reg[3]_1\(5),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(8),
Q => \^reg_data_out_reg[3]_1\(6),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i[12]_i_1_n_0\,
D => p_2_in(9),
Q => \^reg_data_out_reg[3]_1\(7),
R => SR(0)
);
\AXI4_LITE_IF_GEN.bus2ip_rdce_i_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_rdce,
Q => arready_i1,
R => SR(0)
);
\AXI4_LITE_IF_GEN.bvalid_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
O => \AXI4_LITE_IF_GEN.bvalid_i_1_n_0\
);
\AXI4_LITE_IF_GEN.bvalid_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.bvalid_i_1_n_0\,
Q => \^s_axi_bvalid\,
R => SR(0)
);
\AXI4_LITE_IF_GEN.read_in_prog_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => bus2ip_rdce,
I1 => s_axi_arvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => read_in_prog,
O => \AXI4_LITE_IF_GEN.read_in_prog_i_1_n_0\
);
\AXI4_LITE_IF_GEN.read_in_prog_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD5D5D5"
)
port map (
I0 => s_axi_aresetn,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => \^s_axi_bvalid\,
I4 => s_axi_bready,
O => read_in_prog
);
\AXI4_LITE_IF_GEN.read_in_prog_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.read_in_prog_i_1_n_0\,
Q => bus2ip_rdce,
R => '0'
);
\AXI4_LITE_IF_GEN.read_req_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7530"
)
port map (
I0 => s_axi_rready,
I1 => arready_i1,
I2 => s_axi_arvalid,
I3 => read_req,
O => \AXI4_LITE_IF_GEN.read_req_i_1_n_0\
);
\AXI4_LITE_IF_GEN.read_req_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.read_req_i_1_n_0\,
Q => read_req,
R => SR(0)
);
\AXI4_LITE_IF_GEN.rvalid_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00F08080"
)
port map (
I0 => arready_i1,
I1 => read_req,
I2 => s_axi_aresetn,
I3 => s_axi_rready,
I4 => \^s_axi_rlast\,
O => \AXI4_LITE_IF_GEN.rvalid_i_1_n_0\
);
\AXI4_LITE_IF_GEN.rvalid_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.rvalid_i_1_n_0\,
Q => \^s_axi_rlast\,
R => '0'
);
\AXI4_LITE_IF_GEN.write_in_prog_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAAEAA"
)
port map (
I0 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I1 => s_axi_awvalid,
I2 => bus2ip_rdce,
I3 => s_axi_wvalid,
I4 => s_axi_arvalid,
I5 => read_in_prog,
O => \AXI4_LITE_IF_GEN.write_in_prog_i_1_n_0\
);
\AXI4_LITE_IF_GEN.write_in_prog_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.write_in_prog_i_1_n_0\,
Q => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
R => '0'
);
\MDIO_GEN.mdio_data_out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[11]_0\,
I1 => bus2ip_rdce,
I2 => s_axi_aresetn,
O => \MDIO_GEN.mdio_data_out_reg[11]_2\(0)
);
\MDIO_GEN.mdio_data_out[10]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FBFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \XEMAC_I/reg_access_i\,
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \^reg_data_out_reg[3]_1\(1),
I4 => bus2ip_rdce,
O => \^mdio_gen.mdio_data_out_reg[15]_1\
);
\MDIO_GEN.mdio_data_out[10]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00200000"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(0),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \XEMAC_I/reg_access_i\,
O => \^mdio_gen.mdio_data_out_reg[11]\
);
\MDIO_GEN.mdio_data_out[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"44F4"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I1 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(0),
I2 => mdio_rd_data_reg(0),
I3 => \^mdio_gen.mdio_data_out_reg[15]\,
O => \MDIO_GEN.mdio_data_out_reg[11]_1\
);
\MDIO_GEN.mdio_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"44F4"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I1 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(1),
I2 => mdio_rd_data_reg(1),
I3 => \^mdio_gen.mdio_data_out_reg[15]\,
O => \MDIO_GEN.mdio_data_out_reg[12]\
);
\MDIO_GEN.mdio_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"44F4"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I1 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(2),
I2 => mdio_rd_data_reg(2),
I3 => \^mdio_gen.mdio_data_out_reg[15]\,
O => \MDIO_GEN.mdio_data_out_reg[13]\
);
\MDIO_GEN.mdio_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"44F4"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I1 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(3),
I2 => mdio_rd_data_reg(3),
I3 => \^mdio_gen.mdio_data_out_reg[15]\,
O => \MDIO_GEN.mdio_data_out_reg[14]\
);
\MDIO_GEN.mdio_data_out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F0F"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[11]_0\,
I1 => bus2ip_rdce,
I2 => s_axi_aresetn,
I3 => \^mdio_gen.mdio_data_out_reg[11]\,
O => \MDIO_GEN.mdio_data_out_reg[11]_3\
);
\MDIO_GEN.mdio_data_out[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^mdio_gen.mdio_data_out_reg[15]\,
I1 => mdio_rd_data_reg(4),
I2 => \^mdio_gen.mdio_data_out_reg[15]_1\,
I3 => \MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(4),
O => \MDIO_GEN.mdio_data_out_reg[15]_0\
);
\MDIO_GEN.mdio_data_out[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \XEMAC_I/reg_access_i\,
O => \MDIO_GEN.mdio_data_out_reg[3]\
);
\MDIO_GEN.mdio_data_out[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \XEMAC_I/reg_access_i\,
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \^reg_data_out_reg[3]_1\(1),
I4 => bus2ip_rdce,
O => \^mdio_gen.mdio_data_out_reg[15]\
);
\MDIO_GEN.mdio_en_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^p_19_out\,
I2 => mdio_en_i,
O => \MDIO_GEN.mdio_en_i_reg\
);
\MDIO_GEN.mdio_reg_addr[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => s_axi_wvalid,
I1 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => \^reg_data_out_reg[3]_1\(2),
I5 => \XEMAC_I/reg_access_i\,
O => \MDIO_GEN.mdio_reg_addr_reg[4]\(0)
);
\MDIO_GEN.mdio_reg_addr[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(5),
I1 => \^reg_data_out_reg[3]_1\(3),
I2 => \^reg_data_out_reg[3]_1\(8),
I3 => \^reg_data_out_reg[3]_1\(4),
I4 => \^reg_data_out_reg[3]_1\(6),
I5 => \^reg_data_out_reg[3]_1\(7),
O => \XEMAC_I/reg_access_i\
);
\MDIO_GEN.mdio_req_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => s_axi_wvalid,
I1 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => \^reg_data_out_reg[3]_1\(2),
I5 => \XEMAC_I/reg_access_i\,
O => \^p_19_out\
);
\MDIO_GEN.mdio_wr_data_reg[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(1),
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \XEMAC_I/reg_access_i\,
I3 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I4 => s_axi_wvalid,
I5 => \^reg_data_out_reg[3]_1\(0),
O => \MDIO_GEN.mdio_wr_data_reg_reg[15]\(0)
);
\RX_PONG_REG_GEN.pong_rx_status_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \XEMAC_I/reg_access_i\,
I1 => \^reg_data_out_reg[3]_1\(9),
I2 => \^reg_data_out_reg[3]_1\(10),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => \^reg_data_out_reg[3]_1\(1),
I5 => \^reg_data_out_reg[3]_1\(2),
O => \^rx_pong_reg_gen.pong_rx_status_reg\
);
\TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(10),
I1 => \^reg_data_out_reg[3]_1\(9),
O => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\
);
\TX_PONG_REG_GEN.pong_soft_status_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^p_44_out\,
I2 => pong_soft_status,
O => \TX_PONG_REG_GEN.pong_soft_status_reg\
);
\TX_PONG_REG_GEN.pong_tx_status_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \^p_44_out\
);
gie_enable_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFBF0080"
)
port map (
I0 => s_axi_wdata(1),
I1 => s_axi_wvalid,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I3 => gie_enable_i_2_n_0,
I4 => p_5_in(0),
O => gie_enable_reg
);
gie_enable_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFDFFFFFF"
)
port map (
I0 => \XEMAC_I/reg_access_i\,
I1 => \^reg_data_out_reg[3]_1\(9),
I2 => \^reg_data_out_reg[3]_1\(10),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \^reg_data_out_reg[3]_1\(1),
I5 => \^reg_data_out_reg[3]_1\(0),
O => gie_enable_i_2_n_0
);
\ping_pkt_lenth[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000080000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \ping_pkt_lenth[15]_i_3_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => E(0)
);
\ping_pkt_lenth[15]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I1 => s_axi_wvalid,
O => \^ping_pkt_lenth_reg[15]\
);
\ping_pkt_lenth[15]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
O => \ping_pkt_lenth[15]_i_3_n_0\
);
ping_rx_status_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => ping_rx_status_i_3_n_0,
I5 => \XEMAC_I/reg_access_i\,
O => \^rx_intr_en0\
);
ping_rx_status_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
O => ping_rx_status_i_3_n_0
);
ping_soft_status_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^tx_intr_en0\,
I2 => ping_soft_status,
O => ping_soft_status_reg
);
ping_tx_status_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => \^ping_pkt_lenth_reg[15]\,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \ping_pkt_lenth[15]_i_3_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \^tx_intr_en0\
);
reg_access_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \XEMAC_I/reg_access_i\,
I1 => bus2ip_rdce,
I2 => reg_access,
O => reg_access_reg
);
\reg_data_out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2E2EEE2"
)
port map (
I0 => \reg_data_out_reg[0]_0\,
I1 => \^reg_data_out0\,
I2 => \reg_data_out[0]_i_2_n_0\,
I3 => Q(0),
I4 => \^reg_data_out_reg[1]_0\,
I5 => \reg_data_out[0]_i_3_n_0\,
O => \reg_data_out_reg[0]\
);
\reg_data_out[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEEEFFFFFEEEFEEE"
)
port map (
I0 => \reg_data_out[0]_i_4_n_0\,
I1 => ping_tx_status_reg,
I2 => \reg_data_out[15]_i_11_n_0\,
I3 => p_9_in(0),
I4 => \^reg_data_out_reg[6]\,
I5 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(0),
O => \reg_data_out[0]_i_2_n_0\
);
\reg_data_out[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => gie_enable_i_2_n_0,
I1 => bus2ip_rdce,
I2 => s_axi_aresetn,
O => \reg_data_out[0]_i_3_n_0\
);
\reg_data_out[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => pong_rx_status,
I1 => \XEMAC_I/reg_access_i\,
I2 => \^reg_data_out_reg[3]_1\(9),
I3 => \^reg_data_out_reg[3]_1\(10),
I4 => \reg_data_out[0]_i_6_n_0\,
I5 => bus2ip_rdce,
O => \reg_data_out[0]_i_4_n_0\
);
\reg_data_out[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
O => \reg_data_out[0]_i_6_n_0\
);
\reg_data_out[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(9),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(8),
O => \reg_data_out_reg[10]\
);
\reg_data_out[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(10),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(9),
O => \reg_data_out_reg[11]\
);
\reg_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(11),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(10),
O => \reg_data_out_reg[12]\
);
\reg_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(12),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(11),
O => \reg_data_out_reg[13]\
);
\reg_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(13),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(12),
O => \reg_data_out_reg[14]\
);
\reg_data_out[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFBBB0000"
)
port map (
I0 => \^reg_data_out_reg[31]_0\,
I1 => s_axi_aresetn,
I2 => \^reg_data_out_reg[6]_0\,
I3 => \^reg_data_out_reg[6]\,
I4 => \reg_data_out[15]_i_7_n_0\,
I5 => \reg_data_out[15]_i_8_n_0\,
O => \reg_data_out_reg[6]_1\
);
\reg_data_out[15]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF7FFFFFFFFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \ping_pkt_lenth[15]_i_3_n_0\,
I4 => \XEMAC_I/reg_access_i\,
I5 => bus2ip_rdce,
O => \^reg_data_out_reg[3]_0\
);
\reg_data_out[15]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => ping_rx_status_i_3_n_0,
I5 => \XEMAC_I/reg_access_i\,
O => \reg_data_out[15]_i_11_n_0\
);
\reg_data_out[15]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A8AA"
)
port map (
I0 => bus2ip_rdce,
I1 => \XEMAC_I/reg_access_i\,
I2 => \reg_data_out[15]_i_9_n_0\,
I3 => \^reg_data_out_reg[3]_1\(0),
O => \^reg_data_out0\
);
\reg_data_out[15]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(14),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(13),
O => \reg_data_out_reg[15]\
);
\reg_data_out[15]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(0),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(2),
I4 => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \^reg_data_out_reg[31]_0\
);
\reg_data_out[15]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDFFFFFFFFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \ping_pkt_lenth[15]_i_3_n_0\,
I4 => \XEMAC_I/reg_access_i\,
I5 => bus2ip_rdce,
O => \^reg_data_out_reg[6]_0\
);
\reg_data_out[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFDFFFFFFFFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(0),
I1 => \^reg_data_out_reg[3]_1\(1),
I2 => \^reg_data_out_reg[3]_1\(2),
I3 => \TX_PONG_REG_GEN.pong_pkt_lenth[15]_i_2_n_0\,
I4 => \XEMAC_I/reg_access_i\,
I5 => bus2ip_rdce,
O => \^reg_data_out_reg[6]\
);
\reg_data_out[15]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
O => \reg_data_out[15]_i_7_n_0\
);
\reg_data_out[15]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => \^reg_data_out_reg[3]_0\,
I1 => \^reg_data_out_reg[31]_0\,
I2 => \reg_data_out[3]_i_3_n_0\,
I3 => \reg_data_out[15]_i_11_n_0\,
I4 => s_axi_aresetn,
O => \reg_data_out[15]_i_8_n_0\
);
\reg_data_out[15]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(2),
I1 => \^reg_data_out_reg[3]_1\(1),
O => \reg_data_out[15]_i_9_n_0\
);
\reg_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2E2EEE2"
)
port map (
I0 => \reg_data_out_reg[1]_1\,
I1 => \^reg_data_out0\,
I2 => \reg_data_out[1]_i_2_n_0\,
I3 => Q(1),
I4 => \^reg_data_out_reg[1]_0\,
I5 => \reg_data_out[1]_i_3_n_0\,
O => \reg_data_out_reg[1]\
);
\reg_data_out[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF22F2"
)
port map (
I0 => \ping_pkt_lenth_reg[15]_0\(0),
I1 => \^reg_data_out_reg[6]_0\,
I2 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(1),
I3 => \^reg_data_out_reg[6]\,
I4 => \reg_data_out[1]_i_4_n_0\,
O => \reg_data_out[1]_i_2_n_0\
);
\reg_data_out[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => \reg_data_out[15]_i_11_n_0\,
I2 => \reg_data_out[3]_i_3_n_0\,
O => \reg_data_out[1]_i_3_n_0\
);
\reg_data_out[1]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F444"
)
port map (
I0 => \^reg_data_out_reg[3]_0\,
I1 => p_17_in(0),
I2 => \^reg_data_out_reg[31]_0\,
I3 => p_15_in(0),
O => \reg_data_out[1]_i_4_n_0\
);
\reg_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEEE22E2"
)
port map (
I0 => \reg_data_out_reg[2]_0\,
I1 => \^reg_data_out0\,
I2 => Q(2),
I3 => \^reg_data_out_reg[1]_0\,
I4 => \reg_data_out[2]_i_2_n_0\,
I5 => \reg_data_out[15]_i_8_n_0\,
O => \reg_data_out_reg[2]\
);
\reg_data_out[2]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(2),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(1),
O => \reg_data_out[2]_i_2_n_0\
);
\reg_data_out[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE2E2E2"
)
port map (
I0 => \reg_data_out_reg[31]_1\,
I1 => \^reg_data_out0\,
I2 => \reg_data_out[31]_i_2_n_0\,
I3 => pong_soft_status,
I4 => \^reg_data_out_reg[31]_0\,
I5 => \reg_data_out[31]_i_3_n_0\,
O => \reg_data_out_reg[31]\
);
\reg_data_out[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"44444444F4444444"
)
port map (
I0 => \^reg_data_out_reg[3]_0\,
I1 => ping_soft_status,
I2 => p_5_in(0),
I3 => \^rx_pong_reg_gen.pong_rx_status_reg\,
I4 => bus2ip_rdce,
I5 => gie_enable_i_2_n_0,
O => \reg_data_out[31]_i_2_n_0\
);
\reg_data_out[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF8FFFFFFFFFF"
)
port map (
I0 => gie_enable_i_2_n_0,
I1 => \reg_data_out[15]_i_7_n_0\,
I2 => \reg_data_out[31]_i_4_n_0\,
I3 => \^reg_data_out_reg[6]\,
I4 => \reg_data_out[15]_i_11_n_0\,
I5 => s_axi_aresetn,
O => \reg_data_out[31]_i_3_n_0\
);
\reg_data_out[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800000000000"
)
port map (
I0 => bus2ip_rdce,
I1 => \^reg_data_out_reg[3]_1\(2),
I2 => \^reg_data_out_reg[3]_1\(1),
I3 => \^reg_data_out_reg[3]_1\(0),
I4 => \reg_data_out[31]_i_5_n_0\,
I5 => \XEMAC_I/reg_access_i\,
O => \reg_data_out[31]_i_4_n_0\
);
\reg_data_out[31]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
O => \reg_data_out[31]_i_5_n_0\
);
\reg_data_out[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000E200"
)
port map (
I0 => p_21_in144_in,
I1 => \^reg_data_out0\,
I2 => \reg_data_out[3]_i_2_n_0\,
I3 => s_axi_aresetn,
I4 => \^reg_data_out_reg[31]_0\,
I5 => \reg_data_out[3]_i_3_n_0\,
O => \reg_data_out_reg[3]\
);
\reg_data_out[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF44F4"
)
port map (
I0 => \^reg_data_out_reg[1]_0\,
I1 => Q(3),
I2 => p_17_in(1),
I3 => \^reg_data_out_reg[3]_0\,
I4 => \reg_data_out[3]_i_4_n_0\,
O => \reg_data_out[3]_i_2_n_0\
);
\reg_data_out[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0080000200000000"
)
port map (
I0 => \XEMAC_I/reg_access_i\,
I1 => \^reg_data_out_reg[3]_1\(9),
I2 => \^reg_data_out_reg[3]_1\(10),
I3 => \reg_data_out[15]_i_9_n_0\,
I4 => \^reg_data_out_reg[3]_1\(0),
I5 => bus2ip_rdce,
O => \reg_data_out[3]_i_3_n_0\
);
\reg_data_out[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB83030FF3030"
)
port map (
I0 => \reg_data_out[15]_i_11_n_0\,
I1 => \^reg_data_out_reg[6]_0\,
I2 => \ping_pkt_lenth_reg[15]_0\(2),
I3 => \^reg_data_out_reg[6]\,
I4 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(3),
I5 => p_9_in(1),
O => \reg_data_out[3]_i_4_n_0\
);
\reg_data_out[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \reg_data_out[15]_i_11_n_0\,
I1 => s_axi_aresetn,
I2 => \^reg_data_out_reg[31]_0\,
I3 => \reg_data_out[3]_i_3_n_0\,
O => \reg_data_out_reg[4]\
);
\reg_data_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEEE22E2"
)
port map (
I0 => p_33_in182_in,
I1 => \^reg_data_out0\,
I2 => Q(4),
I3 => \^reg_data_out_reg[1]_0\,
I4 => \reg_data_out[5]_i_3_n_0\,
I5 => \reg_data_out[15]_i_8_n_0\,
O => \reg_data_out_reg[5]\
);
\reg_data_out[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF7FFFFFFFF"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \^reg_data_out_reg[6]_0\,
I2 => \reg_data_out[15]_i_11_n_0\,
I3 => \reg_data_out[3]_i_3_n_0\,
I4 => \^reg_data_out_reg[31]_0\,
I5 => \^reg_data_out_reg[3]_0\,
O => \^reg_data_out_reg[1]_0\
);
\reg_data_out[5]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(4),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(3),
O => \reg_data_out[5]_i_3_n_0\
);
\reg_data_out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(5),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(4),
O => \reg_data_out_reg[6]_2\
);
\reg_data_out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(6),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(5),
O => \reg_data_out_reg[7]\
);
\reg_data_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(7),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(6),
O => \reg_data_out_reg[8]\
);
\reg_data_out[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \^reg_data_out_reg[6]\,
I1 => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(8),
I2 => \^reg_data_out_reg[6]_0\,
I3 => \ping_pkt_lenth_reg[15]_0\(7),
O => \reg_data_out_reg[9]\
);
rx_intr_en_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^rx_intr_en0\,
I2 => p_9_in(1),
O => rx_intr_en_reg
);
s_axi_arready_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => arready_i1,
I1 => arready_i2,
O => s_axi_arready
);
tx_intr_en_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^tx_intr_en0\,
I2 => p_17_in(1),
O => tx_intr_en_reg
);
\xpm_memory_base_inst_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"10FF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
I2 => xpm_memory_base_inst_i_5_n_0,
I3 => s_axi_aresetn,
O => enb
);
\xpm_memory_base_inst_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"80FF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
I2 => xpm_memory_base_inst_i_5_n_0,
I3 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg\
);
\xpm_memory_base_inst_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(10),
I1 => \^reg_data_out_reg[3]_1\(9),
I2 => xpm_memory_base_inst_i_5_n_0,
I3 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg_0\
);
xpm_memory_base_inst_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"40FF"
)
port map (
I0 => \^reg_data_out_reg[3]_1\(9),
I1 => \^reg_data_out_reg[3]_1\(10),
I2 => xpm_memory_base_inst_i_5_n_0,
I3 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg_1\
);
\xpm_memory_base_inst_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_wvalid,
I1 => \AXI4_LITE_IF_GEN.write_in_prog_reg_n_0\,
I2 => s_axi_aresetn,
O => web(0)
);
xpm_memory_base_inst_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"EAAAAAAAAAAAAAAA"
)
port map (
I0 => bus2ip_rdce,
I1 => s_axi_wstrb(3),
I2 => s_axi_wstrb(2),
I3 => s_axi_wstrb(0),
I4 => s_axi_wstrb(1),
I5 => \^ping_pkt_lenth_reg[15]\,
O => xpm_memory_base_inst_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cdc_sync is
port (
scndry_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cdc_sync : entity is "cdc_sync";
end system_axi_ethernetlite_0_0_cdc_sync;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cdc_sync is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => SR(0),
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d3,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cdc_sync_0 is
port (
scndry_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cdc_sync_0 : entity is "cdc_sync";
end system_axi_ethernetlite_0_0_cdc_sync_0;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cdc_sync_0 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => SR(0),
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d3,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cdc_sync_12 is
port (
scndry_out : out STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cdc_sync_12 : entity is "cdc_sync";
end system_axi_ethernetlite_0_0_cdc_sync_12;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cdc_sync_12 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => SS(0),
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d3,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cdc_sync_7 is
port (
scndry_out : out STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cdc_sync_7 : entity is "cdc_sync";
end system_axi_ethernetlite_0_0_cdc_sync_7;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cdc_sync_7 is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => phy_tx_clk,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized0\ is
port (
scndry_out : out STD_LOGIC;
prmry_in : in STD_LOGIC;
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized0\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized0\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized0\ is
signal s_level_out_d1_cdc_to : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized1\ is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
prmry_vect_in : in STD_LOGIC_VECTOR ( 3 downto 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized1\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized1\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized1\ is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_vect_in(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_vect_in(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_vect_in(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => prmry_vect_in(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized2\ is
port (
scndry_out : out STD_LOGIC;
prmry_in : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized2\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized2\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized2\ is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => prmry_in,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized3\ is
port (
fifo_tx_en_reg : out STD_LOGIC;
scndry_out : in STD_LOGIC;
tx_en_i : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized3\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized3\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized3\ is
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal tx_en_i_tx_clk : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => tx_en_i,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => tx_en_i_tx_clk,
R => '0'
);
fifo_tx_en_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => tx_en_i_tx_clk,
I1 => scndry_out,
O => fifo_tx_en_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_cdc_sync__parameterized4\ is
port (
scndry_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_cdc_sync__parameterized4\ : entity is "cdc_sync";
end \system_axi_ethernetlite_0_0_cdc_sync__parameterized4\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_cdc_sync__parameterized4\ is
signal s_level_out_d1_cdc_to : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => s_axi_aresetn,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => scndry_out,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cntr5bit is
port (
ifgp1_zero : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\thisState_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\thisState_reg[0]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cntr5bit : entity is "cntr5bit";
end system_axi_ethernetlite_0_0_cntr5bit;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cntr5bit is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \count_reg__0\ : STD_LOGIC_VECTOR ( 0 to 2 );
signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 2 );
signal zero_i_i_1_n_0 : STD_LOGIC;
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\count[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFEAAAAAAAB"
)
port map (
I0 => \thisState_reg[0]\,
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \count_reg__0\(1),
I4 => \count_reg__0\(2),
I5 => \count_reg__0\(0),
O => p_0_in(4)
);
\count[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE01FE01FE010000"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \count_reg__0\(2),
I3 => \count_reg__0\(1),
I4 => \thisState_reg[1]\(1),
I5 => \thisState_reg[1]\(0),
O => p_0_in(3)
);
\count[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1E1E100"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg__0\(2),
I3 => \thisState_reg[1]\(1),
I4 => \thisState_reg[1]\(0),
O => p_0_in(2)
);
\count_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_0_in(4),
Q => \count_reg__0\(0),
S => s_axi_aresetn
);
\count_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_0_in(3),
Q => \count_reg__0\(1),
S => s_axi_aresetn
);
\count_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_0_in(2),
Q => \count_reg__0\(2),
S => s_axi_aresetn
);
\count_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^q\(1),
S => s_axi_aresetn
);
\count_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^q\(0),
S => s_axi_aresetn
);
zero_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg__0\(2),
I3 => \count_reg__0\(1),
I4 => \count_reg__0\(0),
O => zero_i_i_1_n_0
);
zero_i_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => zero_i_i_1_n_0,
Q => ifgp1_zero,
S => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_cntr5bit_11 is
port (
ifgp2_zero : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\thisState_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\thisState_reg[0]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_cntr5bit_11 : entity is "cntr5bit";
end system_axi_ethernetlite_0_0_cntr5bit_11;
architecture STRUCTURE of system_axi_ethernetlite_0_0_cntr5bit_11 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \count[0]_i_2__0_n_0\ : STD_LOGIC;
signal \count_reg__0\ : STD_LOGIC_VECTOR ( 0 to 2 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \zero_i_i_1__0_n_0\ : STD_LOGIC;
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\count[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555400000001"
)
port map (
I0 => \thisState_reg[0]\,
I1 => \count_reg__0\(1),
I2 => \count_reg__0\(2),
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \count_reg__0\(0),
O => \count[0]_i_2__0_n_0\
);
\count[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF11111111F"
)
port map (
I0 => \thisState_reg[1]\(1),
I1 => \thisState_reg[1]\(0),
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \count_reg__0\(2),
I5 => \count_reg__0\(1),
O => \p_0_in__0\(3)
);
\count[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1E1E100"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg__0\(2),
I3 => \thisState_reg[1]\(1),
I4 => \thisState_reg[1]\(0),
O => \p_0_in__0\(2)
);
\count_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \count[0]_i_2__0_n_0\,
Q => \count_reg__0\(0),
S => s_axi_aresetn
);
\count_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \p_0_in__0\(3),
Q => \count_reg__0\(1),
S => s_axi_aresetn
);
\count_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \p_0_in__0\(2),
Q => \count_reg__0\(2),
S => s_axi_aresetn
);
\count_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^q\(1),
S => s_axi_aresetn
);
\count_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^q\(0),
S => s_axi_aresetn
);
\zero_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg__0\(2),
I3 => \count_reg__0\(1),
I4 => \count_reg__0\(0),
O => \zero_i_i_1__0_n_0\
);
zero_i_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \zero_i_i_1__0_n_0\,
Q => ifgp2_zero,
S => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_crcgenrx is
port (
Q : out STD_LOGIC_VECTOR ( 9 downto 0 );
crcokdelay : out STD_LOGIC;
D_0 : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 6 downto 0 );
\gpr1.dout_i_reg[5]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpr1.dout_i_reg[2]\ : in STD_LOGIC;
crcokr1 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
rxCrcEn : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_crcgenrx : entity is "crcgenrx";
end system_axi_ethernetlite_0_0_crcgenrx;
architecture STRUCTURE of system_axi_ethernetlite_0_0_crcgenrx is
signal \^q\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \crc_local_reg_n_0_[27]\ : STD_LOGIC;
signal crcokdelay_i_10_n_0 : STD_LOGIC;
signal crcokdelay_i_3_n_0 : STD_LOGIC;
signal crcokdelay_i_4_n_0 : STD_LOGIC;
signal crcokdelay_i_5_n_0 : STD_LOGIC;
signal crcokdelay_i_6_n_0 : STD_LOGIC;
signal crcokdelay_i_7_n_0 : STD_LOGIC;
signal crcokdelay_i_8_n_0 : STD_LOGIC;
signal crcokdelay_i_9_n_0 : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal p_17_in : STD_LOGIC;
signal p_19_in : STD_LOGIC;
signal p_20_in : STD_LOGIC;
signal p_21_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_24_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_26_in : STD_LOGIC;
signal p_27_in : STD_LOGIC;
signal p_28_in : STD_LOGIC;
signal p_29_in : STD_LOGIC;
signal p_30_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal parallel_crc : STD_LOGIC_VECTOR ( 29 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \crc_local[15]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \crc_local[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \crc_local[17]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \crc_local[18]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \crc_local[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \crc_local[22]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \crc_local[23]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \crc_local[27]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \crc_local[28]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \crc_local[29]_i_1\ : label is "soft_lutpair19";
begin
Q(9 downto 0) <= \^q\(9 downto 0);
\crc_local[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => p_11_in,
I1 => \^q\(8),
I2 => \gpr1.dout_i_reg[5]\(1),
I3 => \^q\(7),
I4 => \gpr1.dout_i_reg[5]\(2),
I5 => D(0),
O => parallel_crc(12)
);
\crc_local[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => p_12_in,
I1 => \^q\(8),
I2 => \gpr1.dout_i_reg[5]\(1),
I3 => \^q\(7),
I4 => \gpr1.dout_i_reg[5]\(2),
I5 => \gpr1.dout_i_reg[2]\,
O => parallel_crc(13)
);
\crc_local[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_13_in,
I1 => \gpr1.dout_i_reg[5]\(1),
I2 => \^q\(8),
I3 => \gpr1.dout_i_reg[5]\(0),
I4 => \^q\(9),
O => parallel_crc(14)
);
\crc_local[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_19_in,
I1 => \^q\(9),
I2 => \gpr1.dout_i_reg[5]\(0),
O => parallel_crc(15)
);
\crc_local[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_20_in,
I1 => \^q\(6),
I2 => \gpr1.dout_i_reg[5]\(3),
O => parallel_crc(16)
);
\crc_local[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_21_in,
I1 => \^q\(7),
I2 => \gpr1.dout_i_reg[5]\(2),
O => parallel_crc(17)
);
\crc_local[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_22_in,
I1 => \^q\(8),
I2 => \gpr1.dout_i_reg[5]\(1),
O => parallel_crc(18)
);
\crc_local[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_23_in,
I1 => \^q\(9),
I2 => \gpr1.dout_i_reg[5]\(0),
O => parallel_crc(19)
);
\crc_local[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \^q\(7),
I1 => \gpr1.dout_i_reg[5]\(2),
I2 => \^q\(6),
I3 => \gpr1.dout_i_reg[5]\(3),
O => parallel_crc(1)
);
\crc_local[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_24_in,
I1 => \^q\(6),
I2 => \gpr1.dout_i_reg[5]\(3),
O => parallel_crc(22)
);
\crc_local[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_14_in,
I1 => \gpr1.dout_i_reg[5]\(3),
I2 => \^q\(6),
I3 => \gpr1.dout_i_reg[5]\(2),
I4 => \^q\(7),
O => parallel_crc(23)
);
\crc_local[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_15_in,
I1 => \gpr1.dout_i_reg[5]\(2),
I2 => \^q\(7),
I3 => \gpr1.dout_i_reg[5]\(1),
I4 => \^q\(8),
O => parallel_crc(24)
);
\crc_local[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_16_in,
I1 => \gpr1.dout_i_reg[5]\(1),
I2 => \^q\(8),
I3 => \gpr1.dout_i_reg[5]\(0),
I4 => \^q\(9),
O => parallel_crc(25)
);
\crc_local[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_17_in,
I1 => \gpr1.dout_i_reg[5]\(3),
I2 => \^q\(6),
I3 => \gpr1.dout_i_reg[5]\(0),
I4 => \^q\(9),
O => parallel_crc(26)
);
\crc_local[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_25_in,
I1 => \^q\(7),
I2 => \gpr1.dout_i_reg[5]\(2),
O => parallel_crc(27)
);
\crc_local[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_26_in,
I1 => \^q\(8),
I2 => \gpr1.dout_i_reg[5]\(1),
O => parallel_crc(28)
);
\crc_local[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_27_in,
I1 => \^q\(9),
I2 => \gpr1.dout_i_reg[5]\(0),
O => parallel_crc(29)
);
\crc_local[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(6),
I1 => \gpr1.dout_i_reg[5]\(3),
I2 => \gpr1.dout_i_reg[5]\(2),
I3 => \^q\(7),
I4 => \gpr1.dout_i_reg[5]\(1),
I5 => \^q\(8),
O => parallel_crc(2)
);
\crc_local[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(9),
I1 => \gpr1.dout_i_reg[5]\(0),
I2 => \gpr1.dout_i_reg[5]\(2),
I3 => \^q\(7),
I4 => \gpr1.dout_i_reg[5]\(1),
I5 => \^q\(8),
O => parallel_crc(3)
);
\crc_local[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_5_in,
I1 => \gpr1.dout_i_reg[5]\(2),
I2 => \^q\(7),
I3 => \gpr1.dout_i_reg[5]\(1),
I4 => \^q\(8),
O => parallel_crc(6)
);
\crc_local[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => p_8_in,
I1 => \gpr1.dout_i_reg[5]\(2),
I2 => \^q\(7),
I3 => \gpr1.dout_i_reg[5]\(1),
I4 => \^q\(8),
O => parallel_crc(9)
);
\crc_local_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(0),
Q => \^q\(0),
S => SS(0)
);
\crc_local_reg[10]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(5),
Q => p_13_in,
S => SS(0)
);
\crc_local_reg[11]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(6),
Q => p_19_in,
S => SS(0)
);
\crc_local_reg[12]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(12),
Q => p_20_in,
S => SS(0)
);
\crc_local_reg[13]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(13),
Q => p_21_in,
S => SS(0)
);
\crc_local_reg[14]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(14),
Q => p_22_in,
S => SS(0)
);
\crc_local_reg[15]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(15),
Q => p_23_in,
S => SS(0)
);
\crc_local_reg[16]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(16),
Q => p_28_in,
S => SS(0)
);
\crc_local_reg[17]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(17),
Q => p_29_in,
S => SS(0)
);
\crc_local_reg[18]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(18),
Q => p_24_in,
S => SS(0)
);
\crc_local_reg[19]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(19),
Q => p_14_in,
S => SS(0)
);
\crc_local_reg[1]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(1),
Q => \^q\(1),
S => SS(0)
);
\crc_local_reg[20]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_28_in,
Q => p_15_in,
S => SS(0)
);
\crc_local_reg[21]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_29_in,
Q => p_16_in,
S => SS(0)
);
\crc_local_reg[22]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(22),
Q => p_17_in,
S => SS(0)
);
\crc_local_reg[23]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(23),
Q => p_25_in,
S => SS(0)
);
\crc_local_reg[24]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(24),
Q => p_26_in,
S => SS(0)
);
\crc_local_reg[25]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(25),
Q => p_27_in,
S => SS(0)
);
\crc_local_reg[26]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(26),
Q => p_30_in,
S => SS(0)
);
\crc_local_reg[27]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(27),
Q => \crc_local_reg_n_0_[27]\,
S => SS(0)
);
\crc_local_reg[28]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(28),
Q => \^q\(6),
S => SS(0)
);
\crc_local_reg[29]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(29),
Q => \^q\(7),
S => SS(0)
);
\crc_local_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(2),
Q => p_5_in,
S => SS(0)
);
\crc_local_reg[30]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_30_in,
Q => \^q\(8),
S => SS(0)
);
\crc_local_reg[31]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => \crc_local_reg_n_0_[27]\,
Q => \^q\(9),
S => SS(0)
);
\crc_local_reg[3]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(3),
Q => \^q\(2),
S => SS(0)
);
\crc_local_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(1),
Q => \^q\(3),
S => SS(0)
);
\crc_local_reg[5]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(2),
Q => p_8_in,
S => SS(0)
);
\crc_local_reg[6]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(6),
Q => \^q\(4),
S => SS(0)
);
\crc_local_reg[7]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(3),
Q => \^q\(5),
S => SS(0)
);
\crc_local_reg[8]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => D(4),
Q => p_11_in,
S => SS(0)
);
\crc_local_reg[9]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => E(0),
D => parallel_crc(9),
Q => p_12_in,
S => SS(0)
);
crcokdelay_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFB0000FFFFFFFF"
)
port map (
I0 => crcokdelay_i_3_n_0,
I1 => crcokdelay_i_4_n_0,
I2 => crcokdelay_i_5_n_0,
I3 => crcokdelay_i_6_n_0,
I4 => crcokr1,
I5 => s_axi_aresetn,
O => crcokdelay
);
crcokdelay_i_10: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => p_20_in,
I1 => p_23_in,
I2 => p_19_in,
I3 => p_30_in,
O => crcokdelay_i_10_n_0
);
crcokdelay_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0004FFFF00040004"
)
port map (
I0 => crcokdelay_i_3_n_0,
I1 => crcokdelay_i_4_n_0,
I2 => crcokdelay_i_5_n_0,
I3 => crcokdelay_i_6_n_0,
I4 => rxCrcEn,
I5 => crcokr1,
O => D_0
);
crcokdelay_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_17_in,
I1 => p_25_in,
I2 => \^q\(7),
I3 => \crc_local_reg_n_0_[27]\,
I4 => crcokdelay_i_7_n_0,
O => crcokdelay_i_3_n_0
);
crcokdelay_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => p_14_in,
I1 => \^q\(8),
I2 => p_26_in,
I3 => p_11_in,
I4 => crcokdelay_i_8_n_0,
O => crcokdelay_i_4_n_0
);
crcokdelay_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_29_in,
I1 => p_15_in,
I2 => p_28_in,
I3 => p_12_in,
I4 => crcokdelay_i_9_n_0,
O => crcokdelay_i_5_n_0
);
crcokdelay_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF7FF"
)
port map (
I0 => p_24_in,
I1 => \^q\(1),
I2 => \^q\(6),
I3 => p_13_in,
I4 => crcokdelay_i_10_n_0,
O => crcokdelay_i_6_n_0
);
crcokdelay_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => p_8_in,
I1 => p_27_in,
I2 => \^q\(4),
I3 => p_16_in,
O => crcokdelay_i_7_n_0
);
crcokdelay_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
I2 => p_5_in,
I3 => \^q\(5),
O => crcokdelay_i_8_n_0
);
crcokdelay_i_9: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => \^q\(0),
I1 => p_22_in,
I2 => \^q\(9),
I3 => p_21_in,
O => crcokdelay_i_9_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_crcnibshiftreg is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
txCrcEn_reg : in STD_LOGIC;
\emac_tx_wr_data_d1_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_crcnibshiftreg : entity is "crcnibshiftreg";
end system_axi_ethernetlite_0_0_crcnibshiftreg;
architecture STRUCTURE of system_axi_ethernetlite_0_0_crcnibshiftreg is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \nibData[12]_i_1_n_0\ : STD_LOGIC;
signal \nibData[13]_i_1_n_0\ : STD_LOGIC;
signal \nibData[14]_i_1_n_0\ : STD_LOGIC;
signal \nibData[15]_i_1_n_0\ : STD_LOGIC;
signal \nibData[16]_i_1_n_0\ : STD_LOGIC;
signal \nibData[17]_i_1_n_0\ : STD_LOGIC;
signal \nibData[18]_i_1_n_0\ : STD_LOGIC;
signal \nibData[19]_i_1_n_0\ : STD_LOGIC;
signal \nibData[20]_i_1_n_0\ : STD_LOGIC;
signal \nibData[21]_i_1_n_0\ : STD_LOGIC;
signal \nibData[22]_i_1_n_0\ : STD_LOGIC;
signal \nibData[23]_i_1_n_0\ : STD_LOGIC;
signal \nibData[24]_i_1_n_0\ : STD_LOGIC;
signal \nibData[25]_i_1_n_0\ : STD_LOGIC;
signal \nibData[26]_i_1_n_0\ : STD_LOGIC;
signal \nibData[26]_i_2_n_0\ : STD_LOGIC;
signal \nibData[27]_i_1_n_0\ : STD_LOGIC;
signal \nibData[27]_i_2_n_0\ : STD_LOGIC;
signal \nibData[28]_i_1_n_0\ : STD_LOGIC;
signal \nibData[28]_i_2_n_0\ : STD_LOGIC;
signal \nibData[29]_i_1_n_0\ : STD_LOGIC;
signal \nibData[29]_i_2_n_0\ : STD_LOGIC;
signal \nibData[2]_i_1_n_0\ : STD_LOGIC;
signal \nibData[30]_i_1_n_0\ : STD_LOGIC;
signal \nibData[31]_i_3_n_0\ : STD_LOGIC;
signal \nibData[3]_i_1_n_0\ : STD_LOGIC;
signal \nibData[4]_i_1_n_0\ : STD_LOGIC;
signal \nibData[5]_i_1_n_0\ : STD_LOGIC;
signal \nibData[6]_i_1_n_0\ : STD_LOGIC;
signal \nibData[7]_i_1_n_0\ : STD_LOGIC;
signal \nibData[8]_i_1_n_0\ : STD_LOGIC;
signal \nibData[9]_i_1_n_0\ : STD_LOGIC;
signal \nibData_reg_n_0_[10]\ : STD_LOGIC;
signal \nibData_reg_n_0_[11]\ : STD_LOGIC;
signal \nibData_reg_n_0_[12]\ : STD_LOGIC;
signal \nibData_reg_n_0_[13]\ : STD_LOGIC;
signal \nibData_reg_n_0_[14]\ : STD_LOGIC;
signal \nibData_reg_n_0_[15]\ : STD_LOGIC;
signal \nibData_reg_n_0_[16]\ : STD_LOGIC;
signal \nibData_reg_n_0_[17]\ : STD_LOGIC;
signal \nibData_reg_n_0_[18]\ : STD_LOGIC;
signal \nibData_reg_n_0_[19]\ : STD_LOGIC;
signal \nibData_reg_n_0_[20]\ : STD_LOGIC;
signal \nibData_reg_n_0_[21]\ : STD_LOGIC;
signal \nibData_reg_n_0_[22]\ : STD_LOGIC;
signal \nibData_reg_n_0_[23]\ : STD_LOGIC;
signal \nibData_reg_n_0_[24]\ : STD_LOGIC;
signal \nibData_reg_n_0_[25]\ : STD_LOGIC;
signal \nibData_reg_n_0_[26]\ : STD_LOGIC;
signal \nibData_reg_n_0_[27]\ : STD_LOGIC;
signal \nibData_reg_n_0_[28]\ : STD_LOGIC;
signal \nibData_reg_n_0_[29]\ : STD_LOGIC;
signal \nibData_reg_n_0_[30]\ : STD_LOGIC;
signal \nibData_reg_n_0_[31]\ : STD_LOGIC;
signal \nibData_reg_n_0_[4]\ : STD_LOGIC;
signal \nibData_reg_n_0_[5]\ : STD_LOGIC;
signal \nibData_reg_n_0_[6]\ : STD_LOGIC;
signal \nibData_reg_n_0_[7]\ : STD_LOGIC;
signal \nibData_reg_n_0_[8]\ : STD_LOGIC;
signal \nibData_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \nibData[12]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \nibData[13]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \nibData[14]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \nibData[15]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \nibData[19]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \nibData[24]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \nibData[26]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \nibData[27]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \nibData[28]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \nibData[29]_i_2\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \nibData[2]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \nibData[30]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \nibData[31]_i_3\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \nibData[3]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \nibData[4]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \nibData[9]_i_1\ : label is "soft_lutpair49";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\nibData[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[16]\,
I1 => \^q\(0),
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => txCrcEn_reg,
O => \nibData[12]_i_1_n_0\
);
\nibData[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[17]\,
I1 => \^q\(1),
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => txCrcEn_reg,
O => \nibData[13]_i_1_n_0\
);
\nibData[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[18]\,
I1 => \^q\(2),
I2 => \emac_tx_wr_data_d1_reg[0]\(2),
I3 => txCrcEn_reg,
O => \nibData[14]_i_1_n_0\
);
\nibData[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[19]\,
I1 => \^q\(3),
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => txCrcEn_reg,
O => \nibData[15]_i_1_n_0\
);
\nibData[16]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[20]\,
I1 => \^q\(0),
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => txCrcEn_reg,
O => \nibData[16]_i_1_n_0\
);
\nibData[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A66A6AA66AA6A66A"
)
port map (
I0 => \nibData_reg_n_0_[21]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => \^q\(1),
I4 => \emac_tx_wr_data_d1_reg[0]\(0),
I5 => \^q\(0),
O => \nibData[17]_i_1_n_0\
);
\nibData[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[22]\,
I1 => \emac_tx_wr_data_d1_reg[0]\(2),
I2 => \^q\(2),
I3 => \nibData[27]_i_2_n_0\,
I4 => txCrcEn_reg,
O => \nibData[18]_i_1_n_0\
);
\nibData[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[23]\,
I1 => \nibData[26]_i_2_n_0\,
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => \^q\(1),
I4 => txCrcEn_reg,
O => \nibData[19]_i_1_n_0\
);
\nibData[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A66A6AA6"
)
port map (
I0 => \nibData_reg_n_0_[24]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => \^q\(0),
I4 => \nibData[26]_i_2_n_0\,
O => \nibData[20]_i_1_n_0\
);
\nibData[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[25]\,
I1 => \nibData[27]_i_2_n_0\,
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => \^q\(3),
I4 => txCrcEn_reg,
O => \nibData[21]_i_1_n_0\
);
\nibData[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96696996AAAAAAAA"
)
port map (
I0 => \nibData_reg_n_0_[26]\,
I1 => \emac_tx_wr_data_d1_reg[0]\(2),
I2 => \^q\(2),
I3 => \emac_tx_wr_data_d1_reg[0]\(1),
I4 => \^q\(1),
I5 => txCrcEn_reg,
O => \nibData[22]_i_1_n_0\
);
\nibData[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A66A6AA6"
)
port map (
I0 => \nibData_reg_n_0_[27]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => \^q\(0),
I4 => \nibData[26]_i_2_n_0\,
O => \nibData[23]_i_1_n_0\
);
\nibData[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[28]\,
I1 => \nibData[27]_i_2_n_0\,
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => \^q\(3),
I4 => txCrcEn_reg,
O => \nibData[24]_i_1_n_0\
);
\nibData[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96696996AAAAAAAA"
)
port map (
I0 => \nibData_reg_n_0_[29]\,
I1 => \emac_tx_wr_data_d1_reg[0]\(2),
I2 => \^q\(2),
I3 => \emac_tx_wr_data_d1_reg[0]\(1),
I4 => \^q\(1),
I5 => txCrcEn_reg,
O => \nibData[25]_i_1_n_0\
);
\nibData[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A66A6AA6"
)
port map (
I0 => \nibData_reg_n_0_[30]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => \^q\(0),
I4 => \nibData[26]_i_2_n_0\,
O => \nibData[26]_i_1_n_0\
);
\nibData[26]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \emac_tx_wr_data_d1_reg[0]\(3),
I1 => \^q\(3),
I2 => \emac_tx_wr_data_d1_reg[0]\(2),
I3 => \^q\(2),
O => \nibData[26]_i_2_n_0\
);
\nibData[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"9669AAAA"
)
port map (
I0 => \nibData_reg_n_0_[31]\,
I1 => \nibData[27]_i_2_n_0\,
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => \^q\(3),
I4 => txCrcEn_reg,
O => \nibData[27]_i_1_n_0\
);
\nibData[27]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \emac_tx_wr_data_d1_reg[0]\(1),
I1 => \^q\(1),
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => \^q\(0),
O => \nibData[27]_i_2_n_0\
);
\nibData[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699600000000"
)
port map (
I0 => \nibData[28]_i_2_n_0\,
I1 => \emac_tx_wr_data_d1_reg[0]\(0),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \emac_tx_wr_data_d1_reg[0]\(2),
I5 => txCrcEn_reg,
O => \nibData[28]_i_1_n_0\
);
\nibData[28]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \emac_tx_wr_data_d1_reg[0]\(1),
O => \nibData[28]_i_2_n_0\
);
\nibData[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9669699600000000"
)
port map (
I0 => \^q\(1),
I1 => \emac_tx_wr_data_d1_reg[0]\(1),
I2 => \nibData[29]_i_2_n_0\,
I3 => \emac_tx_wr_data_d1_reg[0]\(2),
I4 => \^q\(2),
I5 => txCrcEn_reg,
O => \nibData[29]_i_1_n_0\
);
\nibData[29]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(3),
I1 => \emac_tx_wr_data_d1_reg[0]\(3),
O => \nibData[29]_i_2_n_0\
);
\nibData[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[6]\,
I1 => \^q\(0),
I2 => \emac_tx_wr_data_d1_reg[0]\(0),
I3 => txCrcEn_reg,
O => \nibData[2]_i_1_n_0\
);
\nibData[30]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"82282882"
)
port map (
I0 => txCrcEn_reg,
I1 => \^q\(2),
I2 => \emac_tx_wr_data_d1_reg[0]\(2),
I3 => \^q\(3),
I4 => \emac_tx_wr_data_d1_reg[0]\(3),
O => \nibData[30]_i_1_n_0\
);
\nibData[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \emac_tx_wr_data_d1_reg[0]\(3),
I1 => \^q\(3),
I2 => txCrcEn_reg,
O => \nibData[31]_i_3_n_0\
);
\nibData[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[7]\,
I1 => \^q\(1),
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => txCrcEn_reg,
O => \nibData[3]_i_1_n_0\
);
\nibData[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[8]\,
I1 => \^q\(2),
I2 => \emac_tx_wr_data_d1_reg[0]\(2),
I3 => txCrcEn_reg,
O => \nibData[4]_i_1_n_0\
);
\nibData[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A66A6AA66AA6A66A"
)
port map (
I0 => \nibData_reg_n_0_[9]\,
I1 => txCrcEn_reg,
I2 => \^q\(0),
I3 => \emac_tx_wr_data_d1_reg[0]\(0),
I4 => \emac_tx_wr_data_d1_reg[0]\(3),
I5 => \^q\(3),
O => \nibData[5]_i_1_n_0\
);
\nibData[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A66A6AA66AA6A66A"
)
port map (
I0 => \nibData_reg_n_0_[10]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(1),
I3 => \^q\(1),
I4 => \emac_tx_wr_data_d1_reg[0]\(0),
I5 => \^q\(0),
O => \nibData[6]_i_1_n_0\
);
\nibData[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"96696996AAAAAAAA"
)
port map (
I0 => \nibData_reg_n_0_[11]\,
I1 => \emac_tx_wr_data_d1_reg[0]\(2),
I2 => \^q\(2),
I3 => \emac_tx_wr_data_d1_reg[0]\(1),
I4 => \^q\(1),
I5 => txCrcEn_reg,
O => \nibData[7]_i_1_n_0\
);
\nibData[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A66A6AA66AA6A66A"
)
port map (
I0 => \nibData_reg_n_0_[12]\,
I1 => txCrcEn_reg,
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => \^q\(3),
I4 => \emac_tx_wr_data_d1_reg[0]\(2),
I5 => \^q\(2),
O => \nibData[8]_i_1_n_0\
);
\nibData[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"69AA"
)
port map (
I0 => \nibData_reg_n_0_[13]\,
I1 => \^q\(3),
I2 => \emac_tx_wr_data_d1_reg[0]\(3),
I3 => txCrcEn_reg,
O => \nibData[9]_i_1_n_0\
);
\nibData_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData_reg_n_0_[4]\,
Q => \^q\(0),
R => SR(0)
);
\nibData_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData_reg_n_0_[14]\,
Q => \nibData_reg_n_0_[10]\,
R => SR(0)
);
\nibData_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData_reg_n_0_[15]\,
Q => \nibData_reg_n_0_[11]\,
R => SR(0)
);
\nibData_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[12]_i_1_n_0\,
Q => \nibData_reg_n_0_[12]\,
R => SR(0)
);
\nibData_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[13]_i_1_n_0\,
Q => \nibData_reg_n_0_[13]\,
R => SR(0)
);
\nibData_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[14]_i_1_n_0\,
Q => \nibData_reg_n_0_[14]\,
R => SR(0)
);
\nibData_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[15]_i_1_n_0\,
Q => \nibData_reg_n_0_[15]\,
R => SR(0)
);
\nibData_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[16]_i_1_n_0\,
Q => \nibData_reg_n_0_[16]\,
R => SR(0)
);
\nibData_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[17]_i_1_n_0\,
Q => \nibData_reg_n_0_[17]\,
R => SR(0)
);
\nibData_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[18]_i_1_n_0\,
Q => \nibData_reg_n_0_[18]\,
R => SR(0)
);
\nibData_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[19]_i_1_n_0\,
Q => \nibData_reg_n_0_[19]\,
R => SR(0)
);
\nibData_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData_reg_n_0_[5]\,
Q => \^q\(1),
R => SR(0)
);
\nibData_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[20]_i_1_n_0\,
Q => \nibData_reg_n_0_[20]\,
R => SR(0)
);
\nibData_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[21]_i_1_n_0\,
Q => \nibData_reg_n_0_[21]\,
R => SR(0)
);
\nibData_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[22]_i_1_n_0\,
Q => \nibData_reg_n_0_[22]\,
R => SR(0)
);
\nibData_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[23]_i_1_n_0\,
Q => \nibData_reg_n_0_[23]\,
R => SR(0)
);
\nibData_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[24]_i_1_n_0\,
Q => \nibData_reg_n_0_[24]\,
R => SR(0)
);
\nibData_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[25]_i_1_n_0\,
Q => \nibData_reg_n_0_[25]\,
R => SR(0)
);
\nibData_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[26]_i_1_n_0\,
Q => \nibData_reg_n_0_[26]\,
R => SR(0)
);
\nibData_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[27]_i_1_n_0\,
Q => \nibData_reg_n_0_[27]\,
R => SR(0)
);
\nibData_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[28]_i_1_n_0\,
Q => \nibData_reg_n_0_[28]\,
R => SR(0)
);
\nibData_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[29]_i_1_n_0\,
Q => \nibData_reg_n_0_[29]\,
R => SR(0)
);
\nibData_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[2]_i_1_n_0\,
Q => \^q\(2),
R => SR(0)
);
\nibData_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[30]_i_1_n_0\,
Q => \nibData_reg_n_0_[30]\,
R => SR(0)
);
\nibData_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[31]_i_3_n_0\,
Q => \nibData_reg_n_0_[31]\,
R => SR(0)
);
\nibData_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[3]_i_1_n_0\,
Q => \^q\(3),
R => SR(0)
);
\nibData_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[4]_i_1_n_0\,
Q => \nibData_reg_n_0_[4]\,
R => SR(0)
);
\nibData_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[5]_i_1_n_0\,
Q => \nibData_reg_n_0_[5]\,
R => SR(0)
);
\nibData_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[6]_i_1_n_0\,
Q => \nibData_reg_n_0_[6]\,
R => SR(0)
);
\nibData_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[7]_i_1_n_0\,
Q => \nibData_reg_n_0_[7]\,
R => SR(0)
);
\nibData_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[8]_i_1_n_0\,
Q => \nibData_reg_n_0_[8]\,
R => SR(0)
);
\nibData_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \nibData[9]_i_1_n_0\,
Q => \nibData_reg_n_0_[9]\,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_defer_state is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\count_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\count_reg[3]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\count_reg[0]\ : out STD_LOGIC;
D13_out : out STD_LOGIC;
phy_crs_d2 : in STD_LOGIC;
tx_en_i : in STD_LOGIC;
ifgp1_zero : in STD_LOGIC;
ifgp2_zero : in STD_LOGIC;
tx_clk_reg_d3 : in STD_LOGIC;
tx_clk_reg_d2 : in STD_LOGIC;
\count_reg[3]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\count_reg[3]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
ldLngthCntr : in STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : in STD_LOGIC;
enblPreamble : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_defer_state : entity is "defer_state";
end system_axi_ethernetlite_0_0_defer_state;
architecture STRUCTURE of system_axi_ethernetlite_0_0_defer_state is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \thisState[0]_i_1_n_0\ : STD_LOGIC;
signal \thisState[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \count[0]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \count[0]_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \count[3]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \count[3]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \count[4]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \count[4]_i_1__0\ : label is "soft_lutpair55";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
STATE8A_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"80FF8080"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => ldLngthCntr,
I3 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\,
I4 => enblPreamble,
O => D13_out
);
\count[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000004000400FFFF"
)
port map (
I0 => ifgp2_zero,
I1 => ifgp1_zero,
I2 => tx_clk_reg_d3,
I3 => tx_clk_reg_d2,
I4 => \^q\(1),
I5 => \^q\(0),
O => E(0)
);
\count[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"001010FF"
)
port map (
I0 => ifgp1_zero,
I1 => tx_clk_reg_d3,
I2 => tx_clk_reg_d2,
I3 => \^q\(1),
I4 => \^q\(0),
O => \count_reg[4]\(0)
);
\count[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \count_reg[0]\
);
\count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E00E"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg[3]_0\(0),
I3 => \count_reg[3]_0\(1),
O => D(1)
);
\count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E00E"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \count_reg[3]_1\(0),
I3 => \count_reg[3]_1\(1),
O => \count_reg[3]\(1)
);
\count[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => \count_reg[3]_0\(0),
I1 => \^q\(1),
I2 => \^q\(0),
O => D(0)
);
\count[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"54"
)
port map (
I0 => \count_reg[3]_1\(0),
I1 => \^q\(1),
I2 => \^q\(0),
O => \count_reg[3]\(0)
);
\thisState[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3737040400CC00CF"
)
port map (
I0 => phy_crs_d2,
I1 => \^q\(0),
I2 => tx_en_i,
I3 => ifgp1_zero,
I4 => ifgp2_zero,
I5 => \^q\(1),
O => \thisState[0]_i_1_n_0\
);
\thisState[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3704CCCC"
)
port map (
I0 => phy_crs_d2,
I1 => \^q\(1),
I2 => tx_en_i,
I3 => ifgp1_zero,
I4 => \^q\(0),
O => \thisState[1]_i_1_n_0\
);
\thisState_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \thisState[0]_i_1_n_0\,
Q => \^q\(0),
R => s_axi_aresetn
);
\thisState_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \thisState[1]_i_1_n_0\,
Q => \^q\(1),
R => s_axi_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_ld_arith_reg is
port (
STATE13A : out STD_LOGIC_VECTOR ( 0 to 0 );
\txNibbleCnt_pad_reg[11]\ : out STD_LOGIC;
D21_out : out STD_LOGIC;
STATE13A_0 : out STD_LOGIC;
enblData : in STD_LOGIC;
S : in STD_LOGIC;
txComboNibbleCntRst : in STD_LOGIC;
CE : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\tx_packet_length_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
checkBusFifoFull : in STD_LOGIC;
\out\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_ld_arith_reg : entity is "ld_arith_reg";
end system_axi_ethernetlite_0_0_ld_arith_reg;
architecture STRUCTURE of system_axi_ethernetlite_0_0_ld_arith_reg is
signal \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[10].MUXCY_i1_i_3_n_0\ : STD_LOGIC;
signal \PERBIT_GEN[10].MUXCY_i1_i_4_n_0\ : STD_LOGIC;
signal \PERBIT_GEN[10].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[3].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[4].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[5].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[6].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[7].MUXCY_i1_i_2_n_0\ : STD_LOGIC;
signal \PERBIT_GEN[7].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[8].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[9].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \^state13a\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^state13a_0\ : STD_LOGIC;
signal STATE13A_i_2_n_0 : STD_LOGIC;
signal STATE13A_i_3_n_0 : STD_LOGIC;
signal cry : STD_LOGIC_VECTOR ( 11 downto 1 );
signal currentTxNibbleCnt : STD_LOGIC_VECTOR ( 0 to 10 );
signal gen_cry_kill_n_0 : STD_LOGIC;
signal gen_cry_kill_n_1 : STD_LOGIC;
signal gen_cry_kill_n_10 : STD_LOGIC;
signal gen_cry_kill_n_2 : STD_LOGIC;
signal gen_cry_kill_n_3 : STD_LOGIC;
signal gen_cry_kill_n_4 : STD_LOGIC;
signal gen_cry_kill_n_5 : STD_LOGIC;
signal gen_cry_kill_n_6 : STD_LOGIC;
signal gen_cry_kill_n_7 : STD_LOGIC;
signal gen_cry_kill_n_8 : STD_LOGIC;
signal gen_cry_kill_n_9 : STD_LOGIC;
signal \^txnibblecnt_pad_reg[11]\ : STD_LOGIC;
signal xorcy_out_0 : STD_LOGIC;
signal xorcy_out_1 : STD_LOGIC;
signal xorcy_out_10 : STD_LOGIC;
signal xorcy_out_11 : STD_LOGIC;
signal xorcy_out_2 : STD_LOGIC;
signal xorcy_out_3 : STD_LOGIC;
signal xorcy_out_4 : STD_LOGIC;
signal xorcy_out_5 : STD_LOGIC;
signal xorcy_out_6 : STD_LOGIC;
signal xorcy_out_7 : STD_LOGIC;
signal xorcy_out_8 : STD_LOGIC;
signal xorcy_out_9 : STD_LOGIC;
signal \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute box_type : string;
attribute box_type of \PERBIT_GEN[0].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[10].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[10].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[10].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[10].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[11].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[11].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[11].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[11].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[11].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[1].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[1].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[1].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[2].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[2].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[2].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[3].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[3].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[3].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[3].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[3].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[4].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[4].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[4].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[4].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[5].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[5].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[5].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[5].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[6].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[6].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[6].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[6].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[7].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[7].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[7].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[7].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[7].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[7].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[8].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[8].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[8].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[9].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[9].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[9].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[9].MULT_AND_i1\ : label is "PRIMITIVE";
begin
STATE13A(0) <= \^state13a\(0);
STATE13A_0 <= \^state13a_0\;
\txNibbleCnt_pad_reg[11]\ <= \^txnibblecnt_pad_reg[11]\;
\PERBIT_GEN[0].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_11,
Q => currentTxNibbleCnt(0),
R => txComboNibbleCntRst
);
\PERBIT_GEN[0].XORCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(10),
I1 => currentTxNibbleCnt(0),
I2 => enblData,
O => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[10].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_1,
Q => currentTxNibbleCnt(10),
R => txComboNibbleCntRst
);
\PERBIT_GEN[10].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(10),
I1 => enblData,
O => gen_cry_kill_n_1
);
\PERBIT_GEN[10].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F44"
)
port map (
I0 => \^txnibblecnt_pad_reg[11]\,
I1 => \tx_packet_length_reg[15]\(0),
I2 => currentTxNibbleCnt(10),
I3 => enblData,
O => \PERBIT_GEN[10].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[10].MUXCY_i1_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \PERBIT_GEN[10].MUXCY_i1_i_3_n_0\,
I1 => \tx_packet_length_reg[15]\(9),
I2 => \tx_packet_length_reg[15]\(11),
I3 => \tx_packet_length_reg[15]\(15),
I4 => \tx_packet_length_reg[15]\(7),
I5 => \PERBIT_GEN[10].MUXCY_i1_i_4_n_0\,
O => \^txnibblecnt_pad_reg[11]\
);
\PERBIT_GEN[10].MUXCY_i1_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \tx_packet_length_reg[15]\(8),
I1 => \tx_packet_length_reg[15]\(13),
I2 => \tx_packet_length_reg[15]\(14),
I3 => \tx_packet_length_reg[15]\(10),
I4 => \tx_packet_length_reg[15]\(6),
I5 => \tx_packet_length_reg[15]\(12),
O => \PERBIT_GEN[10].MUXCY_i1_i_3_n_0\
);
\PERBIT_GEN[10].MUXCY_i1_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000000000000000"
)
port map (
I0 => \tx_packet_length_reg[15]\(0),
I1 => \tx_packet_length_reg[15]\(1),
I2 => \tx_packet_length_reg[15]\(4),
I3 => \tx_packet_length_reg[15]\(3),
I4 => \tx_packet_length_reg[15]\(5),
I5 => \tx_packet_length_reg[15]\(2),
O => \PERBIT_GEN[10].MUXCY_i1_i_4_n_0\
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_0,
Q => \^state13a\(0),
R => txComboNibbleCntRst
);
\PERBIT_GEN[11].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^state13a\(0),
I1 => enblData,
O => gen_cry_kill_n_0
);
\PERBIT_GEN[11].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 0) => cry(4 downto 1),
CYINIT => enblData,
DI(3) => gen_cry_kill_n_3,
DI(2) => gen_cry_kill_n_2,
DI(1) => gen_cry_kill_n_1,
DI(0) => gen_cry_kill_n_0,
O(3) => xorcy_out_3,
O(2) => xorcy_out_2,
O(1) => xorcy_out_1,
O(0) => xorcy_out_0,
S(3) => \PERBIT_GEN[8].Q_I_GEN_SUB.q_i_ns_reg\,
S(2) => \PERBIT_GEN[9].Q_I_GEN_SUB.q_i_ns_reg\,
S(1) => \PERBIT_GEN[10].Q_I_GEN_SUB.q_i_ns_reg\,
S(0) => S
);
\PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_10,
Q => currentTxNibbleCnt(1),
R => txComboNibbleCntRst
);
\PERBIT_GEN[1].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(1),
I1 => enblData,
O => gen_cry_kill_n_10
);
\PERBIT_GEN[1].MUXCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(9),
I1 => currentTxNibbleCnt(1),
I2 => enblData,
O => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_9,
Q => currentTxNibbleCnt(2),
R => txComboNibbleCntRst
);
\PERBIT_GEN[2].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(2),
I1 => enblData,
O => gen_cry_kill_n_9
);
\PERBIT_GEN[2].MUXCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(8),
I1 => currentTxNibbleCnt(2),
I2 => enblData,
O => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_8,
Q => currentTxNibbleCnt(3),
R => txComboNibbleCntRst
);
\PERBIT_GEN[3].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(3),
I1 => enblData,
O => gen_cry_kill_n_8
);
\PERBIT_GEN[3].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => cry(8),
CO(3) => \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_CO_UNCONNECTED\(3),
CO(2 downto 0) => cry(11 downto 9),
CYINIT => '0',
DI(3) => \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_DI_UNCONNECTED\(3),
DI(2) => gen_cry_kill_n_10,
DI(1) => gen_cry_kill_n_9,
DI(0) => gen_cry_kill_n_8,
O(3) => xorcy_out_11,
O(2) => xorcy_out_10,
O(1) => xorcy_out_9,
O(0) => xorcy_out_8,
S(3) => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\,
S(2) => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\,
S(1) => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\,
S(0) => \PERBIT_GEN[3].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[3].MUXCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(7),
I1 => currentTxNibbleCnt(3),
I2 => enblData,
O => \PERBIT_GEN[3].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[4].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_7,
Q => currentTxNibbleCnt(4),
R => txComboNibbleCntRst
);
\PERBIT_GEN[4].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(4),
I1 => enblData,
O => gen_cry_kill_n_7
);
\PERBIT_GEN[4].MUXCY_i1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"3A"
)
port map (
I0 => \tx_packet_length_reg[15]\(6),
I1 => currentTxNibbleCnt(4),
I2 => enblData,
O => \PERBIT_GEN[4].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[5].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_6,
Q => currentTxNibbleCnt(5),
R => txComboNibbleCntRst
);
\PERBIT_GEN[5].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(5),
I1 => enblData,
O => gen_cry_kill_n_6
);
\PERBIT_GEN[5].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0FEE"
)
port map (
I0 => \tx_packet_length_reg[15]\(5),
I1 => \^txnibblecnt_pad_reg[11]\,
I2 => currentTxNibbleCnt(5),
I3 => enblData,
O => \PERBIT_GEN[5].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[6].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_5,
Q => currentTxNibbleCnt(6),
R => txComboNibbleCntRst
);
\PERBIT_GEN[6].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(6),
I1 => enblData,
O => gen_cry_kill_n_5
);
\PERBIT_GEN[6].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0FEE"
)
port map (
I0 => \tx_packet_length_reg[15]\(4),
I1 => \^txnibblecnt_pad_reg[11]\,
I2 => currentTxNibbleCnt(6),
I3 => enblData,
O => \PERBIT_GEN[6].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[7].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_4,
Q => currentTxNibbleCnt(7),
R => txComboNibbleCntRst
);
\PERBIT_GEN[7].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(7),
I1 => enblData,
O => gen_cry_kill_n_4
);
\PERBIT_GEN[7].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => cry(4),
CO(3 downto 0) => cry(8 downto 5),
CYINIT => '0',
DI(3) => gen_cry_kill_n_7,
DI(2) => gen_cry_kill_n_6,
DI(1) => gen_cry_kill_n_5,
DI(0) => gen_cry_kill_n_4,
O(3) => xorcy_out_7,
O(2) => xorcy_out_6,
O(1) => xorcy_out_5,
O(0) => xorcy_out_4,
S(3) => \PERBIT_GEN[4].Q_I_GEN_SUB.q_i_ns_reg\,
S(2) => \PERBIT_GEN[5].Q_I_GEN_SUB.q_i_ns_reg\,
S(1) => \PERBIT_GEN[6].Q_I_GEN_SUB.q_i_ns_reg\,
S(0) => \PERBIT_GEN[7].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[7].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0FEE"
)
port map (
I0 => \tx_packet_length_reg[15]\(3),
I1 => \PERBIT_GEN[7].MUXCY_i1_i_2_n_0\,
I2 => currentTxNibbleCnt(7),
I3 => enblData,
O => \PERBIT_GEN[7].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[7].MUXCY_i1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \tx_packet_length_reg[15]\(7),
I1 => \tx_packet_length_reg[15]\(15),
I2 => \tx_packet_length_reg[15]\(11),
I3 => \tx_packet_length_reg[15]\(9),
I4 => \PERBIT_GEN[10].MUXCY_i1_i_3_n_0\,
O => \PERBIT_GEN[7].MUXCY_i1_i_2_n_0\
);
\PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_3,
Q => currentTxNibbleCnt(8),
R => txComboNibbleCntRst
);
\PERBIT_GEN[8].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(8),
I1 => enblData,
O => gen_cry_kill_n_3
);
\PERBIT_GEN[8].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0FEE"
)
port map (
I0 => \tx_packet_length_reg[15]\(2),
I1 => \^txnibblecnt_pad_reg[11]\,
I2 => currentTxNibbleCnt(8),
I3 => enblData,
O => \PERBIT_GEN[8].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[9].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_2,
Q => currentTxNibbleCnt(9),
R => txComboNibbleCntRst
);
\PERBIT_GEN[9].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => currentTxNibbleCnt(9),
I1 => enblData,
O => gen_cry_kill_n_2
);
\PERBIT_GEN[9].MUXCY_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"5530"
)
port map (
I0 => currentTxNibbleCnt(9),
I1 => \^txnibblecnt_pad_reg[11]\,
I2 => \tx_packet_length_reg[15]\(1),
I3 => enblData,
O => \PERBIT_GEN[9].Q_I_GEN_SUB.q_i_ns_reg\
);
STATE12A_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state13a_0\,
I1 => checkBusFifoFull,
I2 => \out\,
O => D21_out
);
STATE13A_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => STATE13A_i_2_n_0,
I1 => STATE13A_i_3_n_0,
I2 => currentTxNibbleCnt(8),
I3 => currentTxNibbleCnt(1),
I4 => currentTxNibbleCnt(2),
O => \^state13a_0\
);
STATE13A_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000400"
)
port map (
I0 => currentTxNibbleCnt(3),
I1 => enblData,
I2 => currentTxNibbleCnt(0),
I3 => \^state13a\(0),
I4 => currentTxNibbleCnt(7),
I5 => currentTxNibbleCnt(6),
O => STATE13A_i_2_n_0
);
STATE13A_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => currentTxNibbleCnt(4),
I1 => currentTxNibbleCnt(10),
I2 => currentTxNibbleCnt(5),
I3 => currentTxNibbleCnt(9),
O => STATE13A_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\ is
port (
currentTxBusFifoWrCnt : out STD_LOGIC_VECTOR ( 3 downto 0 );
STATE11A : out STD_LOGIC;
STATE9A : out STD_LOGIC;
emac_tx_wr_i : in STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\ : in STD_LOGIC;
\PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ : in STD_LOGIC;
\PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ : in STD_LOGIC;
\PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ : in STD_LOGIC;
txComboBusFifoWrCntRst : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\ : entity is "ld_arith_reg";
end \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\ is
signal O : STD_LOGIC;
signal \PERBIT_GEN[10].MUXCY_i1_n_0\ : STD_LOGIC;
signal \PERBIT_GEN[9].MUXCY_i1_n_0\ : STD_LOGIC;
signal \^currenttxbusfifowrcnt\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal gen_cry_kill_n_0 : STD_LOGIC;
signal gen_cry_kill_n_1 : STD_LOGIC;
signal gen_cry_kill_n_2 : STD_LOGIC;
signal xorcy_out_0 : STD_LOGIC;
signal xorcy_out_1 : STD_LOGIC;
signal xorcy_out_2 : STD_LOGIC;
signal xorcy_out_3 : STD_LOGIC;
signal \NLW_PERBIT_GEN[11].MUXCY_i1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_PERBIT_GEN[11].MUXCY_i1_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute box_type : string;
attribute box_type of \PERBIT_GEN[10].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[10].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[10].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[10].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[11].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[11].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[11].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[11].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[11].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[9].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[9].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[9].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[9].MULT_AND_i1\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of STATE10A_i_2 : label is "soft_lutpair56";
attribute SOFT_HLUTNM of STATE8A_i_2 : label is "soft_lutpair56";
begin
currentTxBusFifoWrCnt(3 downto 0) <= \^currenttxbusfifowrcnt\(3 downto 0);
\PERBIT_GEN[10].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => emac_tx_wr_i,
D => xorcy_out_1,
Q => \^currenttxbusfifowrcnt\(1),
R => txComboBusFifoWrCntRst
);
\PERBIT_GEN[10].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^currenttxbusfifowrcnt\(1),
I1 => emac_tx_wr_i,
O => gen_cry_kill_n_1
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => emac_tx_wr_i,
D => xorcy_out_0,
Q => \^currenttxbusfifowrcnt\(0),
R => txComboBusFifoWrCntRst
);
\PERBIT_GEN[11].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^currenttxbusfifowrcnt\(0),
I1 => emac_tx_wr_i,
O => gen_cry_kill_n_0
);
\PERBIT_GEN[11].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_PERBIT_GEN[11].MUXCY_i1_CARRY4_CO_UNCONNECTED\(3),
CO(2) => \PERBIT_GEN[9].MUXCY_i1_n_0\,
CO(1) => \PERBIT_GEN[10].MUXCY_i1_n_0\,
CO(0) => O,
CYINIT => '0',
DI(3) => \NLW_PERBIT_GEN[11].MUXCY_i1_CARRY4_DI_UNCONNECTED\(3),
DI(2) => gen_cry_kill_n_2,
DI(1) => gen_cry_kill_n_1,
DI(0) => gen_cry_kill_n_0,
O(3) => xorcy_out_3,
O(2) => xorcy_out_2,
O(1) => xorcy_out_1,
O(0) => xorcy_out_0,
S(3) => \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\,
S(2) => \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\,
S(1) => \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\,
S(0) => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\
);
\PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => emac_tx_wr_i,
D => xorcy_out_3,
Q => \^currenttxbusfifowrcnt\(3),
R => txComboBusFifoWrCntRst
);
\PERBIT_GEN[9].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => emac_tx_wr_i,
D => xorcy_out_2,
Q => \^currenttxbusfifowrcnt\(2),
R => txComboBusFifoWrCntRst
);
\PERBIT_GEN[9].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^currenttxbusfifowrcnt\(2),
I1 => emac_tx_wr_i,
O => gen_cry_kill_n_2
);
STATE10A_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^currenttxbusfifowrcnt\(0),
I1 => \^currenttxbusfifowrcnt\(1),
I2 => \^currenttxbusfifowrcnt\(2),
I3 => \^currenttxbusfifowrcnt\(3),
O => STATE11A
);
STATE8A_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \^currenttxbusfifowrcnt\(0),
I1 => \^currenttxbusfifowrcnt\(1),
I2 => \^currenttxbusfifowrcnt\(2),
I3 => \^currenttxbusfifowrcnt\(3),
O => STATE9A
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\ is
port (
crcCnt : out STD_LOGIC_VECTOR ( 0 to 3 );
DIA : out STD_LOGIC_VECTOR ( 0 to 0 );
STATE15A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
enblCRC : in STD_LOGIC;
S : in STD_LOGIC;
\PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ : in STD_LOGIC;
\PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ : in STD_LOGIC;
\PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
CE : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
tx_en_i : in STD_LOGIC;
checkBusFifoFullCrc : in STD_LOGIC;
\out\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\ : entity is "ld_arith_reg";
end \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\ is
signal \^crccnt\ : STD_LOGIC_VECTOR ( 0 to 3 );
signal cry : STD_LOGIC_VECTOR ( 3 downto 1 );
signal gen_cry_kill_n_0 : STD_LOGIC;
signal gen_cry_kill_n_1 : STD_LOGIC;
signal gen_cry_kill_n_2 : STD_LOGIC;
signal xorcy_out_0 : STD_LOGIC;
signal xorcy_out_1 : STD_LOGIC;
signal xorcy_out_2 : STD_LOGIC;
signal xorcy_out_3 : STD_LOGIC;
signal \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute box_type : string;
attribute box_type of \PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[1].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[1].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[1].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[2].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[2].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[2].MULT_AND_i1\ : label is "PRIMITIVE";
attribute box_type of \PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[3].MULT_AND_i1\ : label is "MULT_AND";
attribute XILINX_TRANSFORM_PINMAP of \PERBIT_GEN[3].MULT_AND_i1\ : label is "LO:O";
attribute box_type of \PERBIT_GEN[3].MULT_AND_i1\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \PERBIT_GEN[3].MUXCY_i1_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \PERBIT_GEN[3].MUXCY_i1_CARRY4\ : label is "PRIMITIVE";
begin
crcCnt(0 to 3) <= \^crccnt\(0 to 3);
\PERBIT_GEN[0].FF_RST1_GEN.FDSE_i1\: unisim.vcomponents.FDSE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_S_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_3,
Q => \^crccnt\(0),
S => s_axi_aresetn
);
\PERBIT_GEN[1].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_2,
Q => \^crccnt\(1),
R => s_axi_aresetn
);
\PERBIT_GEN[1].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^crccnt\(1),
I1 => enblCRC,
O => gen_cry_kill_n_2
);
\PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_1,
Q => \^crccnt\(2),
R => s_axi_aresetn
);
\PERBIT_GEN[2].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^crccnt\(2),
I1 => enblCRC,
O => gen_cry_kill_n_1
);
\PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => CE,
D => xorcy_out_0,
Q => \^crccnt\(3),
R => s_axi_aresetn
);
\PERBIT_GEN[3].MULT_AND_i1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^crccnt\(3),
I1 => enblCRC,
O => gen_cry_kill_n_0
);
\PERBIT_GEN[3].MUXCY_i1_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_CO_UNCONNECTED\(3),
CO(2 downto 0) => cry(3 downto 1),
CYINIT => enblCRC,
DI(3) => \NLW_PERBIT_GEN[3].MUXCY_i1_CARRY4_DI_UNCONNECTED\(3),
DI(2) => gen_cry_kill_n_2,
DI(1) => gen_cry_kill_n_1,
DI(0) => gen_cry_kill_n_0,
O(3) => xorcy_out_3,
O(2) => xorcy_out_2,
O(1) => xorcy_out_1,
O(0) => xorcy_out_0,
S(3) => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\,
S(2) => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\,
S(1) => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\,
S(0) => S
);
RAM_reg_0_15_0_5_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA8AAAAAAAA"
)
port map (
I0 => tx_en_i,
I1 => \^crccnt\(0),
I2 => \^crccnt\(3),
I3 => \^crccnt\(1),
I4 => \^crccnt\(2),
I5 => checkBusFifoFullCrc,
O => DIA(0)
);
STATE15A_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFE0000"
)
port map (
I0 => \^crccnt\(2),
I1 => \^crccnt\(1),
I2 => \^crccnt\(3),
I3 => \^crccnt\(0),
I4 => checkBusFifoFullCrc,
I5 => \out\,
O => STATE15A
);
STATE16A_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000002"
)
port map (
I0 => checkBusFifoFullCrc,
I1 => \^crccnt\(2),
I2 => \^crccnt\(1),
I3 => \^crccnt\(3),
I4 => \^crccnt\(0),
O => \gic0.gc0.count_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_mdio_if is
port (
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 10 downto 0 );
\MDIO_GEN.mdio_req_i_reg\ : out STD_LOGIC;
prmry_in : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\MDIO_GEN.mdio_clk_i_reg\ : in STD_LOGIC;
phy_mdio_i : in STD_LOGIC;
p_6_in : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\AXI4_LITE_IF_GEN.read_in_prog_reg_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_req_i_reg_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\MDIO_GEN.mdio_wr_data_reg_reg[1]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\ : in STD_LOGIC;
mdio_en_i : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[7]\ : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
p_19_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_mdio_if : entity is "mdio_if";
end system_axi_ethernetlite_0_0_mdio_if;
architecture STRUCTURE of system_axi_ethernetlite_0_0_mdio_if is
signal \FSM_sequential_mdio_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_mdio_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_mdio_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_mdio_state[3]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[10].MDIO_RD_DATA[10]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[11].MDIO_RD_DATA[11]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[13].MDIO_RD_DATA[13]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[14].MDIO_RD_DATA[14]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA[15]_i_1_n_0\ : STD_LOGIC;
signal \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[5].MDIO_RD_DATA[5]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[6].MDIO_RD_DATA[6]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[7].MDIO_RD_DATA[7]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_3_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[0]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[10]_i_3_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[2]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[3]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[4]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[5]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[6]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[8]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[9]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_req_i_i_2_n_0\ : STD_LOGIC;
signal PHY_MDIO_O_i_10_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_11_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_12_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_13_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_1_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_2_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_3_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_4_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_5_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_6_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_7_n_0 : STD_LOGIC;
signal PHY_MDIO_O_i_8_n_0 : STD_LOGIC;
signal PHY_MDIO_O_reg_i_9_n_0 : STD_LOGIC;
signal PHY_MDIO_T_i_1_n_0 : STD_LOGIC;
signal clk_cnt : STD_LOGIC;
signal \clk_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \clk_cnt[5]_i_3_n_0\ : STD_LOGIC;
signal \clk_cnt[5]_i_4_n_0\ : STD_LOGIC;
signal \clk_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal data : STD_LOGIC_VECTOR ( 4 downto 1 );
signal ld_cnt_data_cmb : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \ld_cnt_data_reg[4]_i_1_n_0\ : STD_LOGIC;
signal ld_cnt_en_cmb : STD_LOGIC;
signal ld_cnt_en_reg : STD_LOGIC;
signal ld_cnt_en_reg_i_2_n_0 : STD_LOGIC;
signal mdio_clk_reg : STD_LOGIC;
signal mdio_done_i : STD_LOGIC;
signal mdio_en_reg : STD_LOGIC;
signal mdio_en_reg_i_1_n_0 : STD_LOGIC;
signal mdio_idle_i_1_n_0 : STD_LOGIC;
signal mdio_idle_i_3_n_0 : STD_LOGIC;
signal mdio_idle_reg_n_0 : STD_LOGIC;
signal mdio_in_reg1 : STD_LOGIC;
signal mdio_in_reg2 : STD_LOGIC;
signal mdio_rd_data_reg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal mdio_state : STD_LOGIC;
signal \mdio_state__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of \mdio_state__0\ : signal is "yes";
signal mdio_t_comb : STD_LOGIC;
signal next_state : STD_LOGIC;
signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^phy_mdio_o\ : STD_LOGIC;
signal \^phy_mdio_t\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_mdio_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_mdio_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_mdio_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_sequential_mdio_state_reg[3]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[2]_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[4]_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[5]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[6]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[8]_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[9]_i_2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of PHY_MDIO_O_i_4 : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \clk_cnt[0]_i_1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \clk_cnt[1]_i_1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \clk_cnt[2]_i_1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \clk_cnt[5]_i_4\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of mdio_en_reg_i_1 : label is "soft_lutpair83";
attribute SOFT_HLUTNM of mdio_idle_i_3 : label is "soft_lutpair83";
begin
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\(4 downto 0) <= \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(4 downto 0);
phy_mdio_o <= \^phy_mdio_o\;
phy_mdio_t <= \^phy_mdio_t\;
\FSM_sequential_mdio_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"10001F1F"
)
port map (
I0 => \mdio_state__0\(2),
I1 => \mdio_state__0\(1),
I2 => \mdio_state__0\(3),
I3 => p_6_in(10),
I4 => \mdio_state__0\(0),
O => \FSM_sequential_mdio_state[0]_i_1_n_0\
);
\FSM_sequential_mdio_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"112A"
)
port map (
I0 => \mdio_state__0\(0),
I1 => \mdio_state__0\(3),
I2 => \mdio_state__0\(2),
I3 => \mdio_state__0\(1),
O => \FSM_sequential_mdio_state[1]_i_1_n_0\
);
\FSM_sequential_mdio_state[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"3464"
)
port map (
I0 => \mdio_state__0\(3),
I1 => \mdio_state__0\(2),
I2 => \mdio_state__0\(1),
I3 => \mdio_state__0\(0),
O => \FSM_sequential_mdio_state[2]_i_1_n_0\
);
\FSM_sequential_mdio_state[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => next_state,
I1 => mdio_clk_reg,
I2 => \MDIO_GEN.mdio_clk_i_reg\,
O => mdio_state
);
\FSM_sequential_mdio_state[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F80"
)
port map (
I0 => \mdio_state__0\(1),
I1 => \mdio_state__0\(0),
I2 => \mdio_state__0\(2),
I3 => \mdio_state__0\(3),
O => \FSM_sequential_mdio_state[3]_i_2_n_0\
);
\FSM_sequential_mdio_state[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"3F167E563F167F57"
)
port map (
I0 => \mdio_state__0\(1),
I1 => \mdio_state__0\(3),
I2 => \mdio_state__0\(2),
I3 => ld_cnt_en_reg_i_2_n_0,
I4 => \mdio_state__0\(0),
I5 => mdio_idle_reg_n_0,
O => next_state
);
\FSM_sequential_mdio_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => mdio_state,
D => \FSM_sequential_mdio_state[0]_i_1_n_0\,
Q => \mdio_state__0\(0),
R => prmry_in
);
\FSM_sequential_mdio_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => mdio_state,
D => \FSM_sequential_mdio_state[1]_i_1_n_0\,
Q => \mdio_state__0\(1),
R => prmry_in
);
\FSM_sequential_mdio_state_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => mdio_state,
D => \FSM_sequential_mdio_state[2]_i_1_n_0\,
Q => \mdio_state__0\(2),
R => prmry_in
);
\FSM_sequential_mdio_state_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => mdio_state,
D => \FSM_sequential_mdio_state[3]_i_2_n_0\,
Q => \mdio_state__0\(3),
R => prmry_in
);
\MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => ld_cnt_en_reg_i_2_n_0,
I3 => mdio_clk_reg,
I4 => \MDIO_GEN.mdio_clk_i_reg\,
I5 => mdio_rd_data_reg(0),
O => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => \mdio_state__0\(3),
I1 => \mdio_state__0\(2),
I2 => \mdio_state__0\(0),
I3 => \mdio_state__0\(1),
O => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[0].MDIO_RD_DATA_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_1_n_0\,
Q => mdio_rd_data_reg(0),
R => prmry_in
);
\MDIO_CAPTURE_DATA[10].MDIO_RD_DATA[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(10),
O => \MDIO_CAPTURE_DATA[10].MDIO_RD_DATA[10]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[10].MDIO_RD_DATA_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[10].MDIO_RD_DATA[10]_i_1_n_0\,
Q => mdio_rd_data_reg(10),
R => prmry_in
);
\MDIO_CAPTURE_DATA[11].MDIO_RD_DATA[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(0),
O => \MDIO_CAPTURE_DATA[11].MDIO_RD_DATA[11]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[11].MDIO_RD_DATA_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[11].MDIO_RD_DATA[11]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(0),
R => prmry_in
);
\MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \clk_cnt[5]_i_4_n_0\,
I3 => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(1),
O => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FDFF"
)
port map (
I0 => \clk_cnt_reg__0\(3),
I1 => \clk_cnt_reg__0\(4),
I2 => \clk_cnt_reg__0\(5),
I3 => \clk_cnt_reg__0\(2),
O => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[12].MDIO_RD_DATA_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(1),
R => prmry_in
);
\MDIO_CAPTURE_DATA[13].MDIO_RD_DATA[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(2),
O => \MDIO_CAPTURE_DATA[13].MDIO_RD_DATA[13]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[13].MDIO_RD_DATA_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[13].MDIO_RD_DATA[13]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(2),
R => prmry_in
);
\MDIO_CAPTURE_DATA[14].MDIO_RD_DATA[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(3),
O => \MDIO_CAPTURE_DATA[14].MDIO_RD_DATA[14]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[14].MDIO_RD_DATA_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[14].MDIO_RD_DATA[14]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(3),
R => prmry_in
);
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[12].MDIO_RD_DATA[12]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(4),
O => \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA[15]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA[15]_i_1_n_0\,
Q => \^mdio_capture_data[15].mdio_rd_data_reg[15]_0\(4),
R => prmry_in
);
\MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(1),
O => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \clk_cnt_reg__0\(0),
I1 => \clk_cnt_reg__0\(1),
O => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \clk_cnt_reg__0\(2),
I1 => \clk_cnt_reg__0\(4),
I2 => \clk_cnt_reg__0\(5),
I3 => \clk_cnt_reg__0\(3),
O => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\
);
\MDIO_CAPTURE_DATA[1].MDIO_RD_DATA_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_1_n_0\,
Q => mdio_rd_data_reg(1),
R => prmry_in
);
\MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(2),
O => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \clk_cnt_reg__0\(1),
I1 => \clk_cnt_reg__0\(0),
O => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[2].MDIO_RD_DATA_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_1_n_0\,
Q => mdio_rd_data_reg(2),
R => prmry_in
);
\MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_3_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(3),
O => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \clk_cnt_reg__0\(0),
I1 => \clk_cnt_reg__0\(1),
O => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[3].MDIO_RD_DATA_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_1_n_0\,
Q => mdio_rd_data_reg(3),
R => prmry_in
);
\MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \clk_cnt[5]_i_4_n_0\,
I3 => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(4),
O => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FEFF"
)
port map (
I0 => \clk_cnt_reg__0\(4),
I1 => \clk_cnt_reg__0\(5),
I2 => \clk_cnt_reg__0\(3),
I3 => \clk_cnt_reg__0\(2),
O => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[4].MDIO_RD_DATA_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_1_n_0\,
Q => mdio_rd_data_reg(4),
R => prmry_in
);
\MDIO_CAPTURE_DATA[5].MDIO_RD_DATA[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(5),
O => \MDIO_CAPTURE_DATA[5].MDIO_RD_DATA[5]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[5].MDIO_RD_DATA_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[5].MDIO_RD_DATA[5]_i_1_n_0\,
Q => mdio_rd_data_reg(5),
R => prmry_in
);
\MDIO_CAPTURE_DATA[6].MDIO_RD_DATA[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[2].MDIO_RD_DATA[2]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(6),
O => \MDIO_CAPTURE_DATA[6].MDIO_RD_DATA[6]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[6].MDIO_RD_DATA_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[6].MDIO_RD_DATA[6]_i_1_n_0\,
Q => mdio_rd_data_reg(6),
R => prmry_in
);
\MDIO_CAPTURE_DATA[7].MDIO_RD_DATA[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[3].MDIO_RD_DATA[3]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[4].MDIO_RD_DATA[4]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(7),
O => \MDIO_CAPTURE_DATA[7].MDIO_RD_DATA[7]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[7].MDIO_RD_DATA_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[7].MDIO_RD_DATA[7]_i_1_n_0\,
Q => mdio_rd_data_reg(7),
R => prmry_in
);
\MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_3_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(8),
O => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \clk_cnt_reg__0\(1),
I1 => \clk_cnt_reg__0\(0),
I2 => \clk_cnt_reg__0\(2),
O => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \clk_cnt_reg__0\(5),
I1 => \clk_cnt_reg__0\(4),
I2 => \clk_cnt_reg__0\(3),
O => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_3_n_0\
);
\MDIO_CAPTURE_DATA[8].MDIO_RD_DATA_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[8].MDIO_RD_DATA[8]_i_1_n_0\,
Q => mdio_rd_data_reg(8),
R => prmry_in
);
\MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEFFFFF00200000"
)
port map (
I0 => mdio_in_reg2,
I1 => \MDIO_CAPTURE_DATA[0].MDIO_RD_DATA[0]_i_2_n_0\,
I2 => \MDIO_CAPTURE_DATA[1].MDIO_RD_DATA[1]_i_2_n_0\,
I3 => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\,
I4 => mdio_idle_i_3_n_0,
I5 => mdio_rd_data_reg(9),
O => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_1_n_0\
);
\MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \clk_cnt_reg__0\(2),
I1 => \clk_cnt_reg__0\(3),
I2 => \clk_cnt_reg__0\(4),
I3 => \clk_cnt_reg__0\(5),
O => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_2_n_0\
);
\MDIO_CAPTURE_DATA[9].MDIO_RD_DATA_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_CAPTURE_DATA[9].MDIO_RD_DATA[9]_i_1_n_0\,
Q => mdio_rd_data_reg(9),
R => prmry_in
);
\MDIO_GEN.mdio_data_out[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8808"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[0]_i_2_n_0\,
I1 => s_axi_aresetn,
I2 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I3 => p_6_in(0),
O => D(0)
);
\MDIO_GEN.mdio_data_out[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCCFCCEFECEFEC"
)
port map (
I0 => Q(0),
I1 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I2 => \AXI4_LITE_IF_GEN.read_in_prog_reg_0\,
I3 => \MDIO_GEN.mdio_req_i_reg_0\,
I4 => mdio_rd_data_reg(0),
I5 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\(0),
O => \MDIO_GEN.mdio_data_out[0]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[10]_i_3_n_0\,
I1 => Q(10),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(10),
O => D(10)
);
\MDIO_GEN.mdio_data_out[10]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(10),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[10]_i_3_n_0\
);
\MDIO_GEN.mdio_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_wr_data_reg_reg[1]\,
I1 => mdio_rd_data_reg(1),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(1),
O => D(1)
);
\MDIO_GEN.mdio_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[2]_i_2_n_0\,
I1 => Q(2),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(2),
O => D(2)
);
\MDIO_GEN.mdio_data_out[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(2),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[2]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8808"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[3]_i_2_n_0\,
I1 => s_axi_aresetn,
I2 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I3 => p_6_in(3),
O => D(3)
);
\MDIO_GEN.mdio_data_out[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFECEFECFFFCCFCC"
)
port map (
I0 => mdio_rd_data_reg(3),
I1 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I2 => \AXI4_LITE_IF_GEN.read_in_prog_reg_0\,
I3 => mdio_en_i,
I4 => Q(3),
I5 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\(0),
O => \MDIO_GEN.mdio_data_out[3]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[4]_i_2_n_0\,
I1 => Q(4),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(4),
O => D(4)
);
\MDIO_GEN.mdio_data_out[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(4),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[4]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[5]_i_2_n_0\,
I1 => Q(5),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(5),
O => D(5)
);
\MDIO_GEN.mdio_data_out[5]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(5),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[5]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[6]_i_2_n_0\,
I1 => Q(6),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(6),
O => D(6)
);
\MDIO_GEN.mdio_data_out[6]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(6),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[6]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_wr_data_reg_reg[7]\,
I1 => mdio_rd_data_reg(7),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(7),
O => D(7)
);
\MDIO_GEN.mdio_data_out[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[8]_i_2_n_0\,
I1 => Q(8),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(8),
O => D(8)
);
\MDIO_GEN.mdio_data_out[8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(8),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[8]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00AE000000AE00"
)
port map (
I0 => \MDIO_GEN.mdio_data_out[9]_i_2_n_0\,
I1 => Q(9),
I2 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I3 => s_axi_aresetn,
I4 => \AXI4_LITE_IF_GEN.read_in_prog_reg\,
I5 => p_6_in(9),
O => D(9)
);
\MDIO_GEN.mdio_data_out[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_rd_data_reg(9),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
O => \MDIO_GEN.mdio_data_out[9]_i_2_n_0\
);
\MDIO_GEN.mdio_req_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA3FFFAAAA0000"
)
port map (
I0 => s_axi_wdata(0),
I1 => \mdio_state__0\(2),
I2 => \mdio_state__0\(3),
I3 => \MDIO_GEN.mdio_req_i_i_2_n_0\,
I4 => p_19_out,
I5 => \MDIO_GEN.mdio_req_i_reg_0\,
O => \MDIO_GEN.mdio_req_i_reg\
);
\MDIO_GEN.mdio_req_i_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \mdio_state__0\(1),
I1 => \mdio_state__0\(0),
O => \MDIO_GEN.mdio_req_i_i_2_n_0\
);
PHY_MDIO_O_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF1FF0000F100"
)
port map (
I0 => PHY_MDIO_O_i_2_n_0,
I1 => \mdio_state__0\(3),
I2 => PHY_MDIO_O_i_3_n_0,
I3 => mdio_clk_reg,
I4 => \MDIO_GEN.mdio_clk_i_reg\,
I5 => \^phy_mdio_o\,
O => PHY_MDIO_O_i_1_n_0
);
PHY_MDIO_O_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => Q(11),
I1 => Q(10),
I2 => \clk_cnt_reg__0\(1),
I3 => Q(9),
I4 => \clk_cnt_reg__0\(0),
I5 => Q(8),
O => PHY_MDIO_O_i_10_n_0
);
PHY_MDIO_O_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => Q(15),
I1 => Q(14),
I2 => \clk_cnt_reg__0\(1),
I3 => Q(13),
I4 => \clk_cnt_reg__0\(0),
I5 => Q(12),
O => PHY_MDIO_O_i_11_n_0
);
PHY_MDIO_O_i_12: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => \clk_cnt_reg__0\(1),
I3 => Q(1),
I4 => \clk_cnt_reg__0\(0),
I5 => Q(0),
O => PHY_MDIO_O_i_12_n_0
);
PHY_MDIO_O_i_13: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => Q(7),
I1 => Q(6),
I2 => \clk_cnt_reg__0\(1),
I3 => Q(5),
I4 => \clk_cnt_reg__0\(0),
I5 => Q(4),
O => PHY_MDIO_O_i_13_n_0
);
PHY_MDIO_O_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"3FAF0F0F00AF0F0F"
)
port map (
I0 => p_6_in(10),
I1 => PHY_MDIO_O_i_4_n_0,
I2 => \mdio_state__0\(0),
I3 => \mdio_state__0\(1),
I4 => \mdio_state__0\(2),
I5 => PHY_MDIO_O_i_5_n_0,
O => PHY_MDIO_O_i_2_n_0
);
PHY_MDIO_O_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00FC00CC32333233"
)
port map (
I0 => p_6_in(10),
I1 => \mdio_state__0\(0),
I2 => \mdio_state__0\(3),
I3 => \mdio_state__0\(2),
I4 => PHY_MDIO_O_i_6_n_0,
I5 => \mdio_state__0\(1),
O => PHY_MDIO_O_i_3_n_0
);
PHY_MDIO_O_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"02FF0200"
)
port map (
I0 => p_6_in(4),
I1 => \clk_cnt_reg__0\(1),
I2 => \clk_cnt_reg__0\(0),
I3 => \clk_cnt_reg__0\(2),
I4 => PHY_MDIO_O_i_7_n_0,
O => PHY_MDIO_O_i_4_n_0
);
PHY_MDIO_O_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBABFBFBFBFB"
)
port map (
I0 => \mdio_state__0\(0),
I1 => PHY_MDIO_O_i_8_n_0,
I2 => \clk_cnt_reg__0\(2),
I3 => \clk_cnt_reg__0\(0),
I4 => \clk_cnt_reg__0\(1),
I5 => p_6_in(9),
O => PHY_MDIO_O_i_5_n_0
);
PHY_MDIO_O_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => PHY_MDIO_O_reg_i_9_n_0,
I1 => \clk_cnt_reg__0\(3),
I2 => PHY_MDIO_O_i_10_n_0,
I3 => \clk_cnt_reg__0\(2),
I4 => PHY_MDIO_O_i_11_n_0,
I5 => \clk_cnt_reg__0\(4),
O => PHY_MDIO_O_i_6_n_0
);
PHY_MDIO_O_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => p_6_in(3),
I1 => p_6_in(2),
I2 => \clk_cnt_reg__0\(1),
I3 => p_6_in(1),
I4 => \clk_cnt_reg__0\(0),
I5 => p_6_in(0),
O => PHY_MDIO_O_i_7_n_0
);
PHY_MDIO_O_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => p_6_in(8),
I1 => p_6_in(7),
I2 => \clk_cnt_reg__0\(1),
I3 => p_6_in(6),
I4 => \clk_cnt_reg__0\(0),
I5 => p_6_in(5),
O => PHY_MDIO_O_i_8_n_0
);
PHY_MDIO_O_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => PHY_MDIO_O_i_1_n_0,
Q => \^phy_mdio_o\,
R => prmry_in
);
PHY_MDIO_O_reg_i_9: unisim.vcomponents.MUXF7
port map (
I0 => PHY_MDIO_O_i_12_n_0,
I1 => PHY_MDIO_O_i_13_n_0,
O => PHY_MDIO_O_reg_i_9_n_0,
S => \clk_cnt_reg__0\(2)
);
PHY_MDIO_T_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => mdio_t_comb,
I1 => mdio_clk_reg,
I2 => \MDIO_GEN.mdio_clk_i_reg\,
I3 => \^phy_mdio_t\,
O => PHY_MDIO_T_i_1_n_0
);
PHY_MDIO_T_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"222000B9"
)
port map (
I0 => \mdio_state__0\(3),
I1 => \mdio_state__0\(2),
I2 => p_6_in(10),
I3 => \mdio_state__0\(1),
I4 => \mdio_state__0\(0),
O => mdio_t_comb
);
PHY_MDIO_T_reg: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => PHY_MDIO_T_i_1_n_0,
Q => \^phy_mdio_t\,
S => prmry_in
);
\clk_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => data(1),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(0),
O => \p_0_in__1\(0)
);
\clk_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => data(1),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(0),
I3 => \clk_cnt_reg__0\(1),
O => \p_0_in__1\(1)
);
\clk_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => data(2),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(2),
I3 => \clk_cnt_reg__0\(1),
I4 => \clk_cnt_reg__0\(0),
O => \p_0_in__1\(2)
);
\clk_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => data(1),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(3),
I3 => \clk_cnt_reg__0\(2),
I4 => \clk_cnt_reg__0\(0),
I5 => \clk_cnt_reg__0\(1),
O => \p_0_in__1\(3)
);
\clk_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B88BB8B8"
)
port map (
I0 => data(4),
I1 => ld_cnt_en_reg,
I2 => \clk_cnt_reg__0\(4),
I3 => \clk_cnt_reg__0\(3),
I4 => \clk_cnt[5]_i_4_n_0\,
I5 => \clk_cnt_reg__0\(2),
O => \p_0_in__1\(4)
);
\clk_cnt[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => mdio_clk_reg,
I1 => \MDIO_GEN.mdio_clk_i_reg\,
I2 => \clk_cnt[5]_i_3_n_0\,
O => clk_cnt
);
\clk_cnt[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555000055450010"
)
port map (
I0 => ld_cnt_en_reg,
I1 => \clk_cnt_reg__0\(2),
I2 => \clk_cnt[5]_i_4_n_0\,
I3 => \clk_cnt_reg__0\(4),
I4 => \clk_cnt_reg__0\(5),
I5 => \clk_cnt_reg__0\(3),
O => \clk_cnt[5]_i_2_n_0\
);
\clk_cnt[5]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"5545551455451515"
)
port map (
I0 => ld_cnt_en_reg,
I1 => \mdio_state__0\(2),
I2 => \mdio_state__0\(1),
I3 => ld_cnt_en_reg_i_2_n_0,
I4 => \mdio_state__0\(3),
I5 => \mdio_state__0\(0),
O => \clk_cnt[5]_i_3_n_0\
);
\clk_cnt[5]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \clk_cnt_reg__0\(0),
I1 => \clk_cnt_reg__0\(1),
O => \clk_cnt[5]_i_4_n_0\
);
\clk_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(0),
Q => \clk_cnt_reg__0\(0),
R => prmry_in
);
\clk_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(1),
Q => \clk_cnt_reg__0\(1),
R => prmry_in
);
\clk_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(2),
Q => \clk_cnt_reg__0\(2),
R => prmry_in
);
\clk_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(3),
Q => \clk_cnt_reg__0\(3),
R => prmry_in
);
\clk_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \p_0_in__1\(4),
Q => \clk_cnt_reg__0\(4),
R => prmry_in
);
\clk_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => clk_cnt,
D => \clk_cnt[5]_i_2_n_0\,
Q => \clk_cnt_reg__0\(5),
R => prmry_in
);
\ld_cnt_data_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000C01"
)
port map (
I0 => mdio_idle_reg_n_0,
I1 => \mdio_state__0\(3),
I2 => \mdio_state__0\(2),
I3 => \mdio_state__0\(0),
I4 => \mdio_state__0\(1),
O => ld_cnt_data_cmb(1)
);
\ld_cnt_data_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00203C0000203C03"
)
port map (
I0 => ld_cnt_en_reg_i_2_n_0,
I1 => \mdio_state__0\(3),
I2 => \mdio_state__0\(2),
I3 => \mdio_state__0\(0),
I4 => \mdio_state__0\(1),
I5 => mdio_idle_reg_n_0,
O => ld_cnt_data_cmb(2)
);
\ld_cnt_data_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => mdio_idle_reg_n_0,
I1 => \mdio_state__0\(1),
I2 => \mdio_state__0\(0),
I3 => \mdio_state__0\(2),
I4 => \mdio_state__0\(3),
O => \ld_cnt_data_reg[4]_i_1_n_0\
);
\ld_cnt_data_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ld_cnt_data_cmb(1),
Q => data(1),
R => prmry_in
);
\ld_cnt_data_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ld_cnt_data_cmb(2),
Q => data(2),
R => prmry_in
);
\ld_cnt_data_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ld_cnt_data_reg[4]_i_1_n_0\,
Q => data(4),
R => prmry_in
);
ld_cnt_en_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00303803"
)
port map (
I0 => ld_cnt_en_reg_i_2_n_0,
I1 => \mdio_state__0\(1),
I2 => \mdio_state__0\(0),
I3 => \mdio_state__0\(2),
I4 => \mdio_state__0\(3),
O => ld_cnt_en_cmb
);
ld_cnt_en_reg_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \clk_cnt_reg__0\(2),
I1 => \clk_cnt_reg__0\(0),
I2 => \clk_cnt_reg__0\(1),
I3 => \clk_cnt_reg__0\(4),
I4 => \clk_cnt_reg__0\(5),
I5 => \clk_cnt_reg__0\(3),
O => ld_cnt_en_reg_i_2_n_0
);
ld_cnt_en_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ld_cnt_en_cmb,
Q => ld_cnt_en_reg,
R => prmry_in
);
mdio_clk_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.mdio_clk_i_reg\,
Q => mdio_clk_reg,
R => prmry_in
);
mdio_en_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EFFF2000"
)
port map (
I0 => mdio_en_i,
I1 => \MDIO_GEN.mdio_clk_i_reg\,
I2 => mdio_clk_reg,
I3 => mdio_idle_reg_n_0,
I4 => mdio_en_reg,
O => mdio_en_reg_i_1_n_0
);
mdio_en_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mdio_en_reg_i_1_n_0,
Q => mdio_en_reg,
R => prmry_in
);
mdio_idle_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF70FFF0FFF0FF"
)
port map (
I0 => mdio_en_reg,
I1 => \MDIO_GEN.mdio_req_i_reg_0\,
I2 => mdio_idle_reg_n_0,
I3 => s_axi_aresetn,
I4 => mdio_done_i,
I5 => mdio_idle_i_3_n_0,
O => mdio_idle_i_1_n_0
);
mdio_idle_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \mdio_state__0\(0),
I1 => \mdio_state__0\(1),
I2 => \mdio_state__0\(3),
I3 => \mdio_state__0\(2),
O => mdio_done_i
);
mdio_idle_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \MDIO_GEN.mdio_clk_i_reg\,
I1 => mdio_clk_reg,
O => mdio_idle_i_3_n_0
);
mdio_idle_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mdio_idle_i_1_n_0,
Q => mdio_idle_reg_n_0,
R => '0'
);
mdio_in_reg1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => phy_mdio_i,
Q => mdio_in_reg1,
R => prmry_in
);
mdio_in_reg2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mdio_in_reg1,
Q => mdio_in_reg2,
R => prmry_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_mux_onehot_f is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\txNibbleCnt_pad_reg[11]\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC;
STATE15A : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC;
STATE15A_0 : in STD_LOGIC;
STATE12A : in STD_LOGIC;
STATE15A_1 : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC;
STATE15A_2 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_mux_onehot_f : entity is "mux_onehot_f";
end system_axi_ethernetlite_0_0_mux_onehot_f;
architecture STRUCTURE of system_axi_ethernetlite_0_0_mux_onehot_f is
signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal cyout_1 : STD_LOGIC;
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type : string;
attribute box_type of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute box_type of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
begin
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(3),
CO(0) => cyout_1,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => STATE15A,
S(0) => \gen_wr_b.gen_word_wide.mem_reg\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(2),
CO(0) => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => STATE15A_0,
S(0) => \gen_wr_b.gen_word_wide.mem_reg_0\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(1),
CO(0) => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => STATE15A_1,
S(0) => STATE12A
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => Q(0),
I1 => Q(8),
I2 => Q(6),
I3 => Q(7),
I4 => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3_n_0\,
I5 => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4_n_0\,
O => \txNibbleCnt_pad_reg[11]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => Q(11),
I1 => Q(10),
I2 => Q(4),
I3 => Q(1),
O => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_3_n_0\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => Q(5),
I1 => Q(9),
I2 => Q(2),
I3 => Q(3),
O => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_4_n_0\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(0),
CO(0) => \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => STATE15A_2,
S(0) => \gen_wr_b.gen_word_wide.mem_reg_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_ram16x4 is
port (
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]_0\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
mac_addr_ram_we : in STD_LOGIC;
mac_addr_ram_addr : in STD_LOGIC_VECTOR ( 0 to 3 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_ram16x4 : entity is "ram16x4";
end system_axi_ethernetlite_0_0_ram16x4;
architecture STRUCTURE of system_axi_ethernetlite_0_0_ram16x4 is
signal mac_addr_ram_data : STD_LOGIC_VECTOR ( 0 to 3 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ram16x1_0 : label is "RAM16X1S";
attribute box_type : string;
attribute box_type of ram16x1_0 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ram16x1_1 : label is "RAM16X1S";
attribute box_type of ram16x1_1 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ram16x1_2 : label is "RAM16X1S";
attribute box_type of ram16x1_2 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of ram16x1_3 : label is "RAM16X1S";
attribute box_type of ram16x1_3 : label is "PRIMITIVE";
begin
ram16x1_0: unisim.vcomponents.RAM32X1S
generic map(
INIT => X"00000220",
IS_WCLK_INVERTED => '0'
)
port map (
A0 => mac_addr_ram_addr(3),
A1 => mac_addr_ram_addr(2),
A2 => mac_addr_ram_addr(1),
A3 => mac_addr_ram_addr(0),
A4 => '0',
D => \gen_wr_b.gen_word_wide.mem_reg\(0),
O => mac_addr_ram_data(3),
WCLK => s_axi_aclk,
WE => mac_addr_ram_we
);
ram16x1_1: unisim.vcomponents.RAM32X1S
generic map(
INIT => X"00000710",
IS_WCLK_INVERTED => '0'
)
port map (
A0 => mac_addr_ram_addr(3),
A1 => mac_addr_ram_addr(2),
A2 => mac_addr_ram_addr(1),
A3 => mac_addr_ram_addr(0),
A4 => '0',
D => \gen_wr_b.gen_word_wide.mem_reg\(1),
O => mac_addr_ram_data(2),
WCLK => s_axi_aclk,
WE => mac_addr_ram_we
);
ram16x1_2: unisim.vcomponents.RAM32X1S
generic map(
INIT => X"00000E30",
IS_WCLK_INVERTED => '0'
)
port map (
A0 => mac_addr_ram_addr(3),
A1 => mac_addr_ram_addr(2),
A2 => mac_addr_ram_addr(1),
A3 => mac_addr_ram_addr(0),
A4 => '0',
D => \gen_wr_b.gen_word_wide.mem_reg\(2),
O => mac_addr_ram_data(1),
WCLK => s_axi_aclk,
WE => mac_addr_ram_we
);
ram16x1_3: unisim.vcomponents.RAM32X1S
generic map(
INIT => X"00000F10",
IS_WCLK_INVERTED => '0'
)
port map (
A0 => mac_addr_ram_addr(3),
A1 => mac_addr_ram_addr(2),
A2 => mac_addr_ram_addr(1),
A3 => mac_addr_ram_addr(0),
A4 => '0',
D => \gen_wr_b.gen_word_wide.mem_reg\(3),
O => mac_addr_ram_data(0),
WCLK => s_axi_aclk,
WE => mac_addr_ram_we
);
state22a_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => mac_addr_ram_data(2),
I1 => Q(1),
I2 => mac_addr_ram_data(0),
I3 => Q(3),
O => \rdDestAddrNib_D_t_q_reg[1]_0\
);
state22a_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => mac_addr_ram_data(1),
I1 => Q(2),
I2 => mac_addr_ram_data(3),
I3 => Q(0),
O => \rdDestAddrNib_D_t_q_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rx_statemachine is
port (
crcokr1 : out STD_LOGIC;
rxCrcRst : out STD_LOGIC;
sfd1CheckBusFifoEmpty : out STD_LOGIC;
rx_start : out STD_LOGIC;
startReadDestAdrNib : out STD_LOGIC;
startReadDataNib : out STD_LOGIC;
busFifoData_is_5_d1 : out STD_LOGIC;
rxCrcEn : out STD_LOGIC;
rxCrcEn_d1_reg : out STD_LOGIC;
wea : out STD_LOGIC_VECTOR ( 0 to 0 );
rx_addr_en : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]_0\ : out STD_LOGIC;
ram_valid_i : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
state2a_0 : out STD_LOGIC;
\rxbuffer_addr_reg[0]\ : out STD_LOGIC;
D_5 : out STD_LOGIC;
RX_DONE_D1_I : out STD_LOGIC;
\crc_local_reg[31]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : out STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : out STD_LOGIC;
ena : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
state17a_0 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]_1\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
crcokdelay_0 : in STD_LOGIC;
D : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ : in STD_LOGIC;
D5_out : in STD_LOGIC;
D13_out : in STD_LOGIC;
D6_out : in STD_LOGIC;
D11_out : in STD_LOGIC;
\gpr1.dout_i_reg[2]\ : in STD_LOGIC;
\gpr1.dout_i_reg[5]\ : in STD_LOGIC;
rxBusFifoRdAck : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gpr1.dout_i_reg[1]\ : in STD_LOGIC;
\gv.ram_valid_d1_reg\ : in STD_LOGIC;
ram_empty_i_reg : in STD_LOGIC;
goto_readDestAdrNib1 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\gpr1.dout_i_reg[1]_0\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[2]\ : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[1]\ : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_5_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_9_in : in STD_LOGIC_VECTOR ( 0 to 0 );
STATE17A : in STD_LOGIC;
tx_intr_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
rx_intr_en0 : in STD_LOGIC;
rx_pong_ping_l : in STD_LOGIC;
ping_rx_status_reg_0 : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg\ : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg_1\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rx_statemachine : entity is "rx_statemachine";
end system_axi_ethernetlite_0_0_rx_statemachine;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rx_statemachine is
signal D10_out : STD_LOGIC;
signal D12_out : STD_LOGIC;
signal D18_out : STD_LOGIC;
signal \Mac_addr_ram_addr_rd[0]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_rd[1]_i_2_n_0\ : STD_LOGIC;
signal \^rx_done_d1_i\ : STD_LOGIC;
signal \^busfifodata_is_5_d1\ : STD_LOGIC;
signal checkingBroadcastAdr_reg : STD_LOGIC;
signal checkingBroadcastAdr_reg_i_1_n_0 : STD_LOGIC;
signal checkingBroadcastAdr_reg_i_2_n_0 : STD_LOGIC;
signal checkingBroadcastAdr_reg_i_3_n_0 : STD_LOGIC;
signal crcCheck : STD_LOGIC;
signal \^crcokr1\ : STD_LOGIC;
signal \gv.ram_valid_d1_i_3_n_0\ : STD_LOGIC;
signal mac_addr_ram_addr_rd_D : STD_LOGIC_VECTOR ( 0 to 3 );
signal pkt_length_cnt0 : STD_LOGIC;
signal \pkt_length_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[2]_i_2_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[6]_i_3_n_0\ : STD_LOGIC;
signal \pkt_length_cnt[6]_i_4_n_0\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \pkt_length_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal preamble_error_reg : STD_LOGIC;
signal rdDestAddrNib_D_t : STD_LOGIC_VECTOR ( 0 to 3 );
signal rdDestAddrNib_D_t_q : STD_LOGIC_VECTOR ( 0 to 3 );
signal \rdDestAddrNib_D_t_q[0]_i_1_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[0]_i_3_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[0]_i_4_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[0]_i_5_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[1]_i_2_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[1]_i_3_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[1]_i_4_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[2]_i_2_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[3]_i_3_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[3]_i_4_n_0\ : STD_LOGIC;
signal \rdDestAddrNib_D_t_q[3]_i_6_n_0\ : STD_LOGIC;
signal \^rddestaddrnib_d_t_q_reg[1]_0\ : STD_LOGIC;
signal rxAbortRst : STD_LOGIC;
signal \^rxcrcen_d1_reg\ : STD_LOGIC;
signal \^rxcrcrst\ : STD_LOGIC;
signal rxDone : STD_LOGIC;
signal \^rx_addr_en\ : STD_LOGIC;
signal \^rx_start\ : STD_LOGIC;
signal \^sfd1checkbusfifoempty\ : STD_LOGIC;
signal \^startreaddatanib\ : STD_LOGIC;
signal \^startreaddestadrnib\ : STD_LOGIC;
signal state0a_i_3_n_0 : STD_LOGIC;
signal state22a_i_1_n_0 : STD_LOGIC;
signal state22a_i_4_n_0 : STD_LOGIC;
signal waitForSfd1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_rd[0]_i_2\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_rd[1]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_rd[2]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_rd[3]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of checkingBroadcastAdr_reg_i_3 : label is "soft_lutpair44";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of crcokdelay : label is "FDR";
attribute box_type : string;
attribute box_type of crcokdelay : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \gv.ram_valid_d1_i_2\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \gv.ram_valid_d1_i_3\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \pkt_length_cnt[2]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \pkt_length_cnt[3]_i_2\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \pkt_length_cnt[5]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \pkt_length_cnt[6]_i_3\ : label is "soft_lutpair34";
attribute XILINX_LEGACY_PRIM of preamble : label is "FDR";
attribute box_type of preamble : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[0]_i_3\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[0]_i_4\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[1]_i_3\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[1]_i_4\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[3]_i_3\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[3]_i_4\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \rdDestAddrNib_D_t_q[3]_i_6\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of rxCrcEn_d1_i_1 : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \rxbuffer_addr[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \rxbuffer_addr[11]_i_2\ : label is "soft_lutpair35";
attribute XILINX_LEGACY_PRIM of state0a : label is "FDS";
attribute box_type of state0a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state0a_i_3 : label is "soft_lutpair43";
attribute XILINX_LEGACY_PRIM of state17a_RnM : label is "FDR";
attribute box_type of state17a_RnM : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of state18a : label is "FDR";
attribute box_type of state18a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state18a_i_1 : label is "soft_lutpair32";
attribute XILINX_LEGACY_PRIM of state1a : label is "FDR";
attribute box_type of state1a : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of state20a : label is "FDR";
attribute box_type of state20a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state20a_i_1 : label is "soft_lutpair42";
attribute XILINX_LEGACY_PRIM of state22a : label is "FDR";
attribute box_type of state22a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state22a_i_1 : label is "soft_lutpair42";
attribute SOFT_HLUTNM of state22a_i_4 : label is "soft_lutpair41";
attribute XILINX_LEGACY_PRIM of state2a : label is "FDR";
attribute box_type of state2a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of state2a_i_3 : label is "soft_lutpair43";
attribute XILINX_LEGACY_PRIM of state3a : label is "FDR";
attribute box_type of state3a : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of state4a : label is "FDR";
attribute box_type of state4a : label is "PRIMITIVE";
attribute SOFT_HLUTNM of xpm_memory_base_inst_i_1 : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of xpm_memory_base_inst_i_2 : label is "soft_lutpair38";
begin
RX_DONE_D1_I <= \^rx_done_d1_i\;
busFifoData_is_5_d1 <= \^busfifodata_is_5_d1\;
crcokr1 <= \^crcokr1\;
\rdDestAddrNib_D_t_q_reg[1]_0\ <= \^rddestaddrnib_d_t_q_reg[1]_0\;
rxCrcEn_d1_reg <= \^rxcrcen_d1_reg\;
rxCrcRst <= \^rxcrcrst\;
rx_addr_en <= \^rx_addr_en\;
rx_start <= \^rx_start\;
sfd1CheckBusFifoEmpty <= \^sfd1checkbusfifoempty\;
startReadDataNib <= \^startreaddatanib\;
startReadDestAdrNib <= \^startreaddestadrnib\;
IP2INTC_IRPT_REG_I_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AA808080"
)
port map (
I0 => p_5_in(0),
I1 => p_9_in(0),
I2 => \^rx_done_d1_i\,
I3 => STATE17A,
I4 => tx_intr_en_reg(0),
O => D_5
);
\Mac_addr_ram_addr_rd[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFAABA"
)
port map (
I0 => D10_out,
I1 => rxBusFifoRdAck,
I2 => \^startreaddestadrnib\,
I3 => Q(0),
I4 => \rdDestAddrNib_D_t_q[0]_i_1_n_0\,
O => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
\Mac_addr_ram_addr_rd[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"08A2"
)
port map (
I0 => rdDestAddrNib_D_t(0),
I1 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
I2 => rdDestAddrNib_D_t(3),
I3 => rdDestAddrNib_D_t(1),
O => mac_addr_ram_addr_rd_D(0)
);
\Mac_addr_ram_addr_rd[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"23222022"
)
port map (
I0 => rdDestAddrNib_D_t(1),
I1 => \Mac_addr_ram_addr_rd[1]_i_2_n_0\,
I2 => rdDestAddrNib_D_t(3),
I3 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
I4 => rdDestAddrNib_D_t(0),
O => mac_addr_ram_addr_rd_D(1)
);
\Mac_addr_ram_addr_rd[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"C8C8C8C8C8C808C8"
)
port map (
I0 => \rdDestAddrNib_D_t_q[0]_i_5_n_0\,
I1 => rdDestAddrNib_D_t_q(0),
I2 => rdDestAddrNib_D_t_q(1),
I3 => ram_empty_i_reg,
I4 => rdDestAddrNib_D_t_q(2),
I5 => rdDestAddrNib_D_t_q(3),
O => \Mac_addr_ram_addr_rd[1]_i_2_n_0\
);
\Mac_addr_ram_addr_rd[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0055FC00"
)
port map (
I0 => \Mac_addr_ram_addr_rd[1]_i_2_n_0\,
I1 => rdDestAddrNib_D_t(0),
I2 => rdDestAddrNib_D_t(1),
I3 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
I4 => rdDestAddrNib_D_t(3),
O => mac_addr_ram_addr_rd_D(2)
);
\Mac_addr_ram_addr_rd[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E0EF"
)
port map (
I0 => rdDestAddrNib_D_t(0),
I1 => rdDestAddrNib_D_t(1),
I2 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
I3 => \Mac_addr_ram_addr_rd[1]_i_2_n_0\,
I4 => rdDestAddrNib_D_t(3),
O => mac_addr_ram_addr_rd_D(3)
);
\Mac_addr_ram_addr_rd_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_addr_ram_addr_rd_D(0),
Q => \rdDestAddrNib_D_t_q_reg[1]_1\(3),
R => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
\Mac_addr_ram_addr_rd_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_addr_ram_addr_rd_D(1),
Q => \rdDestAddrNib_D_t_q_reg[1]_1\(2),
R => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
\Mac_addr_ram_addr_rd_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_addr_ram_addr_rd_D(2),
Q => \rdDestAddrNib_D_t_q_reg[1]_1\(1),
R => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
\Mac_addr_ram_addr_rd_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_addr_ram_addr_rd_D(3),
Q => \rdDestAddrNib_D_t_q_reg[1]_1\(0),
R => \Mac_addr_ram_addr_rd[0]_i_1_n_0\
);
RX_DONE_D1_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[4]\,
I1 => \pkt_length_cnt_reg_n_0_[6]\,
I2 => \pkt_length_cnt_reg_n_0_[5]\,
I3 => \pkt_length_cnt_reg_n_0_[3]\,
I4 => \pkt_length_cnt[3]_i_2_n_0\,
I5 => rxDone,
O => \^rx_done_d1_i\
);
\RX_PONG_REG_GEN.pong_rx_status_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFEFEFEFEF202020"
)
port map (
I0 => s_axi_wdata(0),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
I2 => \AXI4_LITE_IF_GEN.write_in_prog_reg\,
I3 => rx_pong_ping_l,
I4 => \^rx_done_d1_i\,
I5 => \RX_PONG_REG_GEN.pong_rx_status_reg_1\,
O => \RX_PONG_REG_GEN.pong_rx_status_reg\
);
busFifoData_is_5_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \gpr1.dout_i_reg[5]\,
Q => \^busfifodata_is_5_d1\,
R => SS(0)
);
checkingBroadcastAdr_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444454444"
)
port map (
I0 => \^rxcrcrst\,
I1 => checkingBroadcastAdr_reg,
I2 => checkingBroadcastAdr_reg_i_2_n_0,
I3 => checkingBroadcastAdr_reg_i_3_n_0,
I4 => rdDestAddrNib_D_t_q(3),
I5 => rdDestAddrNib_D_t_q(0),
O => checkingBroadcastAdr_reg_i_1_n_0
);
checkingBroadcastAdr_reg_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \emac_rx_rd_data_d1_reg[0]\(3),
I1 => \emac_rx_rd_data_d1_reg[0]\(0),
I2 => \emac_rx_rd_data_d1_reg[0]\(1),
I3 => \emac_rx_rd_data_d1_reg[0]\(2),
O => checkingBroadcastAdr_reg_i_2_n_0
);
checkingBroadcastAdr_reg_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rdDestAddrNib_D_t_q(2),
I1 => rdDestAddrNib_D_t_q(1),
O => checkingBroadcastAdr_reg_i_3_n_0
);
checkingBroadcastAdr_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => checkingBroadcastAdr_reg_i_1_n_0,
Q => checkingBroadcastAdr_reg,
R => SS(0)
);
\crc_local[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => rxAbortRst,
I1 => s_axi_aresetn,
I2 => \^rxcrcrst\,
O => \crc_local_reg[31]\(0)
);
crcokdelay: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D,
Q => \^crcokr1\,
R => crcokdelay_0
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555515"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => \^rxcrcen_d1_reg\,
I2 => \gv.ram_valid_d1_i_3_n_0\,
I3 => \^rxcrcrst\,
I4 => rxDone,
I5 => rxBusFifoRdAck,
O => E(0)
);
\gv.ram_valid_d1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555515"
)
port map (
I0 => \out\,
I1 => \^rxcrcen_d1_reg\,
I2 => \gv.ram_valid_d1_i_3_n_0\,
I3 => \^rxcrcrst\,
I4 => rxDone,
I5 => rxBusFifoRdAck,
O => ram_valid_i
);
\gv.ram_valid_d1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => rdDestAddrNib_D_t_q(3),
I1 => rdDestAddrNib_D_t_q(2),
I2 => rdDestAddrNib_D_t_q(1),
I3 => rdDestAddrNib_D_t_q(0),
O => \^rxcrcen_d1_reg\
);
\gv.ram_valid_d1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^sfd1checkbusfifoempty\,
I1 => \^startreaddestadrnib\,
I2 => \^startreaddatanib\,
O => \gv.ram_valid_d1_i_3_n_0\
);
ping_rx_status_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"BBBB8B88"
)
port map (
I0 => s_axi_wdata(0),
I1 => rx_intr_en0,
I2 => rx_pong_ping_l,
I3 => \^rx_done_d1_i\,
I4 => ping_rx_status_reg_0,
O => ping_rx_status_reg
);
\pkt_length_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4F444444"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[0]\,
I1 => \pkt_length_cnt[2]_i_2_n_0\,
I2 => Q(0),
I3 => \^startreaddestadrnib\,
I4 => rxBusFifoRdAck,
O => \pkt_length_cnt[0]_i_1_n_0\
);
\pkt_length_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"90FF909090909090"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[1]\,
I1 => \pkt_length_cnt_reg_n_0_[0]\,
I2 => \pkt_length_cnt[2]_i_2_n_0\,
I3 => Q(0),
I4 => \^startreaddestadrnib\,
I5 => rxBusFifoRdAck,
O => \pkt_length_cnt[1]_i_1_n_0\
);
\pkt_length_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFA900"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[2]\,
I1 => \pkt_length_cnt_reg_n_0_[0]\,
I2 => \pkt_length_cnt_reg_n_0_[1]\,
I3 => \pkt_length_cnt[2]_i_2_n_0\,
I4 => goto_readDestAdrNib1,
O => \pkt_length_cnt[2]_i_1_n_0\
);
\pkt_length_cnt[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[4]\,
I1 => \pkt_length_cnt_reg_n_0_[6]\,
I2 => \pkt_length_cnt_reg_n_0_[5]\,
I3 => \pkt_length_cnt_reg_n_0_[3]\,
I4 => \pkt_length_cnt_reg_n_0_[1]\,
I5 => \pkt_length_cnt_reg_n_0_[2]\,
O => \pkt_length_cnt[2]_i_2_n_0\
);
\pkt_length_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF66666662"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[3]\,
I1 => \pkt_length_cnt[3]_i_2_n_0\,
I2 => \pkt_length_cnt_reg_n_0_[5]\,
I3 => \pkt_length_cnt_reg_n_0_[6]\,
I4 => \pkt_length_cnt_reg_n_0_[4]\,
I5 => goto_readDestAdrNib1,
O => \pkt_length_cnt[3]_i_1_n_0\
);
\pkt_length_cnt[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[0]\,
I1 => \pkt_length_cnt_reg_n_0_[1]\,
I2 => \pkt_length_cnt_reg_n_0_[2]\,
O => \pkt_length_cnt[3]_i_2_n_0\
);
\pkt_length_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF6662"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[4]\,
I1 => \pkt_length_cnt[6]_i_4_n_0\,
I2 => \pkt_length_cnt_reg_n_0_[6]\,
I3 => \pkt_length_cnt_reg_n_0_[5]\,
I4 => goto_readDestAdrNib1,
O => \pkt_length_cnt[4]_i_1_n_0\
);
\pkt_length_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFCC2C"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[6]\,
I1 => \pkt_length_cnt_reg_n_0_[5]\,
I2 => \pkt_length_cnt[6]_i_4_n_0\,
I3 => \pkt_length_cnt_reg_n_0_[4]\,
I4 => goto_readDestAdrNib1,
O => \pkt_length_cnt[5]_i_1_n_0\
);
\pkt_length_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => preamble_error_reg,
I1 => s_axi_aresetn,
O => pkt_length_cnt0
);
\pkt_length_cnt[6]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD50000"
)
port map (
I0 => \^rxcrcen_d1_reg\,
I1 => \^startreaddatanib\,
I2 => Q(1),
I3 => \^startreaddestadrnib\,
I4 => rxBusFifoRdAck,
O => \pkt_length_cnt[6]_i_2_n_0\
);
\pkt_length_cnt[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFB00"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[4]\,
I1 => \pkt_length_cnt[6]_i_4_n_0\,
I2 => \pkt_length_cnt_reg_n_0_[5]\,
I3 => \pkt_length_cnt_reg_n_0_[6]\,
I4 => goto_readDestAdrNib1,
O => \pkt_length_cnt[6]_i_3_n_0\
);
\pkt_length_cnt[6]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \pkt_length_cnt_reg_n_0_[2]\,
I1 => \pkt_length_cnt_reg_n_0_[1]\,
I2 => \pkt_length_cnt_reg_n_0_[0]\,
I3 => \pkt_length_cnt_reg_n_0_[3]\,
O => \pkt_length_cnt[6]_i_4_n_0\
);
\pkt_length_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[0]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[0]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[1]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[1]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[2]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[2]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[3]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[3]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[4]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[4]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[5]_i_1_n_0\,
Q => \pkt_length_cnt_reg_n_0_[5]\,
R => pkt_length_cnt0
);
\pkt_length_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \pkt_length_cnt[6]_i_2_n_0\,
D => \pkt_length_cnt[6]_i_3_n_0\,
Q => \pkt_length_cnt_reg_n_0_[6]\,
R => pkt_length_cnt0
);
preamble: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gpr1.dout_i_reg[2]\,
Q => preamble_error_reg,
R => SS(0)
);
\rdDestAddrNib_D_t_q[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => \^rx_start\,
I1 => \^busfifodata_is_5_d1\,
I2 => Q(2),
I3 => \gpr1.dout_i_reg[1]\,
I4 => s_axi_aresetn,
O => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
\rdDestAddrNib_D_t_q[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"30F0BFF03000BF00"
)
port map (
I0 => \rdDestAddrNib_D_t_q[0]_i_3_n_0\,
I1 => \rdDestAddrNib_D_t_q[0]_i_4_n_0\,
I2 => rdDestAddrNib_D_t_q(1),
I3 => rdDestAddrNib_D_t_q(0),
I4 => \gpr1.dout_i_reg[1]_0\,
I5 => \rdDestAddrNib_D_t_q[0]_i_5_n_0\,
O => rdDestAddrNib_D_t(0)
);
\rdDestAddrNib_D_t_q[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^rddestaddrnib_d_t_q_reg[1]_0\,
I1 => rxBusFifoRdAck,
O => \rdDestAddrNib_D_t_q[0]_i_3_n_0\
);
\rdDestAddrNib_D_t_q[0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rdDestAddrNib_D_t_q(3),
I1 => rdDestAddrNib_D_t_q(2),
O => \rdDestAddrNib_D_t_q[0]_i_4_n_0\
);
\rdDestAddrNib_D_t_q[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000E00000000000"
)
port map (
I0 => \^rxcrcen_d1_reg\,
I1 => Q(1),
I2 => rdDestAddrNib_D_t_q(2),
I3 => rxBusFifoRdAck,
I4 => \^rddestaddrnib_d_t_q_reg[1]_0\,
I5 => rdDestAddrNib_D_t_q(3),
O => \rdDestAddrNib_D_t_q[0]_i_5_n_0\
);
\rdDestAddrNib_D_t_q[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"80B0808080B08F8F"
)
port map (
I0 => \rdDestAddrNib_D_t_q[1]_i_2_n_0\,
I1 => rdDestAddrNib_D_t_q(0),
I2 => rdDestAddrNib_D_t_q(1),
I3 => \gpr1.dout_i_reg[1]_0\,
I4 => \rdDestAddrNib_D_t_q[1]_i_3_n_0\,
I5 => \rdDestAddrNib_D_t_q[1]_i_4_n_0\,
O => rdDestAddrNib_D_t(1)
);
\rdDestAddrNib_D_t_q[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBB010FFFFFFFF"
)
port map (
I0 => \^rddestaddrnib_d_t_q_reg[1]_0\,
I1 => rxBusFifoRdAck,
I2 => Q(1),
I3 => \out\,
I4 => \^rxcrcen_d1_reg\,
I5 => \rdDestAddrNib_D_t_q[0]_i_4_n_0\,
O => \rdDestAddrNib_D_t_q[1]_i_2_n_0\
);
\rdDestAddrNib_D_t_q[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => rdDestAddrNib_D_t_q(3),
I1 => \^rddestaddrnib_d_t_q_reg[1]_0\,
I2 => rxBusFifoRdAck,
I3 => rdDestAddrNib_D_t_q(2),
O => \rdDestAddrNib_D_t_q[1]_i_3_n_0\
);
\rdDestAddrNib_D_t_q[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => Q(1),
I1 => rdDestAddrNib_D_t_q(0),
I2 => rdDestAddrNib_D_t_q(1),
I3 => rdDestAddrNib_D_t_q(2),
I4 => rdDestAddrNib_D_t_q(3),
O => \rdDestAddrNib_D_t_q[1]_i_4_n_0\
);
\rdDestAddrNib_D_t_q[2]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \rdDestAddrNib_D_t_q[2]_i_2_n_0\,
O => rdDestAddrNib_D_t(2)
);
\rdDestAddrNib_D_t_q[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"33333333BBBBFBCB"
)
port map (
I0 => \gpr1.dout_i_reg[1]_0\,
I1 => rdDestAddrNib_D_t_q(2),
I2 => rdDestAddrNib_D_t_q(3),
I3 => \rdDestAddrNib_D_t_q[1]_i_4_n_0\,
I4 => \rdDestAddrNib_D_t_q[0]_i_3_n_0\,
I5 => \rdDestAddrNib_D_t_q[3]_i_3_n_0\,
O => \rdDestAddrNib_D_t_q[2]_i_2_n_0\
);
\rdDestAddrNib_D_t_q[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDD03003330"
)
port map (
I0 => ram_empty_i_reg,
I1 => \rdDestAddrNib_D_t_q[3]_i_3_n_0\,
I2 => \rdDestAddrNib_D_t_q[3]_i_4_n_0\,
I3 => goto_readDestAdrNib1,
I4 => \rdDestAddrNib_D_t_q[3]_i_6_n_0\,
I5 => rdDestAddrNib_D_t_q(3),
O => rdDestAddrNib_D_t(3)
);
\rdDestAddrNib_D_t_q[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rdDestAddrNib_D_t_q(0),
I1 => rdDestAddrNib_D_t_q(1),
O => \rdDestAddrNib_D_t_q[3]_i_3_n_0\
);
\rdDestAddrNib_D_t_q[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => rdDestAddrNib_D_t_q(0),
I1 => rdDestAddrNib_D_t_q(1),
I2 => rdDestAddrNib_D_t_q(2),
O => \rdDestAddrNib_D_t_q[3]_i_4_n_0\
);
\rdDestAddrNib_D_t_q[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF1F"
)
port map (
I0 => \^rxcrcen_d1_reg\,
I1 => Q(1),
I2 => rxBusFifoRdAck,
I3 => \^rddestaddrnib_d_t_q_reg[1]_0\,
O => \rdDestAddrNib_D_t_q[3]_i_6_n_0\
);
\rdDestAddrNib_D_t_q_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdDestAddrNib_D_t(0),
Q => rdDestAddrNib_D_t_q(0),
R => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
\rdDestAddrNib_D_t_q_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdDestAddrNib_D_t(1),
Q => rdDestAddrNib_D_t_q(1),
R => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
\rdDestAddrNib_D_t_q_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdDestAddrNib_D_t(2),
Q => rdDestAddrNib_D_t_q(2),
R => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
\rdDestAddrNib_D_t_q_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rdDestAddrNib_D_t(3),
Q => rdDestAddrNib_D_t_q(3),
R => \rdDestAddrNib_D_t_q[0]_i_1_n_0\
);
rxCrcEn_d1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAA80AA"
)
port map (
I0 => rxBusFifoRdAck,
I1 => Q(1),
I2 => \^startreaddatanib\,
I3 => \^rxcrcen_d1_reg\,
I4 => \^startreaddestadrnib\,
O => rxCrcEn
);
\rxbuffer_addr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^rx_start\,
I1 => s_axi_aresetn,
O => \rxbuffer_addr_reg[0]\
);
\rxbuffer_addr[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => rxBusFifoRdAck,
I1 => \^startreaddatanib\,
I2 => \^rxcrcen_d1_reg\,
I3 => \^startreaddestadrnib\,
O => \^rx_addr_en\
);
state0a: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D10_out,
Q => \^rxcrcrst\,
S => SS(0)
);
state0a_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0EFF0EFFFFFF0E"
)
port map (
I0 => \^rx_start\,
I1 => waitForSfd1,
I2 => \gpr1.dout_i_reg[1]\,
I3 => state0a_i_3_n_0,
I4 => \^rxcrcrst\,
I5 => \gv.ram_valid_d1_reg\,
O => D10_out
);
state0a_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF8"
)
port map (
I0 => waitForSfd1,
I1 => Q(2),
I2 => rxAbortRst,
I3 => rxDone,
O => state0a_i_3_n_0
);
state17a_RnM: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D11_out,
Q => \^startreaddatanib\,
R => SS(0)
);
state17a_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000200000000000"
)
port map (
I0 => rdDestAddrNib_D_t_q(3),
I1 => \rdDestAddrNib_D_t_q[0]_i_3_n_0\,
I2 => rdDestAddrNib_D_t_q(2),
I3 => Q(1),
I4 => rdDestAddrNib_D_t_q(1),
I5 => rdDestAddrNib_D_t_q(0),
O => state17a_0
);
state18a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D12_out,
Q => crcCheck,
R => SS(0)
);
state18a_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"DCDCDCD0"
)
port map (
I0 => Q(1),
I1 => Q(0),
I2 => \^startreaddatanib\,
I3 => \^startreaddestadrnib\,
I4 => \^sfd1checkbusfifoempty\,
O => D12_out
);
state1a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RX_PONG_REG_GEN.pong_rx_status_reg_0\,
Q => waitForSfd1,
R => SS(0)
);
state20a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D18_out,
Q => rxDone,
R => SS(0)
);
state20a_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^crcokr1\,
I1 => crcCheck,
O => D18_out
);
state22a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => state22a_i_1_n_0,
Q => rxAbortRst,
R => SS(0)
);
state22a_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFAE"
)
port map (
I0 => \gpr1.dout_i_reg[1]_0\,
I1 => crcCheck,
I2 => \^crcokr1\,
I3 => preamble_error_reg,
O => state22a_i_1_n_0
);
state22a_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FAFBFAFBFAFB4040"
)
port map (
I0 => \^rxcrcrst\,
I1 => checkingBroadcastAdr_reg,
I2 => checkingBroadcastAdr_reg_i_2_n_0,
I3 => state22a_i_4_n_0,
I4 => \emac_rx_rd_data_d1_reg[2]\,
I5 => \emac_rx_rd_data_d1_reg[1]\,
O => \^rddestaddrnib_d_t_q_reg[1]_0\
);
state22a_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => rdDestAddrNib_D_t_q(0),
I1 => rdDestAddrNib_D_t_q(3),
I2 => rdDestAddrNib_D_t_q(1),
I3 => rdDestAddrNib_D_t_q(2),
O => state22a_i_4_n_0
);
state2a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D5_out,
Q => \^sfd1checkbusfifoempty\,
R => SS(0)
);
state2a_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^rx_start\,
I1 => waitForSfd1,
O => state2a_0
);
state3a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D13_out,
Q => \^rx_start\,
R => SS(0)
);
state4a: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D6_out,
Q => \^startreaddestadrnib\,
R => SS(0)
);
xpm_memory_base_inst_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0EFF"
)
port map (
I0 => \^rxcrcrst\,
I1 => \^rx_addr_en\,
I2 => rx_pong_ping_l,
I3 => s_axi_aresetn,
O => ena
);
\xpm_memory_base_inst_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E0FF"
)
port map (
I0 => \^rxcrcrst\,
I1 => \^rx_addr_en\,
I2 => rx_pong_ping_l,
I3 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg\
);
xpm_memory_base_inst_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => s_axi_aresetn,
I1 => \^startreaddatanib\,
I2 => \^rxcrcen_d1_reg\,
I3 => \^startreaddestadrnib\,
O => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_tx_statemachine is
port (
loopback_en_reg : out STD_LOGIC;
transmit_start_reg_reg_0 : out STD_LOGIC;
ldLngthCntr : out STD_LOGIC;
enblPreamble : out STD_LOGIC;
checkBusFifoFull : out STD_LOGIC;
enblData : out STD_LOGIC;
checkBusFifoFullCrc : out STD_LOGIC;
enblCRC : out STD_LOGIC;
waitFifoEmpty : out STD_LOGIC;
STATE24A_0 : out STD_LOGIC;
tx_en_i : out STD_LOGIC;
mac_addr_ram_we : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\emac_tx_wr_data_d1_reg[3]\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[2]\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[1]\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[0]\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[0]_0\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[1]_0\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[3]_0\ : out STD_LOGIC;
\emac_tx_wr_data_d1_reg[2]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
CE : out STD_LOGIC;
S : out STD_LOGIC;
\txNibbleCnt_pad_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
txComboBusFifoWrCntRst : out STD_LOGIC;
axi_phy_tx_en_i_p0 : out STD_LOGIC;
CE_0 : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
txCrcEn : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ : out STD_LOGIC;
\PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ : out STD_LOGIC;
\PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ : out STD_LOGIC;
emac_tx_wr_i : out STD_LOGIC;
S_1 : out STD_LOGIC;
\PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ : out STD_LOGIC;
\PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ : out STD_LOGIC;
txComboNibbleCntRst : out STD_LOGIC;
Rst0 : out STD_LOGIC;
\txbuffer_addr_reg[0]\ : out STD_LOGIC;
\PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ : out STD_LOGIC;
\status_reg_reg[5]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
\status_reg_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
loopback_en_reg_0 : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : out STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : out STD_LOGIC;
tx_addr_en : out STD_LOGIC;
mac_addr_ram_addr_wr : out STD_LOGIC_VECTOR ( 0 to 3 );
s_axi_aclk : in STD_LOGIC;
D13_out : in STD_LOGIC;
D21_out : in STD_LOGIC;
\PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\ : in STD_LOGIC;
\PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\ : in STD_LOGIC;
D18_out : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
emac_tx_wr_d1 : in STD_LOGIC;
txCrcEn_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
douta : in STD_LOGIC_VECTOR ( 3 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\txNibbleCnt_pad_reg[11]_0\ : in STD_LOGIC;
\txNibbleCnt_pad_reg[11]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\tx_packet_length_reg[10]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
txNibbleCnt_pad0 : in STD_LOGIC_VECTOR ( 10 downto 0 );
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\tx_packet_length_reg[9]\ : in STD_LOGIC;
\out\ : in STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_1\ : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC;
STATE14A_0 : in STD_LOGIC;
currentTxBusFifoWrCnt : in STD_LOGIC_VECTOR ( 3 downto 0 );
crcCnt : in STD_LOGIC_VECTOR ( 0 to 3 );
tx_done_d2 : in STD_LOGIC;
ping_mac_program_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
p_17_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\TX_PONG_REG_GEN.pong_mac_program_reg\ : in STD_LOGIC;
p_15_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_2\ : in STD_LOGIC;
txfifo_empty : in STD_LOGIC;
\thisState_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
rx_pong_ping_l : in STD_LOGIC;
rx_done_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_intr_en0 : in STD_LOGIC;
loopback_en_reg_1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_tx_statemachine : entity is "tx_statemachine";
end system_axi_ethernetlite_0_0_tx_statemachine;
architecture STRUCTURE of system_axi_ethernetlite_0_0_tx_statemachine is
signal D11_out : STD_LOGIC;
signal D12_out : STD_LOGIC;
signal D14_out : STD_LOGIC;
signal D15_out : STD_LOGIC;
signal D16_out : STD_LOGIC;
signal D17_out : STD_LOGIC;
signal D19_out : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[0]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[0]_i_2_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[0]_i_3_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[1]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[2]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[2]_i_2_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[2]_i_3_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[3]_i_1_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[3]_i_2_n_0\ : STD_LOGIC;
signal \Mac_addr_ram_addr_wr[3]_i_3_n_0\ : STD_LOGIC;
signal Mac_addr_ram_we0 : STD_LOGIC;
signal Mac_addr_ram_we_i_2_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_3_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_4_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_5_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_6_n_0 : STD_LOGIC;
signal Mac_addr_ram_we_i_7_n_0 : STD_LOGIC;
signal STATE0A_i_2_n_0 : STD_LOGIC;
signal \^state24a_0\ : STD_LOGIC;
signal STATE26A_i_1_n_0 : STD_LOGIC;
signal axi_fifo_tx_en : STD_LOGIC;
signal busFifoWrCntRst_reg : STD_LOGIC;
signal \^checkbusfifofull\ : STD_LOGIC;
signal \^checkbusfifofullcrc\ : STD_LOGIC;
signal checkBusFifoFullSFD : STD_LOGIC;
signal checkCrc : STD_LOGIC;
signal chgMacAdr1 : STD_LOGIC;
signal chgMacAdr10 : STD_LOGIC;
signal chgMacAdr11 : STD_LOGIC;
signal chgMacAdr12 : STD_LOGIC;
signal chgMacAdr13 : STD_LOGIC;
signal chgMacAdr14 : STD_LOGIC;
signal chgMacAdr2 : STD_LOGIC;
signal chgMacAdr3 : STD_LOGIC;
signal chgMacAdr4 : STD_LOGIC;
signal chgMacAdr5 : STD_LOGIC;
signal chgMacAdr6 : STD_LOGIC;
signal chgMacAdr7 : STD_LOGIC;
signal chgMacAdr8 : STD_LOGIC;
signal chgMacAdr9 : STD_LOGIC;
signal \^enblcrc\ : STD_LOGIC;
signal \^enbldata\ : STD_LOGIC;
signal \^enblpreamble\ : STD_LOGIC;
signal enblSFD : STD_LOGIC;
signal \^ldlngthcntr\ : STD_LOGIC;
signal lngthDelay1 : STD_LOGIC;
signal lngthDelay2 : STD_LOGIC;
signal \^loopback_en_reg\ : STD_LOGIC;
signal mac_program_start : STD_LOGIC;
signal mac_program_start_reg : STD_LOGIC;
signal transmit_start : STD_LOGIC;
signal transmit_start_reg : STD_LOGIC;
signal \^transmit_start_reg_reg_0\ : STD_LOGIC;
signal txBusFifoWrCntRst : STD_LOGIC;
signal txDone2 : STD_LOGIC;
signal txDonePause : STD_LOGIC;
signal \^tx_en_i\ : STD_LOGIC;
signal txcrcen_d1_i_2_n_0 : STD_LOGIC;
signal \^waitfifoempty\ : STD_LOGIC;
signal xpm_memory_base_inst_i_4_n_0 : STD_LOGIC;
signal xpm_memory_base_inst_i_6_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[0]_i_2\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[0]_i_3\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[1]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[2]_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \Mac_addr_ram_addr_wr[3]_i_1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of Mac_addr_ram_we_i_1 : label is "soft_lutpair78";
attribute SOFT_HLUTNM of Mac_addr_ram_we_i_3 : label is "soft_lutpair63";
attribute SOFT_HLUTNM of Mac_addr_ram_we_i_5 : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_i_1__0\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \PERBIT_GEN[11].MULT_AND_i1_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1_i_1\ : label is "soft_lutpair66";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of STATE0A : label is "FDS";
attribute box_type : string;
attribute box_type of STATE0A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE10A : label is "FDR";
attribute box_type of STATE10A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE11A : label is "FDR";
attribute box_type of STATE11A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE12A : label is "FDR";
attribute box_type of STATE12A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE13A : label is "FDR";
attribute box_type of STATE13A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE14A : label is "FDR";
attribute box_type of STATE14A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE15A : label is "FDR";
attribute box_type of STATE15A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE16A : label is "FDR";
attribute box_type of STATE16A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE17A : label is "FDR";
attribute box_type of STATE17A : label is "PRIMITIVE";
attribute SOFT_HLUTNM of STATE17A_i_1 : label is "soft_lutpair76";
attribute XILINX_LEGACY_PRIM of STATE24A : label is "FDR";
attribute box_type of STATE24A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE25A : label is "FDR";
attribute box_type of STATE25A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE26A : label is "FDR";
attribute box_type of STATE26A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE27A : label is "FDR";
attribute box_type of STATE27A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE28A : label is "FDR";
attribute box_type of STATE28A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE29A : label is "FDR";
attribute box_type of STATE29A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE30A : label is "FDR";
attribute box_type of STATE30A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE31A : label is "FDR";
attribute box_type of STATE31A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE32A : label is "FDR";
attribute box_type of STATE32A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE33A : label is "FDR";
attribute box_type of STATE33A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE34A : label is "FDR";
attribute box_type of STATE34A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE35A : label is "FDR";
attribute box_type of STATE35A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE36A : label is "FDR";
attribute box_type of STATE36A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE37A : label is "FDR";
attribute box_type of STATE37A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE38A : label is "FDR";
attribute box_type of STATE38A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE39A : label is "FDR";
attribute box_type of STATE39A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE5A : label is "FDR";
attribute box_type of STATE5A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE6A : label is "FDR";
attribute box_type of STATE6A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE7A : label is "FDR";
attribute box_type of STATE7A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE8A : label is "FDR";
attribute box_type of STATE8A : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of STATE9A : label is "FDR";
attribute box_type of STATE9A : label is "PRIMITIVE";
attribute SOFT_HLUTNM of axi_phy_tx_en_i_p_i_1 : label is "soft_lutpair67";
attribute SOFT_HLUTNM of mac_program_start_reg_i_1 : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \nibData[31]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of pipeIt_i_1 : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \status_reg[0]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \status_reg[1]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \status_reg[2]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \status_reg[3]_i_1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \status_reg[4]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \status_reg[5]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \status_reg[5]_i_2\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of transmit_start_reg_i_1 : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \txNibbleCnt_pad[11]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \txNibbleCnt_pad[4]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \txNibbleCnt_pad[8]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \txNibbleCnt_pad[9]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \txbuffer_addr[11]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \txbuffer_addr[11]_i_2\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of txcrcen_d1_i_2 : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \xpm_memory_base_inst_i_1__2\ : label is "soft_lutpair77";
begin
STATE24A_0 <= \^state24a_0\;
checkBusFifoFull <= \^checkbusfifofull\;
checkBusFifoFullCrc <= \^checkbusfifofullcrc\;
enblCRC <= \^enblcrc\;
enblData <= \^enbldata\;
enblPreamble <= \^enblpreamble\;
ldLngthCntr <= \^ldlngthcntr\;
loopback_en_reg <= \^loopback_en_reg\;
transmit_start_reg_reg_0 <= \^transmit_start_reg_reg_0\;
tx_en_i <= \^tx_en_i\;
waitFifoEmpty <= \^waitfifoempty\;
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F5F7FFF7"
)
port map (
I0 => \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
I1 => douta(3),
I2 => \^loopback_en_reg\,
I3 => tx_pong_ping_l,
I4 => \gen_wr_b.gen_word_wide.mem_reg_1\(3),
I5 => enblSFD,
O => \emac_tx_wr_data_d1_reg[0]_0\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^enbldata\,
I1 => \txNibbleCnt_pad_reg[11]_0\,
O => \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => Q(3),
O => \emac_tx_wr_data_d1_reg[0]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A2AAA2AAAAAAAA"
)
port map (
I0 => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
I1 => douta(2),
I2 => \^loopback_en_reg\,
I3 => tx_pong_ping_l,
I4 => \gen_wr_b.gen_word_wide.mem_reg_1\(2),
I5 => \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
O => \emac_tx_wr_data_d1_reg[1]_0\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => enblSFD,
I1 => \^enblpreamble\,
O => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => Q(2),
O => \emac_tx_wr_data_d1_reg[1]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBBFFFFBFFF"
)
port map (
I0 => \txNibbleCnt_pad_reg[11]_0\,
I1 => \^enbldata\,
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(1),
I3 => tx_pong_ping_l,
I4 => \^loopback_en_reg\,
I5 => douta(1),
O => \emac_tx_wr_data_d1_reg[2]_0\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => Q(1),
O => \emac_tx_wr_data_d1_reg[2]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A2AAA2AAAAAAAA"
)
port map (
I0 => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
I1 => douta(0),
I2 => \^loopback_en_reg\,
I3 => tx_pong_ping_l,
I4 => \gen_wr_b.gen_word_wide.mem_reg_1\(0),
I5 => \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2_n_0\,
O => \emac_tx_wr_data_d1_reg[3]_0\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => Q(0),
O => \emac_tx_wr_data_d1_reg[3]\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1110"
)
port map (
I0 => \^state24a_0\,
I1 => \^loopback_en_reg\,
I2 => axi_fifo_tx_en,
I3 => \^enblpreamble\,
O => \^tx_en_i\
);
IP2INTC_IRPT_REG_I_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^transmit_start_reg_reg_0\
);
\Mac_addr_ram_addr_wr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFE"
)
port map (
I0 => chgMacAdr10,
I1 => chgMacAdr11,
I2 => chgMacAdr13,
I3 => chgMacAdr12,
I4 => \Mac_addr_ram_addr_wr[0]_i_2_n_0\,
I5 => \Mac_addr_ram_addr_wr[0]_i_3_n_0\,
O => \Mac_addr_ram_addr_wr[0]_i_1_n_0\
);
\Mac_addr_ram_addr_wr[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => chgMacAdr7,
I1 => chgMacAdr6,
I2 => chgMacAdr9,
I3 => chgMacAdr8,
O => \Mac_addr_ram_addr_wr[0]_i_2_n_0\
);
\Mac_addr_ram_addr_wr[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => chgMacAdr4,
I1 => chgMacAdr5,
I2 => Mac_addr_ram_we_i_3_n_0,
I3 => chgMacAdr2,
I4 => chgMacAdr3,
O => \Mac_addr_ram_addr_wr[0]_i_3_n_0\
);
\Mac_addr_ram_addr_wr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => chgMacAdr8,
I1 => chgMacAdr9,
I2 => chgMacAdr6,
I3 => chgMacAdr7,
I4 => \Mac_addr_ram_addr_wr[0]_i_3_n_0\,
O => \Mac_addr_ram_addr_wr[1]_i_1_n_0\
);
\Mac_addr_ram_addr_wr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFFF01"
)
port map (
I0 => chgMacAdr7,
I1 => chgMacAdr6,
I2 => \Mac_addr_ram_addr_wr[2]_i_2_n_0\,
I3 => chgMacAdr5,
I4 => chgMacAdr4,
I5 => \Mac_addr_ram_addr_wr[2]_i_3_n_0\,
O => \Mac_addr_ram_addr_wr[2]_i_1_n_0\
);
\Mac_addr_ram_addr_wr[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1110111011101111"
)
port map (
I0 => chgMacAdr9,
I1 => chgMacAdr8,
I2 => chgMacAdr10,
I3 => chgMacAdr11,
I4 => chgMacAdr13,
I5 => chgMacAdr12,
O => \Mac_addr_ram_addr_wr[2]_i_2_n_0\
);
\Mac_addr_ram_addr_wr[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFEFFFF"
)
port map (
I0 => chgMacAdr3,
I1 => chgMacAdr2,
I2 => STATE0A_i_2_n_0,
I3 => txDonePause,
I4 => s_axi_aresetn,
O => \Mac_addr_ram_addr_wr[2]_i_3_n_0\
);
\Mac_addr_ram_addr_wr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \Mac_addr_ram_addr_wr[3]_i_2_n_0\,
I1 => Mac_addr_ram_we_i_3_n_0,
I2 => chgMacAdr2,
O => \Mac_addr_ram_addr_wr[3]_i_1_n_0\
);
\Mac_addr_ram_addr_wr[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BABBBABBBABBBABA"
)
port map (
I0 => chgMacAdr3,
I1 => chgMacAdr4,
I2 => chgMacAdr5,
I3 => chgMacAdr6,
I4 => chgMacAdr7,
I5 => \Mac_addr_ram_addr_wr[3]_i_3_n_0\,
O => \Mac_addr_ram_addr_wr[3]_i_2_n_0\
);
\Mac_addr_ram_addr_wr[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFF00F2"
)
port map (
I0 => chgMacAdr13,
I1 => chgMacAdr12,
I2 => chgMacAdr11,
I3 => chgMacAdr10,
I4 => chgMacAdr9,
I5 => chgMacAdr8,
O => \Mac_addr_ram_addr_wr[3]_i_3_n_0\
);
\Mac_addr_ram_addr_wr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Mac_addr_ram_addr_wr[0]_i_1_n_0\,
Q => mac_addr_ram_addr_wr(0),
R => '0'
);
\Mac_addr_ram_addr_wr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Mac_addr_ram_addr_wr[1]_i_1_n_0\,
Q => mac_addr_ram_addr_wr(1),
R => '0'
);
\Mac_addr_ram_addr_wr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Mac_addr_ram_addr_wr[2]_i_1_n_0\,
Q => mac_addr_ram_addr_wr(2),
R => '0'
);
\Mac_addr_ram_addr_wr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Mac_addr_ram_addr_wr[3]_i_1_n_0\,
Q => mac_addr_ram_addr_wr(3),
R => '0'
);
Mac_addr_ram_we_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Mac_addr_ram_we_i_2_n_0,
I1 => Mac_addr_ram_we_i_3_n_0,
O => Mac_addr_ram_we0
);
Mac_addr_ram_we_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFEFFFFFFFFF"
)
port map (
I0 => Mac_addr_ram_we_i_4_n_0,
I1 => Mac_addr_ram_we_i_5_n_0,
I2 => Mac_addr_ram_we_i_6_n_0,
I3 => chgMacAdr3,
I4 => chgMacAdr2,
I5 => Mac_addr_ram_we_i_7_n_0,
O => Mac_addr_ram_we_i_2_n_0
);
Mac_addr_ram_we_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => s_axi_aresetn,
I1 => txDonePause,
I2 => STATE0A_i_2_n_0,
O => Mac_addr_ram_we_i_3_n_0
);
Mac_addr_ram_we_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => chgMacAdr12,
I1 => chgMacAdr13,
I2 => chgMacAdr11,
I3 => chgMacAdr10,
O => Mac_addr_ram_we_i_4_n_0
);
Mac_addr_ram_we_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => chgMacAdr5,
I1 => chgMacAdr4,
O => Mac_addr_ram_we_i_5_n_0
);
Mac_addr_ram_we_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => chgMacAdr8,
I1 => chgMacAdr9,
O => Mac_addr_ram_we_i_6_n_0
);
Mac_addr_ram_we_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => chgMacAdr6,
I1 => chgMacAdr7,
O => Mac_addr_ram_we_i_7_n_0
);
Mac_addr_ram_we_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Mac_addr_ram_we0,
Q => mac_addr_ram_we,
R => '0'
);
\PERBIT_GEN[0].XORCY_i1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^enblcrc\,
I1 => crcCnt(0),
O => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[10].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => currentTxBusFifoWrCnt(1),
I1 => \^enbldata\,
I2 => \^enblpreamble\,
I3 => enblSFD,
I4 => \^enblcrc\,
O => \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF2FFFF"
)
port map (
I0 => busFifoWrCntRst_reg,
I1 => \^enblpreamble\,
I2 => \^loopback_en_reg\,
I3 => \^state24a_0\,
I4 => s_axi_aresetn,
I5 => txDonePause,
O => txComboBusFifoWrCntRst
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => \^loopback_en_reg\,
I1 => s_axi_aresetn,
I2 => txDonePause,
O => txComboNibbleCntRst
);
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^enbldata\,
I1 => enblSFD,
O => CE
);
\PERBIT_GEN[11].MULT_AND_i1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^enbldata\,
I1 => \^enblpreamble\,
I2 => enblSFD,
I3 => \^enblcrc\,
O => emac_tx_wr_i
);
\PERBIT_GEN[11].MUXCY_i1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^enbldata\,
I1 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\(0),
O => S
);
\PERBIT_GEN[11].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => currentTxBusFifoWrCnt(0),
I1 => \^enbldata\,
I2 => \^enblpreamble\,
I3 => enblSFD,
I4 => \^enblcrc\,
O => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\
);
\PERBIT_GEN[1].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^enblcrc\,
I1 => crcCnt(1),
O => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[2].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^enblcrc\,
I1 => crcCnt(2),
O => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\
);
\PERBIT_GEN[3].FF_RST0_GEN.FDRE_i1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFAB"
)
port map (
I0 => \^enblcrc\,
I1 => \^enblpreamble\,
I2 => axi_fifo_tx_en,
I3 => \^loopback_en_reg\,
I4 => \^state24a_0\,
O => CE_0
);
\PERBIT_GEN[3].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^enblcrc\,
I1 => crcCnt(3),
O => S_1
);
\PERBIT_GEN[8].XORCY_i1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => currentTxBusFifoWrCnt(3),
I1 => \^enbldata\,
I2 => \^enblpreamble\,
I3 => enblSFD,
I4 => \^enblcrc\,
O => \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\
);
\PERBIT_GEN[9].MUXCY_i1_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => currentTxBusFifoWrCnt(2),
I1 => \^enbldata\,
I2 => \^enblpreamble\,
I3 => enblSFD,
I4 => \^enblcrc\,
O => \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\
);
STATE0A: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => \^loopback_en_reg\,
S => \^transmit_start_reg_reg_0\
);
STATE0A_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => txDonePause,
I1 => STATE0A_i_2_n_0,
O => D_0
);
STATE0A_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000088808CC08CC"
)
port map (
I0 => tx_done_d2,
I1 => \^loopback_en_reg\,
I2 => ping_mac_program_reg(0),
I3 => p_17_in(0),
I4 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I5 => p_15_in(0),
O => STATE0A_i_2_n_0
);
STATE10A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D15_out,
Q => enblSFD,
R => \^transmit_start_reg_reg_0\
);
STATE10A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \out\,
I1 => checkBusFifoFullSFD,
I2 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_1\,
I3 => enblSFD,
O => D15_out
);
STATE11A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D16_out,
Q => \^checkbusfifofull\,
R => \^transmit_start_reg_reg_0\
);
STATE11A_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF444F444F444"
)
port map (
I0 => \PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\,
I1 => \^enbldata\,
I2 => \^checkbusfifofull\,
I3 => \out\,
I4 => enblSFD,
I5 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_1\,
O => D16_out
);
STATE12A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D21_out,
Q => \^enbldata\,
R => \^transmit_start_reg_reg_0\
);
STATE13A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\,
Q => checkCrc,
R => \^transmit_start_reg_reg_0\
);
STATE14A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D17_out,
Q => \^checkbusfifofullcrc\,
R => \^transmit_start_reg_reg_0\
);
STATE14A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF8"
)
port map (
I0 => \out\,
I1 => \^checkbusfifofullcrc\,
I2 => checkCrc,
I3 => \^enblcrc\,
O => D17_out
);
STATE15A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\,
Q => \^enblcrc\,
R => \^transmit_start_reg_reg_0\
);
STATE16A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D18_out,
Q => \^waitfifoempty\,
R => \^transmit_start_reg_reg_0\
);
STATE17A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D19_out,
Q => \^state24a_0\,
R => \^transmit_start_reg_reg_0\
);
STATE17A_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => chgMacAdr14,
I1 => txfifo_empty,
I2 => \^waitfifoempty\,
O => D19_out
);
STATE24A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \^state24a_0\,
Q => txDone2,
R => \^transmit_start_reg_reg_0\
);
STATE25A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => txDone2,
Q => txDonePause,
R => \^transmit_start_reg_reg_0\
);
STATE26A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => STATE26A_i_1_n_0,
Q => chgMacAdr1,
R => \^transmit_start_reg_reg_0\
);
STATE26A_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F8880000"
)
port map (
I0 => p_15_in(0),
I1 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I2 => p_17_in(0),
I3 => ping_mac_program_reg(0),
I4 => \^loopback_en_reg\,
I5 => mac_program_start_reg,
O => STATE26A_i_1_n_0
);
STATE27A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr1,
Q => chgMacAdr2,
R => \^transmit_start_reg_reg_0\
);
STATE28A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr2,
Q => chgMacAdr3,
R => \^transmit_start_reg_reg_0\
);
STATE29A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr3,
Q => chgMacAdr4,
R => \^transmit_start_reg_reg_0\
);
STATE30A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr4,
Q => chgMacAdr5,
R => \^transmit_start_reg_reg_0\
);
STATE31A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr5,
Q => chgMacAdr6,
R => \^transmit_start_reg_reg_0\
);
STATE32A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr6,
Q => chgMacAdr7,
R => \^transmit_start_reg_reg_0\
);
STATE33A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr7,
Q => chgMacAdr8,
R => \^transmit_start_reg_reg_0\
);
STATE34A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr8,
Q => chgMacAdr9,
R => \^transmit_start_reg_reg_0\
);
STATE35A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr9,
Q => chgMacAdr10,
R => \^transmit_start_reg_reg_0\
);
STATE36A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr10,
Q => chgMacAdr11,
R => \^transmit_start_reg_reg_0\
);
STATE37A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr11,
Q => chgMacAdr12,
R => \^transmit_start_reg_reg_0\
);
STATE38A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr12,
Q => chgMacAdr13,
R => \^transmit_start_reg_reg_0\
);
STATE39A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => chgMacAdr13,
Q => chgMacAdr14,
R => \^transmit_start_reg_reg_0\
);
STATE5A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D11_out,
Q => lngthDelay1,
R => \^transmit_start_reg_reg_0\
);
STATE5A_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => transmit_start,
I1 => \^loopback_en_reg\,
I2 => transmit_start_reg,
O => D11_out
);
STATE6A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => lngthDelay1,
Q => lngthDelay2,
R => \^transmit_start_reg_reg_0\
);
STATE7A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D12_out,
Q => \^ldlngthcntr\,
R => \^transmit_start_reg_reg_0\
);
STATE7A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BFAA"
)
port map (
I0 => lngthDelay1,
I1 => \thisState_reg[1]\(0),
I2 => \thisState_reg[1]\(1),
I3 => \^ldlngthcntr\,
O => D12_out
);
STATE8A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D13_out,
Q => \^enblpreamble\,
R => \^transmit_start_reg_reg_0\
);
STATE9A: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D14_out,
Q => checkBusFifoFullSFD,
R => \^transmit_start_reg_reg_0\
);
STATE9A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_2\,
I1 => \^enblpreamble\,
I2 => \out\,
I3 => checkBusFifoFullSFD,
O => D14_out
);
axi_phy_tx_en_i_p_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => axi_fifo_tx_en,
I1 => \^state24a_0\,
I2 => \^loopback_en_reg\,
O => axi_phy_tx_en_i_p0
);
busFifoWrCntRst_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"EFEE"
)
port map (
I0 => \^state24a_0\,
I1 => \^loopback_en_reg\,
I2 => \^enblpreamble\,
I3 => busFifoWrCntRst_reg,
O => txBusFifoWrCntRst
);
busFifoWrCntRst_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => txBusFifoWrCntRst,
Q => busFifoWrCntRst_reg,
R => \^transmit_start_reg_reg_0\
);
\gic0.gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555555554"
)
port map (
I0 => ram_full_fb_i_reg,
I1 => STATE14A_0,
I2 => \^enblcrc\,
I3 => enblSFD,
I4 => \^enblpreamble\,
I5 => \^enbldata\,
O => \gic0.gc0.count_reg[0]\(0)
);
loopback_en_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"BF80"
)
port map (
I0 => s_axi_wdata(0),
I1 => tx_intr_en0,
I2 => \^loopback_en_reg\,
I3 => loopback_en_reg_1,
O => loopback_en_reg_0
);
mac_program_start_reg_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => ping_mac_program_reg(0),
I1 => p_17_in(0),
I2 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I3 => p_15_in(0),
O => mac_program_start
);
mac_program_start_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => mac_program_start,
Q => mac_program_start_reg,
R => \^transmit_start_reg_reg_0\
);
\nibData[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF57"
)
port map (
I0 => s_axi_aresetn,
I1 => \^enblpreamble\,
I2 => axi_fifo_tx_en,
I3 => \^loopback_en_reg\,
I4 => \^state24a_0\,
O => SR(0)
);
\nibData[31]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAA8"
)
port map (
I0 => emac_tx_wr_d1,
I1 => \^checkbusfifofullcrc\,
I2 => \^enblcrc\,
I3 => txCrcEn_reg,
O => E(0)
);
phytx_en_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^tx_en_i\,
Q => axi_fifo_tx_en,
R => \^transmit_start_reg_reg_0\
);
pipeIt_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => txDonePause,
I1 => s_axi_aresetn,
O => Rst0
);
\status_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I1 => tx_pong_ping_l,
I2 => s_axi_aresetn,
I3 => \^state24a_0\,
O => \status_reg_reg[5]\(0)
);
\status_reg[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => ping_mac_program_reg(0),
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
I3 => tx_pong_ping_l,
O => \status_reg_reg[5]\(1)
);
\status_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => rx_pong_ping_l,
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
O => \status_reg_reg[5]\(2)
);
\status_reg[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => rx_pong_ping_l,
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
O => \status_reg_reg[5]\(3)
);
\status_reg[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I1 => tx_pong_ping_l,
I2 => s_axi_aresetn,
I3 => \^state24a_0\,
O => \status_reg_reg[5]\(4)
);
\status_reg[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => rx_done_d1,
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
O => \status_reg_reg[0]\(0)
);
\status_reg[5]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => ping_mac_program_reg(0),
I1 => s_axi_aresetn,
I2 => \^state24a_0\,
I3 => tx_pong_ping_l,
O => \status_reg_reg[5]\(5)
);
transmit_start_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000044F4"
)
port map (
I0 => \TX_PONG_REG_GEN.pong_mac_program_reg\,
I1 => p_15_in(0),
I2 => p_17_in(0),
I3 => ping_mac_program_reg(0),
I4 => tx_done_d2,
O => transmit_start
);
transmit_start_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => transmit_start,
Q => transmit_start_reg,
R => \^transmit_start_reg_reg_0\
);
\txNibbleCnt_pad[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EA"
)
port map (
I0 => enblSFD,
I1 => \tx_packet_length_reg[9]\,
I2 => \^enbldata\,
O => \txNibbleCnt_pad_reg[11]\(0)
);
\txNibbleCnt_pad[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(10),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(10),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(11)
);
\txNibbleCnt_pad[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(0),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(0),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(1)
);
\txNibbleCnt_pad[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => enblSFD,
I1 => \txNibbleCnt_pad_reg[11]_1\(0),
I2 => \txNibbleCnt_pad_reg[11]_0\,
O => D(0)
);
\txNibbleCnt_pad[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(9),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(9),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(10)
);
\txNibbleCnt_pad[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(8),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(8),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(9)
);
\txNibbleCnt_pad[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(7),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(7),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(8)
);
\txNibbleCnt_pad[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(6),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(6),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(7)
);
\txNibbleCnt_pad[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(5),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(5),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(6)
);
\txNibbleCnt_pad[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(4),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(4),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(5)
);
\txNibbleCnt_pad[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(3),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(3),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(4)
);
\txNibbleCnt_pad[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(2),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(2),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(3)
);
\txNibbleCnt_pad[9]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"88B8"
)
port map (
I0 => \tx_packet_length_reg[10]\(1),
I1 => enblSFD,
I2 => txNibbleCnt_pad0(1),
I3 => \txNibbleCnt_pad_reg[11]_0\,
O => D(2)
);
\txbuffer_addr[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => \^enblpreamble\,
I1 => s_axi_aresetn,
I2 => chgMacAdr1,
O => \txbuffer_addr_reg[0]\
);
\txbuffer_addr[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => chgMacAdr14,
I1 => Mac_addr_ram_we_i_2_n_0,
I2 => \^enbldata\,
O => tx_addr_en
);
txcrcen_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAEAAAAAAAA"
)
port map (
I0 => \^checkbusfifofull\,
I1 => txCrcEn_reg,
I2 => checkBusFifoFullSFD,
I3 => \^loopback_en_reg\,
I4 => \^checkbusfifofullcrc\,
I5 => txcrcen_d1_i_2_n_0,
O => txCrcEn
);
txcrcen_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^enblpreamble\,
I1 => enblSFD,
I2 => \^enblcrc\,
O => txcrcen_d1_i_2_n_0
);
\xpm_memory_base_inst_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"1F"
)
port map (
I0 => xpm_memory_base_inst_i_4_n_0,
I1 => tx_pong_ping_l,
I2 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg\
);
\xpm_memory_base_inst_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => xpm_memory_base_inst_i_4_n_0,
I1 => tx_pong_ping_l,
I2 => s_axi_aresetn,
O => \gen_wr_b.gen_word_wide.mem_reg_0\
);
xpm_memory_base_inst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => chgMacAdr14,
I1 => Mac_addr_ram_we_i_2_n_0,
I2 => xpm_memory_base_inst_i_6_n_0,
I3 => txDone2,
I4 => lngthDelay2,
I5 => \^checkbusfifofull\,
O => xpm_memory_base_inst_i_4_n_0
);
xpm_memory_base_inst_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^ldlngthcntr\,
I1 => lngthDelay1,
I2 => txDonePause,
I3 => chgMacAdr1,
I4 => \^loopback_en_reg\,
I5 => \^state24a_0\,
O => xpm_memory_base_inst_i_6_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_base is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute VERSION : integer;
attribute VERSION of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of system_axi_ethernetlite_0_0_xpm_memory_base : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of system_axi_ethernetlite_0_0_xpm_memory_base : entity is "TRUE";
end system_axi_ethernetlite_0_0_xpm_memory_base;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_base is
signal \<const0>\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "COMMON";
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "{SYNTH-6 {cell *THIS*}} {SYNTH-7 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_b.gen_word_wide.mem_reg\ : label is 16384;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_b.gen_word_wide.mem_reg\ : label is "gen_wr_b.gen_word_wide.mem";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_b.gen_word_wide.mem_reg\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 5) => addrb(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 0) => dinb(31 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 0) => doutb(31 downto 0),
DOPADOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\,
ENBWREN => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\,
INJECTDBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\,
WEA(3) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(2) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(1) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(0) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(2) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(1) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(0) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rsta,
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rstb,
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => wea(0),
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => web(0),
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_xpm_memory_base__4\ is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ : entity is "TRUE";
end \system_axi_ethernetlite_0_0_xpm_memory_base__4\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_xpm_memory_base__4\ is
signal \<const0>\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "COMMON";
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "{SYNTH-6 {cell *THIS*}} {SYNTH-7 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_b.gen_word_wide.mem_reg\ : label is 16384;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_b.gen_word_wide.mem_reg\ : label is "gen_wr_b.gen_word_wide.mem";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_b.gen_word_wide.mem_reg\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 5) => addrb(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 0) => dinb(31 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 0) => doutb(31 downto 0),
DOPADOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\,
ENBWREN => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\,
INJECTDBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\,
WEA(3) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(2) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(1) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(0) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(2) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(1) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(0) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rsta,
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rstb,
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => wea(0),
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => web(0),
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_xpm_memory_base__5\ is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ : entity is "TRUE";
end \system_axi_ethernetlite_0_0_xpm_memory_base__5\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_xpm_memory_base__5\ is
signal \<const0>\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "COMMON";
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "{SYNTH-6 {cell *THIS*}} {SYNTH-7 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_b.gen_word_wide.mem_reg\ : label is 16384;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_b.gen_word_wide.mem_reg\ : label is "gen_wr_b.gen_word_wide.mem";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_b.gen_word_wide.mem_reg\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 5) => addrb(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 0) => dinb(31 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 0) => doutb(31 downto 0),
DOPADOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\,
ENBWREN => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\,
INJECTDBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\,
WEA(3) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(2) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(1) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(0) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(2) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(1) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(0) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rsta,
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rstb,
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => wea(0),
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => web(0),
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_xpm_memory_base__6\ is
port (
sleep : in STD_LOGIC;
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
injectsbiterra : in STD_LOGIC;
injectdbiterra : in STD_LOGIC;
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
sbiterra : out STD_LOGIC;
dbiterra : out STD_LOGIC;
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterrb : in STD_LOGIC;
injectdbiterrb : in STD_LOGIC;
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
sbiterrb : out STD_LOGIC;
dbiterrb : out STD_LOGIC
);
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "xpm_memory_base";
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute VERSION : integer;
attribute VERSION of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ : entity is "TRUE";
end \system_axi_ethernetlite_0_0_xpm_memory_base__6\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_xpm_memory_base__6\ is
signal \<const0>\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\ : STD_LOGIC;
signal \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 4 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "COMMON";
attribute \MEM.PORTA.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTA.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.ADDRESS_END\ : integer;
attribute \MEM.PORTA.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTA.DATA_LSB\ : integer;
attribute \MEM.PORTA.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTA.DATA_MSB\ : integer;
attribute \MEM.PORTA.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute \MEM.PORTB.ADDRESS_BEGIN\ : integer;
attribute \MEM.PORTB.ADDRESS_BEGIN\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.ADDRESS_END\ : integer;
attribute \MEM.PORTB.ADDRESS_END\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute \MEM.PORTB.DATA_LSB\ : integer;
attribute \MEM.PORTB.DATA_LSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute \MEM.PORTB.DATA_MSB\ : integer;
attribute \MEM.PORTB.DATA_MSB\ of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of \gen_wr_b.gen_word_wide.mem_reg\ : label is "{SYNTH-6 {cell *THIS*}} {SYNTH-7 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of \gen_wr_b.gen_word_wide.mem_reg\ : label is 16384;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of \gen_wr_b.gen_word_wide.mem_reg\ : label is "gen_wr_b.gen_word_wide.mem";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 4095;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of \gen_wr_b.gen_word_wide.mem_reg\ : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of \gen_wr_b.gen_word_wide.mem_reg\ : label is 3;
begin
dbiterra <= \<const0>\;
dbiterrb <= \<const0>\;
sbiterra <= \<const0>\;
sbiterrb <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_wr_b.gen_word_wide.mem_reg\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST",
WRITE_MODE_B => "READ_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15 downto 14) => B"10",
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(15 downto 14) => B"10",
ADDRBWRADDR(13 downto 5) => addrb(8 downto 0),
ADDRBWRADDR(4 downto 0) => B"00000",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_gen_wr_b.gen_word_wide.mem_reg_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_DBITERR_UNCONNECTED\,
DIADI(31 downto 4) => B"0000000000000000000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(31 downto 0) => dinb(31 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 4) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOADO_UNCONNECTED\(31 downto 4),
DOADO(3 downto 0) => douta(3 downto 0),
DOBDO(31 downto 0) => doutb(31 downto 0),
DOPADOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\,
ENBWREN => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\,
INJECTDBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTDBITERR_UNCONNECTED\,
INJECTSBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_INJECTSBITERR_UNCONNECTED\,
RDADDRECC(8 downto 0) => \NLW_gen_wr_b.gen_word_wide.mem_reg_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_gen_wr_b.gen_word_wide.mem_reg_SBITERR_UNCONNECTED\,
WEA(3) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(2) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(1) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEA(0) => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\,
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(2) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(1) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\,
WEBWE(0) => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rsta,
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_1_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => rstb,
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_2_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => wea(0),
I1 => ena,
O => \gen_wr_b.gen_word_wide.mem_reg_i_3_n_0\
);
\gen_wr_b.gen_word_wide.mem_reg_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => web(0),
I1 => enb,
O => \gen_wr_b.gen_word_wide.mem_reg_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_dmem is
port (
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_phy_tx_en_i_p : in STD_LOGIC;
fifo_tx_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_dmem : entity is "dmem";
end system_axi_ethernetlite_0_0_dmem;
architecture STRUCTURE of system_axi_ethernetlite_0_0_dmem is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal bus_combo : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(0),
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\
);
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1) => '0',
DIA(0) => DIA(0),
DIB(1 downto 0) => D(1 downto 0),
DIC(1 downto 0) => D(3 downto 2),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_axi_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_1,
Q => bus_combo(0)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(0)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(1)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(2)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => fifo_tx_en_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_dmem_27 is
port (
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
CLK : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
startReadDestAdrNib : in STD_LOGIC;
\gv.ram_valid_d1_reg\ : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\out\ : in STD_LOGIC;
state0a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_dmem_27 : entity is "dmem";
end system_axi_ethernetlite_0_0_dmem_27;
architecture STRUCTURE of system_axi_ethernetlite_0_0_dmem_27 is
signal \^d\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal \^state2a\ : STD_LOGIC;
signal state2a_i_2_n_0 : STD_LOGIC;
signal state3a_i_2_n_0 : STD_LOGIC;
signal state4a_i_2_n_0 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \crc_local[0]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \crc_local[13]_i_2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of preamble_i_1 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of state0a_i_2 : label is "soft_lutpair28";
attribute SOFT_HLUTNM of state3a_i_2 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of state4a_i_2 : label is "soft_lutpair29";
begin
D(6 downto 0) <= \^d\(6 downto 0);
Q(5 downto 0) <= \^q\(5 downto 0);
state2a <= \^state2a\;
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => CLK,
WE => E(0)
);
busFifoData_is_5_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => \^q\(5),
I1 => \^q\(2),
I2 => \^q\(4),
I3 => \^q\(3),
I4 => \gv.ram_valid_d1_reg\,
I5 => busFifoData_is_5_d1,
O => busFifoData_is_5_d1_reg
);
\crc_local[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(5),
I1 => \crc_local_reg[31]\(6),
O => \^d\(0)
);
\crc_local[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(3),
I1 => \crc_local_reg[31]\(8),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(4),
O => \^d\(5)
);
\crc_local[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(4),
I1 => \crc_local_reg[31]\(7),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(5),
O => \^d\(6)
);
\crc_local[13]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(2),
I1 => \crc_local_reg[31]\(9),
O => \crc_local_reg[13]\
);
\crc_local[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^d\(0),
I1 => \^q\(2),
I2 => \crc_local_reg[31]\(9),
I3 => \^q\(3),
I4 => \crc_local_reg[31]\(8),
I5 => \crc_local_reg[31]\(0),
O => \^d\(1)
);
\crc_local[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(4),
I1 => \crc_local_reg[31]\(7),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(1),
O => \^d\(2)
);
\crc_local[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(3),
I1 => \crc_local_reg[31]\(8),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(2),
O => \^d\(3)
);
\crc_local[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \^q\(4),
I1 => \crc_local_reg[31]\(7),
I2 => \^q\(2),
I3 => \crc_local_reg[31]\(9),
I4 => \^d\(0),
I5 => \crc_local_reg[31]\(3),
O => \^d\(4)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_1,
Q => \^q\(0)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_0,
Q => \^q\(1)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_3,
Q => \^q\(2)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_2,
Q => \^q\(3)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_5,
Q => \^q\(4)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => ram_empty_fb_i_reg(0),
CLR => AR(0),
D => RAM_reg_0_15_0_5_n_4,
Q => \^q\(5)
);
preamble_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F7000000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(4),
I2 => \^q\(3),
I3 => rx_start,
I4 => busFifoData_is_5_d1,
O => preamble
);
state0a_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
I2 => \^q\(4),
I3 => \^q\(3),
O => \^state2a\
);
state17a_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => startReadDataNib,
I3 => \rdDestAddrNib_D_t_q_reg[3]_0\,
O => D11_out
);
state22a_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"005D"
)
port map (
I0 => \^q\(1),
I1 => state0a,
I2 => \out\,
I3 => \rdDestAddrNib_D_t_q_reg[3]\,
O => \rdDestAddrNib_D_t_q_reg[1]\
);
state2a_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"040404FF04040404"
)
port map (
I0 => \^q\(0),
I1 => sfd1CheckBusFifoEmpty,
I2 => state2a_i_2_n_0,
I3 => \^q\(5),
I4 => state3a,
I5 => \^state2a\,
O => D5_out
);
state2a_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000400040"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
I2 => \^q\(2),
I3 => \^q\(5),
I4 => \gv.ram_valid_d1_reg\,
I5 => \out\,
O => state2a_i_2_n_0
);
state3a_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000000D0000"
)
port map (
I0 => \out\,
I1 => \gv.ram_valid_d1_reg\,
I2 => \^q\(5),
I3 => state3a_i_2_n_0,
I4 => sfd1CheckBusFifoEmpty,
I5 => \^q\(0),
O => D13_out
);
state3a_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"BF"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
I2 => \^q\(2),
O => state3a_i_2_n_0
);
state4a_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AABA"
)
port map (
I0 => state4a_i_2_n_0,
I1 => \^q\(0),
I2 => startReadDestAdrNib,
I3 => \gv.ram_valid_d1_reg\,
O => D6_out
);
state4a_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^state2a\,
I1 => \^q\(5),
I2 => busFifoData_is_5_d1,
I3 => rx_start,
O => state4a_i_2_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_bin_cntr : entity is "rd_bin_cntr";
end system_axi_ethernetlite_0_0_rd_bin_cntr;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__0\ : label is "soft_lutpair60";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__2\(0)
);
\gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__2\(1)
);
\gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => \plusOp__2\(2)
);
\gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => \plusOp__2\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => E(0),
D => \plusOp__2\(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => E(0),
CLR => AR(0),
D => \plusOp__2\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_bin_cntr_31 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_bin_cntr_31 : entity is "rd_bin_cntr";
end system_axi_ethernetlite_0_0_rd_bin_cntr_31;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_bin_cntr_31 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[1]_i_1\ : label is "soft_lutpair25";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => plusOp(0),
PRE => AR(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => plusOp(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_handshaking_flags is
port (
state1a : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
state0a : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
startReadDestAdrNib : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_handshaking_flags : entity is "rd_handshaking_flags";
end system_axi_ethernetlite_0_0_rd_handshaking_flags;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_handshaking_flags is
signal \^state1a\ : STD_LOGIC;
begin
state1a <= \^state1a\;
\gv.ram_valid_d1_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => ram_valid_i,
Q => \^state1a\
);
\rdDestAddrNib_D_t_q[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^state1a\,
I1 => startReadDestAdrNib,
I2 => Q(0),
O => goto_readDestAdrNib1
);
state0a_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0BBB"
)
port map (
I0 => \^state1a\,
I1 => \out\,
I2 => ping_rx_status_reg,
I3 => \RX_PONG_REG_GEN.pong_rx_status_reg\,
O => state0a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
fifo_tx_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_status_flags_as : entity is "rd_status_flags_as";
end system_axi_ethernetlite_0_0_rd_status_flags_as;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_i;
\gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => fifo_tx_en,
I1 => ram_empty_fb_i,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
PRE => AR(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_status_flags_as_30 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gv.ram_valid_d1_reg\ : in STD_LOGIC;
state0a : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
ping_rx_status_reg : in STD_LOGIC;
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_status_flags_as_30 : entity is "rd_status_flags_as";
end system_axi_ethernetlite_0_0_rd_status_flags_as_30;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_status_flags_as_30 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\gpr1.dout_i_reg[0]\ <= ram_empty_fb_i;
\out\ <= ram_empty_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
PRE => AR(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
PRE => AR(0),
Q => ram_empty_i
);
\rdDestAddrNib_D_t_q[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"1515FF05"
)
port map (
I0 => \rdDestAddrNib_D_t_q_reg[3]_0\,
I1 => ram_empty_i,
I2 => Q(0),
I3 => \gv.ram_valid_d1_reg\,
I4 => state0a,
O => \rdDestAddrNib_D_t_q_reg[3]\
);
state1a_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"77070000"
)
port map (
I0 => \RX_PONG_REG_GEN.pong_rx_status_reg\,
I1 => ping_rx_status_reg,
I2 => ram_empty_i,
I3 => \gv.ram_valid_d1_reg\,
I4 => rxCrcRst,
O => state1a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_10 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_10 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_10;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_10 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_23 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_23 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_23;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_23 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_24 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_24 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_24;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_24 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_25 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_25 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_25;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_25 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_26 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
CLK : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_26 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_26;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_26 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_8 is
port (
\out\ : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_8 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_8;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_8 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_synchronizer_ff_9 is
port (
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_synchronizer_ff_9 : entity is "synchronizer_ff";
end system_axi_ethernetlite_0_0_synchronizer_ff_9;
architecture STRUCTURE of system_axi_ethernetlite_0_0_synchronizer_ff_9 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\ : entity is "synchronizer_ff";
end \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\;
architecture STRUCTURE of \system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_bin_cntr : entity is "wr_bin_cntr";
end system_axi_ethernetlite_0_0_wr_bin_cntr;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_full_i_i_5_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair61";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
O => \plusOp__0\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => p_13_out(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => p_13_out(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => p_13_out(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => p_13_out(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => p_13_out(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \plusOp__0\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
ram_full_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3),
I1 => p_13_out(3),
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(1),
I3 => p_13_out(1),
I4 => ram_full_i_i_5_n_0,
O => ram_full_fb_i_reg
);
ram_full_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_13_out(0),
I1 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
I2 => p_13_out(2),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(2),
O => ram_full_i_i_5_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_bin_cntr_29 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_bin_cntr_29 : entity is "wr_bin_cntr";
end system_axi_ethernetlite_0_0_wr_bin_cntr_29;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_bin_cntr_29 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__0\ : label is "soft_lutpair26";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_status_flags_as is
port (
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_status_flags_as : entity is "wr_status_flags_as";
end system_axi_ethernetlite_0_0_wr_status_flags_as;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
STATE16A <= ram_full_i;
\gic0.gc0.count_reg[0]\ <= ram_full_fb_i;
STATE16A_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => txfifo_empty,
I1 => waitFifoEmpty,
I2 => ram_full_i,
I3 => STATE14A,
O => D18_out
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \grstd1.grst_full.grst_f.rst_d3_reg\,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \grstd1.grst_full.grst_f.rst_d3_reg\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_status_flags_as_28 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
CLK : in STD_LOGIC;
\out\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_status_flags_as_28 : entity is "wr_status_flags_as";
end system_axi_ethernetlite_0_0_wr_status_flags_as_28;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_status_flags_as_28 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_fb_i,
I1 => ram_full_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"1001"
)
port map (
I0 => ram_full_i,
I1 => ram_full_fb_i,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_MacAddrRAM is
port (
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]_0\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
mac_addr_ram_we : in STD_LOGIC;
mac_addr_ram_addr : in STD_LOGIC_VECTOR ( 0 to 3 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_MacAddrRAM : entity is "MacAddrRAM";
end system_axi_ethernetlite_0_0_MacAddrRAM;
architecture STRUCTURE of system_axi_ethernetlite_0_0_MacAddrRAM is
begin
ram16x4i: entity work.system_axi_ethernetlite_0_0_ram16x4
port map (
Q(3 downto 0) => Q(3 downto 0),
\gen_wr_b.gen_word_wide.mem_reg\(3 downto 0) => \gen_wr_b.gen_word_wide.mem_reg\(3 downto 0),
mac_addr_ram_addr(0 to 3) => mac_addr_ram_addr(0 to 3),
mac_addr_ram_we => mac_addr_ram_we,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[1]_0\ => \rdDestAddrNib_D_t_q_reg[1]_0\,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_crcgentx is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
txCrcEn_reg : in STD_LOGIC;
\emac_tx_wr_data_d1_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_crcgentx : entity is "crcgentx";
end system_axi_ethernetlite_0_0_crcgentx;
architecture STRUCTURE of system_axi_ethernetlite_0_0_crcgentx is
begin
NSR: entity work.system_axi_ethernetlite_0_0_crcnibshiftreg
port map (
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
SR(0) => SR(0),
\emac_tx_wr_data_d1_reg[0]\(3 downto 0) => \emac_tx_wr_data_d1_reg[0]\(3 downto 0),
s_axi_aclk => s_axi_aclk,
txCrcEn_reg => txCrcEn_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_deferral is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D13_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_crs_d2 : in STD_LOGIC;
tx_en_i : in STD_LOGIC;
tx_clk_reg_d3 : in STD_LOGIC;
tx_clk_reg_d2 : in STD_LOGIC;
ldLngthCntr : in STD_LOGIC;
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ : in STD_LOGIC;
enblPreamble : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_deferral : entity is "deferral";
end system_axi_ethernetlite_0_0_deferral;
architecture STRUCTURE of system_axi_ethernetlite_0_0_deferral is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \count_reg__0\ : STD_LOGIC_VECTOR ( 3 to 4 );
signal \count_reg__0_0\ : STD_LOGIC_VECTOR ( 3 to 4 );
signal ifgp1_zero : STD_LOGIC;
signal ifgp2_zero : STD_LOGIC;
signal inst_deferral_state_n_2 : STD_LOGIC;
signal inst_deferral_state_n_3 : STD_LOGIC;
signal inst_deferral_state_n_8 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
inst_deferral_state: entity work.system_axi_ethernetlite_0_0_defer_state
port map (
D(1 downto 0) => \p_0_in__0\(1 downto 0),
D13_out => D13_out,
E(0) => inst_deferral_state_n_2,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ => \PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\,
Q(1 downto 0) => \^q\(1 downto 0),
\count_reg[0]\ => inst_deferral_state_n_8,
\count_reg[3]\(1 downto 0) => p_0_in(1 downto 0),
\count_reg[3]_0\(1) => \count_reg__0_0\(3),
\count_reg[3]_0\(0) => \count_reg__0_0\(4),
\count_reg[3]_1\(1) => \count_reg__0\(3),
\count_reg[3]_1\(0) => \count_reg__0\(4),
\count_reg[4]\(0) => inst_deferral_state_n_3,
enblPreamble => enblPreamble,
ifgp1_zero => ifgp1_zero,
ifgp2_zero => ifgp2_zero,
ldLngthCntr => ldLngthCntr,
phy_crs_d2 => phy_crs_d2,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
tx_clk_reg_d2 => tx_clk_reg_d2,
tx_clk_reg_d3 => tx_clk_reg_d3,
tx_en_i => tx_en_i
);
inst_ifgp1_count: entity work.system_axi_ethernetlite_0_0_cntr5bit
port map (
D(1 downto 0) => p_0_in(1 downto 0),
E(0) => inst_deferral_state_n_3,
Q(1) => \count_reg__0\(3),
Q(0) => \count_reg__0\(4),
ifgp1_zero => ifgp1_zero,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\thisState_reg[0]\ => inst_deferral_state_n_8,
\thisState_reg[1]\(1 downto 0) => \^q\(1 downto 0)
);
inst_ifgp2_count: entity work.system_axi_ethernetlite_0_0_cntr5bit_11
port map (
D(1 downto 0) => \p_0_in__0\(1 downto 0),
E(0) => inst_deferral_state_n_2,
Q(1) => \count_reg__0_0\(3),
Q(0) => \count_reg__0_0\(4),
ifgp2_zero => ifgp2_zero,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\thisState_reg[0]\ => inst_deferral_state_n_8,
\thisState_reg[1]\(1 downto 0) => \^q\(1 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_tdpram is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 4 downto 0 );
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 26 downto 0 );
s_axi_aclk : in STD_LOGIC;
\TX_PONG_GEN.tx_pong_ping_l_reg\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
tx_idle : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\reg_data_out_reg[0]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
reg_access_reg : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_2\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\reg_data_out_reg[1]\ : in STD_LOGIC;
p_21_in144_in : in STD_LOGIC;
p_27_in163_in : in STD_LOGIC;
p_33_in182_in : in STD_LOGIC;
p_39_in : in STD_LOGIC;
p_45_in : in STD_LOGIC;
p_57_in : in STD_LOGIC;
p_63_in : in STD_LOGIC;
p_75_in309_in : in STD_LOGIC;
p_74_in307_in : in STD_LOGIC;
p_87_in351_in : in STD_LOGIC;
p_86_in349_in : in STD_LOGIC;
p_93_in : in STD_LOGIC;
p_92_in368_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_tdpram : entity is "xpm_memory_tdpram";
end system_axi_ethernetlite_0_0_xpm_memory_tdpram;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_tdpram is
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_2_n_0\ : STD_LOGIC;
signal \^douta\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 30 downto 0 );
signal xpm_memory_base_inst_n_38 : STD_LOGIC;
signal xpm_memory_base_inst_n_39 : STD_LOGIC;
signal xpm_memory_base_inst_n_4 : STD_LOGIC;
signal xpm_memory_base_inst_n_5 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_1\ : label is "soft_lutpair98";
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of xpm_memory_base_inst : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of xpm_memory_base_inst : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of xpm_memory_base_inst : label is 3;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of xpm_memory_base_inst : label is 4095;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of xpm_memory_base_inst : label is 4;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of xpm_memory_base_inst : label is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of xpm_memory_base_inst : label is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of xpm_memory_base_inst : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of xpm_memory_base_inst : label is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of xpm_memory_base_inst : label is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of xpm_memory_base_inst : label is 1;
attribute VERSION : integer;
attribute VERSION of xpm_memory_base_inst : label is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
begin
douta(3 downto 0) <= \^douta\(3 downto 0);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \reg_data_out_reg[0]\,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(0),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_2_n_0\,
O => D(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AACCFFF0AACC00"
)
port map (
I0 => p_1_out(0),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(0),
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(0),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_2\(0),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[0]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_63_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(8),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_2_n_0\,
O => D(8)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(10),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(8),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(8),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(8),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[10]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_75_in309_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_74_in307_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_2_n_0\,
O => D(9)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(12),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(9),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(9),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(9),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[12]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_87_in351_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_86_in349_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_2_n_0\,
O => D(10)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AACCFFF0AACC00"
)
port map (
I0 => p_1_out(14),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(10),
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(10),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_2\(10),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[14]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_93_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_92_in368_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_2_n_0\,
O => D(11)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(15),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(11),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(11),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(11),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[15]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_2_n_0\,
O => D(12)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(16),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(12),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(12),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(12),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[16]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_2_n_0\,
O => D(13)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(17),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(13),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(13),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(13),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[17]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_2_n_0\,
O => D(14)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(18),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(14),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(14),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(14),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[18]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_2_n_0\,
O => D(15)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(19),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(15),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(15),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(15),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[19]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \reg_data_out_reg[1]\,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(1),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_2_n_0\,
O => D(1)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(1),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(1),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(1),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(1),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[1]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_2_n_0\,
O => D(16)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(20),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(16),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(16),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(16),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[20]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_2_n_0\,
O => D(17)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(21),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(17),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(17),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(17),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[21]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_2_n_0\,
O => D(18)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(22),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(18),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(18),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(18),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[22]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_2_n_0\,
O => D(19)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(23),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(19),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(19),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(19),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[23]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_2_n_0\,
O => D(20)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(24),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(20),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(20),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(20),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[24]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_2_n_0\,
O => D(21)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(25),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(21),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(21),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(21),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[25]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_2_n_0\,
O => D(22)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(26),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(22),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(22),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(22),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[26]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_2_n_0\,
O => D(23)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(27),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(23),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(23),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(23),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[27]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_2_n_0\,
O => D(24)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(28),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(24),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(24),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(24),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[28]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_2_n_0\,
O => D(25)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(29),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(25),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(25),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(25),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[29]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => reg_access_reg,
I1 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_2_n_0\,
O => D(26)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0055330FFF55330F"
)
port map (
I0 => p_1_out(30),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(26),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(26),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(26),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[30]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_21_in144_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(2),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_2_n_0\,
O => D(2)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(3),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(2),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(2),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(2),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[3]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_27_in163_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(3),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_2_n_0\,
O => D(3)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AACCFFF0AACC00"
)
port map (
I0 => p_1_out(4),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(3),
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(3),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_2\(3),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[4]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_33_in182_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(4),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_2_n_0\,
O => D(4)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(5),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(4),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(4),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(4),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[5]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_39_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(5),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_2_n_0\,
O => D(5)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(6),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(5),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(5),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(5),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[6]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_45_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(6),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_2_n_0\,
O => D(6)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAACCF000AACCF0"
)
port map (
I0 => p_1_out(7),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(6),
I2 => \gen_wr_b.gen_word_wide.mem_reg_2\(6),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(6),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[7]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_57_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => Q(7),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_2_n_0\,
O => D(7)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AACCFFF0AACC00"
)
port map (
I0 => p_1_out(9),
I1 => \gen_wr_b.gen_word_wide.mem_reg_0\(7),
I2 => \gen_wr_b.gen_word_wide.mem_reg_1\(7),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_2\(7),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[9]_i_2_n_0\
);
ram16x1_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0B08"
)
port map (
I0 => \^douta\(0),
I1 => tx_pong_ping_l,
I2 => tx_idle,
I3 => \gen_wr_b.gen_word_wide.mem_reg\(0),
O => \rdDestAddrNib_D_t_q_reg[1]\(0)
);
ram16x1_2_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0B08"
)
port map (
I0 => \^douta\(2),
I1 => tx_pong_ping_l,
I2 => tx_idle,
I3 => \gen_wr_b.gen_word_wide.mem_reg\(1),
O => \rdDestAddrNib_D_t_q_reg[1]\(1)
);
ram16x1_3_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0B08"
)
port map (
I0 => \^douta\(3),
I1 => tx_pong_ping_l,
I2 => tx_idle,
I3 => \gen_wr_b.gen_word_wide.mem_reg\(2),
O => \rdDestAddrNib_D_t_q_reg[1]\(2)
);
xpm_memory_base_inst: entity work.\system_axi_ethernetlite_0_0_xpm_memory_base__6\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(8 downto 0),
clka => s_axi_aclk,
clkb => s_axi_aclk,
dbiterra => xpm_memory_base_inst_n_5,
dbiterrb => xpm_memory_base_inst_n_39,
dina(3 downto 0) => B"0000",
dinb(31 downto 0) => s_axi_wdata(31 downto 0),
douta(3 downto 0) => \^douta\(3 downto 0),
doutb(31) => doutb(4),
doutb(30 downto 14) => p_1_out(30 downto 14),
doutb(13) => doutb(3),
doutb(12) => p_1_out(12),
doutb(11) => doutb(2),
doutb(10 downto 9) => p_1_out(10 downto 9),
doutb(8) => doutb(1),
doutb(7 downto 3) => p_1_out(7 downto 3),
doutb(2) => doutb(0),
doutb(1 downto 0) => p_1_out(1 downto 0),
ena => \TX_PONG_GEN.tx_pong_ping_l_reg\,
enb => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '1',
regceb => '1',
rsta => '0',
rstb => '0',
sbiterra => xpm_memory_base_inst_n_4,
sbiterrb => xpm_memory_base_inst_n_38,
sleep => '0',
wea(0) => '0',
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_tdpram_4 is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\TX_PONG_GEN.tx_pong_ping_l_reg\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
tx_idle : in STD_LOGIC;
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_tdpram_4 : entity is "xpm_memory_tdpram";
end system_axi_ethernetlite_0_0_xpm_memory_tdpram_4;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_tdpram_4 is
signal \^douta\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xpm_memory_base_inst_n_38 : STD_LOGIC;
signal xpm_memory_base_inst_n_39 : STD_LOGIC;
signal xpm_memory_base_inst_n_4 : STD_LOGIC;
signal xpm_memory_base_inst_n_5 : STD_LOGIC;
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of xpm_memory_base_inst : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of xpm_memory_base_inst : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of xpm_memory_base_inst : label is 3;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of xpm_memory_base_inst : label is 4095;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of xpm_memory_base_inst : label is 4;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of xpm_memory_base_inst : label is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of xpm_memory_base_inst : label is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of xpm_memory_base_inst : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of xpm_memory_base_inst : label is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of xpm_memory_base_inst : label is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of xpm_memory_base_inst : label is 1;
attribute VERSION : integer;
attribute VERSION of xpm_memory_base_inst : label is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
begin
douta(3 downto 0) <= \^douta\(3 downto 0);
ram16x1_1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"3202"
)
port map (
I0 => \^douta\(1),
I1 => tx_idle,
I2 => tx_pong_ping_l,
I3 => \gen_wr_b.gen_word_wide.mem_reg\(0),
O => \rdDestAddrNib_D_t_q_reg[1]\(0)
);
xpm_memory_base_inst: entity work.\system_axi_ethernetlite_0_0_xpm_memory_base__4\
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0),
clka => s_axi_aclk,
clkb => s_axi_aclk,
dbiterra => xpm_memory_base_inst_n_5,
dbiterrb => xpm_memory_base_inst_n_39,
dina(3 downto 0) => B"0000",
dinb(31 downto 0) => s_axi_wdata(31 downto 0),
douta(3 downto 0) => \^douta\(3 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => \TX_PONG_GEN.tx_pong_ping_l_reg\,
enb => enb,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '1',
regceb => '1',
rsta => '0',
rstb => '0',
sbiterra => xpm_memory_base_inst_n_4,
sbiterrb => xpm_memory_base_inst_n_38,
sleep => '0',
wea(0) => '0',
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_tdpram_5 is
port (
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
state0a : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\rxbuffer_addr_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_tdpram_5 : entity is "xpm_memory_tdpram";
end system_axi_ethernetlite_0_0_xpm_memory_tdpram_5;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_tdpram_5 is
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xpm_memory_base_inst_n_38 : STD_LOGIC;
signal xpm_memory_base_inst_n_39 : STD_LOGIC;
signal xpm_memory_base_inst_n_4 : STD_LOGIC;
signal xpm_memory_base_inst_n_5 : STD_LOGIC;
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of xpm_memory_base_inst : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of xpm_memory_base_inst : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of xpm_memory_base_inst : label is 3;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of xpm_memory_base_inst : label is 4095;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of xpm_memory_base_inst : label is 4;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of xpm_memory_base_inst : label is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of xpm_memory_base_inst : label is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of xpm_memory_base_inst : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of xpm_memory_base_inst : label is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of xpm_memory_base_inst : label is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of xpm_memory_base_inst : label is 1;
attribute VERSION : integer;
attribute VERSION of xpm_memory_base_inst : label is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
begin
xpm_memory_base_inst: entity work.system_axi_ethernetlite_0_0_xpm_memory_base
port map (
addra(11 downto 0) => \rxbuffer_addr_reg[0]\(11 downto 0),
addrb(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0),
clka => s_axi_aclk,
clkb => s_axi_aclk,
dbiterra => xpm_memory_base_inst_n_5,
dbiterrb => xpm_memory_base_inst_n_39,
dina(3 downto 0) => Q(3 downto 0),
dinb(31 downto 0) => s_axi_wdata(31 downto 0),
douta(3 downto 0) => p_5_out(3 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => state0a,
enb => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '1',
regceb => '1',
rsta => '0',
rstb => '0',
sbiterra => xpm_memory_base_inst_n_4,
sbiterrb => xpm_memory_base_inst_n_38,
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xpm_memory_tdpram_6 is
port (
doutb : out STD_LOGIC_VECTOR ( 26 downto 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\rxbuffer_addr_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\reg_data_out_reg[2]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg_access_reg : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_51_in : in STD_LOGIC;
p_69_in : in STD_LOGIC;
p_68_in288_in : in STD_LOGIC;
p_81_in330_in : in STD_LOGIC;
p_80_in328_in : in STD_LOGIC;
\reg_data_out_reg[31]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xpm_memory_tdpram_6 : entity is "xpm_memory_tdpram";
end system_axi_ethernetlite_0_0_xpm_memory_tdpram_6;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xpm_memory_tdpram_6 is
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_3_n_0\ : STD_LOGIC;
signal \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_2_n_0\ : STD_LOGIC;
signal rx_ping_data_out : STD_LOGIC_VECTOR ( 31 downto 2 );
signal rx_ping_rd_data : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xpm_memory_base_inst_n_38 : STD_LOGIC;
signal xpm_memory_base_inst_n_39 : STD_LOGIC;
signal xpm_memory_base_inst_n_4 : STD_LOGIC;
signal xpm_memory_base_inst_n_5 : STD_LOGIC;
attribute ADDR_WIDTH_A : integer;
attribute ADDR_WIDTH_A of xpm_memory_base_inst : label is 12;
attribute ADDR_WIDTH_B : integer;
attribute ADDR_WIDTH_B of xpm_memory_base_inst : label is 9;
attribute AUTO_SLEEP_TIME : integer;
attribute AUTO_SLEEP_TIME of xpm_memory_base_inst : label is 0;
attribute BYTE_WRITE_WIDTH_A : integer;
attribute BYTE_WRITE_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute BYTE_WRITE_WIDTH_B : integer;
attribute BYTE_WRITE_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute CLOCKING_MODE : integer;
attribute CLOCKING_MODE of xpm_memory_base_inst : label is 0;
attribute ECC_MODE : integer;
attribute ECC_MODE of xpm_memory_base_inst : label is 0;
attribute MAX_NUM_CHAR : integer;
attribute MAX_NUM_CHAR of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE\ : boolean;
attribute \MEM.ADDRESS_SPACE\ of xpm_memory_base_inst : label is std.standard.true;
attribute \MEM.ADDRESS_SPACE_BEGIN\ : integer;
attribute \MEM.ADDRESS_SPACE_BEGIN\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_LSB\ of xpm_memory_base_inst : label is 0;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ : integer;
attribute \MEM.ADDRESS_SPACE_DATA_MSB\ of xpm_memory_base_inst : label is 3;
attribute \MEM.ADDRESS_SPACE_END\ : integer;
attribute \MEM.ADDRESS_SPACE_END\ of xpm_memory_base_inst : label is 4095;
attribute \MEM.CORE_MEMORY_WIDTH\ : integer;
attribute \MEM.CORE_MEMORY_WIDTH\ of xpm_memory_base_inst : label is 4;
attribute MEMORY_INIT_FILE : string;
attribute MEMORY_INIT_FILE of xpm_memory_base_inst : label is "none";
attribute MEMORY_INIT_PARAM : string;
attribute MEMORY_INIT_PARAM of xpm_memory_base_inst : label is "";
attribute MEMORY_PRIMITIVE : integer;
attribute MEMORY_PRIMITIVE of xpm_memory_base_inst : label is 2;
attribute MEMORY_SIZE : integer;
attribute MEMORY_SIZE of xpm_memory_base_inst : label is 16384;
attribute MEMORY_TYPE : integer;
attribute MEMORY_TYPE of xpm_memory_base_inst : label is 2;
attribute MESSAGE_CONTROL : integer;
attribute MESSAGE_CONTROL of xpm_memory_base_inst : label is 0;
attribute NUM_CHAR_LOC : integer;
attribute NUM_CHAR_LOC of xpm_memory_base_inst : label is 0;
attribute P_ECC_MODE : string;
attribute P_ECC_MODE of xpm_memory_base_inst : label is "no_ecc";
attribute P_ENABLE_BYTE_WRITE_A : integer;
attribute P_ENABLE_BYTE_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_ENABLE_BYTE_WRITE_B : integer;
attribute P_ENABLE_BYTE_WRITE_B of xpm_memory_base_inst : label is 0;
attribute P_MAX_DEPTH_DATA : integer;
attribute P_MAX_DEPTH_DATA of xpm_memory_base_inst : label is 4096;
attribute P_MEMORY_PRIMITIVE : string;
attribute P_MEMORY_PRIMITIVE of xpm_memory_base_inst : label is "block";
attribute P_MIN_WIDTH_DATA : integer;
attribute P_MIN_WIDTH_DATA of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_A : integer;
attribute P_MIN_WIDTH_DATA_A of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_B : integer;
attribute P_MIN_WIDTH_DATA_B of xpm_memory_base_inst : label is 32;
attribute P_MIN_WIDTH_DATA_ECC : integer;
attribute P_MIN_WIDTH_DATA_ECC of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_LDW : integer;
attribute P_MIN_WIDTH_DATA_LDW of xpm_memory_base_inst : label is 4;
attribute P_MIN_WIDTH_DATA_SHFT : integer;
attribute P_MIN_WIDTH_DATA_SHFT of xpm_memory_base_inst : label is 5;
attribute P_NUM_COLS_WRITE_A : integer;
attribute P_NUM_COLS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_COLS_WRITE_B : integer;
attribute P_NUM_COLS_WRITE_B of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_A : integer;
attribute P_NUM_ROWS_READ_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_READ_B : integer;
attribute P_NUM_ROWS_READ_B of xpm_memory_base_inst : label is 8;
attribute P_NUM_ROWS_WRITE_A : integer;
attribute P_NUM_ROWS_WRITE_A of xpm_memory_base_inst : label is 1;
attribute P_NUM_ROWS_WRITE_B : integer;
attribute P_NUM_ROWS_WRITE_B of xpm_memory_base_inst : label is 8;
attribute P_SDP_WRITE_MODE : string;
attribute P_SDP_WRITE_MODE of xpm_memory_base_inst : label is "yes";
attribute P_WIDTH_ADDR_LSB_READ_A : integer;
attribute P_WIDTH_ADDR_LSB_READ_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_READ_B : integer;
attribute P_WIDTH_ADDR_LSB_READ_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_LSB_WRITE_A : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_A of xpm_memory_base_inst : label is 0;
attribute P_WIDTH_ADDR_LSB_WRITE_B : integer;
attribute P_WIDTH_ADDR_LSB_WRITE_B of xpm_memory_base_inst : label is 3;
attribute P_WIDTH_ADDR_READ_A : integer;
attribute P_WIDTH_ADDR_READ_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_READ_B : integer;
attribute P_WIDTH_ADDR_READ_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_ADDR_WRITE_A : integer;
attribute P_WIDTH_ADDR_WRITE_A of xpm_memory_base_inst : label is 12;
attribute P_WIDTH_ADDR_WRITE_B : integer;
attribute P_WIDTH_ADDR_WRITE_B of xpm_memory_base_inst : label is 9;
attribute P_WIDTH_COL_WRITE_A : integer;
attribute P_WIDTH_COL_WRITE_A of xpm_memory_base_inst : label is 4;
attribute P_WIDTH_COL_WRITE_B : integer;
attribute P_WIDTH_COL_WRITE_B of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_A : integer;
attribute READ_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute READ_DATA_WIDTH_B : integer;
attribute READ_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute READ_LATENCY_A : integer;
attribute READ_LATENCY_A of xpm_memory_base_inst : label is 1;
attribute READ_LATENCY_B : integer;
attribute READ_LATENCY_B of xpm_memory_base_inst : label is 1;
attribute READ_RESET_VALUE_A : string;
attribute READ_RESET_VALUE_A of xpm_memory_base_inst : label is "0";
attribute READ_RESET_VALUE_B : string;
attribute READ_RESET_VALUE_B of xpm_memory_base_inst : label is "0";
attribute USE_MEM_INIT : integer;
attribute USE_MEM_INIT of xpm_memory_base_inst : label is 1;
attribute VERSION : integer;
attribute VERSION of xpm_memory_base_inst : label is 0;
attribute WAKEUP_TIME : integer;
attribute WAKEUP_TIME of xpm_memory_base_inst : label is 0;
attribute WRITE_DATA_WIDTH_A : integer;
attribute WRITE_DATA_WIDTH_A of xpm_memory_base_inst : label is 4;
attribute WRITE_DATA_WIDTH_B : integer;
attribute WRITE_DATA_WIDTH_B of xpm_memory_base_inst : label is 32;
attribute WRITE_MODE_A : integer;
attribute WRITE_MODE_A of xpm_memory_base_inst : label is 1;
attribute WRITE_MODE_B : integer;
attribute WRITE_MODE_B of xpm_memory_base_inst : label is 1;
attribute XPM_MODULE : string;
attribute XPM_MODULE of xpm_memory_base_inst : label is "TRUE";
begin
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_69_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_68_in288_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_2_n_0\,
O => D(2)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(11),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(2),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(2),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(2),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[11]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_81_in330_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => p_80_in328_in,
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_2_n_0\,
O => D(3)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(13),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(3),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(3),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(3),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[13]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \reg_data_out_reg[2]\,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => \MDIO_GEN.mdio_data_out_reg[8]\(0),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_2_n_0\,
O => D(0)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(2),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(0),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(0),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(0),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[2]_i_2_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8F80"
)
port map (
I0 => \reg_data_out_reg[31]\,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => reg_access_reg,
I3 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_3_n_0\,
O => D(4)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(31),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(4),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(4),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(4),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[31]_i_3_n_0\
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_51_in,
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
I2 => \MDIO_GEN.mdio_data_out_reg[8]\(1),
I3 => reg_access_reg,
I4 => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_2_n_0\,
O => D(1)
);
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFCCAAF000CCAAF0"
)
port map (
I0 => rx_ping_data_out(8),
I1 => \gen_wr_b.gen_word_wide.mem_reg\(1),
I2 => \gen_wr_b.gen_word_wide.mem_reg_0\(1),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(9),
I5 => \gen_wr_b.gen_word_wide.mem_reg_1\(1),
O => \AXI4_LITE_IF_GEN.IP2Bus_Data_sampled[8]_i_2_n_0\
);
xpm_memory_base_inst: entity work.\system_axi_ethernetlite_0_0_xpm_memory_base__5\
port map (
addra(11 downto 0) => \rxbuffer_addr_reg[0]\(11 downto 0),
addrb(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(8 downto 0),
clka => s_axi_aclk,
clkb => s_axi_aclk,
dbiterra => xpm_memory_base_inst_n_5,
dbiterrb => xpm_memory_base_inst_n_39,
dina(3 downto 0) => Q(3 downto 0),
dinb(31 downto 0) => s_axi_wdata(31 downto 0),
douta(3 downto 0) => rx_ping_rd_data(3 downto 0),
doutb(31) => rx_ping_data_out(31),
doutb(30 downto 14) => doutb(26 downto 10),
doutb(13) => rx_ping_data_out(13),
doutb(12) => doutb(9),
doutb(11) => rx_ping_data_out(11),
doutb(10 downto 9) => doutb(8 downto 7),
doutb(8) => rx_ping_data_out(8),
doutb(7 downto 3) => doutb(6 downto 2),
doutb(2) => rx_ping_data_out(2),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
injectdbiterra => '0',
injectdbiterrb => '0',
injectsbiterra => '0',
injectsbiterrb => '0',
regcea => '1',
regceb => '1',
rsta => '0',
rstb => '0',
sbiterra => xpm_memory_base_inst_n_4,
sbiterrb => xpm_memory_base_inst_n_38,
sleep => '0',
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]_0\ : in STD_LOGIC;
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
fifo_tx_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_clk_x_pntrs : entity is "clk_x_pntrs";
end system_axi_ethernetlite_0_0_clk_x_pntrs;
architecture STRUCTURE of system_axi_ethernetlite_0_0_clk_x_pntrs is
signal \_inferred__0/i__n_0\ : STD_LOGIC;
signal \_inferred__2/i__n_0\ : STD_LOGIC;
signal \_inferred__3/i__n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_4__0_n_0\ : STD_LOGIC;
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_inferred__2/i_\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \_inferred__3/i_\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair58";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(3 downto 0) <= \^ram_full_fb_i_reg_0\(3 downto 0);
\_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \_inferred__0/i__n_0\
);
\_inferred__2/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_6_out(1),
I1 => p_6_out(0),
I2 => p_6_out(3),
I3 => p_6_out(2),
O => \_inferred__2/i__n_0\
);
\_inferred__3/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_6_out(2),
I1 => p_6_out(1),
I2 => p_6_out(3),
O => \_inferred__3/i__n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
phy_tx_clk => phy_tx_clk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2\
port map (
D(0) => \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
phy_tx_clk => phy_tx_clk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
\out\(3 downto 0) => p_6_out(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \_inferred__2/i__n_0\,
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \_inferred__3/i__n_0\,
Q => \^ram_full_fb_i_reg_0\(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => \^ram_full_fb_i_reg_0\(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => p_6_out(3),
Q => \^ram_full_fb_i_reg_0\(3)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(3),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \_inferred__0/i__n_0\,
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[2].rd_stg_inst_n_4\,
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF41000041"
)
port map (
I0 => \ram_empty_i_i_2__0_n_0\,
I1 => p_22_out(2),
I2 => \gc0.count_d1_reg[3]\(2),
I3 => p_22_out(3),
I4 => \gc0.count_d1_reg[3]\(3),
I5 => \ram_empty_i_i_3__0_n_0\,
O => ram_empty_fb_i_reg
);
\ram_empty_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(1),
I1 => \gc0.count_d1_reg[3]\(1),
I2 => p_22_out(0),
I3 => \gc0.count_d1_reg[3]\(0),
O => \ram_empty_i_i_2__0_n_0\
);
\ram_empty_i_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4100004100000000"
)
port map (
I0 => \ram_empty_i_i_4__0_n_0\,
I1 => p_22_out(2),
I2 => \gc0.count_reg[3]\(2),
I3 => p_22_out(3),
I4 => \gc0.count_reg[3]\(3),
I5 => fifo_tx_en_reg(0),
O => \ram_empty_i_i_3__0_n_0\
);
\ram_empty_i_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(1),
I1 => \gc0.count_reg[3]\(1),
I2 => p_22_out(0),
I3 => \gc0.count_reg[3]\(0),
O => \ram_empty_i_i_4__0_n_0\
);
ram_full_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00F8"
)
port map (
I0 => E(0),
I1 => ram_full_i_i_2_n_0,
I2 => \gnxpm_cdc.rd_pntr_bin_reg[3]_0\,
I3 => \grstd1.grst_full.grst_f.rst_d3_reg\,
O => ram_full_fb_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => Q(2),
I1 => \^ram_full_fb_i_reg_0\(2),
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(3),
I4 => ram_full_i_i_4_n_0,
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^ram_full_fb_i_reg_0\(1),
I1 => Q(1),
I2 => \^ram_full_fb_i_reg_0\(0),
I3 => Q(0),
O => ram_full_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_clk_x_pntrs_18 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_i_reg : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_clk_x_pntrs_18 : entity is "clk_x_pntrs";
end system_axi_ethernetlite_0_0_clk_x_pntrs_18;
architecture STRUCTURE of system_axi_ethernetlite_0_0_clk_x_pntrs_18 is
signal \_inferred__2/i__n_0\ : STD_LOGIC;
signal \_inferred__3/i__n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_3_n_0 : STD_LOGIC;
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__0_n_0\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \_inferred__2/i_\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \_inferred__3/i_\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair23";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\_inferred__0/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => gray2bin(1)
);
\_inferred__2/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_6_out(1),
I1 => p_6_out(0),
I2 => p_6_out(3),
I3 => p_6_out(2),
O => \_inferred__2/i__n_0\
);
\_inferred__3/i_\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_6_out(2),
I1 => p_6_out(1),
I2 => p_6_out(3),
O => \_inferred__3/i__n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized0_32\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3 downto 0) => wr_pntr_gc(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized1_33\
port map (
AR(0) => AR(0),
CLK => CLK,
D(3 downto 0) => p_4_out(3 downto 0),
Q(3 downto 0) => rd_pntr_gc(3 downto 0)
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized2_34\
port map (
D(0) => gray2bin(2),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\system_axi_ethernetlite_0_0_synchronizer_ff__parameterized3_35\
port map (
AR(0) => AR(0),
CLK => CLK,
D(0) => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
\out\(3 downto 0) => p_6_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \_inferred__2/i__n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \_inferred__3/i__n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => p_6_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => p_22_out(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => p_22_out(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(2),
Q => p_22_out(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => p_22_out(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => wr_pntr_gc(3)
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"BAABAAAAAAAABAAB"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => ram_empty_i_i_3_n_0,
I2 => p_22_out(2),
I3 => Q(2),
I4 => p_22_out(1),
I5 => Q(1),
O => ram_empty_fb_i_reg
);
ram_empty_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"2002000000002002"
)
port map (
I0 => E(0),
I1 => ram_empty_i_i_4_n_0,
I2 => p_22_out(1),
I3 => \gc0.count_reg[3]\(1),
I4 => p_22_out(0),
I5 => \gc0.count_reg[3]\(0),
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(3),
I1 => Q(3),
I2 => p_22_out(0),
I3 => Q(0),
O => ram_empty_i_i_3_n_0
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_22_out(2),
I1 => \gc0.count_reg[3]\(2),
I2 => p_22_out(3),
I3 => \gc0.count_reg[3]\(3),
O => ram_empty_i_i_4_n_0
);
\ram_full_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__0_n_0\,
I1 => ram_full_i_reg,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__0_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__0_n_0\
);
\ram_full_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_memory is
port (
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_phy_tx_en_i_p : in STD_LOGIC;
fifo_tx_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_memory : entity is "memory";
end system_axi_ethernetlite_0_0_memory;
architecture STRUCTURE of system_axi_ethernetlite_0_0_memory is
begin
\gdm.dm_gen.dm\: entity work.system_axi_ethernetlite_0_0_dmem
port map (
AR(0) => AR(0),
D(3 downto 0) => D(3 downto 0),
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en_reg(0) => fifo_tx_en_reg(0),
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_memory_21 is
port (
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
CLK : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
startReadDestAdrNib : in STD_LOGIC;
\gv.ram_valid_d1_reg\ : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\out\ : in STD_LOGIC;
state0a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
ram_empty_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_memory_21 : entity is "memory";
end system_axi_ethernetlite_0_0_memory_21;
architecture STRUCTURE of system_axi_ethernetlite_0_0_memory_21 is
begin
\gdm.dm_gen.dm\: entity work.system_axi_ethernetlite_0_0_dmem_27
port map (
AR(0) => AR(0),
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gv.ram_valid_d1_reg\ => \gv.ram_valid_d1_reg\,
\out\ => \out\,
preamble => preamble,
ram_empty_fb_i_reg(0) => ram_empty_fb_i_reg(0),
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_logic is
port (
\out\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
fifo_tx_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_logic : entity is "rd_logic";
end system_axi_ethernetlite_0_0_rd_logic;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
E(0) <= \^e\(0);
\gras.rsts\: entity work.system_axi_ethernetlite_0_0_rd_status_flags_as
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
fifo_tx_en => fifo_tx_en,
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk
);
rpntr: entity work.system_axi_ethernetlite_0_0_rd_bin_cntr
port map (
AR(0) => AR(0),
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3 downto 0) => Q(3 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
phy_tx_clk => phy_tx_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rd_logic_19 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
state0a : out STD_LOGIC;
\gc0.count_d1_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
rxCrcRst : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rd_logic_19 : entity is "rd_logic";
end system_axi_ethernetlite_0_0_rd_logic_19;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rd_logic_19 is
signal \^out\ : STD_LOGIC;
signal \^state1a\ : STD_LOGIC;
begin
\out\ <= \^out\;
state1a <= \^state1a\;
\gras.rsts\: entity work.system_axi_ethernetlite_0_0_rd_status_flags_as_30
port map (
AR(0) => AR(0),
Q(0) => Q(1),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\gv.ram_valid_d1_reg\ => \^state1a\,
\out\ => \^out\,
ping_rx_status_reg => ping_rx_status_reg,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
rxCrcRst => rxCrcRst,
s_axi_aclk => s_axi_aclk,
state0a => state0a_0,
state1a => state1a_0
);
\grhf.rhf\: entity work.system_axi_ethernetlite_0_0_rd_handshaking_flags
port map (
AR(0) => AR(0),
Q(0) => Q(0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\out\ => \^out\,
ping_rx_status_reg => ping_rx_status_reg,
ram_valid_i => ram_valid_i,
s_axi_aclk => s_axi_aclk,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state1a => \^state1a\
);
rpntr: entity work.system_axi_ethernetlite_0_0_rd_bin_cntr_31
port map (
AR(0) => AR(0),
E(0) => E(0),
Q(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end system_axi_ethernetlite_0_0_reset_blk_ramfifo;
architecture STRUCTURE of system_axi_ethernetlite_0_0_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
phy_tx_clk => phy_tx_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_8
port map (
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_9
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
phy_tx_clk => phy_tx_clk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_10
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
in0(0) => wr_rst_asreg,
\out\ => p_8_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => phy_tx_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => '0',
PRE => Rst0,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => phy_tx_clk,
CE => '1',
D => rst_rd_reg1,
PRE => Rst0,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => Rst0,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => Rst0,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_reset_blk_ramfifo_22 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
scndry_out : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_reset_blk_ramfifo_22 : entity is "reset_blk_ramfifo";
end system_axi_ethernetlite_0_0_reset_blk_ramfifo_22;
architecture STRUCTURE of system_axi_ethernetlite_0_0_reset_blk_ramfifo_22 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\ : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_23
port map (
in0(0) => rd_rst_asreg,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
\out\ => p_7_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_24
port map (
CLK => CLK,
in0(0) => wr_rst_asreg,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_25
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
in0(0) => rd_rst_asreg,
\out\ => p_7_out,
s_axi_aclk => s_axi_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.system_axi_ethernetlite_0_0_synchronizer_ff_26
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
CLK => CLK,
in0(0) => wr_rst_asreg,
\out\ => p_8_out
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => '0',
PRE => scndry_out,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => scndry_out,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => scndry_out,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => CLK,
CE => '1',
D => rst_wr_reg1,
PRE => scndry_out,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => CLK,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_logic is
port (
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
D18_out : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_logic : entity is "wr_logic";
end system_axi_ethernetlite_0_0_wr_logic;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_logic is
begin
\gwas.wsts\: entity work.system_axi_ethernetlite_0_0_wr_status_flags_as
port map (
D18_out => D18_out,
STATE14A => STATE14A,
STATE16A => STATE16A,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => \grstd1.grst_full.grst_f.rst_d3_reg\,
\out\ => \out\,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
wpntr: entity work.system_axi_ethernetlite_0_0_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => E(0),
Q(3 downto 0) => Q(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
ram_full_fb_i_reg => ram_full_fb_i_reg,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_wr_logic_20 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
CLK : in STD_LOGIC;
\out\ : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_wr_logic_20 : entity is "wr_logic";
end system_axi_ethernetlite_0_0_wr_logic_20;
architecture STRUCTURE of system_axi_ethernetlite_0_0_wr_logic_20 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.system_axi_ethernetlite_0_0_wr_status_flags_as_28
port map (
CLK => CLK,
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.system_axi_ethernetlite_0_0_wr_bin_cntr_29
port map (
AR(0) => AR(0),
CLK => CLK,
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_emac_dpram is
port (
doutb : out STD_LOGIC_VECTOR ( 26 downto 0 );
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\rxbuffer_addr_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\reg_data_out_reg[2]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[8]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg_access_reg : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_51_in : in STD_LOGIC;
p_69_in : in STD_LOGIC;
p_68_in288_in : in STD_LOGIC;
p_81_in330_in : in STD_LOGIC;
p_80_in328_in : in STD_LOGIC;
\reg_data_out_reg[31]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_emac_dpram : entity is "emac_dpram";
end system_axi_ethernetlite_0_0_emac_dpram;
architecture STRUCTURE of system_axi_ethernetlite_0_0_emac_dpram is
begin
\xpm_mem_gen.xpm_memory_inst\: entity work.system_axi_ethernetlite_0_0_xpm_memory_tdpram_6
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
D(4 downto 0) => D(4 downto 0),
\MDIO_GEN.mdio_data_out_reg[8]\(1 downto 0) => \MDIO_GEN.mdio_data_out_reg[8]\(1 downto 0),
Q(3 downto 0) => Q(3 downto 0),
doutb(26 downto 0) => doutb(26 downto 0),
ena => ena,
\gen_wr_b.gen_word_wide.mem_reg\(4 downto 0) => \gen_wr_b.gen_word_wide.mem_reg\(4 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_0\(4 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_0\(4 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_1\(4 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_1\(4 downto 0),
p_51_in => p_51_in,
p_68_in288_in => p_68_in288_in,
p_69_in => p_69_in,
p_80_in328_in => p_80_in328_in,
p_81_in330_in => p_81_in330_in,
reg_access_reg => reg_access_reg,
\reg_data_out_reg[2]\ => \reg_data_out_reg[2]\,
\reg_data_out_reg[31]\ => \reg_data_out_reg[31]\,
\rxbuffer_addr_reg[0]\(11 downto 0) => \rxbuffer_addr_reg[0]\(11 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_emac_dpram_1 is
port (
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
state0a : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
\rxbuffer_addr_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_emac_dpram_1 : entity is "emac_dpram";
end system_axi_ethernetlite_0_0_emac_dpram_1;
architecture STRUCTURE of system_axi_ethernetlite_0_0_emac_dpram_1 is
begin
\xpm_mem_gen.xpm_memory_inst\: entity work.system_axi_ethernetlite_0_0_xpm_memory_tdpram_5
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
Q(3 downto 0) => Q(3 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
\rxbuffer_addr_reg[0]\(11 downto 0) => \rxbuffer_addr_reg[0]\(11 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
state0a => state0a,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_emac_dpram_2 is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\TX_PONG_GEN.tx_pong_ping_l_reg\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
tx_idle : in STD_LOGIC;
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_emac_dpram_2 : entity is "emac_dpram";
end system_axi_ethernetlite_0_0_emac_dpram_2;
architecture STRUCTURE of system_axi_ethernetlite_0_0_emac_dpram_2 is
begin
\xpm_mem_gen.xpm_memory_inst\: entity work.system_axi_ethernetlite_0_0_xpm_memory_tdpram_4
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0),
\TX_PONG_GEN.tx_pong_ping_l_reg\ => \TX_PONG_GEN.tx_pong_ping_l_reg\,
addra(11 downto 0) => addra(11 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
enb => enb,
\gen_wr_b.gen_word_wide.mem_reg\(0) => \gen_wr_b.gen_word_wide.mem_reg\(0),
\rdDestAddrNib_D_t_q_reg[1]\(0) => \rdDestAddrNib_D_t_q_reg[1]\(0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
tx_idle => tx_idle,
tx_pong_ping_l => tx_pong_ping_l,
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_emac_dpram_3 is
port (
douta : out STD_LOGIC_VECTOR ( 3 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 4 downto 0 );
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 26 downto 0 );
s_axi_aclk : in STD_LOGIC;
\TX_PONG_GEN.tx_pong_ping_l_reg\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
tx_idle : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\reg_data_out_reg[0]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 8 downto 0 );
reg_access_reg : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg_2\ : in STD_LOGIC_VECTOR ( 26 downto 0 );
\reg_data_out_reg[1]\ : in STD_LOGIC;
p_21_in144_in : in STD_LOGIC;
p_27_in163_in : in STD_LOGIC;
p_33_in182_in : in STD_LOGIC;
p_39_in : in STD_LOGIC;
p_45_in : in STD_LOGIC;
p_57_in : in STD_LOGIC;
p_63_in : in STD_LOGIC;
p_75_in309_in : in STD_LOGIC;
p_74_in307_in : in STD_LOGIC;
p_87_in351_in : in STD_LOGIC;
p_86_in349_in : in STD_LOGIC;
p_93_in : in STD_LOGIC;
p_92_in368_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_emac_dpram_3 : entity is "emac_dpram";
end system_axi_ethernetlite_0_0_emac_dpram_3;
architecture STRUCTURE of system_axi_ethernetlite_0_0_emac_dpram_3 is
begin
\xpm_mem_gen.xpm_memory_inst\: entity work.system_axi_ethernetlite_0_0_xpm_memory_tdpram
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
D(26 downto 0) => D(26 downto 0),
Q(8 downto 0) => Q(8 downto 0),
\TX_PONG_GEN.tx_pong_ping_l_reg\ => \TX_PONG_GEN.tx_pong_ping_l_reg\,
addra(11 downto 0) => addra(11 downto 0),
douta(3 downto 0) => douta(3 downto 0),
doutb(4 downto 0) => doutb(4 downto 0),
\gen_wr_b.gen_word_wide.mem_reg\(2 downto 0) => \gen_wr_b.gen_word_wide.mem_reg\(2 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_0\(26 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_0\(26 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_1\(26 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_1\(26 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_2\(26 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_2\(26 downto 0),
p_21_in144_in => p_21_in144_in,
p_27_in163_in => p_27_in163_in,
p_33_in182_in => p_33_in182_in,
p_39_in => p_39_in,
p_45_in => p_45_in,
p_57_in => p_57_in,
p_63_in => p_63_in,
p_74_in307_in => p_74_in307_in,
p_75_in309_in => p_75_in309_in,
p_86_in349_in => p_86_in349_in,
p_87_in351_in => p_87_in351_in,
p_92_in368_in => p_92_in368_in,
p_93_in => p_93_in,
\rdDestAddrNib_D_t_q_reg[1]\(2 downto 0) => \rdDestAddrNib_D_t_q_reg[1]\(2 downto 0),
reg_access_reg => reg_access_reg,
\reg_data_out_reg[0]\ => \reg_data_out_reg[0]\,
\reg_data_out_reg[1]\ => \reg_data_out_reg[1]\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
tx_idle => tx_idle,
tx_pong_ping_l => tx_pong_ping_l,
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_ramfifo is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end system_axi_ethernetlite_0_0_fifo_generator_ramfifo;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_1\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_8\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_7\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rstblk_n_6 : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_axi_ethernetlite_0_0_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_7\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_8\,
E(0) => E(0),
Q(3 downto 0) => wr_pntr_plus2(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
fifo_tx_en_reg(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gc0.count_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]_0\ => \gntv_or_sync_fifo.gl0.wr_n_7\,
\grstd1.grst_full.grst_f.rst_d3_reg\ => rstblk_n_6,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_5_out(3 downto 0),
phy_tx_clk => phy_tx_clk,
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(3 downto 0) => p_23_out(3 downto 0),
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_5_out(1),
I1 => p_5_out(0),
I2 => p_5_out(3),
I3 => p_5_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_axi_ethernetlite_0_0_rd_logic
port map (
AR(0) => rd_rst_i(2),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_7\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_8\,
E(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
Q(3 downto 0) => rd_pntr_plus1(3 downto 0),
fifo_tx_en => fifo_tx_en,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_axi_ethernetlite_0_0_wr_logic
port map (
AR(0) => wr_rst_i(1),
D18_out => D18_out,
E(0) => E(0),
Q(3 downto 0) => wr_pntr_plus2(3 downto 0),
STATE14A => STATE14A,
STATE16A => STATE16A,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(3 downto 0) => p_23_out(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_7\,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
\gntv_or_sync_fifo.mem\: entity work.system_axi_ethernetlite_0_0_memory
port map (
AR(0) => rd_rst_i(0),
D(3 downto 0) => D(3 downto 0),
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en_reg(0) => \gntv_or_sync_fifo.gl0.rd_n_1\,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk
);
rstblk: entity work.system_axi_ethernetlite_0_0_reset_blk_ramfifo
port map (
Rst0 => Rst0,
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
phy_tx_clk => phy_tx_clk,
ram_full_fb_i_reg => rstblk_n_6,
s_axi_aclk => s_axi_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17 : entity is "fifo_generator_ramfifo";
end system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17 is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_10\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_11\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_12\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^out\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rstblk_n_6 : STD_LOGIC;
signal \^state1a\ : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\out\ <= \^out\;
state1a <= \^state1a\;
\gntv_or_sync_fifo.gcx.clkx\: entity work.system_axi_ethernetlite_0_0_clk_x_pntrs_18
port map (
AR(0) => wr_rst_i(0),
CLK => CLK,
D(0) => gray2bin(0),
E(0) => E(0),
Q(3 downto 0) => p_0_out(3 downto 0),
\gc0.count_d1_reg[3]\(2) => \gntv_or_sync_fifo.gl0.rd_n_10\,
\gc0.count_d1_reg[3]\(1) => \gntv_or_sync_fifo.gl0.rd_n_11\,
\gc0.count_d1_reg[3]\(0) => \gntv_or_sync_fifo.gl0.rd_n_12\,
\gc0.count_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => rstblk_n_6,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_5_out(3 downto 0),
ram_empty_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_5\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_axi_aclk => s_axi_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_5_out(1),
I1 => p_5_out(0),
I2 => p_5_out(3),
I3 => p_5_out(2),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.system_axi_ethernetlite_0_0_rd_logic_19
port map (
AR(0) => rd_rst_i(2),
E(0) => E(0),
Q(1 downto 0) => \^q\(1 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
\gc0.count_d1_reg[3]\(3 downto 0) => rd_pntr_plus1(3 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_10\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_11\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_12\,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \^out\,
ping_rx_status_reg => ping_rx_status_reg,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
rxCrcRst => rxCrcRst,
s_axi_aclk => s_axi_aclk,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => \^state1a\,
state1a_0 => state1a_0
);
\gntv_or_sync_fifo.gl0.wr\: entity work.system_axi_ethernetlite_0_0_wr_logic_20
port map (
AR(0) => wr_rst_i(1),
CLK => CLK,
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_5\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.system_axi_ethernetlite_0_0_memory_21
port map (
AR(0) => rd_rst_i(0),
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => p_18_out,
Q(5 downto 0) => \^q\(5 downto 0),
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gv.ram_valid_d1_reg\ => \^state1a\,
\out\ => \^out\,
preamble => preamble,
ram_empty_fb_i_reg(0) => E(0),
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a_0,
state2a => state2a,
state3a => state3a
);
rstblk: entity work.system_axi_ethernetlite_0_0_reset_blk_ramfifo_22
port map (
CLK => CLK,
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => rstblk_n_6,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_top is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_top : entity is "fifo_generator_top";
end system_axi_ethernetlite_0_0_fifo_generator_top;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_top is
begin
\grf.rf\: entity work.system_axi_ethernetlite_0_0_fifo_generator_ramfifo
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => STATE16A,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_top_16 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_top_16 : entity is "fifo_generator_top";
end system_axi_ethernetlite_0_0_fifo_generator_top_16;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_top_16 is
begin
\grf.rf\: entity work.system_axi_ethernetlite_0_0_fifo_generator_ramfifo_17
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => state1a,
state1a_0 => state1a_0,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth : entity is "fifo_generator_v13_1_3_synth";
end system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth is
begin
\gconvfifo.rf\: entity work.system_axi_ethernetlite_0_0_fifo_generator_top
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => STATE16A,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15 : entity is "fifo_generator_v13_1_3_synth";
end system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15 is
begin
\gconvfifo.rf\: entity work.system_axi_ethernetlite_0_0_fifo_generator_top_16
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => state1a,
state1a_0 => state1a_0,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_v13_1_3 is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3 : entity is "fifo_generator_v13_1_3";
end system_axi_ethernetlite_0_0_fifo_generator_v13_1_3;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3 is
begin
inst_fifo_gen: entity work.system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => STATE16A,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14 : entity is "fifo_generator_v13_1_3";
end system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14;
architecture STRUCTURE of system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14 is
begin
inst_fifo_gen: entity work.system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_synth_15
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => state1a,
state1a_0 => state1a_0,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_async_fifo_fg is
port (
\out\ : out STD_LOGIC;
STATE16A : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Rst0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
txfifo_empty : in STD_LOGIC;
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_async_fifo_fg : entity is "async_fifo_fg";
end system_axi_ethernetlite_0_0_async_fifo_fg;
architecture STRUCTURE of system_axi_ethernetlite_0_0_async_fifo_fg is
begin
\LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM\: entity work.system_axi_ethernetlite_0_0_fifo_generator_v13_1_3
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => STATE16A,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => \out\,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_async_fifo_fg_13 is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
state1a : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a_0 : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
scndry_out : in STD_LOGIC;
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_async_fifo_fg_13 : entity is "async_fifo_fg";
end system_axi_ethernetlite_0_0_async_fifo_fg_13;
architecture STRUCTURE of system_axi_ethernetlite_0_0_async_fifo_fg_13 is
begin
\LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM\: entity work.system_axi_ethernetlite_0_0_fifo_generator_v13_1_3_14
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => scndry_out,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => state1a,
state1a_0 => state1a_0,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_rx_intrfce is
port (
\out\ : out STD_LOGIC;
\gpr1.dout_i_reg[0]\ : out STD_LOGIC;
rxBusFifoRdAck : out STD_LOGIC;
D6_out : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
state2a : out STD_LOGIC;
preamble : out STD_LOGIC;
D5_out : out STD_LOGIC;
D13_out : out STD_LOGIC;
goto_readDestAdrNib1 : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC;
D11_out : out STD_LOGIC;
state0a : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 6 downto 0 );
\crc_local_reg[13]\ : out STD_LOGIC;
busFifoData_is_5_d1_reg : out STD_LOGIC;
state1a : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
startReadDestAdrNib : in STD_LOGIC;
busFifoData_is_5_d1 : in STD_LOGIC;
rx_start : in STD_LOGIC;
sfd1CheckBusFifoEmpty : in STD_LOGIC;
state3a : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_0\ : in STD_LOGIC;
state0a_0 : in STD_LOGIC;
startReadDataNib : in STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[3]_1\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
ping_rx_status_reg : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : in STD_LOGIC;
\crc_local_reg[31]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
rxCrcRst : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_rx_intrfce : entity is "rx_intrfce";
end system_axi_ethernetlite_0_0_rx_intrfce;
architecture STRUCTURE of system_axi_ethernetlite_0_0_rx_intrfce is
signal rst_s : STD_LOGIC;
begin
CDC_FIFO_RST: entity work.system_axi_ethernetlite_0_0_cdc_sync_12
port map (
CLK => CLK,
SS(0) => SS(0),
scndry_out => rst_s
);
I_RX_FIFO: entity work.system_axi_ethernetlite_0_0_async_fifo_fg_13
port map (
CLK => CLK,
D(6 downto 0) => D(6 downto 0),
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => E(0),
Q(5 downto 0) => Q(5 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => busFifoData_is_5_d1_reg,
\crc_local_reg[13]\ => \crc_local_reg[13]\,
\crc_local_reg[31]\(9 downto 0) => \crc_local_reg[31]\(9 downto 0),
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \gpr1.dout_i_reg[0]\,
\out\ => \out\,
ping_rx_status_reg => ping_rx_status_reg,
preamble => preamble,
ram_valid_i => ram_valid_i,
\rdDestAddrNib_D_t_q_reg[1]\ => \rdDestAddrNib_D_t_q_reg[1]\,
\rdDestAddrNib_D_t_q_reg[3]\ => \rdDestAddrNib_D_t_q_reg[3]\,
\rdDestAddrNib_D_t_q_reg[3]_0\ => \rdDestAddrNib_D_t_q_reg[3]_0\,
\rdDestAddrNib_D_t_q_reg[3]_1\ => \rdDestAddrNib_D_t_q_reg[3]_1\,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
scndry_out => rst_s,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => state0a,
state0a_0 => state0a_0,
state1a => rxBusFifoRdAck,
state1a_0 => state1a,
state2a => state2a,
state3a => state3a
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_tx_intrfce is
port (
\out\ : out STD_LOGIC;
\gic0.gc0.count_reg[0]\ : out STD_LOGIC;
txfifo_empty : out STD_LOGIC;
D18_out : out STD_LOGIC;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
Rst0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
DIA : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
waitFifoEmpty : in STD_LOGIC;
STATE14A : in STD_LOGIC;
fifo_tx_en : in STD_LOGIC;
axi_phy_tx_en_i_p : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_tx_intrfce : entity is "tx_intrfce";
end system_axi_ethernetlite_0_0_tx_intrfce;
architecture STRUCTURE of system_axi_ethernetlite_0_0_tx_intrfce is
signal fifo_empty_c : STD_LOGIC;
signal fifo_empty_i : STD_LOGIC;
signal \^txfifo_empty\ : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of pipeIt : label is "FDR";
attribute box_type : string;
attribute box_type of pipeIt : label is "PRIMITIVE";
begin
txfifo_empty <= \^txfifo_empty\;
CDC_FIFO_EMPTY: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized2\
port map (
prmry_in => fifo_empty_i,
s_axi_aclk => s_axi_aclk,
scndry_out => fifo_empty_c
);
I_TX_FIFO: entity work.system_axi_ethernetlite_0_0_async_fifo_fg
port map (
D(3 downto 0) => D(3 downto 0),
D18_out => D18_out,
DIA(0) => DIA(0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => Q(3 downto 0),
Rst0 => Rst0,
STATE14A => STATE14A,
STATE16A => \out\,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => \gic0.gc0.count_reg[0]\,
\out\ => fifo_empty_i,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => \^txfifo_empty\,
waitFifoEmpty => waitFifoEmpty
);
pipeIt: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => fifo_empty_c,
Q => \^txfifo_empty\,
R => Rst0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_receive is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
wea : out STD_LOGIC_VECTOR ( 0 to 0 );
rx_addr_en : out STD_LOGIC;
checkingBroadcastAdr_reg_reg : out STD_LOGIC_VECTOR ( 3 downto 0 );
\rxbuffer_addr_reg[0]\ : out STD_LOGIC;
D_5 : out STD_LOGIC;
RX_DONE_D1_I : out STD_LOGIC;
ping_rx_status_reg : out STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : out STD_LOGIC;
ena : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
\rdDestAddrNib_D_t_q_reg[1]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[2]_0\ : in STD_LOGIC;
\emac_rx_rd_data_d1_reg[1]_0\ : in STD_LOGIC;
ping_rx_status_reg_0 : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ : in STD_LOGIC;
p_5_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_9_in : in STD_LOGIC_VECTOR ( 0 to 0 );
STATE17A : in STD_LOGIC;
tx_intr_en_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
rx_intr_en0 : in STD_LOGIC;
rx_pong_ping_l : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_receive : entity is "receive";
end system_axi_ethernetlite_0_0_receive;
architecture STRUCTURE of system_axi_ethernetlite_0_0_receive is
signal D : STD_LOGIC;
signal D11_out : STD_LOGIC;
signal D13_out : STD_LOGIC;
signal D5_out : STD_LOGIC;
signal D6_out : STD_LOGIC;
signal INST_CRCGENRX_n_10 : STD_LOGIC;
signal INST_CRCGENRX_n_9 : STD_LOGIC;
signal INST_RX_INTRFCE_n_10 : STD_LOGIC;
signal INST_RX_INTRFCE_n_11 : STD_LOGIC;
signal INST_RX_INTRFCE_n_15 : STD_LOGIC;
signal INST_RX_INTRFCE_n_16 : STD_LOGIC;
signal INST_RX_INTRFCE_n_18 : STD_LOGIC;
signal INST_RX_INTRFCE_n_26 : STD_LOGIC;
signal INST_RX_INTRFCE_n_27 : STD_LOGIC;
signal INST_RX_INTRFCE_n_28 : STD_LOGIC;
signal INST_RX_STATE_n_11 : STD_LOGIC;
signal INST_RX_STATE_n_14 : STD_LOGIC;
signal INST_RX_STATE_n_23 : STD_LOGIC;
signal INST_RX_STATE_n_8 : STD_LOGIC;
signal \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grhf.rhf/ram_valid_i\ : STD_LOGIC;
signal \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i\ : STD_LOGIC;
signal \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_2_out\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal busFifoData_is_5_d1 : STD_LOGIC;
signal \^checkingbroadcastadr_reg_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal crcokr1 : STD_LOGIC;
signal emac_rx_rd_data_i : STD_LOGIC_VECTOR ( 4 to 5 );
signal fifo_empty_i : STD_LOGIC;
signal goto_readDestAdrNib1 : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_1_in1_in : STD_LOGIC;
signal p_1_in4_in : STD_LOGIC;
signal p_1_in7_in : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_9_in_0 : STD_LOGIC;
signal parallel_crc : STD_LOGIC_VECTOR ( 11 downto 4 );
signal parallel_crc1 : STD_LOGIC;
signal rxBusFifoRdAck : STD_LOGIC;
signal rxComboCrcRst : STD_LOGIC;
signal rxCrcEn : STD_LOGIC;
signal rxCrcEn_d1 : STD_LOGIC;
signal rxCrcRst : STD_LOGIC;
signal rx_start : STD_LOGIC;
signal sfd1CheckBusFifoEmpty : STD_LOGIC;
signal startReadDataNib : STD_LOGIC;
signal startReadDestAdrNib : STD_LOGIC;
begin
Q(3 downto 0) <= \^q\(3 downto 0);
checkingBroadcastAdr_reg_reg(3 downto 0) <= \^checkingbroadcastadr_reg_reg\(3 downto 0);
INST_CRCGENRX: entity work.system_axi_ethernetlite_0_0_crcgenrx
port map (
D(6 downto 5) => parallel_crc(11 downto 10),
D(4 downto 3) => parallel_crc(8 downto 7),
D(2 downto 1) => parallel_crc(5 downto 4),
D(0) => parallel_crc1,
D_0 => D,
E(0) => rxCrcEn_d1,
Q(9) => p_1_in7_in,
Q(8) => p_1_in4_in,
Q(7) => p_1_in1_in,
Q(6) => p_1_in,
Q(5) => p_10_in,
Q(4) => p_9_in_0,
Q(3) => p_7_in,
Q(2) => p_6_in,
Q(1) => p_4_in,
Q(0) => INST_CRCGENRX_n_9,
SS(0) => rxComboCrcRst,
crcokdelay => INST_CRCGENRX_n_10,
crcokr1 => crcokr1,
\gpr1.dout_i_reg[2]\ => INST_RX_INTRFCE_n_26,
\gpr1.dout_i_reg[5]\(3 downto 0) => \^q\(3 downto 0),
rxCrcEn => rxCrcEn,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn
);
INST_RX_INTRFCE: entity work.system_axi_ethernetlite_0_0_rx_intrfce
port map (
CLK => CLK,
D(6 downto 5) => parallel_crc(11 downto 10),
D(4 downto 3) => parallel_crc(8 downto 7),
D(2 downto 1) => parallel_crc(5 downto 4),
D(0) => parallel_crc1,
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
E(0) => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i\,
Q(5 downto 2) => \^q\(3 downto 0),
Q(1) => emac_rx_rd_data_i(4),
Q(0) => emac_rx_rd_data_i(5),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg_0\,
SS(0) => SS(0),
busFifoData_is_5_d1 => busFifoData_is_5_d1,
busFifoData_is_5_d1_reg => INST_RX_INTRFCE_n_27,
\crc_local_reg[13]\ => INST_RX_INTRFCE_n_26,
\crc_local_reg[31]\(9) => p_1_in7_in,
\crc_local_reg[31]\(8) => p_1_in4_in,
\crc_local_reg[31]\(7) => p_1_in1_in,
\crc_local_reg[31]\(6) => p_1_in,
\crc_local_reg[31]\(5) => p_10_in,
\crc_local_reg[31]\(4) => p_9_in_0,
\crc_local_reg[31]\(3) => p_7_in,
\crc_local_reg[31]\(2) => p_6_in,
\crc_local_reg[31]\(1) => p_4_in,
\crc_local_reg[31]\(0) => INST_CRCGENRX_n_9,
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[0]\ => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_2_out\,
\out\ => fifo_empty_i,
ping_rx_status_reg => ping_rx_status_reg_0,
preamble => INST_RX_INTRFCE_n_11,
ram_valid_i => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grhf.rhf/ram_valid_i\,
\rdDestAddrNib_D_t_q_reg[1]\ => INST_RX_INTRFCE_n_16,
\rdDestAddrNib_D_t_q_reg[3]\ => INST_RX_INTRFCE_n_15,
\rdDestAddrNib_D_t_q_reg[3]_0\ => INST_RX_STATE_n_8,
\rdDestAddrNib_D_t_q_reg[3]_1\ => INST_RX_STATE_n_23,
rxBusFifoRdAck => rxBusFifoRdAck,
rxCrcRst => rxCrcRst,
rx_start => rx_start,
s_axi_aclk => s_axi_aclk,
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state0a => INST_RX_INTRFCE_n_18,
state0a_0 => INST_RX_STATE_n_11,
state1a => INST_RX_INTRFCE_n_28,
state2a => INST_RX_INTRFCE_n_10,
state3a => INST_RX_STATE_n_14
);
INST_RX_STATE: entity work.system_axi_ethernetlite_0_0_rx_statemachine
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
\AXI4_LITE_IF_GEN.write_in_prog_reg\ => \AXI4_LITE_IF_GEN.write_in_prog_reg\,
D => D,
D11_out => D11_out,
D13_out => D13_out,
D5_out => D5_out,
D6_out => D6_out,
D_5 => D_5,
E(0) => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/ram_rd_en_i\,
Q(2) => \^q\(3),
Q(1) => emac_rx_rd_data_i(4),
Q(0) => emac_rx_rd_data_i(5),
RX_DONE_D1_I => RX_DONE_D1_I,
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ => INST_RX_INTRFCE_n_28,
\RX_PONG_REG_GEN.pong_rx_status_reg_1\ => \RX_PONG_REG_GEN.pong_rx_status_reg_0\,
SS(0) => SS(0),
STATE17A => STATE17A,
busFifoData_is_5_d1 => busFifoData_is_5_d1,
\crc_local_reg[31]\(0) => rxComboCrcRst,
crcokdelay_0 => INST_CRCGENRX_n_10,
crcokr1 => crcokr1,
\emac_rx_rd_data_d1_reg[0]\(3 downto 0) => \^checkingbroadcastadr_reg_reg\(3 downto 0),
\emac_rx_rd_data_d1_reg[1]\ => \emac_rx_rd_data_d1_reg[1]_0\,
\emac_rx_rd_data_d1_reg[2]\ => \emac_rx_rd_data_d1_reg[2]_0\,
ena => ena,
\gen_wr_b.gen_word_wide.mem_reg\ => \gen_wr_b.gen_word_wide.mem_reg\,
goto_readDestAdrNib1 => goto_readDestAdrNib1,
\gpr1.dout_i_reg[1]\ => INST_RX_INTRFCE_n_10,
\gpr1.dout_i_reg[1]_0\ => INST_RX_INTRFCE_n_16,
\gpr1.dout_i_reg[2]\ => INST_RX_INTRFCE_n_11,
\gpr1.dout_i_reg[5]\ => INST_RX_INTRFCE_n_27,
\gv.ram_valid_d1_reg\ => INST_RX_INTRFCE_n_18,
\out\ => fifo_empty_i,
p_5_in(0) => p_5_in(0),
p_9_in(0) => p_9_in(0),
ping_rx_status_reg => ping_rx_status_reg,
ping_rx_status_reg_0 => ping_rx_status_reg_0,
ram_empty_fb_i_reg => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_2_out\,
ram_empty_i_reg => INST_RX_INTRFCE_n_15,
ram_valid_i => \I_RX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grhf.rhf/ram_valid_i\,
\rdDestAddrNib_D_t_q_reg[1]_0\ => INST_RX_STATE_n_11,
\rdDestAddrNib_D_t_q_reg[1]_1\(3 downto 0) => \rdDestAddrNib_D_t_q_reg[1]\(3 downto 0),
rxBusFifoRdAck => rxBusFifoRdAck,
rxCrcEn => rxCrcEn,
rxCrcEn_d1_reg => INST_RX_STATE_n_8,
rxCrcRst => rxCrcRst,
rx_addr_en => rx_addr_en,
rx_intr_en0 => rx_intr_en0,
rx_pong_ping_l => rx_pong_ping_l,
rx_start => rx_start,
\rxbuffer_addr_reg[0]\ => \rxbuffer_addr_reg[0]\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(0),
sfd1CheckBusFifoEmpty => sfd1CheckBusFifoEmpty,
startReadDataNib => startReadDataNib,
startReadDestAdrNib => startReadDestAdrNib,
state17a_0 => INST_RX_STATE_n_23,
state2a_0 => INST_RX_STATE_n_14,
tx_intr_en_reg(0) => tx_intr_en_reg(0),
wea(0) => wea(0)
);
\emac_rx_rd_data_d1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(3),
Q => \^checkingbroadcastadr_reg_reg\(3),
R => SS(0)
);
\emac_rx_rd_data_d1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(2),
Q => \^checkingbroadcastadr_reg_reg\(2),
R => SS(0)
);
\emac_rx_rd_data_d1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(1),
Q => \^checkingbroadcastadr_reg_reg\(1),
R => SS(0)
);
\emac_rx_rd_data_d1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(0),
Q => \^checkingbroadcastadr_reg_reg\(0),
R => SS(0)
);
rxCrcEn_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rxCrcEn,
Q => rxCrcEn_d1,
R => SS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_transmit is
port (
loopback_en_reg : out STD_LOGIC;
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
STATE24A : out STD_LOGIC;
mac_addr_ram_we : out STD_LOGIC;
\txbuffer_addr_reg[0]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 5 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
loopback_en_reg_0 : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : out STD_LOGIC;
tx_addr_en : out STD_LOGIC;
mac_addr_ram_addr_wr : out STD_LOGIC_VECTOR ( 0 to 3 );
prmry_vect_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
douta : in STD_LOGIC_VECTOR ( 3 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\tx_packet_length_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
phy_crs_d2 : in STD_LOGIC;
tx_clk_reg_d3 : in STD_LOGIC;
tx_clk_reg_d2 : in STD_LOGIC;
tx_done_d2 : in STD_LOGIC;
ping_mac_program_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
p_17_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\TX_PONG_REG_GEN.pong_mac_program_reg\ : in STD_LOGIC;
p_15_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rx_pong_ping_l : in STD_LOGIC;
rx_done_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_intr_en0 : in STD_LOGIC;
loopback_en_reg_1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_transmit : entity is "transmit";
end system_axi_ethernetlite_0_0_transmit;
architecture STRUCTURE of system_axi_ethernetlite_0_0_transmit is
signal CDC_TX_EN_n_0 : STD_LOGIC;
signal CE : STD_LOGIC;
signal CE_1 : STD_LOGIC;
signal D13_out : STD_LOGIC;
signal D18_out : STD_LOGIC;
signal D21_out : STD_LOGIC;
signal INST_CRCCOUNTER_n_5 : STD_LOGIC;
signal INST_CRCCOUNTER_n_6 : STD_LOGIC;
signal INST_TXBUSFIFOWRITENIBBLECOUNT_n_4 : STD_LOGIC;
signal INST_TXBUSFIFOWRITENIBBLECOUNT_n_5 : STD_LOGIC;
signal INST_TXNIBBLECOUNT_n_1 : STD_LOGIC;
signal INST_TXNIBBLECOUNT_n_3 : STD_LOGIC;
signal INST_TX_INTRFCE_n_1 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_13 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_14 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_15 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_16 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_17 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_18 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_19 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_20 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_35 : STD_LOGIC;
signal INST_TX_STATE_MACHINE_n_63 : STD_LOGIC;
signal \I_TX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_18_out\ : STD_LOGIC;
signal \NSR/nibData\ : STD_LOGIC;
signal ONR_HOT_MUX_n_4 : STD_LOGIC;
signal \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ : STD_LOGIC;
signal \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ : STD_LOGIC;
signal Rst0 : STD_LOGIC;
signal S : STD_LOGIC;
signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal S_0 : STD_LOGIC;
signal axi_phy_tx_en_i_p : STD_LOGIC;
signal axi_phy_tx_en_i_p0 : STD_LOGIC;
signal bus_combo : STD_LOGIC_VECTOR ( 5 downto 2 );
signal checkBusFifoFull : STD_LOGIC;
signal checkBusFifoFullCrc : STD_LOGIC;
signal crcCnt : STD_LOGIC_VECTOR ( 0 to 3 );
signal crcComboRst : STD_LOGIC;
signal currentTxBusFifoWrCnt : STD_LOGIC_VECTOR ( 8 to 11 );
signal currentTxNibbleCnt : STD_LOGIC_VECTOR ( 11 to 11 );
signal emac_tx_wr_d1 : STD_LOGIC;
signal emac_tx_wr_data_d1 : STD_LOGIC_VECTOR ( 0 to 3 );
signal emac_tx_wr_data_i : STD_LOGIC_VECTOR ( 0 to 3 );
signal emac_tx_wr_i : STD_LOGIC;
signal enblCRC : STD_LOGIC;
signal enblData : STD_LOGIC;
signal enblPreamble : STD_LOGIC;
signal fifo_tx_en : STD_LOGIC;
signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
signal \i__carry__1_i_1_n_0\ : STD_LOGIC;
signal \i__carry__1_i_2_n_0\ : STD_LOGIC;
signal \i__carry__1_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_1_n_0\ : STD_LOGIC;
signal \i__carry_i_2_n_0\ : STD_LOGIC;
signal \i__carry_i_3_n_0\ : STD_LOGIC;
signal \i__carry_i_4_n_0\ : STD_LOGIC;
signal \inst_deferral_state/thisState\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ldLngthCntr : STD_LOGIC;
signal mux_in_data : STD_LOGIC_VECTOR ( 16 to 19 );
signal p_1_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal txComboBusFifoWrCntRst : STD_LOGIC;
signal txComboNibbleCntRst : STD_LOGIC;
signal txCrcEn : STD_LOGIC;
signal txCrcEn_reg : STD_LOGIC;
signal txNibbleCnt_pad : STD_LOGIC_VECTOR ( 0 to 11 );
signal txNibbleCnt_pad0 : STD_LOGIC_VECTOR ( 11 downto 1 );
signal \txNibbleCnt_pad0_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__1_n_2\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry_n_0\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry_n_1\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry_n_2\ : STD_LOGIC;
signal \txNibbleCnt_pad0_inferred__0/i__carry_n_3\ : STD_LOGIC;
signal tx_d_rst : STD_LOGIC;
signal tx_en_i : STD_LOGIC;
signal tx_en_mod : STD_LOGIC;
signal txfifo_empty : STD_LOGIC;
signal txfifo_full : STD_LOGIC;
signal waitFifoEmpty : STD_LOGIC;
signal \NLW_txNibbleCnt_pad0_inferred__0/i__carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_txNibbleCnt_pad0_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\ : label is "soft_lutpair81";
begin
SS(0) <= \^ss\(0);
CDC_PHY_TX_RST: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized4\
port map (
phy_tx_clk => phy_tx_clk,
s_axi_aresetn => \^ss\(0),
scndry_out => tx_d_rst
);
CDC_TX_EN: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized3\
port map (
fifo_tx_en_reg => CDC_TX_EN_n_0,
phy_tx_clk => phy_tx_clk,
scndry_out => tx_d_rst,
tx_en_i => tx_en_i
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(2),
O => prmry_vect_in(0)
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(3),
O => prmry_vect_in(1)
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(4),
O => prmry_vect_in(2)
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_phy_tx_en_i_p,
I1 => bus_combo(5),
O => prmry_vect_in(3)
);
INST_CRCCOUNTER: entity work.\system_axi_ethernetlite_0_0_ld_arith_reg__parameterized1\
port map (
CE => CE,
DIA(0) => tx_en_mod,
\PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\,
S => S,
STATE15A => INST_CRCCOUNTER_n_5,
checkBusFifoFullCrc => checkBusFifoFullCrc,
crcCnt(0 to 3) => crcCnt(0 to 3),
enblCRC => enblCRC,
\gic0.gc0.count_reg[0]\ => INST_CRCCOUNTER_n_6,
\out\ => txfifo_full,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \^ss\(0),
tx_en_i => tx_en_i
);
INST_CRCGENTX: entity work.system_axi_ethernetlite_0_0_crcgentx
port map (
E(0) => \NSR/nibData\,
Q(3) => mux_in_data(16),
Q(2) => mux_in_data(17),
Q(1) => mux_in_data(18),
Q(0) => mux_in_data(19),
SR(0) => crcComboRst,
\emac_tx_wr_data_d1_reg[0]\(3) => emac_tx_wr_data_d1(0),
\emac_tx_wr_data_d1_reg[0]\(2) => emac_tx_wr_data_d1(1),
\emac_tx_wr_data_d1_reg[0]\(1) => emac_tx_wr_data_d1(2),
\emac_tx_wr_data_d1_reg[0]\(0) => emac_tx_wr_data_d1(3),
s_axi_aclk => s_axi_aclk,
txCrcEn_reg => txCrcEn_reg
);
INST_DEFERRAL_CONTROL: entity work.system_axi_ethernetlite_0_0_deferral
port map (
D13_out => D13_out,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ => INST_TXBUSFIFOWRITENIBBLECOUNT_n_5,
Q(1 downto 0) => \inst_deferral_state/thisState\(1 downto 0),
enblPreamble => enblPreamble,
ldLngthCntr => ldLngthCntr,
phy_crs_d2 => phy_crs_d2,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \^ss\(0),
tx_clk_reg_d2 => tx_clk_reg_d2,
tx_clk_reg_d3 => tx_clk_reg_d3,
tx_en_i => tx_en_i
);
INST_TXBUSFIFOWRITENIBBLECOUNT: entity work.\system_axi_ethernetlite_0_0_ld_arith_reg__parameterized0\
port map (
\PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\ => INST_TX_STATE_MACHINE_n_63,
\PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\,
\PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\,
STATE11A => INST_TXBUSFIFOWRITENIBBLECOUNT_n_4,
STATE9A => INST_TXBUSFIFOWRITENIBBLECOUNT_n_5,
currentTxBusFifoWrCnt(3) => currentTxBusFifoWrCnt(8),
currentTxBusFifoWrCnt(2) => currentTxBusFifoWrCnt(9),
currentTxBusFifoWrCnt(1) => currentTxBusFifoWrCnt(10),
currentTxBusFifoWrCnt(0) => currentTxBusFifoWrCnt(11),
emac_tx_wr_i => emac_tx_wr_i,
s_axi_aclk => s_axi_aclk,
txComboBusFifoWrCntRst => txComboBusFifoWrCntRst
);
INST_TXNIBBLECOUNT: entity work.system_axi_ethernetlite_0_0_ld_arith_reg
port map (
CE => CE_1,
D21_out => D21_out,
S => S_0,
STATE13A(0) => currentTxNibbleCnt(11),
STATE13A_0 => INST_TXNIBBLECOUNT_n_3,
checkBusFifoFull => checkBusFifoFull,
enblData => enblData,
\out\ => txfifo_full,
s_axi_aclk => s_axi_aclk,
txComboNibbleCntRst => txComboNibbleCntRst,
\txNibbleCnt_pad_reg[11]\ => INST_TXNIBBLECOUNT_n_1,
\tx_packet_length_reg[15]\(15 downto 0) => \tx_packet_length_reg[15]\(15 downto 0)
);
INST_TX_INTRFCE: entity work.system_axi_ethernetlite_0_0_tx_intrfce
port map (
D(3) => emac_tx_wr_data_i(0),
D(2) => emac_tx_wr_data_i(1),
D(1) => emac_tx_wr_data_i(2),
D(0) => emac_tx_wr_data_i(3),
D18_out => D18_out,
DIA(0) => tx_en_mod,
E(0) => \I_TX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_18_out\,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
Q(3 downto 0) => bus_combo(5 downto 2),
Rst0 => Rst0,
STATE14A => INST_CRCCOUNTER_n_6,
axi_phy_tx_en_i_p => axi_phy_tx_en_i_p,
fifo_tx_en => fifo_tx_en,
\gic0.gc0.count_reg[0]\ => INST_TX_INTRFCE_n_1,
\out\ => txfifo_full,
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
INST_TX_STATE_MACHINE: entity work.system_axi_ethernetlite_0_0_tx_statemachine
port map (
CE => CE_1,
CE_0 => CE,
D(11 downto 0) => p_1_in(11 downto 0),
D13_out => D13_out,
D18_out => D18_out,
D21_out => D21_out,
E(0) => \NSR/nibData\,
\PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[0].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[10].Q_I_GEN_ADD.q_i_ns_reg\,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1\ => INST_TX_STATE_MACHINE_n_63,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_0\(0) => currentTxNibbleCnt(11),
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_1\ => INST_TXBUSFIFOWRITENIBBLECOUNT_n_4,
\PERBIT_GEN[11].FF_RST0_GEN.FDRE_i1_2\ => INST_TXBUSFIFOWRITENIBBLECOUNT_n_5,
\PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[1].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[2].FF_RST0_GEN.FDRE_i1\ => INST_CRCCOUNTER_n_5,
\PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\ => \PERBIT_GEN[2].Q_I_GEN_SUB.q_i_ns_reg\,
\PERBIT_GEN[8].FF_RST0_GEN.FDRE_i1\ => INST_TXNIBBLECOUNT_n_3,
\PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[8].Q_I_GEN_ADD.q_i_ns_reg\,
\PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\ => \PERBIT_GEN[9].Q_I_GEN_ADD.q_i_ns_reg\,
Q(3) => mux_in_data(16),
Q(2) => mux_in_data(17),
Q(1) => mux_in_data(18),
Q(0) => mux_in_data(19),
Rst0 => Rst0,
S => S_0,
SR(0) => crcComboRst,
STATE14A_0 => INST_CRCCOUNTER_n_6,
STATE24A_0 => STATE24A,
S_1 => S,
\TX_PONG_REG_GEN.pong_mac_program_reg\ => \TX_PONG_REG_GEN.pong_mac_program_reg\,
axi_phy_tx_en_i_p0 => axi_phy_tx_en_i_p0,
checkBusFifoFull => checkBusFifoFull,
checkBusFifoFullCrc => checkBusFifoFullCrc,
crcCnt(0 to 3) => crcCnt(0 to 3),
currentTxBusFifoWrCnt(3) => currentTxBusFifoWrCnt(8),
currentTxBusFifoWrCnt(2) => currentTxBusFifoWrCnt(9),
currentTxBusFifoWrCnt(1) => currentTxBusFifoWrCnt(10),
currentTxBusFifoWrCnt(0) => currentTxBusFifoWrCnt(11),
douta(3 downto 0) => douta(3 downto 0),
emac_tx_wr_d1 => emac_tx_wr_d1,
\emac_tx_wr_data_d1_reg[0]\ => INST_TX_STATE_MACHINE_n_16,
\emac_tx_wr_data_d1_reg[0]_0\ => INST_TX_STATE_MACHINE_n_17,
\emac_tx_wr_data_d1_reg[1]\ => INST_TX_STATE_MACHINE_n_15,
\emac_tx_wr_data_d1_reg[1]_0\ => INST_TX_STATE_MACHINE_n_18,
\emac_tx_wr_data_d1_reg[2]\ => INST_TX_STATE_MACHINE_n_14,
\emac_tx_wr_data_d1_reg[2]_0\ => INST_TX_STATE_MACHINE_n_20,
\emac_tx_wr_data_d1_reg[3]\ => INST_TX_STATE_MACHINE_n_13,
\emac_tx_wr_data_d1_reg[3]_0\ => INST_TX_STATE_MACHINE_n_19,
emac_tx_wr_i => emac_tx_wr_i,
enblCRC => enblCRC,
enblData => enblData,
enblPreamble => enblPreamble,
\gen_wr_b.gen_word_wide.mem_reg\ => \gen_wr_b.gen_word_wide.mem_reg\,
\gen_wr_b.gen_word_wide.mem_reg_0\ => \gen_wr_b.gen_word_wide.mem_reg_0\,
\gen_wr_b.gen_word_wide.mem_reg_1\(3 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_1\(3 downto 0),
\gic0.gc0.count_reg[0]\(0) => \I_TX_FIFO/LEGACY_COREGEN_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/p_18_out\,
ldLngthCntr => ldLngthCntr,
loopback_en_reg => loopback_en_reg,
loopback_en_reg_0 => loopback_en_reg_0,
loopback_en_reg_1 => loopback_en_reg_1,
mac_addr_ram_addr_wr(0 to 3) => mac_addr_ram_addr_wr(0 to 3),
mac_addr_ram_we => mac_addr_ram_we,
\out\ => txfifo_full,
p_15_in(0) => p_15_in(0),
p_17_in(0) => p_17_in(0),
ping_mac_program_reg(0) => ping_mac_program_reg(0),
ram_full_fb_i_reg => INST_TX_INTRFCE_n_1,
rx_done_d1 => rx_done_d1,
rx_pong_ping_l => rx_pong_ping_l,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(0),
\status_reg_reg[0]\(0) => E(0),
\status_reg_reg[5]\(5 downto 0) => D(5 downto 0),
\thisState_reg[1]\(1 downto 0) => \inst_deferral_state/thisState\(1 downto 0),
transmit_start_reg_reg_0 => \^ss\(0),
txComboBusFifoWrCntRst => txComboBusFifoWrCntRst,
txComboNibbleCntRst => txComboNibbleCntRst,
txCrcEn => txCrcEn,
txCrcEn_reg => txCrcEn_reg,
txNibbleCnt_pad0(10 downto 0) => txNibbleCnt_pad0(11 downto 1),
\txNibbleCnt_pad_reg[11]\(0) => INST_TX_STATE_MACHINE_n_35,
\txNibbleCnt_pad_reg[11]_0\ => ONR_HOT_MUX_n_4,
\txNibbleCnt_pad_reg[11]_1\(0) => txNibbleCnt_pad(11),
tx_addr_en => tx_addr_en,
tx_done_d2 => tx_done_d2,
tx_en_i => tx_en_i,
tx_intr_en0 => tx_intr_en0,
\tx_packet_length_reg[10]\(10 downto 0) => \tx_packet_length_reg[15]\(10 downto 0),
\tx_packet_length_reg[9]\ => INST_TXNIBBLECOUNT_n_1,
tx_pong_ping_l => tx_pong_ping_l,
\txbuffer_addr_reg[0]\ => \txbuffer_addr_reg[0]\,
txfifo_empty => txfifo_empty,
waitFifoEmpty => waitFifoEmpty
);
ONR_HOT_MUX: entity work.system_axi_ethernetlite_0_0_mux_onehot_f
port map (
D(3) => emac_tx_wr_data_i(0),
D(2) => emac_tx_wr_data_i(1),
D(1) => emac_tx_wr_data_i(2),
D(0) => emac_tx_wr_data_i(3),
Q(11) => txNibbleCnt_pad(0),
Q(10) => txNibbleCnt_pad(1),
Q(9) => txNibbleCnt_pad(2),
Q(8) => txNibbleCnt_pad(3),
Q(7) => txNibbleCnt_pad(4),
Q(6) => txNibbleCnt_pad(5),
Q(5) => txNibbleCnt_pad(6),
Q(4) => txNibbleCnt_pad(7),
Q(3) => txNibbleCnt_pad(8),
Q(2) => txNibbleCnt_pad(9),
Q(1) => txNibbleCnt_pad(10),
Q(0) => txNibbleCnt_pad(11),
STATE12A => INST_TX_STATE_MACHINE_n_20,
STATE15A => INST_TX_STATE_MACHINE_n_16,
STATE15A_0 => INST_TX_STATE_MACHINE_n_15,
STATE15A_1 => INST_TX_STATE_MACHINE_n_14,
STATE15A_2 => INST_TX_STATE_MACHINE_n_13,
\gen_wr_b.gen_word_wide.mem_reg\ => INST_TX_STATE_MACHINE_n_17,
\gen_wr_b.gen_word_wide.mem_reg_0\ => INST_TX_STATE_MACHINE_n_18,
\gen_wr_b.gen_word_wide.mem_reg_1\ => INST_TX_STATE_MACHINE_n_19,
\txNibbleCnt_pad_reg[11]\ => ONR_HOT_MUX_n_4
);
axi_phy_tx_en_i_p_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => axi_phy_tx_en_i_p0,
Q => axi_phy_tx_en_i_p,
R => \^ss\(0)
);
emac_tx_wr_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_i,
Q => emac_tx_wr_d1,
R => \^ss\(0)
);
\emac_tx_wr_data_d1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_data_i(0),
Q => emac_tx_wr_data_d1(0),
R => \^ss\(0)
);
\emac_tx_wr_data_d1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_data_i(1),
Q => emac_tx_wr_data_d1(1),
R => \^ss\(0)
);
\emac_tx_wr_data_d1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_data_i(2),
Q => emac_tx_wr_data_d1(2),
R => \^ss\(0)
);
\emac_tx_wr_data_d1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => emac_tx_wr_data_i(3),
Q => emac_tx_wr_data_d1(3),
R => \^ss\(0)
);
fifo_tx_en_reg: unisim.vcomponents.FDRE
port map (
C => phy_tx_clk,
CE => '1',
D => CDC_TX_EN_n_0,
Q => fifo_tx_en,
R => '0'
);
\i__carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(3),
O => \i__carry__0_i_1_n_0\
);
\i__carry__0_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(4),
O => \i__carry__0_i_2_n_0\
);
\i__carry__0_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(5),
O => \i__carry__0_i_3_n_0\
);
\i__carry__0_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(6),
O => \i__carry__0_i_4_n_0\
);
\i__carry__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(0),
O => \i__carry__1_i_1_n_0\
);
\i__carry__1_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(1),
O => \i__carry__1_i_2_n_0\
);
\i__carry__1_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(2),
O => \i__carry__1_i_3_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(7),
O => \i__carry_i_1_n_0\
);
\i__carry_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(8),
O => \i__carry_i_2_n_0\
);
\i__carry_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(9),
O => \i__carry_i_3_n_0\
);
\i__carry_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => txNibbleCnt_pad(10),
O => \i__carry_i_4_n_0\
);
\txNibbleCnt_pad0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \txNibbleCnt_pad0_inferred__0/i__carry_n_0\,
CO(2) => \txNibbleCnt_pad0_inferred__0/i__carry_n_1\,
CO(1) => \txNibbleCnt_pad0_inferred__0/i__carry_n_2\,
CO(0) => \txNibbleCnt_pad0_inferred__0/i__carry_n_3\,
CYINIT => txNibbleCnt_pad(11),
DI(3) => txNibbleCnt_pad(7),
DI(2) => txNibbleCnt_pad(8),
DI(1) => txNibbleCnt_pad(9),
DI(0) => txNibbleCnt_pad(10),
O(3 downto 0) => txNibbleCnt_pad0(4 downto 1),
S(3) => \i__carry_i_1_n_0\,
S(2) => \i__carry_i_2_n_0\,
S(1) => \i__carry_i_3_n_0\,
S(0) => \i__carry_i_4_n_0\
);
\txNibbleCnt_pad0_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \txNibbleCnt_pad0_inferred__0/i__carry_n_0\,
CO(3) => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_0\,
CO(2) => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_1\,
CO(1) => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_2\,
CO(0) => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_3\,
CYINIT => '0',
DI(3) => txNibbleCnt_pad(3),
DI(2) => txNibbleCnt_pad(4),
DI(1) => txNibbleCnt_pad(5),
DI(0) => txNibbleCnt_pad(6),
O(3 downto 0) => txNibbleCnt_pad0(8 downto 5),
S(3) => \i__carry__0_i_1_n_0\,
S(2) => \i__carry__0_i_2_n_0\,
S(1) => \i__carry__0_i_3_n_0\,
S(0) => \i__carry__0_i_4_n_0\
);
\txNibbleCnt_pad0_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \txNibbleCnt_pad0_inferred__0/i__carry__0_n_0\,
CO(3 downto 2) => \NLW_txNibbleCnt_pad0_inferred__0/i__carry__1_CO_UNCONNECTED\(3 downto 2),
CO(1) => \txNibbleCnt_pad0_inferred__0/i__carry__1_n_2\,
CO(0) => \txNibbleCnt_pad0_inferred__0/i__carry__1_n_3\,
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => txNibbleCnt_pad(1),
DI(0) => txNibbleCnt_pad(2),
O(3) => \NLW_txNibbleCnt_pad0_inferred__0/i__carry__1_O_UNCONNECTED\(3),
O(2 downto 0) => txNibbleCnt_pad0(11 downto 9),
S(3) => '0',
S(2) => \i__carry__1_i_1_n_0\,
S(1) => \i__carry__1_i_2_n_0\,
S(0) => \i__carry__1_i_3_n_0\
);
\txNibbleCnt_pad_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(11),
Q => txNibbleCnt_pad(0),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(1),
Q => txNibbleCnt_pad(10),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(0),
Q => txNibbleCnt_pad(11),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(10),
Q => txNibbleCnt_pad(1),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(9),
Q => txNibbleCnt_pad(2),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(8),
Q => txNibbleCnt_pad(3),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(7),
Q => txNibbleCnt_pad(4),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(6),
Q => txNibbleCnt_pad(5),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(5),
Q => txNibbleCnt_pad(6),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(4),
Q => txNibbleCnt_pad(7),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(3),
Q => txNibbleCnt_pad(8),
R => \^ss\(0)
);
\txNibbleCnt_pad_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => INST_TX_STATE_MACHINE_n_35,
D => p_1_in(2),
Q => txNibbleCnt_pad(9),
R => \^ss\(0)
);
txcrcen_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => txCrcEn,
Q => txCrcEn_reg,
R => \^ss\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac is
port (
prmry_in : out STD_LOGIC;
tx_idle : out STD_LOGIC;
txDone : out STD_LOGIC;
addra : out STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_wr_b.gen_word_wide.mem_reg\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
wea : out STD_LOGIC_VECTOR ( 0 to 0 );
D_5 : out STD_LOGIC;
rx_done : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 5 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
loopback_en_reg : out STD_LOGIC;
ping_rx_status_reg : out STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg\ : out STD_LOGIC;
ena : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_0\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_1\ : out STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_2\ : out STD_LOGIC;
prmry_vect_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
phy_tx_clk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ping_rx_status_reg_0 : in STD_LOGIC;
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ : in STD_LOGIC;
douta : in STD_LOGIC_VECTOR ( 3 downto 0 );
tx_pong_ping_l : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_3\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\tx_packet_length_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
p_5_in : in STD_LOGIC_VECTOR ( 0 to 0 );
p_9_in : in STD_LOGIC_VECTOR ( 0 to 0 );
tx_intr_en_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
tx_done_d2 : in STD_LOGIC;
p_17_in : in STD_LOGIC_VECTOR ( 0 to 0 );
\TX_PONG_REG_GEN.pong_mac_program_reg\ : in STD_LOGIC;
p_15_in : in STD_LOGIC_VECTOR ( 0 to 0 );
rx_pong_ping_l : in STD_LOGIC;
rx_done_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 1 downto 0 );
tx_intr_en0 : in STD_LOGIC;
loopback_en_reg_0 : in STD_LOGIC;
rx_intr_en0 : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg\ : in STD_LOGIC;
\gen_wr_b.gen_word_wide.mem_reg_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac : entity is "axi_ethernetlite_v3_0_9_emac";
end system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac;
architecture STRUCTURE of system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac is
signal NODEMACADDRRAMI_n_0 : STD_LOGIC;
signal NODEMACADDRRAMI_n_1 : STD_LOGIC;
signal Phy_tx_clk_axi_d : STD_LOGIC;
signal RX_n_10 : STD_LOGIC;
signal TX_n_4 : STD_LOGIC;
signal \^addra\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal emac_rx_rd_data_d1 : STD_LOGIC_VECTOR ( 5 downto 2 );
signal \^gen_wr_b.gen_word_wide.mem_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal mac_addr_ram_addr : STD_LOGIC_VECTOR ( 0 to 3 );
signal mac_addr_ram_addr_rd : STD_LOGIC_VECTOR ( 0 to 3 );
signal mac_addr_ram_addr_wr : STD_LOGIC_VECTOR ( 0 to 3 );
signal mac_addr_ram_we : STD_LOGIC;
signal phy_crs_d1 : STD_LOGIC;
signal phy_crs_d2 : STD_LOGIC;
signal \^prmry_in\ : STD_LOGIC;
signal rx_addr_en : STD_LOGIC;
signal \rxbuffer_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[11]_i_6_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[11]_i_7_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[3]_i_2_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[7]_i_2_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \rxbuffer_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_0\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_4\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_5\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_6\ : STD_LOGIC;
signal \rxbuffer_addr_reg[11]_i_3_n_7\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \rxbuffer_addr_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \rxbuffer_addr_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \^txdone\ : STD_LOGIC;
signal tx_addr_en : STD_LOGIC;
signal tx_clk_reg_d1 : STD_LOGIC;
signal tx_clk_reg_d2 : STD_LOGIC;
signal tx_clk_reg_d3 : STD_LOGIC;
signal \txbuffer_addr[11]_i_4_n_0\ : STD_LOGIC;
signal \txbuffer_addr[11]_i_5_n_0\ : STD_LOGIC;
signal \txbuffer_addr[11]_i_6_n_0\ : STD_LOGIC;
signal \txbuffer_addr[11]_i_7_n_0\ : STD_LOGIC;
signal \txbuffer_addr[3]_i_2_n_0\ : STD_LOGIC;
signal \txbuffer_addr[3]_i_3_n_0\ : STD_LOGIC;
signal \txbuffer_addr[3]_i_4_n_0\ : STD_LOGIC;
signal \txbuffer_addr[3]_i_5_n_0\ : STD_LOGIC;
signal \txbuffer_addr[7]_i_2_n_0\ : STD_LOGIC;
signal \txbuffer_addr[7]_i_3_n_0\ : STD_LOGIC;
signal \txbuffer_addr[7]_i_4_n_0\ : STD_LOGIC;
signal \txbuffer_addr[7]_i_5_n_0\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_0\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_4\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_5\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_6\ : STD_LOGIC;
signal \txbuffer_addr_reg[11]_i_3_n_7\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_1\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_2\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_3\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_4\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_5\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_6\ : STD_LOGIC;
signal \txbuffer_addr_reg[3]_i_1_n_7\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_4\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_5\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_6\ : STD_LOGIC;
signal \txbuffer_addr_reg[7]_i_1_n_7\ : STD_LOGIC;
signal \NLW_rxbuffer_addr_reg[3]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_txbuffer_addr_reg[3]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of C_SENSE_SYNC_1 : label is "FDR";
attribute box_type : string;
attribute box_type of C_SENSE_SYNC_1 : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of C_SENSE_SYNC_2 : label is "FDR";
attribute box_type of C_SENSE_SYNC_2 : label is "PRIMITIVE";
begin
addra(11 downto 0) <= \^addra\(11 downto 0);
\gen_wr_b.gen_word_wide.mem_reg\(11 downto 0) <= \^gen_wr_b.gen_word_wide.mem_reg\(11 downto 0);
prmry_in <= \^prmry_in\;
txDone <= \^txdone\;
CDC_TX_CLK: entity work.system_axi_ethernetlite_0_0_cdc_sync_7
port map (
phy_tx_clk => phy_tx_clk,
s_axi_aclk => s_axi_aclk,
scndry_out => Phy_tx_clk_axi_d
);
C_SENSE_SYNC_1: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => phy_crs,
Q => phy_crs_d1,
R => \^prmry_in\
);
C_SENSE_SYNC_2: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => phy_crs_d1,
Q => phy_crs_d2,
R => \^prmry_in\
);
NODEMACADDRRAMI: entity work.system_axi_ethernetlite_0_0_MacAddrRAM
port map (
Q(3 downto 0) => emac_rx_rd_data_d1(5 downto 2),
\gen_wr_b.gen_word_wide.mem_reg\(3 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_4\(3 downto 0),
mac_addr_ram_addr(0 to 3) => mac_addr_ram_addr(0 to 3),
mac_addr_ram_we => mac_addr_ram_we,
\rdDestAddrNib_D_t_q_reg[1]\ => NODEMACADDRRAMI_n_0,
\rdDestAddrNib_D_t_q_reg[1]_0\ => NODEMACADDRRAMI_n_1,
s_axi_aclk => s_axi_aclk
);
RX: entity work.system_axi_ethernetlite_0_0_receive
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
\AXI4_LITE_IF_GEN.write_in_prog_reg\ => \AXI4_LITE_IF_GEN.write_in_prog_reg\,
CLK => CLK,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
D_5 => D_5,
Q(3 downto 0) => Q(3 downto 0),
RX_DONE_D1_I => rx_done,
\RX_PONG_REG_GEN.pong_rx_status_reg\ => \RX_PONG_REG_GEN.pong_rx_status_reg\,
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ => \RX_PONG_REG_GEN.pong_rx_status_reg_0\,
SS(0) => \^prmry_in\,
STATE17A => \^txdone\,
checkingBroadcastAdr_reg_reg(3 downto 0) => emac_rx_rd_data_d1(5 downto 2),
\emac_rx_rd_data_d1_reg[1]_0\ => NODEMACADDRRAMI_n_0,
\emac_rx_rd_data_d1_reg[2]_0\ => NODEMACADDRRAMI_n_1,
ena => ena,
\gen_wr_b.gen_word_wide.mem_reg\ => \gen_wr_b.gen_word_wide.mem_reg_0\,
p_5_in(0) => p_5_in(0),
p_9_in(0) => p_9_in(0),
ping_rx_status_reg => ping_rx_status_reg,
ping_rx_status_reg_0 => ping_rx_status_reg_0,
\rdDestAddrNib_D_t_q_reg[1]\(3) => mac_addr_ram_addr_rd(0),
\rdDestAddrNib_D_t_q_reg[1]\(2) => mac_addr_ram_addr_rd(1),
\rdDestAddrNib_D_t_q_reg[1]\(1) => mac_addr_ram_addr_rd(2),
\rdDestAddrNib_D_t_q_reg[1]\(0) => mac_addr_ram_addr_rd(3),
rx_addr_en => rx_addr_en,
rx_intr_en0 => rx_intr_en0,
rx_pong_ping_l => rx_pong_ping_l,
\rxbuffer_addr_reg[0]\ => RX_n_10,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(0),
tx_intr_en_reg(0) => tx_intr_en_reg(1),
wea(0) => wea(0)
);
TX: entity work.system_axi_ethernetlite_0_0_transmit
port map (
D(5 downto 0) => D(5 downto 0),
E(0) => E(0),
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\,
SS(0) => \^prmry_in\,
STATE24A => \^txdone\,
\TX_PONG_REG_GEN.pong_mac_program_reg\ => \TX_PONG_REG_GEN.pong_mac_program_reg\,
douta(3 downto 0) => douta(3 downto 0),
\gen_wr_b.gen_word_wide.mem_reg\ => \gen_wr_b.gen_word_wide.mem_reg_1\,
\gen_wr_b.gen_word_wide.mem_reg_0\ => \gen_wr_b.gen_word_wide.mem_reg_2\,
\gen_wr_b.gen_word_wide.mem_reg_1\(3 downto 0) => \gen_wr_b.gen_word_wide.mem_reg_3\(3 downto 0),
loopback_en_reg => tx_idle,
loopback_en_reg_0 => loopback_en_reg,
loopback_en_reg_1 => loopback_en_reg_0,
mac_addr_ram_addr_wr(0 to 3) => mac_addr_ram_addr_wr(0 to 3),
mac_addr_ram_we => mac_addr_ram_we,
p_15_in(0) => p_15_in(0),
p_17_in(0) => p_17_in(0),
phy_crs_d2 => phy_crs_d2,
phy_tx_clk => phy_tx_clk,
ping_mac_program_reg(0) => tx_intr_en_reg(0),
prmry_vect_in(3 downto 0) => prmry_vect_in(3 downto 0),
rx_done_d1 => rx_done_d1,
rx_pong_ping_l => rx_pong_ping_l,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(1),
tx_addr_en => tx_addr_en,
tx_clk_reg_d2 => tx_clk_reg_d2,
tx_clk_reg_d3 => tx_clk_reg_d3,
tx_done_d2 => tx_done_d2,
tx_intr_en0 => tx_intr_en0,
\tx_packet_length_reg[15]\(15 downto 0) => \tx_packet_length_reg[15]\(15 downto 0),
tx_pong_ping_l => tx_pong_ping_l,
\txbuffer_addr_reg[0]\ => TX_n_4
);
ram16x1_0_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_addr_ram_addr_wr(3),
I1 => mac_addr_ram_we,
I2 => mac_addr_ram_addr_rd(3),
O => mac_addr_ram_addr(3)
);
ram16x1_0_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_addr_ram_addr_wr(2),
I1 => mac_addr_ram_we,
I2 => mac_addr_ram_addr_rd(2),
O => mac_addr_ram_addr(2)
);
ram16x1_0_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_addr_ram_addr_wr(1),
I1 => mac_addr_ram_we,
I2 => mac_addr_ram_addr_rd(1),
O => mac_addr_ram_addr(1)
);
ram16x1_0_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => mac_addr_ram_addr_wr(0),
I1 => mac_addr_ram_we,
I2 => mac_addr_ram_addr_rd(0),
O => mac_addr_ram_addr(0)
);
\rxbuffer_addr[11]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(3),
O => \rxbuffer_addr[11]_i_4_n_0\
);
\rxbuffer_addr[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(2),
O => \rxbuffer_addr[11]_i_5_n_0\
);
\rxbuffer_addr[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(1),
O => \rxbuffer_addr[11]_i_6_n_0\
);
\rxbuffer_addr[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(0),
O => \rxbuffer_addr[11]_i_7_n_0\
);
\rxbuffer_addr[3]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(11),
O => \rxbuffer_addr[3]_i_2_n_0\
);
\rxbuffer_addr[3]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(10),
O => \rxbuffer_addr[3]_i_3_n_0\
);
\rxbuffer_addr[3]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(9),
O => \rxbuffer_addr[3]_i_4_n_0\
);
\rxbuffer_addr[3]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(8),
O => \rxbuffer_addr[3]_i_5_n_0\
);
\rxbuffer_addr[7]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(7),
O => \rxbuffer_addr[7]_i_2_n_0\
);
\rxbuffer_addr[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(6),
O => \rxbuffer_addr[7]_i_3_n_0\
);
\rxbuffer_addr[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(5),
O => \rxbuffer_addr[7]_i_4_n_0\
);
\rxbuffer_addr[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^gen_wr_b.gen_word_wide.mem_reg\(4),
O => \rxbuffer_addr[7]_i_5_n_0\
);
\rxbuffer_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[3]_i_1_n_4\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(11),
R => RX_n_10
);
\rxbuffer_addr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[11]_i_3_n_6\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(1),
R => RX_n_10
);
\rxbuffer_addr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[11]_i_3_n_7\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(0),
R => RX_n_10
);
\rxbuffer_addr_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \rxbuffer_addr_reg[11]_i_3_n_0\,
CO(2) => \rxbuffer_addr_reg[11]_i_3_n_1\,
CO(1) => \rxbuffer_addr_reg[11]_i_3_n_2\,
CO(0) => \rxbuffer_addr_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \rxbuffer_addr_reg[11]_i_3_n_4\,
O(2) => \rxbuffer_addr_reg[11]_i_3_n_5\,
O(1) => \rxbuffer_addr_reg[11]_i_3_n_6\,
O(0) => \rxbuffer_addr_reg[11]_i_3_n_7\,
S(3) => \rxbuffer_addr[11]_i_4_n_0\,
S(2) => \rxbuffer_addr[11]_i_5_n_0\,
S(1) => \rxbuffer_addr[11]_i_6_n_0\,
S(0) => \rxbuffer_addr[11]_i_7_n_0\
);
\rxbuffer_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[3]_i_1_n_5\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(10),
R => RX_n_10
);
\rxbuffer_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[3]_i_1_n_6\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(9),
R => RX_n_10
);
\rxbuffer_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[3]_i_1_n_7\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(8),
R => RX_n_10
);
\rxbuffer_addr_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rxbuffer_addr_reg[7]_i_1_n_0\,
CO(3) => \NLW_rxbuffer_addr_reg[3]_i_1_CO_UNCONNECTED\(3),
CO(2) => \rxbuffer_addr_reg[3]_i_1_n_1\,
CO(1) => \rxbuffer_addr_reg[3]_i_1_n_2\,
CO(0) => \rxbuffer_addr_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rxbuffer_addr_reg[3]_i_1_n_4\,
O(2) => \rxbuffer_addr_reg[3]_i_1_n_5\,
O(1) => \rxbuffer_addr_reg[3]_i_1_n_6\,
O(0) => \rxbuffer_addr_reg[3]_i_1_n_7\,
S(3) => \rxbuffer_addr[3]_i_2_n_0\,
S(2) => \rxbuffer_addr[3]_i_3_n_0\,
S(1) => \rxbuffer_addr[3]_i_4_n_0\,
S(0) => \rxbuffer_addr[3]_i_5_n_0\
);
\rxbuffer_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[7]_i_1_n_4\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(7),
R => RX_n_10
);
\rxbuffer_addr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[7]_i_1_n_5\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(6),
R => RX_n_10
);
\rxbuffer_addr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[7]_i_1_n_6\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(5),
R => RX_n_10
);
\rxbuffer_addr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[7]_i_1_n_7\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(4),
R => RX_n_10
);
\rxbuffer_addr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \rxbuffer_addr_reg[11]_i_3_n_0\,
CO(3) => \rxbuffer_addr_reg[7]_i_1_n_0\,
CO(2) => \rxbuffer_addr_reg[7]_i_1_n_1\,
CO(1) => \rxbuffer_addr_reg[7]_i_1_n_2\,
CO(0) => \rxbuffer_addr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \rxbuffer_addr_reg[7]_i_1_n_4\,
O(2) => \rxbuffer_addr_reg[7]_i_1_n_5\,
O(1) => \rxbuffer_addr_reg[7]_i_1_n_6\,
O(0) => \rxbuffer_addr_reg[7]_i_1_n_7\,
S(3) => \rxbuffer_addr[7]_i_2_n_0\,
S(2) => \rxbuffer_addr[7]_i_3_n_0\,
S(1) => \rxbuffer_addr[7]_i_4_n_0\,
S(0) => \rxbuffer_addr[7]_i_5_n_0\
);
\rxbuffer_addr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[11]_i_3_n_4\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(3),
R => RX_n_10
);
\rxbuffer_addr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rx_addr_en,
D => \rxbuffer_addr_reg[11]_i_3_n_5\,
Q => \^gen_wr_b.gen_word_wide.mem_reg\(2),
R => RX_n_10
);
tx_clk_reg_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Phy_tx_clk_axi_d,
Q => tx_clk_reg_d1,
R => \^prmry_in\
);
tx_clk_reg_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_clk_reg_d1,
Q => tx_clk_reg_d2,
R => \^prmry_in\
);
tx_clk_reg_d3_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_clk_reg_d2,
Q => tx_clk_reg_d3,
R => \^prmry_in\
);
\txbuffer_addr[11]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(3),
O => \txbuffer_addr[11]_i_4_n_0\
);
\txbuffer_addr[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(2),
O => \txbuffer_addr[11]_i_5_n_0\
);
\txbuffer_addr[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(1),
O => \txbuffer_addr[11]_i_6_n_0\
);
\txbuffer_addr[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^addra\(0),
O => \txbuffer_addr[11]_i_7_n_0\
);
\txbuffer_addr[3]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(11),
O => \txbuffer_addr[3]_i_2_n_0\
);
\txbuffer_addr[3]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(10),
O => \txbuffer_addr[3]_i_3_n_0\
);
\txbuffer_addr[3]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(9),
O => \txbuffer_addr[3]_i_4_n_0\
);
\txbuffer_addr[3]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(8),
O => \txbuffer_addr[3]_i_5_n_0\
);
\txbuffer_addr[7]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(7),
O => \txbuffer_addr[7]_i_2_n_0\
);
\txbuffer_addr[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(6),
O => \txbuffer_addr[7]_i_3_n_0\
);
\txbuffer_addr[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(5),
O => \txbuffer_addr[7]_i_4_n_0\
);
\txbuffer_addr[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^addra\(4),
O => \txbuffer_addr[7]_i_5_n_0\
);
\txbuffer_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[3]_i_1_n_4\,
Q => \^addra\(11),
R => TX_n_4
);
\txbuffer_addr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[11]_i_3_n_6\,
Q => \^addra\(1),
R => TX_n_4
);
\txbuffer_addr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[11]_i_3_n_7\,
Q => \^addra\(0),
R => TX_n_4
);
\txbuffer_addr_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \txbuffer_addr_reg[11]_i_3_n_0\,
CO(2) => \txbuffer_addr_reg[11]_i_3_n_1\,
CO(1) => \txbuffer_addr_reg[11]_i_3_n_2\,
CO(0) => \txbuffer_addr_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \txbuffer_addr_reg[11]_i_3_n_4\,
O(2) => \txbuffer_addr_reg[11]_i_3_n_5\,
O(1) => \txbuffer_addr_reg[11]_i_3_n_6\,
O(0) => \txbuffer_addr_reg[11]_i_3_n_7\,
S(3) => \txbuffer_addr[11]_i_4_n_0\,
S(2) => \txbuffer_addr[11]_i_5_n_0\,
S(1) => \txbuffer_addr[11]_i_6_n_0\,
S(0) => \txbuffer_addr[11]_i_7_n_0\
);
\txbuffer_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[3]_i_1_n_5\,
Q => \^addra\(10),
R => TX_n_4
);
\txbuffer_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[3]_i_1_n_6\,
Q => \^addra\(9),
R => TX_n_4
);
\txbuffer_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[3]_i_1_n_7\,
Q => \^addra\(8),
R => TX_n_4
);
\txbuffer_addr_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \txbuffer_addr_reg[7]_i_1_n_0\,
CO(3) => \NLW_txbuffer_addr_reg[3]_i_1_CO_UNCONNECTED\(3),
CO(2) => \txbuffer_addr_reg[3]_i_1_n_1\,
CO(1) => \txbuffer_addr_reg[3]_i_1_n_2\,
CO(0) => \txbuffer_addr_reg[3]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \txbuffer_addr_reg[3]_i_1_n_4\,
O(2) => \txbuffer_addr_reg[3]_i_1_n_5\,
O(1) => \txbuffer_addr_reg[3]_i_1_n_6\,
O(0) => \txbuffer_addr_reg[3]_i_1_n_7\,
S(3) => \txbuffer_addr[3]_i_2_n_0\,
S(2) => \txbuffer_addr[3]_i_3_n_0\,
S(1) => \txbuffer_addr[3]_i_4_n_0\,
S(0) => \txbuffer_addr[3]_i_5_n_0\
);
\txbuffer_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[7]_i_1_n_4\,
Q => \^addra\(7),
R => TX_n_4
);
\txbuffer_addr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[7]_i_1_n_5\,
Q => \^addra\(6),
R => TX_n_4
);
\txbuffer_addr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[7]_i_1_n_6\,
Q => \^addra\(5),
R => TX_n_4
);
\txbuffer_addr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[7]_i_1_n_7\,
Q => \^addra\(4),
R => TX_n_4
);
\txbuffer_addr_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \txbuffer_addr_reg[11]_i_3_n_0\,
CO(3) => \txbuffer_addr_reg[7]_i_1_n_0\,
CO(2) => \txbuffer_addr_reg[7]_i_1_n_1\,
CO(1) => \txbuffer_addr_reg[7]_i_1_n_2\,
CO(0) => \txbuffer_addr_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \txbuffer_addr_reg[7]_i_1_n_4\,
O(2) => \txbuffer_addr_reg[7]_i_1_n_5\,
O(1) => \txbuffer_addr_reg[7]_i_1_n_6\,
O(0) => \txbuffer_addr_reg[7]_i_1_n_7\,
S(3) => \txbuffer_addr[7]_i_2_n_0\,
S(2) => \txbuffer_addr[7]_i_3_n_0\,
S(1) => \txbuffer_addr[7]_i_4_n_0\,
S(0) => \txbuffer_addr[7]_i_5_n_0\
);
\txbuffer_addr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[11]_i_3_n_4\,
Q => \^addra\(3),
R => TX_n_4
);
\txbuffer_addr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => tx_addr_en,
D => \txbuffer_addr_reg[11]_i_3_n_5\,
Q => \^addra\(2),
R => TX_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_xemac is
port (
ip2intc_irpt : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
phy_mdc : out STD_LOGIC;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[31]\ : out STD_LOGIC;
p_33_in182_in : out STD_LOGIC;
p_21_in144_in : out STD_LOGIC;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[2]\ : out STD_LOGIC;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[1]\ : out STD_LOGIC;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[0]\ : out STD_LOGIC;
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
reg_access : out STD_LOGIC;
mdio_en_i : out STD_LOGIC;
\status_reg_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
IP2INTC_IRPT_REG_I_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
p_9_in : out STD_LOGIC_VECTOR ( 1 downto 0 );
pong_rx_status : out STD_LOGIC;
p_5_in : out STD_LOGIC_VECTOR ( 0 to 0 );
ping_soft_status : out STD_LOGIC;
pong_soft_status : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
\tx_packet_length_reg[15]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\tx_packet_length_reg[15]_1\ : out STD_LOGIC_VECTOR ( 14 downto 0 );
\reg_data_out_reg[0]_0\ : out STD_LOGIC;
\MDIO_GEN.mdio_data_out_reg[15]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
prmry_vect_in : out STD_LOGIC_VECTOR ( 3 downto 0 );
prmry_in : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
CLK : in STD_LOGIC;
DIA : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIB : in STD_LOGIC_VECTOR ( 1 downto 0 );
DIC : in STD_LOGIC_VECTOR ( 1 downto 0 );
phy_tx_clk : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_0\ : in STD_LOGIC;
phy_mdio_i : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.read_in_prog_reg\ : in STD_LOGIC;
reg_data_out0 : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[14]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[13]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[12]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[11]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[10]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[9]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[8]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[7]_0\ : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[6]_0\ : in STD_LOGIC;
\reg_data_out_reg[31]_0\ : in STD_LOGIC;
\reg_data_out_reg[5]_0\ : in STD_LOGIC;
\reg_data_out_reg[3]_0\ : in STD_LOGIC;
\reg_data_out_reg[2]_0\ : in STD_LOGIC;
\reg_data_out_reg[1]_0\ : in STD_LOGIC;
\reg_data_out_reg[0]_1\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_en_i_reg_0\ : in STD_LOGIC;
tx_intr_en_reg_0 : in STD_LOGIC;
rx_intr_en_reg_0 : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg\ : in STD_LOGIC;
ping_soft_status_reg_0 : in STD_LOGIC;
\TX_PONG_REG_GEN.pong_soft_status_reg_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_1\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_2\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_2\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_3\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.read_in_prog_reg_4\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_3\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\ : in STD_LOGIC;
p_19_out : in STD_LOGIC;
tx_intr_en0 : in STD_LOGIC;
rx_intr_en0 : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_1\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.write_in_prog_reg_0\ : in STD_LOGIC;
p_44_out : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.read_in_prog_reg_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.read_in_prog_reg_6\ : in STD_LOGIC;
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[14]_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[13]_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[12]_0\ : in STD_LOGIC;
\MDIO_GEN.mdio_wr_data_reg_reg[11]_0\ : in STD_LOGIC;
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_xemac : entity is "xemac";
end system_axi_ethernetlite_0_0_xemac;
architecture STRUCTURE of system_axi_ethernetlite_0_0_xemac is
signal \^axi4_lite_if_gen.ip2bus_data_sampled_reg[0]\ : STD_LOGIC;
signal \^axi4_lite_if_gen.ip2bus_data_sampled_reg[1]\ : STD_LOGIC;
signal \^axi4_lite_if_gen.ip2bus_data_sampled_reg[2]\ : STD_LOGIC;
signal \^axi4_lite_if_gen.ip2bus_data_sampled_reg[31]\ : STD_LOGIC;
signal D_5 : STD_LOGIC;
signal EMAC_I_n_34 : STD_LOGIC;
signal EMAC_I_n_35 : STD_LOGIC;
signal EMAC_I_n_36 : STD_LOGIC;
signal EMAC_I_n_37 : STD_LOGIC;
signal EMAC_I_n_38 : STD_LOGIC;
signal EMAC_I_n_39 : STD_LOGIC;
signal EMAC_I_n_40 : STD_LOGIC;
signal EMAC_I_n_41 : STD_LOGIC;
signal EMAC_I_n_42 : STD_LOGIC;
signal EMAC_I_n_43 : STD_LOGIC;
signal EMAC_I_n_44 : STD_LOGIC;
signal EMAC_I_n_45 : STD_LOGIC;
signal EMAC_I_n_46 : STD_LOGIC;
signal EMAC_I_n_47 : STD_LOGIC;
signal \^ip2intc_irpt_reg_i_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \MDIO_GEN.MDIO_IF_I_n_10\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_11\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_12\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_13\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_14\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_15\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_16\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_17\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_18\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_7\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_8\ : STD_LOGIC;
signal \MDIO_GEN.MDIO_IF_I_n_9\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \MDIO_GEN.clk_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \MDIO_GEN.mdio_clk_i_i_1_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_clk_i_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[1]_i_2_n_0\ : STD_LOGIC;
signal \MDIO_GEN.mdio_data_out[7]_i_2_n_0\ : STD_LOGIC;
signal \^mdio_gen.mdio_data_out_reg[15]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \MDIO_GEN.mdio_data_out_reg_n_0_[0]\ : STD_LOGIC;
signal \MDIO_GEN.mdio_req_i_reg_n_0\ : STD_LOGIC;
signal Q_4 : STD_LOGIC;
signal \RX_PONG_GEN.rx_pong_ping_l_i_1_n_0\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \TX/INST_TX_STATE_MACHINE/txDone\ : STD_LOGIC;
signal \TX_PONG_GEN.tx_pong_ping_l_i_1_n_0\ : STD_LOGIC;
signal \TX_PONG_REG_GEN.pong_mac_program_i_1_n_0\ : STD_LOGIC;
signal \TX_PONG_REG_GEN.pong_tx_status_i_1_n_0\ : STD_LOGIC;
signal data7 : STD_LOGIC_VECTOR ( 4 to 4 );
signal loopback_en_reg_n_0 : STD_LOGIC;
signal \^mdio_en_i\ : STD_LOGIC;
signal mdio_wr_data_reg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal p_0_in_6 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal p_14_in125_in : STD_LOGIC;
signal p_15_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_17_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 31 downto 2 );
signal p_20_in : STD_LOGIC;
signal \^p_21_in144_in\ : STD_LOGIC;
signal p_26_in161_in : STD_LOGIC;
signal p_27_in163_in : STD_LOGIC;
signal p_2_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal p_32_in180_in : STD_LOGIC;
signal \^p_33_in182_in\ : STD_LOGIC;
signal p_38_in : STD_LOGIC;
signal p_39_in : STD_LOGIC;
signal p_44_in : STD_LOGIC;
signal p_45_in : STD_LOGIC;
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_50_in236_in : STD_LOGIC;
signal p_51_in : STD_LOGIC;
signal p_56_in : STD_LOGIC;
signal p_57_in : STD_LOGIC;
signal \^p_5_in\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_62_in270_in : STD_LOGIC;
signal p_63_in : STD_LOGIC;
signal p_68_in288_in : STD_LOGIC;
signal p_69_in : STD_LOGIC;
signal p_6_in : STD_LOGIC_VECTOR ( 10 downto 0 );
signal p_74_in307_in : STD_LOGIC;
signal p_75_in309_in : STD_LOGIC;
signal p_80_in328_in : STD_LOGIC;
signal p_81_in330_in : STD_LOGIC;
signal p_86_in349_in : STD_LOGIC;
signal p_87_in351_in : STD_LOGIC;
signal p_8_in107_in : STD_LOGIC;
signal p_92_in368_in : STD_LOGIC;
signal p_93_in : STD_LOGIC;
signal \^p_9_in\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^phy_mdc\ : STD_LOGIC;
signal ping_mac_program_i_1_n_0 : STD_LOGIC;
signal ping_pkt_lenth : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ping_tx_status_i_1_n_0 : STD_LOGIC;
signal pong_pkt_lenth : STD_LOGIC_VECTOR ( 4 to 4 );
signal \^pong_rx_status\ : STD_LOGIC;
signal \^reg_access\ : STD_LOGIC;
signal \reg_data_out[4]_i_1_n_0\ : STD_LOGIC;
signal \reg_data_out[4]_i_2_n_0\ : STD_LOGIC;
signal rx_DPM_adr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal rx_DPM_wr_data : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rx_done : STD_LOGIC;
signal rx_done_d1 : STD_LOGIC;
signal rx_ping_data_out : STD_LOGIC_VECTOR ( 30 downto 0 );
signal rx_pong_ping_l : STD_LOGIC;
signal \^status_reg_reg[0]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal tx_DPM_adr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal tx_DPM_rd_data : STD_LOGIC_VECTOR ( 3 downto 0 );
signal tx_done_d2 : STD_LOGIC;
signal tx_idle : STD_LOGIC;
signal tx_packet_length : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^tx_packet_length_reg[15]_0\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \^tx_packet_length_reg[15]_1\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal tx_ping_data_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal tx_ping_rd_data : STD_LOGIC_VECTOR ( 3 downto 0 );
signal tx_pong_ping_l : STD_LOGIC;
signal wr_rd_n_a_i : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of IP2INTC_IRPT_REG_I : label is "FDR";
attribute box_type : string;
attribute box_type of IP2INTC_IRPT_REG_I : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \MDIO_GEN.clk_cnt[2]_i_1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \MDIO_GEN.clk_cnt[4]_i_1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[1]_i_2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \MDIO_GEN.mdio_data_out[7]_i_2\ : label is "soft_lutpair108";
attribute XILINX_LEGACY_PRIM of RX_DONE_D1_I : label is "FDR";
attribute box_type of RX_DONE_D1_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of TX_DONE_D1_I : label is "FDR";
attribute box_type of TX_DONE_D1_I : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of TX_DONE_D2_I : label is "FDR";
attribute box_type of TX_DONE_D2_I : label is "PRIMITIVE";
attribute SOFT_HLUTNM of \tx_packet_length[0]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \tx_packet_length[10]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \tx_packet_length[11]_i_1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \tx_packet_length[12]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \tx_packet_length[13]_i_1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \tx_packet_length[14]_i_1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \tx_packet_length[15]_i_1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \tx_packet_length[1]_i_1\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \tx_packet_length[2]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \tx_packet_length[3]_i_1\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \tx_packet_length[4]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \tx_packet_length[5]_i_1\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \tx_packet_length[6]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \tx_packet_length[7]_i_1\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \tx_packet_length[8]_i_1\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \tx_packet_length[9]_i_1\ : label is "soft_lutpair103";
begin
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[0]\ <= \^axi4_lite_if_gen.ip2bus_data_sampled_reg[0]\;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[1]\ <= \^axi4_lite_if_gen.ip2bus_data_sampled_reg[1]\;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[2]\ <= \^axi4_lite_if_gen.ip2bus_data_sampled_reg[2]\;
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[31]\ <= \^axi4_lite_if_gen.ip2bus_data_sampled_reg[31]\;
IP2INTC_IRPT_REG_I_0(1 downto 0) <= \^ip2intc_irpt_reg_i_0\(1 downto 0);
\MDIO_GEN.mdio_data_out_reg[15]_0\(4 downto 0) <= \^mdio_gen.mdio_data_out_reg[15]_0\(4 downto 0);
SR(0) <= \^sr\(0);
mdio_en_i <= \^mdio_en_i\;
p_21_in144_in <= \^p_21_in144_in\;
p_33_in182_in <= \^p_33_in182_in\;
p_5_in(0) <= \^p_5_in\(0);
p_9_in(1 downto 0) <= \^p_9_in\(1 downto 0);
phy_mdc <= \^phy_mdc\;
pong_rx_status <= \^pong_rx_status\;
reg_access <= \^reg_access\;
\status_reg_reg[0]_0\(0) <= \^status_reg_reg[0]_0\(0);
\tx_packet_length_reg[15]_0\(13 downto 0) <= \^tx_packet_length_reg[15]_0\(13 downto 0);
\tx_packet_length_reg[15]_1\(14 downto 0) <= \^tx_packet_length_reg[15]_1\(14 downto 0);
EMAC_I: entity work.system_axi_ethernetlite_0_0_axi_ethernetlite_v3_0_9_emac
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_1\,
\AXI4_LITE_IF_GEN.write_in_prog_reg\ => \AXI4_LITE_IF_GEN.write_in_prog_reg_0\,
CLK => CLK,
D(5) => EMAC_I_n_34,
D(4) => EMAC_I_n_35,
D(3) => EMAC_I_n_36,
D(2) => EMAC_I_n_37,
D(1) => EMAC_I_n_38,
D(0) => EMAC_I_n_39,
DIA(1 downto 0) => DIA(1 downto 0),
DIB(1 downto 0) => DIB(1 downto 0),
DIC(1 downto 0) => DIC(1 downto 0),
D_5 => D_5,
E(0) => EMAC_I_n_40,
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ => prmry_in,
Q(3 downto 0) => rx_DPM_wr_data(3 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => EMAC_I_n_43,
\RX_PONG_REG_GEN.pong_rx_status_reg_0\ => \^pong_rx_status\,
\TX_PONG_REG_GEN.pong_mac_program_reg\ => \^status_reg_reg[0]_0\(0),
addra(11 downto 0) => tx_DPM_adr(11 downto 0),
douta(3 downto 0) => tx_ping_rd_data(3 downto 0),
ena => EMAC_I_n_44,
\gen_wr_b.gen_word_wide.mem_reg\(11 downto 0) => rx_DPM_adr(11 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_0\ => EMAC_I_n_45,
\gen_wr_b.gen_word_wide.mem_reg_1\ => EMAC_I_n_46,
\gen_wr_b.gen_word_wide.mem_reg_2\ => EMAC_I_n_47,
\gen_wr_b.gen_word_wide.mem_reg_3\(3 downto 0) => p_4_out(3 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_4\(3 downto 0) => tx_DPM_rd_data(3 downto 0),
loopback_en_reg => EMAC_I_n_41,
loopback_en_reg_0 => loopback_en_reg_n_0,
p_15_in(0) => p_15_in(0),
p_17_in(0) => p_17_in(0),
p_5_in(0) => \^p_5_in\(0),
p_9_in(0) => \^p_9_in\(1),
phy_crs => phy_crs,
phy_tx_clk => phy_tx_clk,
ping_rx_status_reg => EMAC_I_n_42,
ping_rx_status_reg_0 => \^p_9_in\(0),
prmry_in => \^sr\(0),
prmry_vect_in(3 downto 0) => prmry_vect_in(3 downto 0),
rx_done => rx_done,
rx_done_d1 => rx_done_d1,
rx_intr_en0 => rx_intr_en0,
rx_pong_ping_l => rx_pong_ping_l,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(1) => s_axi_wdata(4),
s_axi_wdata(0) => s_axi_wdata(0),
txDone => \TX/INST_TX_STATE_MACHINE/txDone\,
tx_done_d2 => tx_done_d2,
tx_idle => tx_idle,
tx_intr_en0 => tx_intr_en0,
tx_intr_en_reg(1 downto 0) => \^ip2intc_irpt_reg_i_0\(1 downto 0),
\tx_packet_length_reg[15]\(15 downto 0) => tx_packet_length(15 downto 0),
tx_pong_ping_l => tx_pong_ping_l,
wea(0) => wr_rd_n_a_i
);
IP2INTC_IRPT_REG_I: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_5,
Q => ip2intc_irpt,
R => \^sr\(0)
);
\MDIO_GEN.MDIO_IF_I\: entity work.system_axi_ethernetlite_0_0_mdio_if
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\(0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_3\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\,
\AXI4_LITE_IF_GEN.read_in_prog_reg\ => \AXI4_LITE_IF_GEN.read_in_prog_reg_3\,
\AXI4_LITE_IF_GEN.read_in_prog_reg_0\ => \AXI4_LITE_IF_GEN.read_in_prog_reg_4\,
D(10) => \MDIO_GEN.MDIO_IF_I_n_7\,
D(9) => \MDIO_GEN.MDIO_IF_I_n_8\,
D(8) => \MDIO_GEN.MDIO_IF_I_n_9\,
D(7) => \MDIO_GEN.MDIO_IF_I_n_10\,
D(6) => \MDIO_GEN.MDIO_IF_I_n_11\,
D(5) => \MDIO_GEN.MDIO_IF_I_n_12\,
D(4) => \MDIO_GEN.MDIO_IF_I_n_13\,
D(3) => \MDIO_GEN.MDIO_IF_I_n_14\,
D(2) => \MDIO_GEN.MDIO_IF_I_n_15\,
D(1) => \MDIO_GEN.MDIO_IF_I_n_16\,
D(0) => \MDIO_GEN.MDIO_IF_I_n_17\,
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\(4 downto 0) => \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]\(4 downto 0),
\MDIO_GEN.mdio_clk_i_reg\ => \^phy_mdc\,
\MDIO_GEN.mdio_req_i_reg\ => \MDIO_GEN.MDIO_IF_I_n_18\,
\MDIO_GEN.mdio_req_i_reg_0\ => \MDIO_GEN.mdio_req_i_reg_n_0\,
\MDIO_GEN.mdio_wr_data_reg_reg[1]\ => \MDIO_GEN.mdio_data_out[1]_i_2_n_0\,
\MDIO_GEN.mdio_wr_data_reg_reg[7]\ => \MDIO_GEN.mdio_data_out[7]_i_2_n_0\,
Q(15 downto 11) => \^mdio_gen.mdio_data_out_reg[15]_0\(4 downto 0),
Q(10 downto 0) => mdio_wr_data_reg(10 downto 0),
mdio_en_i => \^mdio_en_i\,
p_19_out => p_19_out,
p_6_in(10 downto 0) => p_6_in(10 downto 0),
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
prmry_in => \^sr\(0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(0) => s_axi_wdata(0)
);
\MDIO_GEN.clk_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
O => \MDIO_GEN.clk_cnt[0]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F00FF00FF00FF00E"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I5 => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
O => \MDIO_GEN.clk_cnt[1]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
O => \MDIO_GEN.clk_cnt[2]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCC9CCC9CCC9CCC8"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I5 => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
O => \MDIO_GEN.clk_cnt[3]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
O => \MDIO_GEN.clk_cnt[4]_i_1_n_0\
);
\MDIO_GEN.clk_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000000"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I5 => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
O => \MDIO_GEN.clk_cnt[5]_i_1_n_0\
);
\MDIO_GEN.clk_cnt_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[0]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
S => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[1]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
R => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[2]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[2]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
S => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[3]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
R => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[4]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[4]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
S => \^sr\(0)
);
\MDIO_GEN.clk_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.clk_cnt[5]_i_1_n_0\,
Q => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
R => \^sr\(0)
);
\MDIO_GEN.mdio_clk_i_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \MDIO_GEN.mdio_clk_i_i_2_n_0\,
I1 => \^phy_mdc\,
O => \MDIO_GEN.mdio_clk_i_i_1_n_0\
);
\MDIO_GEN.mdio_clk_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \MDIO_GEN.clk_cnt_reg_n_0_[5]\,
I1 => \MDIO_GEN.clk_cnt_reg_n_0_[4]\,
I2 => \MDIO_GEN.clk_cnt_reg_n_0_[1]\,
I3 => \MDIO_GEN.clk_cnt_reg_n_0_[0]\,
I4 => \MDIO_GEN.clk_cnt_reg_n_0_[3]\,
I5 => \MDIO_GEN.clk_cnt_reg_n_0_[2]\,
O => \MDIO_GEN.mdio_clk_i_i_2_n_0\
);
\MDIO_GEN.mdio_clk_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.mdio_clk_i_i_1_n_0\,
Q => \^phy_mdc\,
R => \^sr\(0)
);
\MDIO_GEN.mdio_data_out[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_wr_data_reg(1),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\,
O => \MDIO_GEN.mdio_data_out[1]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => mdio_wr_data_reg(7),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\,
O => \MDIO_GEN.mdio_data_out[7]_i_2_n_0\
);
\MDIO_GEN.mdio_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_17\,
Q => \MDIO_GEN.mdio_data_out_reg_n_0_[0]\,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_7\,
Q => p_62_in270_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.mdio_wr_data_reg_reg[11]_0\,
Q => p_68_in288_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.mdio_wr_data_reg_reg[12]_0\,
Q => p_74_in307_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.mdio_wr_data_reg_reg[13]_0\,
Q => p_80_in328_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.mdio_wr_data_reg_reg[14]_0\,
Q => p_86_in349_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\,
Q => p_92_in368_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg_6\
);
\MDIO_GEN.mdio_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_16\,
Q => p_8_in107_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_15\,
Q => p_14_in125_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_14\,
Q => p_20_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_13\,
Q => p_26_in161_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_12\,
Q => p_32_in180_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_11\,
Q => p_38_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_10\,
Q => p_44_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_9\,
Q => p_50_in236_in,
R => '0'
);
\MDIO_GEN.mdio_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0),
D => \MDIO_GEN.MDIO_IF_I_n_8\,
Q => p_56_in,
R => '0'
);
\MDIO_GEN.mdio_en_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.mdio_en_i_reg_0\,
Q => \^mdio_en_i\,
R => \^sr\(0)
);
\MDIO_GEN.mdio_op_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(10),
Q => p_6_in(10),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(5),
Q => p_6_in(5),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(6),
Q => p_6_in(6),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(7),
Q => p_6_in(7),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(8),
Q => p_6_in(8),
R => \^sr\(0)
);
\MDIO_GEN.mdio_phy_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(9),
Q => p_6_in(9),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(0),
Q => p_6_in(0),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(1),
Q => p_6_in(1),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(2),
Q => p_6_in(2),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(3),
Q => p_6_in(3),
R => \^sr\(0)
);
\MDIO_GEN.mdio_reg_addr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => s_axi_wdata(4),
Q => p_6_in(4),
R => \^sr\(0)
);
\MDIO_GEN.mdio_req_i_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MDIO_GEN.MDIO_IF_I_n_18\,
Q => \MDIO_GEN.mdio_req_i_reg_n_0\,
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(0),
Q => mdio_wr_data_reg(0),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(10),
Q => mdio_wr_data_reg(10),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(11),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(0),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(12),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(1),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(13),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(2),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(14),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(3),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(15),
Q => \^mdio_gen.mdio_data_out_reg[15]_0\(4),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(1),
Q => mdio_wr_data_reg(1),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(2),
Q => mdio_wr_data_reg(2),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(3),
Q => mdio_wr_data_reg(3),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(4),
Q => mdio_wr_data_reg(4),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(5),
Q => mdio_wr_data_reg(5),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(6),
Q => mdio_wr_data_reg(6),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(7),
Q => mdio_wr_data_reg(7),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(8),
Q => mdio_wr_data_reg(8),
R => \^sr\(0)
);
\MDIO_GEN.mdio_wr_data_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0),
D => s_axi_wdata(9),
Q => mdio_wr_data_reg(9),
R => \^sr\(0)
);
RX_DONE_D1_I: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rx_done,
Q => rx_done_d1,
R => \^sr\(0)
);
RX_PING: entity work.system_axi_ethernetlite_0_0_emac_dpram
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
D(4) => D(31),
D(3) => D(13),
D(2) => D(11),
D(1) => D(8),
D(0) => D(2),
\MDIO_GEN.mdio_data_out_reg[8]\(1) => p_50_in236_in,
\MDIO_GEN.mdio_data_out_reg[8]\(0) => p_14_in125_in,
Q(3 downto 0) => rx_DPM_wr_data(3 downto 0),
doutb(26 downto 10) => rx_ping_data_out(30 downto 14),
doutb(9) => rx_ping_data_out(12),
doutb(8 downto 7) => rx_ping_data_out(10 downto 9),
doutb(6 downto 2) => rx_ping_data_out(7 downto 3),
doutb(1 downto 0) => rx_ping_data_out(1 downto 0),
ena => EMAC_I_n_44,
\gen_wr_b.gen_word_wide.mem_reg\(4) => p_1_out(31),
\gen_wr_b.gen_word_wide.mem_reg\(3) => p_1_out(13),
\gen_wr_b.gen_word_wide.mem_reg\(2) => p_1_out(11),
\gen_wr_b.gen_word_wide.mem_reg\(1) => p_1_out(8),
\gen_wr_b.gen_word_wide.mem_reg\(0) => p_1_out(2),
\gen_wr_b.gen_word_wide.mem_reg_0\(4) => tx_ping_data_out(31),
\gen_wr_b.gen_word_wide.mem_reg_0\(3) => tx_ping_data_out(13),
\gen_wr_b.gen_word_wide.mem_reg_0\(2) => tx_ping_data_out(11),
\gen_wr_b.gen_word_wide.mem_reg_0\(1) => tx_ping_data_out(8),
\gen_wr_b.gen_word_wide.mem_reg_0\(0) => tx_ping_data_out(2),
\gen_wr_b.gen_word_wide.mem_reg_1\(4) => p_2_out(31),
\gen_wr_b.gen_word_wide.mem_reg_1\(3) => p_2_out(13),
\gen_wr_b.gen_word_wide.mem_reg_1\(2) => p_2_out(11),
\gen_wr_b.gen_word_wide.mem_reg_1\(1) => p_2_out(8),
\gen_wr_b.gen_word_wide.mem_reg_1\(0) => p_2_out(2),
p_51_in => p_51_in,
p_68_in288_in => p_68_in288_in,
p_69_in => p_69_in,
p_80_in328_in => p_80_in328_in,
p_81_in330_in => p_81_in330_in,
reg_access_reg => \^reg_access\,
\reg_data_out_reg[2]\ => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[2]\,
\reg_data_out_reg[31]\ => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[31]\,
\rxbuffer_addr_reg[0]\(11 downto 0) => rx_DPM_adr(11 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
wea(0) => wr_rd_n_a_i,
web(0) => web(0)
);
\RX_PONG_GEN.RX_PONG_I\: entity work.system_axi_ethernetlite_0_0_emac_dpram_1
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(8 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_0\,
Q(3 downto 0) => rx_DPM_wr_data(3 downto 0),
doutb(31 downto 0) => p_2_out(31 downto 0),
\rxbuffer_addr_reg[0]\(11 downto 0) => rx_DPM_adr(11 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
state0a => EMAC_I_n_45,
wea(0) => wr_rd_n_a_i,
web(0) => web(0)
);
\RX_PONG_GEN.rx_pong_ping_l_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rx_done_d1,
I1 => rx_pong_ping_l,
O => \RX_PONG_GEN.rx_pong_ping_l_i_1_n_0\
);
\RX_PONG_GEN.rx_pong_ping_l_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \RX_PONG_GEN.rx_pong_ping_l_i_1_n_0\,
Q => rx_pong_ping_l,
R => \^sr\(0)
);
\RX_PONG_REG_GEN.pong_rx_status_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => EMAC_I_n_43,
Q => \^pong_rx_status\,
R => \^sr\(0)
);
TX_DONE_D1_I: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TX/INST_TX_STATE_MACHINE/txDone\,
Q => Q_4,
R => \^sr\(0)
);
TX_DONE_D2_I: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => Q_4,
Q => tx_done_d2,
R => \^sr\(0)
);
TX_PING: entity work.system_axi_ethernetlite_0_0_emac_dpram_2
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[10]\(8 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(8 downto 0),
\TX_PONG_GEN.tx_pong_ping_l_reg\ => EMAC_I_n_46,
addra(11 downto 0) => tx_DPM_adr(11 downto 0),
douta(3 downto 0) => tx_ping_rd_data(3 downto 0),
doutb(31 downto 0) => tx_ping_data_out(31 downto 0),
enb => enb,
\gen_wr_b.gen_word_wide.mem_reg\(0) => p_4_out(1),
\rdDestAddrNib_D_t_q_reg[1]\(0) => tx_DPM_rd_data(1),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
tx_idle => tx_idle,
tx_pong_ping_l => tx_pong_ping_l,
web(0) => web(0)
);
\TX_PONG_GEN.TX_PONG_I\: entity work.system_axi_ethernetlite_0_0_emac_dpram_3
port map (
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\(10 downto 0) => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\,
D(26 downto 10) => D(30 downto 14),
D(9) => D(12),
D(8 downto 7) => D(10 downto 9),
D(6 downto 2) => D(7 downto 3),
D(1 downto 0) => D(1 downto 0),
Q(8) => p_62_in270_in,
Q(7) => p_56_in,
Q(6) => p_44_in,
Q(5) => p_38_in,
Q(4) => p_32_in180_in,
Q(3) => p_26_in161_in,
Q(2) => p_20_in,
Q(1) => p_8_in107_in,
Q(0) => \MDIO_GEN.mdio_data_out_reg_n_0_[0]\,
\TX_PONG_GEN.tx_pong_ping_l_reg\ => EMAC_I_n_47,
addra(11 downto 0) => tx_DPM_adr(11 downto 0),
douta(3 downto 0) => p_4_out(3 downto 0),
doutb(4) => p_1_out(31),
doutb(3) => p_1_out(13),
doutb(2) => p_1_out(11),
doutb(1) => p_1_out(8),
doutb(0) => p_1_out(2),
\gen_wr_b.gen_word_wide.mem_reg\(2 downto 1) => tx_ping_rd_data(3 downto 2),
\gen_wr_b.gen_word_wide.mem_reg\(0) => tx_ping_rd_data(0),
\gen_wr_b.gen_word_wide.mem_reg_0\(26 downto 10) => rx_ping_data_out(30 downto 14),
\gen_wr_b.gen_word_wide.mem_reg_0\(9) => rx_ping_data_out(12),
\gen_wr_b.gen_word_wide.mem_reg_0\(8 downto 7) => rx_ping_data_out(10 downto 9),
\gen_wr_b.gen_word_wide.mem_reg_0\(6 downto 2) => rx_ping_data_out(7 downto 3),
\gen_wr_b.gen_word_wide.mem_reg_0\(1 downto 0) => rx_ping_data_out(1 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_1\(26 downto 10) => p_2_out(30 downto 14),
\gen_wr_b.gen_word_wide.mem_reg_1\(9) => p_2_out(12),
\gen_wr_b.gen_word_wide.mem_reg_1\(8 downto 7) => p_2_out(10 downto 9),
\gen_wr_b.gen_word_wide.mem_reg_1\(6 downto 2) => p_2_out(7 downto 3),
\gen_wr_b.gen_word_wide.mem_reg_1\(1 downto 0) => p_2_out(1 downto 0),
\gen_wr_b.gen_word_wide.mem_reg_2\(26 downto 10) => tx_ping_data_out(30 downto 14),
\gen_wr_b.gen_word_wide.mem_reg_2\(9) => tx_ping_data_out(12),
\gen_wr_b.gen_word_wide.mem_reg_2\(8 downto 7) => tx_ping_data_out(10 downto 9),
\gen_wr_b.gen_word_wide.mem_reg_2\(6 downto 2) => tx_ping_data_out(7 downto 3),
\gen_wr_b.gen_word_wide.mem_reg_2\(1 downto 0) => tx_ping_data_out(1 downto 0),
p_21_in144_in => \^p_21_in144_in\,
p_27_in163_in => p_27_in163_in,
p_33_in182_in => \^p_33_in182_in\,
p_39_in => p_39_in,
p_45_in => p_45_in,
p_57_in => p_57_in,
p_63_in => p_63_in,
p_74_in307_in => p_74_in307_in,
p_75_in309_in => p_75_in309_in,
p_86_in349_in => p_86_in349_in,
p_87_in351_in => p_87_in351_in,
p_92_in368_in => p_92_in368_in,
p_93_in => p_93_in,
\rdDestAddrNib_D_t_q_reg[1]\(2 downto 1) => tx_DPM_rd_data(3 downto 2),
\rdDestAddrNib_D_t_q_reg[1]\(0) => tx_DPM_rd_data(0),
reg_access_reg => \^reg_access\,
\reg_data_out_reg[0]\ => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[0]\,
\reg_data_out_reg[1]\ => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[1]\,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
tx_idle => tx_idle,
tx_pong_ping_l => tx_pong_ping_l,
web(0) => web(0)
);
\TX_PONG_GEN.tx_pong_ping_l_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"45AE"
)
port map (
I0 => Q_4,
I1 => p_15_in(0),
I2 => p_17_in(0),
I3 => tx_pong_ping_l,
O => \TX_PONG_GEN.tx_pong_ping_l_i_1_n_0\
);
\TX_PONG_GEN.tx_pong_ping_l_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TX_PONG_GEN.tx_pong_ping_l_i_1_n_0\,
Q => tx_pong_ping_l,
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_mac_program_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8888"
)
port map (
I0 => s_axi_wdata(1),
I1 => p_44_out,
I2 => Q_4,
I3 => tx_pong_ping_l,
I4 => \^status_reg_reg[0]_0\(0),
O => \TX_PONG_REG_GEN.pong_mac_program_i_1_n_0\
);
\TX_PONG_REG_GEN.pong_mac_program_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \TX_PONG_REG_GEN.pong_mac_program_i_1_n_0\,
Q => \^status_reg_reg[0]_0\(0),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(0),
Q => \^tx_packet_length_reg[15]_1\(0),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(10),
Q => \^tx_packet_length_reg[15]_1\(9),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(11),
Q => \^tx_packet_length_reg[15]_1\(10),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(12),
Q => \^tx_packet_length_reg[15]_1\(11),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(13),
Q => \^tx_packet_length_reg[15]_1\(12),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(14),
Q => \^tx_packet_length_reg[15]_1\(13),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(15),
Q => \^tx_packet_length_reg[15]_1\(14),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(1),
Q => \^tx_packet_length_reg[15]_1\(1),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(2),
Q => \^tx_packet_length_reg[15]_1\(2),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(3),
Q => \^tx_packet_length_reg[15]_1\(3),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(4),
Q => pong_pkt_lenth(4),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(5),
Q => \^tx_packet_length_reg[15]_1\(4),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(6),
Q => \^tx_packet_length_reg[15]_1\(5),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(7),
Q => \^tx_packet_length_reg[15]_1\(6),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(8),
Q => \^tx_packet_length_reg[15]_1\(7),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0),
D => s_axi_wdata(9),
Q => \^tx_packet_length_reg[15]_1\(8),
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_soft_status_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \TX_PONG_REG_GEN.pong_soft_status_reg_0\,
Q => pong_soft_status,
R => \^sr\(0)
);
\TX_PONG_REG_GEN.pong_tx_status_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8888"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_44_out,
I2 => Q_4,
I3 => tx_pong_ping_l,
I4 => p_15_in(0),
O => \TX_PONG_REG_GEN.pong_tx_status_i_1_n_0\
);
\TX_PONG_REG_GEN.pong_tx_status_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \TX_PONG_REG_GEN.pong_tx_status_i_1_n_0\,
Q => p_15_in(0),
R => \^sr\(0)
);
gie_enable_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.write_in_prog_reg\,
Q => \^p_5_in\(0),
R => \^sr\(0)
);
loopback_en_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => EMAC_I_n_41,
Q => loopback_en_reg_n_0,
R => \^sr\(0)
);
ping_mac_program_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BB8888"
)
port map (
I0 => s_axi_wdata(1),
I1 => tx_intr_en0,
I2 => tx_pong_ping_l,
I3 => Q_4,
I4 => \^ip2intc_irpt_reg_i_0\(0),
O => ping_mac_program_i_1_n_0
);
ping_mac_program_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ping_mac_program_i_1_n_0,
Q => \^ip2intc_irpt_reg_i_0\(0),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(0),
Q => ping_pkt_lenth(0),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(10),
Q => \^tx_packet_length_reg[15]_0\(8),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(11),
Q => \^tx_packet_length_reg[15]_0\(9),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(12),
Q => \^tx_packet_length_reg[15]_0\(10),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(13),
Q => \^tx_packet_length_reg[15]_0\(11),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(14),
Q => \^tx_packet_length_reg[15]_0\(12),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(15),
Q => \^tx_packet_length_reg[15]_0\(13),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(1),
Q => \^tx_packet_length_reg[15]_0\(0),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(2),
Q => \^tx_packet_length_reg[15]_0\(1),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(3),
Q => \^tx_packet_length_reg[15]_0\(2),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(4),
Q => ping_pkt_lenth(4),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(5),
Q => \^tx_packet_length_reg[15]_0\(3),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(6),
Q => \^tx_packet_length_reg[15]_0\(4),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(7),
Q => \^tx_packet_length_reg[15]_0\(5),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(8),
Q => \^tx_packet_length_reg[15]_0\(6),
R => \^sr\(0)
);
\ping_pkt_lenth_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0),
D => s_axi_wdata(9),
Q => \^tx_packet_length_reg[15]_0\(7),
R => \^sr\(0)
);
ping_rx_status_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => EMAC_I_n_42,
Q => \^p_9_in\(0),
R => \^sr\(0)
);
ping_soft_status_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ping_soft_status_reg_0,
Q => ping_soft_status,
R => \^sr\(0)
);
ping_tx_status_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BB8888"
)
port map (
I0 => s_axi_wdata(0),
I1 => tx_intr_en0,
I2 => tx_pong_ping_l,
I3 => Q_4,
I4 => p_17_in(0),
O => ping_tx_status_i_1_n_0
);
ping_tx_status_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ping_tx_status_i_1_n_0,
Q => p_17_in(0),
R => \^sr\(0)
);
reg_access_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \AXI4_LITE_IF_GEN.read_in_prog_reg_0\,
Q => \^reg_access\,
R => \^sr\(0)
);
\reg_data_out[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFF222F222"
)
port map (
I0 => p_17_in(0),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_2\,
I2 => p_15_in(0),
I3 => \AXI4_LITE_IF_GEN.read_in_prog_reg_2\,
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
I5 => ping_pkt_lenth(0),
O => \reg_data_out_reg[0]_0\
);
\reg_data_out[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2E2EEE2"
)
port map (
I0 => p_27_in163_in,
I1 => reg_data_out0,
I2 => \reg_data_out[4]_i_2_n_0\,
I3 => data7(4),
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\,
I5 => \AXI4_LITE_IF_GEN.read_in_prog_reg_1\,
O => \reg_data_out[4]_i_1_n_0\
);
\reg_data_out[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFF22F222F2"
)
port map (
I0 => ping_pkt_lenth(4),
I1 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\,
I2 => pong_pkt_lenth(4),
I3 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\,
I4 => \AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_2\,
I5 => loopback_en_reg_n_0,
O => \reg_data_out[4]_i_2_n_0\
);
\reg_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[0]_1\,
Q => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[0]\,
R => '0'
);
\reg_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[10]_0\,
Q => p_63_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[11]_0\,
Q => p_69_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[12]_0\,
Q => p_75_in309_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[13]_0\,
Q => p_81_in330_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[14]_0\,
Q => p_87_in351_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\,
Q => p_93_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[1]_0\,
Q => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[1]\,
R => '0'
);
\reg_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[2]_0\,
Q => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[2]\,
R => '0'
);
\reg_data_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[31]_0\,
Q => \^axi4_lite_if_gen.ip2bus_data_sampled_reg[31]\,
R => '0'
);
\reg_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[3]_0\,
Q => \^p_21_in144_in\,
R => '0'
);
\reg_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out[4]_i_1_n_0\,
Q => p_27_in163_in,
R => '0'
);
\reg_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \reg_data_out_reg[5]_0\,
Q => \^p_33_in182_in\,
R => '0'
);
\reg_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[6]_0\,
Q => p_39_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[7]_0\,
Q => p_45_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[8]_0\,
Q => p_51_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
\reg_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => reg_data_out0,
D => \TX_PONG_REG_GEN.pong_pkt_lenth_reg[9]_0\,
Q => p_57_in,
R => \AXI4_LITE_IF_GEN.read_in_prog_reg\
);
rx_intr_en_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rx_intr_en_reg_0,
Q => \^p_9_in\(1),
R => \^sr\(0)
);
\status_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_39,
Q => Q(0),
R => '0'
);
\status_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_38,
Q => Q(1),
R => '0'
);
\status_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_37,
Q => Q(2),
R => '0'
);
\status_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_36,
Q => Q(3),
R => '0'
);
\status_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_35,
Q => data7(4),
R => '0'
);
\status_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => EMAC_I_n_40,
D => EMAC_I_n_34,
Q => Q(4),
R => '0'
);
tx_intr_en_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => tx_intr_en_reg_0,
Q => \^ip2intc_irpt_reg_i_0\(1),
R => \^sr\(0)
);
\tx_packet_length[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(0),
I1 => tx_pong_ping_l,
I2 => ping_pkt_lenth(0),
O => p_0_in_6(0)
);
\tx_packet_length[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(9),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(8),
O => p_0_in_6(10)
);
\tx_packet_length[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(10),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(9),
O => p_0_in_6(11)
);
\tx_packet_length[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(11),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(10),
O => p_0_in_6(12)
);
\tx_packet_length[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(12),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(11),
O => p_0_in_6(13)
);
\tx_packet_length[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(13),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(12),
O => p_0_in_6(14)
);
\tx_packet_length[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(14),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(13),
O => p_0_in_6(15)
);
\tx_packet_length[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(1),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(0),
O => p_0_in_6(1)
);
\tx_packet_length[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(2),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(1),
O => p_0_in_6(2)
);
\tx_packet_length[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(3),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(2),
O => p_0_in_6(3)
);
\tx_packet_length[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => pong_pkt_lenth(4),
I1 => tx_pong_ping_l,
I2 => ping_pkt_lenth(4),
O => p_0_in_6(4)
);
\tx_packet_length[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(4),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(3),
O => p_0_in_6(5)
);
\tx_packet_length[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(5),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(4),
O => p_0_in_6(6)
);
\tx_packet_length[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(6),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(5),
O => p_0_in_6(7)
);
\tx_packet_length[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(7),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(6),
O => p_0_in_6(8)
);
\tx_packet_length[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^tx_packet_length_reg[15]_1\(8),
I1 => tx_pong_ping_l,
I2 => \^tx_packet_length_reg[15]_0\(7),
O => p_0_in_6(9)
);
\tx_packet_length_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(0),
Q => tx_packet_length(0),
R => \^sr\(0)
);
\tx_packet_length_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(10),
Q => tx_packet_length(10),
R => \^sr\(0)
);
\tx_packet_length_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(11),
Q => tx_packet_length(11),
R => \^sr\(0)
);
\tx_packet_length_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(12),
Q => tx_packet_length(12),
R => \^sr\(0)
);
\tx_packet_length_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(13),
Q => tx_packet_length(13),
R => \^sr\(0)
);
\tx_packet_length_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(14),
Q => tx_packet_length(14),
R => \^sr\(0)
);
\tx_packet_length_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(15),
Q => tx_packet_length(15),
R => \^sr\(0)
);
\tx_packet_length_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(1),
Q => tx_packet_length(1),
R => \^sr\(0)
);
\tx_packet_length_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(2),
Q => tx_packet_length(2),
R => \^sr\(0)
);
\tx_packet_length_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(3),
Q => tx_packet_length(3),
R => \^sr\(0)
);
\tx_packet_length_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(4),
Q => tx_packet_length(4),
R => \^sr\(0)
);
\tx_packet_length_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(5),
Q => tx_packet_length(5),
R => \^sr\(0)
);
\tx_packet_length_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(6),
Q => tx_packet_length(6),
R => \^sr\(0)
);
\tx_packet_length_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(7),
Q => tx_packet_length(7),
R => \^sr\(0)
);
\tx_packet_length_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(8),
Q => tx_packet_length(8),
R => \^sr\(0)
);
\tx_packet_length_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_in_6(9),
Q => tx_packet_length(9),
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0_axi_ethernetlite is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
phy_rx_clk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
phy_dv : in STD_LOGIC;
phy_rx_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_col : in STD_LOGIC;
phy_rx_er : in STD_LOGIC;
phy_rst_n : out STD_LOGIC;
phy_tx_en : out STD_LOGIC;
phy_tx_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_mdio_i : in STD_LOGIC;
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
phy_mdc : out STD_LOGIC
);
attribute C_DUPLEX : integer;
attribute C_DUPLEX of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "artix7";
attribute C_INCLUDE_GLOBAL_BUFFERS : integer;
attribute C_INCLUDE_GLOBAL_BUFFERS of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_INCLUDE_INTERNAL_LOOPBACK : integer;
attribute C_INCLUDE_INTERNAL_LOOPBACK of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 0;
attribute C_INCLUDE_MDIO : integer;
attribute C_INCLUDE_MDIO of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "axi_ethernetlite_inst";
attribute C_RX_PING_PONG : integer;
attribute C_RX_PING_PONG of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_S_AXI_ACLK_PERIOD_PS : integer;
attribute C_S_AXI_ACLK_PERIOD_PS of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 10000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 13;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "AXI4LITE";
attribute C_TX_PING_PONG : integer;
attribute C_TX_PING_PONG of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "axi_ethernetlite";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_ethernetlite_0_0_axi_ethernetlite : entity is "yes";
end system_axi_ethernetlite_0_0_axi_ethernetlite;
architecture STRUCTURE of system_axi_ethernetlite_0_0_axi_ethernetlite is
signal \<const0>\ : STD_LOGIC;
signal C : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_10 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_11 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_12 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_13 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_14 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_15 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_16 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_18 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_3 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_30 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_31 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_32 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_33 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_34 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_35 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_36 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_37 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_38 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_39 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_40 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_48 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_49 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_5 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_50 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_51 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_53 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_54 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_55 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_56 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_57 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_58 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_59 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_6 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_60 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_61 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_62 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_63 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_64 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_65 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_66 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_67 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_68 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_69 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_7 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_70 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_71 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_72 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_8 : STD_LOGIC;
signal I_AXI_NATIVE_IPIF_n_9 : STD_LOGIC;
signal \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal Q0_out : STD_LOGIC;
signal Q2_out : STD_LOGIC;
signal Q4_out : STD_LOGIC;
signal XEMAC_I_n_3 : STD_LOGIC;
signal XEMAC_I_n_33 : STD_LOGIC;
signal XEMAC_I_n_34 : STD_LOGIC;
signal XEMAC_I_n_35 : STD_LOGIC;
signal XEMAC_I_n_36 : STD_LOGIC;
signal XEMAC_I_n_37 : STD_LOGIC;
signal XEMAC_I_n_38 : STD_LOGIC;
signal XEMAC_I_n_39 : STD_LOGIC;
signal XEMAC_I_n_40 : STD_LOGIC;
signal XEMAC_I_n_41 : STD_LOGIC;
signal XEMAC_I_n_42 : STD_LOGIC;
signal XEMAC_I_n_43 : STD_LOGIC;
signal XEMAC_I_n_44 : STD_LOGIC;
signal XEMAC_I_n_45 : STD_LOGIC;
signal XEMAC_I_n_46 : STD_LOGIC;
signal XEMAC_I_n_47 : STD_LOGIC;
signal XEMAC_I_n_6 : STD_LOGIC;
signal XEMAC_I_n_7 : STD_LOGIC;
signal XEMAC_I_n_8 : STD_LOGIC;
signal XEMAC_I_n_93 : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 12 downto 2 );
signal bus_rst : STD_LOGIC;
signal bus_rst_rx_sync_core : STD_LOGIC;
signal bus_rst_tx_sync_core : STD_LOGIC;
signal data7 : STD_LOGIC_VECTOR ( 5 downto 0 );
signal ip2bus_data : STD_LOGIC_VECTOR ( 31 downto 0 );
signal mdio_en_i : STD_LOGIC;
signal mdio_rd_data_reg : STD_LOGIC_VECTOR ( 15 downto 11 );
signal mdio_wr_data_reg : STD_LOGIC_VECTOR ( 15 downto 11 );
signal o : STD_LOGIC;
signal p_15_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal p_15_out : STD_LOGIC;
signal p_17_in : STD_LOGIC_VECTOR ( 3 downto 1 );
signal p_17_out : STD_LOGIC;
signal p_19_out : STD_LOGIC;
signal p_21_in144_in : STD_LOGIC;
signal p_33_in182_in : STD_LOGIC;
signal p_38_out : STD_LOGIC;
signal p_44_out : STD_LOGIC;
signal p_5_in : STD_LOGIC_VECTOR ( 31 to 31 );
signal p_9_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal phy_dv_reg : STD_LOGIC;
signal phy_rx_er_reg : STD_LOGIC;
signal phy_tx_clk_core : STD_LOGIC;
signal phy_tx_data_i : STD_LOGIC_VECTOR ( 3 downto 0 );
signal phy_tx_data_i_cdc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal phy_tx_en_i : STD_LOGIC;
signal phy_tx_en_i_cdc : STD_LOGIC;
signal ping_pkt_lenth : STD_LOGIC_VECTOR ( 15 downto 1 );
signal ping_pkt_lenth0 : STD_LOGIC;
signal ping_soft_status : STD_LOGIC;
signal pong_pkt_lenth : STD_LOGIC_VECTOR ( 15 downto 0 );
signal pong_rx_status : STD_LOGIC;
signal pong_soft_status : STD_LOGIC;
signal reg_access : STD_LOGIC;
signal reg_data_out0 : STD_LOGIC;
signal rx_intr_en0 : STD_LOGIC;
signal \^s_axi_aresetn\ : STD_LOGIC;
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
attribute RTL_MAX_FANOUT : string;
attribute RTL_MAX_FANOUT of s_axi_aresetn : signal is "found";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal tx_intr_en0 : STD_LOGIC;
attribute box_type : string;
attribute box_type of \IOFFS_GEN2.DVD_FF\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN2.RER_FF\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN2.TEN_FF\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[0].RX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[0].TX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[1].RX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[1].TX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[2].RX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[2].TX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[3].RX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \IOFFS_GEN[3].TX_FF_I\ : label is "PRIMITIVE";
attribute box_type of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_RX\ : label is "PRIMITIVE";
attribute box_type of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_TX\ : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\ : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\ : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\ : label is "AUTO";
attribute box_type of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\ : label is "PRIMITIVE";
attribute CAPACITANCE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\ : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\ : label is "0";
attribute IFD_DELAY_VALUE of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\ : label is "AUTO";
attribute box_type of \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\ : label is "PRIMITIVE";
begin
\^s_axi_aresetn\ <= s_axi_aresetn;
phy_rst_n <= \^s_axi_aresetn\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \^s_axi_rlast\;
s_axi_wready <= \^s_axi_wready\;
BUS_RST_RX_SYNC_CORE_I: entity work.system_axi_ethernetlite_0_0_cdc_sync
port map (
CLK => C,
SR(0) => bus_rst,
scndry_out => bus_rst_rx_sync_core
);
BUS_RST_TX_SYNC_CORE_I: entity work.system_axi_ethernetlite_0_0_cdc_sync_0
port map (
CLK => phy_tx_clk_core,
SR(0) => bus_rst,
scndry_out => bus_rst_tx_sync_core
);
CDC_PHY_TX_DATA_OUT: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized1\
port map (
CLK => phy_tx_clk_core,
prmry_vect_in(3 downto 0) => phy_tx_data_i(3 downto 0),
scndry_vect_out(3 downto 0) => phy_tx_data_i_cdc(3 downto 0)
);
CDC_PHY_TX_EN_O: entity work.\system_axi_ethernetlite_0_0_cdc_sync__parameterized0\
port map (
CLK => phy_tx_clk_core,
prmry_in => phy_tx_en_i,
scndry_out => phy_tx_en_i_cdc
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\IOFFS_GEN2.DVD_FF\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_dv,
Q => phy_dv_reg,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN2.RER_FF\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_er,
Q => phy_rx_er_reg,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN2.TEN_FF\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_en_i_cdc,
Q => phy_tx_en,
R => bus_rst_tx_sync_core
);
\IOFFS_GEN[0].RX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_data(0),
Q => Q0_out,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN[0].TX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_data_i_cdc(0),
Q => phy_tx_data(0),
R => bus_rst_tx_sync_core
);
\IOFFS_GEN[1].RX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_data(1),
Q => Q2_out,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN[1].TX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_data_i_cdc(1),
Q => phy_tx_data(1),
R => bus_rst_tx_sync_core
);
\IOFFS_GEN[2].RX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_data(2),
Q => Q4_out,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN[2].TX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_data_i_cdc(2),
Q => phy_tx_data(2),
R => bus_rst_tx_sync_core
);
\IOFFS_GEN[3].RX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => C,
CE => '1',
D => phy_rx_data(3),
Q => Q,
R => bus_rst_rx_sync_core
);
\IOFFS_GEN[3].TX_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => phy_tx_clk_core,
CE => '1',
D => phy_tx_data_i_cdc(3),
Q => phy_tx_data(3),
R => bus_rst_tx_sync_core
);
I_AXI_NATIVE_IPIF: entity work.system_axi_ethernetlite_0_0_axi_interface
port map (
D(31) => ip2bus_data(31),
D(30) => XEMAC_I_n_33,
D(29) => XEMAC_I_n_34,
D(28) => XEMAC_I_n_35,
D(27) => XEMAC_I_n_36,
D(26) => XEMAC_I_n_37,
D(25) => XEMAC_I_n_38,
D(24) => XEMAC_I_n_39,
D(23) => XEMAC_I_n_40,
D(22) => XEMAC_I_n_41,
D(21) => XEMAC_I_n_42,
D(20) => XEMAC_I_n_43,
D(19) => XEMAC_I_n_44,
D(18) => XEMAC_I_n_45,
D(17) => XEMAC_I_n_46,
D(16) => XEMAC_I_n_47,
D(15 downto 0) => ip2bus_data(15 downto 0),
E(0) => ping_pkt_lenth0,
\MDIO_GEN.mdio_data_out_reg[11]\ => I_AXI_NATIVE_IPIF_n_48,
\MDIO_GEN.mdio_data_out_reg[11]_0\ => I_AXI_NATIVE_IPIF_n_51,
\MDIO_GEN.mdio_data_out_reg[11]_1\ => I_AXI_NATIVE_IPIF_n_70,
\MDIO_GEN.mdio_data_out_reg[11]_2\(0) => I_AXI_NATIVE_IPIF_n_71,
\MDIO_GEN.mdio_data_out_reg[11]_3\ => I_AXI_NATIVE_IPIF_n_72,
\MDIO_GEN.mdio_data_out_reg[12]\ => I_AXI_NATIVE_IPIF_n_69,
\MDIO_GEN.mdio_data_out_reg[13]\ => I_AXI_NATIVE_IPIF_n_68,
\MDIO_GEN.mdio_data_out_reg[14]\ => I_AXI_NATIVE_IPIF_n_67,
\MDIO_GEN.mdio_data_out_reg[15]\ => I_AXI_NATIVE_IPIF_n_49,
\MDIO_GEN.mdio_data_out_reg[15]_0\ => I_AXI_NATIVE_IPIF_n_65,
\MDIO_GEN.mdio_data_out_reg[15]_1\ => I_AXI_NATIVE_IPIF_n_66,
\MDIO_GEN.mdio_data_out_reg[3]\ => I_AXI_NATIVE_IPIF_n_50,
\MDIO_GEN.mdio_en_i_reg\ => I_AXI_NATIVE_IPIF_n_54,
\MDIO_GEN.mdio_reg_addr_reg[4]\(0) => p_17_out,
\MDIO_GEN.mdio_wr_data_reg_reg[15]\(0) => p_15_out,
\MDIO_GEN.mdio_wr_data_reg_reg[15]_0\(4 downto 0) => mdio_wr_data_reg(15 downto 11),
Q(4) => data7(5),
Q(3 downto 0) => data7(3 downto 0),
\RX_PONG_REG_GEN.pong_rx_status_reg\ => I_AXI_NATIVE_IPIF_n_16,
SR(0) => bus_rst,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]\(0) => p_38_out,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(14 downto 4) => pong_pkt_lenth(15 downto 5),
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\(3 downto 0) => pong_pkt_lenth(3 downto 0),
\TX_PONG_REG_GEN.pong_soft_status_reg\ => I_AXI_NATIVE_IPIF_n_56,
enb => I_AXI_NATIVE_IPIF_n_59,
\gen_wr_b.gen_word_wide.mem_reg\ => I_AXI_NATIVE_IPIF_n_60,
\gen_wr_b.gen_word_wide.mem_reg_0\ => I_AXI_NATIVE_IPIF_n_61,
\gen_wr_b.gen_word_wide.mem_reg_1\ => I_AXI_NATIVE_IPIF_n_62,
gie_enable_reg => I_AXI_NATIVE_IPIF_n_55,
mdio_en_i => mdio_en_i,
mdio_rd_data_reg(4 downto 0) => mdio_rd_data_reg(15 downto 11),
p_15_in(0) => p_15_in(1),
p_17_in(1) => p_17_in(3),
p_17_in(0) => p_17_in(1),
p_19_out => p_19_out,
p_21_in144_in => p_21_in144_in,
p_33_in182_in => p_33_in182_in,
p_44_out => p_44_out,
p_5_in(0) => p_5_in(31),
p_9_in(1) => p_9_in(3),
p_9_in(0) => p_9_in(0),
\ping_pkt_lenth_reg[15]\ => I_AXI_NATIVE_IPIF_n_18,
\ping_pkt_lenth_reg[15]_0\(13 downto 3) => ping_pkt_lenth(15 downto 5),
\ping_pkt_lenth_reg[15]_0\(2 downto 0) => ping_pkt_lenth(3 downto 1),
ping_soft_status => ping_soft_status,
ping_soft_status_reg => I_AXI_NATIVE_IPIF_n_57,
ping_tx_status_reg => XEMAC_I_n_93,
pong_rx_status => pong_rx_status,
pong_soft_status => pong_soft_status,
reg_access => reg_access,
reg_access_reg => I_AXI_NATIVE_IPIF_n_53,
reg_data_out0 => reg_data_out0,
\reg_data_out_reg[0]\ => I_AXI_NATIVE_IPIF_n_9,
\reg_data_out_reg[0]_0\ => XEMAC_I_n_8,
\reg_data_out_reg[10]\ => I_AXI_NATIVE_IPIF_n_36,
\reg_data_out_reg[11]\ => I_AXI_NATIVE_IPIF_n_35,
\reg_data_out_reg[12]\ => I_AXI_NATIVE_IPIF_n_34,
\reg_data_out_reg[13]\ => I_AXI_NATIVE_IPIF_n_33,
\reg_data_out_reg[14]\ => I_AXI_NATIVE_IPIF_n_32,
\reg_data_out_reg[15]\ => I_AXI_NATIVE_IPIF_n_31,
\reg_data_out_reg[1]\ => I_AXI_NATIVE_IPIF_n_7,
\reg_data_out_reg[1]_0\ => I_AXI_NATIVE_IPIF_n_8,
\reg_data_out_reg[1]_1\ => XEMAC_I_n_7,
\reg_data_out_reg[2]\ => I_AXI_NATIVE_IPIF_n_11,
\reg_data_out_reg[2]_0\ => XEMAC_I_n_6,
\reg_data_out_reg[31]\ => I_AXI_NATIVE_IPIF_n_3,
\reg_data_out_reg[31]_0\ => I_AXI_NATIVE_IPIF_n_5,
\reg_data_out_reg[31]_1\ => XEMAC_I_n_3,
\reg_data_out_reg[3]\ => I_AXI_NATIVE_IPIF_n_6,
\reg_data_out_reg[3]_0\ => I_AXI_NATIVE_IPIF_n_12,
\reg_data_out_reg[3]_1\(10 downto 0) => bus2ip_addr(12 downto 2),
\reg_data_out_reg[4]\ => I_AXI_NATIVE_IPIF_n_30,
\reg_data_out_reg[5]\ => I_AXI_NATIVE_IPIF_n_10,
\reg_data_out_reg[6]\ => I_AXI_NATIVE_IPIF_n_13,
\reg_data_out_reg[6]_0\ => I_AXI_NATIVE_IPIF_n_14,
\reg_data_out_reg[6]_1\ => I_AXI_NATIVE_IPIF_n_15,
\reg_data_out_reg[6]_2\ => I_AXI_NATIVE_IPIF_n_40,
\reg_data_out_reg[7]\ => I_AXI_NATIVE_IPIF_n_39,
\reg_data_out_reg[8]\ => I_AXI_NATIVE_IPIF_n_38,
\reg_data_out_reg[9]\ => I_AXI_NATIVE_IPIF_n_37,
rx_intr_en0 => rx_intr_en0,
rx_intr_en_reg => I_AXI_NATIVE_IPIF_n_64,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(10 downto 0) => s_axi_araddr(12 downto 2),
s_axi_aresetn => \^s_axi_aresetn\,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(10 downto 0) => s_axi_awaddr(12 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rlast => \^s_axi_rlast\,
s_axi_rready => s_axi_rready,
s_axi_wdata(1) => s_axi_wdata(31),
s_axi_wdata(0) => s_axi_wdata(3),
s_axi_wready => \^s_axi_wready\,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid,
tx_intr_en0 => tx_intr_en0,
tx_intr_en_reg => I_AXI_NATIVE_IPIF_n_58,
web(0) => I_AXI_NATIVE_IPIF_n_63
);
\NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_RX\: unisim.vcomponents.BUFG
port map (
I => \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST_n_0\,
O => C
);
\NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.CLOCK_BUFG_TX\: unisim.vcomponents.BUFG
port map (
I => o,
O => phy_tx_clk_core
);
\NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST\: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => phy_rx_clk,
O => \NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.RX_IBUF_INST_n_0\
);
\NO_LOOPBACK_GEN.INCLUDE_BUFG_GEN.TX_IBUF_INST\: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => phy_tx_clk,
O => o
);
XEMAC_I: entity work.system_axi_ethernetlite_0_0_xemac
port map (
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[0]\ => XEMAC_I_n_8,
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[1]\ => XEMAC_I_n_7,
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[2]\ => XEMAC_I_n_6,
\AXI4_LITE_IF_GEN.IP2Bus_Data_sampled_reg[31]\ => XEMAC_I_n_3,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]\ => I_AXI_NATIVE_IPIF_n_62,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_0\ => I_AXI_NATIVE_IPIF_n_60,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[11]_1\ => I_AXI_NATIVE_IPIF_n_16,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]\(10 downto 0) => bus2ip_addr(12 downto 2),
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[12]_0\ => I_AXI_NATIVE_IPIF_n_61,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]\ => I_AXI_NATIVE_IPIF_n_8,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_0\ => I_AXI_NATIVE_IPIF_n_14,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_1\ => I_AXI_NATIVE_IPIF_n_13,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_2\ => I_AXI_NATIVE_IPIF_n_12,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_3\ => I_AXI_NATIVE_IPIF_n_49,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_4\ => I_AXI_NATIVE_IPIF_n_66,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_5\(0) => ping_pkt_lenth0,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[2]_6\(0) => p_38_out,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[3]\(0) => p_15_out,
\AXI4_LITE_IF_GEN.bus2ip_addr_i_reg[4]\ => I_AXI_NATIVE_IPIF_n_51,
\AXI4_LITE_IF_GEN.read_in_prog_reg\ => I_AXI_NATIVE_IPIF_n_15,
\AXI4_LITE_IF_GEN.read_in_prog_reg_0\ => I_AXI_NATIVE_IPIF_n_53,
\AXI4_LITE_IF_GEN.read_in_prog_reg_1\ => I_AXI_NATIVE_IPIF_n_30,
\AXI4_LITE_IF_GEN.read_in_prog_reg_2\ => I_AXI_NATIVE_IPIF_n_5,
\AXI4_LITE_IF_GEN.read_in_prog_reg_3\ => I_AXI_NATIVE_IPIF_n_48,
\AXI4_LITE_IF_GEN.read_in_prog_reg_4\ => I_AXI_NATIVE_IPIF_n_50,
\AXI4_LITE_IF_GEN.read_in_prog_reg_5\(0) => I_AXI_NATIVE_IPIF_n_71,
\AXI4_LITE_IF_GEN.read_in_prog_reg_6\ => I_AXI_NATIVE_IPIF_n_72,
\AXI4_LITE_IF_GEN.write_in_prog_reg\ => I_AXI_NATIVE_IPIF_n_55,
\AXI4_LITE_IF_GEN.write_in_prog_reg_0\ => I_AXI_NATIVE_IPIF_n_18,
CLK => C,
D(31) => ip2bus_data(31),
D(30) => XEMAC_I_n_33,
D(29) => XEMAC_I_n_34,
D(28) => XEMAC_I_n_35,
D(27) => XEMAC_I_n_36,
D(26) => XEMAC_I_n_37,
D(25) => XEMAC_I_n_38,
D(24) => XEMAC_I_n_39,
D(23) => XEMAC_I_n_40,
D(22) => XEMAC_I_n_41,
D(21) => XEMAC_I_n_42,
D(20) => XEMAC_I_n_43,
D(19) => XEMAC_I_n_44,
D(18) => XEMAC_I_n_45,
D(17) => XEMAC_I_n_46,
D(16) => XEMAC_I_n_47,
D(15 downto 0) => ip2bus_data(15 downto 0),
DIA(1) => phy_dv_reg,
DIA(0) => phy_rx_er_reg,
DIB(1) => Q2_out,
DIB(0) => Q0_out,
DIC(1) => Q,
DIC(0) => Q4_out,
E(0) => p_17_out,
IP2INTC_IRPT_REG_I_0(1) => p_17_in(3),
IP2INTC_IRPT_REG_I_0(0) => p_17_in(1),
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]\(4 downto 0) => mdio_rd_data_reg(15 downto 11),
\MDIO_CAPTURE_DATA[15].MDIO_RD_DATA_reg[15]_0\ => I_AXI_NATIVE_IPIF_n_65,
\MDIO_GEN.mdio_data_out_reg[15]_0\(4 downto 0) => mdio_wr_data_reg(15 downto 11),
\MDIO_GEN.mdio_en_i_reg_0\ => I_AXI_NATIVE_IPIF_n_54,
\MDIO_GEN.mdio_wr_data_reg_reg[11]_0\ => I_AXI_NATIVE_IPIF_n_70,
\MDIO_GEN.mdio_wr_data_reg_reg[12]_0\ => I_AXI_NATIVE_IPIF_n_69,
\MDIO_GEN.mdio_wr_data_reg_reg[13]_0\ => I_AXI_NATIVE_IPIF_n_68,
\MDIO_GEN.mdio_wr_data_reg_reg[14]_0\ => I_AXI_NATIVE_IPIF_n_67,
Q(4) => data7(5),
Q(3 downto 0) => data7(3 downto 0),
SR(0) => bus_rst,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[10]_0\ => I_AXI_NATIVE_IPIF_n_36,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[11]_0\ => I_AXI_NATIVE_IPIF_n_35,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[12]_0\ => I_AXI_NATIVE_IPIF_n_34,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[13]_0\ => I_AXI_NATIVE_IPIF_n_33,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[14]_0\ => I_AXI_NATIVE_IPIF_n_32,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[15]_0\ => I_AXI_NATIVE_IPIF_n_31,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[6]_0\ => I_AXI_NATIVE_IPIF_n_40,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[7]_0\ => I_AXI_NATIVE_IPIF_n_39,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[8]_0\ => I_AXI_NATIVE_IPIF_n_38,
\TX_PONG_REG_GEN.pong_pkt_lenth_reg[9]_0\ => I_AXI_NATIVE_IPIF_n_37,
\TX_PONG_REG_GEN.pong_soft_status_reg_0\ => I_AXI_NATIVE_IPIF_n_56,
enb => I_AXI_NATIVE_IPIF_n_59,
ip2intc_irpt => ip2intc_irpt,
mdio_en_i => mdio_en_i,
p_19_out => p_19_out,
p_21_in144_in => p_21_in144_in,
p_33_in182_in => p_33_in182_in,
p_44_out => p_44_out,
p_5_in(0) => p_5_in(31),
p_9_in(1) => p_9_in(3),
p_9_in(0) => p_9_in(0),
phy_crs => phy_crs,
phy_mdc => phy_mdc,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_tx_clk => phy_tx_clk_core,
ping_soft_status => ping_soft_status,
ping_soft_status_reg_0 => I_AXI_NATIVE_IPIF_n_57,
pong_rx_status => pong_rx_status,
pong_soft_status => pong_soft_status,
prmry_in => phy_tx_en_i,
prmry_vect_in(3 downto 0) => phy_tx_data_i(3 downto 0),
reg_access => reg_access,
reg_data_out0 => reg_data_out0,
\reg_data_out_reg[0]_0\ => XEMAC_I_n_93,
\reg_data_out_reg[0]_1\ => I_AXI_NATIVE_IPIF_n_9,
\reg_data_out_reg[1]_0\ => I_AXI_NATIVE_IPIF_n_7,
\reg_data_out_reg[2]_0\ => I_AXI_NATIVE_IPIF_n_11,
\reg_data_out_reg[31]_0\ => I_AXI_NATIVE_IPIF_n_3,
\reg_data_out_reg[3]_0\ => I_AXI_NATIVE_IPIF_n_6,
\reg_data_out_reg[5]_0\ => I_AXI_NATIVE_IPIF_n_10,
rx_intr_en0 => rx_intr_en0,
rx_intr_en_reg_0 => I_AXI_NATIVE_IPIF_n_64,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => \^s_axi_aresetn\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
\status_reg_reg[0]_0\(0) => p_15_in(1),
tx_intr_en0 => tx_intr_en0,
tx_intr_en_reg_0 => I_AXI_NATIVE_IPIF_n_58,
\tx_packet_length_reg[15]_0\(13 downto 3) => ping_pkt_lenth(15 downto 5),
\tx_packet_length_reg[15]_0\(2 downto 0) => ping_pkt_lenth(3 downto 1),
\tx_packet_length_reg[15]_1\(14 downto 4) => pong_pkt_lenth(15 downto 5),
\tx_packet_length_reg[15]_1\(3 downto 0) => pong_pkt_lenth(3 downto 0),
web(0) => I_AXI_NATIVE_IPIF_n_63
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_ethernetlite_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
phy_tx_clk : in STD_LOGIC;
phy_rx_clk : in STD_LOGIC;
phy_crs : in STD_LOGIC;
phy_dv : in STD_LOGIC;
phy_rx_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
phy_col : in STD_LOGIC;
phy_rx_er : in STD_LOGIC;
phy_rst_n : out STD_LOGIC;
phy_tx_en : out STD_LOGIC;
phy_tx_data : out STD_LOGIC_VECTOR ( 3 downto 0 );
phy_mdio_i : in STD_LOGIC;
phy_mdio_o : out STD_LOGIC;
phy_mdio_t : out STD_LOGIC;
phy_mdc : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_ethernetlite_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_ethernetlite_0_0 : entity is "system_axi_ethernetlite_0_0,axi_ethernetlite,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_ethernetlite_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_ethernetlite_0_0 : entity is "axi_ethernetlite,Vivado 2016.4";
end system_axi_ethernetlite_0_0;
architecture STRUCTURE of system_axi_ethernetlite_0_0 is
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_DUPLEX : integer;
attribute C_DUPLEX of U0 : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_INCLUDE_GLOBAL_BUFFERS : integer;
attribute C_INCLUDE_GLOBAL_BUFFERS of U0 : label is 1;
attribute C_INCLUDE_INTERNAL_LOOPBACK : integer;
attribute C_INCLUDE_INTERNAL_LOOPBACK of U0 : label is 0;
attribute C_INCLUDE_MDIO : integer;
attribute C_INCLUDE_MDIO of U0 : label is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of U0 : label is "axi_ethernetlite_inst";
attribute C_RX_PING_PONG : integer;
attribute C_RX_PING_PONG of U0 : label is 1;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 1;
attribute C_S_AXI_ACLK_PERIOD_PS : integer;
attribute C_S_AXI_ACLK_PERIOD_PS of U0 : label is 10000;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 13;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4LITE";
attribute C_TX_PING_PONG : integer;
attribute C_TX_PING_PONG of U0 : label is 1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_axi_ethernetlite_0_0_axi_ethernetlite
port map (
ip2intc_irpt => ip2intc_irpt,
phy_col => phy_col,
phy_crs => phy_crs,
phy_dv => phy_dv,
phy_mdc => phy_mdc,
phy_mdio_i => phy_mdio_i,
phy_mdio_o => phy_mdio_o,
phy_mdio_t => phy_mdio_t,
phy_rst_n => phy_rst_n,
phy_rx_clk => phy_rx_clk,
phy_rx_data(3 downto 0) => phy_rx_data(3 downto 0),
phy_rx_er => phy_rx_er,
phy_tx_clk => phy_tx_clk,
phy_tx_data(3 downto 0) => phy_tx_data(3 downto 0),
phy_tx_en => phy_tx_en,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(12 downto 0) => s_axi_araddr(12 downto 0),
s_axi_arburst(1 downto 0) => B"00",
s_axi_arcache(3 downto 0) => B"0000",
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(12 downto 0) => s_axi_awaddr(12 downto 0),
s_axi_awburst(1 downto 0) => B"00",
s_axi_awcache(3 downto 0) => B"0000",
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => '1',
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
entity timestamp is
Port ( ibus : in std_logic_vector(15 downto 0);
obus : out std_logic_vector(15 downto 0);
loadtsdiv : in std_logic;
readts : in std_logic;
readtsdiv : in std_logic;
tscount : out std_logic_vector (15 downto 0);
clk : in std_logic);
end timestamp;
architecture Behavioral of timestamp is
signal counter: std_logic_vector (15 downto 0);
signal div: std_logic_vector(15 downto 0);
alias divmsb: std_logic is div(15);
signal divlatch: std_logic_vector (15 downto 0);
begin
atimestamp: process (clk,readts, counter, readtsdiv, divlatch)
begin
if rising_edge(clk) then
div <= div -1;
if divmsb = '1' then
div <= divlatch;
counter <= counter + 1;
end if;
if loadtsdiv = '1' then
divlatch <= ibus;
end if;
end if; -- clk
obus <= (others => 'Z');
if readts = '1' then
obus <= counter;
end if;
if readtsdiv = '1' then
obus <= divlatch;
end if;
tscount <= counter;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------------------------
--
-- SPI to AXI4-Lite Bridge Testbench
--
-- Description:
-- OSVVM testbench for the SPI to AXI4-Lite Bridge component. Use SPI master verification
-- component (VC) to issue SPI transactions to the unit under test, and AXI4Lite subordinate
-- VC to emulate an AXI4 lite register bank.
--
-- Author(s):
-- Guy Eschemann, [email protected]
--
----------------------------------------------------------------------------------------------------
--
-- Copyright (c) 2022 Guy Eschemann
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
context OSVVM.OsvvmContext;
library osvvm_spi;
context osvvm_spi.SpiContext;
library osvvm_axi4;
context osvvm_axi4.Axi4LiteContext;
entity tb_spi2axi is
generic(
SPI_CPOL : natural range 0 to 1 := 0; -- SPI clock polarity
SPI_CPHA : natural range 0 to 1 := 0 -- SPI clock phase
);
end entity tb_spi2axi;
architecture TestHarness of tb_spi2axi is
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component tb_spi2axi_testctrl is
generic(
SPI_CPOL : natural range 0 to 1; -- SPI clock polarity
SPI_CPHA : natural range 0 to 1 -- SPI clock phase
);
port(
-- Record Interfaces
SpiRec : inout SpiRecType;
Axi4MemRec : inout AddressBusRecType;
-- Global Signal Interface
Clk : in std_logic;
nReset : in std_logic
);
end component;
------------------------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------------------------
constant AXI_ADDR_WIDTH : integer := 32; -- AXI address bus width, in bits
constant AXI_DATA_WIDTH : integer := 32;
constant AXI_STRB_WIDTH : integer := AXI_DATA_WIDTH / 8;
constant AXI_CLK_PERIOD : time := 10 ns;
constant TPD : time := 2 ns;
------------------------------------------------------------------------------------------------
-- Signals
------------------------------------------------------------------------------------------------
signal Axi4LiteBus : Axi4LiteRecType(
WriteAddress(Addr(AXI_ADDR_WIDTH - 1 downto 0)),
WriteData(Data(AXI_DATA_WIDTH - 1 downto 0), Strb(AXI_STRB_WIDTH - 1 downto 0)),
ReadAddress(Addr(AXI_ADDR_WIDTH - 1 downto 0)),
ReadData(Data(AXI_DATA_WIDTH - 1 downto 0))
);
signal Axi4MemRec : AddressBusRecType(
Address(AXI_ADDR_WIDTH - 1 downto 0),
DataToModel(AXI_DATA_WIDTH - 1 downto 0),
DataFromModel(AXI_DATA_WIDTH - 1 downto 0)
);
signal SpiRec : SpiRecType;
signal spi_sck : std_logic; -- SPI clock
signal spi_ss_n : std_logic; -- SPI slave select (low active)
signal spi_mosi : std_logic; -- SPI master-out-slave-in
signal spi_miso : std_logic; -- SPI master-in-slave-out
signal axi_aclk : std_logic;
signal axi_aresetn : std_logic;
signal s_axi_awvalid : std_logic;
signal s_axi_awvalid_mask : std_logic := '1'; -- @suppress "signal s_axi_awvalid_mask is never written"
signal s_axi_arvalid : std_logic;
signal s_axi_arvalid_mask : std_logic := '1'; -- @suppress "signal s_axi_arvalid_mask is never written"
begin
------------------------------------------------------------------------------------------------
-- Clock generator
------------------------------------------------------------------------------------------------
Osvvm.TbUtilPkg.CreateClock(
Clk => axi_aclk,
Period => AXI_CLK_PERIOD
);
------------------------------------------------------------------------------------------------
-- Reset generator
------------------------------------------------------------------------------------------------
Osvvm.TbUtilPkg.CreateReset(
Reset => axi_aresetn,
ResetActive => '0',
Clk => axi_aclk,
Period => 7 * AXI_CLK_PERIOD,
tpd => TPD
);
------------------------------------------------------------------------------------------------
-- Test controller
------------------------------------------------------------------------------------------------
testctrl_inst : tb_spi2axi_testctrl
generic map(
SPI_CPOL => SPI_CPOL,
SPI_CPHA => SPI_CPHA
)
port map(
SpiRec => SpiRec,
Axi4MemRec => Axi4MemRec,
Clk => axi_aclk,
nReset => axi_aresetn
);
------------------------------------------------------------------------------------------------
-- SPI master verification component
------------------------------------------------------------------------------------------------
spi_master_inst : entity osvvm_spi.Spi
generic map(
MODEL_ID_NAME => "Spi",
DEFAULT_SCLK_PERIOD => SPI_SCLK_PERIOD_1M
)
port map(
TransRec => SpiRec,
SCLK => spi_sck,
SS => spi_ss_n,
MOSI => spi_mosi,
MISO => spi_miso
);
------------------------------------------------------------------------------------------------
-- Unit under test
------------------------------------------------------------------------------------------------
uut : entity work.spi2axi
generic map(
SPI_CPOL => SPI_CPOL,
SPI_CPHA => SPI_CPHA,
AXI_ADDR_WIDTH => AXI_ADDR_WIDTH
)
port map(
spi_sck => spi_sck,
spi_ss_n => spi_ss_n,
spi_mosi => spi_mosi,
spi_miso => spi_miso,
axi_aclk => axi_aclk,
axi_aresetn => axi_aresetn,
s_axi_awaddr => Axi4LiteBus.WriteAddress.Addr,
s_axi_awprot => Axi4LiteBus.WriteAddress.Prot,
s_axi_awvalid => s_axi_awvalid, -- Axi4LiteBus.WriteAddress.Valid,
s_axi_awready => Axi4LiteBus.WriteAddress.Ready,
s_axi_wdata => Axi4LiteBus.WriteData.Data,
s_axi_wstrb => Axi4LiteBus.WriteData.Strb,
s_axi_wvalid => Axi4LiteBus.WriteData.Valid,
s_axi_wready => Axi4LiteBus.WriteData.Ready,
s_axi_araddr => Axi4LiteBus.ReadAddress.Addr,
s_axi_arprot => Axi4LiteBus.ReadAddress.Prot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => Axi4LiteBus.ReadAddress.Ready,
s_axi_rdata => Axi4LiteBus.ReadData.Data,
s_axi_rresp => Axi4LiteBus.ReadData.Resp,
s_axi_rvalid => Axi4LiteBus.ReadData.Valid,
s_axi_rready => Axi4LiteBus.ReadData.Ready,
s_axi_bresp => Axi4LiteBus.WriteResponse.Resp,
s_axi_bvalid => Axi4LiteBus.WriteResponse.Valid,
s_axi_bready => Axi4LiteBus.WriteResponse.Ready
);
Axi4LiteBus.WriteAddress.Valid <= s_axi_awvalid and s_axi_awvalid_mask;
Axi4LiteBus.ReadAddress.Valid <= s_axi_arvalid and s_axi_arvalid_mask;
------------------------------------------------------------------------------------------------
-- AXI4 lite memory verification component
------------------------------------------------------------------------------------------------
axi4lite_memory_inst : entity osvvm_axi4.Axi4LiteMemory
generic map(
MODEL_ID_NAME => "Axi4LiteMemory",
MEMORY_NAME => "Axi4LiteMemory",
tperiod_Clk => AXI_CLK_PERIOD
)
port map(
-- Globals
Clk => axi_aclk,
nReset => axi_aresetn,
-- AXI Manager Functional Interface
AxiBus => Axi4LiteBus,
-- Testbench Transaction Interface
TransRec => Axi4MemRec
);
end architecture TestHarness;
|
---------------------------------------------------------------------
-- TITLE: Multiplication and Division Unit
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mult.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the multiplication and division unit in 32 clocks.
--
-- To reduce space, compile your code using the flag "-mno-mul" which
-- will use software base routines in math.c if USE_SW_MULT is defined.
-- Then remove references to the entity mult in mlite_cpu.vhd.
--
-- MULTIPLICATION
-- long64 answer = 0;
-- for(i = 0; i < 32; ++i)
-- {
-- answer = (answer >> 1) + (((b&1)?a:0) << 31);
-- b = b >> 1;
-- }
--
-- DIVISION
-- long upper=a, lower=0;
-- a = b << 31;
-- for(i = 0; i < 32; ++i)
-- {
-- lower = lower << 1;
-- if(upper >= a && a && b < 2)
-- {
-- upper = upper - a;
-- lower |= 1;
-- }
-- a = ((b&2) << 30) | (a >> 1);
-- b = b >> 1;
-- }
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.mlite_pack.all;
entity mult is
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end; --entity mult
architecture logic of mult is
constant MODE_MULT : std_logic := '1';
constant MODE_DIV : std_logic := '0';
signal mode_reg : std_logic;
signal negate_reg : std_logic;
signal sign_reg : std_logic;
signal sign2_reg : std_logic;
signal count_reg : std_logic_vector(5 downto 0);
signal aa_reg : std_logic_vector(31 downto 0);
signal bb_reg : std_logic_vector(31 downto 0);
signal upper_reg : std_logic_vector(31 downto 0);
signal lower_reg : std_logic_vector(31 downto 0);
signal a_neg : std_logic_vector(31 downto 0);
signal b_neg : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(32 downto 0);
begin
-- Result
c_mult <=
-- BEGIN ENABLE_(MFLO)
lower_reg when mult_func = MULT_READ_LO and negate_reg = '0' else
bv_negate(lower_reg) when mult_func = MULT_READ_LO and negate_reg = '1' else
-- END ENABLE_(MFLO)
-- BEGIN ENABLE_(MFHI)
upper_reg when mult_func = MULT_READ_HI else
-- END ENABLE_(MFHI)
ZERO;
pause_out <=
-- BEGIN ENABLE_(MFLO)
'1' when (count_reg /= "000000") and (mult_func = MULT_READ_LO) else
-- END ENABLE_(MFLO)
-- BEGIN ENABLE_(MFHI)
'1' when (count_reg /= "000000") and (mult_func = MULT_READ_HI) else
-- END ENABLE_(MFHI)
'0';
-- ABS and remainder signals
a_neg <= bv_negate(a);
b_neg <= bv_negate(b);
-- BEGIN ENABLE_(MULT,MULTU,DIV,DIVU)
sum <= bv_adder(upper_reg, aa_reg, mode_reg);
-- END ENABLE_(MULT,MULTU,DIV,DIVU)
--multiplication / division unit
--mult_proc: process(clk, reset_in, a, b, mult_func,
-- a_neg, b_neg, sum, sign_reg, mode_reg, negate_reg,
-- count_reg, aa_reg, bb_reg, upper_reg, lower_reg)
mult_proc: process(clk, reset_in)
variable count : std_logic_vector(2 downto 0);
begin
if reset_in = '1' then
mode_reg <= '0';
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
count_reg <= "000000";
aa_reg <= ZERO;
bb_reg <= ZERO;
upper_reg <= ZERO;
lower_reg <= ZERO;
else
if rising_edge(clk) then
count := "001"; -- FOR DESIGN COMPILER (ASIC)
case mult_func is
-- BEGIN ENABLE_(MTLO)
when MULT_WRITE_LO =>
lower_reg <= a;
negate_reg <= '0';
-- END ENABLE_(MTLO)
-- BEGIN ENABLE_(MTHI)
when MULT_WRITE_HI =>
upper_reg <= a;
negate_reg <= '0';
-- END ENABLE_(MTHI)
-- BEGIN ENABLE_(MULTU)
when MULT_MULT =>
mode_reg <= MODE_MULT;
aa_reg <= a;
bb_reg <= b;
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
sign_reg <= '0';
sign2_reg <= '0';
-- END ENABLE_(MULTU)
-- BEGIN ENABLE_(MULT)
when MULT_SIGNED_MULT =>
mode_reg <= MODE_MULT;
if b(31) = '0' then
aa_reg <= a;
bb_reg <= b;
else
aa_reg <= a_neg;
bb_reg <= b_neg;
end if;
sign_reg <= a(31) xor b(31);
sign2_reg <= '0';
upper_reg <= ZERO;
count_reg <= "100000";
negate_reg <= '0';
-- END ENABLE_(MULT)
-- BEGIN ENABLE_(DIVU)
when MULT_DIVIDE =>
mode_reg <= MODE_DIV;
aa_reg <= b(0) & ZERO(30 downto 0);
bb_reg <= b;
upper_reg <= a;
count_reg <= "100000";
negate_reg <= '0';
-- END ENABLE_(DIVU)
-- BEGIN ENABLE_(DIV)
when MULT_SIGNED_DIVIDE =>
mode_reg <= MODE_DIV;
if b(31) = '0' then
aa_reg(31) <= b(0);
bb_reg <= b;
else
aa_reg(31) <= b_neg(0);
bb_reg <= b_neg;
end if;
if a(31) = '0' then
upper_reg <= a;
else
upper_reg <= a_neg;
end if;
aa_reg(30 downto 0) <= ZERO(30 downto 0);
count_reg <= "100000";
negate_reg <= a(31) xor b(31);
-- END ENABLE_(DIV)
when others =>
-- BEGIN ENABLE_(MULT,MULTU,DIV,DIVU)
if count_reg /= "000000" then
-- END ENABLE_(MULT,MULTU,DIV,DIVU)
if mode_reg = MODE_MULT then
-- BEGIN ENABLE_(MULT,MULTU)
-- Multiplication
if bb_reg(0) = '1' then
upper_reg <= (sign_reg xor sum(32)) & sum(31 downto 1);
lower_reg <= sum(0) & lower_reg(31 downto 1);
sign2_reg <= sign2_reg or sign_reg;
sign_reg <= '0';
bb_reg <= '0' & bb_reg(31 downto 1);
-- The following six lines are optional for speedup
elsif bb_reg(3 downto 0) = "0000" and sign2_reg = '0' and
count_reg(5 downto 2) /= "0000" then
upper_reg <= "0000" & upper_reg(31 downto 4);
lower_reg <= upper_reg(3 downto 0) & lower_reg(31 downto 4);
count := "100";
bb_reg <= "0000" & bb_reg(31 downto 4);
else
upper_reg <= sign2_reg & upper_reg(31 downto 1);
lower_reg <= upper_reg(0) & lower_reg(31 downto 1);
bb_reg <= '0' & bb_reg(31 downto 1);
end if;
-- END ENABLE_(MULT,MULTU)
else
-- BEGIN ENABLE_(DIV,DIVU)
-- Division
if sum(32) = '0' and aa_reg /= ZERO and
bb_reg(31 downto 1) = ZERO(31 downto 1) then
upper_reg <= sum(31 downto 0);
lower_reg(0) <= '1';
else
lower_reg(0) <= '0';
end if;
aa_reg <= bb_reg(1) & aa_reg(31 downto 1);
lower_reg(31 downto 1) <= lower_reg(30 downto 0);
bb_reg <= '0' & bb_reg(31 downto 1);
-- END ENABLE_(DIV,DIVU)
end if;
-- BEGIN ENABLE_(MULT,MULTU,DIV,DIVU)
count_reg <= count_reg - count;
end if;
-- END ENABLE_(MULT,MULTU,DIV,DIVU)
end case;
end if;
end if;
end process;
end; --architecture logic
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
generic (
-- This can be overridden to change the refresh rate. The anode pattern will change at a
-- frequency given by F(clk_in) / (2**COUNTER_WIDTH). So for a 50MHz clk_in and
-- COUNTER_WIDTH=18, the anode pattern changes at ~191Hz, which means each digit gets
-- refreshed at ~48Hz.
COUNTER_WIDTH : integer := 27
);
port(
sysClk_in : in std_logic;
led_out : out std_logic_vector(1 downto 0)
);
end entity;
architecture rtl of top_level is
signal count : unsigned(COUNTER_WIDTH-1 downto 0) := (others => '0');
signal count_next : unsigned(COUNTER_WIDTH-1 downto 0);
begin
-- Infer registers
process(sysClk_in)
begin
if ( rising_edge(sysClk_in) ) then
count <= count_next;
end if;
end process;
count_next <= count + 1;
led_out <= std_logic_vector(count(COUNTER_WIDTH-1 downto COUNTER_WIDTH-2));
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(20-1 DOWNTO 0);
DOUT : OUT std_logic_vector(20-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes;
architecture xilinx of system_axi_vdma_0_wrapper_fifo_generator_v9_1_1_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component system_axi_vdma_0_wrapper_fifo_generator_v9_1_1 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(20-1 DOWNTO 0);
DOUT : OUT std_logic_vector(20-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : system_axi_vdma_0_wrapper_fifo_generator_v9_1_1
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity train4_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(0 downto 0)
);
end train4_hot;
architecture behaviour of train4_hot is
constant st0: std_logic_vector(3 downto 0) := "1000";
constant st1: std_logic_vector(3 downto 0) := "0100";
constant st2: std_logic_vector(3 downto 0) := "0010";
constant st3: std_logic_vector(3 downto 0) := "0001";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-";
case current_state is
when st0 =>
if std_match(input, "00") then next_state <= st0; output <= "0";
elsif std_match(input, "10") then next_state <= st1; output <= "-";
elsif std_match(input, "01") then next_state <= st1; output <= "-";
end if;
when st1 =>
if std_match(input, "10") then next_state <= st1; output <= "1";
elsif std_match(input, "01") then next_state <= st1; output <= "1";
elsif std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
end if;
when st2 =>
if std_match(input, "00") then next_state <= st2; output <= "1";
elsif std_match(input, "11") then next_state <= st2; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "10") then next_state <= st3; output <= "1";
end if;
when st3 =>
if std_match(input, "10") then next_state <= st3; output <= "1";
elsif std_match(input, "01") then next_state <= st3; output <= "1";
elsif std_match(input, "00") then next_state <= st0; output <= "-";
end if;
when others => next_state <= "----"; output <= "-";
end case;
end process;
end behaviour;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:26:59 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_rgb888_to_rgb565_0_0/system_rgb888_to_rgb565_0_0_sim_netlist.vhdl
-- Design : system_rgb888_to_rgb565_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_rgb888_to_rgb565_0_0 is
port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_rgb888_to_rgb565_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_rgb888_to_rgb565_0_0 : entity is "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_rgb888_to_rgb565_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_rgb888_to_rgb565_0_0 : entity is "rgb888_to_rgb565,Vivado 2016.4";
end system_rgb888_to_rgb565_0_0;
architecture STRUCTURE of system_rgb888_to_rgb565_0_0 is
signal \^rgb_888\ : STD_LOGIC_VECTOR ( 23 downto 0 );
begin
\^rgb_888\(23 downto 19) <= rgb_888(23 downto 19);
\^rgb_888\(15 downto 10) <= rgb_888(15 downto 10);
\^rgb_888\(7 downto 3) <= rgb_888(7 downto 3);
rgb_565(15 downto 11) <= \^rgb_888\(23 downto 19);
rgb_565(10 downto 5) <= \^rgb_888\(15 downto 10);
rgb_565(4 downto 0) <= \^rgb_888\(7 downto 3);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.defs.all;
entity phasedetect is
port(xx_in : in signed36; -- overkill, could have reduced to 18 bits by now.
yy_in : in signed36;
in_last : in std_logic;
phase : out unsigned18;
out_strobe : out std_logic;
out_last : out std_logic;
phasor_last : in unsigned18;
clk : in std_logic);
end phasedetect;
-- The main phase detect uses a pipeline, 16 iterations, main usage is
-- (iterations 1 to 15):
-- stage1: yy_div = yy right-shifted (by 2n).
-- stage2: trial xx' = xx + yy_div, yy' = yy - xx
-- stage3: commit, if yy' has not underflown, update angle.
-- We want to reuse the first time through the pipeline:
-- shift=0. If no underflow, then swap xx and yy.
-- We load every 20 (?) cycles,
-- and ship out 60 cycles later.
-- The phase detection is bypassed when out_last is asserted; we take
-- phasor_last instead.
architecture behavioural of phasedetect is
constant width : integer := 20;
subtype xunsigned is unsigned(width - 1 downto 0);
subtype yunsigned is unsigned(width downto 0);
signal shift : boolean;
signal x_shift, y_shift : unsigned36;
signal shift_last : std_logic;
signal xx1 : xunsigned; -- Real component.
signal yy1 : yunsigned; -- Imaginary component.
signal last1 : std_logic;
signal angle1 : unsigned18; -- Accumulated angle.
signal positive1 : boolean; -- Positive adjustments to angle.
signal xx2 : xunsigned;
signal yy2 : yunsigned;
signal yy2_shifted : yunsigned;
signal angle2 : unsigned18;
signal positive2 : boolean;
signal load2 : boolean;
signal last2 : std_logic;
signal xx3 : xunsigned;
signal yy3 : yunsigned;
signal xx3_trial : xunsigned;
signal yy3_trial : yunsigned;
signal angle3 : unsigned18;
signal angle3_update : unsigned16;
signal positive3 : boolean;
signal start3 : boolean;
signal last3 : std_logic;
signal count : integer range 0 to 19;
type stage_t is array(0 to 19) of integer range 0 to 19;
-- For pipeline stage 1, map the cycle counter to the iteration of the
-- calculation.
constant iteration1 : stage_t :=
(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
-- Iteration number for pipeline stage 2.
constant iteration2 : stage_t :=
(13, 14, 15, 16, 17, 18, 19, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12);
-- Iteration number for pipeline stage 3.
constant iteration3 : stage_t :=
(6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 0, 1, 2, 3, 4, 5);
-- Angle updates. Exhaustive testing indicates that the odd first value is
-- best.
type angles_t is array(0 to 19) of unsigned16;
constant angle_update : angles_t :=
(x"fffe", x"4b90", x"27ed", x"1444",
x"0a2c", x"0517", x"028c", x"0146",
x"00a3", x"0051", x"0029", x"0014",
x"000a", x"0005", x"0003", x"0001",
x"0000", x"0000", x"0000", x"0000");
begin
process
begin
wait until rising_edge(clk);
-- Preprocess each sample for 20 cycles, left shifting as much as possible.
-- This reduces the precision required in the main calculations.
if shift then
if load2 then
x_shift <= unsigned(xx_in);
y_shift <= unsigned(yy_in);
shift_last <= in_last;
else
x_shift <= x_shift sll 1;
y_shift <= y_shift sll 1;
end if;
end if;
if count = 19 then
shift <= true; -- Same cycle as load2.
elsif load2 then
shift <= xx_in(35) = xx_in(34) and yy_in(35) = yy_in(34);
else
shift <= shift and
x_shift(34) = x_shift(33) and y_shift(34) = y_shift(33);
end if;
if count >= 13 then
count <= count - 13;
else
count <= count + 7;
end if;
start3 <= (count = 7);
-- The default flow is just to cycle things around; override later if
-- need be.
xx2 <= xx1;
yy2 <= yy1;
angle2 <= angle1;
positive2 <= positive1;
last2 <= last1;
xx3 <= xx2;
-- Include left shift. If this loses a bit, then the trial will succeed
-- anyway, and get us back.
yy3 <= yy2 sll 1;
angle3 <= angle2;
positive3 <= positive2;
last3 <= last2;
xx1 <= xx3;
yy1 <= yy3;
angle1 <= angle3;
positive1 <= positive3;
last1 <= last3;
-- First pipeline stage is the right shift. Note that for the start
-- iteration, the high bit of yy is still zero, so the high bit of
-- yy_shifted will always be zero.
yy2_shifted <= yy1 srl (2 * (count mod 16));
load2 <= (count = 19);
-- Second pipeline stage is the trial operation. It also handles the
-- loading of data into the pipeline.
xx3_trial <= xx2 + yy2_shifted(width - 1 downto 0);
-- Note that yy is at most twice the 36 bit xx, so if the arithmetic does
-- not overflow, then the result of the subtract will fit in 36 bits.
-- Except for round-0 (where we normalise to the first octant). In that
-- case everything is 36 bits.
yy3_trial <= yy2 - ('0' & xx2);
angle3_update <= angle_update(iteration2(count));
if load2 then
last3 <= shift_last;
yy3_trial(width) <= '1'; -- Make sure we don't adjust on next cycle.
-- 'not' is cheaper than proper true negation. And given our
-- round-towards-negative behaviour, more accurate.
if x_shift(35) = '0' then
xx3 <= x_shift(35 downto 36 - width);
else
xx3 <= not x_shift(35 downto 36 - width);
end if;
if y_shift(35) = '0' then
yy3 <= '0' & y_shift(35 downto 36 - width);
else
yy3 <= '0' & not y_shift(35 downto 36 - width);
end if;
positive3 <= (x_shift(35) xor y_shift(35)) = '1';
-- Our convention is that angle zero covers the first sliver of the
-- first quadrant etc., so bias the start angle just into the
-- appropriate quadrant. Yes the 0=>1 looks like a step too far,
-- but after exhaustive testing, it gives better results, presumably
-- because of the granularity of the result.
angle3 <= (17 => y_shift(35), 0 => '1',
others => x_shift(35) xor y_shift(35));
if last2 = '1' then
phase <= phasor_last;
else
phase <= angle2; -- ship out previous result.
end if;
out_last <= last2;
end if;
out_strobe <= b2s(load2);
-- Third pipeline stage is commitment.
if yy3_trial(width) = '0' then
if not start3 then
xx1 <= xx3_trial;
-- yy got left shifted at the previous stage, but yy_trial did not.
-- so take that into account.
yy1 <= yy3_trial sll 1;
else
-- No overflow, yy is bigger than xx, so swap things over. Remember
-- that yy got left shifted, so take that into account in the swap.
xx1 <= yy3(width downto 1);
yy1 <= xx3 & '0';
positive1 <= not positive3;
end if;
if positive3 then
angle1 <= angle3 + ("00" & angle3_update);
else
angle1 <= angle3 - ("00" & angle3_update);
end if;
end if;
end process;
end behavioural;
|
entity tb_func06 is
end tb_func06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func06 is
signal r : std_logic_vector(15 downto 0);
signal s : natural;
begin
dut: entity work.func06
port map (s, r);
process
begin
s <= 2;
wait for 1 ns;
assert r = x"1234" severity failure;
s <= 0;
wait for 1 ns;
assert r = x"0000" severity failure;
s <= 3;
wait for 1 ns;
assert r = x"5678" severity failure;
s <= 4;
wait for 1 ns;
assert r = x"0000" severity failure;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
package orbit_intlk_pkg is
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant c_CHAN_X_IDX : natural := 0;
constant c_CHAN_Y_IDX : natural := 1;
constant c_CHAN_Q_IDX : natural := 2;
constant c_CHAN_SUM_IDX : natural := 3;
constant c_CHAN_A_IDX : natural := 0;
constant c_CHAN_B_IDX : natural := 1;
constant c_CHAN_C_IDX : natural := 2;
constant c_CHAN_D_IDX : natural := 3;
constant c_NUM_CHANNELS : natural := 4;
constant c_BPM_DS_IDX : natural := 0;
constant c_BPM_US_IDX : natural := 1;
constant c_NUM_BPMS : natural := 2;
-- generate interlock logic up to which channel?
constant c_INTLK_GEN_UPTO_CHANNEL : natural := c_CHAN_Y_IDX;
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component orbit_intlk
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Interlock enable and limits signals
-----------------------------
intlk_en_i : in std_logic;
intlk_clr_i : in std_logic;
-- Minimum threshold interlock on/off
intlk_min_sum_en_i : in std_logic;
-- Minimum threshold to interlock
intlk_min_sum_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-- Translation interlock on/off
intlk_trans_en_i : in std_logic;
-- Translation interlock clear
intlk_trans_clr_i : in std_logic;
intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-- Angular interlock on/off
intlk_ang_en_i : in std_logic;
-- Angular interlock clear
intlk_ang_clr_i : in std_logic;
intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_trans_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_trans_o : out std_logic;
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ang_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_ang_o : out std_logic;
-- only cleared when intlk_clr_i is asserted
intlk_ltc_o : out std_logic;
-- conditional to intlk_en_i
intlk_o : out std_logic
);
end component;
component orbit_intlk_trans is
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Interlock enable and limits signals
-----------------------------
-- Translation interlock on/off
intlk_trans_en_i : in std_logic;
-- Translation interlock clear
intlk_trans_clr_i : in std_logic;
intlk_trans_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_trans_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-----------------------------
-- Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_trans_bigger_x_o : out std_logic;
intlk_trans_bigger_y_o : out std_logic;
intlk_trans_bigger_ltc_x_o : out std_logic;
intlk_trans_bigger_ltc_y_o : out std_logic;
intlk_trans_bigger_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_bigger_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_bigger_o : out std_logic;
intlk_trans_smaller_x_o : out std_logic;
intlk_trans_smaller_y_o : out std_logic;
intlk_trans_smaller_ltc_x_o : out std_logic;
intlk_trans_smaller_ltc_y_o : out std_logic;
intlk_trans_smaller_any_o : out std_logic;
-- only cleared when intlk_trans_clr_i is asserted
intlk_trans_smaller_ltc_o : out std_logic;
-- conditional to intlk_trans_en_i
intlk_trans_smaller_o : out std_logic
);
end component;
component orbit_intlk_ang is
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Interlock enable and limits signals
-----------------------------
-- Angular interlock on/off
intlk_ang_en_i : in std_logic;
-- Angular interlock clear
intlk_ang_clr_i : in std_logic;
intlk_ang_max_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_max_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_x_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
intlk_ang_min_y_i : in std_logic_vector(g_INTLK_LMT_WIDTH-1 downto 0);
-----------------------------
-- Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Interlock outputs
-----------------------------
intlk_ang_bigger_x_o : out std_logic;
intlk_ang_bigger_y_o : out std_logic;
intlk_ang_bigger_ltc_x_o : out std_logic;
intlk_ang_bigger_ltc_y_o : out std_logic;
intlk_ang_bigger_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_bigger_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_bigger_o : out std_logic;
intlk_ang_smaller_x_o : out std_logic;
intlk_ang_smaller_y_o : out std_logic;
intlk_ang_smaller_ltc_x_o : out std_logic;
intlk_ang_smaller_ltc_y_o : out std_logic;
intlk_ang_smaller_any_o : out std_logic;
-- only cleared when intlk_ang_clr_i is asserted
intlk_ang_smaller_ltc_o : out std_logic;
-- conditional to intlk_ang_en_i
intlk_ang_smaller_o : out std_logic
);
end component;
component orbit_intlk_cdc_fifo
generic
(
g_data_width : natural;
g_size : natural
);
port
(
clk_wr_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
valid_i : in std_logic;
clk_rd_i : in std_logic;
rd_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
valid_o : out std_logic;
empty_o : out std_logic
);
end component;
component orbit_intlk_cdc
generic
(
g_ADC_WIDTH : natural := 16;
g_DECIM_WIDTH : natural := 32;
-- interlock limits
g_INTLK_LMT_WIDTH : natural := 32
);
port
(
-----------------------------
-- Clocks and resets
-----------------------------
ref_rst_n_i : in std_logic;
ref_clk_i : in std_logic;
-----------------------------
-- Downstream ADC and position signals
-----------------------------
fs_clk_ds_i : in std_logic;
adc_ds_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_i : in std_logic := '0';
decim_ds_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_i : in std_logic;
-----------------------------
-- Upstream ADC and position signals
-----------------------------
fs_clk_us_i : in std_logic;
adc_us_ch0_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_i : in std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_i : in std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_i : in std_logic := '0';
decim_us_pos_x_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_i : in std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_i : in std_logic;
-----------------------------
-- Synched Downstream ADC and position signals
-----------------------------
adc_ds_ch0_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch1_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch2_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_ch3_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_ds_tag_o : out std_logic_vector(0 downto 0) := (others => '0');
adc_ds_swap_valid_o : out std_logic := '0';
decim_ds_pos_x_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_y_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_q_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_sum_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_ds_pos_valid_o : out std_logic;
-----------------------------
-- Synched Upstream ADC and position signals
-----------------------------
adc_us_ch0_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch1_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch2_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_ch3_swap_o : out std_logic_vector(g_ADC_WIDTH-1 downto 0) := (others => '0');
adc_us_tag_o : out std_logic_vector(0 downto 0) := (others => '0');
adc_us_swap_valid_o : out std_logic := '0';
decim_us_pos_x_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_y_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_q_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_sum_o : out std_logic_vector(g_DECIM_WIDTH-1 downto 0);
decim_us_pos_valid_o : out std_logic
);
end component;
constant c_xwb_orbit_intlk_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"87efeda8",
version => x"00000001",
date => x"20200612",
name => "LNLS_INTLK_REGS ")));
end orbit_intlk_pkg;
package body orbit_intlk_pkg is
end orbit_intlk_pkg;
|
entity FIFO is
end entity;
entity --Comment
--Comment
--Comment
FIFO is
end
entity;
|
-- Accellera Standard V2.3 Open Verification Library (OVL).
-- Accellera Copyright (c) 2008. All rights reserved.
-- NOTE : This file is not suitable for use with synthesis tools, use
-- std_ovl_procs_syn.vhd instead.
library ieee;
use ieee.std_logic_1164.all;
use work.std_ovl.all;
use std.textio.all;
package std_ovl_procs is
------------------------------------------------------------------------------
-- Users must only use the ovl_set_msg and ovl_print_init_count_proc --
-- subprograms. All other subprograms are for internal use only. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_set_msg
--
-- This allows the default message string to be set for a
-- ovl_ctrl_record.msg_default constant.
------------------------------------------------------------------------------
function ovl_set_msg (
constant default : in string
) return string;
------------------------------------------------------------------------------
-- ovl_print_init_count_proc
--
-- This is used to print a message stating the number of checkers that have
-- been initialized.
------------------------------------------------------------------------------
procedure ovl_print_init_count_proc (
constant controls : in ovl_ctrl_record
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_error_proc
------------------------------------------------------------------------------
procedure ovl_error_proc (
constant err_msg : in string;
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
signal fatal_sig : out std_logic;
variable error_count : inout natural
);
------------------------------------------------------------------------------
-- ovl_init_msg_proc
------------------------------------------------------------------------------
procedure ovl_init_msg_proc (
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record
);
------------------------------------------------------------------------------
-- ovl_cover_proc
------------------------------------------------------------------------------
procedure ovl_cover_proc (
constant cvr_msg : in string;
constant assert_name : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
variable cover_count : inout natural
);
------------------------------------------------------------------------------
-- ovl_finish_proc
------------------------------------------------------------------------------
procedure ovl_finish_proc (
constant assert_name : in string;
constant path : in string;
constant runtime_after_fatal : in string;
signal fatal_sig : in std_logic
);
------------------------------------------------------------------------------
-- ovl_2state_is_on
------------------------------------------------------------------------------
function ovl_2state_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type
) return boolean;
------------------------------------------------------------------------------
-- ovl_xcheck_is_on
------------------------------------------------------------------------------
function ovl_xcheck_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type;
constant explicit_x_check : in boolean
) return boolean;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in integer;
constant default_ctrl_val : in natural
) return natural;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in string;
constant default_ctrl_val : in string
) return string;
------------------------------------------------------------------------------
-- cover_item_set
------------------------------------------------------------------------------
function cover_item_set (
constant level : in ovl_coverage_level;
constant item : in ovl_coverage_level
) return boolean;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic
) return boolean;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic_vector
) return boolean;
------------------------------------------------------------------------------
-- or_reduce
------------------------------------------------------------------------------
function or_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- and_reduce
------------------------------------------------------------------------------
function and_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- xor_reduce
------------------------------------------------------------------------------
function xor_reduce (
v : in std_logic_vector
) return std_logic;
------------------------------------------------------------------------------
-- "sll"
------------------------------------------------------------------------------
function "sll" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector;
------------------------------------------------------------------------------
-- "srl"
------------------------------------------------------------------------------
function "srl" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned comparison functions --
-- Note: the width of l must be > 0. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ">"
------------------------------------------------------------------------------
function ">" (
l : in std_logic_vector;
r : in natural
) return boolean;
------------------------------------------------------------------------------
-- "<"
------------------------------------------------------------------------------
function "<" (
l : in std_logic_vector;
r : in natural
) return boolean;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
type err_array is array (ovl_severity_level_natural) of string (1 to 16);
constant err_typ : err_array := (OVL_FATAL => " OVL_FATAL",
OVL_ERROR => " OVL_ERROR",
OVL_WARNING => " OVL_WARNING",
OVL_INFO => " OVL_INFO");
end package std_ovl_procs;
package body std_ovl_procs is
------------------------------------------------------------------------------
-- Users must only use the ovl_set_msg and ovl_print_init_count_proc --
-- subprograms. All other subprograms are for internal use only. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_set_msg
--
-- This allows the default message string to be set for a
-- ovl_ctrl_record.msg_default constant.
------------------------------------------------------------------------------
function ovl_set_msg (
constant default : in string
) return string is
variable new_default : ovl_msg_default_type := (others => NUL);
begin
new_default(1 to default'high) := default;
return new_default;
end function ovl_set_msg;
------------------------------------------------------------------------------
-- ovl_print_init_count_proc
--
-- This is used to print a message stating the number of checkers that have
-- been initialized.
------------------------------------------------------------------------------
procedure ovl_print_init_count_proc (
constant controls : in ovl_ctrl_record
) is
variable ln : line;
begin
if ((controls.init_msg_ctrl = OVL_ON) and (controls.init_count_ctrl = OVL_ON)) then
writeline(output, ln);
write(ln, "OVL_METRICS: " & integer'image(ovl_init_count) & " OVL assertions initialized");
writeline(output, ln);
writeline(output, ln);
end if;
end procedure ovl_print_init_count_proc;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ovl_error_proc
------------------------------------------------------------------------------
procedure ovl_error_proc (
constant err_msg : in string;
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
signal fatal_sig : out std_logic;
variable error_count : inout natural
) is
variable ln : line;
constant severity_level_ctrl : ovl_severity_level_natural :=
ovl_get_ctrl_val(severity_level, controls.severity_level_default);
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
constant msg_ctrl : string :=
ovl_get_ctrl_val(msg, controls.msg_default);
begin
error_count := error_count + 1;
if (error_count <= controls.max_report_error) then
case (property_type_ctrl) is
when OVL_ASSERT | OVL_ASSUME | OVL_ASSERT_2STATE | OVL_ASSUME_2STATE =>
write(ln, err_typ(severity_level_ctrl) & " : "
& assert_name & " : "
& msg_ctrl & " : "
& err_msg
& " : severity " & ovl_severity_level'image(severity_level_ctrl)
& " : time " & time'image(now)
& " " & path);
writeline(output, ln);
when OVL_IGNORE => null;
end case;
end if;
if ((severity_level_ctrl = OVL_FATAL) and (controls.finish_ctrl = OVL_ON)) then
fatal_sig <= '1';
end if;
end procedure ovl_error_proc;
------------------------------------------------------------------------------
-- ovl_init_msg_proc
------------------------------------------------------------------------------
procedure ovl_init_msg_proc (
constant severity_level : in ovl_severity_level;
constant property_type : in ovl_property_type;
constant assert_name : in string;
constant msg : in string;
constant path : in string;
constant controls : in ovl_ctrl_record
) is
variable ln : line;
constant severity_level_ctrl : ovl_severity_level_natural :=
ovl_get_ctrl_val(severity_level, controls.severity_level_default);
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
constant msg_ctrl : string :=
ovl_get_ctrl_val(msg, controls.msg_default);
begin
if (controls.init_count_ctrl = OVL_ON) then
ovl_init_count := ovl_init_count + 1;
else
case (property_type_ctrl) is
when OVL_ASSERT | OVL_ASSUME | OVL_ASSERT_2STATE | OVL_ASSUME_2STATE =>
write(ln, "OVL_NOTE: " & OVL_VERSION & ": "
& assert_name
& " initialized @ " & path
& " Severity: " & ovl_severity_level'image(severity_level_ctrl)
& ", Message: " & msg_ctrl);
writeline(output, ln);
when OVL_IGNORE => NULL;
end case;
end if;
end procedure ovl_init_msg_proc;
------------------------------------------------------------------------------
-- ovl_cover_proc
------------------------------------------------------------------------------
procedure ovl_cover_proc (
constant cvr_msg : in string;
constant assert_name : in string;
constant path : in string;
constant controls : in ovl_ctrl_record;
variable cover_count : inout natural
) is
variable ln : line;
begin
cover_count := cover_count + 1;
if (cover_count <= controls.max_report_cover_point) then
write(ln, "OVL_COVER_POINT : "
& assert_name & " : "
& cvr_msg & " : "
& "time " & time'image(now)
& " " & path);
writeline(output, ln);
end if;
end procedure ovl_cover_proc;
------------------------------------------------------------------------------
-- ovl_finish_proc
------------------------------------------------------------------------------
procedure ovl_finish_proc (
constant assert_name : in string;
constant path : in string;
constant runtime_after_fatal : in string;
signal fatal_sig : in std_logic
) is
variable ln : line;
variable runtime_after_fatal_time : time;
begin
if (fatal_sig = '1') then
-- convert string to time
write(ln, runtime_after_fatal);
read(ln, runtime_after_fatal_time);
wait for runtime_after_fatal_time;
report " OVL : Simulation stopped due to a fatal error : " & assert_name & " : " & "time " &
time'image(now) & " " & path severity failure;
end if;
end procedure ovl_finish_proc;
------------------------------------------------------------------------------
-- ovl_2state_is_on
------------------------------------------------------------------------------
function ovl_2state_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type
) return boolean is
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
begin
return (controls.assert_ctrl = OVL_ON) and
(property_type_ctrl /= OVL_IGNORE);
end function ovl_2state_is_on;
------------------------------------------------------------------------------
-- ovl_xcheck_is_on
------------------------------------------------------------------------------
function ovl_xcheck_is_on (
constant controls : in ovl_ctrl_record;
constant property_type : in ovl_property_type;
constant explicit_x_check : in boolean
) return boolean is
constant property_type_ctrl : ovl_property_type_natural :=
ovl_get_ctrl_val(property_type, controls.property_type_default);
begin
return (controls.assert_ctrl = OVL_ON) and
(property_type_ctrl /= OVL_IGNORE) and
(property_type_ctrl /= OVL_ASSERT_2STATE) and
(property_type_ctrl /= OVL_ASSUME_2STATE) and
(controls.xcheck_ctrl = OVL_ON) and
((controls.implicit_xcheck_ctrl = OVL_ON) or explicit_x_check);
end function ovl_xcheck_is_on;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in integer;
constant default_ctrl_val : in natural
) return natural is
begin
if (instance_val = OVL_NOT_SET) then
return default_ctrl_val;
else
return instance_val;
end if;
end function ovl_get_ctrl_val;
------------------------------------------------------------------------------
-- ovl_get_ctrl_val
------------------------------------------------------------------------------
function ovl_get_ctrl_val (
constant instance_val : in string;
constant default_ctrl_val : in string
) return string is
variable msg_default_width : integer := ovl_msg_default_type'high;
begin
if (instance_val = OVL_MSG_NOT_SET) then
-- get width of msg_default value
for i in 1 to ovl_msg_default_type'high loop
if (default_ctrl_val(i) = NUL) then
msg_default_width := i - 1;
exit;
end if;
end loop;
return default_ctrl_val(1 to msg_default_width);
else
return instance_val;
end if;
end function ovl_get_ctrl_val;
------------------------------------------------------------------------------
-- cover_item_set
-- determines if a bit in the level integer is set or not.
------------------------------------------------------------------------------
function cover_item_set (
constant level : in ovl_coverage_level;
constant item : in ovl_coverage_level
) return boolean is
begin
return ((level mod (item * 2)) >= item);
end function cover_item_set;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic
) return boolean is
begin
return is_x(s);
end function ovl_is_x;
------------------------------------------------------------------------------
-- ovl_is_x
------------------------------------------------------------------------------
function ovl_is_x (
s : in std_logic_vector
) return boolean is
begin
return is_x(s);
end function ovl_is_x;
------------------------------------------------------------------------------
-- or_reduce
------------------------------------------------------------------------------
function or_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result or v(i);
end if;
exit when result = '1';
end loop;
return result;
end function or_reduce;
------------------------------------------------------------------------------
-- and_reduce
------------------------------------------------------------------------------
function and_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result and v(i);
end if;
exit when result = '0';
end loop;
return result;
end function and_reduce;
------------------------------------------------------------------------------
-- xor_reduce
------------------------------------------------------------------------------
function xor_reduce (
v : in std_logic_vector
) return std_logic is
variable result : std_logic;
begin
for i in v'range loop
if i = v'left then
result := v(i);
else
result := result xor v(i);
end if;
end loop;
return result;
end function xor_reduce;
------------------------------------------------------------------------------
-- "sll"
------------------------------------------------------------------------------
function "sll" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(l) sll r);
end function "sll";
------------------------------------------------------------------------------
-- "srl"
------------------------------------------------------------------------------
function "srl" (
l : in std_logic_vector;
r : in integer
) return std_logic_vector is
begin
return to_stdlogicvector(to_bitvector(l) srl r);
end function "srl";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- private functions used by "<" and ">" functions --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned_num_bits
------------------------------------------------------------------------------
function unsigned_num_bits (arg: natural) return natural is
variable nbits: natural;
variable n: natural;
begin
n := arg;
nbits := 1;
while n > 1 loop
nbits := nbits+1;
n := n / 2;
end loop;
return nbits;
end unsigned_num_bits;
------------------------------------------------------------------------------
-- to_unsigned
------------------------------------------------------------------------------
function to_unsigned (arg, size: natural) return std_logic_vector is
variable result: std_logic_vector(size-1 downto 0);
variable i_val: natural := arg;
begin
for i in 0 to result'left loop
if (i_val mod 2) = 0 then
result(i) := '0';
else result(i) := '1';
end if;
i_val := i_val/2;
end loop;
return result;
end to_unsigned;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- unsigned comparison functions --
-- Note: the width of l must be > 0. --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- ">"
------------------------------------------------------------------------------
function ">" (
l : in std_logic_vector;
r : in natural
) return boolean is
begin
if is_x(l) then return false; end if;
if unsigned_num_bits(r) > l'length then return false; end if;
return not (l <= to_unsigned(r, l'length));
end function ">";
------------------------------------------------------------------------------
-- "<"
------------------------------------------------------------------------------
function "<" (
l : in std_logic_vector;
r : in natural
) return boolean is
begin
if is_x(l) then return false; end if;
if unsigned_num_bits(r) > l'length then return 0 < r; end if;
return (l < to_unsigned(r, l'length));
end function "<";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end package body std_ovl_procs;
|
library verilog;
use verilog.vl_types.all;
entity HAZARD is
port(
clk : in vl_logic;
rst : in vl_logic;
decoding_op_src1: in vl_logic_vector(2 downto 0);
decoding_op_src2: in vl_logic_vector(2 downto 0);
decoding_op_dest: in vl_logic_vector(2 downto 0);
ex_op_dest : in vl_logic_vector(2 downto 0);
mem_op_dest : in vl_logic_vector(2 downto 0);
wb_op_dest : in vl_logic_vector(2 downto 0);
pipeline_stall_n: out vl_logic
);
end HAZARD;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: arith_addw_tb
--
-- Description:
-- ------------
-- Testbench for arith_addw.
--
-- License:
-- ============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.strings.all;
use PoC.physical.all;
use PoC.arith.all;
-- simulation only packages
use PoC.sim_global.all;
use PoC.sim_types.all;
use PoC.simulation.all;
entity arith_addw_tb is
end entity;
architecture tb of arith_addw_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
-- component generics
constant N : positive := 9;
constant K : positive := 2;
subtype tArch_test is tArch;
subtype tSkip_test is tSkipping;
-- component ports
subtype word is std_logic_vector(N-1 downto 0);
type word_vector is array(tArch_test, tSkip_test, boolean) of word;
type carry_vector is array(tArch_test, tSkip_test, boolean) of std_logic;
signal Clock : STD_LOGIC;
signal a, b : word;
signal cin : std_logic;
signal s : word_vector;
signal cout : carry_vector;
begin
-- initialize global simulation status
simInitialize;
-- generate global testbench clock
simGenerateClock(Clock, CLOCK_FREQ);
-- DUTs
genArchs: for i in tArch_test generate
genSkips: for j in tSkip_test generate
genIncl: for p in false to true generate
constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup: " &
"ARCH=" & str_lalign(TARCH'image(i), 5) &
"SKIPPING=" & str_lalign(TSKIPPING'image(j), 8) &
"P_INCLUSIVE=" & str_lalign(BOOLEAN'image(p), 7));
begin
DUT : entity PoC.arith_addw
generic map (
N => N,
K => K,
ARCH => i,
SKIPPING => j,
P_INCLUSIVE => p
)
port map (
a => a,
b => b,
cin => cin,
s => s(i, j, p),
cout => cout(i, j, p)
);
end generate genIncl;
end generate;
end generate;
-- Stimuli
procChecker : process
-- from Simulation
constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Combined Generator and Checker"); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name);
begin
for i in natural range 0 to 2**N-1 loop
a <= std_logic_vector(to_unsigned(i, N));
for j in natural range 0 to 2**N-1 loop
b <= std_logic_vector(to_unsigned(j, N));
cin <= '0';
wait until rising_edge(Clock);
for arch in tArch_test loop
for skip in tSkip_test loop
for incl in boolean loop
simAssertion((i+j) mod 2**(N+1) = to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl))),
"Output Error["&tArch'image(arch)&','&tSkipping'image(skip)&','&boolean'image(incl)&"]: "&
integer'image(i)&'+'&integer'image(j)&" != "&
integer'image(to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl)))));
end loop;
end loop;
end loop;
cin <= '1';
wait until falling_edge(Clock);
for arch in tArch_test loop
for skip in tSkip_test loop
for incl in boolean loop
simAssertion((i+j+1) mod 2**(N+1) = to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl))),
"Output Error["&tArch'image(arch)&','&tSkipping'image(skip)&','&boolean'image(incl)&"]: "&
integer'image(i)&'+'&integer'image(j)&"+1 != "&
integer'image(to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl)))));
end loop;
end loop;
end loop;
end loop; -- j
end loop; -- i
-- This process is finished
simDeactivateProcess(simProcessID);
-- Report overall result
simFinalize;
wait; -- forever
end process;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Thomas B. Preusser
--
-- Testbench: arith_addw_tb
--
-- Description:
-- ------------
-- Testbench for arith_addw.
--
-- License:
-- ============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library PoC;
use PoC.strings.all;
use PoC.physical.all;
use PoC.arith.all;
-- simulation only packages
use PoC.sim_global.all;
use PoC.sim_types.all;
use PoC.simulation.all;
entity arith_addw_tb is
end entity;
architecture tb of arith_addw_tb is
constant CLOCK_FREQ : FREQ := 100 MHz;
-- component generics
constant N : positive := 9;
constant K : positive := 2;
subtype tArch_test is tArch;
subtype tSkip_test is tSkipping;
-- component ports
subtype word is std_logic_vector(N-1 downto 0);
type word_vector is array(tArch_test, tSkip_test, boolean) of word;
type carry_vector is array(tArch_test, tSkip_test, boolean) of std_logic;
signal Clock : STD_LOGIC;
signal a, b : word;
signal cin : std_logic;
signal s : word_vector;
signal cout : carry_vector;
begin
-- initialize global simulation status
simInitialize;
-- generate global testbench clock
simGenerateClock(Clock, CLOCK_FREQ);
-- DUTs
genArchs: for i in tArch_test generate
genSkips: for j in tSkip_test generate
genIncl: for p in false to true generate
constant simTestID : T_SIM_TEST_ID := simCreateTest("Test setup: " &
"ARCH=" & str_lalign(TARCH'image(i), 5) &
"SKIPPING=" & str_lalign(TSKIPPING'image(j), 8) &
"P_INCLUSIVE=" & str_lalign(BOOLEAN'image(p), 7));
begin
DUT : entity PoC.arith_addw
generic map (
N => N,
K => K,
ARCH => i,
SKIPPING => j,
P_INCLUSIVE => p
)
port map (
a => a,
b => b,
cin => cin,
s => s(i, j, p),
cout => cout(i, j, p)
);
end generate genIncl;
end generate;
end generate;
-- Stimuli
procChecker : process
-- from Simulation
constant simProcessID : T_SIM_PROCESS_ID := simRegisterProcess("Combined Generator and Checker"); --, "aaa/bbb/ccc"); --globalSimulationStatus'instance_name);
begin
for i in natural range 0 to 2**N-1 loop
a <= std_logic_vector(to_unsigned(i, N));
for j in natural range 0 to 2**N-1 loop
b <= std_logic_vector(to_unsigned(j, N));
cin <= '0';
wait until rising_edge(Clock);
for arch in tArch_test loop
for skip in tSkip_test loop
for incl in boolean loop
simAssertion((i+j) mod 2**(N+1) = to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl))),
"Output Error["&tArch'image(arch)&','&tSkipping'image(skip)&','&boolean'image(incl)&"]: "&
integer'image(i)&'+'&integer'image(j)&" != "&
integer'image(to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl)))));
end loop;
end loop;
end loop;
cin <= '1';
wait until falling_edge(Clock);
for arch in tArch_test loop
for skip in tSkip_test loop
for incl in boolean loop
simAssertion((i+j+1) mod 2**(N+1) = to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl))),
"Output Error["&tArch'image(arch)&','&tSkipping'image(skip)&','&boolean'image(incl)&"]: "&
integer'image(i)&'+'&integer'image(j)&"+1 != "&
integer'image(to_integer(unsigned(cout(arch, skip, incl) & s(arch, skip, incl)))));
end loop;
end loop;
end loop;
end loop; -- j
end loop; -- i
-- This process is finished
simDeactivateProcess(simProcessID);
-- Report overall result
simFinalize;
wait; -- forever
end process;
end architecture;
|
------------------------------------------------------------------------------
-- Title : Wishbone FMC130m_4ch Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-19-08
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top Module for the FMC130m_4ch ADC board interface.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-19-08 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone Stream Interface
--use work.wb_stream_pkg.all;
use work.wb_stream_generic_pkg.all;
-- Register interface
use work.wb_fmc_130m_4ch_csr_wbgen2_pkg.all;
-- FMC ADC package
use work.fmc_adc_pkg.all;
-- Reset Synch
use work.dbe_common_pkg.all;
-- General common cores
use work.gencores_pkg.all;
-- For Xilinx primitives
library unisim;
use unisim.vcomponents.all;
--package wb_stream_64_pkg is new wb_stream_generic_pkg
-- generic map (type => std_logic_vector(63 downto 0));
entity wb_fmc130m_4ch is
generic
(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device : string := "VIRTEX6";
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_adc_clk_period_values : t_clk_values_array := default_adc_clk_period_values;
g_use_clk_chains : t_clk_use_chain := default_clk_use_chain;
g_with_bufio_clk_chains : t_clk_use_bufio_chain := default_clk_use_bufio_chain;
g_with_bufr_clk_chains : t_clk_use_bufr_chain := default_clk_use_bufr_chain;
g_use_data_chains : t_data_use_chain := default_data_use_chain;
g_map_clk_data_chains : t_map_clk_data_chain := default_map_clk_data_chain;
g_ref_clk : t_ref_adc_clk := default_ref_adc_clk;
g_packet_size : natural := 32;
g_sim : integer := 0
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
-- ADC LTC2208 interface
fmc_adc_pga_o : out std_logic;
fmc_adc_shdn_o : out std_logic;
fmc_adc_dith_o : out std_logic;
fmc_adc_rand_o : out std_logic;
-- ADC0 LTC2208
fmc_adc0_clk_i : in std_logic := '0';
fmc_adc0_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0) := (others => '0');
fmc_adc0_of_i : in std_logic := '0'; -- Unused
-- ADC1 LTC2208
fmc_adc1_clk_i : in std_logic := '0';
fmc_adc1_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0) := (others => '0');
fmc_adc1_of_i : in std_logic := '0'; -- Unused
-- ADC2 LTC2208
fmc_adc2_clk_i : in std_logic := '0';
fmc_adc2_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0) := (others => '0');
fmc_adc2_of_i : in std_logic := '0'; -- Unused
-- ADC3 LTC2208
fmc_adc3_clk_i : in std_logic;
fmc_adc3_data_i : in std_logic_vector(c_num_adc_bits-1 downto 0) := (others => '0');
fmc_adc3_of_i : in std_logic := '0'; -- Unused
-- FMC General Status
fmc_prsnt_i : in std_logic := '0';
fmc_pg_m2c_i : in std_logic := '0';
--fmc_clk_dir_i : in std_logic;, -- not supported on Kintex7 KC705 board
-- Trigger
fmc_trig_dir_o : out std_logic;
fmc_trig_term_o : out std_logic;
fmc_trig_val_p_b : inout std_logic;
fmc_trig_val_n_b : inout std_logic;
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic := '0';
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic := '0';
fmc_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-- EEPROM
eeprom_scl_pad_b : inout std_logic;
eeprom_sda_pad_b : inout std_logic;
-- Temperature monitor
-- LM75AIMM
lm75_scl_pad_b : inout std_logic;
lm75_sda_pad_b : inout std_logic;
fmc_lm75_temp_alarm_i : in std_logic := '0';
-- FMC LEDs
fmc_led1_o : out std_logic;
fmc_led2_o : out std_logic;
fmc_led3_o : out std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_rst_n_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
-----------------------------
-- General ADC output signals and status
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o : out std_logic;
trig_hw_i : in std_logic := '0';
-- General board status
fmc_mmcm_lock_o : out std_logic;
fmc_pll_status_o : out std_logic;
-----------------------------
-- Wishbone Streaming Interface Source
-----------------------------
wbs_adr_o : out std_logic_vector(c_num_adc_channels*c_wbs_adr4_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_num_adc_channels*c_wbs_dat16_width-1 downto 0);
wbs_cyc_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
wbs_stb_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
wbs_we_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
wbs_sel_o : out std_logic_vector(c_num_adc_channels*c_wbs_sel16_width-1 downto 0);
wbs_ack_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_stall_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_err_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_rty_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
adc_dly_debug_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
);
end wb_fmc130m_4ch;
architecture rtl of wb_fmc130m_4ch is
-- Slightly different behaviour than the one located at wishbone_pkg.vhd.
-- The original f_ceil_log2 returns 0 for x <= 1. We cannot allow this,
-- as we must have at least one bit size, for x > 0
function f_ceil_log2(x : natural) return natural is
begin
if x <= 2
then return 1;
else return f_ceil_log2((x+1)/2) +1;
end if;
end f_ceil_log2;
-----------------------------
-- General Contants
-----------------------------
-- Number packet size counter bits
constant c_packet_num_bits : natural := f_packet_num_bits(g_packet_size);
-- Numbert of bits in Wishbone register interface. Plus 2 to account for BYTE addressing
constant c_periph_addr_size : natural := 4+2;
constant c_first_used_clk : natural := f_first_used_clk(g_use_clk_chains);
constant c_ref_clk : natural := g_ref_clk;
constant c_with_clk_single_ended : boolean := true;
constant c_with_data_single_ended : boolean := true;
constant c_with_data_sdr : boolean := true;
constant c_with_fn_dly_select : boolean := true;
constant c_with_idelay_var_loadable : boolean := true;
constant c_with_idelay_variable : boolean := false;
-- 130 MHz parameters
constant c_mmcm_param : t_mmcm_param :=
(1, 8.000, g_adc_clk_period_values(c_ref_clk), 8.000, 4);
-----------------------------
-- Crossbar component constants
-----------------------------
-- Internal crossbar layout
-- 0 -> FMC130_4CH Register Wishbone Interface
-- 1 -> VCXO Si571 I2C Bus.
-- 2 -> PLL and Clock Distribution AD9510 SPI
-- 3 -> EEPROM I2C Bus.
-- 4 -> LM75A I2C Bus.
-- Number of slaves
constant c_slaves : natural := 5;
-- Number of masters
constant c_masters : natural := 1; -- Top master.
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(c_xwb_fmc130m_4ch_regs_sdb, x"00000000"), -- Register interface
1 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00000100"), -- VCXO Si571 I2C
2 => f_sdb_embed_device(c_xwb_spi_sdb, x"00000200"), -- AD9510 SPI
3 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00000300"), -- EEPROM I2C
4 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00000400") -- LM75A I2C
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well.
constant c_sdb_address : t_wishbone_address := x"00000800";
-----------------------------
-- Clock and reset signals
-----------------------------
signal sys_rst_n : std_logic;
signal sys_rst_sync_n : std_logic;
--signal adc_clk_chain_rst : std_logic;
-----------------------------
-- Wishbone Register Interface signals
-----------------------------
-- FMC130m_4ch reg structure
signal regs_out : t_wb_fmc_130m_4ch_csr_out_registers;
signal regs_in : t_wb_fmc_130m_4ch_csr_in_registers;
-----------------------------
-- ADC Interface signals
-----------------------------
--signal fs_clk : std_logic;
signal fs_rst_n : std_logic;
signal fs_rst_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_rst : std_logic; -- ADC reset from wishbone
signal mmcm_adc_locked : std_logic;
-- ADC clock + data single ended inputs
signal adc_in : t_adc_sdr_in_array(c_num_adc_channels-1 downto 0);
signal adc_in_dummy : t_adc_in_array(c_num_adc_channels-1 downto 0) :=
(0 => ('0', '0', (others => '0')),
1 => ('0', '0', (others => '0')),
2 => ('0', '0', (others => '0')),
3 => ('0', '0', (others => '0'))
);
signal adc_clk0 : std_logic;
signal adc_clk1 : std_logic;
signal adc_clk2 : std_logic;
signal adc_clk3 : std_logic;
signal adc_data_ch0 : std_logic_vector(f_num_adc_pins(c_with_data_sdr)-1 downto 0);
signal adc_data_ch1 : std_logic_vector(f_num_adc_pins(c_with_data_sdr)-1 downto 0);
signal adc_data_ch2 : std_logic_vector(f_num_adc_pins(c_with_data_sdr)-1 downto 0);
signal adc_data_ch3 : std_logic_vector(f_num_adc_pins(c_with_data_sdr)-1 downto 0);
-- ADC fine delay signals.
signal adc_fn_dly_in : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal adc_idelay_rdy : std_logic;
signal adc_idelay_update_or : std_logic;
--signal adc_fn_dly_in_int : t_adc_fn_dly_int_array(c_num_adc_channels-1 downto 0);
signal adc_fn_dly_wb_ctl_out : t_adc_fn_dly_wb_ctl_array(c_num_adc_channels-1 downto 0);
signal adc_fn_dly_out : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
-- ADC coarse delay signals.
signal adc_cs_dly_in : t_adc_cs_dly_array(c_num_adc_channels-1 downto 0);
signal adc_cs_dly_in_int : t_adc_cs_dly_array(c_num_adc_channels-1 downto 0);
-- ADC output signals.
signal adc_out : t_adc_out_array(c_num_adc_channels-1 downto 0);
-- ADC Clock/Data variable delay interface internal structure
signal adc_dly_pulse_clk_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_pulse_data_int : std_logic_vector(c_num_adc_channels-1 downto 0);
-- Signals for adc internal use
--signal adc_clk_int : std_logic_vector(c_num_adc_bits-1 downto 0);
signal fs_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fs_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_data : std_logic_vector(c_num_adc_bits*c_num_adc_channels-1 downto 0);
-- ADC Reset signals
signal adc_clk_div_rst_int : std_logic;
signal adc_clk_div_rst_int_p : std_logic;
signal fmc_reset_adcs_int : std_logic;
-----------------------------
-- Test data signals and constants
-----------------------------
-- Counter width. It willl count up to 2^32 clock cycles
constant c_counter_width : natural := 16;
-- 100MHz period or 1 second
constant c_counter_full : natural := 1000000;
-- Offset between adjacent test data channels
constant c_offset_test_data : natural := 10;
-- Counter signal
type t_wbs_test_data_array is array(natural range<>) of unsigned(c_counter_width-1 downto 0);
signal wbs_test_data : t_wbs_test_data_array(c_num_adc_channels-1 downto 0);
-----------------------------
-- Wishbone Streaming control signals
-----------------------------
type t_wbs_dat16_array is array(natural range<>) of std_logic_vector(c_wbs_dat16_width-1 downto 0);
type t_wbs_valid16_array is array(natural range<>) of std_logic;
signal wbs_dat : t_wbs_dat16_array(c_num_adc_channels-1 downto 0);
signal wbs_valid : t_wbs_valid16_array(c_num_adc_channels-1 downto 0);
signal wbs_adr : std_logic_vector(c_wbs_adr4_width-1 downto 0);
--signal wbs_dat : std_logic_vector(c_wbs_dat16_width-1 downto 0);
--signal wbs_dvalid : std_logic;
signal wbs_sof : std_logic;
signal wbs_eof : std_logic;
signal wbs_error : std_logic;
signal wbs_sel : std_logic_vector(c_wbs_sel16_width-1 downto 0);
-- Wishbone Streaming interface structure
signal wbs_stream_out : t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
signal wbs_stream_in : t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
-----------------------------
-- Wishbone slave adapter signals/structures
-----------------------------
signal wb_slv_adp_out : t_wishbone_master_out;
signal wb_slv_adp_in : t_wishbone_master_in;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
-----------------------------
-- Wishbone crossbar signals
-----------------------------
--signal wb_out : t_wishbone_master_in_array(0 to c_num_int_slaves-1);
--signal wb_in : t_wishbone_master_out_array(0 to c_num_int_slaves-1);
-- Crossbar master/slave arrays
signal cbar_slave_in : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_out : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_in : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_slaves-1 downto 0);
-----------------------------
-- VCXO Si571 I2C Signals
-----------------------------
signal si571_i2c_scl_in : std_logic;
signal si571_i2c_scl_out : std_logic;
signal si571_i2c_scl_oe_n : std_logic;
signal si571_i2c_sda_in : std_logic;
signal si571_i2c_sda_out : std_logic;
signal si571_i2c_sda_oe_n : std_logic;
-----------------------------
-- AD9510 SPI signals
-----------------------------
signal ad9510_spi_din : std_logic;
signal ad9510_spi_dout : std_logic;
signal ad9510_spi_ss_int : std_logic_vector(7 downto 0);
signal ad9510_spi_clk : std_logic;
signal ad9510_spi_miosio_oe_n : std_logic;
-----------------------------
-- EEPROM I2C Signals
-----------------------------
signal eeprom_i2c_scl_in : std_logic;
signal eeprom_i2c_scl_out : std_logic;
signal eeprom_i2c_scl_oe_n : std_logic;
signal eeprom_i2c_sda_in : std_logic;
signal eeprom_i2c_sda_out : std_logic;
signal eeprom_i2c_sda_oe_n : std_logic;
-----------------------------
-- LM75A I2C Signals
-----------------------------
signal lm75a_i2c_scl_in : std_logic;
signal lm75a_i2c_scl_out : std_logic;
signal lm75a_i2c_scl_oe_n : std_logic;
signal lm75a_i2c_sda_in : std_logic;
signal lm75a_i2c_sda_out : std_logic;
signal lm75a_i2c_sda_oe_n : std_logic;
-----------------------------
-- Trigger signals
-----------------------------
--signal m2c_trig : std_logic;
--signal m2c_trig_sync : std_logic;
--signal c2m_trig : std_logic;
signal fmc_trig_val_in : std_logic;
signal fmc_trig_val_in_sync : std_logic;
signal fmc_trig_dir_int : std_logic;
signal fmc_trig_term_int : std_logic;
signal fmc_trig_val_int_reg : std_logic;
signal fmc_trig_val_int : std_logic;
-----------------------------
-- Led signals
-----------------------------
signal led1_extd_p : std_logic;
signal led2_extd_p : std_logic;
signal led3_extd_p : std_logic;
signal fmc_led1_int : std_logic;
signal fmc_led2_int : std_logic;
signal fmc_led3_int : std_logic;
-----------------------------
-- Dummy signals
-----------------------------
signal dummy_bit_low : std_logic := '0';
signal dummy_adc_vector_low : std_logic_vector(f_num_adc_pins(c_with_data_sdr)-1 downto 0) :=
(others => '0');
-----------------------------
-- Components
-----------------------------
component wb_fmc_130m_4ch_csr
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
regs_i : in t_wb_fmc_130m_4ch_csr_in_registers;
regs_o : out t_wb_fmc_130m_4ch_csr_out_registers
);
end component;
begin
-- Reset signals and sychronization with positive edge of
-- respective clock
--sys_rst_n <= sys_rst_n_i and mmcm_adc_locked;
sys_rst_n <= sys_rst_n_i;
fs_rst_n <= sys_rst_n and mmcm_adc_locked;
-- Reset synchronization with SYS clock domain
-- Align the reset deassertion to the next clock edge
cmp_reset_sys_synch : reset_synch
port map(
clk_i => sys_clk_i,
arst_n_i => sys_rst_n,
rst_n_o => sys_rst_sync_n
);
--sys_rst_sync_n <= sys_rst_n;
-- Reset synchronization with FS clock domain (just clock 1
-- is used for now). Align the reset deassertion to the next
-- clock edge
gen_adc_reset_synch : for i in 0 to c_num_adc_channels-1 generate
gen_adc_reset_synch_ch : if g_use_data_chains(i) = '1' generate
cmp_reset_fs_synch : reset_synch
port map(
clk_i => fs_clk(i),
arst_n_i => fs_rst_n,
--rst_n_o => fs_rst_sync_n
rst_n_o => fs_rst_sync_n(i)
);
-- Output adc sync'ed reset to downstream FPGA logic
adc_rst_n_o(i) <= fs_rst_sync_n(i);
--fs_rst_sync_n(i) <= fs_rst_n;
end generate;
end generate;
-----------------------------
-- General status board pins
-----------------------------
-- PLL status available through a regular core pin
fmc_pll_status_o <= fmc_pll_status_i;
-----------------------------
-- FMC130M_4CH Address decoder for SPI/I2C Wishbone interfaces modules
-----------------------------
-- We need 5 outputs, as in the same wishbone addressing range, 5
-- other wishbone peripherals must be driven:
--
-- 0 -> FMC130_4CH Register Wishbone Interface
-- 1 -> VCXO Si571 I2C Bus.
-- 2 -> PLL and Clock Distribution AD9510 SPI
-- 3 -> EEPROM I2C Bus.
-- 4 -> LM75A I2C Bus.
-- The Internal Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_sync_n,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_in,
slave_o => cbar_slave_out,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_in,
master_o => cbar_master_out
);
-- External master connection
cbar_slave_in(0).adr <= wb_adr_i;
cbar_slave_in(0).dat <= wb_dat_i;
cbar_slave_in(0).sel <= wb_sel_i;
cbar_slave_in(0).we <= wb_we_i;
cbar_slave_in(0).cyc <= wb_cyc_i;
cbar_slave_in(0).stb <= wb_stb_i;
wb_dat_o <= cbar_slave_out(0).dat;
wb_ack_o <= cbar_slave_out(0).ack;
wb_err_o <= cbar_slave_out(0).err;
wb_rty_o <= cbar_slave_out(0).rty;
wb_stall_o <= cbar_slave_out(0).stall;
-----------------------------
-- Slave adapter for Wishbone Register Interface
-----------------------------
cmp_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity
)
port map (
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_sync_n,
master_i => wb_slv_adp_in,
master_o => wb_slv_adp_out,
sl_adr_i => resized_addr,
sl_dat_i => cbar_master_out(0).dat,
sl_sel_i => cbar_master_out(0).sel,
sl_cyc_i => cbar_master_out(0).cyc,
sl_stb_i => cbar_master_out(0).stb,
sl_we_i => cbar_master_out(0).we,
sl_dat_o => cbar_master_in(0).dat,
sl_ack_o => cbar_master_in(0).ack,
sl_rty_o => cbar_master_in(0).rty,
sl_err_o => cbar_master_in(0).err,
sl_int_o => cbar_master_in(0).int,
sl_stall_o => cbar_master_in(0).stall
);
-- By doing this zeroing we avoid the issue related to BYTE -> WORD conversion
-- slave addressing (possibly performed by the slave adapter component)
-- in which a bit in the MSB of the peripheral addressing part (31 - 4 in our case)
-- is shifted to the internal register adressing part (3 - 0 in our case).
-- Therefore, possibly changing the these bits!
resized_addr(c_periph_addr_size-1 downto 0)
<= cbar_master_out(0).adr(c_periph_addr_size-1 downto 0);
resized_addr(c_wishbone_address_width-1 downto c_periph_addr_size)
<= (others => '0');
-----------------------------
-- FMC516 Register Wishbone Interface. Word addressed!
-----------------------------
--FMC516 register interface is the slave number 0, word addressed
cmp_wb_fmc_130m_4ch_csr : wb_fmc_130m_4ch_csr
port map(
rst_n_i => sys_rst_sync_n,
clk_sys_i => sys_clk_i,
wb_adr_i => wb_slv_adp_out.adr(3 downto 0),
wb_dat_i => wb_slv_adp_out.dat,
wb_dat_o => wb_slv_adp_in.dat,
wb_cyc_i => wb_slv_adp_out.cyc,
wb_sel_i => wb_slv_adp_out.sel,
wb_stb_i => wb_slv_adp_out.stb,
wb_we_i => wb_slv_adp_out.we,
wb_ack_o => wb_slv_adp_in.ack,
wb_stall_o => wb_slv_adp_in.stall,
fs_clk_i => fs_clk(c_ref_clk),
regs_i => regs_in,
regs_o => regs_out
);
-- Unused wishbone signals
wb_slv_adp_in.int <= '0';
wb_slv_adp_in.err <= '0';
wb_slv_adp_in.rty <= '0';
-- Wishbone Interface Register input assignments. There are others registers
-- not assigned here.
regs_in.fmc_status_prsnt_i <= fmc_prsnt_i;
regs_in.fmc_status_pg_m2c_i <= fmc_pg_m2c_i;
regs_in.fmc_status_clk_dir_i <= '0';
regs_in.fmc_status_firmware_id_i <= '0' & x"1332A11"; -- Should be the current date
regs_in.trigger_reserved_i <= (others => '0');
regs_in.adc_reserved_i <= (others => '0');
regs_in.clk_distrib_pll_status_i <= fmc_pll_status_i;
regs_in.clk_distrib_reserved_i <= (others => '0');
regs_in.monitor_temp_alarm_i <= fmc_lm75_temp_alarm_i;
regs_in.monitor_reserved_i <= (others => '0');
regs_in.fpga_ctrl_fmc_idelay0_rdy_i <= adc_idelay_rdy;
regs_in.fpga_ctrl_fmc_idelay1_rdy_i <= adc_idelay_rdy;
regs_in.fpga_ctrl_fmc_idelay2_rdy_i <= adc_idelay_rdy;
regs_in.fpga_ctrl_fmc_idelay3_rdy_i <= adc_idelay_rdy;
regs_in.fpga_ctrl_reserved1_i <= (others => '0');
regs_in.fpga_ctrl_reserved2_i <= (others => '0');
regs_in.idelay0_cal_val_i <= adc_fn_dly_out(0).data_chain.idelay.val;
regs_in.idelay0_cal_reserved_i <= (others => '0');
regs_in.idelay1_cal_val_i <= adc_fn_dly_out(1).data_chain.idelay.val;
regs_in.idelay1_cal_reserved_i <= (others => '0');
regs_in.idelay2_cal_val_i <= adc_fn_dly_out(2).data_chain.idelay.val;
regs_in.idelay2_cal_reserved_i <= (others => '0');
regs_in.idelay3_cal_val_i <= adc_fn_dly_out(3).data_chain.idelay.val;
regs_in.idelay3_cal_reserved_i <= (others => '0');
-- ADC RAW data channel 0
regs_in.data0_val_i(regs_in.data0_val_i'left downto c_num_adc_bits)
<= (others => '0');
regs_in.data0_val_i(c_num_adc_bits-1 downto 0)
<= adc_out(0).adc_data;
-- ADC RAW data channel 1
regs_in.data1_val_i(regs_in.data1_val_i'left downto c_num_adc_bits)
<= (others => '0');
regs_in.data1_val_i(c_num_adc_bits-1 downto 0)
<= adc_out(1).adc_data;
-- ADC RAW data channel 2
regs_in.data2_val_i(regs_in.data2_val_i'left downto c_num_adc_bits)
<= (others => '0');
regs_in.data2_val_i(c_num_adc_bits-1 downto 0)
<= adc_out(2).adc_data;
-- ADC RAW data channel 3
regs_in.data3_val_i(regs_in.data3_val_i'left downto c_num_adc_bits)
<= (others => '0');
regs_in.data3_val_i(c_num_adc_bits-1 downto 0)
<= adc_out(3).adc_data;
regs_in.dcm_adc_done_i <= '0'; -- Unused
regs_in.dcm_adc_status0_i <= '0'; -- Unused
regs_in.dcm_reserved_i <= (others => '0');
--regs_in.ch0_sta_val_i <= adc_out(0).adc_data;
--regs_in.ch0_sta_reserved_i <= (others => '0');
--regs_in.ch0_fn_dly_reserved_clk_chain_dly_i <= (others => '0');
--regs_in.ch0_fn_dly_reserved_data_chain_dly_i <= (others => '0');
--regs_in.ch1_sta_val_i <= adc_out(1).adc_data;
--regs_in.ch1_sta_reserved_i <= (others => '0');
--regs_in.ch1_fn_dly_reserved_clk_chain_dly_i <= (others => '0');
--regs_in.ch1_fn_dly_reserved_data_chain_dly_i <= (others => '0');
--regs_in.ch2_sta_val_i <= adc_out(2).adc_data;
--regs_in.ch2_sta_reserved_i <= (others => '0');
--regs_in.ch2_fn_dly_reserved_clk_chain_dly_i <= (others => '0');
--regs_in.ch2_fn_dly_reserved_data_chain_dly_i <= (others => '0');
--regs_in.ch3_sta_val_i <= adc_out(3).adc_data;
--regs_in.ch3_sta_reserved_i <= (others => '0');
--regs_in.ch3_fn_dly_reserved_clk_chain_dly_i <= (others => '0');
--regs_in.ch3_fn_dly_reserved_data_chain_dly_i <= (others => '0');
---- ADC delay registers out
--regs_in.ch0_fn_dly_clk_chain_dly_i <= adc_fn_dly_out(0).adc_clk_dly_val;
--regs_in.ch0_fn_dly_data_chain_dly_i <= adc_fn_dly_out(0).adc_data_dly_val;
--regs_in.ch1_fn_dly_clk_chain_dly_i <= adc_fn_dly_out(1).adc_clk_dly_val;
--regs_in.ch1_fn_dly_data_chain_dly_i <= adc_fn_dly_out(1).adc_data_dly_val;
--regs_in.ch2_fn_dly_clk_chain_dly_i <= adc_fn_dly_out(2).adc_clk_dly_val;
--regs_in.ch2_fn_dly_data_chain_dly_i <= adc_fn_dly_out(2).adc_data_dly_val;
--regs_in.ch3_fn_dly_clk_chain_dly_i <= adc_fn_dly_out(3).adc_clk_dly_val;
--regs_in.ch3_fn_dly_data_chain_dly_i <= adc_fn_dly_out(3).adc_data_dly_val;
--
-- ADC delay registers in
adc_fn_dly_wb_ctl_out(0).clk_chain.loadable.load <= regs_out.idelay0_cal_val_load_o;
adc_fn_dly_wb_ctl_out(0).data_chain.loadable.load <= regs_out.idelay0_cal_val_load_o;
adc_fn_dly_wb_ctl_out(0).clk_chain.loadable.val <= regs_out.idelay0_cal_val_o;
adc_fn_dly_wb_ctl_out(0).data_chain.loadable.val <= regs_out.idelay0_cal_val_o;
adc_fn_dly_wb_ctl_out(0).clk_chain.loadable.pulse <= adc_idelay_update_or;
adc_fn_dly_wb_ctl_out(0).data_chain.loadable.pulse <= adc_idelay_update_or;
adc_fn_dly_wb_ctl_out(0).clk_chain.sel.which <= regs_out.idelay0_cal_line_o(c_num_adc_bits);
adc_fn_dly_wb_ctl_out(0).data_chain.sel.which <= regs_out.idelay0_cal_line_o(c_num_adc_bits-1 downto 0);
--adc_fn_dly_wb_ctl_out(0).clk_chain.var.inc <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(0).data_chain.var.inc <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(0).clk_chain.var.dec <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(0).data_chain.var.dec <= '0'; -- Unused
adc_fn_dly_wb_ctl_out(1).clk_chain.loadable.load <= regs_out.idelay1_cal_val_load_o;
adc_fn_dly_wb_ctl_out(1).data_chain.loadable.load <= regs_out.idelay1_cal_val_load_o;
adc_fn_dly_wb_ctl_out(1).clk_chain.loadable.val <= regs_out.idelay1_cal_val_o;
adc_fn_dly_wb_ctl_out(1).data_chain.loadable.val <= regs_out.idelay1_cal_val_o;
adc_fn_dly_wb_ctl_out(1).clk_chain.loadable.pulse <= adc_idelay_update_or;
adc_fn_dly_wb_ctl_out(1).data_chain.loadable.pulse <= adc_idelay_update_or;
adc_fn_dly_wb_ctl_out(1).clk_chain.sel.which <= regs_out.idelay1_cal_line_o(c_num_adc_bits);
adc_fn_dly_wb_ctl_out(1).data_chain.sel.which <= regs_out.idelay1_cal_line_o(c_num_adc_bits-1 downto 0);
--adc_fn_dly_wb_ctl_out(1).clk_chain.var.inc <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(1).data_chain.var.inc <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(1).clk_chain.var.dec <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(1).data_chain.var.dec <= '0'; -- Unused
adc_fn_dly_wb_ctl_out(2).clk_chain.loadable.load <= regs_out.idelay2_cal_val_load_o;
adc_fn_dly_wb_ctl_out(2).data_chain.loadable.load <= regs_out.idelay2_cal_val_load_o;
adc_fn_dly_wb_ctl_out(2).clk_chain.loadable.val <= regs_out.idelay2_cal_val_o;
adc_fn_dly_wb_ctl_out(2).data_chain.loadable.val <= regs_out.idelay2_cal_val_o;
adc_fn_dly_wb_ctl_out(2).clk_chain.loadable.pulse <= adc_idelay_update_or;
adc_fn_dly_wb_ctl_out(2).data_chain.loadable.pulse <= adc_idelay_update_or;
adc_fn_dly_wb_ctl_out(2).clk_chain.sel.which <= regs_out.idelay2_cal_line_o(c_num_adc_bits);
adc_fn_dly_wb_ctl_out(2).data_chain.sel.which <= regs_out.idelay2_cal_line_o(c_num_adc_bits-1 downto 0);
--adc_fn_dly_wb_ctl_out(2).clk_chain.var.inc <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(2).data_chain.var.inc <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(2).clk_chain.var.dec <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(2).data_chain.var.dec <= '0'; -- Unused
adc_fn_dly_wb_ctl_out(3).clk_chain.loadable.load <= regs_out.idelay3_cal_val_load_o;
adc_fn_dly_wb_ctl_out(3).data_chain.loadable.load <= regs_out.idelay3_cal_val_load_o;
adc_fn_dly_wb_ctl_out(3).clk_chain.loadable.val <= regs_out.idelay3_cal_val_o;
adc_fn_dly_wb_ctl_out(3).data_chain.loadable.val <= regs_out.idelay3_cal_val_o;
adc_fn_dly_wb_ctl_out(3).clk_chain.loadable.pulse <= adc_idelay_update_or;
adc_fn_dly_wb_ctl_out(3).data_chain.loadable.pulse <= adc_idelay_update_or;
adc_fn_dly_wb_ctl_out(3).clk_chain.sel.which <= regs_out.idelay3_cal_line_o(c_num_adc_bits);
adc_fn_dly_wb_ctl_out(3).data_chain.sel.which <= regs_out.idelay3_cal_line_o(c_num_adc_bits-1 downto 0);
--adc_fn_dly_wb_ctl_out(3).clk_chain.var.inc <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(3).data_chain.var.inc <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(3).clk_chain.var.dec <= '0'; -- Unused
--adc_fn_dly_wb_ctl_out(3).data_chain.var.dec <= '0'; -- Unused
adc_idelay_update_or <= regs_out.idelay0_cal_update_o or
regs_out.idelay1_cal_update_o or
regs_out.idelay2_cal_update_o or
regs_out.idelay3_cal_update_o;
---- ADC delay falling edge control
--adc_cs_dly_in_int(0).adc_data_fe_d1_en <= regs_out.ch0_cs_dly_fe_dly_o(0);
--adc_cs_dly_in_int(0).adc_data_fe_d2_en <= regs_out.ch0_cs_dly_fe_dly_o(1);
--adc_cs_dly_in_int(1).adc_data_fe_d1_en <= regs_out.ch1_cs_dly_fe_dly_o(0);
--adc_cs_dly_in_int(1).adc_data_fe_d2_en <= regs_out.ch1_cs_dly_fe_dly_o(1);
--adc_cs_dly_in_int(2).adc_data_fe_d1_en <= regs_out.ch2_cs_dly_fe_dly_o(0);
--adc_cs_dly_in_int(2).adc_data_fe_d2_en <= regs_out.ch2_cs_dly_fe_dly_o(1);
--adc_cs_dly_in_int(3).adc_data_fe_d1_en <= regs_out.ch3_cs_dly_fe_dly_o(0);
--adc_cs_dly_in_int(3).adc_data_fe_d2_en <= regs_out.ch3_cs_dly_fe_dly_o(1);
--
---- ADC regular delay control
--adc_cs_dly_in_int(0).adc_data_rg_d1_en <= regs_out.ch0_cs_dly_rg_dly_o(0);
--adc_cs_dly_in_int(0).adc_data_rg_d2_en <= regs_out.ch0_cs_dly_rg_dly_o(1);
--adc_cs_dly_in_int(1).adc_data_rg_d1_en <= regs_out.ch1_cs_dly_rg_dly_o(0);
--adc_cs_dly_in_int(1).adc_data_rg_d2_en <= regs_out.ch1_cs_dly_rg_dly_o(1);
--adc_cs_dly_in_int(2).adc_data_rg_d1_en <= regs_out.ch2_cs_dly_rg_dly_o(0);
--adc_cs_dly_in_int(2).adc_data_rg_d2_en <= regs_out.ch2_cs_dly_rg_dly_o(1);
--adc_cs_dly_in_int(3).adc_data_rg_d1_en <= regs_out.ch3_cs_dly_rg_dly_o(0);
--adc_cs_dly_in_int(3).adc_data_rg_d2_en <= regs_out.ch3_cs_dly_rg_dly_o(1);
-- Wishbone Interface Register output assignments. There are others registers
-- not assigned here.
fmc_trig_dir_int <= regs_out.trigger_dir_o;
fmc_trig_term_o <= regs_out.trigger_term_o;
fmc_trig_val_int_reg <= regs_out.trigger_trig_val_o;
fmc_adc_rand_o <= regs_out.adc_rand_o;
fmc_adc_dith_o <= regs_out.adc_dith_o;
fmc_adc_shdn_o <= regs_out.adc_shdn_o;
fmc_adc_pga_o <= regs_out.adc_pga_o;
fmc_si571_oe_o <= regs_out.clk_distrib_si571_oe_o;
fmc_pll_function_o <= regs_out.clk_distrib_pll_function_o;
fmc_clk_sel_o <= regs_out.clk_distrib_clk_sel_o;
fmc_led1_int <= regs_out.monitor_led1_o;
fmc_led2_int <= regs_out.monitor_led2_o;
fmc_led3_int <= regs_out.monitor_led3_o;
adc_rst <= regs_out.fpga_ctrl_fmc_idelay_rst_o;
--regs_out.fpga_ctrl_fmc_fifo_rst_o; -- Unused
--regs_out.dcm_adc_en_o -- Unused
--regs_out.dcm_adc_phase_o -- Unused
--regs_out.dcm_adc_reset_o -- Unused
-----------------------------
-- Pins connections for ADC interface structures
-----------------------------
-- The hardcoded part here is innevitable as we have to mannualy connect
-- the external ports to the structures.
--
-- WARNING: just clock 1 is is used for now. If more clocks are used,
-- we would have to synchronise the other resets (adc_in(x).adc_rst_n)
-- to it and map them below!
-- ADC in signal mangling
adc_in(0).adc_clk <= adc_clk0;
adc_in(0).adc_data <= adc_data_ch0;
adc_in(1).adc_clk <= adc_clk1;
adc_in(1).adc_data <= adc_data_ch1;
adc_in(2).adc_clk <= adc_clk2;
adc_in(2).adc_data <= adc_data_ch2;
adc_in(3).adc_clk <= adc_clk3;
adc_in(3).adc_data <= adc_data_ch3;
gen_fs_rst_in : for i in 0 to c_num_adc_channels-1 generate
adc_in(i).adc_rst_n <= fs_rst_sync_n(i);
end generate;
-----------------------------
-- Wishbone Delay Register Interface <-> ADC interface (clock + data delays).
-----------------------------
-- Clock/Data Chain delays
-- Capture delay signals (clock + data chains) coming from the Wishbone
-- Register Interface.
gen_adc_idly_iface : for i in 0 to c_num_adc_channels-1 generate
cmp_fmc_adc_dly_iface : fmc_adc_dly_iface
generic map(
g_with_var_loadable => c_with_idelay_var_loadable,
g_with_variable => c_with_idelay_variable,
g_with_fn_dly_select => c_with_fn_dly_select
)
port map(
rst_n_i => sys_rst_sync_n,
clk_sys_i => sys_clk_i,
adc_fn_dly_wb_ctl_i => adc_fn_dly_wb_ctl_out(i),
adc_fn_dly_o => adc_fn_dly_in(i)
);
-- Debug interface
adc_dly_debug_o(i) <= adc_fn_dly_in(i);
end generate;
-----------------------------
-- ADC Interface
-----------------------------
cmp_fmc_adc_buf : fmc_adc_buf
generic map (
g_with_clk_single_ended => c_with_clk_single_ended,
g_with_data_single_ended => c_with_data_single_ended,
g_with_data_sdr => c_with_data_sdr
)
port map (
-----------------------------
-- External ports
-----------------------------
adc_clk0_p_i => dummy_bit_low,
adc_clk0_n_i => dummy_bit_low,
adc_clk1_p_i => dummy_bit_low,
adc_clk1_n_i => dummy_bit_low,
adc_clk2_p_i => dummy_bit_low,
adc_clk2_n_i => dummy_bit_low,
adc_clk3_p_i => dummy_bit_low,
adc_clk3_n_i => dummy_bit_low,
-- ADC clocks. One clock per ADC channel
adc_clk0_i => fmc_adc0_clk_i,
adc_clk1_i => fmc_adc1_clk_i,
adc_clk2_i => fmc_adc2_clk_i,
adc_clk3_i => fmc_adc3_clk_i,
adc_data_ch0_p_i => dummy_adc_vector_low,
adc_data_ch0_n_i => dummy_adc_vector_low,
adc_data_ch1_p_i => dummy_adc_vector_low,
adc_data_ch1_n_i => dummy_adc_vector_low,
adc_data_ch2_p_i => dummy_adc_vector_low,
adc_data_ch2_n_i => dummy_adc_vector_low,
adc_data_ch3_p_i => dummy_adc_vector_low,
adc_data_ch3_n_i => dummy_adc_vector_low,
-- SDR ADC data channels.
adc_data_ch0_i => fmc_adc0_data_i,
adc_data_ch1_i => fmc_adc1_data_i,
adc_data_ch2_i => fmc_adc2_data_i,
adc_data_ch3_i => fmc_adc3_data_i,
adc_clk0_o => adc_clk0,
adc_clk1_o => adc_clk1,
adc_clk2_o => adc_clk2,
adc_clk3_o => adc_clk3,
adc_data_ch0_o => adc_data_ch0,
adc_data_ch1_o => adc_data_ch1,
adc_data_ch2_o => adc_data_ch2,
adc_data_ch3_o => adc_data_ch3
);
cmp_fmc_adc_iface : fmc_adc_iface
generic map(
-- The only supported values are VIRTEX6 and 7SERIES
g_fpga_device => g_fpga_device,
g_delay_type => "VAR_LOADABLE",
--g_delay_type => "VARIABLE",
g_adc_clk_period_values => g_adc_clk_period_values,
g_use_clk_chains => g_use_clk_chains,
g_use_data_chains => g_use_data_chains,
g_map_clk_data_chains => g_map_clk_data_chains,
g_ref_clk => g_ref_clk,
g_mmcm_param => c_mmcm_param,
g_with_bufio_clk_chains => g_with_bufio_clk_chains,
g_with_bufr_clk_chains => g_with_bufr_clk_chains,
g_with_data_sdr => c_with_data_sdr,
g_with_fn_dly_select => c_with_fn_dly_select,
g_sim => g_sim
)
port map(
sys_clk_i => sys_clk_i,
-- System Reset
sys_rst_n_i => sys_rst_sync_n,
-- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-----------------------------
-- External ports
-----------------------------
adc_in_i => adc_in_dummy,
adc_in_sdr_i => adc_in,
-----------------------------
-- ADC Delay signals
-----------------------------
adc_fn_dly_i => adc_fn_dly_in,
adc_fn_dly_o => adc_fn_dly_out,
adc_cs_dly_i => adc_cs_dly_in,
-----------------------------
-- ADC output signals
-----------------------------
adc_out_o => adc_out,
-- Idelay ready signal
idelay_rdy_o => adc_idelay_rdy,
-----------------------------
-- MMCM general signals
-----------------------------
mmcm_adc_locked_o => mmcm_adc_locked,
fifo_debug_valid_o => fifo_debug_valid_o,
fifo_debug_full_o => fifo_debug_full_o,
fifo_debug_empty_o => fifo_debug_empty_o
);
-- Clock and reset assignments
-- General status board pins
fmc_mmcm_lock_o <= mmcm_adc_locked;
-- ADC data for internal use
gen_adc_data_int : for i in 0 to c_num_adc_channels-1 generate
--adc_clk_int(i) <= adc_out(i).adc_clk;
fs_clk(i) <= adc_out(i).adc_clk;
fs_clk2x(i) <= adc_out(i).adc_clk2x;
adc_data(c_num_adc_bits*(i+1)-1 downto c_num_adc_bits*i)
<= adc_out(i).adc_data;
adc_valid(i) <= adc_out(i).adc_data_valid;
end generate;
-- Output ADC signals to external FPGA
adc_clk_o <= fs_clk;
adc_clk2x_o <= fs_clk2x;
adc_data_o <= adc_data;
adc_data_valid_o <= adc_valid;
-----------------------------
-- I2C Programmable Si571 VCXO
-----------------------------
-- I2C Programmable VCXO control interface.
-- I2C Programmable VCXO is slave number 1, word addressed
-- Note: I2C registers are 8-bit wide, but accessed as 32-bit registers
cmp_vcxo_i2c : xwb_i2c_master
generic map(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map (
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_sync_n,
slave_i => cbar_master_out(1),
slave_o => cbar_master_in(1),
desc_o => open,
scl_pad_i => si571_i2c_scl_in,
scl_pad_o => si571_i2c_scl_out,
scl_padoen_o => si571_i2c_scl_oe_n,
sda_pad_i => si571_i2c_sda_in,
sda_pad_o => si571_i2c_sda_out,
sda_padoen_o => si571_i2c_sda_oe_n
);
si571_scl_pad_b <= si571_i2c_scl_out when si571_i2c_scl_oe_n = '0' else 'Z';
si571_i2c_scl_in <= si571_scl_pad_b;
si571_sda_pad_b <= si571_i2c_sda_out when si571_i2c_sda_oe_n = '0' else 'Z';
si571_i2c_sda_in <= si571_sda_pad_b;
-- Not used wishbone signals
cbar_master_in(1).err <= '0';
cbar_master_in(1).rty <= '0';
-----------------------------
-- AD9510 SPI Bus
-----------------------------
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
-- ADC SPI is slave number 2, word addressed
cmp_ad9510_spi : xwb_spi_bidir
generic map(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map (
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_sync_n,
slave_i => cbar_master_out(2),
slave_o => cbar_master_in(2),
desc_o => open,
pad_cs_o => ad9510_spi_ss_int,
pad_sclk_o => ad9510_spi_clk, --spi_ad9510_sclk_o,
pad_mosi_o => ad9510_spi_dout, --spi_ad9510_mosi_o,
pad_mosi_i => '0',
pad_mosi_en_o => open,
pad_miso_i => ad9510_spi_din --spi_ad9510_miso_i
);
spi_ad9510_cs_o <= ad9510_spi_ss_int(0);
spi_ad9510_sclk_o <= ad9510_spi_clk;
spi_ad9510_mosi_o <= ad9510_spi_dout;
ad9510_spi_din <= spi_ad9510_miso_i;
-- Not used wishbone signals
--cbar_master_in(2).err <= '0';
cbar_master_in(2).rty <= '0';
-----------------------------
-- I2C EEPROM 24AA64T-I
-----------------------------
-- I2C EEPROM is slave number 3, word addressed
cmp_eeprom_i2c : xwb_i2c_master
generic map(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map (
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_sync_n,
slave_i => cbar_master_out(3),
slave_o => cbar_master_in(3),
desc_o => open,
scl_pad_i => eeprom_i2c_scl_in,
scl_pad_o => eeprom_i2c_scl_out,
scl_padoen_o => eeprom_i2c_scl_oe_n,
sda_pad_i => eeprom_i2c_sda_in,
sda_pad_o => eeprom_i2c_sda_out,
sda_padoen_o => eeprom_i2c_sda_oe_n
);
eeprom_scl_pad_b <= eeprom_i2c_scl_out when eeprom_i2c_scl_oe_n = '0' else 'Z';
eeprom_i2c_scl_in <= eeprom_scl_pad_b;
eeprom_sda_pad_b <= eeprom_i2c_sda_out when eeprom_i2c_sda_oe_n = '0' else 'Z';
eeprom_i2c_sda_in <= eeprom_sda_pad_b;
-- Not used wishbone signals
cbar_master_in(3).err <= '0';
cbar_master_in(3).rty <= '0';
-----------------------------
-- I2C LM75AIMM
-----------------------------
-- I2C LM75AIMM is slave number 4, word addressed
cmp_lm75_i2c : xwb_i2c_master
generic map(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map (
clk_sys_i => sys_clk_i,
rst_n_i => sys_rst_sync_n,
slave_i => cbar_master_out(4),
slave_o => cbar_master_in(4),
desc_o => open,
scl_pad_i => lm75a_i2c_scl_in,
scl_pad_o => lm75a_i2c_scl_out,
scl_padoen_o => lm75a_i2c_scl_oe_n,
sda_pad_i => lm75a_i2c_sda_in,
sda_pad_o => lm75a_i2c_sda_out,
sda_padoen_o => lm75a_i2c_sda_oe_n
);
lm75_scl_pad_b <= lm75a_i2c_scl_out when lm75a_i2c_scl_oe_n = '0' else 'Z';
lm75a_i2c_scl_in <= lm75_scl_pad_b;
lm75_sda_pad_b <= lm75a_i2c_sda_out when lm75a_i2c_sda_oe_n = '0' else 'Z';
lm75a_i2c_sda_in <= lm75_sda_pad_b;
-- Not used wishbone signals
cbar_master_in(4).err <= '0';
cbar_master_in(4).rty <= '0';
-----------------------------
-- Wishbone Streaming Interface
-----------------------------
-- This stream source is in ADC clock domain
gen_wbs_interfaces : for i in 0 to c_num_adc_channels-1 generate
gen_wbs_interfaces_ch : if g_use_data_chains(i) = '1' generate
-- Generate 16-bit wishbone streaming interface
cmp_wb_stream_source_gen : wb_stream_source_gen
generic map (
g_wbs_interface_width => NARROW2
)
port map(
--clk_i => fs_clk,
clk_i => fs_clk(i),
rst_n_i => fs_rst_sync_n(i),
---- Wishbone Fabric Interface I/O
-- 16-bit interface
src_adr16_o => wbs_adr_o(c_wbs_adr4_width*(i+1)-1 downto
c_wbs_adr4_width*i),
src_dat16_o => wbs_dat_o(c_wbs_dat16_width*(i+1)-1 downto
c_wbs_dat16_width*i),
src_sel16_o => wbs_sel_o(c_wbs_sel16_width*(i+1)-1 downto
c_wbs_sel16_width*i),
-- Common Wishbone Streaming lines
src_cyc_o => wbs_cyc_o(i),
src_stb_o => wbs_stb_o(i),
src_we_o => wbs_we_o(i),
src_ack_i => wbs_ack_i(i),
src_stall_i => wbs_stall_i(i),
--src_err_i => wbs_err_i(i),
src_err_i => '0',
src_rty_i => wbs_rty_i(i),
-- Decoded & buffered logic
-- 16-bit interface
adr16_i => wbs_adr,
dat16_i => wbs_dat(i),
sel16_i => wbs_sel,
dvalid_i => wbs_valid(i),
sof_i => '1',
eof_i => '0',
error_i => wbs_error,
dreq_o => open
);
-- Generate test data
p_gen_test_data : process(fs_clk(i))
--p_gen_test_data : process(fs_clk2x(c_ref_clk), fs_rst_sync_n(c_ref_clk))
begin
if rising_edge(fs_clk(i)) then
if fs_rst_sync_n(i) = '0' then
wbs_test_data(i) <= (others => '0');
else
wbs_test_data(i) <= wbs_test_data(i) + 1;
end if;
end if;
end process;
wbs_dat(i) <= adc_out(i).adc_data when regs_out.fpga_ctrl_test_data_en_o = '0'
else std_logic_vector(wbs_test_data(i));
wbs_valid(i) <= adc_out(i).adc_data_valid when regs_out.fpga_ctrl_test_data_en_o = '0'
else '1';
end generate;
end generate;
-- Write always to addr c_WBS_DATA (meaning we are transmiting data)
wbs_adr <= std_logic_vector(resize(c_WBS_DATA, wbs_adr'length));
wbs_error <= '0';
wbs_sel <= (others => '1');
-- generate SOF and EOF signals
--p_gen_wbs_sof_eof : process(fs_clk, fs_rst_sync_n)
--begin
-- if fs_rst_sync_n = '0' then
-- wbs_packet_counter <= (others => '0');
-- wbs_sof <= '0';
-- wbs_eof <= '0';
-- elsif rising_edge(fs_clk) then
-- -- Increment counter if data is valid
-- if wbs_dvalid = '1' then
-- wbs_packet_counter <= wbs_packet_counter + 1;
-- end if;
--
-- if wbs_packet_counter = to_unsigned(0, g_packet_size) then
-- wbs_sof <= '1';
-- else
-- wbs_sof <= '0';
-- end if;
--
-- if wbs_packet_counter = g_packet_size-2 and wbs_dvalid = '1' then
-- wbs_eof <= '1';
-- else
-- wbs_eof <= '0';
-- end if;
-- end if;
--end process;
-- Generate SOF and EOF signals based on counter
--wbs_sof <= '1' when wbs_packet_counter = to_unsigned(0, g_packet_size) else '0';
--wbs_eof <= '1' when wbs_packet_counter = g_packet_size-1 else '0';
-----------------------------
-- Trigger Interface.
-----------------------------
--Trigger data output (if in output mode)
cmp_trigger_iobufds : iobufds
generic map (
diff_term => false, -- Differential Termination ("TRUE"/"FALSE")
ibuf_low_pwr => false, -- Low Power - "TRUE", High Performance = "FALSE"
iostandard => "BLVDS_25" -- Specify the I/O standard
)
port map (
o => fmc_trig_val_in, -- Buffer output for further use!!!
io => fmc_trig_val_p_b, -- Diff_p inout (connect directly to top-level port)
iob => fmc_trig_val_n_b, -- Diff_n inout (connect directly to top-level port)
i => fmc_trig_val_int, -- Buffer input
t => fmc_trig_dir_int -- 3-state enable input, high=input, low=output
);
fmc_trig_dir_o <= fmc_trig_dir_int;
-- External hardware trigger synchronization
cmp_trig_sync : gc_ext_pulse_sync
generic map(
g_min_pulse_width => 1, -- clk_i ticks
--g_clk_frequency => 1/g_adc_clk_period_values(g_ref_clk), -- MHz
g_clk_frequency => 130, -- MHz
g_output_polarity => '0', -- positive pulse
g_output_retrig => false,
g_output_length => 1 -- clk_i tick
)
port map(
rst_n_i => fs_rst_sync_n(c_ref_clk),
clk_i => fs_clk(c_ref_clk),
input_polarity_i => '1',
pulse_i => fmc_trig_val_in,
pulse_o => fmc_trig_val_in_sync
);
-- Input external trigger to FPGA pin
fmc_trig_val_int <= fmc_trig_val_int_reg or trig_hw_i;
-- Output external trigger to other logic. Hardware trigger enable
trig_hw_o <= fmc_trig_val_in_sync;
-----------------------------
-- LEDs Interface. Output extended pulses of important commands
-----------------------------
-- FMC LED1
cmp_led1_extende_pulse : gc_extend_pulse
generic map (
-- Input clock = 100MHz
-- 20000000 clock pulses = 0.2s pulse
g_width => 20000000
)
port map(
clk_i => sys_clk_i,
rst_n_i => sys_rst_sync_n,
-- input pulse (synchronous to clk_i)
pulse_i => fmc_trig_val_in_sync,
-- extended output pulse
extended_o => led1_extd_p
);
-- Output extended pulse led from FMC power good signal or register interface
-- manual led control
fmc_led1_o <= led1_extd_p or fmc_led1_int;
fmc_led2_o <= fmc_led2_int;
fmc_led3_o <= fmc_led3_int;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity muxb_265 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end muxb_265;
architecture augh of muxb_265 is
begin
out_data <= in_data0 when in_sel = '0' else in_data1;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity muxb_265 is
port (
in_sel : in std_logic;
out_data : out std_logic;
in_data0 : in std_logic;
in_data1 : in std_logic
);
end muxb_265;
architecture augh of muxb_265 is
begin
out_data <= in_data0 when in_sel = '0' else in_data1;
end architecture;
|
-------------------------------------------------------------------------------
-- Design : Signal Spy testbench for Load/Store Address Buffer
-- Project : Tomasulo Processor
-- Author : Waleed Dweik
-- Data : 07/12/2010
-- Company : University of Southern California
-------------------------------------------------------------------------------
library std,ieee;
library modelsim_lib;
use ieee.std_logic_1164.all;
use modelsim_lib.util.all;
use std.textio.all;
use ieee.std_logic_textio.all;
-- synopsys translate_off
--use work.reverseAssemblyFunctionPkg.all;
-- synopsys translate_on
-----------------------------------------------------------------------------
--added by Sabya to use compiled library
library ee560;
use ee560.all;
------------------------------------------------------------------------------
entity top_tb is
end entity top_tb;
architecture arch_top_tb_Dispatch of top_tb is
-- local signals
signal Clk, Reset: std_logic;
-- clock period
constant Clk_Period: time:= 20 ns;
-- clock count signal to make it easy for debugging
signal Clk_Count: integer range 0 to 999;
-- a 10% delayed clock for clock counting
signal Clk_Delayed10: std_logic;
signal Walking_Led: std_logic;
signal Fio_Icache_Addr_IM: std_logic_vector(5 downto 0);
signal Fio_Icache_Data_In_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Wea_IM: std_logic;
signal Fio_Icache_Data_Out_IM: std_logic_vector(127 downto 0);
signal Fio_Icache_Ena_IM : std_logic;
signal Fio_Dmem_Addr_DM: std_logic_vector(5 downto 0);
signal Fio_Dmem_Data_Out_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Data_In_DM: std_logic_vector(31 downto 0);
signal Fio_Dmem_Wea_DM : std_logic;
-- Hierarchy signals (Golden Dispatch)
signal Dis_Ren_gold : std_logic;
signal Dis_JmpBrAddr_gold : std_logic_vector(31 downto 0);
signal Dis_JmpBr_gold : std_logic;
signal Dis_JmpBrAddrValid_gold : std_logic;
signal Dis_CdbUpdBranch_gold : std_logic;
signal Dis_CdbUpdBranchAddr_gold : std_logic_vector(2 downto 0);
signal Dis_CdbBranchOutcome_gold : std_logic;
signal Dis_BpbBranchPCBits_gold : std_logic_vector(2 downto 0);
signal Dis_BpbBranch_gold : std_logic;
signal Dis_CfcRsAddr_gold : std_logic_vector(4 downto 0);
signal Dis_CfcRtAddr_gold : std_logic_vector(4 downto 0);
signal Dis_CfcRdAddr_gold : std_logic_vector(4 downto 0);
signal Dis_CfcBranchTag_gold : std_logic_vector(4 downto 0) ;
signal Dis_CfcRegWrite_gold : std_logic;
signal Dis_CfcNewRdPhyAddr_gold : std_logic_vector(5 downto 0);
signal Dis_CfcBranch_gold : std_logic;
signal Dis_CfcInstValid_gold : std_logic;
signal Dis_RegWrite_gold : std_logic;
signal Dis_RsDataRdy_gold : std_logic;
signal Dis_RtDataRdy_gold : std_logic;
signal Dis_RsPhyAddr_gold : std_logic_vector(5 downto 0);
signal Dis_RtPhyAddr_gold : std_logic_vector(5 downto 0);
signal Dis_RobTag_gold : std_logic_vector(4 downto 0);
signal Dis_Opcode_gold : std_logic_vector(2 downto 0);
signal Dis_IntIssquenable_gold : std_logic;
signal Dis_LdIssquenable_gold : std_logic;
signal Dis_DivIssquenable_gold : std_logic;
signal Dis_MulIssquenable_gold : std_logic;
signal Dis_Immediate_gold : std_logic_vector(15 downto 0);
signal Dis_BranchOtherAddr_gold : std_logic_vector(31 downto 0);
signal Dis_BranchPredict_gold : std_logic;
signal Dis_Branch_gold : std_logic;
signal Dis_BranchPCBits_gold : std_logic_vector(2 downto 0);
signal Dis_JrRsInst_gold : std_logic;
signal Dis_JalInst_gold : std_logic ;
signal Dis_Jr31Inst_gold : std_logic;
signal Dis_FrlRead_gold : std_logic ;
signal Dis_RasJalInst_gold : std_logic ;
signal Dis_RasJr31Inst_gold : std_logic;
signal Dis_PcPlusFour_gold : std_logic_vector(31 downto 0);
signal Dis_PrevPhyAddr_gold : std_logic_vector(5 downto 0);
signal Dis_NewRdPhyAddr_gold : std_logic_vector(5 downto 0);
signal Dis_RobRdAddr_gold : std_logic_vector(4 downto 0);
signal Dis_InstValid_gold : std_logic ;
signal Dis_InstSw_gold : std_logic ;
signal Dis_SwRtPhyAddr_gold : std_logic_vector(5 downto 0);
-- translate_off
signal Dis_Instruction_gold : std_logic_vector(31 downto 0);
-- translate_on
-- Signals for the student's DUT (Dispatch)
signal Resetb : std_logic ;
signal Ifetch_Instruction : std_logic_vector(31 downto 0);
signal Ifetch_PcPlusFour : std_logic_vector(31 downto 0);
signal Ifetch_EmptyFlag : std_logic;
signal Dis_Ren : std_logic;
signal Dis_JmpBrAddr : std_logic_vector(31 downto 0);
signal Dis_JmpBr : std_logic;
signal Dis_JmpBrAddrValid : std_logic;
signal Dis_CdbUpdBranch : std_logic;
signal Dis_CdbUpdBranchAddr : std_logic_vector(2 downto 0);
signal Dis_CdbBranchOutcome : std_logic;
signal Bpb_BranchPrediction : std_logic;
signal Dis_BpbBranchPCBits : std_logic_vector(2 downto 0);
signal Dis_BpbBranch : std_logic;
signal Cdb_Branch : std_logic;
signal Cdb_BranchOutcome : std_logic;
signal Cdb_BranchAddr : std_logic_vector(31 downto 0);
signal Cdb_BranchUpdtAddr : std_logic_vector(2 downto 0);
signal Cdb_Flush : std_logic;
signal Cdb_RobTag : std_logic_vector(4 downto 0);
signal Dis_CfcRsAddr : std_logic_vector(4 downto 0);
signal Dis_CfcRtAddr : std_logic_vector(4 downto 0);
signal Dis_CfcRdAddr : std_logic_vector(4 downto 0);
signal Cfc_RsPhyAddr : std_logic_vector(5 downto 0);
signal Cfc_RtPhyAddr : std_logic_vector(5 downto 0);
signal Cfc_RdPhyAddr : std_logic_vector(5 downto 0);
signal Cfc_Full : std_logic ;
signal Dis_CfcBranchTag : std_logic_vector(4 downto 0) ;
signal Dis_CfcRegWrite : std_logic;
signal Dis_CfcNewRdPhyAddr : std_logic_vector(5 downto 0);
signal Dis_CfcBranch : std_logic;
signal Dis_CfcInstValid : std_logic;
signal PhyReg_RsDataRdy : std_logic ;
signal PhyReg_RtDataRdy : std_logic ;
signal Dis_RegWrite : std_logic;
signal Dis_RsDataRdy : std_logic;
signal Dis_RtDataRdy : std_logic;
signal Dis_RsPhyAddr : std_logic_vector(5 downto 0);
signal Dis_RtPhyAddr : std_logic_vector(5 downto 0);
signal Dis_RobTag : std_logic_vector(4 downto 0);
signal Dis_Opcode : std_logic_vector(2 downto 0);
signal Dis_IntIssquenable : std_logic;
signal Dis_LdIssquenable : std_logic;
signal Dis_DivIssquenable : std_logic;
signal Dis_MulIssquenable : std_logic;
signal Dis_Immediate : std_logic_vector(15 downto 0);
signal Issque_IntQueueFull : std_logic;
signal Issque_LdStQueueFull : std_logic;
signal Issque_DivQueueFull : std_logic;
signal Issque_MulQueueFull : std_logic;
signal Issque_IntQueueTwoOrMoreVacant : std_logic;
signal Issque_LdStQueueTwoOrMoreVacant : std_logic;
signal Issque_DivQueueTwoOrMoreVacant : std_logic;
signal Issque_MulQueueTwoOrMoreVacant : std_logic;
signal Dis_BranchOtherAddr : std_logic_vector(31 downto 0);
signal Dis_BranchPredict : std_logic;
signal Dis_Branch : std_logic;
signal Dis_BranchPCBits : std_logic_vector(2 downto 0);
signal Dis_JrRsInst : std_logic;
signal Dis_JalInst : std_logic ;
signal Dis_Jr31Inst : std_logic;
signal Frl_RdPhyAddr : std_logic_vector(5 downto 0);
signal Dis_FrlRead : std_logic ;
signal Frl_Empty : std_logic;
signal Dis_RasJalInst : std_logic ;
signal Dis_RasJr31Inst : std_logic;
signal Dis_PcPlusFour : std_logic_vector(31 downto 0);
signal Ras_Addr : std_logic_vector(31 downto 0);
signal Dis_PrevPhyAddr : std_logic_vector(5 downto 0);
signal Dis_NewRdPhyAddr : std_logic_vector(5 downto 0);
signal Dis_RobRdAddr : std_logic_vector(4 downto 0);
signal Dis_InstValid : std_logic ;
signal Dis_InstSw : std_logic ;
signal Dis_SwRtPhyAddr : std_logic_vector(5 downto 0);
signal Rob_BottomPtr : std_logic_vector(4 downto 0);
signal Rob_Full : std_logic;
signal Rob_TwoOrMoreVacant : std_logic;
signal Dis_Instruction : std_logic_vector(31 downto 0);
component tomasulo_top
port (
Reset : in std_logic;
Clk : in std_logic;
Fio_Icache_Addr_IM : in std_logic_vector(5 downto 0);
Fio_Icache_Data_In_IM : in std_logic_vector(127 downto 0);
Fio_Icache_Wea_IM : in std_logic;
Fio_Icache_Data_Out_IM : out std_logic_vector(127 downto 0);
Fio_Icache_Ena_IM : in std_logic;
Fio_Dmem_Addr_DM : in std_logic_vector(5 downto 0);
Fio_Dmem_Data_Out_DM : out std_logic_vector(31 downto 0);
Fio_Dmem_Data_In_DM : in std_logic_vector(31 downto 0);
Fio_Dmem_Wea_DM : in std_logic;
Test_mode : in std_logic;
Walking_Led_start : out std_logic
);
end component tomasulo_top;
component dispatch_unit is
port(
Clk : in std_logic ;
Resetb : in std_logic ;
Ifetch_Instruction : in std_logic_vector(31 downto 0);
Ifetch_PcPlusFour : in std_logic_vector(31 downto 0);
Ifetch_EmptyFlag : in std_logic;
Dis_Ren : out std_logic;
Dis_JmpBrAddr : out std_logic_vector(31 downto 0);
Dis_JmpBr : out std_logic;
Dis_JmpBrAddrValid : out std_logic;
Dis_CdbUpdBranch : out std_logic;
Dis_CdbUpdBranchAddr : out std_logic_vector(2 downto 0);
Dis_CdbBranchOutcome : out std_logic;
Bpb_BranchPrediction : in std_logic;
Dis_BpbBranchPCBits : out std_logic_vector(2 downto 0);
Dis_BpbBranch : out std_logic;
Cdb_Branch : in std_logic;
Cdb_BranchOutcome : in std_logic;
Cdb_BranchAddr : in std_logic_vector(31 downto 0);
Cdb_BrUpdtAddr : in std_logic_vector(2 downto 0);
Cdb_Flush : in std_logic;
Cdb_RobTag : in std_logic_vector(4 downto 0);
Dis_CfcRsAddr : out std_logic_vector(4 downto 0);
Dis_CfcRtAddr : out std_logic_vector(4 downto 0);
Dis_CfcRdAddr : out std_logic_vector(4 downto 0);
Cfc_RsPhyAddr : in std_logic_vector(5 downto 0);
Cfc_RtPhyAddr : in std_logic_vector(5 downto 0);
Cfc_RdPhyAddr : in std_logic_vector(5 downto 0);
Cfc_Full : in std_logic ;
Dis_CfcBranchTag : out std_logic_vector(4 downto 0) ;
Dis_CfcRegWrite : out std_logic;
Dis_CfcNewRdPhyAddr : out std_logic_vector(5 downto 0);
Dis_CfcBranch : out std_logic;
Dis_CfcInstValid : out std_logic;
PhyReg_RsDataRdy : in std_logic ;
PhyReg_RtDataRdy : in std_logic ;
-- translate_off
Dis_Instruction : out std_logic_vector(31 downto 0);
-- translate_on
Dis_RegWrite : out std_logic;
Dis_RsDataRdy : out std_logic;
Dis_RtDataRdy : out std_logic;
Dis_RsPhyAddr : out std_logic_vector(5 downto 0);
Dis_RtPhyAddr : out std_logic_vector(5 downto 0);
Dis_RobTag : out std_logic_vector(4 downto 0);
Dis_Opcode : out std_logic_vector(2 downto 0);
Dis_IntIssquenable : out std_logic;
Dis_LdIssquenable : out std_logic;
Dis_DivIssquenable : out std_logic;
Dis_MulIssquenable : out std_logic;
Dis_Immediate : out std_logic_vector(15 downto 0);
Issque_IntQueueFull : in std_logic;
Issque_LdStQueueFull : in std_logic;
Issque_DivQueueFull : in std_logic;
Issque_MulQueueFull : in std_logic;
Issque_IntQueTwoOrMoreVacant : in std_logic;
Issque_LdStQueTwoOrMoreVacant : in std_logic;
Issque_DivQueTwoOrMoreVacant : in std_logic;
Issque_MulQueTwoOrMoreVacant : in std_logic;
Dis_BranchOtherAddr : out std_logic_vector(31 downto 0);
Dis_BranchPredict : out std_logic;
Dis_Branch : out std_logic;
Dis_BranchPCBits : out std_logic_vector(2 downto 0);
Dis_JrRsInst : out std_logic;
Dis_JalInst : out std_logic ;
Dis_Jr31Inst : out std_logic;
Frl_RdPhyAddr : in std_logic_vector(5 downto 0);
Dis_FrlRead : out std_logic ;
Frl_Empty : in std_logic;
Dis_RasJalInst : out std_logic ;
Dis_RasJr31Inst : out std_logic;
Dis_PcPlusFour : out std_logic_vector(31 downto 0);
Ras_Addr : in std_logic_vector(31 downto 0);
Dis_PrevPhyAddr : out std_logic_vector(5 downto 0);
Dis_NewRdPhyAddr : out std_logic_vector(5 downto 0);
Dis_RobRdAddr : out std_logic_vector(4 downto 0);
Dis_InstValid : out std_logic ;
Dis_InstSw : out std_logic ;
Dis_SwRtPhyAddr : out std_logic_vector(5 downto 0);
Rob_BottomPtr : in std_logic_vector(4 downto 0);
Rob_Full : in std_logic;
Rob_TwoOrMoreVacant : in std_logic
);
end component;
for dispatch_unit_TEST: dispatch_unit use entity work.dispatch_unit(behv);
begin
UUT: tomasulo_top
port map (
Reset => Reset,
Clk => Clk,
Fio_Icache_Addr_IM => Fio_Icache_Addr_IM,
Fio_Icache_Data_In_IM => Fio_Icache_Data_In_IM,
Fio_Icache_Wea_IM => Fio_Icache_Wea_IM ,
Fio_Icache_Data_Out_IM => Fio_Icache_Data_Out_IM,
Fio_Icache_Ena_IM => Fio_Icache_Ena_IM,
Fio_Dmem_Addr_DM => Fio_Dmem_Addr_DM,
Fio_Dmem_Data_Out_DM => Fio_Dmem_Data_Out_DM,
Fio_Dmem_Data_In_DM => Fio_Dmem_Data_In_DM,
Fio_Dmem_Wea_DM => Fio_Dmem_Wea_DM,
Test_mode => '0',
Walking_Led_start => Walking_Led
);
dispatch_unit_TEST : dispatch_unit
port map(
Clk => Clk,
Resetb => Resetb,
Ifetch_Instruction => Ifetch_Instruction,
Ifetch_PcPlusFour => Ifetch_PcPlusFour,
Ifetch_EmptyFlag => Ifetch_EmptyFlag,
Dis_Ren => Dis_Ren,
Dis_JmpBrAddr => Dis_JmpBrAddr,
Dis_JmpBr => Dis_JmpBr,
Dis_JmpBrAddrValid => Dis_JmpBrAddrValid,
Dis_CdbUpdBranch => Dis_CdbUpdBranch,
Dis_CdbUpdBranchAddr => Dis_CdbUpdBranchAddr,
Dis_CdbBranchOutcome => Dis_CdbBranchOutcome,
Bpb_BranchPrediction => Bpb_BranchPrediction,
Dis_BpbBranchPCBits => Dis_BpbBranchPCBits,
Dis_BpbBranch => Dis_BpbBranch,
Cdb_Branch => Cdb_Branch,
Cdb_BranchOutcome => Cdb_BranchOutcome,
Cdb_BranchAddr => Cdb_BranchAddr,
Cdb_BrUpdtAddr => Cdb_BranchUpdtAddr,
Cdb_Flush => Cdb_Flush,
Cdb_RobTag => Cdb_RobTag,
Dis_CfcRsAddr => Dis_CfcRsAddr,
Dis_CfcRtAddr => Dis_CfcRtAddr,
Dis_CfcRdAddr => Dis_CfcRdAddr,
Cfc_RsPhyAddr => Cfc_RsPhyAddr,
Cfc_RtPhyAddr => Cfc_RtPhyAddr,
Cfc_RdPhyAddr => Cfc_RdPhyAddr,
Cfc_Full => Cfc_Full,
Dis_CfcBranchTag => Dis_CfcBranchTag,
Dis_CfcRegWrite => Dis_CfcRegWrite,
Dis_CfcNewRdPhyAddr => Dis_CfcNewRdPhyAddr,
Dis_CfcBranch => Dis_CfcBranch,
Dis_CfcInstValid => Dis_CfcInstValid,
PhyReg_RsDataRdy => PhyReg_RsDataRdy,
PhyReg_RtDataRdy => PhyReg_RtDataRdy,
-- translate_off
Dis_Instruction => Dis_instruction,
-- translate_on
Dis_RegWrite => Dis_RegWrite,
Dis_RsDataRdy => Dis_RsDataRdy,
Dis_RtDataRdy => Dis_RtDataRdy,
Dis_RsPhyAddr => Dis_RsPhyAddr,
Dis_RtPhyAddr => Dis_RtPhyAddr,
Dis_RobTag => Dis_RobTag,
Dis_Opcode => Dis_Opcode,
Dis_IntIssquenable => Dis_IntIssquenable,
Dis_LdIssquenable => Dis_LdIssquenable,
Dis_DivIssquenable => Dis_DivIssquenable,
Dis_MulIssquenable => Dis_MulIssquenable,
Dis_Immediate => Dis_Immediate,
Issque_IntQueueFull => Issque_IntQueueFull,
Issque_LdStQueueFull => Issque_LdStQueueFull,
Issque_DivQueueFull => Issque_DivQueueFull,
Issque_MulQueueFull => Issque_MulQueueFull,
Issque_IntQueTwoOrMoreVacant => Issque_IntQueueTwoOrMoreVacant,
Issque_LdStQueTwoOrMoreVacant => Issque_LdStQueueTwoOrMoreVacant,
Issque_DivQueTwoOrMoreVacant => Issque_DivQueueTwoOrMoreVacant,
Issque_MulQueTwoOrMoreVacant => Issque_MulQueueTwoOrMoreVacant,
Dis_BranchOtherAddr => Dis_BranchOtherAddr,
Dis_BranchPredict => Dis_BranchPredict,
Dis_BranchPCBits => Dis_BranchPCBits,
Dis_Branch => Dis_Branch,
Dis_JrRsInst => Dis_JrRsInst,
Dis_JalInst => Dis_JalInst,
Dis_Jr31Inst => Dis_Jr31Inst,
Frl_RdPhyAddr => Frl_RdPhyAddr,
Dis_FrlRead => Dis_FrlRead,
Frl_Empty => Frl_Empty,
Dis_RasJalInst => Dis_RasJalInst,
Dis_RasJr31Inst => Dis_RasJr31Inst,
Dis_PcPlusFour => Dis_PcPlusFour,
Ras_Addr => Ras_Addr,
Dis_PrevPhyAddr => Dis_PrevPhyAddr,
Dis_NewRdPhyAddr => Dis_NewRdPhyAddr,
Dis_RobRdAddr => Dis_RobRdAddr,
Dis_InstValid => Dis_InstValid,
Dis_InstSw => Dis_InstSw,
Dis_SwRtPhyAddr => Dis_SwRtPhyAddr,
Rob_BottomPtr => Rob_BottomPtr,
Rob_Full => Rob_Full,
Rob_TwoOrMoreVacant => Rob_TwoOrMoreVacant
);
clock_generate: process
begin
Clk <= '0', '1' after (Clk_Period/2);
wait for Clk_Period;
end process clock_generate;
-- Reset activation and inactivation
Reset <= '1', '0' after (Clk_Period * 4.1 );
Clk_Delayed10 <= Clk after (Clk_Period/10);
-- clock count processes
Clk_Count_process: process (Clk_Delayed10, Reset)
begin
if Reset = '1' then
Clk_Count <= 0;
elsif Clk_Delayed10'event and Clk_Delayed10 = '1' then
Clk_Count <= Clk_Count + 1;
end if;
end process Clk_Count_process;
-------------------------------------------------
--check outputs of Load/Store Address Buffer only--
-------------------------------------------------
compare_outputs_Clkd: process (Clk_Delayed10, Reset)
file my_outfile: text open append_mode is "TomasuloCompareTestLog.log";
variable my_inline, my_outline: line;
begin
if (Reset = '0' and (Clk_Delayed10'event and Clk_Delayed10 = '0')) then --- 10%after the middle of the clock.
if (Dis_Ren_gold /= Dis_Ren) then
write (my_outline, string'("ERROR! Dis_Ren of TEST does not match Dis_Ren_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_JmpBrAddr_gold /= Dis_JmpBrAddr) then
write (my_outline, string'("ERROR! Dis_JmpBrAddr of TEST does not match Dis_JmpBrAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_JmpBr_gold /= Dis_JmpBr) then
write (my_outline, string'("ERROR! Dis_JmpBr of TEST does not match Dis_JmpBr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_JmpBrAddrValid_gold /= Dis_JmpBrAddrValid) then
write (my_outline, string'("ERROR! Dis_JmpBrAddrValid of TEST does not match Dis_JmpBrAddrValid_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CdbUpdBranch_gold /= Dis_CdbUpdBranch) then
write (my_outline, string'("ERROR! Dis_CdbUpdBranch of TEST does not match Dis_CdbUpdBranch_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CdbUpdBranchAddr_gold /= Dis_CdbUpdBranchAddr) then
write (my_outline, string'("ERROR! Dis_CdbUpdBranchAddr of TEST does not match Dis_CdbUpdBranchAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CdbBranchOutcome_gold /= Dis_CdbBranchOutcome) then
write (my_outline, string'("ERROR! Dis_CdbBranchOutcome of TEST does not match Dis_CdbBranchOutcome_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_BpbBranchPCBits_gold /= Dis_BpbBranchPCBits) then
write (my_outline, string'("ERROR! Dis_BpbBranchPCBits of TEST does not match Dis_BpbBranchPCBits_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_BpbBranch_gold /= Dis_BpbBranch) then
write (my_outline, string'("ERROR! Dis_BpbBranch of TEST does not match Dis_BpbBranch_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CfcRsAddr_gold /= Dis_CfcRsAddr) then
write (my_outline, string'("ERROR! Dis_CfcRsAddr of TEST does not match Dis_CfcRsAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CfcRtAddr_gold /= Dis_CfcRtAddr) then
write (my_outline, string'("ERROR! Dis_CfcRtAddr of TEST does not match Dis_CfcRtAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CfcRdAddr_gold /= Dis_CfcRdAddr) then
write (my_outline, string'("ERROR! Dis_CfcRdAddr of TEST does not match Dis_CfcRdAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CfcBranchTag_gold /= Dis_CfcBranchTag) then
write (my_outline, string'("ERROR! Dis_CfcBranchTag of TEST does not match Dis_CfcBranchTag_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CfcRegWrite_gold /= Dis_CfcRegWrite) then
write (my_outline, string'("ERROR! Dis_CfcRegWrite of TEST does not match Dis_CfcRegWrite_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CfcNewRdPhyAddr_gold /= Dis_CfcNewRdPhyAddr) then
write (my_outline, string'("ERROR! Dis_CfcNewRdPhyAddr of TEST does not match Dis_CfcNewRdPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CfcBranch_gold /= Dis_CfcBranch) then
write (my_outline, string'("ERROR! Dis_CfcBranch of TEST does not match Dis_CfcBranch_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_CfcInstValid_gold /= Dis_CfcInstValid) then
write (my_outline, string'("ERROR! Dis_CfcInstValid of TEST does not match Dis_CfcInstValid_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_RegWrite_gold /= Dis_RegWrite) then
write (my_outline, string'("ERROR! Dis_RegWrite of TEST does not match Dis_RegWrite_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_RsDataRdy_gold /= Dis_RsDataRdy) then
write (my_outline, string'("ERROR! Dis_RsDataRdy of TEST does not match Dis_RsDataRdy_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_RtDataRdy_gold /= Dis_RtDataRdy) then
write (my_outline, string'("ERROR! Dis_RtDataRdy of TEST does not match Dis_RtDataRdy_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_RsPhyAddr_gold /= Dis_RsPhyAddr) then
write (my_outline, string'("ERROR! Dis_RsPhyAddr of TEST does not match Dis_RsPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_RtPhyAddr_gold /= Dis_RtPhyAddr) then
write (my_outline, string'("ERROR! Dis_RtPhyAddr of TEST does not match Dis_RtPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_RobTag_gold /= Dis_RobTag) then
write (my_outline, string'("ERROR! Dis_RobTag of TEST does not match Dis_RobTag_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_Opcode_gold /= Dis_Opcode) then
write (my_outline, string'("ERROR! Dis_Opcode of TEST does not match Dis_Opcode_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_IntIssquenable_gold /= Dis_IntIssquenable) then
write (my_outline, string'("ERROR! Dis_IntIssquenable of TEST does not match Dis_IntIssquenable_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_LdIssquenable_gold /= Dis_LdIssquenable) then
write (my_outline, string'("ERROR! Dis_LdIssquenable of TEST does not match Dis_LdIssquenable_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_DivIssquenable_gold /= Dis_DivIssquenable) then
write (my_outline, string'("ERROR! Dis_DivIssquenable of TEST does not match Dis_DivIssquenable_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_MulIssquenable_gold /= Dis_MulIssquenable) then
write (my_outline, string'("ERROR! Dis_MulIssquenable of TEST does not match Dis_MulIssquenable_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_Immediate_gold /= Dis_Immediate) then
write (my_outline, string'("ERROR! Dis_Immediate of TEST does not match Dis_Immediate_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_BranchOtherAddr_gold /= Dis_BranchOtherAddr) then
write (my_outline, string'("ERROR! Dis_BranchOtherAddr of TEST does not match Dis_BranchOtherAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_BranchPredict_gold /= Dis_BranchPredict) then
write (my_outline, string'("ERROR! Dis_BranchPredict of TEST does not match Dis_BranchPredict_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_Branch_gold /= Dis_Branch) then
write (my_outline, string'("ERROR! Dis_Branch of TEST does not match Dis_Branch_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_BranchPCBits_gold /= Dis_BranchPCBits) then
write (my_outline, string'("ERROR! Dis_BranchPCBits of TEST does not match Dis_BranchPCBits_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_JrRsInst_gold /= Dis_JrRsInst) then
write (my_outline, string'("ERROR! Dis_JrRsInst of TEST does not match Dis_JrRsInst_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_JalInst_gold /= Dis_JalInst) then
write (my_outline, string'("ERROR! Dis_JalInst of TEST does not match Dis_JalInst_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_Jr31Inst_gold /= Dis_Jr31Inst) then
write (my_outline, string'("ERROR! Dis_Jr31Inst of TEST does not match Dis_Jr31Inst_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_FrlRead_gold /= Dis_FrlRead) then
write (my_outline, string'("ERROR! Dis_FrlRead of TEST does not match Dis_FrlRead_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_RasJalInst_gold /= Dis_RasJalInst) then
write (my_outline, string'("ERROR! Dis_RasJalInst of TEST does not match Dis_RasJalInst_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_RasJr31Inst_gold /= Dis_RasJr31Inst) then
write (my_outline, string'("ERROR! Dis_RasJr31Inst of TEST does not match Dis_RasJr31Inst_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_PcPlusFour_gold /= Dis_PcPlusFour) then
write (my_outline, string'("ERROR! Dis_PcPlusFour of TEST does not match Dis_PcPlusFour_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_PrevPhyAddr_gold /= Dis_PrevPhyAddr) then
write (my_outline, string'("ERROR! Dis_PrevPhyAddr of TEST does not match Dis_PrevPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_NewRdPhyAddr_gold /= Dis_NewRdPhyAddr) then
write (my_outline, string'("ERROR! Dis_NewRdPhyAddr of TEST does not match Dis_NewRdPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_RobRdAddr_gold /= Dis_RobRdAddr) then
write (my_outline, string'("ERROR! Dis_RobRdAddr of TEST does not match Dis_RobRdAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_InstValid_gold /= Dis_InstValid) then
write (my_outline, string'("ERROR! Dis_InstValid of TEST does not match Dis_InstValid_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_InstSw_gold /= Dis_InstSw) then
write (my_outline, string'("ERROR! Dis_InstSw of TEST does not match Dis_InstSw_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_SwRtPhyAddr_gold /= Dis_SwRtPhyAddr) then
write (my_outline, string'("ERROR! Dis_SwRtPhyAddr of TEST does not match Dis_SwRtPhyAddr_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
if (Dis_Instruction_gold /= Dis_Instruction) then
write (my_outline, string'("ERROR! Dis_Instruction of TEST does not match Dis_Instruction_gold at clock_count = " & integer'image(Clk_Count)));
writeline (my_outfile, my_outline);
end if;
end if;
end process compare_outputs_Clkd;
spy_process: process
begin
--inputs
init_signal_spy("/UUT/dispatch_inst/Resetb","Resetb",1,1);
enable_signal_spy("/UUT/dispatch_inst/Resetb","Resetb",0);
init_signal_spy("/UUT/dispatch_inst/Ifetch_Instruction","Ifetch_Instruction",1,1);
enable_signal_spy("/UUT/dispatch_inst/Ifetch_Instruction","Ifetch_Instruction",0);
init_signal_spy("/UUT/dispatch_inst/Ifetch_PcPlusFour","Ifetch_PcPlusFour",1,1);
enable_signal_spy("/UUT/dispatch_inst/Ifetch_PcPlusFour","Ifetch_PcPlusFour",0);
init_signal_spy("/UUT/dispatch_inst/Ifetch_EmptyFlag","Ifetch_EmptyFlag",1,1);
enable_signal_spy("/UUT/dispatch_inst/Ifetch_EmptyFlag","Ifetch_EmptyFlag",0);
init_signal_spy("/UUT/dispatch_inst/Bpb_BranchPrediction","Bpb_BranchPrediction",1,1);
enable_signal_spy("/UUT/dispatch_inst/Bpb_BranchPrediction","Bpb_BranchPrediction",0);
init_signal_spy("/UUT/dispatch_inst/Cdb_Branch","Cdb_Branch",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cdb_Branch","Cdb_Branch",0);
init_signal_spy("/UUT/dispatch_inst/Cdb_BranchOutcome","Cdb_BranchOutcome",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cdb_BranchOutcome","Cdb_BranchOutcome",0);
init_signal_spy("/UUT/dispatch_inst/Cdb_BranchAddr","Cdb_BranchAddr",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cdb_BranchAddr","Cdb_BranchAddr",0);
init_signal_spy("/UUT/dispatch_inst/Cdb_BrUpdtAddr","Cdb_BranchUpdtAddr",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cdb_BrUpdtAddr","Cdb_BranchUpdtAddr",0);
init_signal_spy("/UUT/dispatch_inst/Cdb_Flush","Cdb_Flush",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cdb_Flush","Cdb_Flush",0);
init_signal_spy("/UUT/dispatch_inst/Cdb_RobTag","Cdb_RobTag",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cdb_RobTag","Cdb_RobTag",0);
init_signal_spy("/UUT/dispatch_inst/Cfc_RsPhyAddr","Cfc_RsPhyAddr",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cfc_RsPhyAddr","Cfc_RsPhyAddr",0);
init_signal_spy("/UUT/dispatch_inst/Cfc_RtPhyAddr","Cfc_RtPhyAddr",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cfc_RtPhyAddr","Cfc_RtPhyAddr",0);
init_signal_spy("/UUT/dispatch_inst/Cfc_RdPhyAddr","Cfc_RdPhyAddr",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cfc_RdPhyAddr","Cfc_RdPhyAddr",0);
init_signal_spy("/UUT/dispatch_inst/Cfc_Full","Cfc_Full",1,1);
enable_signal_spy("/UUT/dispatch_inst/Cfc_Full","Cfc_Full",0);
init_signal_spy("/UUT/dispatch_inst/PhyReg_RsDataRdy","PhyReg_RsDataRdy",1,1);
enable_signal_spy("/UUT/dispatch_inst/PhyReg_RsDataRdy","PhyReg_RsDataRdy",0);
init_signal_spy("/UUT/dispatch_inst/PhyReg_RtDataRdy","PhyReg_RtDataRdy",1,1);
enable_signal_spy("/UUT/dispatch_inst/PhyReg_RtDataRdy","PhyReg_RtDataRdy",0);
init_signal_spy("/UUT/dispatch_inst/Issque_IntQueueFull","Issque_IntQueueFull",1,1);
enable_signal_spy("/UUT/dispatch_inst/Issque_IntQueueFull","Issque_IntQueueFull",0);
init_signal_spy("/UUT/dispatch_inst/Issque_LdStQueueFull","Issque_LdStQueueFull",1,1);
enable_signal_spy("/UUT/dispatch_inst/Issque_LdStQueueFull","Issque_LdStQueueFull",0);
init_signal_spy("/UUT/dispatch_inst/Issque_DivQueueFull","Issque_DivQueueFull",1,1);
enable_signal_spy("/UUT/dispatch_inst/Issque_DivQueueFull","Issque_DivQueueFull",0);
init_signal_spy("/UUT/dispatch_inst/Issque_MulQueueFull","Issque_MulQueueFull",1,1);
enable_signal_spy("/UUT/dispatch_inst/Issque_MulQueueFull","Issque_MulQueueFull",0);
init_signal_spy("/UUT/dispatch_inst/Issque_IntQueTwoOrMoreVacant","Issque_IntQueueTwoOrMoreVacant",1,1);
enable_signal_spy("/UUT/dispatch_inst/Issque_IntQueTwoOrMoreVacant","Issque_IntQueueTwoOrMoreVacant",0);
init_signal_spy("/UUT/dispatch_inst/Issque_LdStQueTwoOrMoreVacant","Issque_LdStQueueTwoOrMoreVacant",1,1);
enable_signal_spy("/UUT/dispatch_inst/Issque_LdStQueTwoOrMoreVacant","Issque_LdStQueueTwoOrMoreVacant",0);
init_signal_spy("/UUT/dispatch_inst/Issque_DivQueTwoOrMoreVacant","Issque_DivQueueTwoOrMoreVacant",1,1);
enable_signal_spy("/UUT/dispatch_inst/Issque_DivQueTwoOrMoreVacant","Issque_DivQueueTwoOrMoreVacant",0);
init_signal_spy("/UUT/dispatch_inst/Issque_MulQueTwoOrMoreVacant","Issque_MulQueueTwoOrMoreVacant",1,1);
enable_signal_spy("/UUT/dispatch_inst/Issque_MulQueTwoOrMoreVacant","Issque_MulQueueTwoOrMoreVacant",0);
init_signal_spy("/UUT/dispatch_inst/Frl_RdPhyAddr","Frl_RdPhyAddr",1,1);
enable_signal_spy("/UUT/dispatch_inst/Frl_RdPhyAddr","Frl_RdPhyAddr",0);
init_signal_spy("/UUT/dispatch_inst/Frl_Empty","Frl_Empty",1,1);
enable_signal_spy("/UUT/dispatch_inst/Frl_Empty","Frl_Empty",0);
init_signal_spy("/UUT/dispatch_inst/Ras_Addr","Ras_Addr",1,1);
enable_signal_spy("/UUT/dispatch_inst/Ras_Addr","Ras_Addr",0);
init_signal_spy("/UUT/dispatch_inst/Rob_BottomPtr","Rob_BottomPtr",1,1);
enable_signal_spy("/UUT/dispatch_inst/Rob_BottomPtr","Rob_BottomPtr",0);
init_signal_spy("/UUT/dispatch_inst/Rob_Full","Rob_Full",1,1);
enable_signal_spy("/UUT/dispatch_inst/Rob_Full","Rob_Full",0);
init_signal_spy("/UUT/dispatch_inst/Rob_TwoOrMoreVacant","Rob_TwoOrMoreVacant",1,1);
enable_signal_spy("/UUT/dispatch_inst/Rob_TwoOrMoreVacant","Rob_TwoOrMoreVacant",0);
--outputs--
init_signal_spy("/UUT/dispatch_inst/Dis_Ren","Dis_Ren_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_Ren","Dis_Ren_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_JmpBrAddr","Dis_JmpBrAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_JmpBrAddr","Dis_JmpBrAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_JmpBr","Dis_JmpBr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_JmpBr","Dis_JmpBr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_JmpBrAddrValid","Dis_JmpBrAddrValid_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_JmpBrAddrValid","Dis_JmpBrAddrValid_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CdbUpdBranch","Dis_CdbUpdBranch_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CdbUpdBranch","Dis_CdbUpdBranch_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CdbUpdBranchAddr","Dis_CdbUpdBranchAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CdbUpdBranchAddr","Dis_CdbUpdBranchAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CdbBranchOutcome","Dis_CdbBranchOutcome_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CdbBranchOutcome","Dis_CdbBranchOutcome_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_BpbBranchPCBits","Dis_BpbBranchPCBits_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_BpbBranchPCBits","Dis_BpbBranchPCBits_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_BpbBranch","Dis_BpbBranch_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_BpbBranch","Dis_BpbBranch_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CfcRsAddr","Dis_CfcRsAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CfcRsAddr","Dis_CfcRsAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CfcRtAddr","Dis_CfcRtAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CfcRtAddr","Dis_CfcRtAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CfcRdAddr","Dis_CfcRdAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CfcRdAddr","Dis_CfcRdAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CfcBranchTag","Dis_CfcBranchTag_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CfcBranchTag","Dis_CfcBranchTag_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CfcRegWrite","Dis_CfcRegWrite_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CfcRegWrite","Dis_CfcRegWrite_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CfcNewRdPhyAddr","Dis_CfcNewRdPhyAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CfcNewRdPhyAddr","Dis_CfcNewRdPhyAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CfcBranch","Dis_CfcBranch_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CfcBranch","Dis_CfcBranch_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_CfcInstValid","Dis_CfcInstValid_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_CfcInstValid","Dis_CfcInstValid_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_RegWrite","Dis_RegWrite_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_RegWrite","Dis_RegWrite_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_RsDataRdy","Dis_RsDataRdy_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_RsDataRdy","Dis_RsDataRdy_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_RtDataRdy","Dis_RtDataRdy_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_RtDataRdy","Dis_RtDataRdy_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_RsPhyAddr","Dis_RsPhyAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_RsPhyAddr","Dis_RsPhyAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_RtPhyAddr","Dis_RtPhyAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_RtPhyAddr","Dis_RtPhyAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_RobTag","Dis_RobTag_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_RobTag","Dis_RobTag_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_Opcode","Dis_Opcode_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_Opcode","Dis_Opcode_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_IntIssquenable","Dis_IntIssquenable_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_IntIssquenable","Dis_IntIssquenable_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_LdIssquenable","Dis_LdIssquenable_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_LdIssquenable","Dis_LdIssquenable_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_DivIssquenable","Dis_DivIssquenable_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_DivIssquenable","Dis_DivIssquenable_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_MulIssquenable","Dis_MulIssquenable_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_MulIssquenable","Dis_MulIssquenable_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_Immediate","Dis_Immediate_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_Immediate","Dis_Immediate_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_BranchOtherAddr","Dis_BranchOtherAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_BranchOtherAddr","Dis_BranchOtherAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_BranchPredict","Dis_BranchPredict_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_BranchPredict","Dis_BranchPredict_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_Branch","Dis_Branch_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_Branch","Dis_Branch_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_BranchPCBits","Dis_BranchPCBits_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_BranchPCBits","Dis_BranchPCBits_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_JrRsInst","Dis_JrRsInst_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_JrRsInst","Dis_JrRsInst_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_JalInst","Dis_JalInst_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_JalInst","Dis_JalInst_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_Jr31Inst","Dis_Jr31Inst_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_Jr31Inst","Dis_Jr31Inst_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_FrlRead","Dis_FrlRead_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_FrlRead","Dis_FrlRead_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_RasJalInst","Dis_RasJalInst_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_RasJalInst","Dis_RasJalInst_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_RasJr31Inst","Dis_RasJr31Inst_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_RasJr31Inst","Dis_RasJr31Inst_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_PcPlusFour","Dis_PcPlusFour_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_PcPlusFour","Dis_PcPlusFour_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_PrevPhyAddr","Dis_PrevPhyAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_PrevPhyAddr","Dis_PrevPhyAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_NewRdPhyAddr","Dis_NewRdPhyAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_NewRdPhyAddr","Dis_NewRdPhyAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_RobRdAddr","Dis_RobRdAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_RobRdAddr","Dis_RobRdAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_InstValid","Dis_InstValid_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_InstValid","Dis_InstValid_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_InstSw","Dis_InstSw_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_InstSw","Dis_InstSw_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_SwRtPhyAddr","Dis_SwRtPhyAddr_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_SwRtPhyAddr","Dis_SwRtPhyAddr_gold",0);
init_signal_spy("/UUT/dispatch_inst/Dis_Instruction","Dis_Instruction_gold",1,1);
enable_signal_spy("/UUT/dispatch_inst/Dis_Instruction","Dis_Instruction_gold",0);
wait;
end process spy_process;
end architecture arch_top_tb_Dispatch;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity fft_core_v6 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
pol0: in std_logic_vector(17 downto 0);
pol1: in std_logic_vector(17 downto 0);
pol2: in std_logic_vector(17 downto 0);
pol3: in std_logic_vector(17 downto 0);
shift: in std_logic_vector(15 downto 0);
sync: in std_logic;
oflow: out std_logic;
pol02_out: out std_logic_vector(35 downto 0);
pol13_out: out std_logic_vector(35 downto 0);
sync_out: out std_logic
);
end fft_core_v6;
architecture structural of fft_core_v6 is
begin
end structural;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:36:49 01/22/2016
-- Design Name:
-- Module Name: /home/aaron/Dokumente/STUDIUM/SEM5/Elektronik3/Digital/Miniprojekt/vhdl-irdecoder/outputswitcher_tb.vhd
-- Project Name: irdecoder
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: outputswitcher
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY outputswitcher_tb IS
END outputswitcher_tb;
ARCHITECTURE behavior OF outputswitcher_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT outputswitcher
PORT(
sel_raw : IN std_logic;
sel_decoded : IN std_logic;
dclk : IN std_logic;
data : IN std_logic_vector(19 downto 0);
seg6_en : OUT std_logic;
seg6 : OUT std_logic_vector(3 downto 0);
seg5_en : OUT std_logic;
seg5 : OUT std_logic_vector(3 downto 0);
seg4_en : OUT std_logic;
seg4 : OUT std_logic_vector(3 downto 0);
seg3_en : OUT std_logic;
seg3 : OUT std_logic_vector(3 downto 0);
seg2_en : OUT std_logic;
seg2 : OUT std_logic_vector(3 downto 0);
seg1_en : OUT std_logic;
seg1 : OUT std_logic_vector(3 downto 0);
dp : OUT std_logic
);
END COMPONENT;
--Inputs
signal sel_raw : std_logic := '0';
signal sel_decoded : std_logic := '0';
signal dclk : std_logic := '0';
signal data : std_logic_vector(19 downto 0) := (others => '0');
--Outputs
signal seg6_en : std_logic;
signal seg6 : std_logic_vector(3 downto 0);
signal seg5_en : std_logic;
signal seg5 : std_logic_vector(3 downto 0);
signal seg4_en : std_logic;
signal seg4 : std_logic_vector(3 downto 0);
signal seg3_en : std_logic;
signal seg3 : std_logic_vector(3 downto 0);
signal seg2_en : std_logic;
signal seg2 : std_logic_vector(3 downto 0);
signal seg1_en : std_logic;
signal seg1 : std_logic_vector(3 downto 0);
signal dp : std_logic;
-- Clock period definitions
constant dclk_period : time := 1000 ms / 81;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: outputswitcher PORT MAP (
sel_raw => sel_raw,
sel_decoded => sel_decoded,
dclk => dclk,
data => data,
seg6_en => seg6_en,
seg6 => seg6,
seg5_en => seg5_en,
seg5 => seg5,
seg4_en => seg4_en,
seg4 => seg4,
seg3_en => seg3_en,
seg3 => seg3,
seg2_en => seg2_en,
seg2 => seg2,
seg1_en => seg1_en,
seg1 => seg1,
dp => dp
);
-- Clock process definitions
dclk_process :process
begin
dclk <= '0';
wait for dclk_period/2;
dclk <= '1';
wait for dclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for dclk_period*10;
data <= "00001001110100011111"; -- apply valid signal (Signal 1)
wait for dclk_period * 10;
-- configuration 1
sel_raw <= '0';
sel_decoded <= '0';
wait for dclk_period * 10;
-- configuration 2
sel_raw <= '1';
sel_decoded <= '0';
wait for dclk_period * 10;
-- configuration 3
sel_raw <= '0';
sel_decoded <= '1';
wait for dclk_period * 10;
-- configuration 4
sel_raw <= '1';
sel_decoded <= '1';
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2138.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02138ent IS
END c07s02b04x00p21n01i02138ent;
ARCHITECTURE c07s02b04x00p21n01i02138arch OF c07s02b04x00p21n01i02138ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_1 is positive_v (1 to 1);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_1;
variable l_operand : positive := 1 ;
variable r_operand : positive_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = 1 )
report "***PASSED TEST: c07s02b04x00p21n01i02138"
severity NOTE;
assert ( result(1) = 1 )
report "***FAILED TEST: c07s02b04x00p21n01i02138 - Concatenation of null and POSITIVE element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02138arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2138.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02138ent IS
END c07s02b04x00p21n01i02138ent;
ARCHITECTURE c07s02b04x00p21n01i02138arch OF c07s02b04x00p21n01i02138ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_1 is positive_v (1 to 1);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_1;
variable l_operand : positive := 1 ;
variable r_operand : positive_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = 1 )
report "***PASSED TEST: c07s02b04x00p21n01i02138"
severity NOTE;
assert ( result(1) = 1 )
report "***FAILED TEST: c07s02b04x00p21n01i02138 - Concatenation of null and POSITIVE element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02138arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2138.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02138ent IS
END c07s02b04x00p21n01i02138ent;
ARCHITECTURE c07s02b04x00p21n01i02138arch OF c07s02b04x00p21n01i02138ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_1 is positive_v (1 to 1);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_1;
variable l_operand : positive := 1 ;
variable r_operand : positive_null;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = 1 )
report "***PASSED TEST: c07s02b04x00p21n01i02138"
severity NOTE;
assert ( result(1) = 1 )
report "***FAILED TEST: c07s02b04x00p21n01i02138 - Concatenation of null and POSITIVE element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02138arch;
|
-- $Id: gray_cnt_4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007--2017 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_4 - syn
-- Description: 4 bit Gray code counter (ROM based)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-07 840 1.1 disable fsm recognition in vivado
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 4 4 365MHz/ 2.76ns
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray_cnt_4 is -- 4 bit gray code counter (ROM based)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE : in slbit := '1'; -- count enable
DATA : out slv4 -- data out
);
end entity gray_cnt_4;
architecture syn of gray_cnt_4 is
signal R_DATA : slv4 := (others=>'0');
signal N_DATA : slv4 := (others=>'0');
-- Note: in xst 8.2.03 fsm_extract="no" is needed. Otherwise an fsm is
-- inferred. For 4 bit the coding was 'Gray', but see remarks in
-- gray_cnt_5. To be save, disallow fsm inferal, enforce reg+rom.
attribute fsm_extract : string;
attribute fsm_extract of R_DATA : signal is "no";
attribute rom_style : string;
attribute rom_style of N_DATA : signal is "distributed";
-- Note: vivado started with -fsm_extraction one_hot didn't fsm recognize
-- this code up to 2016.2. With 2016.3 and later it is converted into a
-- 31 state one-hot fsm, unless explicitely suppressed
attribute fsm_encoding : string;
attribute fsm_encoding of R_DATA : signal is "none";
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_DATA <= (others=>'0');
elsif CE = '1' then
R_DATA <= N_DATA;
end if;
end if;
end process proc_regs;
proc_next: process (R_DATA)
begin
N_DATA <= (others=>'0');
case R_DATA is
when "0000" => N_DATA <= "0001"; -- 0
when "0001" => N_DATA <= "0011"; -- 1
when "0011" => N_DATA <= "0010"; -- 2
when "0010" => N_DATA <= "0110"; -- 3
when "0110" => N_DATA <= "0111"; -- 4
when "0111" => N_DATA <= "0101"; -- 5
when "0101" => N_DATA <= "0100"; -- 6
when "0100" => N_DATA <= "1100"; -- 7
when "1100" => N_DATA <= "1101"; -- 8
when "1101" => N_DATA <= "1111"; -- 9
when "1111" => N_DATA <= "1110"; -- 10
when "1110" => N_DATA <= "1010"; -- 11
when "1010" => N_DATA <= "1011"; -- 12
when "1011" => N_DATA <= "1001"; -- 13
when "1001" => N_DATA <= "1000"; -- 14
when "1000" => N_DATA <= "0000"; -- 15
when others => null;
end case;
end process proc_next;
DATA <= R_DATA;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity extender_32 is
generic (
SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0 extend on 16 bits , when 1 extend on 26 bits
SIGN : in std_logic; -- when 0 unsigned, when 1 signed
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end extender_32;
architecture Bhe of extender_32 is
signal TEMP16 : std_logic_vector(15 downto 0);
signal TEMP26 : std_logic_vector(25 downto 0);
begin
TEMP16 <= IN1(15 downto 0);
TEMP26 <= IN1(25 downto 0);
OUT1 <= std_logic_vector(resize(signed(TEMP26),SIZE)) when CTRL = '1' else
std_logic_vector(resize(signed(TEMP16),SIZE)) when CTRL = '0' and SIGN = '1' else
std_logic_vector(resize(unsigned(TEMP16),SIZE)); -- CTRL = 0 SIGN = 0
end Bhe;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use work.myTypes.all;
entity extender_32 is
generic (
SIZE : integer := 32
);
port (
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic; -- when 0 extend on 16 bits , when 1 extend on 26 bits
SIGN : in std_logic; -- when 0 unsigned, when 1 signed
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end extender_32;
architecture Bhe of extender_32 is
signal TEMP16 : std_logic_vector(15 downto 0);
signal TEMP26 : std_logic_vector(25 downto 0);
begin
TEMP16 <= IN1(15 downto 0);
TEMP26 <= IN1(25 downto 0);
OUT1 <= std_logic_vector(resize(signed(TEMP26),SIZE)) when CTRL = '1' else
std_logic_vector(resize(signed(TEMP16),SIZE)) when CTRL = '0' and SIGN = '1' else
std_logic_vector(resize(unsigned(TEMP16),SIZE)); -- CTRL = 0 SIGN = 0
end Bhe;
|
-------------------------------------------------------------------------------
-- Title : u2p_memtest
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Toplevel with just the alt-mem phy. Testing and experimenting
-- with memory latency.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity u2p_memtest is
port (
-- slot side
SLOT_PHI2 : in std_logic;
SLOT_DOTCLK : in std_logic;
SLOT_RSTn : inout std_logic;
SLOT_BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
SLOT_RWn : inout std_logic;
SLOT_BA : in std_logic;
SLOT_DMAn : out std_logic;
SLOT_EXROMn : inout std_logic;
SLOT_GAMEn : inout std_logic;
SLOT_ROMHn : inout std_logic;
SLOT_ROMLn : inout std_logic;
SLOT_IO1n : inout std_logic;
SLOT_IO2n : inout std_logic;
SLOT_IRQn : inout std_logic;
SLOT_NMIn : inout std_logic;
SLOT_VCC : in std_logic;
-- memory
SDRAM_A : out std_logic_vector(13 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(2 downto 0) := (others => '0');
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : inout std_logic;
SDRAM_CLKn : inout std_logic;
SDRAM_ODT : out std_logic;
SDRAM_DQS : inout std_logic;
AUDIO_MCLK : out std_logic := '0';
AUDIO_BCLK : out std_logic := '0';
AUDIO_LRCLK : out std_logic := '0';
AUDIO_SDO : out std_logic := '0';
AUDIO_SDI : in std_logic;
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
LED_DISKn : out std_logic; -- activity LED
LED_CARTn : out std_logic;
LED_SDACTn : out std_logic;
LED_MOTORn : out std_logic;
-- Ethernet RMII
ETH_RESETn : out std_logic := '1';
ETH_IRQn : in std_logic;
RMII_REFCLK : in std_logic;
RMII_CRS_DV : in std_logic;
RMII_RX_ER : in std_logic;
RMII_RX_DATA : in std_logic_vector(1 downto 0);
RMII_TX_DATA : out std_logic_vector(1 downto 0);
RMII_TX_EN : out std_logic;
MDIO_CLK : out std_logic := '0';
MDIO_DATA : inout std_logic := 'Z';
-- Speaker data
SPEAKER_DATA : out std_logic := '0';
SPEAKER_ENABLE : out std_logic := '0';
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- I2C Interface for RTC, audio codec and usb hub
I2C_SDA : inout std_logic := 'Z';
I2C_SCL : inout std_logic := 'Z';
I2C_SDA_18 : inout std_logic := 'Z';
I2C_SCL_18 : inout std_logic := 'Z';
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
FLASH_SEL : out std_logic := '0';
FLASH_SELCK : out std_logic := '0';
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
HUB_RESETn : out std_logic := '1';
HUB_CLOCK : out std_logic := '0';
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture rtl of u2p_memtest is
component pll
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component memphy
port (
pll_ref_clk : IN STD_LOGIC;
global_reset_n : IN STD_LOGIC;
soft_reset_n : IN STD_LOGIC;
ctl_dqs_burst : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_wdata_valid : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_wdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
ctl_dm : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ctl_addr : IN STD_LOGIC_VECTOR (27 DOWNTO 0);
ctl_ba : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
ctl_cas_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cke : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cs_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_odt : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_ras_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_we_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_rst_n : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_mem_clk_disable : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
ctl_doing_rd : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_cal_req : IN STD_LOGIC;
ctl_cal_byte_lane_sel_n : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dbg_clk : IN STD_LOGIC;
dbg_reset_n : IN STD_LOGIC;
dbg_addr : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
dbg_wr : IN STD_LOGIC;
dbg_rd : IN STD_LOGIC;
dbg_cs : IN STD_LOGIC;
dbg_wr_data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
reset_request_n : OUT STD_LOGIC;
ctl_clk : OUT STD_LOGIC;
ctl_reset_n : OUT STD_LOGIC;
ctl_wlat : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
ctl_rdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
ctl_rdata_valid : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
ctl_rlat : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
ctl_cal_success : OUT STD_LOGIC;
ctl_cal_fail : OUT STD_LOGIC;
ctl_cal_warning : OUT STD_LOGIC;
mem_addr : OUT STD_LOGIC_VECTOR (13 DOWNTO 0);
mem_ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
mem_cas_n : OUT STD_LOGIC;
mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dm : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_ras_n : OUT STD_LOGIC;
mem_we_n : OUT STD_LOGIC;
mem_reset_n : OUT STD_LOGIC;
dbg_rd_data : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
dbg_waitrequest : OUT STD_LOGIC;
aux_half_rate_clk : OUT STD_LOGIC;
aux_full_rate_clk : OUT STD_LOGIC;
mem_clk : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_clk_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dq : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
mem_dqs : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0);
mem_dqs_n : INOUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
end component;
signal por_n : std_logic;
signal por_count : unsigned(23 downto 0) := (others => '0');
signal audio_clock : std_logic;
signal audio_reset : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_reset_n : std_logic;
signal eth_reset : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
signal reset_request_n : std_logic := '1';
signal ctl_dqs_burst : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_wdata_valid : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_wdata : STD_LOGIC_VECTOR (31 DOWNTO 0) := (others => '0');
signal ctl_dm : STD_LOGIC_VECTOR (3 DOWNTO 0) := (others => '0');
signal ctl_addr : STD_LOGIC_VECTOR (27 DOWNTO 0) := (others => '0');
signal ctl_ba : STD_LOGIC_VECTOR (3 DOWNTO 0) := (others => '0');
signal ctl_cas_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_cke : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_cs_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_odt : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_ras_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_we_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_rst_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '1');
signal ctl_mem_clk_disable : STD_LOGIC_VECTOR (0 DOWNTO 0) := (others => '0');
signal ctl_doing_rd : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_wlat : STD_LOGIC_VECTOR (4 DOWNTO 0) := (others => '0');
signal ctl_rdata : STD_LOGIC_VECTOR (31 DOWNTO 0) := (others => '0');
signal ctl_rdata_valid : STD_LOGIC_VECTOR (1 DOWNTO 0) := (others => '0');
signal ctl_rlat : STD_LOGIC_VECTOR (4 DOWNTO 0) := (others => '0');
signal ctl_cal_success : STD_LOGIC := '0';
signal ctl_cal_fail : STD_LOGIC := '0';
signal ctl_cal_warning : STD_LOGIC := '0';
signal count : unsigned(23 downto 0) := (others => '0');
begin
process(RMII_REFCLK, button_i)
begin
if button_i(0) = '1' then
por_count <= (others => '0');
elsif rising_edge(RMII_REFCLK) then
-- if rising_edge(RMII_REFCLK) then
if por_count = X"FFFFFF" then
por_n <= '1';
else
por_n <= '0';
por_count <= por_count + 1;
end if;
end if;
end process;
sys_reset <= not sys_reset_n;
i_pll: pll port map (
inclk0 => RMII_REFCLK, -- 50 MHz
c0 => HUB_CLOCK, -- 24 MHz
c1 => audio_clock, -- 12.245 MHz (47.831 kHz sample rate)
locked => open );
i_audio_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => audio_clock,
input => not sys_reset_n,
input_c => audio_reset );
i_ulpi_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => ulpi_clock,
input => sys_reset,
input_c => ulpi_reset_i );
i_eth_reset: entity work.level_synchronizer
generic map ('1')
port map (
clock => RMII_REFCLK,
input => sys_reset,
input_c => eth_reset );
i_memphy: memphy
port map (
pll_ref_clk => RMII_REFCLK,
global_reset_n => por_n,
soft_reset_n => por_n,
reset_request_n => reset_request_n,
aux_half_rate_clk => open,
aux_full_rate_clk => open,
ctl_clk => sys_clock,
ctl_reset_n => sys_reset_n,
ctl_dqs_burst => ctl_dqs_burst,
ctl_wdata_valid => ctl_wdata_valid,
ctl_wdata => ctl_wdata,
ctl_dm => ctl_dm,
ctl_addr => ctl_addr,
ctl_ba => ctl_ba,
ctl_cas_n => ctl_cas_n,
ctl_cke => ctl_cke,
ctl_cs_n => ctl_cs_n,
ctl_odt => ctl_odt,
ctl_ras_n => ctl_ras_n,
ctl_we_n => ctl_we_n,
ctl_rst_n => ctl_rst_n,
ctl_mem_clk_disable => ctl_mem_clk_disable,
ctl_doing_rd => ctl_doing_rd,
ctl_rdata => ctl_rdata,
ctl_rdata_valid => ctl_rdata_valid,
ctl_cal_req => '0',
ctl_cal_byte_lane_sel_n => "0",
ctl_cal_success => ctl_cal_success,
ctl_cal_fail => ctl_cal_fail,
ctl_cal_warning => ctl_cal_warning,
ctl_wlat => ctl_wlat,
ctl_rlat => ctl_rlat,
dbg_clk => sys_clock,
dbg_reset_n => sys_reset_n,
dbg_addr => (others => '0'),
dbg_wr => '0',
dbg_rd => '0',
dbg_cs => '0',
dbg_wr_data => (others => '0'),
dbg_rd_data => open,
dbg_waitrequest => open,
mem_addr => SDRAM_A,
mem_ba => SDRAM_BA(1 downto 0),
mem_cas_n => SDRAM_CASn,
mem_cke(0) => SDRAM_CKE,
mem_cs_n(0) => SDRAM_CSn,
mem_dm(0) => SDRAM_DM,
mem_odt(0) => SDRAM_ODT,
mem_ras_n => SDRAM_RASn,
mem_we_n => SDRAM_WEn,
mem_reset_n => open,
mem_clk(0) => SDRAM_CLK,
mem_clk_n(0) => SDRAM_CLKn,
mem_dq => SDRAM_DQ,
mem_dqs(0) => SDRAM_DQS,
mem_dqs_n(0) => open
);
MDIO_CLK <= 'Z';
MDIO_DATA <= 'Z';
ETH_RESETn <= '1';
HUB_RESETn <= eth_reset;
SPEAKER_ENABLE <= '0';
SLOT_ADDR <= (others => 'Z');
SLOT_DATA <= (others => 'Z');
-- top
SLOT_DMAn <= 'Z';
SLOT_ROMLn <= 'Z';
SLOT_IO2n <= 'Z';
SLOT_EXROMn <= 'Z';
SLOT_GAMEn <= 'Z';
SLOT_IO1n <= 'Z';
SLOT_RWn <= 'Z';
SLOT_IRQn <= 'Z';
SLOT_NMIn <= 'Z';
SLOT_RSTn <= 'Z';
SLOT_ROMHn <= 'Z';
-- Cassette Interface
CAS_SENSE <= '0';
CAS_READ <= '0';
CAS_WRITE <= '0';
LED_MOTORn <= not ctl_cal_success;
LED_DISKn <= not ctl_cal_fail;
LED_CARTn <= count(count'high); -- not ctl_cal_warning xor button_i(0) xor button_i(1) xor button_i(2);
LED_SDACTn <= sys_reset_n;
process(sys_clock)
begin
if rising_edge(sys_clock) then
count <= count + 1;
end if;
end process;
button_i <= not BUTTON;
SLOT_BUFFER_ENn <= SLOT_BA xor SLOT_DOTCLK xor SLOT_PHI2 xor CAS_MOTOR xor SLOT_VCC; -- we don't connect to a C64
-- Debug UART
UART_TXD <= '1';
-- Flash Interface
FLASH_SEL <= '0';
FLASH_SELCK <= '0';
FLASH_CSn <= '1';
FLASH_SCK <= '1';
FLASH_MOSI <= '1';
-- USB Interface (ULPI)
ULPI_RESET <= por_n;
ULPI_STP <= '0';
ULPI_DATA <= (others => 'Z');
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity AveragingFilter is
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end AveragingFilter;
architecture rtl of AveragingFilter is
component AveragingFilter_process
generic (
LINE_WIDTH_MAX : integer;
CLK_PROC_FREQ : integer;
IN_SIZE : integer;
OUT_SIZE : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : in std_logic;
widthimg_reg_width : in std_logic_vector(15 downto 0);
------------------------- in flow -----------------------
in_data : in std_logic_vector(IN_SIZE-1 downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
------------------------ out flow -----------------------
out_data : out std_logic_vector(OUT_SIZE-1 downto 0);
out_fv : out std_logic;
out_dv : out std_logic
);
end component;
component AveragingFilter_slave
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end component;
signal status_reg_enable_bit : std_logic;
signal widthimg_reg_width : std_logic_vector (15 downto 0);
begin
AveragingFilter_process_inst : AveragingFilter_process
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ,
LINE_WIDTH_MAX => LINE_WIDTH_MAX,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
in_data => in_data,
in_fv => in_fv,
in_dv => in_dv,
out_data => out_data,
out_fv => out_fv,
out_dv => out_dv
);
AveragingFilter_slave_inst : AveragingFilter_slave
generic map (
CLK_PROC_FREQ => CLK_PROC_FREQ
)
port map (
clk_proc => clk_proc,
reset_n => reset_n,
status_reg_enable_bit => status_reg_enable_bit,
widthimg_reg_width => widthimg_reg_width,
addr_rel_i => addr_rel_i,
wr_i => wr_i,
rd_i => rd_i,
datawr_i => datawr_i,
datard_o => datard_o
);
end rtl;
|
-----------------------------------------------------------------------------------
-- Top SPI Speed Calculation (Please check my math - no warranties implied)
-- To determine top speed, look at worst case and count user clocks
-- 1) SPI_CACHE_FULL_FLAG goes high too late for tSU to react
-- 2) CACHE_FULL_FLAG(0) = '1'
-- 3) CACHE_FULL_FLAG(1) = '1'. User Logic sends reset signal.
--
--
-- We can accept up to 7 bits of the full SPI (plus a half clock minus setup
-- time, actually, due to "if (ACK_SPI_BYTE = '1')") based on our code -
-- so 7.5 clocks of SPI cannot be faster than 3 clocks of User Logic. We write
-- the inverse to convert to time, as time is 1/frequency:
--
-- (3/7.5)tUSER < tSPI
--
-- "How much" less is determined by the setup time on the user logic flip flop,
-- so we can constrain it further, and add back the setup time factor:
--
-- (7.5 * tSPI) > (3 * tUSER) + tSU + tSU
-- tSPI > (3*tUSER + 2*tSU)/7.5
--
-- Example: In this firmware version, we're using *roughly* NTSC frequency *5, or
-- 17,896,845.40452 Hz . Divide that by 2 because we internally have two 'cycles',
-- a write and a read, so tUSER = 111.751538 ns.
--
-- tSPI > ((3 * 111.751538) +(3.0 + 3.0))/7.5 = 45.5006 ns
-- For this part combination in NTSC and our code, SPI speed shouldn't exceed
-- 1/45.5006ns or 21.9777 MHz...
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPI_Slave is
Port (
--------------------------------------------------------
-- SPI Declarations --
--------------------------------------------------------
SEL_SPI : in STD_LOGIC;
-- SPI Pins from World
EXT_SCK : in STD_LOGIC;
EXT_SEL : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC;
-- SPI Pins from AVR
AVR_SCK : in STD_LOGIC;
AVR_SEL : in STD_LOGIC;
AVR_MOSI : in STD_LOGIC;
-- AVR_MISO : out STD_LOGIC;
-- One byte FIFO
SPI_DATA_CACHE : out STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- Asynchronous flags for signals to display logic
SPI_CACHE_FULL_FLAG : out STD_LOGIC := '0';
SPI_CMD_RESET_FLAG : out STD_LOGIC := '0';
-- Async Flags returned from user logic
ACK_USER_RESET : in STD_LOGIC;
ACK_SPI_BYTE : in STD_LOGIC
);
end SPI_Slave;
architecture Behavioral of SPI_Slave is
-- Temporary Storage for SPI (Sneaky: cheat by one bit out of 8 to save a flip-flop)
signal SPI_DATA_REG : STD_LOGIC_VECTOR(6 downto 0) := "0000000";
-- Counter for our receiver
signal SCK_COUNTER : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal SCK : STD_LOGIC := '0';
signal SEL : STD_LOGIC := '0';
signal MOSI : STD_LOGIC := '0';
begin
--SEL <= (not SEL_SPI or EXT_SEL) and (SEL_SPI or AVR_SEL); -- Normally High, when SEL_SPI = 0 AVR can drive low.
--SCK <= (not SEL_SPI and AVR_SCK) or (SEL_SPI and EXT_SCK);
--MOSI <= (not SEL_SPI and AVR_MOSI) or (SEL_SPI and EXT_MOSI);
-- Code for SPI receiver
SPI_Logic: process (SEL_SPI, SCK, SEL, ACK_USER_RESET, ACK_SPI_BYTE)
begin
if (SEL_SPI = '1') then
SEL <= AVR_SEL;
SCK <= AVR_SCK;
MOSI <= AVR_MOSI;
else
SEL <= EXT_SEL;
SCK <= EXT_SCK;
MOSI <= EXT_MOSI;
end if;
-- Code to handle 'Mode Reset' in the User Logic
if (ACK_USER_RESET = '1') then -- User Logic acknowledges it was reset
SPI_CMD_RESET_FLAG <= '0';
else -- User doesn't currently acknowledge a reset
if (rising_edge(SEL)) then -- CPLD was just deselected
SPI_CMD_RESET_FLAG <= '1';
end if;
end if;
-- Code to handle our SPI arbitration, reading, and clocking
if (ACK_SPI_BYTE = '1') then -- User Logic acknowledges receiving a byte
-- Lower the Cache Full flag
SPI_CACHE_FULL_FLAG <= '0';
-- If we continue clocking while the user logic is reacting,
-- put it into our data register. This is the logic
-- which limits the top speed of the logic - but usually you'll be
-- hardware limited.
if (rising_edge(SCK)) then
if (SEL = '0') then
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
end if;
else -- NOT currently acknowledging a byte received RISING EDGE
-- Normal, conventional, everyday, typical, average SPI logic begins.
if (rising_edge(SCK)) then
-- Our CPLD is selected
if (SEL = '0') then
-- If we've just received a whole byte...
if (SCK_COUNTER = "111") then
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
-- Put the received byte into the single entry FIFO
SPI_DATA_CACHE <= SPI_DATA_REG(6 downto 0) & MOSI;
-- To: User Logic... "You've got mail."
SPI_CACHE_FULL_FLAG <= '1';
-- We're not full yet so the bits will keep coming
else
SPI_DATA_REG <= SPI_DATA_REG(5 downto 0) & MOSI;
SCK_COUNTER <= STD_LOGIC_VECTOR(unsigned(SCK_COUNTER) + 1);
end if;
-- CPLD is NOT selected
else
-- Reset counter, register
SCK_COUNTER <= "000";
SPI_DATA_REG <= "0000000";
end if; -- End CPLD Selected
end if; -- End Rising SCK edge
end if; -- end Byte Received
end process; -- end SPI
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use std.textio.ALL;
use IEEE.MATH_REAL.ALL;
entity tb_main is
generic ( SEED : natural);
end tb_main;
architecture tb of tb_main is
-- Constant declaration --
constant clock_period : time := 20 ns; -- Please make sure this number is divisible by 2.
-- Signal declaration --
signal clk : STD_LOGIC := '0';
signal seven_segments_done : boolean := true;
signal seven_segments_success : boolean := true;
signal common_done : boolean := true;
signal common_success : boolean := true;
signal uart_success : boolean := true;
signal uart_done : boolean := true;
signal spi_success : boolean := true;
signal spi_done : boolean := true;
signal bus_success : boolean := true;
signal bus_done : boolean := true;
constant run_seven_segments_test : boolean := true;
constant run_common_test : boolean := true;
constant run_uart_test : boolean := true;
constant run_spi_test : boolean := true;
constant run_bus_test : boolean := true;
signal randVal : natural := 0;
begin
seven_segments_generate:
if run_seven_segments_test generate
seven_segments_test : entity work.seven_segments_tb
generic map (
clock_period => clock_period
)
port map (
clk => clk,
done => seven_segments_done,
success => seven_segments_success
);
end generate seven_segments_generate;
common_generate:
if run_common_test generate
common_test : entity work.common_tb
generic map (
clock_period => clock_period
)
port map (
clk => clk,
done => common_done,
success => common_success
);
end generate common_generate;
uart_generate:
if run_uart_test generate
uart_test : entity work.uart_tb
generic map (
clock_period => clock_period,
randVal => randVal
)
port map (
clk => clk,
done => uart_done,
success => uart_success
);
end generate uart_generate;
spi_generate:
if run_spi_test generate
spi_test : entity work.spi_tb
generic map (
clock_period => clock_period,
randVal => randVal
)
port map (
clk => clk,
done => spi_done,
success => spi_success
);
end generate spi_generate;
bus_generate:
if run_bus_test generate
bus_test : entity work.bus_tb
generic map (
clock_period => clock_period,
randVal =>randVal
)
port map (
clk => clk,
done => bus_done,
success => bus_success
);
end generate bus_generate;
rand_gen : process
begin
wait for 20 ns;
randVal <= SEED rem 256;
wait for 20 ns;
report "Seed is " & integer'image(SEED) severity note;
report "randVal is " & integer'image(randVal) severity note;
wait;
end process;
clock_gen : process
begin
if not (common_done and seven_segments_done and uart_done and spi_done and bus_done) then
-- 1/2 duty cycle
clk <= not clk;
wait for clock_period/2;
else
wait;
end if;
end process;
end tb;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ambatest
-- File: ambatest.vhd
-- Author: Alf Vaerneus
-- Description: Test package for emulators
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use grlib.devices.all;
use grlib.stdlib.all;
library std;
use std.textio.all;
package ambatest is
function printhex(value : std_logic_vector; len : integer) return string;
function conv_std_logic_vector(value : string; len : integer) return std_logic_vector;
function trimlen(str : string) return integer;
procedure printf(str : string; timestamp : boolean := false);
procedure printf(str : string; vari : integer; timestamp : boolean := false);
procedure printf(str : string; vari : std_logic_vector; timestamp : boolean := false);
procedure printf(str : string; vari : string; timestamp : boolean := false);
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer);
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer; printlvl : integer; err : out boolean);
type command_type is (RD_SINGLE,
RD_INCR,
RD_WRAP4,
RD_INCR4,
RD_WRAP8,
RD_INCR8,
RD_WRAP16,
RD_INCR16,
WR_SINGLE,
WR_INCR,
WR_WRAP4,
WR_INCR4,
WR_WRAP8,
WR_INCR8,
WR_WRAP16,
WR_INCR16,
M_READ,
M_READ_LINE,
M_READ_MULT,
M_WRITE,
M_WRITE_INV,
C_READ,
C_WRITE,
I_READ,
I_WRITE
);
constant MAX_NO_TB : integer := 20;
type tb_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
start : std_logic;
command : command_type;
no_words : natural;
userfile : boolean;
usewfile : boolean;
rfile : string(18 downto 1);
wfile : string(18 downto 1);
end record;
type tbi_array_type is array(0 to MAX_NO_TB) of tb_in_type;
type status_type is (OK, ERR, TIMEOUT, RETRY);
type tb_out_type is record
data : std_logic_vector(31 downto 0);
ready : std_logic;
status : status_type;
end record;
type tbo_array_type is array(0 to MAX_NO_TB) of tb_out_type;
type ctrl_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
status : status_type;
curword : natural;
no_words : natural;
userfile : boolean;
usewfile : boolean;
rfile : string(18 downto 1);
wfile : string(18 downto 1);
end record;
constant tb_in_init : tb_in_type := (
address => (others => '0'),
data => (others => '0'),
start => '0',
command => RD_SINGLE,
no_words => 0,
userfile => false,
usewfile => false,
rfile => " ",
wfile => " ");
constant ctrl_init : ctrl_type := (
address => (others => '0'),
data => (others => '0'),
status => OK,
curword => 0,
no_words => 1,
userfile => false,
usewfile => false,
rfile => " ",
wfile => " ");
constant AHB_IDLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_IDLE,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant READ_SINGLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant READ_INCR : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_INCR,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant WRITE_SINGLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '1',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant WRITE_INCR : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '1',
hsize => HSIZE_WORD,
hburst => HBURST_INCR,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
-- AHB Master Emulator
component ahbmst_em
generic(
hindex : integer := 0;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
-- AHB Slave Emulator
component ahbslv_em
generic(
hindex : integer := 0;
abits : integer := 10;
waitcycles : integer := 2;
retries : integer := 0;
memaddr : integer := 16#E00#;
memmask : integer := 16#FFF#;
ioaddr : integer := 16#000#;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
end ambatest;
package body ambatest is
function printhex( value : std_logic_vector; len : integer) return string is
variable str1, str2 : string (1 to 8);
variable stmp : string (8 downto 1);
variable x : std_logic_vector(31 downto 0);
begin
x:= (others => '0');
x(len-1 downto 0) := value;
case len is
when 4 | 8 | 12 | 16 | 20 | 24 | 28 | 32 =>
for i in 0 to (len/4)-1 loop
case conv_integer(x(((len-1)-(i*4)) downto ((len-1)-(i*4)-3))) is
when 0 => stmp(i+1) := '0';
when 1 => stmp(i+1) := '1';
when 2 => stmp(i+1) := '2';
when 3 => stmp(i+1) := '3';
when 4 => stmp(i+1) := '4';
when 5 => stmp(i+1) := '5';
when 6 => stmp(i+1) := '6';
when 7 => stmp(i+1) := '7';
when 8 => stmp(i+1) := '8';
when 9 => stmp(i+1) := '9';
when 10 => stmp(i+1) := 'A';
when 11 => stmp(i+1) := 'B';
when 12 => stmp(i+1) := 'C';
when 13 => stmp(i+1) := 'D';
when 14 => stmp(i+1) := 'E';
when 15 => stmp(i+1) := 'F';
when others => stmp(i+1) := 'X';
end case;
end loop;
when others => stmp := (others => ' ');
end case;
str2(1 to 8) := stmp(8 downto 1);
for i in 1 to 8 loop
str1(i) := str2(9-i);
end loop;
return(str1);
end printhex;
function to_char( x : INTEGER range 0 to 15) return character is
begin
case x is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when 10 => return('A');
when 11 => return('B');
when 12 => return('C');
when 13 => return('D');
when 14 => return('E');
when 15 => return('F');
end case;
end to_char;
function conv_std_logic_vector(value : string; len : integer) return std_logic_vector is
variable tmpvect : std_logic_vector(31 downto 0);
variable str1,str2 : string(1 to 8);
begin
str1 := value;
for i in 1 to (len/4) loop
str2(i) := str1(((len/4)+1)-i);
end loop;
case len is
when 4 | 8 | 12 | 16 | 20 | 24 | 28 | 32 =>
for i in 0 to 7 loop
case str2(i+1) is
when '0' => tmpvect(((i*4)+3) downto (i*4)) := "0000";
when '1' => tmpvect(((i*4)+3) downto (i*4)) := "0001";
when '2' => tmpvect(((i*4)+3) downto (i*4)) := "0010";
when '3' => tmpvect(((i*4)+3) downto (i*4)) := "0011";
when '4' => tmpvect(((i*4)+3) downto (i*4)) := "0100";
when '5' => tmpvect(((i*4)+3) downto (i*4)) := "0101";
when '6' => tmpvect(((i*4)+3) downto (i*4)) := "0110";
when '7' => tmpvect(((i*4)+3) downto (i*4)) := "0111";
when '8' => tmpvect(((i*4)+3) downto (i*4)) := "1000";
when '9' => tmpvect(((i*4)+3) downto (i*4)) := "1001";
when 'A' => tmpvect(((i*4)+3) downto (i*4)) := "1010";
when 'B' => tmpvect(((i*4)+3) downto (i*4)) := "1011";
when 'C' => tmpvect(((i*4)+3) downto (i*4)) := "1100";
when 'D' => tmpvect(((i*4)+3) downto (i*4)) := "1101";
when 'E' => tmpvect(((i*4)+3) downto (i*4)) := "1110";
when 'F' => tmpvect(((i*4)+3) downto (i*4)) := "1111";
when 'a' => tmpvect(((i*4)+3) downto (i*4)) := "1010";
when 'b' => tmpvect(((i*4)+3) downto (i*4)) := "1011";
when 'c' => tmpvect(((i*4)+3) downto (i*4)) := "1100";
when 'd' => tmpvect(((i*4)+3) downto (i*4)) := "1101";
when 'e' => tmpvect(((i*4)+3) downto (i*4)) := "1110";
when 'f' => tmpvect(((i*4)+3) downto (i*4)) := "1111";
when others => tmpvect(((i*4)+3) downto (i*4)) := "0000";
end case;
end loop;
when others => tmpvect := (others => '0');
end case;
return(tmpvect(len-1 downto 0));
end conv_std_logic_vector;
procedure printf(str : string; timestamp : boolean := false) is
variable lenstr,offset,i : integer;
variable rstr : string(1 to 128);
variable L : line;
begin
lenstr := str'length; offset := 1; i := 1;
while i <= lenstr loop
rstr(offset) := str(i); offset := offset+1; i := i+1;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure printf(str : string; vari : integer; timestamp : boolean := false) is
variable lenstr,offset,i,j,x,y,z : integer;
variable rstr : string(1 to 128);
variable tmpstr : string(1 to 8);
variable remzer : boolean;
variable L : line;
begin
lenstr := str'length; offset := 1; i := 1; x := vari;
while i <= lenstr loop
if str(i) = '%' then
if vari = 0 then
rstr(offset) := '0'; offset := offset+1;
else
if vari = 0 then tmpstr := (others => '0');
else
j := 8;
l2: while true loop
j := j-1;
exit l2 when j = 0;
y := x/10;
z := x - y*10;
x := y;
tmpstr(j) := to_char(z);
end loop;
if x>0 then printf("Value is out of range"); end if;
end if;
-- tmpstr := printhex(conv_std_logic_vector(vari,32),32);
remzer := false;
for k in 1 to 8 loop
if (tmpstr(k) /= '0' or remzer = true) then
rstr(offset) := tmpstr(k); remzer := true; offset := offset+1;
end if;
end loop;
end if;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure printf(
str : string;
vari : std_logic_vector;
timestamp : boolean := false) is
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
variable lenstr,lenvct,offset,i : integer;
variable rstr : string(1 to 128);
variable tmpstr : string(1 to 8);
variable L : line;
begin
lenstr := str'length; offset := 1;
lenvct := vari'length; i := 1;
while i <= lenstr loop
if str(i) = '%' then
if vari = zero32(lenvct-1 downto 0) then
rstr(offset) := '0'; offset := offset+1;
else
tmpstr := printhex(vari,lenvct);
for j in 1 to 8 loop
rstr(offset) := tmpstr(j); offset := offset+1;
end loop;
end if;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
function trimlen(str : string) return integer is
variable lenstr,i : integer;
begin
lenstr := str'length; i := 1;
while str(lenstr) /= ' ' loop
i := i+1 ; lenstr := lenstr-1;
end loop;
return(lenstr+1);
end function;
procedure printf(
str : string;
vari : string;
timestamp : boolean := false) is
variable lenstr,lenvct,offset,i : integer;
variable rstr : string(1 to 128);
variable L : line;
begin
lenstr := str'length; offset := 1;
lenvct := vari'length; i := 1;
while i <= lenstr loop
if str(i) = '%' then
for j in 1 to lenvct loop
rstr(offset) := vari(j); offset := offset+1;
end loop;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure compfiles(
file1 : string(18 downto 1);
file2 : string(18 downto 1);
format : integer) is
file comp1, comp2 : text;
variable L1, L2 : line;
variable datahex1, datahex2 : string(1 to 8);
variable dataint1, dataint2, pos, errs : integer;
begin
pos := 0; errs := 0;
file_open(comp1, external_name => file1(18 downto trimlen(file1)), open_kind => read_mode);
file_open(comp2, external_name => file2(18 downto trimlen(file2)), open_kind => read_mode);
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
while not (endfile(comp1) or endfile(comp2)) loop
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end loop;
if endfile(comp1) /= endfile(comp2) then
printf("Compared files have different size!"); errs := errs+1;
end if;
file_close(comp1); file_close(comp2);
if errs = 0 then
printf("Comparision complete. No failure.");
elsif errs = 1 then
printf("Comparision complete. 1 failure.");
else
printf("Comparision complete. %d failures.",errs);
end if;
end procedure;
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer; printlvl : integer; err : out boolean) is
file comp1, comp2 : text;
variable L1, L2 : line;
variable datahex1, datahex2 : string(1 to 8);
variable dataint1, dataint2, pos, errs : integer;
begin
pos := 0; errs := 0;
file_open(comp1, external_name => file1(18 downto trimlen(file1)), open_kind => read_mode);
file_open(comp2, external_name => file2(18 downto trimlen(file2)), open_kind => read_mode);
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end if;
while not (endfile(comp1) or endfile(comp2)) loop
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end if;
end loop;
if endfile(comp1) /= endfile(comp2) then
if printlvl /= 0 then
printf("Compared files have different size!"); errs := errs+1;
end if;
end if;
file_close(comp1); file_close(comp2);
err := true;
if errs = 0 then
err := false;
if printlvl >= 2 then
printf("Comparision complete. No failure.");
end if;
elsif errs = 1 then
if printlvl >= 1 then
printf("Comparision complete. 1 failure.");
end if;
else
if printlvl >= 1 then
printf("Comparision complete. %d failures.",errs);
end if;
end if;
end procedure;
end ambatest;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ambatest
-- File: ambatest.vhd
-- Author: Alf Vaerneus
-- Description: Test package for emulators
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use grlib.devices.all;
use grlib.stdlib.all;
library std;
use std.textio.all;
package ambatest is
function printhex(value : std_logic_vector; len : integer) return string;
function conv_std_logic_vector(value : string; len : integer) return std_logic_vector;
function trimlen(str : string) return integer;
procedure printf(str : string; timestamp : boolean := false);
procedure printf(str : string; vari : integer; timestamp : boolean := false);
procedure printf(str : string; vari : std_logic_vector; timestamp : boolean := false);
procedure printf(str : string; vari : string; timestamp : boolean := false);
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer);
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer; printlvl : integer; err : out boolean);
type command_type is (RD_SINGLE,
RD_INCR,
RD_WRAP4,
RD_INCR4,
RD_WRAP8,
RD_INCR8,
RD_WRAP16,
RD_INCR16,
WR_SINGLE,
WR_INCR,
WR_WRAP4,
WR_INCR4,
WR_WRAP8,
WR_INCR8,
WR_WRAP16,
WR_INCR16,
M_READ,
M_READ_LINE,
M_READ_MULT,
M_WRITE,
M_WRITE_INV,
C_READ,
C_WRITE,
I_READ,
I_WRITE
);
constant MAX_NO_TB : integer := 20;
type tb_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
start : std_logic;
command : command_type;
no_words : natural;
userfile : boolean;
usewfile : boolean;
rfile : string(18 downto 1);
wfile : string(18 downto 1);
end record;
type tbi_array_type is array(0 to MAX_NO_TB) of tb_in_type;
type status_type is (OK, ERR, TIMEOUT, RETRY);
type tb_out_type is record
data : std_logic_vector(31 downto 0);
ready : std_logic;
status : status_type;
end record;
type tbo_array_type is array(0 to MAX_NO_TB) of tb_out_type;
type ctrl_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
status : status_type;
curword : natural;
no_words : natural;
userfile : boolean;
usewfile : boolean;
rfile : string(18 downto 1);
wfile : string(18 downto 1);
end record;
constant tb_in_init : tb_in_type := (
address => (others => '0'),
data => (others => '0'),
start => '0',
command => RD_SINGLE,
no_words => 0,
userfile => false,
usewfile => false,
rfile => " ",
wfile => " ");
constant ctrl_init : ctrl_type := (
address => (others => '0'),
data => (others => '0'),
status => OK,
curword => 0,
no_words => 1,
userfile => false,
usewfile => false,
rfile => " ",
wfile => " ");
constant AHB_IDLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_IDLE,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant READ_SINGLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant READ_INCR : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '0',
hsize => HSIZE_WORD,
hburst => HBURST_INCR,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant WRITE_SINGLE : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '1',
hsize => HSIZE_WORD,
hburst => HBURST_SINGLE,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
constant WRITE_INCR : ahb_mst_out_type := (
hbusreq => '0',
hlock => '0',
htrans => HTRANS_NONSEQ,
haddr => (others => '0'),
hwrite => '1',
hsize => HSIZE_WORD,
hburst => HBURST_INCR,
hprot => (others => '0'),
hwdata => (others => '0'),
hirq => (others => '0'),
hconfig => (others => zero32),
hindex => 0
);
-- AHB Master Emulator
component ahbmst_em
generic(
hindex : integer := 0;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
-- AHB Slave Emulator
component ahbslv_em
generic(
hindex : integer := 0;
abits : integer := 10;
waitcycles : integer := 2;
retries : integer := 0;
memaddr : integer := 16#E00#;
memmask : integer := 16#FFF#;
ioaddr : integer := 16#000#;
timeoutc : integer := 100;
dbglevel : integer := 2
);
port(
rst : in std_logic;
clk : in std_logic;
-- AMBA signals
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
-- TB signals
tbi : in tb_in_type;
tbo : out tb_out_type
);
end component;
end ambatest;
package body ambatest is
function printhex( value : std_logic_vector; len : integer) return string is
variable str1, str2 : string (1 to 8);
variable stmp : string (8 downto 1);
variable x : std_logic_vector(31 downto 0);
begin
x:= (others => '0');
x(len-1 downto 0) := value;
case len is
when 4 | 8 | 12 | 16 | 20 | 24 | 28 | 32 =>
for i in 0 to (len/4)-1 loop
case conv_integer(x(((len-1)-(i*4)) downto ((len-1)-(i*4)-3))) is
when 0 => stmp(i+1) := '0';
when 1 => stmp(i+1) := '1';
when 2 => stmp(i+1) := '2';
when 3 => stmp(i+1) := '3';
when 4 => stmp(i+1) := '4';
when 5 => stmp(i+1) := '5';
when 6 => stmp(i+1) := '6';
when 7 => stmp(i+1) := '7';
when 8 => stmp(i+1) := '8';
when 9 => stmp(i+1) := '9';
when 10 => stmp(i+1) := 'A';
when 11 => stmp(i+1) := 'B';
when 12 => stmp(i+1) := 'C';
when 13 => stmp(i+1) := 'D';
when 14 => stmp(i+1) := 'E';
when 15 => stmp(i+1) := 'F';
when others => stmp(i+1) := 'X';
end case;
end loop;
when others => stmp := (others => ' ');
end case;
str2(1 to 8) := stmp(8 downto 1);
for i in 1 to 8 loop
str1(i) := str2(9-i);
end loop;
return(str1);
end printhex;
function to_char( x : INTEGER range 0 to 15) return character is
begin
case x is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when 10 => return('A');
when 11 => return('B');
when 12 => return('C');
when 13 => return('D');
when 14 => return('E');
when 15 => return('F');
end case;
end to_char;
function conv_std_logic_vector(value : string; len : integer) return std_logic_vector is
variable tmpvect : std_logic_vector(31 downto 0);
variable str1,str2 : string(1 to 8);
begin
str1 := value;
for i in 1 to (len/4) loop
str2(i) := str1(((len/4)+1)-i);
end loop;
case len is
when 4 | 8 | 12 | 16 | 20 | 24 | 28 | 32 =>
for i in 0 to 7 loop
case str2(i+1) is
when '0' => tmpvect(((i*4)+3) downto (i*4)) := "0000";
when '1' => tmpvect(((i*4)+3) downto (i*4)) := "0001";
when '2' => tmpvect(((i*4)+3) downto (i*4)) := "0010";
when '3' => tmpvect(((i*4)+3) downto (i*4)) := "0011";
when '4' => tmpvect(((i*4)+3) downto (i*4)) := "0100";
when '5' => tmpvect(((i*4)+3) downto (i*4)) := "0101";
when '6' => tmpvect(((i*4)+3) downto (i*4)) := "0110";
when '7' => tmpvect(((i*4)+3) downto (i*4)) := "0111";
when '8' => tmpvect(((i*4)+3) downto (i*4)) := "1000";
when '9' => tmpvect(((i*4)+3) downto (i*4)) := "1001";
when 'A' => tmpvect(((i*4)+3) downto (i*4)) := "1010";
when 'B' => tmpvect(((i*4)+3) downto (i*4)) := "1011";
when 'C' => tmpvect(((i*4)+3) downto (i*4)) := "1100";
when 'D' => tmpvect(((i*4)+3) downto (i*4)) := "1101";
when 'E' => tmpvect(((i*4)+3) downto (i*4)) := "1110";
when 'F' => tmpvect(((i*4)+3) downto (i*4)) := "1111";
when 'a' => tmpvect(((i*4)+3) downto (i*4)) := "1010";
when 'b' => tmpvect(((i*4)+3) downto (i*4)) := "1011";
when 'c' => tmpvect(((i*4)+3) downto (i*4)) := "1100";
when 'd' => tmpvect(((i*4)+3) downto (i*4)) := "1101";
when 'e' => tmpvect(((i*4)+3) downto (i*4)) := "1110";
when 'f' => tmpvect(((i*4)+3) downto (i*4)) := "1111";
when others => tmpvect(((i*4)+3) downto (i*4)) := "0000";
end case;
end loop;
when others => tmpvect := (others => '0');
end case;
return(tmpvect(len-1 downto 0));
end conv_std_logic_vector;
procedure printf(str : string; timestamp : boolean := false) is
variable lenstr,offset,i : integer;
variable rstr : string(1 to 128);
variable L : line;
begin
lenstr := str'length; offset := 1; i := 1;
while i <= lenstr loop
rstr(offset) := str(i); offset := offset+1; i := i+1;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure printf(str : string; vari : integer; timestamp : boolean := false) is
variable lenstr,offset,i,j,x,y,z : integer;
variable rstr : string(1 to 128);
variable tmpstr : string(1 to 8);
variable remzer : boolean;
variable L : line;
begin
lenstr := str'length; offset := 1; i := 1; x := vari;
while i <= lenstr loop
if str(i) = '%' then
if vari = 0 then
rstr(offset) := '0'; offset := offset+1;
else
if vari = 0 then tmpstr := (others => '0');
else
j := 8;
l2: while true loop
j := j-1;
exit l2 when j = 0;
y := x/10;
z := x - y*10;
x := y;
tmpstr(j) := to_char(z);
end loop;
if x>0 then printf("Value is out of range"); end if;
end if;
-- tmpstr := printhex(conv_std_logic_vector(vari,32),32);
remzer := false;
for k in 1 to 8 loop
if (tmpstr(k) /= '0' or remzer = true) then
rstr(offset) := tmpstr(k); remzer := true; offset := offset+1;
end if;
end loop;
end if;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure printf(
str : string;
vari : std_logic_vector;
timestamp : boolean := false) is
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
variable lenstr,lenvct,offset,i : integer;
variable rstr : string(1 to 128);
variable tmpstr : string(1 to 8);
variable L : line;
begin
lenstr := str'length; offset := 1;
lenvct := vari'length; i := 1;
while i <= lenstr loop
if str(i) = '%' then
if vari = zero32(lenvct-1 downto 0) then
rstr(offset) := '0'; offset := offset+1;
else
tmpstr := printhex(vari,lenvct);
for j in 1 to 8 loop
rstr(offset) := tmpstr(j); offset := offset+1;
end loop;
end if;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
function trimlen(str : string) return integer is
variable lenstr,i : integer;
begin
lenstr := str'length; i := 1;
while str(lenstr) /= ' ' loop
i := i+1 ; lenstr := lenstr-1;
end loop;
return(lenstr+1);
end function;
procedure printf(
str : string;
vari : string;
timestamp : boolean := false) is
variable lenstr,lenvct,offset,i : integer;
variable rstr : string(1 to 128);
variable L : line;
begin
lenstr := str'length; offset := 1;
lenvct := vari'length; i := 1;
while i <= lenstr loop
if str(i) = '%' then
for j in 1 to lenvct loop
rstr(offset) := vari(j); offset := offset+1;
end loop;
i := i+2;
else
rstr(offset) := str(i); offset := offset+1; i := i+1;
end if;
end loop;
rstr(offset+1) := NUL;
if timestamp then
write(L, rstr & " : ");
write(L, Now, Left, 15);
else
write(L,rstr);
end if;
writeline(output,L);
end procedure;
procedure compfiles(
file1 : string(18 downto 1);
file2 : string(18 downto 1);
format : integer) is
file comp1, comp2 : text;
variable L1, L2 : line;
variable datahex1, datahex2 : string(1 to 8);
variable dataint1, dataint2, pos, errs : integer;
begin
pos := 0; errs := 0;
file_open(comp1, external_name => file1(18 downto trimlen(file1)), open_kind => read_mode);
file_open(comp2, external_name => file2(18 downto trimlen(file2)), open_kind => read_mode);
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
while not (endfile(comp1) or endfile(comp2)) loop
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end loop;
if endfile(comp1) /= endfile(comp2) then
printf("Compared files have different size!"); errs := errs+1;
end if;
file_close(comp1); file_close(comp2);
if errs = 0 then
printf("Comparision complete. No failure.");
elsif errs = 1 then
printf("Comparision complete. 1 failure.");
else
printf("Comparision complete. %d failures.",errs);
end if;
end procedure;
procedure compfiles(file1 : string(18 downto 1); file2 : string(18 downto 1); format : integer; printlvl : integer; err : out boolean) is
file comp1, comp2 : text;
variable L1, L2 : line;
variable datahex1, datahex2 : string(1 to 8);
variable dataint1, dataint2, pos, errs : integer;
begin
pos := 0; errs := 0;
file_open(comp1, external_name => file1(18 downto trimlen(file1)), open_kind => read_mode);
file_open(comp2, external_name => file2(18 downto trimlen(file2)), open_kind => read_mode);
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end if;
while not (endfile(comp1) or endfile(comp2)) loop
readline(comp1,L1);
readline(comp2,L2);
pos := pos+1;
if format = 0 then
read(L1,dataint1);
read(L2,dataint2);
if dataint1 /= dataint2 then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %d",dataint1);
printf("Compared data: %d",dataint2);
end if;
end if;
elsif format = 1 then
read(L1,datahex1);
read(L2,datahex2);
if conv_std_logic_vector(datahex1,32) /= conv_std_logic_vector(datahex2,32) then
errs := errs+1;
if printlvl /= 0 then
printf("Comparision error at pos. %d",pos);
printf("Expected data: %x",datahex1);
printf("Compared data: %x",datahex2);
end if;
end if;
end if;
end loop;
if endfile(comp1) /= endfile(comp2) then
if printlvl /= 0 then
printf("Compared files have different size!"); errs := errs+1;
end if;
end if;
file_close(comp1); file_close(comp2);
err := true;
if errs = 0 then
err := false;
if printlvl >= 2 then
printf("Comparision complete. No failure.");
end if;
elsif errs = 1 then
if printlvl >= 1 then
printf("Comparision complete. 1 failure.");
end if;
else
if printlvl >= 1 then
printf("Comparision complete. %d failures.",errs);
end if;
end if;
end procedure;
end ambatest;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkgen_saed32
-- File: clkgen_saed32.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler AB
-- Description: Clock generator for SAED32
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkgen_saed32 is
port (
clkin : in std_logic;
clk : out std_logic; -- main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic); -- unscaled 2X clock
end;
architecture struct of clkgen_saed32 is
component PLL
port (
-- VDD25 : in std_logic;
-- DVDD : inout std_logic;
-- VSSA : in std_logic;
-- AVDD : inout std_logic;
REF_CLK : in std_logic;
FB_CLK : in std_logic;
FB_MODE : in std_logic;
PLL_BYPASS : in std_logic;
CLK_4X : out std_logic;
CLK_2X : out std_logic;
CLK_1X : out std_logic);
end component;
-----------------------------------------------------------------------------
-- attributes
-----------------------------------------------------------------------------
attribute DONT_TOUCH : Boolean;
attribute DONT_TOUCH of pll0 : label is True;
begin
pll0 : PLL port map (
-- VDD25 => '1',
-- DVDD => open,
-- VSSA => '0',
-- AVDD => open,
REF_CLK => clkin,
FB_CLK => cgi.pllref,
FB_MODE => cgi.pllctrl(1),
PLL_BYPASS => cgi.pllctrl(0),
CLK_4X => clk4x,
CLK_2X => clk2x,
CLK_1X => clk
);
cgo.clklock <= '1';
sdclk <= '0';
pciclk <= '0';
cgo.pcilock <= '1';
clk1xu <= '0';
clk2xu <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
--library saed32;
--use saed32.CGLPPSX4_LVT;
-- pragma translate_on
entity clkand_saed32 is
port (
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0');
end clkand_saed32;
architecture rtl of clkand_saed32 is
component CGLPPSX4_LVT
port (
GCLK : out std_ulogic;
CLK : in std_ulogic;
EN : in std_ulogic;
SE : in std_ulogic
);
end component;
attribute DONT_TOUCH : Boolean;
attribute DONT_TOUCH of gate : label is True;
begin
gate: CGLPPSX4_LVT port map (GCLK => o , CLK => i , EN => en, SE => tsten);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
--library saed32;
--use saed32.MUX21X1_LVT;
-- pragma translate_on
entity clkmux_saed32 is
port (
i0 : in std_ulogic;
i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic);
end clkmux_saed32;
architecture rtl of clkmux_saed32 is
component MUX21X1_LVT
port (
Y : out std_ulogic;
A1 : in std_ulogic;
A2 : in std_ulogic;
S0 : in std_ulogic
);
end component;
attribute DONT_TOUCH : Boolean;
attribute DONT_TOUCH of m0 : label is True;
begin
m0: MUX21X1_LVT port map (A1 => i0 , A2 => i1 , S0 => sel, Y => o);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
--library saed32;
--use saed32.INVX4_LVT;
-- pragma translate_on
entity clkinv_saed32 is
port (
i : in std_ulogic;
o : out std_ulogic);
end clkinv_saed32;
architecture rtl of clkinv_saed32 is
component INVX4_LVT
port (
Y : out std_ulogic;
A : in std_ulogic
);
end component;
attribute DONT_TOUCH : Boolean;
attribute DONT_TOUCH of gate : label is True;
begin
gate: INVX4_LVT port map (A => i , Y => o);
end rtl;
|
-- megafunction wizard: %ALTERA_FP_FUNCTIONS v17.0%
-- GENERATION: XML
-- fp_cmp_gt.vhd
-- Generated using ACDS version 17.0 595
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity fp_cmp_gt is
port (
clk : in std_logic := '0'; -- clk.clk
areset : in std_logic := '0'; -- areset.reset
a : in std_logic_vector(31 downto 0) := (others => '0'); -- a.a
b : in std_logic_vector(31 downto 0) := (others => '0'); -- b.b
q : out std_logic_vector(0 downto 0) -- q.q
);
end entity fp_cmp_gt;
architecture rtl of fp_cmp_gt is
component fp_cmp_gt_0002 is
port (
clk : in std_logic := 'X'; -- clk
areset : in std_logic := 'X'; -- reset
a : in std_logic_vector(31 downto 0) := (others => 'X'); -- a
b : in std_logic_vector(31 downto 0) := (others => 'X'); -- b
q : out std_logic_vector(0 downto 0) -- q
);
end component fp_cmp_gt_0002;
begin
fp_cmp_gt_inst : component fp_cmp_gt_0002
port map (
clk => clk, -- clk.clk
areset => areset, -- areset.reset
a => a, -- a.a
b => b, -- b.b
q => q -- q.q
);
end architecture rtl; -- of fp_cmp_gt
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2018 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_fp_functions" version="17.0" >
-- Retrieval info: <generic name="FUNCTION_FAMILY" value="COMPARE" />
-- Retrieval info: <generic name="ARITH_function" value="ADD" />
-- Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
-- Retrieval info: <generic name="ALL_function" value="ADD" />
-- Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
-- Retrieval info: <generic name="TRIG_function" value="SIN" />
-- Retrieval info: <generic name="COMPARE_function" value="GT" />
-- Retrieval info: <generic name="ROOTS_function" value="SQRT" />
-- Retrieval info: <generic name="fp_format" value="single" />
-- Retrieval info: <generic name="fp_exp" value="8" />
-- Retrieval info: <generic name="fp_man" value="23" />
-- Retrieval info: <generic name="exponent_width" value="23" />
-- Retrieval info: <generic name="frequency_target" value="25" />
-- Retrieval info: <generic name="latency_target" value="2" />
-- Retrieval info: <generic name="performance_goal" value="frequency" />
-- Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
-- Retrieval info: <generic name="faithful_rounding" value="false" />
-- Retrieval info: <generic name="gen_enable" value="false" />
-- Retrieval info: <generic name="divide_type" value="0" />
-- Retrieval info: <generic name="select_signal_enable" value="false" />
-- Retrieval info: <generic name="scale_by_pi" value="false" />
-- Retrieval info: <generic name="number_of_inputs" value="2" />
-- Retrieval info: <generic name="trig_no_range_reduction" value="false" />
-- Retrieval info: <generic name="report_resources_to_xml" value="false" />
-- Retrieval info: <generic name="fxpt_width" value="32" />
-- Retrieval info: <generic name="fxpt_fraction" value="0" />
-- Retrieval info: <generic name="fxpt_sign" value="1" />
-- Retrieval info: <generic name="fp_out_format" value="single" />
-- Retrieval info: <generic name="fp_out_exp" value="8" />
-- Retrieval info: <generic name="fp_out_man" value="23" />
-- Retrieval info: <generic name="fp_in_format" value="single" />
-- Retrieval info: <generic name="fp_in_exp" value="8" />
-- Retrieval info: <generic name="fp_in_man" value="23" />
-- Retrieval info: <generic name="enable_hard_fp" value="true" />
-- Retrieval info: <generic name="manual_dsp_planning" value="true" />
-- Retrieval info: <generic name="forceRegisters" value="1111" />
-- Retrieval info: <generic name="selected_device_family" value="MAX 10" />
-- Retrieval info: <generic name="selected_device_speedgrade" value="6" />
-- Retrieval info: </instance>
-- IPFS_FILES : fp_cmp_gt.vho
-- RELATED_FILES: fp_cmp_gt.vhd, dspba_library_package.vhd, dspba_library.vhd, fp_cmp_gt_0002.vhd
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : SRAM model
-------------------------------------------------------------------------------
-- File : sram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple SRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity sram_model_8 is
generic (
g_given_name : string;
g_depth : positive := 18;
g_tAC : time := 50 ns );
port (
A : in std_logic_vector(g_depth-1 downto 0);
DQ : inout std_logic_vector(7 downto 0);
CSn : in std_logic;
OEn : in std_logic;
WEn : in std_logic );
end sram_model_8;
architecture bfm of sram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(sram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(bound, A, CSn, OEn, WEn)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if bound then
if CSn='1' then
DQ <= (others => 'Z') after 5 ns;
else
addr(g_depth-1 downto 0) := A;
if OEn = '0' then
DQ <= read_memory_8(this, addr) after g_tAC;
else
DQ <= (others => 'Z') after 5 ns;
end if;
if WEn'event and WEn='1' then
write_memory_8(this, addr, DQ);
end if;
end if;
end if;
end process;
end bfm;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : SRAM model
-------------------------------------------------------------------------------
-- File : sram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple SRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity sram_model_8 is
generic (
g_given_name : string;
g_depth : positive := 18;
g_tAC : time := 50 ns );
port (
A : in std_logic_vector(g_depth-1 downto 0);
DQ : inout std_logic_vector(7 downto 0);
CSn : in std_logic;
OEn : in std_logic;
WEn : in std_logic );
end sram_model_8;
architecture bfm of sram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(sram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(bound, A, CSn, OEn, WEn)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if bound then
if CSn='1' then
DQ <= (others => 'Z') after 5 ns;
else
addr(g_depth-1 downto 0) := A;
if OEn = '0' then
DQ <= read_memory_8(this, addr) after g_tAC;
else
DQ <= (others => 'Z') after 5 ns;
end if;
if WEn'event and WEn='1' then
write_memory_8(this, addr, DQ);
end if;
end if;
end if;
end process;
end bfm;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : SRAM model
-------------------------------------------------------------------------------
-- File : sram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple SRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity sram_model_8 is
generic (
g_given_name : string;
g_depth : positive := 18;
g_tAC : time := 50 ns );
port (
A : in std_logic_vector(g_depth-1 downto 0);
DQ : inout std_logic_vector(7 downto 0);
CSn : in std_logic;
OEn : in std_logic;
WEn : in std_logic );
end sram_model_8;
architecture bfm of sram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(sram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(bound, A, CSn, OEn, WEn)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if bound then
if CSn='1' then
DQ <= (others => 'Z') after 5 ns;
else
addr(g_depth-1 downto 0) := A;
if OEn = '0' then
DQ <= read_memory_8(this, addr) after g_tAC;
else
DQ <= (others => 'Z') after 5 ns;
end if;
if WEn'event and WEn='1' then
write_memory_8(this, addr, DQ);
end if;
end if;
end if;
end process;
end bfm;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : SRAM model
-------------------------------------------------------------------------------
-- File : sram_model_8.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple SRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity sram_model_8 is
generic (
g_given_name : string;
g_depth : positive := 18;
g_tAC : time := 50 ns );
port (
A : in std_logic_vector(g_depth-1 downto 0);
DQ : inout std_logic_vector(7 downto 0);
CSn : in std_logic;
OEn : in std_logic;
WEn : in std_logic );
end sram_model_8;
architecture bfm of sram_model_8 is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(sram_model_8'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(bound, A, CSn, OEn, WEn)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if bound then
if CSn='1' then
DQ <= (others => 'Z') after 5 ns;
else
addr(g_depth-1 downto 0) := A;
if OEn = '0' then
DQ <= read_memory_8(this, addr) after g_tAC;
else
DQ <= (others => 'Z') after 5 ns;
end if;
if WEn'event and WEn='1' then
write_memory_8(this, addr, DQ);
end if;
end if;
end if;
end process;
end bfm;
|
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